Preparation method for junction-less transistor

Abstract

Provided in the present application is a preparation method for a junction-less transistor. The method comprises: providing a substrate, wherein a buried oxide layer and a semiconductor layer are formed on the substrate; doping the semiconductor layer to obtain a core layer; forming a semiconductor material on the core layer to serve as a shell layer, wherein the doping concentration of the shell layer is less than the doping concentration of the core layer; and forming a source electrode, a drain electrode and a gate electrode on the shell layer. In this way, the core layer can be doped before the shell layer is formed, and when there is a huge concentration gradient between the core layer and the shell layer, accurate doping can be realized, thereby facilitating control over the doping depth and the doping thickness of the core layer in a core-shell structure, reducing negative effects such as impurity diffusion and lattice damage, and thus improving the performance and stability of a device.

Description

A method for fabricating a junctionless transistor

[0001] This application claims priority to Chinese Patent Application No. 2024109321637, filed on July 11, 2024, entitled "A Method for Preparing a Junctionless Transistor", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductors, and in particular to a method for fabricating a junctionless transistor. Background Technology

[0003] A fully depleted silicon-on-insulator (FDSOI) transistor employs a special structure to improve the performance and power consumption of semiconductor devices. It consists of an insulating layer and a thin layer of single-crystal silicon on a substrate. The insulating layer is typically silicon dioxide, known as a buried oxide (BOX) layer, and the thin single-crystal silicon layer is called the top silicon or SOI layer, achieving a top silicon-buried oxide-bottom silicon SOI structure. By thinning the top silicon layer, the depletion layer fills the entire channel region, achieving full depletion, thus realizing the fully depleted silicon-on-insulator structure.

[0004] Junction-less (JL) transistors have attracted considerable attention due to their simple fabrication process and potential in 3D integration requiring low thermal budgets. JL transistors have uniform doping between the source / drain and the channel, thus lacking a junction. They achieve turn-off by depleting carriers in the channel, exhibiting strong suppression of short-channel effects and possessing full CMOS functionality. Furthermore, JL transistors offer advantages such as simple fabrication, multiple threshold adjustment options, and low noise.

[0005] However, JL transistors also have some fundamental weaknesses: low mobility, high contact resistance, and a negative threshold voltage. Therefore, to address these challenges, a core-shell junction-less (CS-JL) transistor is proposed. The core-shell junction-less transistor is a novel junction-less transistor based on FDSOI technology. Compared to traditional junction-less transistors, the core-shell structure uses the heavily doped top silicon layer of a traditional FDSOI wafer as the core layer, and adds an ultrathin lightly doped or undoped shell layer on top to improve device performance. The core layer and the shell layer constitute a core-shell structure.

[0006] The formation of this Core-Shell structure layer requires doping existing SOI wafers to form a Core layer. However, the depth and thickness of the Core layer are difficult to control during the doping process, which can easily lead to a decrease in device performance and stability. Summary of the Invention

[0007] In view of this, the purpose of this application is to provide a method for fabricating junctionless transistors, which enables precise doping and helps to improve device performance and stability.

[0008] This application provides a method for fabricating a junctionless transistor, including:

[0009] A substrate is provided on which a buried oxide layer and a semiconductor layer are formed;

[0010] The semiconductor layer is doped to obtain a core layer;

[0011] A semiconductor material is formed on the core layer as a shell layer, and the doping concentration of the shell layer is less than that of the core layer.

[0012] The source, drain, and gate are formed on the shell.

[0013] Optionally, forming a shell on the core layer includes:

[0014] A shell layer is formed on the core layer using wafer-level bonding, deposition, or epitaxial processes.

[0015] Optionally, the method further includes:

[0016] Provide a sacrificial base;

[0017] An oxygen-buried layer is formed on the sacrificial substrate;

[0018] The substrate is bonded to the buried oxide layer;

[0019] The semiconductor layer is obtained by thinning the sacrificial substrate.

[0020] Optionally, the doping concentration of the core layer is greater than or equal to 10. 19 cm -3 .

[0021] Optionally, the thickness of the core layer ranges from 5 to 10 nm, and the thickness of the shell layer ranges from 5 to 10 nm.

[0022] Optionally, the core layer and the shell layer may be made of different materials, or the core layer and the shell layer may be made of the same material.

[0023] Optionally, the method further includes:

[0024] The diffusion of the source electrode to the shell and the diffusion of the drain electrode to the shell are achieved by thermal annealing.

[0025] Optionally, the method further includes:

[0026] A gate oxide layer is formed between the gate and the shell, and a sidewall is formed on the sidewall of the gate.

[0027] Optionally, the semiconductor layer and the substrate are made of silicon.

[0028] Optionally, forming the source, drain, and gate on the shell includes:

[0029] The source, drain, and gate are formed on the shell through a deposition process.

[0030] This application provides a method for fabricating a junctionless transistor. A substrate is provided, on which a buried oxide layer and a semiconductor layer are formed. The semiconductor layer is doped to obtain a core layer, and a semiconductor material is formed on the core layer as a shell layer. The doping concentration of the shell layer is lower than that of the core layer. A source, drain, and gate are formed on the shell layer. This allows for core layer doping before shell layer formation, enabling precise doping even with a large concentration gradient between the core and shell layers. This facilitates control over the doping depth and thickness of the core layer in the core-shell structure, reduces negative effects such as impurity diffusion and lattice damage, and improves device performance and stability. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 shows a schematic diagram of a channel structure with a junction transistor provided in an embodiment of this application;

[0033] Figure 2 is a schematic diagram of the channel structure of a junctionless transistor provided in an embodiment of this application;

[0034] Figure 3 is a schematic diagram of a Core-Shell structure layer provided in an embodiment of this application;

[0035] Figure 4 is a flowchart of a method for fabricating a junctionless transistor according to an embodiment of this application;

[0036] Figures 5-8 are schematic diagrams of the junctionless transistor in the embodiments of this application during the fabrication process. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0038] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0039] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0040] Referring to Figure 1, which is a schematic diagram of a channel structure for a junction transistor according to an embodiment of this application, a buried oxide layer 110 is located on a substrate 100, and a source 130 and a drain 140 are located on both sides of a channel layer 120. The source 130 and drain 140 of the junction transistor have higher doping concentrations, and have different doping concentrations and doping elements than the channel layer 120. In the manufacturing process of this structure, photolithography using a mask is required, along with etching and implantation processes to achieve different doping in different areas. Specifically, the channel and source / drain patterns are first defined on a silicon wafer using photolithography, and then the patterns are transferred to the silicon wafer using etching technology to form the desired structure. This process requires self-alignment technology, and the use of photolithography leads to higher costs.

[0041] Referring to Figure 2, which is a schematic diagram of the channel structure of a junctionless transistor according to an embodiment of this application, the buried oxide layer 110 is located on the substrate 100, and the channel layer 120 is located on the buried oxide layer 110. The channel of the junctionless transistor is uniformly doped, allowing for direct integral molding, which is convenient and saves on photolithography, while avoiding errors that may be caused by self-alignment. Furthermore, the fabrication of other parts such as the source, drain, and gate in subsequent steps can be compatible with existing self-alignment techniques, thereby reducing the use of photolithography and lowering costs. At the same time, the stability and reliability of the device are also improved.

[0042] Core-Shell junctionless transistors are a novel type of FDSOI junctionless device. Compared to basic junctionless transistor structures, they incorporate a shell structure to enhance performance. This structure uses the heavily doped top silicon layer of a traditional FDSOI wafer as the core layer, and then adds an ultrathin, lightly doped or undoped shell layer on top, thus forming a core-shell structure layer. Referring to Figure 3, which is a schematic diagram of a core-shell structure layer provided in an embodiment of this application, the core-shell structure layer is formed on a buried oxide layer 110 on a substrate 100, including a core layer 150 and a shell layer 160. It comprises an ultrathin structure with a large concentration gradient. Currently, fabricating this structure using doping techniques (such as ion implantation) in the front-end process presents considerable difficulty and instability. Specifically, it is difficult to control the doping depth and the thickness of the doped layer in the front-end process, and side effects such as impurity diffusion and lattice damage are prone to occur, resulting in reduced device performance and stability.

[0043] Based on the above technical problems, this application provides a method for fabricating a junctionless transistor. A substrate is provided, on which a buried oxide layer and a semiconductor layer are formed. The semiconductor layer is doped to obtain a core layer, and a semiconductor material is formed on the core layer as a shell layer. The doping concentration of the shell layer is less than that of the core layer. A source, drain, and gate are formed on the shell layer. This allows for core layer doping before shell layer formation, enabling precise doping even with a large concentration gradient between the core and shell layers. This facilitates control over the doping depth and thickness of the core layer in the core-shell structure, reduces negative effects such as impurity diffusion and lattice damage, and improves device performance and stability.

[0044] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0045] Referring to Figure 4, which is a flowchart of a method for fabricating a junctionless transistor according to an embodiment of this application, and referring to Figures 5-8, which are schematic diagrams of the structure of the junctionless transistor in the fabrication process according to an embodiment of this application, the method may include:

[0046] S101, a substrate 100 is provided, on which a buried oxide layer 110 and a semiconductor layer 201 are formed, as shown in FIG5.

[0047] In this embodiment, the substrate 100 can be a semiconductor substrate, used to provide support for the film layer thereon. For example, it can be a silicon substrate, germanium substrate, etc. The substrate can be circular during manufacturing, for example, it can be a silicon wafer, on which multiple chips can be formed to form an array, enabling the simultaneous batch manufacturing of multiple chips and improving manufacturing efficiency. A buried oxide layer 110 and a semiconductor layer 201 can be formed on the substrate 100, constituting an SOI substrate. The buried oxide layer 110 is an insulating layer used to isolate the semiconductor layer 201 and the substrate 100, preventing carrier leakage from the semiconductor layer 201 from the substrate 100 during device operation. The buried oxide layer 110 can be, for example, silicon oxide, germanium oxide, etc. The semiconductor layer 201, as part of the channel layer, can be made of silicon or germanium, and its thickness can range from 5-10 nm, for example, 5 nm. When the semiconductor layer 201 is made of silicon, the substrate 100, the buried oxide layer 110, and the semiconductor layer 201 constitute an SOI substrate.

[0048] As one possible implementation, the buried oxide layer 110 can be obtained by oxidizing the substrate 100, and the semiconductor layer 201 can be formed on the buried oxide layer 110 by bonding, deposition or epitaxial processes, thereby obtaining a high-quality SOI substrate.

[0049] As another possible implementation, a high-quality SOI substrate can be obtained by forming an SOI substrate using a smart-cut wafer bonding technique. Specifically, referring to Figure 5, a sacrificial substrate (referred to as wafer A) 200 can be provided, and then the following steps are performed: (1) forming a buried oxide layer 110 on the sacrificial substrate 200; (2) bonding a substrate (referred to as wafer B) 100 on the buried oxide layer 110; and (3) thinning the sacrificial substrate (wafer A) 200 to obtain a semiconductor layer 201. In (1), the buried oxide layer 110 is formed on the sacrificial substrate 200 by oxidation and hydrogen ion implantation. The bonding process in (2) is a wafer bonding process, and the thinning process in (3) is a stripping process. The sacrificial substrate 200 is stripped to obtain a semiconductor layer 201 and a stripping layer 202. Then, the wafer is flipped for subsequent operations.

[0050] S102, the semiconductor layer is doped to obtain a core layer, as shown in FIG6.

[0051] After forming the semiconductor layer 201, the wafer obtained by flipping can be referred to Figure 6. Then, the following can be performed: (4) doping the semiconductor layer 201 to obtain the core layer 150. The doping of the semiconductor layer 201 can be heavy doping, and the doping method can be ion implantation. The doping concentration of the core layer 150 is greater than or equal to 10. 19 cm -3 The semiconductor layer 201 can be made of silicon or germanium, etc. For example, both the substrate 100 and the semiconductor layer 201 are made of silicon.

[0052] S103, a semiconductor material is formed on the core layer 150 as a shell layer 160, and the doping concentration of the shell layer 160 is less than the doping concentration of the core layer 150.

[0053] Referring to Figure 7, after doping the semiconductor layer 201 to obtain the core layer 150, the following can be performed: (5) forming a semiconductor material as a shell layer 160 on the core layer 150, wherein the doping concentration of the shell layer 160 is less than that of the core layer 150, and it can be a lightly doped or undoped film layer. The thickness of the shell layer 160 can be in the range of 5-10 nm, for example 5 nm.

[0054] The core layer 150 and the shell layer 160 can be made of the same material, and there is no problem of lattice mismatch between them, which is conducive to obtaining a high-quality shell. The core layer 150 and the shell layer 160 can be made of different materials, which is conducive to realizing a heterogeneous core-shell structure, making the core-shell structure more diverse, which is conducive to meeting diverse needs and facilitating subsequent optimization.

[0055] Optionally, the shell 160 can be formed using wafer-level wafer bonding technology. Another wafer can be bonded to the surface of the core layer 150 and then thinned to obtain the shell 160, thus forming a core-shell structure. However, silicon-silicon bonding strength is lower than silicon-silicon dioxide bonding strength, making bonding more difficult. This method is more suitable when the core layer 150 and shell 160 are made of different materials.

[0056] Optionally, the shell 160 can also be formed using wafer-level epitaxial growth techniques, such as molecular beam epitaxy. This involves using thermal evaporation or a laser beam to epitaxially grow the desired semiconductor material (e.g., silicon) onto the existing core layer 150 to obtain the shell 160. This allows for precise control over the thickness and composition of the shell 160, resulting in a high-purity, high-quality shell 160 (e.g., a single-crystal silicon layer). This method is particularly suitable when the core layer 150 and the shell 160 are made of the same material.

[0057] Optionally, the shell 160 can also be formed by wafer-level deposition processes, such as physical vapor deposition, whereby a semiconductor material gas is deposited on the core layer 150 to obtain a thin film of semiconductor material constituting the shell 160.

[0058] The aforementioned methods can all achieve large-scale integrated fabrication of Core-Shell structures at the wafer level, filling the gap in the fabrication of novel Core-Shell junctionless transistors. By advancing the front-end process to wafer processing, Core-Shell structures can be directly fabricated on a large scale at the wafer level, ensuring the uniformity and consistency of the quality of Core-Shell structures in each device. This eliminates the need for subsequent Core-Shell structure fabrication for individual devices, improving quality and stability while simplifying the fabrication process, reducing fabrication difficulty and cost, and increasing production efficiency. It is expected to achieve large-scale, high-quality production and meet the needs of industrial production.

[0059] S104, a source 130, a drain 140 and a gate 170 are formed on the shell 160, as shown in FIG8.

[0060] After forming the wafer-level core-shell structure, an isolation structure can be formed to separate multiple chips. Source 130, drain 140, and gate 170 are formed on the core-shell structure of each chip to obtain a chip array, as shown in Figure 8. The source 130, drain 140, and gate 170 can be formed through a deposition process, with the source 130 and drain 140 located on either side of the gate 170. The material of the source 130 and drain 140 can be a semiconductor material, such as silicon. The material of the gate 170 can be a metal material, such as aluminum or gold.

[0061] Specifically, the source 130 and drain 140 can be formed first, and then the gate 170 can be formed between the source 130 and drain 140; alternatively, the gate 170 can be formed first, and then the source 130 and drain 140 can be formed on both sides of the gate 170. The source 130, drain 140 and gate 170 are formed through conventional semiconductor manufacturing processes, such as photolithography, etching, and deposition.

[0062] In this embodiment, a gate dielectric layer 171 may also be formed between the gate 170 and the shell 160, and a sidewall (including a first sidewall 172 and a second sidewall 173) located on the sidewall of the gate 170. The first sidewall 172 can separate the gate 170 and the source 130, and the second sidewall 173 can separate the gate 170 and the drain 140.

[0063] In this embodiment, source 130 can be a raised source, and drain 140 can be a raised drain. The source and drain are formed by deposition on a core-shell structure. Source 130 and drain 140 can be doped, such as in-situ doping or ion implantation doping. Source contact 131 can be formed on source 130, and drain contact 141 can be formed on drain 140. Source contact 131 and drain 141 can be metal silicides to reduce contact resistance.

[0064] After the source 130 and drain 140 are formed, thermal annealing can be used to diffuse the source 130 to the core layer 160 and the drain 140 to the shell layer 160, so that the shell layer 160 under the source 130 also contains doped elements and the shell layer 160 under the drain 140 also contains doped elements. The temperature and time of thermal annealing can affect the diffusion effect of the source 130 and drain 140.

[0065] In this embodiment, source-drain self-alignment can be achieved, avoiding errors that may be caused by alignment, reducing multiple photolithography and etching steps, reducing the need for photolithography, lowering the fabrication cost, eliminating the need for source-drain doping, reducing the possibility of introducing additional defects, improving transistor performance, and possessing advantages such as simple fabrication process, low cost, high production efficiency, and excellent transistor performance.

[0066] This application provides a method for fabricating a junctionless transistor. A substrate is provided, on which a buried oxide layer and a semiconductor layer are formed. The semiconductor layer is doped to obtain a core layer, and a semiconductor material is formed on the core layer as a shell layer. The doping concentration of the shell layer is lower than that of the core layer. A source, drain, and gate are formed on the shell layer. This allows for core layer doping before shell layer formation, enabling precise doping even with a large concentration gradient between the core and shell layers. This facilitates control over the doping depth and thickness of the core layer in the core-shell structure, reduces negative effects such as impurity diffusion and lattice damage, and improves device performance and stability.

[0067] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for fabricating a junctionless transistor, characterized in that, include: A substrate is provided on which a buried oxide layer and a semiconductor layer are formed; The semiconductor layer is doped to obtain a core layer; A semiconductor material is formed on the core layer as a shell layer, and the doping concentration of the shell layer is less than that of the core layer. The source, drain, and gate are formed on the shell.

2. The method according to claim 1, characterized in that, The formation of a shell on the core layer includes: A shell layer is formed on the core layer using wafer-level bonding, deposition, or epitaxial processes.

3. The method according to claim 1 or 2, characterized in that, The method further includes: Provide a sacrificial base; An oxygen-buried layer is formed on the sacrificial substrate; The substrate is bonded to the buried oxide layer; The semiconductor layer is obtained by thinning the sacrificial substrate.

4. The method according to any one of claims 1-3, characterized in that, The doping concentration of the core layer is greater than or equal to 10. 19 cm -3 .

5. The method according to any one of claims 1-4, characterized in that, The thickness of the core layer ranges from 5 to 10 nm, and the thickness of the shell layer ranges from 5 to 10 nm.

6. The method according to any one of claims 1-5, characterized in that, The core layer and the shell layer are made of different materials, or the core layer and the shell layer are made of the same materials.

7. The method according to any one of claims 1-6, characterized in that, The method further includes: The diffusion of the source electrode to the shell and the diffusion of the drain electrode to the shell are achieved by thermal annealing.

8. The method according to any one of claims 1-7, characterized in that, The method further includes: A gate oxide layer is formed between the gate and the shell, and a sidewall is formed on the sidewall of the gate.

9. The method according to any one of claims 1-8, characterized in that, The semiconductor layer and the substrate are made of silicon.

10. The method according to any one of claims 1-9, characterized in that, The formation of the source, drain, and gate on the shell includes: The source, drain, and gate are formed on the shell through a deposition process.

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