Semiconductor device and manufacturing method therefor, and electronic apparatus

Abstract

Provided are a semiconductor device and a manufacturing method therefor, and an electronic apparatus. The method comprises: providing a substrate, wherein a first interlayer dielectric layer is formed on the substrate; etching the first interlayer dielectric layer to form a trench; forming a first electrode plate layer on the bottom and side walls of the trench; forming a ferroelectric dielectric layer that covers the first electrode plate layer; and forming a second electrode plate layer that covers the ferroelectric dielectric layer, wherein the second electrode plate layer fills the remaining part of the trench; and the first electrode plate layer, the ferroelectric dielectric layer and the second electrode plate layer constitute a ferroelectric capacitor. The ferroelectric capacitor in the solution of the present invention comprises a capacitive structure in a horizontal direction and a capacitive structure in a vertical direction, such that the capacitor area in the vertical direction can be increased, thereby improving the capacitance and solving the problem of it not being possible to further reduce the area of the ferroelectric capacitor; therefore, the horizontal area of a memory cell structure can be further reduced, thereby improving the integration and performance of the device; moreover, a further reduced memory cell can also be very compatible with copper process technology.

Description

A semiconductor device and its manufacturing method, and an electronic device Cross-references to related applications This application claims to have been filed with the Chinese Patent Office on July 11, 2024, application number 202410935306X, invention. Priority is claimed in Chinese patent application entitled “A semiconductor device and a method for manufacturing the same, and an electronic device thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] Ferroelectric RAM (FRAM) is a new type of memory that combines the non-volatility of read-only memory (ROM) with the non-volatility of random access memory (RAM), and has advantages such as high durability, high-speed read and write speed and low power consumption. It has been widely used in various fields.

[0003] The basic memory cell of ferroelectric memory is a 1T1C (1 Transistor-1 Capacitor) memory cell. A typical 1T1C memory cell includes one transistor and one ferroelectric capacitor. The ferroelectric capacitor generally employs a planar MIM (metal / insulator / metal) structure. Specifically, this MIM structure includes a metal layer as the lower electrode, a ferroelectric thin film material as the dielectric layer, and a metal layer as the upper electrode.

[0004] However, as integrated circuits continue to shrink according to Moore's Law, especially at technology nodes below the 0.13µm standard CMOS (Complementary Metal Oxide Semiconductor) manufacturing process, memory cells encounter the problem of not being able to shrink their structure further, thus preventing further improvements in integration density. This is because reducing the horizontal area of ​​ferroelectric capacitors leads to a decrease in memory cell performance and reading difficulties. Furthermore, ferroelectric capacitors, whose horizontal area cannot be further reduced, are also incompatible with copper-based processes at technology nodes below 0.13µm. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key features and essential technical features of the claimed technical solutions, nor is it intended to determine the scope of protection of the claimed technical solutions.

[0006] To address the existing problems, this disclosure provides a method for manufacturing a semiconductor device, comprising: forming a first interlayer dielectric layer on a substrate; etching the first interlayer dielectric layer to form a trench; forming a first electrode layer at the bottom and sidewalls of the trench; forming a ferroelectric dielectric layer covering the first electrode layer; and forming a second electrode layer covering the ferroelectric dielectric layer, wherein the second electrode layer fills the remaining portion of the trench, such that the first electrode layer, the ferroelectric dielectric layer, and the second electrode layer constitute a ferroelectric capacitor.

[0007] For example, the second electrode layer includes an adhesive layer that covers the ferroelectric dielectric layer, and a metal layer that covers the adhesive layer and fills the remainder of the trench.

[0008] For example, the material of the first electrode layer includes titanium nitride, tantalum nitride, or platinum; the material of the ferroelectric layer includes zirconium-doped hafnium oxide; the material of the adhesion layer includes titanium nitride, tantalum nitride, or platinum; and the metal layer includes copper or tungsten.

[0009] For example, after forming the ferroelectric capacitor, the method further includes: forming a protective layer covering the trench; and performing an annealing process.

[0010] For example, the material of the protective layer includes silicon nitride, silicon oxynitride, or silicon oxide.

[0011] Exemplarily, the method further includes: forming a transistor on the substrate such that the first interlayer dielectric layer covers the transistor; and forming a first conductive plug in the first interlayer dielectric layer to electrically connect the source of the transistor to the first electrode layer.

[0012] For example, after forming a first interlayer dielectric layer on the substrate, the method further includes: forming a first conductive layer in the first interlayer dielectric layer, wherein the first conductive plug is electrically connected to the first electrode layer through the first conductive layer.

[0013] This disclosure also provides a semiconductor device comprising: a substrate; a first interlayer dielectric layer located on the substrate; a trench extending from the surface of the first interlayer dielectric layer into the first interlayer dielectric layer; a first electrode layer covering the bottom and sidewalls of the trench; a ferroelectric dielectric layer covering the first electrode layer; and a second electrode layer covering the ferroelectric dielectric layer and filling the remaining portion of the trench, wherein the first electrode layer, the ferroelectric dielectric layer, and the second electrode layer constitute a ferroelectric capacitor.

[0014] Exemplarily, it also includes a transistor located on the substrate, the first interlayer dielectric layer covering the transistor, and a first conductive plug formed in the first interlayer dielectric layer to electrically connect the source of the transistor to the first plate layer of the ferroelectric capacitor.

[0015] For example, it also includes a first conductive layer located in the first interlayer dielectric layer, and the first conductive plug is electrically connected to the first electrode layer of the ferroelectric capacitor through the first conductive layer.

[0016] For example, the second electrode layer includes: an adhesive layer covering the ferroelectric dielectric layer, and a metal layer covering the adhesive layer and filling the remainder of the trench.

[0017] For example, the material of the first electrode layer includes titanium nitride, tantalum nitride, or platinum; the material of the ferroelectric layer includes zirconium-doped hafnium oxide; the material of the adhesion layer includes titanium nitride, tantalum nitride, or platinum; and the metal layer includes copper or tungsten.

[0018] For example, the semiconductor device further includes a protective layer that covers the trench.

[0019] For example, the material of the protective layer includes silicon nitride, silicon oxynitride, or silicon oxide.

[0020] In another aspect, this disclosure provides an electronic device comprising the aforementioned semiconductor device.

[0021] According to embodiments of the semiconductor device and its manufacturing method, and electronic apparatus, the ferroelectric capacitor in the semiconductor device includes a horizontal capacitor structure and a vertical capacitor structure. This allows for an increase in the capacitor area in the vertical direction, maintaining capacitance even when the horizontal area of ​​the ferroelectric capacitor is reduced, thereby enabling a further reduction in the horizontal area of ​​the memory cell structure containing the ferroelectric capacitor. This not only effectively improves the integration and performance of the semiconductor device but also ensures good compatibility with copper process technology. Attached Figure Description

[0022] The following drawings, which are incorporated herein by reference as part of this disclosure, are provided for understanding the disclosure. The drawings illustrate embodiments of the disclosure and their descriptions, serving to explain the principles of the disclosure.

[0023] Figure 1 shows a flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of the present disclosure.

[0024] Figures 2A-2G show cross-sectional schematic diagrams of the semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present disclosure.

[0025] Figures 3A-3D show cross-sectional schematic diagrams of the semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present disclosure.

[0026] Figure 4 shows a circuit netlist diagram of a 1T1C unit structure according to a specific embodiment of the present disclosure.

[0027] Figure 5 shows an array layout of a 1T1C cell structure according to a specific embodiment of the present disclosure. Detailed Implementation

[0028] The present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. However, the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the disclosure to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0030] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] Embodiments of this disclosure are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of this disclosure.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is made. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as interpreted in an ideal or overly formal sense, unless expressly defined herein.

[0034] To fully understand this disclosure, detailed steps and structures will be set forth in the following description to illustrate the technical solutions presented herein. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0035] In related technologies, as integrated circuits continue to shrink according to Moore's Law, especially at technology nodes below the 0.13µm standard CMOS manufacturing process, if ferroelectric capacitors shrink accordingly, their capacitance will be too low due to their small horizontal area, resulting in a significant reduction in the amount of charge they can store. This not only leads to a decrease in the performance of memory cells but also causes reading difficulties due to insufficient current generated in the circuit. Therefore, in related technologies, ferroelectric capacitors need to maintain a large capacitance structure, which limits the further miniaturization of the corresponding memory cell structure. For example, the horizontal area of ​​the memory cell structure cannot be less than 0.5µm², thus preventing further improvements in integration density.

[0036] Furthermore, in current technology nodes below 0.13µm, the back-end of CMOS manufacturing processes generally employs copper processes, such as the dual damascene process. However, current larger memory cell structures typically use aluminum processes, which are not compatible with copper processes.

[0037] Therefore, in view of the aforementioned technical problems, this disclosure proposes a method for manufacturing a semiconductor device, as shown in FIG1, which mainly includes the following steps S1 to S5.

[0038] Step S1: Provide a substrate on which a first interlayer dielectric layer is formed.

[0039] Step S2: Etch the first interlayer dielectric layer to form a trench.

[0040] Step S3: A first electrode layer is formed at the bottom and sidewalls of the trench.

[0041] Step S4: Form a ferroelectric dielectric layer covering the first electrode layer.

[0042] Step S5: A second electrode layer is formed to cover the ferroelectric dielectric layer. The second electrode layer fills the remaining portion of the trench. The first electrode layer, the ferroelectric dielectric layer, and the second electrode layer constitute a ferroelectric capacitor.

[0043] According to the semiconductor device manufacturing method disclosed herein, the ferroelectric capacitor in the manufactured semiconductor device includes a horizontal capacitor structure and a vertical capacitor structure. The vertical capacitor area can be increased, allowing the ferroelectric capacitor to maintain a certain capacitance even when the horizontal area is reduced. This further reduces the horizontal area of ​​the memory cell structure containing the ferroelectric capacitor, effectively improving the integration and performance of the semiconductor device and ensuring good compatibility with copper fabrication processes.

[0044] Example 1

[0045] The method for manufacturing a semiconductor device according to the present disclosure will now be described in detail with reference to Figures 1, 2A to 2G, and 3A to 3D. Figure 1 shows a flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of the present disclosure; Figures 2A-2G show cross-sectional schematic diagrams of devices obtained by sequentially implementing the method for manufacturing a semiconductor device according to a specific embodiment of the present disclosure; and Figures 3A-3D show cross-sectional schematic diagrams of devices obtained by sequentially implementing the method for manufacturing a semiconductor device according to another specific embodiment of the present disclosure.

[0046] For example, the method for manufacturing a semiconductor device disclosed herein includes the following steps.

[0047] First, step S1 is performed, providing a substrate on which a first interlayer dielectric layer is formed.

[0048] The semiconductor device can be any suitable type of device known to those skilled in the art. In this embodiment, the technical solution of this disclosure is explained and illustrated mainly by taking the case of the semiconductor device being a ferroelectric memory as an example.

[0049] Specifically, as shown in Figures 2A to 2C, the substrate 200 is a bulk silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. According to an example of this disclosure, the substrate 200 may also include a multilayer structure made of these semiconductor materials, or be silicon on insulator (SOI), strained silicon on insulator (SSOI), strained silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), etc.

[0050] In one example, as shown in FIG2C, a first interlayer dielectric layer 205 is formed on substrate 200. Exemplarily, various deposition methods commonly used in the art can be employed to form the first interlayer dielectric layer 205. For example, the first interlayer dielectric layer 205 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc.

[0051] For example, the material of the first interlayer dielectric layer 205 can be insulating materials such as silicon dioxide, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride, and this application does not impose any restrictions on this.

[0052] Exemplarily, after forming the first interlayer dielectric layer 205, the method further includes: planarizing the first interlayer dielectric layer 205. Non-limiting examples of this planarization method include mechanical planarization and chemical mechanical polishing planarization. Exemplarily, the first interlayer dielectric layer 205 can be deposited in multiple stages, and the specific steps will be described in detail below.

[0053] Next, step S2 is performed to etch the first interlayer dielectric layer to form a trench. Specifically, as shown in FIG2D, various etching processes conventional in the art can be used to etch the first interlayer dielectric layer 205 to a certain depth to form the trench 212.

[0054] Next, step S3 is performed to form a first electrode layer 213 on the bottom and sidewalls of the trench 212. Specifically, as shown in FIG2E, various deposition methods commonly used in the art can be used to form the first electrode layer 213. For example, the first electrode layer 213 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). This first electrode layer 213 serves as the lower electrode of the finally formed ferroelectric capacitor.

[0055] For example, the material of the first electrode layer 213 may include titanium nitride, tantalum nitride, or platinum, or may be any other suitable material.

[0056] For example, the thickness of the first electrode layer 213 can be 250 angstroms or any other suitable thickness.

[0057] Next, step S4 is performed to form a ferroelectric dielectric layer covering the first electrode layer. Specifically, as shown in FIG2E, various deposition methods commonly used in the art can be used to form the ferroelectric dielectric layer 214. For example, the ferroelectric dielectric layer 214 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In this embodiment, atomic layer deposition is used to form the ferroelectric dielectric layer 214.

[0058] For example, the ferroelectric layer 214 is made of zirconium-doped hafnium oxide. The doping ratio of zirconium, hafnium, and oxygen is approximately 0.5 / 0.5 / 2. Zirconium-doped hafnium oxide (HZO, Hf) 1-x Zr x Hafnium oxide (HfO) is an extension of hafnium oxide (HfO)-based ferroelectric materials and is a novel type of ferroelectric material. Compared to traditional ferroelectric materials, the components of HfO... 1-x Zr x Hafnium dioxide (HfO2) and zirconium dioxide (ZrO2) have been used as gate oxides in MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and dielectric layers in DRAMs (Dynamic Random Access Memory). Therefore, HZO ferroelectric materials are well-compatible with CMOS (Complementary Metal-Oxide-Semiconductor) processes and exhibit strong ferroelectricity even at ultra-thin thicknesses of around 10 nm, demonstrating excellent scalability.

[0059] For example, the thickness of the ferroelectric dielectric layer 214 can be 5nm-15nm or any other suitable thickness range.

[0060] Finally, step S5 is performed to form a second electrode layer covering the ferroelectric dielectric layer. The second electrode layer fills the remaining portion of the trench. The first electrode layer, the ferroelectric dielectric layer, and the second electrode layer constitute a ferroelectric capacitor.

[0061] Specifically, as shown in Figure 2E, the second electrode layer 215 can be formed using various deposition methods commonly used in the art. For example, the second electrode layer 215 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the second electrode layer 215 serves as the upper electrode of the ferroelectric capacitor, together with the ferroelectric dielectric layer 214 and the first electrode layer 213, constituting the ferroelectric capacitor. Exemplarily, the vertical length (also referred to as the height of the ferroelectric capacitor) can be controlled by controlling the depth of the formed trench 212.

[0062] In one example, as shown in FIG2E, the second electrode layer 215 includes an adhesive layer 2151 and a metal layer 2152. The adhesive layer 2151 covers the ferroelectric layer 214, and the metal layer 2152 covers the adhesive layer 2151 and fills the remainder of the trench 212.

[0063] For example, the material of the adhesive layer 2151 includes titanium nitride, tantalum nitride, or platinum, or may be any other suitable material; the material of the metal layer 2152 includes copper or tungsten, or may be any other suitable material.

[0064] In one example, as shown in Figure 2E, the ferroelectric capacitor composed of a first electrode layer 213, a ferroelectric dielectric layer 214, and a second electrode layer 215 includes a horizontal capacitor structure and a vertical capacitor structure. Compared to ferroelectric capacitors in related technologies that only include a horizontal capacitor structure, the ferroelectric capacitor of this application, due to the inclusion of a vertical capacitor structure, can increase the area of ​​the ferroelectric capacitor in the vertical direction, thereby achieving a higher capacitance. Thus, when the horizontal area of ​​the ferroelectric capacitor decreases, the capacitance of the vertical capacitor structure can compensate for the reduced capacitance of the horizontal capacitor structure, maintaining the capacitance of the ferroelectric capacitor at a level that is not too low. Correspondingly, the horizontal area of ​​the memory cell structure containing the ferroelectric capacitor can also be further reduced, effectively improving the device's integration and performance, and also ensuring good compatibility with copper process technology.

[0065] In one example, as shown in Figures 2A to 2E, a transistor is also formed on the substrate 200, a first interlayer dielectric layer 205 covers the transistor, and a first conductive plug 206 is formed in the first interlayer dielectric layer 205 to electrically connect the source 202 of the transistor and the first electrode layer 213 of the ferroelectric capacitor. Exemplarily, as shown in Figure 2A, a shallow trench isolation structure 204 is also formed in the substrate 200.

[0066] Specifically, as shown in Figures 2A to 2E, the transistor includes a gate structure 201, a source 202, and a drain 203. The gate structure 201 includes a polysilicon gate layer and a gate dielectric layer, with the gate dielectric layer providing isolation and protection. Exemplarily, the gate structure 201 may further include sidewalls located on both sides of the polysilicon gate layer.

[0067] In one example, as shown in Figures 2A to 2C, a second conductive plug 207, a third conductive plug 208, a second conductive layer 210, and a third conductive layer 211 are also formed in the first interlayer dielectric layer. The second conductive layer 210 is electrically connected to the drain 203 of the transistor via the second conductive plug 207.

[0068] For example, the specific formation steps of the first interlayer dielectric layer 205, the first conductive plug 206, the second conductive plug 207, the third conductive plug 208, the second conductive layer 210 and the third conductive layer 211 will be described below with reference to Figures 2A to 2C.

[0069] First, as shown in Figure 2A, a first interlayer dielectric layer 205 of a preliminary depth is deposited, and a first conductive plug 206, a second conductive plug 207, and a third conductive plug 208 are formed in this portion of the interlayer dielectric layer 205. The first conductive plug 206, the second conductive plug 207, and the third conductive plug 208 can be formed simultaneously or sequentially.

[0070] Next, as shown in Figure 2B, a first interlayer dielectric layer 205 of a certain depth is deposited, for example, a first interlayer dielectric layer 205 with a thickness of 300 angstroms to 8000 angstroms, and a second conductive layer 210 and a third conductive layer 211 are formed. The second conductive layer 210 and the third conductive layer 211 can be formed using a single damask process for copper fabrication. After forming the second conductive layer 210 and the third conductive layer 211, a planarization process is also performed on the second conductive layer 210 and the third conductive layer 211.

[0071] Finally, the first interlayer dielectric layer 205 is deposited to a certain depth, for example, a first interlayer dielectric layer 205 with a thickness of 300 angstroms to 8000 angstroms, to obtain the first interlayer dielectric layer 205 as shown in FIG2C.

[0072] In one example, as shown in FIG2F, after forming the ferroelectric capacitor, the method of the present disclosure further includes: forming a protective layer 216 covering the trench 212; and performing an annealing process to activate the ferroelectric properties of the ferroelectric dielectric layer 214 in the ferroelectric capacitor.

[0073] For example, the protective layer 216 covers the ferroelectric capacitor in the trench 212, thereby protecting the ferroelectric capacitor. The protective layer 216 may also cover at least a portion of the surface of the first interlayer dielectric layer 205.

[0074] For example, the material of the protective layer 216 may include silicon nitride, silicon oxynitride, or silicon oxide, or may be any other suitable material.

[0075] For example, high-temperature annealing can be used for the annealing process, with an annealing temperature of 450 degrees Celsius to 750 degrees Celsius.

[0076] In one example, as shown in Figure 2G, after forming the protective layer 216, the method of this application further includes forming a first conductive via 217, a fourth conductive layer 218, a second conductive via 219, a fifth conductive layer 220, a third conductive via 221, a sixth conductive layer 222, and a second interlayer dielectric layer 223. The first conductive via 217 is electrically connected to the third conductive layer 211 and the fourth conductive layer 218, the second conductive via 219 is electrically connected to the fifth conductive layer 220 and the second electrode layer 215 of the ferroelectric capacitor, and the third conductive via 221 is electrically connected to the fourth conductive layer 218 and the sixth conductive layer 222. This step is a back-end step in a conventional CMOS manufacturing process and will not be described in detail here.

[0077] For example, a double damask process using copper can be used to form the first conductive via 217 and the fourth conductive layer 218, the second conductive via 219 and the fifth conductive layer 220, and the third conductive via 221 and the sixth conductive layer 222.

[0078] For example, the second interlayer dielectric layer 223 can be formed using various deposition methods commonly used in the art. For instance, the second interlayer dielectric layer 223 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0079] For example, the material of the second interlayer dielectric layer 223 can be an insulating material such as silicon dioxide, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride, and this application does not impose any restrictions on this.

[0080] As described above, the ferroelectric capacitor according to the embodiments of this application includes a horizontal capacitor structure and a vertical capacitor structure, which allows the horizontal area of ​​the memory cell structure in which the ferroelectric capacitor is located to be further reduced, thereby making it well compatible with the copper process technology of conventional CMOS back-end (e.g., it can be compatible with copper process technology nodes below 0.13um).

[0081] In another embodiment of this application, as shown in Figures 3A to 3D, a first conductive layer 209 formed in the first interlayer dielectric layer 205 may be included, and the first conductive plug 206 is electrically connected to the first electrode layer 213 of the ferroelectric capacitor through the first conductive layer 209.

[0082] For example, as shown in FIG3A, the first conductive layer 209 can be formed simultaneously with the second conductive layer 210 and the third conductive layer 211.

[0083] As exemplarily shown in Figures 3B to 3D, the subsequent steps are consistent with the embodiments described above with reference to Figures 2D to 2G, and will not be repeated here.

[0084] For example, a single damask process using copper can be used to form the first conductive layer 209.

[0085] As shown in Figure 3D, due to the formation of the first conductive layer 209, the source of the transistor and the first plate layer 213 of the ferroelectric capacitor can be electrically connected through the first conductive layer 209 and the first conductive plug 206. Compared to Figure 2G, the ferroelectric capacitor and the transistor are farther apart in the vertical direction, resulting in a smaller parasitic capacitance between them and thus higher overall device reliability. Of course, those skilled in the art should understand that this will reduce the vertical length of the ferroelectric capacitor to some extent, and correspondingly reduce the capacitance of the vertical capacitor structure. However, the greater vertical distance between the ferroelectric capacitor and the transistor also leads to a larger interconnect resistance. In summary, whether to choose to directly connect the source of the transistor in the semiconductor device and the first plate layer 213 of the ferroelectric capacitor through the first conductive plug 206 as shown in Figure 2G, or to choose to form a first conductive layer 209 as shown in Figure 3D so that the source of the transistor and the first plate layer 213 of the ferroelectric capacitor are electrically connected through the first conductive layer 209 and the first conductive plug 206, those skilled in the art can freely choose according to actual application requirements, based on comprehensive considerations such as the capacitance of the ferroelectric capacitor, the interconnection resistance between the ferroelectric capacitor and the transistor, and the parasitic capacitance between the ferroelectric capacitor and the transistor. This application does not impose any restrictions on this.

[0086] In one example, a transistor and a ferroelectric capacitor can jointly form a 1T1C (1 Transistor-1 Capacitor) cell structure. In this structure, the polysilicon gate layer in the transistor's gate structure 201 serves as the word line (WL), the second conductive layer 210 serves as the bit line (BL), and the fifth conductive layer 220 serves as the plate line (PL). The circuit netlist and array layout of this 1T1C cell structure are shown in Figures 4 and 5, respectively. Exemplarily, by controlling WL to select the ferroelectric capacitor, and by controlling BL and PL to apply forward and reverse voltages to the ferroelectric capacitor respectively, the ferroelectric dielectric layer 214 in the middle of the ferroelectric capacitor forms different iron domains (polarizations) under the forward and reverse electric fields. These iron domains do not disappear when the external electric field is removed, thus enabling the ferroelectric capacitor to store different charges and achieve a storage function.

[0087] This concludes the description of the key steps in the manufacturing method of the semiconductor device disclosed herein. Other steps may also be included in the preparation of a complete semiconductor device, which will not be elaborated here.

[0088] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0089] In summary, according to the semiconductor device manufacturing method disclosed herein, the ferroelectric capacitor in the manufactured semiconductor device includes a horizontal capacitor structure and a vertical capacitor structure. It can increase the capacitor area in the vertical direction, so that the capacitance can be maintained even when the horizontal area of ​​the ferroelectric capacitor is reduced. This allows the area of ​​the memory cell structure where the ferroelectric capacitor is located to be further reduced, effectively improving the integration and performance of the device, and also being well compatible with copper process technology.

[0090] Example 2

[0091] This disclosure also provides a semiconductor device prepared by the method described in the first embodiment. Specifically, as shown in Figures 2G and 3D, the semiconductor device includes: a substrate 200; a first interlayer dielectric layer 205 located on the substrate 200; a trench 212 extending from the surface of the first interlayer dielectric layer 205 into the first interlayer dielectric layer 205; a first electrode layer 213 covering the bottom and sidewalls of the trench 212; a ferroelectric dielectric layer 214 covering the first electrode layer 213; and a second electrode layer 215 covering the ferroelectric dielectric layer 214 and filling the remaining portion of the trench 212. The first electrode layer 213, the ferroelectric dielectric layer 214, and the second electrode layer 215 constitute a ferroelectric capacitor.

[0092] In one example, as shown in Figures 2G and 3D, the ferroelectric capacitor composed of the first electrode layer 213, the ferroelectric dielectric layer 214, and the second electrode layer 215 includes both horizontal and vertical capacitor structures. Compared to a capacitor structure that only includes a horizontal one, increasing the area of ​​the ferroelectric capacitor in the vertical direction allows it to have a higher capacitance. Thus, even when the horizontal area of ​​the ferroelectric capacitor decreases, the capacitance of the vertical capacitor structure can compensate for the reduced capacitance of the horizontal capacitor structure, thereby maintaining the capacitance of the ferroelectric capacitor at a level that is not too low. This allows for a further reduction in the horizontal area of ​​the memory cell structure containing the ferroelectric capacitor. This effectively improves the integration and performance of the semiconductor device and is also well-compatible with copper process technology.

[0093] In one example, as shown in Figures 2G and 3D, the semiconductor device further includes a transistor located on a substrate 200. A first interlayer dielectric layer 205 covers the transistor, and a first conductive plug 206 is formed in the first interlayer dielectric layer 205 to electrically connect the source 202 of the transistor and the first electrode layer 213 of the ferroelectric capacitor. Exemplarily, as shown in Figure 2A, a shallow trench isolation structure 204 is also formed in the substrate 200.

[0094] Specifically, as shown in Figures 2G and 3D, the transistor includes a gate structure 201, a source 202, and a drain 203. The gate structure 201 includes a polysilicon gate layer and a gate dielectric layer, with the gate dielectric layer providing isolation and protection. Exemplarily, the gate structure 201 may further include sidewalls located on both sides of the polysilicon gate layer.

[0095] In one example, as shown in FIG3D, a first conductive layer 209 located in the first interlayer dielectric layer 205 is also included, and the first conductive plug 206 is electrically connected to the first electrode layer 213 of the ferroelectric capacitor through the first conductive layer 209.

[0096] As shown in Figure 3D, due to the formation of the first conductive layer 209, the source of the transistor and the first plate layer 213 of the ferroelectric capacitor can be electrically connected through the first conductive layer 209 and the first conductive plug 206. Compared to Figure 2G, the ferroelectric capacitor and the transistor are farther apart in the vertical direction, resulting in a smaller parasitic capacitance between them and thus higher overall device reliability. Of course, those skilled in the art should understand that this will reduce the vertical length of the ferroelectric capacitor to some extent, and correspondingly reduce the capacitance of the vertical capacitor structure. However, the greater vertical distance between the ferroelectric capacitor and the transistor also leads to a larger interconnect resistance. In summary, whether to choose to directly connect the source of the transistor in the semiconductor device and the first plate layer 213 of the ferroelectric capacitor through the first conductive plug 206 as shown in Figure 2G, or to choose to form a first conductive layer 209 as shown in Figure 3D so that the source of the transistor and the first plate layer 213 of the ferroelectric capacitor are electrically connected through the first conductive layer 209 and the first conductive plug 206, those skilled in the art can freely choose according to actual application requirements, based on comprehensive considerations such as the capacitance of the ferroelectric capacitor, the interconnection resistance between the ferroelectric capacitor and the transistor, and the parasitic capacitance between the ferroelectric capacitor and the transistor. This application does not impose any restrictions on this.

[0097] In one example, as shown in Figures 2G and 3D, a second conductive plug 207, a third conductive plug 208, a second conductive layer 210, and a third conductive layer 211 are also formed in the first interlayer dielectric layer 205. The second conductive layer 210 is electrically connected to the drain 203 of the transistor via the second conductive plug 207.

[0098] In one example, as shown in Figures 2G and 3D, the system further includes a first conductive via 217, a fourth conductive layer 218, a second conductive via 219, a fifth conductive layer 220, a third conductive via 221, a sixth conductive layer 222, and a second interlayer dielectric layer 223. Specifically, the first conductive via 217 is electrically connected to the third conductive layer 211 and the fourth conductive layer 218, the second conductive via 219 is electrically connected to the fifth conductive layer 220 and the second electrode layer 215 of the ferroelectric capacitor, and the third conductive via 221 is electrically connected to the fourth conductive layer 218 and the sixth conductive layer 222.

[0099] In one example, a transistor and a ferroelectric capacitor can jointly form a 1T1C (1 Transistor-1 Capacitor) cell structure. In this structure, the polysilicon gate layer of the transistor's gate structure 201 serves as the word line (WL), the second conductive layer 210 serves as the bit line (BL), and the fifth conductive layer 220 serves as the plate line (PL). The circuit netlist and array layout of this 1T1C cell structure are shown in Figures 4 and 5, respectively. Exemplarily, by controlling WL to select the ferroelectric capacitor, BL and PL apply forward and reverse voltages to the ferroelectric capacitor, respectively. Because the intermediate ferroelectric dielectric layer 214 is ferroelectric, it can form different iron domains (polarizations) under both forward and reverse electric fields. These iron domains do not disappear when the external electric field is removed, thus allowing the ferroelectric capacitor to store different charges and achieve a storage function.

[0100] This concludes the introduction to the structure of the semiconductor device disclosed herein. A complete device may also include other components, which will not be elaborated here.

[0101] Because the semiconductor device disclosed herein includes a ferroelectric capacitor with a horizontal capacitor structure and a vertical capacitor structure, the capacitor area can be increased in the vertical direction, thereby increasing the capacitance. The capacitance can be maintained even when the horizontal area of ​​the ferroelectric capacitor is reduced, solving the problem that the area of ​​the ferroelectric capacitor cannot be further reduced due to its small capacitance. This allows the area of ​​the memory cell structure where the ferroelectric capacitor is located to be further reduced, improving the integration and performance of the device. At the same time, the further reduced memory cell is also well compatible with copper process technology.

[0102] Example 3

[0103] This disclosure also provides an electronic device comprising the semiconductor device described in Embodiment 2 or a semiconductor device prepared by the method described in Embodiment 1.

[0104] The electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or it can be an intermediate product with the aforementioned semiconductor device, such as a mobile phone motherboard with the integrated circuit. The electronic device of this disclosure embodiment has better performance because it uses the aforementioned semiconductor device.

[0105] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More particularly, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first interlayer dielectric layer is formed on the substrate; The first interlayer dielectric layer is etched to form a trench; A first electrode layer is formed at the bottom and sidewalls of the trench; A ferroelectric dielectric layer is formed covering the first electrode layer; as well as A second electrode layer is formed covering the ferroelectric dielectric layer. The second electrode layer fills the remaining portion of the trench, such that the first electrode layer, the ferroelectric dielectric layer, and the second electrode layer constitute a ferroelectric capacitor.

2. The manufacturing method according to claim 1, wherein, The second electrode layer includes: An adhesive layer covering the ferroelectric dielectric layer, and A metal layer that covers the adhesive layer and fills the remainder of the trench.

3. The manufacturing method according to claim 2, wherein, The material of the first electrode layer includes titanium nitride, tantalum nitride, or platinum. The ferroelectric dielectric layer is made of zirconium-doped hafnium oxide. The adhesive layer may be made of titanium nitride, tantalum nitride, or platinum. The metal layer includes copper or tungsten.

4. The manufacturing method according to any one of claims 1-3, wherein, After forming the ferroelectric capacitor, the method further includes: A protective layer is formed covering the trench; Perform the annealing process.

5. The manufacturing method according to claim 4, wherein, The protective layer is made of silicon nitride, silicon oxynitride, or silicon oxide.

6. The manufacturing method according to any one of claims 1-5, wherein, The method further includes: A transistor is formed on the substrate such that the first interlayer dielectric layer covers the transistor; and A first conductive plug is formed in the first interlayer dielectric layer to electrically connect the source of the transistor to the first electrode layer.

7. The manufacturing method according to claim 6, wherein, After forming the first interlayer dielectric layer on the substrate, the method further includes: A first conductive layer is formed in the first interlayer dielectric layer, and the first conductive plug is electrically connected to the first electrode layer through the first conductive layer.

8. A semiconductor device, comprising: Substrate; The first interlayer dielectric layer is located on the substrate; The trench extends from the surface of the first interlayer dielectric layer into the first interlayer dielectric layer; The first electrode layer covers the bottom and sidewalls of the trench; A ferroelectric dielectric layer covers the first electrode layer; as well as The second electrode layer covers the ferroelectric dielectric layer and fills the remaining portion of the trench. The first electrode layer, the ferroelectric dielectric layer, and the second electrode layer constitute a ferroelectric capacitor.

9. The semiconductor device according to claim 8, wherein, It also includes transistors located on the substrate. The first interlayer dielectric layer covers the transistor, and a first conductive plug is formed in the first interlayer dielectric layer to electrically connect the source of the transistor to the first plate layer of the ferroelectric capacitor.

10. The semiconductor device according to claim 9, wherein, It also includes a first conductive layer located in the first interlayer dielectric layer. The first conductive plug is electrically connected to the first plate layer of the ferroelectric capacitor through the first conductive layer.

11. The semiconductor device according to any one of claims 8-10, wherein, The second electrode layer includes: An adhesive layer covering the ferroelectric dielectric layer, and A metal layer that covers the adhesive layer and fills the remainder of the trench.

12. The semiconductor device according to claim 11, wherein, The material of the first electrode layer includes titanium nitride, tantalum nitride, or platinum. The ferroelectric dielectric layer is made of zirconium-doped hafnium oxide. The adhesive layer may be made of titanium nitride, tantalum nitride, or platinum. The metal layer includes copper or tungsten.

13. The semiconductor device according to any one of claims 8-12, further comprising: A protective layer that covers the trench.

14. The semiconductor device according to claim 13, wherein, The protective layer is made of silicon nitride, silicon oxynitride, or silicon oxide.

15. An electronic device comprising the semiconductor device according to any one of claims 8-14.

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