Transistor device and manufacturing method for transistor device

Abstract

Disclosed in the present invention are a transistor device and manufacturing method for a transistor device. The transistor device comprises: a substrate, a gate stack structure and a select gate, wherein the gate stack structure is arranged on the substrate; the gate stack structure at least comprises a floating gate and a control gate; the select gate is arranged on one side of the gate stack structure; and the upper surface of the select gate is lower than the lower surface of the control gate. The floating gate, the control gate, and the select gate belong to a same transistor device. That is, in the present application, the select gate is formed on one side of the gate stack structure, and the upper surface of the select gate is lower than the lower surface of the gate stack structure, thereby reducing the coupling between the control gate in the gate stack structure, the select gate and increasing the breakdown voltage between the control gate and the select gate to expand a corresponding regulation range for voltage bearing, improving the operating speed of the transistor device, and then improving the performance of the transistor device.

Description

A transistor device and a method for manufacturing the transistor device.

[0001] Cross-referencing

[0002] This application claims priority to Chinese patent application No. CN202410927199.6, filed on July 11, 2024, the entire contents of which are incorporated herein by reference. [Technical Field]

[0003] This invention relates to the field of semiconductor technology, and in particular to a transistor device and a method for manufacturing the transistor device. [Background Technology]

[0004] In the application of integrated circuits, the performance of various devices is affected by the structure formed by the materials and thickness of each layer. In particular, for transistor devices, the different gate structures affect the performance of transistor devices.

[0005] In practice, the researchers of this application found that current semiconductor device manufacturing solutions, especially for transistor devices, typically use an ETOX (Electron Tunneling Oxide Device) floating gate structure. Due to the structure of the device, its breakdown voltage is relatively small, and the corresponding adjustment range is also small, which affects the operating speed of the device and thus affects the performance of the transistor device. [Summary of the Invention]

[0006] According to various embodiments of this application, a transistor device and a method for manufacturing the transistor device are provided.

[0007] This application provides a transistor device comprising: a substrate, a gate stack structure, and a select gate; the gate stack structure is disposed on the substrate, wherein the gate stack structure includes at least a floating gate and a control gate; the select gate is disposed on one side of the gate stack structure, and the upper surface of the select gate is lower than the lower surface of the control gate.

[0008] On the other hand, this application provides a method for manufacturing a transistor device, comprising: providing a substrate; forming a gate stack structure on the substrate, wherein the gate stack structure includes at least a floating gate and a control gate; forming a select gate on one side of the gate stack structure, wherein the upper surface of the select gate is lower than the lower surface of the control gate.

[0009] Details of one or more embodiments of the present invention are set forth in the following drawings and description. Other features, objects, and advantages of the invention will become apparent from the specification, drawings, and claims. [Attached Image Description]

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0011] Figure 1 is a schematic diagram of a transistor device according to an embodiment of this application;

[0012] Figure 2 is a schematic flowchart of an embodiment of the manufacturing method of the transistor device in this application;

[0013] Figure 3 is a schematic diagram of a substrate embodiment provided in this application;

[0014] Figure 4 is a schematic diagram of a structure of an embodiment of forming a gate layer on a substrate in this application;

[0015] Figure 5 is a structural schematic diagram of an embodiment of the second groove in this application;

[0016] Figure 6 is a schematic diagram of the structure of the first embodiment of forming the second inter-gate dielectric layer in this application;

[0017] Figure 7 is a schematic diagram of the structure of the first embodiment of forming the third gate layer in this application;

[0018] Figure 8 is a schematic diagram of the structure of the first embodiment of reducing the third gate layer in this application;

[0019] Figure 9 is a schematic diagram of the structure of the first embodiment of the gate stack structure in this application;

[0020] Figure 10 is a schematic diagram of the structure of the first embodiment of the selection gate in this application;

[0021] Figure 11 is a structural schematic diagram of the first embodiment of forming the isolation sidewall in this application;

[0022] Figure 12 is a schematic diagram of the structure of the first embodiment of forming the interlayer dielectric layer in this application;

[0023] Figure 13 is a schematic diagram of the structure of the second embodiment of forming the second inter-gate dielectric layer in this application;

[0024] Figure 14 is a schematic diagram of the structure of the second embodiment of forming the third gate layer in this application;

[0025] Figure 15 is a schematic diagram of the structure of the second embodiment of reducing the third gate layer in this application;

[0026] Figure 16 is a schematic diagram of a structural embodiment of removing the mask layer in this application;

[0027] Figure 17 is a schematic diagram of the structure of the second embodiment of the gate stack structure in this application;

[0028] Figure 18 is a schematic diagram of the structure of the second embodiment of the selection gate in this application;

[0029] Figure 19 is a structural schematic diagram of the second embodiment of forming the isolation sidewall in this application;

[0030] Figure 20 is a structural schematic diagram of the second embodiment of forming an interlayer dielectric layer in this application.

[0031] In the attached figures, there are transistor device 10, substrate 100, shallow trench isolation structure 101, gate stack structure 200, second trench 201, third trench 202, fourth trench 203, fifth trench 204, sixth trench 205, first gate insulating layer 210, first gate layer 221, floating gate 220, first inter-gate dielectric layer 230, second gate layer 241, control gate 240, mask layer 250, third gate layer 301, select gate 300, second inter-gate dielectric layer 310, first silicon oxide layer 311, silicon nitride layer 312, second silicon oxide layer 313, second gate insulating layer 320, isolation sidewall 400, first isolation sidewall 410, second isolation sidewall 420, third isolation sidewall 430, interlayer dielectric layer ILD, connecting pillar V, source region S, drain region D, storage region C, and peripheral region P.

Detailed Implementation Methods

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0033] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0034] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0035] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] In current semiconductor device manufacturing processes, especially in the manufacture of transistor devices, the ETOX floating gate structure is typically used. Due to the structure of the device, its breakdown voltage is relatively low, and the corresponding adjustment range is also relatively small, which affects the operating speed of the device and thus the performance of the transistor device. For example, if the transistor device is a memory device, the low breakdown voltage will affect the read, write and erase speeds of the memory device, thereby affecting the storage performance of the memory device.

[0037] Therefore, a transistor device is provided in which a selection gate is formed on one side of the gate stack structure on the substrate, and the upper surface of the selection gate is set to be lower than the lower surface of the control gate in the gate stack structure. This can effectively improve the corresponding breakdown voltage, increase the corresponding adjustment range, improve the operating speed of the transistor device, and thus ensure the performance of the transistor device.

[0038] Please refer to Figure 1, which is a schematic diagram of the structure of the first embodiment of the transistor device in this application.

[0039] Figure 1 shows a longitudinal cross-sectional view of a transistor device. The transistor device 10 of this application includes a substrate 100, a gate stack structure 200, and a select gate 300. The substrate 100 includes a storage region, and the gate stack structure 200 is disposed on the substrate 100 of the storage region. The gate stack structure 200 includes at least a floating gate and a control gate. The select gate 300 is disposed on one side of the gate stack structure, and the upper surface of the select gate 300 is lower than the lower surface of the control gate. The floating gate, control gate, and select gate belong to the same transistor device.

[0040] The substrate 100 can be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI).

[0041] In this embodiment, by forming a select gate on one side of the gate stack structure and setting the upper surface of the select gate to be lower than the lower surface of the control gate in the gate stack structure, the coupling between the control gate and the select gate is reduced. Furthermore, the vertical pressure between the control gate and the select gate increases their breakdown voltage and corresponding adjustment range, thereby improving the operating speed of the transistor device and ensuring the performance of the transistor device.

[0042] In some embodiments, the gate stack structure 200 may include: a first gate insulating layer 210, a floating gate 220, a first inter-gate dielectric layer 230, and a control gate 240.

[0043] The first gate insulating layer 210 is formed on the substrate 100, and the floating gate 220 is formed on the first gate insulating layer 210, so the floating gate 220 is isolated from the substrate 100 by the first gate insulating layer 210; the first inter-gate dielectric layer 230 is formed on the floating gate 220, and the control gate 240 is formed on the first inter-gate dielectric layer 230, so the control gate 240 is isolated from the floating gate 220 by the first inter-gate dielectric layer 230.

[0044] The first gate insulating layer can be an oxide layer covering the substrate; the first inter-gate dielectric layer can be a single-layer structure, such as a silicon oxide layer, or a double-layer structure, such as an ON structure, i.e., the first oxide layer and the nitride layer form an ON structure; or it can be a three-layer structure, such as an ONO structure, i.e., the first oxide layer, the nitride layer and the second oxide layer form an ONO structure, specifically an ONO structure composed of a silicon oxide layer, a silicon nitride layer and another silicon oxide layer.

[0045] In some embodiments, the select gate 300 is disposed on one side of the gate stack structure 200, and the upper surface of the select gate 300 is lower than the lower surface of the control gate 240 in the gate stack structure 200, further reducing the coupling between the control gate 240 and the select gate 300. When the transistor device is a memory device, during the erase operation of the memory device, the pressure between the control gate and the select gate is changed from the traditional method of relying on the dielectric between the select gate and the control gate to the vertical pressure between the control gate and the select gate, increasing the adjustment range. At the same time, the breakdown voltage between the control gate 240 and the select gate 300 is increased. Even when the parasitic MOS threshold of the floating gate portion is negative, the device channel will not be in the open state when the select gate is not selected, so there will be no BL (Bitline) leakage.

[0046] In some embodiments, the distance between the upper surface of the selection gate and the lower surface of the control gate is K, where K is greater than 20 nm, for example, the distance between the upper surface of the selection gate and the lower surface of the control gate is 30 nm.

[0047] Furthermore, the transistor device also includes a second inter-gate dielectric layer 310, that is, a second inter-gate dielectric layer 310 is disposed between the gate stack structure 200 and the select gate 300, that is, the second inter-gate dielectric layer 310 is disposed on one side of the gate stack structure 200, and the select gate 300 is isolated from the gate stack structure 200 by means of the second inter-gate dielectric layer 310.

[0048] The second inter-gate dielectric layer can be a single-layer structure, such as a silicon oxide layer, or a double-layer structure, such as an ON structure, which is composed of a first oxide layer and a nitride layer; or a three-layer structure, such as an ONO structure, which is composed of a first oxide layer, a nitride layer and a second oxide layer. Specifically, it can be an ONO structure composed of a silicon oxide layer, a silicon nitride layer and another silicon oxide layer.

[0049] Furthermore, the transistor device also includes a second gate insulating layer 320, that is, a second gate insulating layer 320 is formed between the select gate 300 and the substrate, and the select gate 300 is isolated from the substrate by the second gate insulating layer 320. The thickness of the second gate insulating layer 320 is greater than or equal to the thickness of the first gate insulating layer 210.

[0050] The thickness of the second gate insulating layer 320 can be greater than that of the first gate insulating layer 210. This can prevent electrons in the selection gate from entering the substrate. That is, the selection gate will be connected to the power supply during erasure. If the second gate insulating layer is too thin, electrons will continuously flow into the substrate, which is not conducive to erasure.

[0051] Furthermore, the transistor device may also include an isolation sidewall 400 disposed on both sides of the gate stack structure 200 and on one side of the select gate 300.

[0052] Specifically, because the select gate 300 is disposed on one side of the gate stack structure 200, and the upper surface of the select gate 300 is lower than the lower surface of the control gate 240 in the gate stack structure 200, and a second inter-gate dielectric layer 310 is disposed between the select gate 300 and the gate stack structure 200, the isolation sidewall 400 covers the exposed sidewall of the gate stack structure 200; therefore, the isolation sidewall includes a first isolation sidewall 410, a second isolation sidewall 420, and a third isolation sidewall 430; the first isolation sidewall 410 is disposed on the side of the gate stack structure 200 away from the select gate to cover the exposed sidewall of the gate stack structure 200; the second isolation sidewall 420 is disposed on the sidewall of the select gate away from the gate stack structure to cover the exposed sidewall of the select gate away from the gate stack structure; the third isolation sidewall 430 is disposed on the select gate 300 on the side of the gate stack structure 200 close to the select gate to cover the exposed sidewall of the gate stack structure on the select gate side. In some embodiments, the third isolation sidewall 430 may be omitted.

[0053] Furthermore, the transistor device also includes a source region S and a drain region D, wherein the source region S is disposed in the substrate 100 on the side of the select gate 300 away from the gate stack structure 200, and the drain region D is disposed in the substrate on the side of the gate stack structure 200 away from the select gate 300.

[0054] Specifically, in the presence of isolation sidewalls, the drain region D is disposed in the substrate on the side of the first isolation sidewall, that is, the drain region D is disposed in the substrate on the side of the isolation sidewall away from the select gate of the gate stack structure; then the source region S is disposed in the substrate on the side of the third isolation sidewall, that is, the source region S is disposed in the substrate on the side of the isolation sidewall away from the select gate of the gate stack structure.

[0055] Furthermore, the transistor device also includes an interlayer dielectric layer, wherein the interlayer dielectric layer covers the gate stack structure, the select gate and the substrate, and interconnects are formed in the interlayer dielectric layer, including source interconnects, drain interconnects, control gate interconnects and select gate interconnects.

[0056] Specifically, the source connection post is connected to the source region in the substrate and leads out the source region; the drain connection post is connected to the drain region in the substrate and leads out the drain region; the control gate connection post is connected to the control gate in the gate stack structure and leads out the control gate; the select gate connection post is connected to the select gate and leads out the select gate; that is, the source region, drain region, control gate and select gate are led out through the connection posts respectively, which facilitates voltage application.

[0057] In some embodiments, a connection improvement layer may also be provided, which corresponds to the connection post. That is, a connection improvement layer is provided under each connection post, so that the connection post can better lead out the source region, drain region, control gate, and select gate through the connection improvement layer. In some embodiments, the connection improvement layer may be a metal silicide layer, used to reduce the contact resistance between the connection post and the corresponding region.

[0058] In this embodiment, by setting a select gate on one side of the gate stack structure and setting the upper surface of the select gate to be lower than the lower surface of the control gate in the gate stack structure, the coupling between the control gate and the select gate in the gate stack structure is reduced. Furthermore, the vertical pressure between the control gate and the select gate increases the breakdown voltage between the control gate and the select gate, thereby increasing the adjustment range of the corresponding pressure and improving the operating speed of the transistor device, which in turn improves the performance of the transistor device.

[0059] Furthermore, the transistor device in this application also includes a peripheral region, that is, the substrate includes a storage region and a peripheral region.

[0060] Specifically, the substrate of a transistor device can be divided into a storage region and a peripheral region (not shown in the figure). The structure corresponding to the storage region is shown in Figure 1. The storage region and the peripheral region are separated by a shallow trench isolation structure in the substrate, and a MOS transistor is formed in the peripheral region.

[0061] This application also provides a method for manufacturing a transistor device.

[0062] Please refer to Figure 2, which is a schematic flowchart of an embodiment of the manufacturing method of a transistor device in this application.

[0063] As shown in Figure 2, the manufacturing method of the transistor device of this application includes the following steps:

[0064] S10, Provides a substrate.

[0065] S20. A gate stack structure is formed on the substrate, wherein the gate stack structure includes at least a floating gate and a control gate.

[0066] S30. A select gate is formed on one side of the gate stack structure, the upper surface of the select gate is lower than the lower surface of the control gate, wherein the floating gate, the control gate and the select gate belong to the same transistor device.

[0067] Figure 3-12 below is a schematic diagram of the manufacturing method of the transistor device in the first embodiment, as follows:

[0068] S10, Provides a substrate.

[0069] The substrate is any suitable substrate known in semiconductor devices, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI).

[0070] Specifically, a substrate 100 is provided, and a shallow trench isolation structure is formed in the substrate, wherein a portion of the shallow trench isolation structure divides the substrate 100 into a storage region C and a peripheral region P.

[0071] S20. A gate stack structure is formed on the substrate, wherein the gate stack structure includes at least a floating gate and a control gate.

[0072] The gate stack structure is formed on the substrate of the memory region C, meaning the gate stack structure is only formed in the memory region C; and the floating gate and the control gate can be polysilicon.

[0073] Specifically, a floating gate and a control gate are sequentially formed on the substrate of the storage region to form a gate stack structure. In one embodiment, a first gate insulating layer is formed on the substrate before forming the floating gate, and a first inter-gate dielectric layer is formed on the floating gate before forming the control gate. That is, the gate stack structure includes a first gate insulating layer, a floating gate, a first inter-gate dielectric layer, and a control gate.

[0074] S30. A selection gate is formed on one side of the gate stack structure.

[0075] The selection gate is also formed on the substrate of the storage region C, and the selection gate is made of polysilicon.

[0076] Specifically, after forming the gate stack structure, a select gate is formed on one side of the gate stack structure; in some embodiments, before forming the select gate, a second inter-gate dielectric layer needs to be formed on the side of the gate stack structure near the select gate, so that the subsequently formed select gate is isolated from the gate stack structure by the second inter-gate dielectric layer.

[0077] In this embodiment, by forming a gate stack structure on the substrate of the storage region, and then forming a select gate on the substrate on one side of the gate stack structure, the breakdown voltage between the control gate and the select gate is increased by the vertical pressure between the control gate and the select gate, thereby increasing the adjustment range of the corresponding pressure, improving the operating speed of the transistor device, and thus improving the performance of the transistor device.

[0078] The following describes the fabrication of a transistor device, with the upper surface of the selection gate being lower than the lower surface of the control gate and the second inter-gate dielectric layer being a three-layer structure.

[0079] First, a substrate 100 is provided, and the substrate 100 is divided into a storage region C and a peripheral region P.

[0080] Please refer to Figure 3, which is a schematic diagram of the structure of an embodiment of the substrate provided in this application.

[0081] As shown in Figure 3, step S10 may include the following operations: providing a substrate 100; in some embodiments, a first groove may be formed in the substrate, and a shallow trench isolation structure 101 may be formed in the first groove, thereby dividing the substrate into a storage region C and other regions through the shallow trench isolation structure 101, where the other regions may be peripheral regions P.

[0082] Next, a first gate insulating layer, a first gate layer, a first inter-gate dielectric layer, and a second gate layer are formed on the substrate 100.

[0083] Please refer to Figure 4, which is a schematic diagram of an embodiment of forming a gate layer on a substrate in this application.

[0084] As shown in Figure 4, based on Figure 3, a first gate insulating layer 210 is formed on the substrate 100, wherein the first gate insulating layer 210 covers the storage region C and the peripheral region P; then a first gate layer 221 is formed on the first gate insulating layer 210 in the storage region C, that is, the first gate layer 221 covers the first gate insulating layer 210 in the storage region C, and a first inter-gate dielectric layer 230 is formed on the first gate layer 221; then a second gate layer 241 is formed on the first inter-gate dielectric layer 230.

[0085] Since a gate stack structure will be formed in the storage region, the gate stack structure includes a first gate insulating layer, a floating gate, a first inter-gate dielectric layer, and a control gate, wherein the first gate layer 221 is used for subsequent formation of the floating gate, and the second gate layer 241 is used for subsequent formation of the control gate, therefore, the first gate insulating layer 210, the first gate layer 221, the first inter-gate dielectric layer 230, and the second gate layer 241 are formed in the storage region. A MOSFET will be formed in the peripheral region, wherein the first gate insulating layer 210 is used to form the gate insulating layer of the MOSFET, and the second gate layer 241 is used for subsequent formation of the gate of the MOSFET, therefore, the first gate insulating layer 210 and the second gate layer 241 are also formed in the peripheral region.

[0086] The first gate insulating layer can be an oxide layer to isolate the substrate and the first gate layer of the storage region; the first gate layer and the second gate layer can be polysilicon; the first inter-gate dielectric layer can be a single-layer structure, such as a silicon oxide layer, or a double-layer structure, such as an ON structure; or a three-layer structure, such as an ONO structure, that is, the first oxide layer, the nitride layer and the second oxide layer form an ONO structure, specifically an ONO structure composed of the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer.

[0087] In some embodiments, the second gate layer 241 further covers the first gate insulating layer of the peripheral region P, and a mask layer 250 is formed on the second gate layer 241 to cover the entire second gate layer 241, and the second gate layer 241 is isolated from the substrate 100 of the peripheral region P through the first gate insulating layer 210. The mask layer 250 may be a hard mask layer such as silicon oxide or silicon oxynitride.

[0088] Furthermore, a second groove is formed from the mask layer toward the first gate insulating layer to form a first island structure.

[0089] Please refer to Figure 5, which is a structural schematic diagram of an embodiment of the second groove in this application.

[0090] As shown in Figure 5, based on Figure 4, in the storage region C, a plurality of spaced second grooves 201 are formed from the mask layer 250 toward the first gate insulating layer 210, thereby forming a plurality of first island-shaped structures isolated by the second grooves 201.

[0091] Specifically, the second groove can be formed by etching, that is, from top to bottom, the mask layer 250, the second gate layer 241, the first inter-gate dielectric layer 230 and the first gate layer 221 are etched sequentially, and the first gate insulating layer is used as the etching stop layer.

[0092] In another embodiment, etching to form the second groove can sequentially etch the mask layer 250, the second gate layer 241, the first inter-gate dielectric layer 230, the first gate layer 221, and the first gate insulating layer 210, with the substrate as the etching stop layer.

[0093] In some embodiments, it is also necessary to etch a portion of the structure above the shallow trench isolation structure between the storage region C and the peripheral region P, as well as a portion of the shallow trench isolation structure, so that the shallow trench isolation structure in this region is flush with the substrate or slightly higher than the substrate.

[0094] In addition, a second inter-gate dielectric layer can be formed before forming the gate stack structure. The second inter-gate dielectric layer can be the same as the first inter-gate dielectric structure, which can be a single-layer structure, a double-layer structure, or a triple-layer structure. In this embodiment, it can be a double-layer structure, such as an ON structure, that is, a first oxide layer and a nitride layer form an ON structure. The material of the nitride layer can be silicon nitride or silicon oxynitride. It can also be a triple-layer structure, such as an ONO structure, that is, a first oxide layer, a nitride layer, and a second oxide layer form an ONO structure. Specifically, it can be an ONO structure composed of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.

[0095] Please refer to Figure 6, which is a schematic diagram of the structure of the first embodiment of forming the second inter-gate dielectric layer in this application. A second gate dielectric layer is formed on the sidewall of the first island structure, and a second gate insulating layer is formed at the bottom of the second groove during the formation of the second inter-gate dielectric layer.

[0096] As shown in Figure 6, taking the second inter-gate dielectric layer as a three-layer structure as an example, specifically: based on Figure 5, a first silicon oxide layer 311 and a silicon nitride layer 312 are formed sequentially to cover the sidewall of the first island structure; then, a second silicon oxide layer 313 is formed at the bottom of the second groove and on the first island structure, and the second silicon oxide layer 313 at the bottom of the second groove is used as the second gate insulating layer 320 (if the first gate insulating layer is retained at the bottom of the second groove, then the first gate insulating layer 210 and the second silicon oxide layer 313 at the bottom of the second groove are used as the second gate insulating layer 320), and the second silicon oxide layer 313, the silicon nitride layer 312 and the first silicon oxide layer 311 on the sidewall of the first island structure are used as the second inter-gate dielectric layer 310. That is, the second inter-gate dielectric layer 310 covers the sidewall of the first island structure of the storage region C; the second gate insulating layer 320 covers the bottom of the second groove; at the same time, the second inter-gate dielectric layer 310 can also cover the peripheral region P, wherein the thickness of the second gate insulating layer in the height direction is greater than or equal to the thickness of the first gate insulating layer, as shown in Figure 6, where the thickness of the second gate insulating layer in the height direction is greater than the thickness of the first gate insulating layer.

[0097] Furthermore, after forming the second inter-gate dielectric layer and the second gate insulating layer, and before forming the gate stack structure, a third gate layer also needs to be formed.

[0098] Please refer to Figure 7, which is a schematic diagram of a structure in an embodiment of forming a third gate layer in this application.

[0099] As shown in Figure 7, based on Figure 6, gate material is filled in the second groove 201 to form a third gate layer 301, and the third gate layer 301 is chemically and mechanically polished so that the third gate layer 301 is flush with the mask layer 250.

[0100] In some embodiments, when performing chemical mechanical polishing, the mask layer 250 can be used as a stop layer, and the thickness of the mask layer 250 can be appropriately reduced.

[0101] Furthermore, the height of the third gate layer needs to be reduced.

[0102] As shown in Figure 8, Figure 8 is a structural schematic diagram of an embodiment of reducing the third gate layer in this application.

[0103] As shown in Figure 8, the height of the third gate layer is reduced so that the upper surface of the third gate layer 301 is lower than the lower surface of the second gate layer 241, and the distance between the upper surface of the third gate layer 301 and the lower surface of the second gate layer 241 is K, where K is greater than 20nm, for example, the distance between the upper surface of the third gate layer 301 and the lower surface of the second gate layer 241 is 30nm.

[0104] Further, the first island structure is etched to form a gate stack structure.

[0105] Please refer to Figure 9, which is a schematic diagram of an embodiment of forming a gate stack structure in this application.

[0106] As shown in Figure 9, based on Figure 8, multiple third grooves 202 are formed from the second gate layer 241 toward the first gate insulating layer 210 to form a second island structure with the remaining second gate layer, first inter-gate dielectric layer, first gate layer and first gate insulating layer, and the second island structure is used as the gate stack structure 200.

[0107] In some embodiments, since a portion of the mask layer remains on the second gate layer, it is necessary to remove the remaining mask layer on the second gate layer first, so that the second gate layer is exposed.

[0108] Specifically, for example, the middle part of the first island structure can be removed to form a third groove 202. The third groove divides the remaining first island structure into two second island structures, each of which serves as a gate stack structure. That is, the remaining second gate layer, the first inter-gate dielectric layer, the remaining first gate layer, and the first gate insulating layer serve as the second island structure, while the remaining second gate layer in the second island structure serves as the control gate, and the remaining first gate layer serves as the floating gate. In other words, the gate stack structure includes, from top to bottom, a control gate 240, a first inter-gate dielectric layer 230, a floating gate 220, and a first gate insulating layer 210.

[0109] For the peripheral region, the residual second intergate dielectric layer between the peripheral region P and the storage region C needs to be removed.

[0110] Furthermore, after reducing the height of the third gate layer, the third gate layer is etched to form a select gate.

[0111] Please refer to Figure 10, which is a schematic diagram of the structure of an embodiment of the selection gate in this application.

[0112] As shown in Figure 10, based on Figure 9, in the storage region C, a portion of the third gate layer is removed, exposing the second gate insulating layer, with the remaining third gate layer serving as the select gate 300; that is, multiple fourth grooves 203 are formed from the third gate layer 301 toward the second gate insulating layer 320, with the remaining third gate layer serving as the select gate. For example, the middle portion of the third gate layer is removed to form the fourth groove 203, which divides the remaining third gate layer into two select gates. Each select gate 300 is isolated from the corresponding gate stack structure 200 through the second inter-gate dielectric layer 310.

[0113] The bottom of the fourth groove may end at the second gate insulating layer, or the fourth groove 203 may extend into the substrate.

[0114] For the peripheral area, the second gate layer is etched to form a MOS transistor.

[0115] Furthermore, isolation sidewalls need to be formed on both sides of the gate stack structure and on one side of the select gate.

[0116] Please refer to Figure 11, which is a structural schematic diagram of an embodiment of forming an isolation sidewall in this application.

[0117] As shown in Figure 11, based on Figure 10, the gate stack structure 200, the second inter-gate dielectric layer 310, and the select gate 300 are considered as a single structure. Isolation sidewalls 400 are formed on both sides of the single structure. Since the upper surface of the select gate 300 is lower than the lower surface of the control gate in the gate stack structure, isolation sidewalls also need to be formed on the sidewall of the gate stack structure 200 near the select gate 300. That is, the isolation sidewall 400 can include three parts: a first isolation sidewall 410, a second isolation sidewall 420, and a third isolation sidewall 430. The first isolation sidewall 410 covers the sidewall of the gate stack structure 200 away from the select gate 300, the second isolation sidewall 420 covers the sidewall of the select gate 300 away from the gate stack structure 200, and the third isolation sidewall 430 covers a portion of the sidewall of the gate stack structure 200 near the select gate 300. In some embodiments, the third isolation sidewall 430 can be omitted.

[0118] In some embodiments, a source region is formed in a substrate on one side of the gate stack structure 200 and the select gate 300, and a drain region (not shown) is formed in a substrate on the other side of the gate stack structure 200 and the select gate 300; specifically, a drain region is formed in a substrate on one side of the first isolation sidewall 410, and a source region is formed in a substrate on one side of the second isolation sidewall 420. The configuration of the source region and the drain region can be referred to FIG1.

[0119] In some embodiments, the positions of the source and drain regions can be interchanged, depending on the design.

[0120] Furthermore, an interlayer dielectric layer also needs to be formed.

[0121] Please refer to Figure 12, which is a schematic diagram of a structure of an embodiment of forming an interlayer dielectric layer in this application.

[0122] As shown in Figure 12, based on Figure 11, an interlayer dielectric layer (ILD) is formed to cover the corresponding gate stack structure 200, select gate 300 and substrate 100, and a connection pillar V is formed in the interlayer dielectric layer. The connection pillar V includes a source connection pillar, a drain connection pillar, a control gate connection pillar and a select gate connection pillar.

[0123] Specifically, the source connection post is connected to the source region in the substrate and leads out the source region; the drain connection post is connected to the drain region in the substrate and leads out the drain region; the control gate connection post is connected to the control gate 240 in the gate stack structure 200 and leads out the control gate 240; the select gate connection post is connected to the select gate 300 and leads out the select gate 300; that is, the source region, drain region, control gate and select gate are led out through the connection posts respectively, which facilitates voltage application.

[0124] In some embodiments, a connection improvement layer may also be provided, which corresponds to the connection post. That is, a connection improvement layer is provided under each connection post, so that the connection post can better lead out the source region, drain region, control gate, and select gate through the connection improvement layer. In some embodiments, the connection improvement layer may be a metal silicide layer, used to reduce the contact resistance between the connection post and the corresponding region.

[0125] In this embodiment, a gate stack structure is formed on the substrate, and a select gate is formed on one side of the gate stack structure. The gate stack structure and the select gate are isolated by a second inter-gate dielectric layer. The upper surface of the select gate is set to be lower than the lower surface of the control gate in the gate stack structure to form a transistor device. This reduces the coupling between the control gate and the select gate. Furthermore, the vertical pressure between the control gate and the select gate increases the breakdown voltage and the corresponding adjustment range, thereby improving the operating speed of the transistor device and ensuring its performance.

[0126] Furthermore, the second inter-gate dielectric layer is described as a single-layer structure.

[0127] In another embodiment of the manufacturing method of transistor device, the second gate dielectric layer is a single-layer structure or a double-layer structure. The similarities will not be repeated here. The manufacturing process of another embodiment will be described based on Figure 5.

[0128] Alternatively, before forming the gate stack structure, a single-layer second gate dielectric layer or a double-layer second gate dielectric layer can be formed; the single-layer structure can be a silicon oxide layer, and the double-layer structure can be an ON structure composed of a first oxide layer and a nitride layer.

[0129] Figures 13-20 below are schematic diagrams illustrating the manufacturing method of the transistor device in the second embodiment. (See below for details.)

[0130] Please refer to Figure 13, which is a structural schematic diagram of a second embodiment of forming the second inter-gate dielectric layer in this application. When forming the second inter-gate dielectric layer, a second gate insulating layer is formed at the bottom of the second groove.

[0131] As shown in Figure 13, taking the second inter-gate dielectric layer as a single-layer structure as an example, specifically: based on Figure 5, a first silicon oxide layer 311 is covered to cover the second groove 201 and the first island structure, and the first silicon oxide layer on the sidewall of the first island structure is used as the second inter-gate dielectric layer 310.

[0132] In some embodiments, the first silicon oxide layer 311 covers the bottom of the second groove 201, and the first gate insulating layer and the first silicon oxide layer at the bottom of the second groove serve as the second gate insulating layer 320. The first gate insulating layer and the first silicon oxide layer are made of the same material, for example, both are silicon oxide. The thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer, which can prevent electrons in the selection gate from entering the substrate. That is, the selection gate will be connected to the power supply during erasure. If the second gate insulating layer is too thin, electrons will continuously flow into the substrate, which is not conducive to erasure.

[0133] In some embodiments, the first gate insulating layer at the bottom of the second groove can be cleaned away first, and then a first silicon oxide layer can be formed at the bottom of the second groove. The first silicon oxide layer at the bottom of the second groove can be used as the second gate insulating layer. In one embodiment, the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer.

[0134] Furthermore, after forming the second inter-gate dielectric layer, a third gate layer is formed.

[0135] Please refer to Figure 14, which is a schematic diagram of the structure of the second embodiment of forming the third gate layer in this application.

[0136] As shown in Figure 14, based on Figure 13, gate material is filled in the second groove 201 to form a third gate layer 301, and the third gate layer 301 is chemically mechanically polished to remove the silicon oxide layer above the mask layer 250, so that the third gate layer is flush with the mask layer.

[0137] In some embodiments, during chemical mechanical polishing, the mask layer 250 can be used as a stop layer, and the thickness of the mask layer 250 can be appropriately reduced so that the third gate layer 301 is flush with the reduced mask layer 250.

[0138] Furthermore, the height of the third gate layer needs to be reduced.

[0139] Please refer to Figure 15, which is a schematic diagram of the structure of the second embodiment of reducing the third gate layer in this application.

[0140] As shown in Figure 15, based on Figure 14, the third gate layer 301 is etched to reduce its height, making the upper surface of the third gate layer 301 lower than the upper surface of the second gate layer 241. This ensures that the subsequently formed control gate and select gate are on different horizontal lines, thereby preventing short-circuit risks during the subsequent formation of the corresponding metal silicides.

[0141] In some embodiments, the height of the third gate layer can be set according to actual conditions, such as the upper surface of the third gate layer being lower than the upper surface of the second gate layer, or the upper surface of the third gate layer being flush with the lower surface of the second gate layer, or the upper surface of the third gate layer being lower than the lower surface of the second gate layer; in the accompanying drawings, it is indicated that the upper surface of the third gate layer is flush with the lower surface of the second gate layer.

[0142] In some embodiments, the remaining mask layer also needs to be removed.

[0143] Please refer to Figure 16, which is a structural schematic diagram of an embodiment of removing the mask layer in this application.

[0144] As shown in Figure 16, based on Figure 15, the remaining mask layer is removed to expose the second gate layer 241 of the storage region and the peripheral region.

[0145] Further, the first island structure is etched to form a gate stack structure.

[0146] Please refer to Figure 17, which is a schematic diagram of the structure of the second embodiment of forming the gate stack structure in this application.

[0147] As shown in Figure 17, based on Figure 16, in the storage region C, a plurality of fifth grooves 204 are formed from the second gate layer 241 toward the first gate insulating layer 210, so as to form a second island structure with the remaining second gate layer, the first inter-gate dielectric layer, the first gate layer and the first gate insulating layer, and the second island structure is used as the gate stack structure 200.

[0148] Specifically, for example, the middle part of the first island structure can be removed to form a fifth groove 204. The fifth groove divides the remaining first island structure into two second island structures, each of which serves as a gate stack structure. That is, the remaining second gate layer, the first inter-gate dielectric layer, the remaining first gate layer, and the first gate insulating layer serve as the second island structure, while the remaining second gate layer in the second island structure serves as the control gate, and the remaining first gate layer serves as the floating gate. In other words, the gate stack structure includes, from top to bottom, a control gate 240, a first inter-gate dielectric layer 230, a floating gate 220, and a first gate insulating layer 210.

[0149] For the peripheral region, the residual second intergate dielectric layer between the peripheral region P and the storage region C needs to be removed.

[0150] Further, the third gate layer is etched to form the select gate.

[0151] Please refer to Figure 18, which is a structural schematic diagram of the second embodiment of forming the selection gate in this application.

[0152] As shown in Figure 18, based on Figure 17, in the storage region C, a portion of the third gate layer is removed by etching, exposing the second gate insulating layer, with the remaining third gate layer serving as the select gate 300; that is, multiple sixth grooves 205 are formed from the third gate layer 301 toward the second gate insulating layer 320, with the remaining third gate layer serving as the select gate. For example, the middle portion of the third gate layer is removed to form the sixth groove 205, and the sixth groove 205 divides the remaining third gate layer into two select gates. Each select gate 300 is isolated from the corresponding gate stack structure 200 through the second inter-gate dielectric layer 310.

[0153] The bottom of the sixth groove 205 may end at the second gate insulating layer or extend into the substrate.

[0154] For the peripheral area, the second gate layer is etched to form a MOS transistor.

[0155] Furthermore, isolation sidewalls and interlayer media layers are formed.

[0156] Please refer to Figure 19, which is a structural schematic diagram of the second embodiment of forming the isolation sidewall in this application.

[0157] As shown in Figure 19, based on Figure 18, isolation sidewalls and interlayer medium layers are formed sequentially;

[0158] Specifically, the isolation sidewall 400 may include three parts: a first isolation sidewall 410, a second isolation sidewall 420, and a third isolation sidewall 430. The first isolation sidewall 410 covers the sidewall of the gate stack structure 200 away from the select gate 300, the second isolation sidewall 420 covers the sidewall of the select gate 300 away from the gate stack structure 200, and the third isolation sidewall 430 covers a portion of the sidewall of the gate stack structure 200 close to the select gate 300.

[0159] A drain region (not shown in the figure) is formed in the substrate on the side of the first isolation sidewall 410, and a source region (not shown in the figure) is formed in the substrate on the side of the second isolation sidewall 420.

[0160] Furthermore, an interlayer medium layer is formed.

[0161] Please refer to Figure 20, which is a structural schematic diagram of the second embodiment of forming an interlayer dielectric layer in this application.

[0162] As shown in Figure 20, based on Figure 19, an interlayer dielectric layer (ILD) is formed to cover the corresponding gate stack structure 200, select gate 300 and substrate 100, and a connection pillar V is formed in the interlayer dielectric layer. The connection pillar V includes a source connection pillar, a drain connection pillar, a control gate connection pillar and a select gate connection pillar.

[0163] Referring again to Figure 20, the source connection post connects to the source region S (not labeled in the figure) in the substrate and leads out the source region S; the drain connection post connects to the drain region D (not labeled in the figure) in the substrate and leads out the drain region D; the control gate connection post connects to the control gate 240 in the gate stack structure 200 and leads out the control gate 240; the select gate connection post connects to the select gate 300 and leads out the select gate 300. That is, the source region, drain region, control gate and select gate are led out through the connection posts respectively, which facilitates voltage application.

[0164] In some embodiments, a connection improvement layer may also be provided, which corresponds to the connection post. That is, a connection improvement layer is provided below each connection post, so that the connection post can better lead out the source region, drain region, control gate and select gate through the connection improvement layer.

[0165] In this embodiment, a transistor device is formed by forming a gate stack structure on the substrate, and a select gate on one side of the gate stack structure. The upper surface of the select gate is set lower than the upper surface of the control gate in the gate stack structure. This reduces the coupling between the control gate and the select gate. Furthermore, the vertical pressure between the control gate and the select gate increases their breakdown voltage and corresponding adjustment range, thereby improving the operating speed of the transistor device and ensuring its performance. Additionally, the control gate and the select gate are on different horizontal lines, preventing short-circuit risks during the subsequent formation of the corresponding metal silicide.

[0166] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A transistor device, characterized in that, include: Substrate; A gate stack structure is disposed on the substrate, wherein the gate stack structure includes at least a floating gate and a control gate; A selection gate is disposed on one side of the gate stack structure, the upper surface of the selection gate being lower than the lower surface of the control gate, wherein the floating gate, the control gate, and the selection gate belong to the same transistor device.

2. The transistor device according to claim 1, characterized in that, The gate stack structure includes: A first gate insulating layer is formed on the substrate; A floating gate is formed on the first gate insulating layer, and the floating gate is isolated from the substrate by the first gate insulating layer; A first inter-gate dielectric layer is formed on the floating gate; A control gate is formed on the first inter-gate dielectric layer, and the control gate is isolated from the floating gate by the first inter-gate dielectric layer.

3. The transistor device according to claim 1, characterized in that, Also includes: A second inter-gate dielectric layer is disposed on one side of the gate stack structure, wherein the select gate is isolated from the gate stack structure by means of the second inter-gate dielectric layer.

4. The transistor device according to claim 3, characterized in that, The second inter-gate dielectric layer is a single-layer structure, a double-layer structure, or a triple-layer structure. The single-layer structure is a silicon oxide layer, the double-layer structure includes a first oxide layer and a silicon nitride layer, and the triple-layer structure includes a first oxide layer, a silicon nitride layer, and a second oxide layer.

5. The transistor device according to claim 1, characterized in that, Also includes: A second gate insulating layer is disposed on the substrate, wherein the select gate is isolated from the substrate by the second gate insulating layer, and the thickness of the second gate insulating layer is greater than or equal to the thickness of the first gate insulating layer in the gate stack structure.

6. The transistor device according to claim 1, characterized in that, Also includes: Isolation sidewalls are disposed on both sides of the gate stack structure and on one side of the select gate.

7. The transistor device according to claim 1, characterized in that, Also includes: The source region is disposed in the substrate on the side of the select gate away from the gate stack structure; The drain region is disposed in the substrate on the side of the gate stack structure away from the select gate.

8. The transistor device according to claim 7, characterized in that, Also includes: An interlayer dielectric layer covers the gate stack structure, the select gate, and the substrate, and interconnect pillars are formed in the interlayer dielectric layer. The interconnect pillars include a drain interconnect pillar, a source interconnect pillar, a control gate interconnect pillar, and a select gate interconnect pillar. The drain interconnect pillar leads out the drain region, the source interconnect pillar leads out the source region, the control gate interconnect pillar leads out the control gate in the gate stack structure, and the select gate interconnect pillar leads out the select gate.

9. The transistor device according to claim 1, characterized in that, Also includes: A shallow trench isolation structure is disposed in the substrate and divides the substrate into a storage region and a peripheral region.

10. The transistor device according to claim 9, characterized in that, The gate stack structure and the select gate are disposed on the substrate of the memory region.

11. The transistor device according to claim 1, characterized in that, The distance between the upper surface of the selection gate and the lower surface of the control gate is K, where K is greater than 20 nm.

12. A method for manufacturing a transistor device, characterized in that, include: Provide substrate; A gate stack structure is formed on the substrate, wherein the gate stack structure includes at least a floating gate and a control gate; A select gate is formed on one side of the gate stack structure, the upper surface of the select gate being lower than the lower surface of the control gate, wherein the floating gate, the control gate, and the select gate belong to the same transistor device.

13. The method according to claim 12, characterized in that, The formation of the gate stack structure on the substrate includes: A first gate insulating layer is formed on the substrate; A first gate layer is formed to cover the first gate insulating layer, and a first inter-gate dielectric layer is formed on the first gate layer; A second gate layer is formed on the first inter-gate dielectric layer, and a mask layer is formed on the second gate layer; A second groove is formed from the mask layer toward the first gate insulating layer to form a first island structure; The first island structure is etched to form the gate stack structure.

14. The method according to claim 13, characterized in that, Before forming the gate stack structure, the method further includes: A second inter-gate dielectric layer is formed on the sidewall of the first island structure, and a second gate insulating layer is formed at the bottom of the second groove.

15. The method according to claim 14, characterized in that, After forming the second inter-gate dielectric layer and the second gate insulating layer, the method further includes: A third gate layer is formed in the second groove; the height of the third gate layer is reduced so that the upper surface of the third gate layer is lower than the lower surface of the second gate layer.

16. The method according to claim 15, characterized in that, The step of forming a selection gate on one side of the gate stack structure includes: After reducing the height of the third gate layer, the third gate layer is etched to form the select gate.

17. The method according to claim 12, characterized in that, Also includes: Isolation sidewalls are formed on both sides of the gate stack structure and on one side of the select gate; A source region is formed in the substrate on the side of the select gate away from the gate stack structure, and a drain region is formed on the side of the gate stack structure away from the select gate.

18. The method according to claim 17, characterized in that, Also includes: An interlayer dielectric layer is formed to cover the gate stack structure, the select gate, and the substrate, and interconnect pillars are formed in the interlayer dielectric layer. The interconnect pillars include a drain interconnect pillar, a source interconnect pillar, a control gate interconnect pillar, and a select gate interconnect pillar. The drain interconnect pillar leads out the drain region, the source interconnect pillar leads out the source region, the control gate interconnect pillar leads out the control gate in the gate stack structure, and the select gate interconnect pillar leads out the select gate.

19. The method according to claim 12, characterized in that, Also includes: A shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure divides the substrate into a storage region and a peripheral region, and the gate stack structure and the select gate are formed on the substrate in the storage region.

20. The method according to claim 12, characterized in that, The distance between the upper surface of the selection gate and the lower surface of the control gate is K, where K is greater than 20 nm.

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