CMOS device and manufacturing method therefor

Abstract

The present invention provides a CMOS device and a manufacturing method therefor. The manufacturing method for a CMOS device comprises: forming a first gate dielectric layer in a first region and a second region; forming a second gate dielectric layer on the first gate dielectric layer, the second gate dielectric layer covering the first gate dielectric layer, and the thickness of the second gate dielectric layer being greater than that of the first gate dielectric layer; performing heat treatment on the first gate dielectric layer and the second gate dielectric layer; and removing the second gate dielectric layer in the second region. A first gate dielectric layer covers both a first region and a second region; therefore, no grain boundary defect occurs between the first gate dielectric layer in the first region and the first gate dielectric layer in the second region, thereby avoiding the problem of electric leakage. Additionally, a second gate dielectric layer is formed on the first gate dielectric layer, so that a semiconductor substrate is not consumed in the process of forming the second gate dielectric layer, and thus a height difference on the surface of the semiconductor substrate can be avoided, thereby avoiding the problem of electric leakage of the semiconductor substrate.

Description

CMOS devices and their manufacturing methods

[0001] This invention claims priority to Chinese Patent Application No. 202410935481.9, filed on July 12, 2024, entitled "CMOS Device and Manufacturing Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor technology, and in particular to a CMOS device and its manufacturing method. Background Technology

[0003] In integrated circuit manufacturing technology, to improve device integration and performance, the gate dielectric layer thickness of CMOS (Complementary Metal Oxide Semiconductor) devices is continuously decreasing according to the principle of proportional scaling. Currently, in CMOS devices, to improve device performance and reliability, gate dielectric layers of different thicknesses are used to isolate gates from the semiconductor substrate; that is, the thickness of the gate dielectric layer between a thick gate and the semiconductor substrate is usually greater than the thickness of the gate dielectric layer between a thin gate and the semiconductor substrate.

[0004] Specifically, existing methods for forming gate dielectric layers of different thicknesses in CMOS devices include: First, as shown in Figure 1, a thicker first gate dielectric layer 11 is formed on the first region 10A and the second region 10B using a thermal oxidation process; then, as shown in Figure 2, the first gate dielectric layer 11 on the second region 10B is removed, exposing the second region 10B; next, as shown in Figure 3, a second gate dielectric layer 12 is formed on the second region 10B. The thickness of the second gate dielectric layer 12 is less than the thickness of the first gate dielectric layer 11, i.e., the first gate dielectric layer 11 is thicker and the second gate dielectric layer 12 is thinner. Since the first gate dielectric layer 11 and the second gate dielectric layer 12 are not formed in the same process step, grain boundary defects are likely to exist at the boundary (or junction) between the first gate dielectric layer 11 and the second gate dielectric layer 12, resulting in leakage current and affecting the electrical properties and reliability of the device. Furthermore, the second gate dielectric layer 12 is directly formed on the surface of the semiconductor substrate 10 in the second region 10B. Therefore, the growth of the second gate dielectric layer 12 will consume the semiconductor substrate 10, resulting in a height difference between the surface of the semiconductor substrate 10 in the second region and the surface of the semiconductor substrate 10 in the first region. This will affect the channel current of the device or cause leakage problems. Summary of the Invention

[0005] The purpose of this invention is to provide a CMOS device and its manufacturing method to improve grain boundary defects at the gate dielectric layer boundaries in different regions and leakage current problems on the surface of semiconductor substrates.

[0006] To achieve the above objectives, the present invention provides a method for manufacturing a CMOS device, comprising:

[0007] A semiconductor substrate is provided, the semiconductor substrate comprising a first region and a second region;

[0008] A first gate dielectric layer is formed on the semiconductor substrate, the first gate dielectric layer covering the first region and the second region;

[0009] A second gate dielectric layer is formed on the first gate dielectric layer, the second gate dielectric layer covers the first gate dielectric layer, and the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer;

[0010] The first gate dielectric layer and the second gate dielectric layer are subjected to heat treatment;

[0011] Remove the second gate dielectric layer from the second region.

[0012] Optionally, in the manufacturing method of the CMOS device, the material of the first gate dielectric layer includes silicon oxide, and the first gate dielectric layer is formed by an in-situ vapor generation process.

[0013] Optionally, in the manufacturing method of the CMOS device, the material of the second gate dielectric layer includes silicon oxide, and the second gate dielectric layer is formed by thermal oxidation process or atomic layer deposition process.

[0014] Optionally, in the manufacturing method of the CMOS device, the thickness of the first gate dielectric layer is 8 angstroms to 40 angstroms; and the thickness of the second gate dielectric layer is 20 angstroms to 50 angstroms.

[0015] Optionally, in the method for manufacturing the CMOS device, after forming the first gate dielectric layer and before forming the second gate dielectric layer, the method further includes:

[0016] The first gate dielectric layer is nitrided using a decoupled plasma nitriding process; and,

[0017] An annealing process is performed on the first gate dielectric layer after nitriding.

[0018] Optionally, in the manufacturing method of the CMOS device, the heat treatment is a peak annealing process or an immersion annealing process, and the temperature of the heat treatment is 950℃~1050℃.

[0019] Optionally, in the method for manufacturing the CMOS device, the method for removing the second gate dielectric layer in the second region includes:

[0020] A patterned photoresist layer is formed on the second gate dielectric layer, the patterned photoresist layer exposing the second gate dielectric layer in the second region;

[0021] Using the patterned photoresist layer as a mask, a chemical gas etching process is employed to remove the second gate dielectric layer in the second region; and,

[0022] Remove the patterned photoresist layer.

[0023] Optionally, in the manufacturing method of the CMOS device, the etching gas used in the chemical gas etching process includes ammonia and hydrogen fluoride.

[0024] Optionally, in the method for manufacturing the CMOS device, after removing the second gate dielectric layer in the second region, the first gate dielectric layer in the second region is exposed;

[0025] After removing the second gate dielectric layer in the second region, the method further includes: forming a third gate dielectric layer that covers the first gate dielectric layer and the second gate dielectric layer.

[0026] Based on the same inventive concept, the present invention also provides a CMOS device, comprising:

[0027] A semiconductor substrate, the semiconductor substrate comprising a first region and a second region;

[0028] A first gate dielectric layer, the first gate dielectric layer covering the first region and the second region;

[0029] A second gate dielectric layer covers the first gate dielectric layer in the first region.

[0030] In the CMOS device manufacturing method provided by this invention, a first gate dielectric layer is first formed on a first region and a second region; then, a second gate dielectric layer is formed on the first gate dielectric layer, the second gate dielectric layer covering the first gate dielectric layer, and the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer; next, the first and second gate dielectric layers are heat-treated to improve the film quality of the first and second gate dielectric layers and repair lattice damage, thereby improving the performance of the first and second gate dielectric layers; then, the second gate dielectric layer in the second region is removed. Since the first gate dielectric layer simultaneously covers the first and second regions, the first gate dielectric layer in the first region and the first gate dielectric layer in the second region are a continuous integral film layer, so there are no grain boundary defects between the first gate dielectric layer in the first region and the first gate dielectric layer in the second region, thereby avoiding leakage current problems. Furthermore, the second gate dielectric layer is formed on the first gate dielectric layer, that is, the first gate dielectric layer isolates the second gate dielectric layer from the semiconductor substrate, so the semiconductor substrate is not consumed during the formation of the second gate dielectric layer, thereby avoiding height differences on the surface of the semiconductor substrate and thus avoiding leakage current problems in the semiconductor substrate. Attached Figure Description

[0031] Figures 1 to 3 are schematic diagrams of the structure after the gate dielectric layer is formed on the first and second regions in the existing CMOS device manufacturing method;

[0032] Figure 4 is a flowchart illustrating the manufacturing method of a CMOS device provided in an embodiment of the present invention;

[0033] Figures 5 to 10 are schematic diagrams of the structure formed in the manufacturing method of the CMOS device provided in the embodiments of the present invention.

[0034] The reference numerals in the attached drawings are explained as follows: 10-Semiconductor substrate; 10A-First region; 10B-Second region; 11-First gate dielectric layer; 100-Semiconductor substrate; 100A-First region; 100-Second region; 110-First gate dielectric layer; 120-Second gate dielectric layer; 130-Patterned photoresist layer; 140-Third gate dielectric layer; 150-First gate; 160-Second gate. Detailed Implementation

[0035] The CMOS device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0036] Figure 4 is a schematic flowchart of a CMOS device manufacturing method provided in an embodiment of the present invention. As shown in Figure 4, this embodiment provides a CMOS device manufacturing method, including:

[0037] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a first region and a second region;

[0038] Step S2: A first gate dielectric layer is formed using an in-situ steam generation process, the first gate dielectric layer covering the first region and the second region;

[0039] Step S3: A second gate dielectric layer is formed on the first gate dielectric layer, the second gate dielectric layer covers the first gate dielectric layer, and the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer;

[0040] Step S4: Perform heat treatment on the first gate dielectric layer and the second gate dielectric layer;

[0041] Step S5: Remove the second gate dielectric layer in the second region.

[0042] Figures 5 to 10 are schematic diagrams of the structure formed in the manufacturing method of the CMOS device provided in the embodiments of the present invention. The manufacturing method of the CMOS device provided in this embodiment will be described in more detail below with reference to Figures 5 to 10.

[0043] In step S1, referring to FIG. 5, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a first region 100A and a second region 100B. The semiconductor substrate 100 can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in this embodiment, silicon (Si) is selected as the constituent material of the semiconductor substrate 100.

[0044] In this embodiment, the first region 100A of the semiconductor substrate 100 can be used to form the source extension region or the drain extension region of a CMOS device. A thicker gate dielectric layer can be formed on the first region 100A to provide better isolation and protection. The second region 100B can be used to form a channel region. A thinner gate dielectric layer can be formed on the second region 100B.

[0045] In this embodiment, a well region and a shallow trench isolation structure (STI) are formed in the semiconductor substrate. To better illustrate the inventive points of the present invention, the description and illustration of the well region and the shallow trench isolation structure are omitted.

[0046] In step S2, as shown in FIG5, a first gate dielectric layer 110 is formed on the semiconductor substrate 100, the first gate dielectric layer 110 covering the first region 100A and the second region 100B. The first gate dielectric layer 110 may be made of silicon oxide and is formed by an in-situ steam generation (ISSG) process.

[0047] Specifically, the method for forming the first gate dielectric layer 110 includes: first, cleaning the semiconductor substrate 100 to remove impurities and contaminants from its surface; then, placing the semiconductor substrate 100 in an in-situ vapor generation process apparatus and introducing hydrogen and oxygen to synthesize water vapor in situ on the surface of the semiconductor substrate 100, which then combines with silicon and other materials on the surface of the semiconductor substrate 100 to form an oxide, thereby forming the first gate dielectric layer 110. The in-situ vapor generation process for forming the first gate dielectric layer 110 results in better film quality and uniformity. The thickness of the first gate dielectric layer 110 can be 8 angstroms to 40 angstroms, for example, 10 angstroms, 15 angstroms, 20 angstroms, or 30 angstroms.

[0048] In a further embodiment, after forming the first gate dielectric layer 110, the method further includes: performing a nitriding treatment on the first gate dielectric layer 110 to increase the dielectric constant of the first gate dielectric layer 110, thereby improving the performance of the first gate dielectric layer 110.

[0049] Preferably, the nitrogen doping treatment is performed using a decoupled plasma nitridation (DPN) process. The process temperature of the decoupled plasma nitridation process can be between 550°C and 700°C. The relatively low process temperature prevents nitrogen atoms from diffusing to the surface of the semiconductor substrate 100, while simultaneously ensuring a high nitrogen content in the first gate dielectric layer 110, which is beneficial for improving gate leakage current and increasing carrier mobility.

[0050] Subsequently, an annealing process is performed on the first gate dielectric layer 110 after nitriding. For example, the annealing process can be a peak annealing process. By performing the annealing process on the first gate dielectric layer 110, the lattice defects generated in the aforementioned nitrogen doping step are repaired, and the nitrogen atoms doped in the first gate dielectric layer 110 are also activated. The annealing temperature should not be too low or too high. If the annealing temperature is too low, the annealing process is less effective in repairing lattice defects and activating nitrogen atoms; if the annealing temperature is too high, it easily increases the diffusion of nitrogen atoms in the first gate dielectric layer 110, thereby increasing the probability of nitrogen atoms diffusing to the surface of the semiconductor substrate 100. Therefore, in this embodiment, the annealing process temperature is 950℃~1050℃.

[0051] In step S3, referring to FIG6, a second gate dielectric layer 120 is formed on the first gate dielectric layer 110. The second gate dielectric layer 120 covers the first gate dielectric layer 110, and the thickness of the second gate dielectric layer 120 is greater than the thickness of the first gate dielectric layer 110.

[0052] In this embodiment, the second gate dielectric layer 120 is made of silicon oxide and can be formed using a rapid thermal oxidation (RTO) process. Specifically, the RTO process utilizes an oxidation furnace or a rapid thermal annealing chamber, employing oxygen as the process gas, to form the second gate dielectric layer 120 on the first gate dielectric layer 110. This process is simple to operate, and the resulting second gate dielectric layer 120 exhibits good thickness uniformity and density, which is beneficial for improving the film quality of the second gate dielectric layer 120. The temperature of the RTO process can be between 900℃ and 1050℃.

[0053] In another embodiment, the second gate dielectric layer 120 can be formed using an atomic layer deposition (ALDCVD) process. Specifically, the ALD process uses silane as the precursor and oxygen as the reactant gas, and utilizes pulsed radio frequency ionization of the reactant gas and precursor to form the second gate dielectric layer 120 on the first gate dielectric layer 110.

[0054] Since the second gate dielectric layer 120 is formed on the first gate dielectric layer 110, i.e. the first gate dielectric layer 110 isolates the second gate dielectric layer 120 from the semiconductor substrate 100, the semiconductor substrate 100 is not consumed during the formation of the second gate dielectric layer 120. This avoids the height difference between the surface of the semiconductor substrate 100 in the second region 100B and the surface of the semiconductor substrate 100 in the first region 100A, thereby avoiding the problem of leakage current in the semiconductor substrate 100.

[0055] In this embodiment, the thickness of the second gate dielectric layer 120 can be 20 angstroms to 50 angstroms, for example, 20 angstroms, 30 angstroms or 50 angstroms, to meet the withstand voltage requirements of the first region 100A.

[0056] In step S4, the first gate dielectric layer 110 and the second gate dielectric layer 120 are heat-treated. This improves the film quality of the first gate dielectric layer 110 and the second gate dielectric layer 120 and repairs lattice damage.

[0057] Specifically, the heat treatment can be a spike anneal, with the process gas including nitrogen (N2) or argon (Ar). Additionally, oxygen (O2) or water vapor (H2O) can be used to adjust the oxidizing or reducing atmosphere during the annealing process. Alternatively, the heat treatment can be a soak anneal, with the process gas including nitrogen (N2) or argon (Ar).

[0058] Furthermore, the heat treatment temperature is 950℃ to 1050℃. If the heat treatment temperature is too low, the effect of heat treatment in repairing lattice defects and improving film quality will be poor; if the heat treatment temperature is too high, it will easily increase the diffusion of nitrogen atoms in the first gate dielectric layer 110, thereby increasing the probability of nitrogen atoms diffusing to the surface of the semiconductor substrate 100. Therefore, in this embodiment, the process temperature of the heat treatment is 950℃ to 1050℃, for example, 1000℃ or 1050℃.

[0059] In step S5, referring to FIG8, the second gate dielectric layer 120 of the second region 100B is removed. That is, the first gate dielectric layer 110 of the second region 100B is retained. The first gate dielectric layer 110 of the second region 100B is used to achieve isolation between the subsequently formed thin gate and the semiconductor substrate 100, thereby meeting the withstand voltage requirement between the thin gate and the semiconductor substrate 100. The second gate dielectric layer 120 and the first gate dielectric layer 110 of the first region 100A are also retained. The second gate dielectric layer 120 and the first gate dielectric layer 110 of the first region 100A are used to achieve isolation between the subsequently formed thick gate and the semiconductor substrate 100, thereby meeting the withstand voltage requirement between the thick gate and the semiconductor substrate 100. Furthermore, the first gate dielectric layer 110 of the first region 100A and the first gate dielectric layer 110 of the second region 100B are a continuous monolithic film layer. Therefore, there are no grain boundary defects between the first gate dielectric layer 110 of the first region 100A and the first gate dielectric layer 110 of the second region 100B, thereby avoiding leakage current problems.

[0060] Specifically, the method for removing the second gate dielectric layer 120 of the second region 100B includes: as shown in FIG. 7, forming a patterned photoresist layer 130 on the second gate dielectric layer 120, wherein the patterned photoresist layer 130 exposes the second gate dielectric layer 120 of the second region 100B, that is, the patterned photoresist layer covers the second gate dielectric layer 120 of the first region 100A; then, as shown in FIG. 8, using the patterned photoresist layer as a mask, removing the second gate dielectric layer 120 of the second region 100B using a chemical gas etching process. The etching gases used in the chemical gas etching process include ammonia (NH3) and hydrogen fluoride (HF). Next, removing the patterned photoresist layer 130, wherein the patterned photoresist layer 130 can be removed by an ashing process or a wet cleaning method.

[0061] Subsequently, as shown in Figure 9, a third gate dielectric layer 140 is formed, which covers the second gate dielectric layer 120 and the first gate dielectric layer 110. The third gate dielectric layer 140 can be made of hafnium oxide (HfO2) and is formed using a chemical vapor deposition (CVD) process.

[0062] Next, an annealing process is performed on the third gate dielectric layer 140 to improve the film quality of the third gate dielectric layer 140.

[0063] Next, as shown in FIG10, a first gate 150 is formed on the third gate dielectric layer 140 of the first region 100A, and a second gate 160 is formed on the third gate dielectric layer 140 of the second region 100B. The thickness of the first gate 150 is greater than the thickness of the second gate 160, that is, the first gate 150 is a thick gate and the second gate 160 is a thin gate.

[0064] It should be noted that the first gate 150 and the second gate 160 are a hybrid gate structure, meaning that the first gate 150 and the second gate 160 are electrically connected and integrated into the same device (or transistor), but the regions where the first gate 150 and the second gate 160 are located are different. The first gate 150 can be located in a non-critical region of the CMOS device, such as the source extension region or the drain extension region, which can improve the thermal stability of the device. The second gate 160 can be located in a critical region of the CMOS device, such as the channel region, which can reduce the gate capacitance, improve the switching speed of the CMOS device, and reduce the power consumption of the device.

[0065] Furthermore, the method for forming the first gate 150 and the second gate 160 includes: sequentially forming a barrier layer and a dummy gate on the third gate dielectric layer 140, wherein the barrier layer can be made of titanium nitride and the dummy gate can be made of polysilicon; then, etching the dummy gate to expose a portion of the barrier layer; next, forming an interlayer dielectric layer that covers the barrier layer and whose top surface is flush with the top surface of the dummy gate; next, removing the dummy gate to form a dummy gate opening; next, forming a gate material layer in the dummy gate opening, wherein the gate material layer is made of metal; and then, etching the gate material layer in the first region and the gate material layer in the second region respectively to form a first gate and a second gate with different thicknesses.

[0066] Furthermore, after etching the dummy gate to expose a portion of the barrier layer, before forming the interlayer dielectric layer, sidewalls can be formed on the sidewalls of the dummy gate, and source and drain regions can be formed in the semiconductor substrates (i.e., the first and second regions) on both sides of the dummy gate. After forming the interlayer dielectric layer, the interlayer dielectric layer also covers the source and drain regions. In this embodiment, for better illustration of the inventive points of the present invention, the description and illustration of the sidewalls, barrier layer, source and drain regions are omitted.

[0067] This embodiment also provides a CMOS device, as shown in FIG10. The CMOS device provided in this embodiment includes: a semiconductor substrate 100, the semiconductor substrate including a first region 100A and a second region 100B; a first gate dielectric layer 110, the first gate dielectric layer 110 covering the first region 100A and the second region 100B; and a second gate dielectric layer 120, the second gate dielectric layer 120 covering the first gate dielectric layer 110 of the first region 100A.

[0068] In this embodiment, the CMOS device can be a PMOS transistor or an NMOS transistor.

[0069] In summary, in the CMOS device and its manufacturing method provided by this invention, a first gate dielectric layer is first formed on a first region and a second region; then, a second gate dielectric layer is formed on the first gate dielectric layer, covering the first gate dielectric layer, and the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer; next, the first and second gate dielectric layers are heat-treated to improve the film quality of the first and second gate dielectric layers and repair lattice damage, thereby improving the performance of the first and second gate dielectric layers; then, the second gate dielectric layer in the second region is removed. Since the first gate dielectric layer simultaneously covers the first and second regions, the first gate dielectric layer in the first region and the first gate dielectric layer in the second region are a continuous integral film layer, so there are no grain boundary defects between the first gate dielectric layer in the first region and the first gate dielectric layer in the second region, thus avoiding leakage problems. Furthermore, the second gate dielectric layer is formed on the first gate dielectric layer, that is, the first gate dielectric layer isolates the second gate dielectric layer from the semiconductor substrate, so the semiconductor substrate is not consumed during the formation of the second gate dielectric layer, thereby avoiding height differences on the surface of the semiconductor substrate and thus avoiding leakage problems in the semiconductor substrate.

[0070] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing a CMOS device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate comprising a first region and a second region; A first gate dielectric layer is formed on the semiconductor substrate, the first gate dielectric layer covering the first region and the second region; A second gate dielectric layer is formed on the first gate dielectric layer, the second gate dielectric layer covers the first gate dielectric layer, and the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer; The first gate dielectric layer and the second gate dielectric layer are subjected to heat treatment; Remove the second gate dielectric layer from the second region.

2. The method for manufacturing a CMOS device as described in claim 1, characterized in that, The first gate dielectric layer is made of silicon oxide and is formed using an in-situ vapor generation process.

3. The method for manufacturing a CMOS device as described in claim 1, characterized in that, The second gate dielectric layer is made of silicon oxide and is formed by thermal oxidation or atomic layer deposition.

4. The method for manufacturing a CMOS device as described in claim 1, characterized in that, The thickness of the first gate dielectric layer is 8 angstroms to 40 angstroms; the thickness of the second gate dielectric layer is 20 angstroms to 50 angstroms.

5. The method for manufacturing a CMOS device as described in claim 1, characterized in that, After forming the first gate dielectric layer and before forming the second gate dielectric layer, the method for manufacturing the CMOS device further includes: The first gate dielectric layer is nitrided using a decoupled plasma nitriding process; and, An annealing process is performed on the first gate dielectric layer after nitriding.

6. The method for manufacturing a CMOS device as described in claim 1, characterized in that, The heat treatment is either peak annealing or immersion annealing, and the temperature of the heat treatment is 950℃~1050℃.

7. The method for manufacturing a CMOS device as described in claim 1, characterized in that, The method for removing the second gate dielectric layer in the second region includes: A patterned photoresist layer is formed on the second gate dielectric layer, the patterned photoresist layer exposing the second gate dielectric layer in the second region; Using the patterned photoresist layer as a mask, a chemical gas etching process is employed to remove the second gate dielectric layer in the second region; and, Remove the patterned photoresist layer.

8. The method for manufacturing a CMOS device as described in claim 7, characterized in that, The etching gases used in the chemical gas etching process include ammonia and hydrogen fluoride.

9. The method for manufacturing a CMOS device as described in claim 1, characterized in that, After removing the second gate dielectric layer in the second region, the first gate dielectric layer in the second region is exposed; After removing the second gate dielectric layer in the second region, the method further includes: forming a third gate dielectric layer that covers the first gate dielectric layer and the second gate dielectric layer.

10. A CMOS device, characterized in that, include: A semiconductor substrate, the semiconductor substrate comprising a first region and a second region; A first gate dielectric layer, the first gate dielectric layer covering the first region and the second region; A second gate dielectric layer covers the first gate dielectric layer in the first region.

Images