Operation circuit, processor, and computing apparatus

Abstract

The present disclosure relates to an operation circuit, a processor, and a computing apparatus. The operation circuit comprises: symbol processing sub-circuits, configured to convert second matrix elements in a second matrix into corresponding first operands, wherein the first operands are unsigned numbers; and multiply-accumulate sub-circuits, input ends of the multiply-accumulate sub-circuits being communicatively connected to output ends of the symbol processing sub-circuits, and each multiply-accumulate sub-circuit being configured to calculate at least an inner product of a first vector and a second vector, wherein a k-th component of the first vector is a k-th first matrix element in a current operation row of the first matrix, a k-th component of the second vector is a first operand obtained by converting a k-th second matrix element in a current operation column of the second matrix, and the dimension of the first vector and the dimension of the second vector are each N.

Description

Arithmetic circuits, processors, and computing devices

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410912414.5, filed on July 9, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to the field of electronic circuit technology, and more specifically, to an arithmetic circuit, a processor, and a computing device. Background Technology

[0004] Matrix multiplication is a common operation in data processing. However, current circuits used for matrix multiplication suffer from problems such as complex structure, high power consumption, and difficulty in meeting timing requirements, necessitating improvements. Summary of the Invention

[0005] One of the purposes of this disclosure is to provide an arithmetic circuit, a processor, and a computing device.

[0006] According to a first aspect of this disclosure, a computational circuit is provided for performing a multiplication of a first matrix by a second matrix, wherein the number of columns in the first matrix and the number of rows in the second matrix are each N, and each first matrix element in the first matrix is ​​a pre-known coefficient, the computational circuit comprising:

[0007] A symbol processing subcircuit, configured to convert a second matrix element in the second matrix into a corresponding first operand, wherein the first operand is an unsigned number; and,

[0008] A multiply-accumulate subcircuit is provided, the input of which is communicatively connected to the output of the symbol processing subcircuit. The multiply-accumulate subcircuit is configured to compute at least the inner product of a first vector and a second vector, wherein the k-th component of the first vector is the k-th first matrix element in the current operation row of the first matrix, the k-th component of the second vector is the first operand obtained by transforming the k-th second matrix element in the current operation column of the second matrix, and the dimensions of the first vector and the second vector are each N.

[0009] In some embodiments, the arithmetic circuit includes N symbol processing sub-circuits, each symbol processing sub-circuit being configured, in the same operating cycle, to transform a corresponding second matrix element in the same column of the second matrix; and / or,

[0010] The computational circuit includes N' multiply-accumulate sub-circuits. In the same operation cycle, each multiply-accumulate sub-circuit is configured to calculate the inner product of a first vector and a second vector associated with a corresponding element of the third matrix in the same column of the third matrix, where N' is the number of rows of the first matrix and the third matrix is ​​the matrix obtained by multiplying the first matrix by the second matrix.

[0011] In some embodiments, the symbol processing subcircuit is configured to invert the target symbol bit of the second matrix element to generate a corresponding first operand, wherein the target symbol bit of the second matrix element is the most significant bit of the second matrix element.

[0012] In some embodiments, the symbol processing subcircuit is configured as follows:

[0013] Determine whether the high m bits of each second matrix element in the current operation column of the second matrix are all extended sign bits, where m is a preset positive integer and m is less than the total number of bits M of the second matrix element;

[0014] If the high m bits of each second matrix element in the current operand column are extended sign bits, then the high m bits of the second matrix element are set to zero, and the target sign bit of the second matrix element is inverted to generate the corresponding first operand. Here, the target sign bit of the second matrix element is the next lower bit adjacent to the high m bits of that second matrix element, or...

[0015] If at least one of the high m bits of a second matrix element in the current operand is not an extended sign bit, the target sign bit of the second matrix element is inverted to generate the corresponding first operand, wherein the target sign bit of the second matrix element is the highest bit of the second matrix element.

[0016] In some embodiments, the symbol processing subcircuit is configured as follows:

[0017] Determine the position of the true sign bit of each second matrix element in the current operation column of the second matrix, and take the highest true sign bit among all the true sign bits of the second matrix elements in the current operation column as the target sign bit; and,

[0018] Set all bits of the second matrix element that are higher than the target sign bit to zero, and invert the target sign bit of the second matrix element to generate the corresponding first operand.

[0019] In some embodiments, the symbol processing subcircuit includes an inverter whose input is configured to receive a target symbol bit of a second matrix element to invert the target symbol bit.

[0020] In some embodiments, the symbol processing subcircuit includes a symbol bit determination unit, the symbol bit determination unit comprising:

[0021] A first AND gate unit, having multiple input terminals, each input terminal configured to receive a corresponding bit to be determined from a second matrix element in the current operation column, and the output terminal of the first AND gate unit configured to output an indication signal indicating whether the received multiple bits to be determined are all extended sign bits; or,

[0022] An OR gate unit, having multiple input terminals, each input terminal configured to receive a corresponding bit to be determined from a second matrix element in the current operation column, and the output terminal of the OR gate unit configured to output an indication signal indicating whether the received multiple bits to be determined are all extended sign bits; or,

[0023] An XOR gate unit has multiple input terminals, each input terminal being configured to receive a corresponding bit to be determined from a second matrix element in the current operation column, and the output terminal of the XOR gate unit being configured to output an indication signal indicating whether the multiple bits to be determined received are all extended sign bits.

[0024] In some embodiments, the symbol processing subcircuit includes a second AND gate unit, the two inputs of which are configured to receive a signal zero representing zero and a corresponding bit to be set to zero for a second matrix element, respectively, so as to set the bit to be set to zero.

[0025] In some embodiments, the multiply-accumulate subcircuit includes a shift-add unit, which is configured to:

[0026] If the first matrix element multiplied with the first operand is positive, the first operand is shifted by a preset number of positions in a preset direction to generate one or more corresponding second operands, wherein the preset direction and the preset number of positions are determined based on the first matrix element multiplied with the first operand.

[0027] In some embodiments, the multiply-accumulate sub-circuit further includes a bit-by-bit inversion unit, which is configured to: invert the first operand bit by bit when the first matrix element multiplied with the first operand is negative, so as to generate a corresponding third operand;

[0028] The shift-add unit is further configured to shift the third operand by a preset number of bits in a preset direction to generate one or more corresponding fourth operands, wherein the preset direction and the preset number of bits are determined based on the first matrix element multiplied by the first operand.

[0029] In some embodiments, the shift-add unit is further configured to:

[0030] Calculate the sum of all second or fourth operands generated from N first operands.

[0031] In some embodiments, the first matrix element cik multiplied by the first operand Xkj satisfies cik=∑[(-1)] s *2 p In the case of:

[0032] If s is even, shift the first operand p bits to the left to produce the corresponding second operand;

[0033] If s is odd, invert the first operand bit by bit to generate the third operand, and shift the third operand p bits to the left to generate the corresponding fourth operand;

[0034] Wherein, the i-th row is the current operation row of the first matrix, and the j-th column is the current operation column of the second matrix.

[0035] In some embodiments, the multiply-accumulate subcircuit is configured to calculate the sum of the inner product of the first vector and the second vector and a preset constant, wherein the preset constant is determined based on the transformation relationship between the second matrix element associated with the second vector and the corresponding first operand, and the first matrix element associated with the first vector.

[0036] In some embodiments, where at least two first matrix elements having the same absolute value exist in at least one row of the first matrix, the computation circuit further includes:

[0037] A symmetric operation subcircuit, configured to calculate the sum or difference of a second matrix element or a corresponding first operand multiplied by at least two first matrix elements having the same absolute value in the same row of a first matrix.

[0038] In some embodiments, the symmetric operation sub-circuit is disposed between the symbol processing sub-circuit and the multiply-accumulate sub-circuit.

[0039] In some embodiments, the symmetric operation sub-circuit includes a single-level butterfly operation unit or a cascaded multi-level butterfly operation unit.

[0040] In some embodiments, the second matrix is ​​the transpose of the image matrix; or,

[0041] The second matrix is ​​the transpose of the fourth matrix, wherein the fourth matrix is ​​the matrix obtained by multiplying the first matrix by the transpose of the image matrix;

[0042] Wherein, the matrix element in the image matrix represents the pixel parameter of the pixel at the corresponding position in the image to be processed, or the matrix element in the image matrix represents the difference in pixel parameter of the pixel at the corresponding position in two adjacent frames of the image to be processed.

[0043] In some embodiments, the arithmetic circuit is configured to perform a discrete cosine transform operation, and the first matrix is ​​a discrete cosine transform coefficient matrix.

[0044] According to a second aspect of this disclosure, a processor is provided, including the arithmetic circuitry described above.

[0045] According to a third aspect of this disclosure, a computing device is provided, including the arithmetic circuitry described above or the processor described above.

[0046] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0047] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0048] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0049] Figure 1 shows a schematic diagram of an operational circuit for performing DCT8 operations;

[0050] Figure 2 shows a schematic diagram of the structure of an operational circuit according to an exemplary embodiment of the present disclosure;

[0051] Figure 3 shows a schematic diagram of the symbol processing sub-circuit in an arithmetic circuit according to a specific embodiment of the present disclosure;

[0052] Figure 4 shows a schematic diagram of the symbol processing sub-circuit in an arithmetic circuit according to another specific embodiment of the present disclosure;

[0053] Figure 5 shows a schematic diagram of the sign bit determination unit in an arithmetic circuit according to a specific embodiment of the present disclosure;

[0054] Figure 6 shows a schematic diagram of the sign bit determination unit in an arithmetic circuit according to another specific embodiment of the present disclosure;

[0055] Figure 7 shows a schematic diagram of the sign bit determination unit in an arithmetic circuit according to another specific embodiment of the present disclosure;

[0056] Figure 8 shows a schematic diagram of the structure of the multiply-accumulate sub-circuit in an arithmetic circuit according to a specific embodiment of the present disclosure;

[0057] Figure 9 shows a schematic diagram of the structure of an operational circuit according to another exemplary embodiment of the present disclosure;

[0058] Figure 10 shows a schematic diagram of another operational circuit for performing DCT8 operations;

[0059] Figure 11 shows a schematic diagram of another operational circuit for performing DCT8 operations;

[0060] Figure 12 shows a block diagram of a processor according to an exemplary embodiment of the present disclosure;

[0061] Figure 13 shows a block diagram of a computing device according to an exemplary embodiment of the present disclosure;

[0062] Figure 14 shows a block diagram of a computing device according to another exemplary embodiment of the present disclosure.

[0063] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0064] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0065] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0066] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0067] In addition, techniques, methods and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods and equipment should be considered part of the specification.

[0068] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0069] Matrix multiplication is a common operation in various data processing processes. For example, the multiplication of the first matrix C and the second matrix X can be represented as: Y = CX (1)

[0070] If we let cij represent the first matrix element located in the i-th row and j-th column of the first matrix C, xij represent the second matrix element located in the i-th row and j-th column of the second matrix X, and yij represent the third matrix element located in the i-th row and j-th column of the third matrix Y obtained by multiplying the first and second matrices, where i and j can be integers greater than or equal to zero (those skilled in the art will understand that i and j can also be integers greater than or equal to 1, which does not affect the essence of the operation; therefore, this paper will take the example of i and j starting from zero for detailed explanation), then, according to the rules of matrix multiplication, the third matrix element yij in the third matrix Y can be represented in the following form:

[0071] In this matrix, the number of columns in the first matrix C and the number of rows in the second matrix X are both N, and k is an integer.

[0072] In a specific example, the operational circuitry used to implement matrix multiplication, as described herein, can be configured to perform a Discrete Cosine Transform (DCT) operation. DCT, a crucial component of image or video coding, transforms an image described in pixel form in the spatial domain to the transform domain. Considering that most images typically contain large areas of flatness or regions with slow content changes, appropriate DCT operations can convert the relatively dispersed distribution of image energy in the spatial domain into a relatively concentrated distribution in the transform domain, thereby removing spatial redundancy and simplifying subsequent image or video data processing. For example, a two-dimensional DCT operation can be represented as a matrix multiplication as shown below: Z = CX0C T =C(CX0) T ) T (3)

[0073] Here, X0 represents the image matrix corresponding to the image to be processed. In some embodiments, the matrix elements in the image matrix can represent the pixel parameters of the pixels at corresponding positions in a certain frame of the image to be processed. The pixel parameters may include, for example, the RGB parameters of the pixel or other types of color parameters. In other embodiments, considering that the difference between two adjacent frames in a video is usually small, in order to optimize the compression rate of video encoding, the two adjacent frames in the video can be subtracted before processing. In this case, the matrix elements in the image matrix can represent the difference in pixel parameters of pixels at corresponding positions in two adjacent frames of the image to be processed. For example, the matrix elements can represent the difference in color parameters of pixels at the same corresponding position in two adjacent frames. X0 in the above formula (3) T This represents the transpose of the image matrix X0. In some computational processes (such as the first matrix multiplication in a DCT operation), X0 can be used as the transpose of the image matrix X0. T The coefficient matrix of the 2D DCT operation is used as the first matrix C to perform matrix multiplication, with X as the second matrix. Additionally, in some operations (such as the second matrix multiplication in the DCT operation), the first matrix C is multiplied by the transpose of the image matrix, X0. T The resulting fourth matrix CX0 T The transpose of the fourth matrix (CX0) can be used. T ) T Using the coefficient matrix of the two-dimensional DCT operation as the first matrix C, matrix multiplication is performed to complete the entire DCT operation. In other words, a two-dimensional DCT operation can be implemented through two one-dimensional DCT operations, each involving the multiplication of two matrices. The technical solution of this disclosure will be illustrated in detail in some specific examples below, using DCT operations as an example. However, those skilled in the art will understand that the operational circuit described herein, as well as the processor and computing device including such operational circuit, can be used for any matrix multiplication operation involved in any type of data processing, and are not limited herein.

[0074] Taking DCT8 (where each matrix involved in the multiplication operation has an 8x8 dimension) as an example, its coefficient matrix C can be represented in the following form:

[0075] As can be seen, the coefficient matrix C of DCT8 contains both positive and negative coefficients. Therefore, the arithmetic circuit used to perform matrix multiplication should also be compatible with operations between signed numbers. Furthermore, it can be noted that the coefficient matrix C of DCT8 exhibits high symmetry, which can be used to simplify the arithmetic circuit. In a specific example, the arithmetic circuit shown in Figure 1 can be used to implement the matrix multiplication operation of each one-dimensional DCT operation in DCT8. This arithmetic circuit can include a symmetric arithmetic sub-circuit 120' and a multiply-accumulate sub-circuit 110'. The symmetric arithmetic sub-circuit 120' can be used to execute the butterfly algorithm, which is designed based on the symmetric relationships in the coefficient matrix C of DCT8, as will be explained in detail later. The multiply-accumulate sub-circuit 110' can be formed by units or modules such as multipliers, adders, or adder trees to implement the multiply-accumulate operation in the above formula (2) to obtain the corresponding third matrix element in the third matrix Y. However, due to the presence of signed numbers in matrix multiplication, the arithmetic circuit shown in Figure 1, especially the multiply-accumulate sub-circuit 110', must be able to perform signed multiplication and addition operations. That is, the sign bits of each operand involved in the operation must be processed during the operation. This results in the arithmetic circuit shown in Figure 1 having disadvantages such as complex structure, high power consumption, and difficulty in meeting timing requirements.

[0076] To address the aforementioned issues, this disclosure provides an operational circuit for performing the operation of multiplying a first matrix C by a second matrix X, as shown in FIG2. The operational circuit 100 may include a symbol processing sub-circuit 130 and a multiply-accumulate sub-circuit 110.

[0077] As mentioned above, according to the rules of matrix multiplication, the number of columns in the first matrix C should be equal to the number of rows in the second matrix X. For ease of description, let the number of columns in the first matrix C and the number of rows in the second matrix X each be N. Furthermore, according to the rules of matrix multiplication, the number of rows in the third matrix Y obtained by multiplying the first matrix C by the second matrix X should be equal to the number of rows N' of the first matrix C, and the number of columns in the third matrix Y should be equal to the number of columns N' of the second matrix X. In some detailed examples below, the first, second, and third matrices will be square matrices for detailed explanation. However, those skilled in the art will understand that in some embodiments, the first, second, and third matrices may not be square matrices, which is not a limitation here, as long as their number of rows and columns meets the limitations imposed by the above-mentioned rules of matrix multiplication. In addition, in the exemplary embodiments of this disclosure, each first matrix element cij in the first matrix C can be a pre-known coefficient, so as to determine the specific structure of the operation circuit and the values ​​of various parameters that may be involved therein, as will be explained in detail below. In addition, the second matrix X can be generated based on the data to be processed, which may include image data, video data, or other types of data, etc., which is not limited here.

[0078] The inventors of this disclosure note that in some embodiments, the above formula (2) involving operations on signed numbers xkj can be rewritten in the following form by the following mathematical derivation:

[0079] Where M is the bit width of the second matrix element in the second matrix X. By inverting the highest bit (or sign bit) of the signed number xkj, the signed number xkj can be converted to an unsigned number Xkj, i.e., Xkj = xkj + 2. M-1 .

[0080] Furthermore, in actual data processing, most of the second matrix elements xkj involved may be numbers with small absolute values ​​(for example, in the case where the matrix elements in the image matrix described above represent the difference in pixel parameters of corresponding pixels in two adjacent frames of the image to be processed). That is, many high-order bits in such a second matrix element may be extended sign bits, or the highest bit of such a second matrix element may not be its true sign bit. When these extended sign bits participate in the computation process, they will cause a large number of flips in related devices, units, or modules in the computation circuit. The power consumption of the computation circuit can be divided into static power consumption and dynamic power consumption. Static power consumption is generally related to the size of the computation circuit, while dynamic power consumption is related not only to the size of the computation circuit but also to the flip rate in the computation circuit. Therefore, the large number of flips caused by the extended sign bits will lead to a significant increase in the power consumption of the computation circuit. To address this, the power consumption of the computation circuit can be reduced by decreasing the flip rate. In some embodiments, at least some of the extended sign bits of the second matrix elements that meet the conditions can be set to zero to reduce or even avoid the participation of extended sign bits in matrix multiplication operations, thereby reducing the flip rate of the computation circuit. In this case, formula (2) involving operations on signed numbers xkj can be rewritten as follows:

[0081] Where M is the bit width of the second matrix element in the second matrix X, and m is the number of bits of the extended sign bit of the second matrix element that is set to zero. Here, the lower bit adjacent to the extended sign bit of the second matrix element is taken as the target sign bit of the second matrix element. By setting the high m bits of the second matrix element to zero and inverting the target sign bit of the second matrix element, the signed number xkj can be converted into the unsigned number Xkj, that is, Xkj = xkj + 2. M-m-1 It is understandable that, in order to simplify subsequent calculations, the same sign bit processing is generally applied to a group of second matrix elements associated with the same third matrix element. Therefore, for each second matrix element, its target sign bit may be the actual sign bit of the second matrix element, or it may be an extended sign bit of the second matrix element, as will be illustrated in detail later.

[0082] As described above, the symbol processing subcircuit 130 can be configured to convert the second matrix element xkj in the second matrix X into a corresponding first operand Xkj existing in the form of an unsigned number. In the following text, for the sake of brevity, let m' take the value M or Mm, and the specific value of m' is as described above. Thus, Xkj = xkj + 2 m’-1 .

[0083] Furthermore, the above formula (4) or (4') can be rewritten in the following form:

[0084] in, Since cik, N, and m' are all known constants, Ai1 is also a constant. Thus, Ai1 in the above formula (5) can be extracted as a constant term for subsequent processing, and the multiply-accumulate sub-circuit 110 can calculate only the first term in the above formula (5). That's it. It's important to note that since Ai1 is related to cik, the corresponding value of Ai1 may be different for different elements in the same column of the third matrix Y, requiring separate handling.

[0085] Furthermore, since cik is a known coefficient and Xkj is an unsigned number, when cik is positive, the value of cik*Xkj can be calculated directly using unsigned multiplication. When cik is negative, considering that cik is known in advance, cik*Xkj can be converted into unsigned multiplication in advance, as will be explained in detail later.

[0086] As shown in Figure 2, the input of the multiply-accumulate subcircuit 110 can be communicatively connected to the output of the symbol processing subcircuit 130, and the multiply-accumulate subcircuit 110 can be configured to at least calculate the inner product of the first vector and the second vector, wherein the k-th component of the first vector is the k-th first matrix element cik in the current operation row (e.g., the i-th row) of the first matrix C, and the k-th component of the second vector is the first operand Xkj obtained by transforming the k-th second matrix element xkj in the current operation column (e.g., the j-th column) of the second matrix X. It can be understood that the dimensions of the first vector and the second vector are each N.

[0087] In some embodiments, all third matrix elements in the same column of the third matrix Y, or all vector inner products related to these third matrix elements as described above, can be computed in parallel or substantially in parallel within the same operating cycle of the arithmetic circuit.

[0088] Therefore, the arithmetic circuit may include N symbol processing sub-circuits 130. In the same operation cycle, each symbol processing sub-circuit 130 may be configured to transform a corresponding second matrix element in the same column of the second matrix X. For example, to implement DCT8 operation, the arithmetic circuit may include a total of 8 symbol processing sub-circuits 130, wherein the k-th symbol processing sub-circuit may be configured to receive the k-th second matrix element xkj in the j-th column (i.e., the current operation column) of the second matrix processed in the current operation cycle, where k is an integer and 0 ≤ k < 8.

[0089] Similarly, the arithmetic circuit may include N' multiply-accumulate subcircuits 110, where N' is the number of rows in the first matrix C, as described above. Thus, in the same operating cycle, each multiply-accumulate subcircuit 110 can be configured to calculate the inner product of a first vector and a second vector associated with a corresponding third matrix element in the same column of the third matrix Y. It is understood that each multiply-accumulate subcircuit 110 shown in Figure 2 can be communicatively connected to all symbol processing subcircuits 130 to obtain all second matrix elements in the same column of the second matrix X for calculating the inner product of the first vector and the second vector associated with a corresponding third matrix element. For simplicity, the communication connections between all symbol processing subcircuits 130 and multiply-accumulate subcircuits 110 are not shown in the figures. When the first and second matrices are square matrices, N' = N. For example, to implement DCT8 operations, the operation circuit may include a total of 8 multiply-accumulate sub-circuits 110, wherein each multiply-accumulate sub-circuit 110 may be configured to calculate the inner product of a first vector and a second vector associated with a corresponding third matrix element ykj in the j-th column of the third matrix Y, where k is an integer and 0≤k<8.

[0090] Furthermore, in the exemplary embodiments of this disclosure, an arithmetic circuit 100 comprising N symbol processing sub-circuits 130 and N' multiply-accumulate sub-circuits 110 can complete the multiplication of the first matrix C by the second matrix X within a total of N” operation cycles, obtaining the values ​​of all third matrix elements or vector inner products or other parameters related to these third matrix elements in the third matrix, as described above, where N” is the number of columns in the second matrix. When the first and second matrices are square matrices, N” = N.

[0091] In some other embodiments, the arithmetic circuit may include more or fewer symbol processing sub-circuits 130 or multiply-accumulate sub-circuits 110. A buffer or similar device may also be incorporated into the arithmetic circuit to cache intermediate results involved in the operation, thereby completing the matrix multiplication operation. No limitation is imposed here. Furthermore, as the scale of the arithmetic circuit 100 increases (e.g., the number of symbol processing sub-circuits 130 or multiply-accumulate sub-circuits 110 increases), the number of operation cycles required for matrix operations may decrease, and the corresponding computation time may decrease. However, the structural complexity of the arithmetic circuit 100 may increase. Therefore, a trade-off can be made according to actual needs to determine the appropriate number and arrangement of the symbol processing sub-circuits 130 and multiply-accumulate sub-circuits 110.

[0092] In some embodiments, as described above, the symbol processing subcircuit 130 can be configured to invert the target sign bit of the second matrix element to generate a corresponding first operand. In a specific example, the target sign bit of the second matrix element can be the most significant bit of the second matrix element, i.e., the first operand Xkj = xkj + 2.M-1 .

[0093] Accordingly, as shown in Figure 3, the symbol processing subcircuit 130 may include an inverter 131, the input of which can be configured to receive the target symbol bit (i.e., the most significant bit) of the second matrix element, and invert the target symbol bit. Furthermore, the symbol processing subcircuit 130 can directly output the other bits of the second matrix element by concatenating the inverted target symbol bit with the other bits in sequence to obtain the corresponding first operand. It is understood that when the symbol processing subcircuit 130 processes only one second matrix element at a time, it may have only one inverter 131, and the symbol processing subcircuit 130 may also have M-1 paths to directly output the other bits of the second matrix element besides the target symbol bit, where M is the total number of bits or the bit width of the second matrix element. In some other embodiments, if the symbol processing subcircuit 130 processes multiple second matrix elements at a time, it may include multiple inverters 131 and a corresponding number of other paths, etc., without limitation.

[0094] In other embodiments, as described above, at least some of the extended sign bits of the second matrix element can be set to zero to suppress high-bit flips, reduce the idling of the arithmetic circuit, and thus reduce the power consumption of the arithmetic circuit.

[0095] Specifically, in some embodiments, the symbol processing subcircuit 130 can be configured to determine whether the high m bits of each second matrix element in the current operation column (e.g., the j-th column) of the second matrix are all extended sign bits. Here, m can be a preset positive integer, and m is less than the total number of bits M of the second matrix element. For example, empirically, m can be set to the largest integer less than half the total number of bits M of the second matrix element. Of course, m can also be set to other values ​​empirically to minimize the oscillation of the arithmetic circuit, which is not limited here. Further, the symbol processing subcircuit 130 can be configured to, when the high m bits of each second matrix element in the current operation column are extended sign bits, set all the high m bits of the second matrix element to zero and invert the target sign bit of the second matrix element to generate a corresponding first operand, where the target sign bit of the second matrix element is the lower bit adjacent to the high m bits of the second matrix element; or, when the high m bits of at least one second matrix element in the current operation column are not all extended sign bits, invert the target sign bit of the second matrix element to generate a corresponding first operand, where the target sign bit of the second matrix element is the highest bit of the second matrix element. In other words, based on experience accumulated during data processing, a suitable value for m can be pre-set. For each group of second matrix elements (i.e., second matrix elements in the same column of the second matrix) involved in the operation of each third matrix element, it can be determined whether their high m bits are extended sign bits. If so, the number of bits of this group of second matrix elements can be reduced, that is, the high m bits of each second matrix element in this group are set to 0, and the lower bit adjacent to the high m bits is used as the target sign bit for inversion. Otherwise, the number of bits of this group of second matrix elements is not reduced, but the highest bit of each second matrix element in this group is directly inverted for subsequent calculations.

[0096] In a specific example, suppose M = 8, and the eight second matrix elements in a column participating in the DCT8 operation are: 11110001, 11110101, 11111101, 11110000, 11111001, 11111111, 00000001, 00001001. If the value of m is set to 3, then the first set of operands obtained by adjusting the sign bit of this set of second matrix elements as described above includes: 00000001, 0000010 1. 00001101, 00000000, 00001001, 00001111, 00010001, 00011001; If the value of m is set to 5, then the first set of operands obtained by adjusting the sign bit of this set of second matrix elements as described above includes: 01110001, 01110101, 01111101, 01110000, 01111001, 01111111, 10000001, 10001001.

[0097] To achieve the sign bit adjustment as described above, as shown in Figure 4, the sign processing subcircuit 130 may further include a sign bit determination unit 133 to determine whether the high m bits of each second matrix element in the current operation column of the second matrix are extended sign bits. The sign bit determination unit 133 can be configured in various ways, and no limitation is made here.

[0098] In some embodiments, as shown in FIG5, the sign bit determination unit 133 may include a first AND gate unit. This first AND gate unit may have multiple input terminals, each configured to receive a corresponding bit to be determined from a second matrix element in the current operation column. The output terminal of the first AND gate unit may be configured to output an indication signal indicating whether the received multiple bits to be determined are all extended sign bits. In a specific example, a corresponding first AND gate unit may be set for a second matrix element. This first AND gate unit may include m+1 input terminals, each used to receive a corresponding bit from the high m+1 bits of the second matrix element. If the output of the first AND gate unit is 1, it indicates that the high m+1 bits of the second matrix element are all 1, thus determining that the high m bits of the second matrix element are all extended sign bits (corresponding to the case where the second matrix element is negative); otherwise, the high m bits of the second matrix element are not necessarily all extended sign bits.

[0099] In some embodiments, as shown in FIG6, the sign bit determination unit 133 may include an OR gate unit. This OR gate unit may have multiple input terminals, each configured to receive a corresponding bit to be determined from a second matrix element in the current operation column. The output terminal of the OR gate unit may be configured to output an indication signal indicating whether the received multiple bits to be determined are all extended sign bits. In a specific example, a corresponding OR gate unit may be set for a second matrix element. This OR gate unit may include m+1 input terminals, each used to receive a corresponding bit from the high m+1 bits of the second matrix element. If the output of the OR gate unit is 0, it indicates that the values ​​of the high m+1 bits of the second matrix element are all 0. Therefore, it can be determined that the high m bits of the second matrix element are all extended sign bits (corresponding to the case where the second matrix element is a positive number); otherwise, the high m bits of the second matrix element are not necessarily all extended sign bits.

[0100] Since the value of the second matrix element may be positive or negative, in some embodiments, the sign bit determination unit 133 can be formed by both the first AND gate unit and the OR gate unit in order to accurately determine whether the high m bits of the second matrix element are all extended sign bits.

[0101] Alternatively, as shown in Figure 7, the sign bit determination unit 133 may include an XOR gate unit. This XOR gate unit can be composed of one or more XOR gates and can have multiple input terminals. Each input terminal can be configured to receive a corresponding bit to be determined from a second matrix element in the current operation column. The output terminal of the XOR gate unit can be configured to output an indication signal indicating whether the received bits to be determined are all extended sign bits. In a specific example, a corresponding XOR gate unit can be set for a second matrix element. This XOR gate unit may include m+1 input terminals, each used to receive a corresponding bit from the high m+1 bits of the second matrix element, to determine whether the high m bits of the second matrix element are all extended sign bits.

[0102] In other embodiments, the symbol processing subcircuit 130 can be configured to determine the position of the true sign bit of each second matrix element in the current operation column (e.g., the j-th column) of the second matrix, and take the highest true sign bit among all the true sign bits of the second matrix elements in the current operation column as the target sign bit; and set all bits of the second matrix element higher than the target sign bit to zero, and invert the target sign bit of the second matrix element to generate the corresponding first operand. That is, the true sign bit and extended sign bit of each second matrix element in each group of second matrix elements can be determined one by one, so as to maximize the reduction of the number of bits or the adjustment of the sign bits for that group of second matrix elements, thereby reducing the idling of the arithmetic circuit and reducing power consumption.

[0103] In a specific example, suppose M = 8, and the group of eight second matrix elements participating in the DCT8 operation includes: 11110001, 11110101, 11111101, 11110000, 11111001, 11111111, 00000001, 00001001. Then, for each of the above second matrix elements, the high 3 bits, high 3 bits, high 5 bits, high 3 bits, high 4 bits, high 7 bits, and high... The 6th bit and the high 3 bits are the extended sign bits, so the 4th bit (the lowest bit is the 0th bit) of the second matrix element should be used as the target sign bit. The corresponding set of first operands obtained by adjusting the sign bit in the above manner includes: 00000001, 00000101, 00001101, 00000000, 00001001, 00001111, 00010001, 00011001.

[0104] Similarly, to achieve the sign bit adjustment as described above, as shown in FIG4, the sign processing subcircuit 130 may include a sign bit determination unit 133 to determine the position of the true sign bit of each second matrix element in the current operation column of the second matrix. It is understood that the sign bit determination unit 133 may also be formed by a first AND gate, OR gate, or XOR gate. Unlike the previous embodiment, since the sign bit determination unit 133 here needs to determine the position of the true sign bit of each second matrix element in the current operation column of the second matrix, it may include M input terminals, where M is the bit width of the second matrix element, in order to determine the true sign bit of each second matrix element. It is understood that in other embodiments, the sign bit determination unit 133 may be configured in other ways, and this is not limited here.

[0105] As described above, in order to invert the determined target symbol bit, as shown in Figure 4, the symbol processing sub-circuit 130 may include an inverter 131. The input of the inverter 131 can be configured to receive the target symbol bit of the second matrix element to invert the target symbol bit. Alternatively, other units or modules may be used to invert the target symbol bit, which is not limited here.

[0106] Further, as shown in Figure 4, the symbol processing subcircuit 130 may also include a second AND gate unit 132. The two input terminals of the second AND gate unit 132 can be configured to receive a signal zero representing zero and a corresponding unset zero bit for a second matrix element, respectively, to set the unset zero bit to zero, thereby reducing the idling of the arithmetic circuit and reducing power consumption. In a specific example, a corresponding symbol processing subcircuit 130 can be set for a second matrix element. If it is necessary to set all m high bits of the second matrix element to zero, then the symbol processing subcircuit 130 can have m second AND gate units 132. In addition, in the embodiment where the true symbol bit of each second matrix element in each group of second matrix elements is determined one by one, the symbol processing subcircuit 130 can have M-1 second AND gate units 132. The activation or deactivation of each second AND gate unit 132 can be controlled according to the determined target symbol bit to achieve the desired symbol bit adjustment. Alternatively, other units or modules can be used to extend the symbol bit of at least part of the second matrix element to zero, which is not limited here.

[0107] As described above, after generating the first operand in the form of an unsigned number based on the second matrix element, the multiply-accumulate subcircuit 110 can be used to perform at least the calculation of the vector inner product. In some embodiments, the constant Ai1 described above can be incorporated into other operations besides matrix multiplication, so that the multiply-accumulate subcircuit 110 can calculate only the first term in the above formula (5), i.e. Alternatively, in other embodiments, the multiply-accumulate subcircuit 110 can be configured to calculate the sum of the inner product of the first vector and the second vector and a preset constant. In one specific example, the preset constant can be Ai1, which can be determined based on the conversion relationship between the second matrix element associated with the second vector and the corresponding first operand, and the first matrix element associated with the first vector, i.e., the multiply-accumulate subcircuit 110 can calculate the result of the above formula (5). Alternatively, in other specific examples, the preset constant may be other constants associated with Ai1, depending on the specific data processing method, which is not limited here. It is understood that the value of the corresponding preset constant may be different for each third matrix element in the same column of the third matrix Y, so the corresponding preset constant can be set separately in the multiply-accumulate subcircuit 110 used to calculate each third matrix element.

[0108] In some embodiments, the multiply-accumulate subcircuit 110 may include multipliers and adders (or adder trees, subtractors, etc.) to calculate or The value of is taken here. Since the signed number xkj has been converted into the first operand Xkj in the form of an unsigned number, the multiplier in the at least multiply accumulator subcircuit 110 only needs to support the multiplication operation of unsigned numbers, thereby simplifying the structure of the arithmetic circuit and helping to reduce the power consumption of the arithmetic circuit. However, since the coefficient cik may be negative, negative numbers may still be generated in the addition or subtraction operation after the multiplication operation, which requires processing of the sign. In order to further simplify the operation, the known coefficient cik can be decomposed into the following form: cik=∑[(-1) s *2 p (6)

[0109] In other words, cik can be represented as a power of 2 or the sum or subtraction of multiple powers of 2. For simplicity, s can be 0 or 1.

[0110] In a specific example, taking the coefficient matrix C used for DCT8 operations above as an example, where:

[0111] c30=75=0B1001011=(-1) 0 *2 6 +(-1) 0 *2 3 +(-1) 0 *2 1 +(-1) 0 *2 0 That is, in each term, the value of s is 0, while the values ​​of p are 0, 1, 3 and 6 respectively;

[0112] c31 = -18 = (-1) 1 *0B10010=(-1) 1 *2 4 +(-1) 1 *2 1 That is, in each term, the value of s is 1, while the values ​​of p are 1 and 4 respectively;

[0113] c32 = -89 = (-1) 1 *0B1011001=(-1) 1 *2 6 +(-1) 1 *2 4 +(-1) 1 *2 3 +(-1) 1 *2 0 That is, in each term, the value of s is 1, while the values ​​of p are 0, 3, 4 and 6 respectively;

[0114] c33 = -50 = (-1)1 *0B110010 = (-1) 1 *2 5 + (-1) 1 *2 4 + (-1) 1 *2 1 , that is, in each term, the value of s is 1, and the values of p are 1, 4, and 5 respectively.

[0115] Alternatively, some coefficients can have multiple representations. For example, taking the value of the coefficient as 31, it can be represented as (-1) 0 *2 4 + (-1) 0 *2 3 + (-1) 0 *2 2 + (-1) 0 *2 1 + (-1) 0 *2 0 in the form of, or it can also be represented as (-1) 0 *2 5 + (-1) 1 *2 0 in the form of.

[0116] As will be described in detail later, each summation term in the above formula (6) can be associated with a shift of the operand. Therefore, if the number of summation terms can be reduced as much as possible, the number of shifts of the operand can be correspondingly reduced, which helps to simplify the structure of the arithmetic circuit, reduce the arithmetic power consumption, and ensure timing convergence. It can be seen that in the specific example of the coefficient with a value of 31 above, representing it as (-1) 0 *2 5 + (-1) 1 *2 0 for processing is generally more preferable.

[0117] Furthermore, 2 p *Xkj is equivalent to shifting the first operand Xkj in binary form to the left by p bits. It can be seen that if p1 is used to represent any value of p when s = 0, then 2 p1 *Xkj = Xkj << p1; and if p2 is used to represent any value of p when s = 1, then based on the rule of representing negative numbers in two's complement, (-1)*Xkj = ~Xkj + 1, where ~Xkj is the bitwise inversion of Xkj. Then, (-1)*2 p2 *Xkj = 2 p2 *(~Xkj + 1) = (~Xkj << p2) + 2 p2 , where 2 p2This can be extracted as a constant term for subsequent processing. Thus, the above formula (5) can be rewritten as follows:

[0118] Among them, the constant term Ai2 is based on Ai1 and all the involved 2 p2 It has been determined.

[0119] According to formula (7) above, multiplication and accumulation operations can be implemented using shift calculation and accumulation calculation. Accordingly, in some embodiments, as shown in FIG8, the multiplication and accumulation sub-circuit 110 may include a shift addition unit 111. The shift addition unit 111 may be configured to shift the first operand by a preset number of positions in a preset direction when the first matrix element multiplied with the first operand is positive, so as to generate one or more corresponding second operands, wherein the preset direction and the preset number of positions are determined according to the first matrix element multiplied with the first operand. For example, in the DCT8 operation, the coefficient c30 = 75 = (-1). 0 *2 6 +(-1) 0 *2 3 +(-1) 0 *2 1 +(-1) 0 *2 0 For example, the first operand Xkj multiplied by the coefficient can be shifted to the left by 0, 1, 3, and 6 bits respectively, resulting in four second operands: Xkj itself, Xkj<<1, Xkj<<3, and Xkj<<6, for further processing.

[0120] In some embodiments, as shown in FIG8, the multiply-accumulate sub-circuit 110 may further include a bit-by-bit inversion unit 112. The bit-by-bit inversion unit 112 may be configured to invert the first operand bit by bit when the first matrix element multiplied with the first operand is negative, to generate a corresponding third operand, i.e., X3kj = ~Xkj. In some embodiments, the bit-by-bit inversion unit 112 may be formed by multiple inverters. Alternatively, the bit-by-bit inversion unit 112 may be formed in other ways, without limitation. Further, the shift-add unit 111 may also be configured to shift the third operand by a preset number of bits in a preset direction to generate one or more corresponding fourth operands, wherein the preset direction and the preset number of bits are determined according to the first matrix element multiplied with the first operand. The coefficients in the DCT8 operation are c31 = -18 = (-1). 1 *2 4 +(-1) 1 *2 1For example, the first operand Xkj multiplied by the coefficient can be inverted bit by bit by the bit-by-bit inversion unit 112 to generate the corresponding third operand X3kj = ~Xkj. Then, the third operand X3kj can be shifted to the left by 1 bit and 4 bits by the shift addition unit 111 to obtain two fourth operands, namely X3kj<<1 and X3kj<<4, for further processing.

[0121] Furthermore, the shift-add unit 111 can also be configured to calculate the sum of all second or fourth operands generated based on the N first operands, that is, to calculate the sum of the first and second terms in the above formula (7). In addition, in some embodiments, the shift-add unit 111 can also calculate the sum of all three terms in the above formula (7), and also obtain the value of the third matrix element yij. It is understood that for each third matrix element in the same column of the third matrix Y, the value of its corresponding constant term Ai2 may be different, so the corresponding constant term Ai2 can be set in the multiply-accumulate sub-circuit 110 used to calculate each third matrix element.

[0122] It is understandable that since all coefficients in the first matrix C are known in advance, the number and arrangement of shift-adder units 111 and bit-by-bit inversion units 112 in the multiply-accumulate sub-circuit 110 can be determined in advance based on the values ​​of these coefficients, thereby simplifying the design of the arithmetic circuit.

[0123] In some embodiments, the shift-add unit 111 can be implemented by a compression tree. A compression tree can efficiently compress multiple data points into a sum of two or three data points. Furthermore, shift operations on related data can be implemented within the compression tree as needed. Thus, by combining a compression tree with a bit-by-bit inversion unit, shift and addition operations as shown in formula (7) above can be easily implemented, thereby compressing the shifted sum of multiple numbers into a sum of two or three numbers. Common compression trees can include 4:2 compression trees, 3:2 compression trees, etc., which have two outputs, and can also include 5:3 compression trees, 6:3 compression trees, 7:3 compression trees, etc., which have three outputs. The compression tree here can be an existing or future-developed compression tree with any number of inputs and outputs, or a compression tree module with any number of inputs and outputs implemented by combining multiple existing compression trees. For simplicity, in the embodiments of this disclosure, a compression tree with two outputs can be used, and then the two output data of the compression tree can be added by an adder to obtain the operation result related to the third matrix element. In other embodiments, the shift-add unit 111 may also be implemented as a full adder or a combination of a full adder and a half adder.

[0124] In most cases, especially in DCT operations, there are numerous symmetric relationships within the first matrix, or coefficient matrix. These symmetric relationships can be utilized to further simplify the computation. Specifically, multiple second matrix elements multiplied by coefficients with the same absolute value can be pre-added or subtracted to reduce the number of multiplications, additions, subtractions, or shift calculations performed in the multiply-accumulate subcircuit 110. This helps simplify the circuit structure, reduce power consumption, and avoid timing convergence problems caused by multiple cascaded operations. As shown in Figure 9, when at least two first matrix elements with the same absolute value exist in at least one row of the first matrix, the computation circuit may further include a symmetric operation subcircuit 120. This symmetric operation subcircuit 120 can be configured to calculate the sum or difference of second matrix elements or corresponding first operands multiplied by at least two first matrix elements with the same absolute value in the same row of the first matrix. The symmetric operation subcircuit 120 can be positioned before or after the symbol processing subcircuit 130 as needed. Furthermore, considering that converting the operands to be processed in the arithmetic circuit into unsigned numbers as early as possible can simplify subsequent operations, the symmetric arithmetic sub-circuit 120 is generally placed between the sign processing sub-circuit 130 and the multiply-accumulate sub-circuit 110.

[0125] In some embodiments, the symmetric operation sub-circuit 120 may include a single-stage butterfly operation unit or cascaded multi-stage butterfly operation units, wherein each stage of the butterfly operation unit may include multiple adders or subtractors, each adder or subtractor being used to pre-calculate the sum or difference of a pair of second matrix elements or a corresponding pair of first operands. It is understood that the higher the symmetry in the coefficient matrix, the more stages of butterfly operation units can be set up to simplify the calculation as much as possible.

[0126] Taking the DCT8 operation as an example, observing the coefficient matrix of the DCT8 operation as shown above, we can see that the coefficients in the even-numbered rows (i.e., rows 0, 2, 4, and 6) have an even symmetric characteristic, that is, the value of the j-th coefficient is equal to the value of the (7-j)-th coefficient; while the coefficients in the odd-numbered rows (i.e., rows 1, 3, 5, and 7) have an odd symmetric characteristic, that is, the value of the j-th coefficient is the negative of the value of the (7-j)-th coefficient. Based on these characteristics, the sum and difference between the i-th and (7-i)-th first operands corresponding to the i-th and (7-i)-th second matrix elements in the current operation column of the second matrix can be calculated using the four adders and four subtractors in the first-level butterfly operation unit 121 shown in Figure 10. These are X0j+X7j, X1j+X6j, X2j+X5j, X3j+X4j, X3j-X4j, X2j-X5j, X1j-X6j, and X0j-X7j. Furthermore, it can be noted that in the coefficient matrix of the DCT8 operation, for each even-numbered row, the coefficients in each half-row also exhibit even-symmetric or odd-symmetric characteristics. Accordingly, the second-level butterfly operation unit 122 shown in Figure 10 can be used to further calculate the sum and difference of these first operands, specifically including X0j+X7j+X3j+X4j, X1j+X6j+X2j+X5j, X0j+X7j-X3j-X4j and X1j+X6j-X2j-X5j.

[0127] Taking the calculation of the coefficients in the second row of the coefficient matrix as an example, without the symmetric operation sub-circuit 120, the multiply-accumulate sub-circuit 110 used to calculate y2j might need to calculate the values ​​of 83*X0j, 36*X1j, 36*(~X2j), 83*(~X3j), 83*(~X4j), 36*(~X5j), 36*X6j, and 83*X7j respectively, and then combine them with the summation operation to obtain the value associated with the third matrix element y2j; however, with the symmetric operation sub-circuit 120, it can be done through... The symmetric operation sub-circuit 120 first calculates the values ​​of X0j+X7j-X3j-X4j and X1j+X6j-X2j-X5j, and then calculates the values ​​of 83*(X0j+X7j-X3j-X4j) and 36*(X1j+X6j-X2j-X5j) in the multiply-accumulate sub-circuit 110. Combining these values ​​and performing an addition operation yields the value associated with the third matrix element y2j, thereby significantly reducing the number of multiplication operations or shift-addition operations required, which helps to reduce power consumption and ensure timing convergence.

[0128] In some embodiments, as shown in FIG11, the symmetric operation sub-circuit 120 may include an adder 123 and a compression tree 124. The adder 123 can be used to calculate the sum or subtraction of two first operands, while the compression tree 124 can be used to convert the sum or subtraction of four first operands into the form of a sum of two numbers, and the final sum or subtraction result is further obtained through the adder 123. It is understood that in other embodiments, other methods may be used to implement the above-described symmetric operation sub-circuit 120, and no limitations are imposed here.

[0129] This disclosure also provides a processor, as shown in FIG12, which may include the arithmetic circuitry 100 as described above. For example, such a processor 200 may be a neural network processor, a central processing unit, a coprocessor, a digital signal processor, a dedicated instruction processor, or various other processors.

[0130] This disclosure also proposes a computing device, as shown in Figures 13 and 14, which may include the arithmetic circuitry 100 or processor 200 as described above. Examples of the computing device 300 may include, but are not limited to, consumer electronics products, components of consumer electronics products, electronic testing equipment, image processing equipment, cellular communication infrastructure such as base stations, etc. Examples of the computing device 300 may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smartwatches or headphones, telephones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable video cameras, cameras such as digital cameras, portable storage chips, washing machines, dryers, washer / dryer systems, peripheral devices, clocks, etc. Furthermore, the computing device 300 may include incomplete products.

[0131] In the technical solution disclosed herein, by converting signed number operations involved in matrix multiplication into unsigned number operations, the data path in the arithmetic circuit is designed as entirely unsigned numbers, thereby effectively simplifying the structure of the arithmetic circuit, reducing power consumption, and making the timing of the arithmetic circuit easier to converge. Furthermore, by processing at least a portion of the extended sign bits of the operands, the toggle rate of the arithmetic circuit can be effectively reduced, thereby further reducing the power consumption of the arithmetic circuit. In addition, by converting multiply-accumulate operations into shift and addition operations on the operands, the circuit structure can be further simplified. In some examples, based on the symmetry of the coefficient matrix in matrix multiplication, some of the matrix elements involved in the operation can be pre-processed by adding or subtracting, thereby further reducing the number of multiplication operations involved and lowering the computational cost.

[0132] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, enabling embodiments of this disclosure described herein to operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0133] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0134] As used herein, the term “exemplary” means “serving as an example, instance, or illustration” and not as a “model” to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, this disclosure is not limited to any theory expressed or implied as given in the field of art, background art, summary of invention, or detailed description.

[0135] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0136] Furthermore, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0137] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0138] Additionally, when used herein, the terms “here,” “above,” “below,” “below,” “in the preceding text,” and similar terms should refer to the entirety of this application and not any particular part thereof. Furthermore, unless expressly stated otherwise or otherwise understood in the context in which they are used, conditional language used herein, such as “may,” “possibly,” “for example,” “like,” etc., is generally intended to express that certain embodiments include, while other embodiments do not, certain features, elements, and / or states. Therefore, such conditional language is not generally intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0139] In this disclosure, the term "provide" is used broadly to cover all ways of obtaining an object, and therefore "providing an object" includes, but is not limited to, "purchasing," "preparing / manufacturing," "arranging / setting up," "installing / assembling," and / or "ordering" an object. Furthermore, in this disclosure, the terms "circuit," "unit," and "module" are used interchangeably.

[0140] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0141] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in various different ways.

[0142] The various embodiments of this disclosure can be described in a progressive manner, with references made to similar or identical parts between embodiments. Each embodiment focuses on describing the differences from other embodiments. In this disclosure, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this disclosure, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0143] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. An arithmetic circuit for performing an operation of multiplying a first matrix by a second matrix, wherein, The number of columns in the first matrix and the number of rows in the second matrix are each N, and each element of the first matrix is ​​a pre-known coefficient. The computation circuit includes: A symbol processing subcircuit, configured to convert a second matrix element in the second matrix into a corresponding first operand, wherein the first operand is an unsigned number; and A multiply-accumulate subcircuit is provided, the input of which is communicatively connected to the output of the symbol processing subcircuit. The multiply-accumulate subcircuit is configured to compute at least the inner product of a first vector and a second vector, wherein the k-th component of the first vector is the k-th first matrix element in the current operation row of the first matrix, the k-th component of the second vector is the first operand obtained by transforming the k-th second matrix element in the current operation column of the second matrix, and the dimensions of the first vector and the second vector are each N.

2. The operational circuit according to claim 1, wherein, The computational circuit includes N symbol processing sub-circuits, each configured in the same operation cycle to transform a corresponding element of the second matrix in the same column of the second matrix; and / or The computational circuit includes N' multiply-accumulate sub-circuits. In the same operation cycle, each multiply-accumulate sub-circuit is configured to calculate the inner product of a first vector and a second vector associated with a corresponding element of the third matrix in the same column of the third matrix, where N' is the number of rows of the first matrix and the third matrix is ​​the matrix obtained by multiplying the first matrix by the second matrix.

3. The operational circuit according to claim 1, wherein, The symbol processing subcircuit is configured to invert the target symbol bit of the second matrix element to generate the corresponding first operand, wherein the target symbol bit of the second matrix element is the most significant bit of the second matrix element.

4. The operational circuit according to claim 1, wherein, The symbol processing sub-circuit is configured as follows: Determine whether the high m bits of each second matrix element in the current operation column of the second matrix are all extended sign bits, where m is a preset positive integer and m is less than the total number of bits M of the second matrix element; If the high m bits of each second matrix element in the current operand column are extended sign bits, set all high m bits of the second matrix element to zero and invert the target sign bit of the second matrix element to generate the corresponding first operand. The target sign bit of the second matrix element is the lower bit adjacent to the high m bits of that second matrix element, or... If at least one of the high m bits of a second matrix element in the current operand is not an extended sign bit, the target sign bit of the second matrix element is inverted to generate the corresponding first operand, wherein the target sign bit of the second matrix element is the highest bit of the second matrix element.

5. The operational circuit according to claim 1, wherein, The symbol processing sub-circuit is configured as follows: Determine the position of the true sign bit of each second matrix element in the current operation column of the second matrix, and take the highest true sign bit among all the true sign bits of the second matrix elements in the current operation column as the target sign bit; as well as Set all bits of the second matrix element that are higher than the target sign bit to zero, and invert the target sign bit of the second matrix element to generate the corresponding first operand.

6. The operational circuit according to any one of claims 3 to 5, wherein, The symbol processing subcircuit includes an inverter whose input is configured to receive the target symbol bit of the second matrix element to invert the target symbol bit.

7. The operational circuit according to claim 4 or 5, wherein, The symbol processing sub-circuit includes a symbol bit determination unit, which includes: The first AND gate unit has multiple input terminals, each configured to receive a corresponding bit to be determined from a second matrix element in the current operation column, and the output terminal of the first AND gate unit is configured to output an indication signal indicating whether the received multiple bits to be determined are all extended sign bits; or An OR gate unit, having multiple input terminals, each input terminal configured to receive a corresponding bit to be determined from a second matrix element in the current operation column, and the output terminal of the OR gate unit configured to output an indication signal indicating whether the received multiple bits to be determined are all extended sign bits; or An XOR gate unit has multiple input terminals, each input terminal being configured to receive a corresponding bit to be determined from a second matrix element in the current operation column, and the output terminal of the XOR gate unit being configured to output an indication signal indicating whether the multiple bits to be determined received are all extended sign bits.

8. The operational circuit according to claim 4 or 5, wherein, The symbol processing sub-circuit includes a second AND gate unit, the two inputs of which are configured to receive a signal zero representing zero and a corresponding bit to be set to zero for a second matrix element, respectively, so as to set the bit to be set to zero.

9. The operational circuit according to claim 1, wherein, The multiply-accumulate subcircuit includes a shift-add unit, which is configured to: If the first matrix element multiplied with the first operand is positive, the first operand is shifted by a preset number of positions in a preset direction to generate one or more corresponding second operands, wherein the preset direction and the preset number of positions are determined based on the first matrix element multiplied with the first operand.

10. The operational circuit according to claim 9, wherein, The multiply-accumulate sub-circuit further includes a bit-by-bit inversion unit, which is configured to: invert the first operand bit by bit when the first matrix element multiplied with the first operand is negative, so as to generate a corresponding third operand; The shift-add unit is further configured to shift the third operand by a preset number of bits in a preset direction to generate one or more corresponding fourth operands, wherein the preset direction and the preset number of bits are determined based on the first matrix element multiplied by the first operand.

11. The operational circuit according to claim 9 or 10, wherein, The shift-add unit is also configured to: Calculate the sum of all second or fourth operands generated from N first operands.

12. The operational circuit according to claim 9 or 10, wherein, The first matrix element cik multiplied by the first operand Xkj satisfies cik=∑[(-1)] s *2 p In the case of: If s is even, shift the first operand p bits to the left to produce the corresponding second operand; If s is odd, invert the first operand bit by bit to generate the third operand, and shift the third operand p bits to the left to generate the corresponding fourth operand; Wherein, the i-th row is the current operation row of the first matrix, and the j-th column is the current operation column of the second matrix.

13. The operational circuit according to claim 1, wherein, The multiply-accumulate sub-circuit is configured to calculate the sum of the inner product of the first vector and the second vector and a preset constant, wherein the preset constant is determined based on the conversion relationship between the second matrix element associated with the second vector and the corresponding first operand, and the first matrix element associated with the first vector.

14. The operational circuit according to claim 1, wherein, If at least two elements of the first matrix have the same absolute value in at least one row of the first matrix, the arithmetic circuit further includes: A symmetric operation subcircuit, configured to calculate the sum or difference of a second matrix element or a corresponding first operand multiplied by at least two first matrix elements having the same absolute value in the same row of a first matrix.

15. The operational circuit according to claim 14, wherein, The symmetric operation sub-circuit is positioned between the symbol processing sub-circuit and the multiply-accumulate sub-circuit.

16. The operational circuit according to claim 14, wherein, The symmetric operation sub-circuit includes a single-level butterfly operation unit or a cascaded multi-level butterfly operation unit.

17. The operational circuit according to claim 1, wherein, The second matrix is ​​the transpose of the image matrix; or The second matrix is ​​the transpose of the fourth matrix, wherein the fourth matrix is ​​the matrix obtained by multiplying the first matrix by the transpose of the image matrix; Wherein, the matrix element in the image matrix represents the pixel parameter of the pixel at the corresponding position in the image to be processed, or the matrix element in the image matrix represents the difference in pixel parameter of the pixel at the corresponding position in two adjacent frames of the image to be processed.

18. The operational circuit according to claim 1, wherein, The arithmetic circuit is configured to perform discrete cosine transform operations, and the first matrix is ​​a discrete cosine transform coefficient matrix.

19. A processor comprising an arithmetic circuit according to any one of claims 1 to 18.

20. A computing device comprising an arithmetic circuit according to any one of claims 1 to 18 or comprising a processor according to claim 19.

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