Solar cell, solar module, and photovoltaic system

Abstract

The present disclosure is applicable to the technical field of solar cells, and provides a solar cell, a solar module, and a photovoltaic system. The solar cell comprises: a silicon substrate, comprising a first region and a second region, wherein the first region and the second region are located on a same side or two opposite sides of the silicon substrate; a P-type doped polysilicon layer formed at least on the first region; and an N-type doped polysilicon layer formed at least on the second region. Both the P-type doped polysilicon layer and the N-type doped polysilicon layer contain a metal impurity, wherein the metal impurity comprises at least one of iron, copper, cobalt, nickel, and chromium. The N-type doped polysilicon layer comprises a first portion close to the silicon substrate, the P-type doped polysilicon layer comprises a third portion close to the silicon substrate, and the concentration of at least one metal impurity in the first portion is greater than the concentration of the same metal impurity in the third portion. In the solar cell of the present disclosure, the impurity gettering effect of the N-type doped polysilicon layer is better than the impurity gettering effect of the P-type doped polysilicon layer, thereby facilitating prolonging the minority carrier lifetime of the cell and improving the cell efficiency.

Description

A solar cell, a battery module and a photovoltaic system

[0001] Cross-referencing

[0002] This disclosure incorporates, in its entirety, Chinese Patent Application No. 202410940051.6, filed on July 12, 2024, entitled “A Solar Cell, Battery Module and Photovoltaic System”. Technical Field

[0003] This disclosure relates to the field of solar cell technology, specifically to a solar cell, a battery module, and a photovoltaic system. Background Technology

[0004] Solar cells utilize the photovoltaic effect of semiconductors to convert sunlight into electrical energy. Solar cells mainly include bifacial solar cells and back-contact solar cells. Back-contact solar cells, with both positive and negative electrodes located on the back of the cell, completely avoid the shading caused by metal grid lines on the front surface, thus eliminating optical losses and significantly improving cell conversion efficiency, compared to bifacial solar cells.

[0005] In related technologies, metallic impurities such as iron, copper, cobalt, nickel, and chromium in the silicon substrate of solar cells have a significant impact on P-type doped polycrystalline silicon layers but a smaller impact on N-type doped polycrystalline silicon layers. Since existing solar cells typically do not consider the differences in gettering of metallic impurities in the silicon substrate by N-type and P-type doped polycrystalline silicon layers, the removal of metallic impurities from the silicon substrate is poor, which is not conducive to improving the minority carrier lifetime of solar cells, resulting in low cell efficiency. Summary of the Invention

[0006] This disclosure provides a solar cell aimed at solving the problem that related solar cells have poor gettering effect on silicon substrates, which is not conducive to improving minority carrier lifetime and thus results in low cell efficiency.

[0007] This disclosure is implemented by providing a solar cell comprising:

[0008] The silicon substrate includes a first region and a second region, the first region and the second region being located on the same side of the silicon substrate, or the first region and the second region being located on opposite sides of the silicon substrate.

[0009] A P-type doped polysilicon layer is formed at least in the first region;

[0010] An N-type doped polysilicon layer is formed at least in the second region;

[0011] Both the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer contain metal impurities, including at least one of iron, copper, cobalt, nickel, and chromium. The N-type doped polycrystalline silicon layer includes a first part close to the silicon substrate, and the P-type doped polycrystalline silicon layer includes a third part close to the silicon substrate. The concentration of at least one metal impurity in the first part is greater than the concentration of the same metal impurity in the third part.

[0012] In some embodiments, the N-type doped polysilicon layer includes a second portion remote from the silicon substrate, and the P-type doped polysilicon layer includes a fourth portion remote from the silicon substrate, wherein the concentration of at least one metal impurity in the second portion is greater than the concentration of the same metal impurity in the fourth portion.

[0013] In some embodiments, the concentration of at least one metallic impurity in the first part is greater than the concentration of the same metallic impurity in the second part.

[0014] In some embodiments, the concentration of at least one metallic impurity in the third part is greater than the concentration of the same metallic impurity in the fourth part.

[0015] In some embodiments, the concentration of metal impurities in the first portion of the N-type doped polysilicon layer is 0.1 to 100 ppbw.

[0016] In some embodiments, the concentration of metal impurities in the first portion of the N-type doped polysilicon layer is 10 to 100 ppbw.

[0017] In some embodiments, the concentration of metal impurities in the first portion of the N-type doped polysilicon layer is 30–100 ppbw.

[0018] In some embodiments, the concentration of at least one metallic impurity in the first portion is greater than the concentration of the same metallic impurity in the silicon substrate.

[0019] In some embodiments, the concentration ratio of the same metallic impurities in the first part to the third part is 1.5 to 100.

[0020] In some implementations, it also includes:

[0021] The first tunneling layer is disposed between the silicon substrate and the P-type doped polycrystalline silicon layer;

[0022] The second tunneling layer is disposed between the silicon substrate and the N-type doped polysilicon layer;

[0023] The thickness of the second tunneling layer is less than that of the first tunneling layer.

[0024] In some embodiments, the thickness of the second tunneling layer is 0.1 to 0.9 times the thickness of the first tunneling layer.

[0025] In some embodiments, both the second tunneling layer and the first tunneling layer are provided with pores, and the pore density of the second tunneling layer is greater than that of the first tunneling layer.

[0026] In some embodiments, both the second tunneling layer and the first tunneling layer are provided with holes, and the average size of the holes in the second tunneling layer is larger than the average size of the holes in the first tunneling layer.

[0027] In some implementations, the area of ​​the N-type doped polysilicon layer is larger than the area of ​​the P-type doped polysilicon layer.

[0028] In some implementations, the area of ​​the N-type doped polysilicon layer is 1 to 10 times the area of ​​the P-type doped polysilicon layer.

[0029] In some implementations, the thickness of the N-type doped polysilicon layer is greater than the thickness of the P-type doped polysilicon layer.

[0030] In some embodiments, the thickness of the N-type doped polysilicon layer is 1 to 10 times the thickness of the P-type doped polysilicon layer.

[0031] In some embodiments, the solar cell is a back-contact solar cell, with the first region and the second region located on the same side of the silicon substrate.

[0032] In some embodiments, the solar cell is a bifacial solar cell, with the first region and the second region located on opposite sides of the silicon substrate.

[0033] In some embodiments, the silicon substrate includes a first surface and a second surface disposed opposite to the first surface. The first surface is provided with a plurality of first regions and a plurality of third regions, which are alternately disposed in sequence. The second surface is provided with a plurality of second regions and a plurality of fourth regions, which are alternately disposed in sequence. A P-type doped polysilicon layer is disposed on the first region and does not cover the third region. An N-type doped polysilicon layer is disposed on the second region and does not cover the fourth region.

[0034] This disclosure also provides a battery assembly including the solar cell described above.

[0035] This disclosure also provides a photovoltaic system including the aforementioned battery module.

[0036] The present disclosure discloses a solar cell in which the concentration of at least one metal impurity in the first portion of the N-type doped polycrystalline silicon layer near the silicon substrate is greater than the concentration of the same metal impurity in the third portion of the P-type doped polycrystalline silicon layer near the silicon substrate. That is, there are more metal impurities from the silicon substrate entering the first portion of the N-type doped polycrystalline silicon layer than there are metal impurities from the silicon substrate entering the third portion of the P-type doped polycrystalline silicon layer. Therefore, the gettering effect of the N-type doped polycrystalline silicon layer on the silicon substrate is better than that of the P-type doped polycrystalline silicon layer. This can reduce the adverse effects of metal impurities in the silicon substrate on both the N-type and P-type doped polycrystalline silicon layers, and also facilitate the absorption of metal impurities from the silicon substrate by the doped polycrystalline silicon layer, thereby improving the minority carrier lifetime of the cell and thus improving the cell efficiency. Attached Figure Description

[0037] Figure 1 is a schematic diagram of a solar cell provided in Embodiment 1 of this disclosure;

[0038] Figure 2 is a schematic diagram of a solar cell provided in Embodiment 2 of this disclosure.

[0039] Key component symbols: 1. Silicon substrate; 10. Second passivation layer; 11. First surface; 12. Second surface; 111. First region; 112. Third region; 121. Second region; 122. Fourth region; 2. P-type doped polysilicon layer; 21. Third part; 22. Fourth part; 3. N-type doped polysilicon layer; 31. First part; 32. Second part; 4. First tunneling layer; 5. Second tunneling layer; 6. First electrode; 7. Second electrode; 8. Back passivation layer; 9. First passivation layer. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this disclosure.

[0041] In an embodiment of this disclosure, the concentration of at least one metallic impurity in the first portion of the N-type doped polycrystalline silicon layer near the silicon substrate is greater than the concentration of the same metallic impurity in the third portion of the P-type doped polycrystalline silicon layer near the silicon substrate. Specifically, the amount of metallic impurities from the silicon substrate entering the first portion of the N-type doped polycrystalline silicon layer is greater than the amount entering the third portion of the P-type doped polycrystalline silicon layer. Therefore, the gettering effect of the N-type doped polycrystalline silicon layer on the silicon substrate is superior to that of the P-type doped polycrystalline silicon layer. This reduces the adverse effects of metallic impurities in the silicon substrate on both the N-type and P-type doped polycrystalline silicon layers and facilitates the absorption of metallic impurities from the silicon substrate by the doped polycrystalline silicon layer, thereby improving the minority carrier lifetime of the cell and ultimately increasing the cell efficiency.

[0042] Example 1

[0043] Please refer to Figure 1. An embodiment of this disclosure provides a solar cell, including:

[0044] The silicon substrate 1 includes a first region 111 and a second region 121, the first region 111 and the second region 121 being located on the same side of the silicon substrate 1;

[0045] A p-type doped polysilicon layer 2 is formed at least on the first region 111;

[0046] An N-type doped polysilicon layer 3 is formed at least on the second region 121;

[0047] Both the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3 contain metal impurities, including at least one of iron, copper, cobalt, nickel, and chromium. The N-type doped polycrystalline silicon layer 3 includes a first portion 31 close to the silicon substrate 1, and the P-type doped polycrystalline silicon layer 2 includes a third portion 21 close to the silicon substrate 1. The concentration of at least one metal impurity in the first portion 31 is greater than the concentration of the same metal impurity in the third portion 21.

[0048] In this embodiment, the solar cell is a back-contact solar cell. The first region 111 and the second region 121 are located on the same side of the silicon substrate 1, that is, the first region 111 and the second region 121 are located on the back surface of the silicon substrate 1. A P-type doped polycrystalline silicon layer 2 is formed on the first region 111. In some embodiments, the P-type doped polycrystalline silicon layer 2 is provided in a region other than the first region 111. An N-type doped polycrystalline silicon layer 3 is formed on the second region 121; in other embodiments, the N-type doped polycrystalline silicon layer 3 is provided in a region other than the second region 121.

[0049] In this embodiment, the N-type doped polysilicon layer 3 is divided along its thickness direction into a first portion 31 close to the silicon substrate 1 and a second portion 32 far from the silicon substrate 1; the P-type doped polysilicon layer 2 is divided along its thickness direction into a third portion 21 close to the silicon substrate 1 and a fourth portion 22 far from the silicon substrate 1. The dashed line L1 in Figure 1 is only used to distinguish the first portion 31 and the second portion 32 of the N-type doped polysilicon layer 3, and the dashed line L2 is used to distinguish the third portion 21 and the fourth portion 22 of the P-type doped polysilicon layer 2. The dashed lines L1 and L2 in Figure 1 do not actually exist.

[0050] In some embodiments of this disclosure, the first portion 31 and the second portion 32 of the N-type doped polysilicon layer 3 have equal thicknesses; in other embodiments, the first portion 31 and the second portion 32 of the N-type doped polysilicon layer 3 have unequal thicknesses, and the specific thicknesses of the first portion 31 and the second portion 32 are not limited. In some embodiments, the third portion 21 and the fourth portion 22 of the P-type doped polysilicon layer 2 have equal thicknesses; in other embodiments, the third portion 21 and the fourth portion 22 of the P-type doped polysilicon layer 2 have unequal thicknesses, and the specific thicknesses of the third portion 21 and the fourth portion 22 are not limited.

[0051] In this embodiment, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 contain metallic impurities, including at least one of iron, copper, cobalt, nickel, and chromium. The concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the third part 21. This can be understood as follows: compared to the same metallic impurities in the third part 21, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the corresponding same metallic impurity in the third part 21. For example, the concentration of iron in the first part 31 is greater than the concentration of iron in the third part 21; the concentration of copper in the first part 31 is greater than the concentration of copper in the third part 21; the concentration of nickel in the first part 31 is greater than the concentration of nickel in the third part 21. In some embodiments, the concentration of various metallic impurities in the first part 31 is greater than the concentration of the same metallic impurity in the third part 21, that is, the concentration of each metallic impurity in the first part 31 is greater than its concentration in the third part 21.

[0052] In this embodiment of the disclosure, since metal impurities such as iron, copper, cobalt, nickel, and chromium in the silicon substrate 1 have a smaller impact on the N-type doped polycrystalline silicon layer 3 than on the P-type doped polycrystalline silicon layer 2, in some embodiments, the gettering effect on the silicon substrate 1 is improved by increasing the gettering effect of the N-type doped polycrystalline silicon layer 3. That is, the gettering ability of the N-type doped polycrystalline silicon layer 3 on the silicon substrate 1 is greater than that of the P-type doped polycrystalline silicon layer 2. As a result, the concentration of the same metal impurity in the N-type doped polycrystalline silicon layer 3 is greater than that in the P-type doped polycrystalline silicon layer 2. Therefore, the concentration of metal impurities in the first part 31 of the N-type doped polycrystalline silicon layer 3 is greater than that in the third part 21 of the P-type doped polycrystalline silicon layer 2, which is beneficial to improving the minority carrier lifetime of the battery and thus improving the battery efficiency.

[0053] In this embodiment, the gettering effect of the N-type doped polysilicon layer 3 is improved by adjusting the doping concentration, doping diffusion temperature, thickness, or grain size of the N-type doped polysilicon layer 3. This results in the N-type doped polysilicon layer 3 having a better gettering effect than the P-type doped polysilicon layer 2. Consequently, the concentration of metal impurities in the first part 31 of the N-type doped polysilicon layer 3 is greater than the concentration of metal impurities in the third part 21 of the P-type doped polysilicon layer 2. That is, more metal impurities such as iron, copper, cobalt, nickel, and chromium in the silicon substrate 1 enter the N-type doped polysilicon layer 3. This reduces the adverse effects of metal impurities on both the N-type and P-type doped polysilicon layers 3 and facilitates the absorption of metal impurities in the silicon substrate 1 by the doped polysilicon layer, thereby improving the minority carrier lifetime of the battery and ultimately increasing the battery efficiency.

[0054] As some embodiments of this disclosure, the N-type doped polysilicon layer 3 includes a second portion 32 away from the silicon substrate 1; the P-type doped polysilicon layer 2 includes a fourth portion 22 close to the silicon substrate 1; and the concentration of at least one metal impurity in the second portion 32 is greater than the concentration of the same metal impurity in the fourth portion 22.

[0055] In this embodiment, the concentration of at least one metallic impurity in the second part 32 is greater than the concentration of the same metallic impurity in the fourth part 22. This can be understood as meaning that, compared to the same metallic impurities in the fourth part 22, the concentration of at least one metallic impurity in the second part 32 is greater than the concentration of the same metallic impurity in the fourth part 22. For example, the concentration of iron in the second part 32 is greater than the concentration of iron in the fourth part 22; the concentration of copper in the second part 32 is greater than the concentration of copper in the fourth part 22; the concentration of nickel in the second part 32 is greater than the concentration of nickel in the fourth part 22. In some embodiments, the concentration of various metallic impurities in the second part 32 is greater than the concentration of the same metallic impurity in the fourth part 22, that is, the concentration of each metallic impurity in the second part 32 is greater than its concentration in the fourth part 22.

[0056] In this embodiment, since the gettering effect of the N-type doped polysilicon layer 3 is better than that of the P-type doped polysilicon layer 2, the concentration of metal impurities in the second part 32 of the N-type doped polysilicon layer 3 is also greater than that in the fourth part 22 of the P-type doped polysilicon layer 2, which can further improve the gettering effect of the N-type doped polysilicon layer 3.

[0057] As some embodiments of this disclosure, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the second part 32.

[0058] In this embodiment, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the second part 32. This can be understood as the first part 31 having a higher concentration of at least one metallic impurity than the second part 32. For example, the concentration of iron in the first part 31 is greater than the concentration of iron in the second part 32; the concentration of copper in the first part 31 is greater than the concentration of copper in the second part 32; the concentration of nickel in the first part 31 is greater than the concentration of nickel in the second part 32. In some embodiments, the concentration of each metallic impurity in the first part 31 is greater than the concentration of the corresponding same metallic impurity in the second part 32, meaning the concentration of each metallic impurity in the second part 32 is greater than its concentration in the second part 32.

[0059] In this embodiment, since the first part 31 of the N-type doped polysilicon layer 3 is closer to the silicon substrate 1 than the second part 32, the concentration of metal impurities in the first part 31 is greater than the concentration of metal impurities in the second part 32 of the N-type doped polysilicon layer 3.

[0060] As some embodiments of this disclosure, the concentration of at least one metallic impurity in the third part 21 is greater than the concentration of the same metallic impurity in the fourth part 22.

[0061] In this embodiment, the concentration of at least one metallic impurity in the third part 21 is greater than the concentration of the same metallic impurity in the fourth part 22. This can be understood as follows: compared to the same metallic impurities in the fourth part 22, the concentration of at least one metallic impurity in the third part 21 is greater than the concentration of the same metallic impurity in the fourth part 22. For example, the concentration of iron in the third part 21 is greater than the concentration of iron in the fourth part 22; the concentration of copper in the third part 21 is greater than the concentration of copper in the fourth part 22; the concentration of nickel in the third part 21 is greater than the concentration of nickel in the fourth part 22. In some embodiments, the concentration of each metallic impurity in the third part 21 is greater than the concentration of the corresponding same metallic impurity in the fourth part 22, that is, the concentration of each metallic impurity in the third part 21 is greater than the concentration in the fourth part 22.

[0062] In this embodiment, since the third part 21 of the P-type doped polysilicon layer 2 is closer to the silicon substrate 1 than the fourth part 22, the concentration of metal impurities in the third part 21 is greater than the concentration of metal impurities in the fourth part 22.

[0063] As some embodiments of this disclosure, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 0.1 to 100 ppbw.

[0064] In some implementations, the concentration of the metal impurity is specifically obtained by measuring inductively coupled plasma mass spectrometry (ICP-MS).

[0065] In this embodiment, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 0.1–100 PPBW. This can be understood as the concentration of various metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 being 0.1–100 PPBW. Specifically, metal impurities such as iron, copper, cobalt, nickel, and chromium from the silicon substrate 1 enter the N-type doped polysilicon layer 3, and the concentration of these metal impurities within the N-type doped polysilicon layer 3 is 0.1–100 PPBW.

[0066] As some embodiments of this disclosure, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 10 to 100 ppbw.

[0067] In this embodiment, metal impurities such as iron, copper, cobalt, nickel, and chromium in the silicon substrate 1 enter the N-type doped polycrystalline silicon layer 3, and the concentration of metal impurities in the N-type doped polycrystalline silicon layer 3 is 10 to 100 PPBW, which further increases the concentration of metal impurities in the N-type doped polycrystalline silicon layer 3 and enhances the gettering ability of the N-type doped polycrystalline silicon layer 3.

[0068] As some embodiments of this disclosure, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 30 to 100 ppbw.

[0069] In this embodiment, the concentration of metal impurities in the N-type doped polysilicon layer 3 is further increased, thereby further enhancing the gettering ability of the N-type doped polysilicon layer 3.

[0070] As some embodiments of this disclosure, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 1 × 10⁻⁶. 11 ~8×10 13 atoms / cm 3 The concentration of the metal impurities was measured using secondary ion mass spectrometry (SIMS) or other more precise instruments.

[0071] In this embodiment, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 1×10⁻⁶. 11 ~8×10 13 atoms / cm 3 This can be understood as the concentration of various metal impurities in the first part 31 of the N-type doped polycrystalline silicon layer 3 being all within 1×10⁻⁶. 11 ~8×1013 atoms / cm 3 Within the specified range, metallic impurities such as iron, copper, cobalt, nickel, and chromium from the silicon substrate 1 enter the first portion 31 of the N-type doped polycrystalline silicon layer 3, resulting in a concentration of 1 × 10⁻⁶ metallic impurities within the first portion 31 of the N-type doped polycrystalline silicon layer 3. 11 ~8×10 13 atoms / cm 3 .

[0072] As some embodiments of this disclosure, the concentration of metal impurities in the third portion 21 of the P-type doped polysilicon layer 2 is 0.6 × 10⁻⁶. 11 ~5×10 13 atoms / cm 3 The concentration of the metal impurities was measured using secondary ion mass spectrometry (SIMS) or other more precise instruments.

[0073] Among them, metallic impurities such as iron, copper, cobalt, nickel, and chromium in the silicon substrate 1 enter the third part 21 of the P-type doped polycrystalline silicon layer 2, so that the concentration of each metallic impurity in the third part 21 of the P-type doped polycrystalline silicon layer 2 is 0.6 × 10⁻⁶. 11 ~5×10 13 atoms / cm 3 .

[0074] As some embodiments of this disclosure, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the silicon substrate 1.

[0075] In this embodiment, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the silicon substrate 1. This can be understood as the first part 31 having a higher concentration of at least one metallic impurity compared to the silicon substrate 1. For example, the concentration of iron in the first part 31 is greater than the concentration of iron in the silicon substrate 1; the concentration of copper in the first part 31 is greater than the concentration of copper in the silicon substrate 1; and the concentration of nickel in the first part 31 is greater than the concentration of nickel in the silicon substrate 1. In some embodiments, the concentration of various metallic impurities in the first part 31 is greater than the concentration of the corresponding metallic impurity in the silicon substrate 1, meaning that the concentration of each metallic impurity in the first part 31 is greater than its concentration in the silicon substrate 1. In other words, a greater number of metallic impurities in the silicon substrate 1 are absorbed into the N-type doped polycrystalline silicon layer 3, achieving a good gettering effect in the silicon substrate 1.

[0076] As some embodiments of this disclosure, the ratio of the concentrations of the same metallic impurities in the first part 31 to the third part 21 is 1.5 to 100.

[0077] In this embodiment, the concentration ratio of the same metallic impurities in the first part 31 to the third part 21 is 1.5 to 100. This can be understood as the ratio of the concentration of metallic impurities in the first part 31 to the concentration of metallic impurities in the third part 21 being 1.5 to 100. Therefore, the gettering ability of the N-type doped polysilicon layer 3 is 1.5 to 100 times that of the P-type doped polysilicon layer 2, effectively improving the gettering ability of the N-type doped polysilicon layer 3 compared to the P-type doped polysilicon layer 2.

[0078] Furthermore, the ratio of the concentrations of the same metallic impurities in Part 31 to Part 21 is 10 to 100.

[0079] In some embodiments, the concentration ratio of the same metallic impurities in the first part 31 to the third part 21 is 50 to 100.

[0080] As some embodiments of this disclosure, it also includes:

[0081] The first tunneling layer 4 is disposed between the silicon substrate 1 and the P-type doped polycrystalline silicon layer 2;

[0082] The second tunneling layer 5 is disposed between the silicon substrate 1 and the N-type doped polysilicon layer 3;

[0083] The thickness of the second tunneling layer 5 is less than the thickness of the first tunneling layer 4.

[0084] In this embodiment, the first tunneling layer 4 and the second tunneling layer 5 achieve tunneling passivation, which can improve battery efficiency. Since the thickness of the second tunneling layer 5 is smaller than that of the first tunneling layer 4, it is easier for more impurities in the silicon substrate 1 to pass through the second tunneling layer 5 into the N-type doped polycrystalline silicon layer 3, thereby improving the gettering effect.

[0085] As some embodiments of this disclosure, the thickness of the second tunneling layer 5 is 0.1 to 0.9 times the thickness of the first tunneling layer 4.

[0086] In this embodiment, the thickness of the second tunneling layer 5 is 0.1 to 0.9 times the thickness of the first tunneling layer 4. This facilitates the passage of impurities in the silicon substrate 1 through the second tunneling layer 5 into the N-type doped polysilicon layer 3, and also allows the second tunneling layer 5 and the first tunneling layer 4 to maintain good tunneling passivation.

[0087] As some embodiments of this disclosure, both the second tunneling layer 5 and the first tunneling layer 4 are provided with holes, and the hole density of the second tunneling layer 5 is greater than that of the first tunneling layer 4.

[0088] In this embodiment, the pore density of the second tunneling layer 5 is greater than that of the first tunneling layer 4. This can be understood as the number of pores in the second tunneling layer 5 per unit area being greater than the number of pores in the first tunneling layer 4. Because the pore density of the second tunneling layer 5 is less than that of the first tunneling layer 4, it is easier for impurities to pass through the second tunneling layer 5 into the N-type doped polycrystalline silicon layer 3, and this improves the gettering effect of the N-type doped polycrystalline silicon layer 3, thus contributing to improved battery efficiency.

[0089] As some embodiments of this disclosure, both the second tunneling layer 5 and the first tunneling layer 4 are provided with holes, and the average size of the holes in the second tunneling layer 5 is larger than the average size of the holes in the first tunneling layer 4.

[0090] In some embodiments, the pore diameters of the pores in the second tunneling layer 5 are equal, while in other embodiments, the pore diameters of the pores in the second tunneling layer 5 are unequal. Similarly, in some embodiments, the pore diameters of the pores in the first tunneling layer 4 are equal, while in other embodiments, the pore diameters of the pores in the first tunneling layer 4 are unequal. The average pore diameter of the pores in the second tunneling layer 5 can be understood as the average pore diameter of all pores in the second tunneling layer 5; the average pore diameter of the pores in the first tunneling layer 4 can be understood as the average pore diameter of all pores in the first tunneling layer 4. By setting the average pore diameter of the pores in the second tunneling layer 5 to be larger than the average pore diameter of the pores in the first tunneling layer 4, it is beneficial for impurities to pass through the second tunneling layer 5 into the N-type doped polycrystalline silicon layer 3, and it is also beneficial to improve the gettering effect of the N-type doped polycrystalline silicon layer 3, which is conducive to improving the battery efficiency.

[0091] As some embodiments of this disclosure, the area of ​​the N-type doped polysilicon layer 3 is larger than the area of ​​the P-type doped polysilicon layer 2.

[0092] In this embodiment, since the area of ​​the N-type doped polycrystalline silicon layer 3 is larger than that of the P-type doped polycrystalline silicon layer 2, the area covered by the N-type doped polycrystalline silicon layer 3 on the silicon substrate 1 can be increased. This is beneficial for more impurities in the silicon substrate 1 to enter the N-type doped polycrystalline silicon layer 3, thereby improving the gettering effect of the N-type doped polycrystalline silicon layer 3 and improving the battery efficiency.

[0093] As some embodiments of this disclosure, the area of ​​the N-type doped polysilicon layer 3 is 1 to 10 times the area of ​​the P-type doped polysilicon layer 2.

[0094] In this embodiment, the ratio of the area of ​​the N-type doped polysilicon layer 3 to the area of ​​the P-type doped polysilicon layer 2 is: 1.01, 1.5, 2.0, 2.4, 3.0, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.5, 9, 9.5, or 10.

[0095] As some embodiments of this disclosure, the area of ​​the N-type doped polysilicon layer 3 is 3 to 10 times the area of ​​the P-type doped polysilicon layer 2, which can further increase the difference between the area of ​​the N-type doped polysilicon layer 3 and the area of ​​the P-type doped polysilicon layer 2, which is beneficial to improving the gettering effect of the N-type doped polysilicon layer 3.

[0096] As some embodiments of this disclosure, the width of the N-type doped polysilicon layer 3 is greater than the width of the P-type doped polysilicon layer 2.

[0097] In this embodiment, the lengths of the N-type doped polysilicon layer 3 and the P-type doped polysilicon layer 2 are equal, and the width of the N-type doped polysilicon layer 3 is greater than the width of the P-type doped polysilicon layer 2. Therefore, the area of ​​the N-type doped polysilicon layer 3 can be larger than the area of ​​the P-type doped polysilicon layer 2, which can increase the area of ​​the N-type doped polysilicon layer 3 covering the silicon substrate 1. This is beneficial for more impurities in the silicon substrate 1 to enter the N-type doped polysilicon layer 3, thereby improving the gettering effect of the N-type doped polysilicon layer 3 and improving the battery efficiency.

[0098] As some embodiments of this disclosure, the thickness of the N-type doped polysilicon layer 3 is greater than the thickness of the P-type doped polysilicon layer 2.

[0099] In this embodiment, since the thickness of the N-type doped polycrystalline silicon layer 3 is greater than that of the P-type doped polycrystalline silicon layer 2, the volume of the N-type doped polycrystalline silicon layer 3 can be increased, thereby further increasing its gettering capacity. This is beneficial for more impurities in the silicon substrate 1 to enter the N-type doped polycrystalline silicon layer 3, which is conducive to improving the gettering effect of the N-type doped polycrystalline silicon layer 3 and improving the battery efficiency.

[0100] As some embodiments of this disclosure, the thickness of the N-type doped polysilicon layer 3 is 1 to 10 times the thickness of the P-type doped polysilicon layer 2.

[0101] In this embodiment, the ratio of the thickness of the N-type doped polysilicon layer 3 to the thickness of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 10. The ratio of the thickness of the N-type doped polysilicon layer 3 to the thickness of the P-type doped polysilicon layer 2 is: 1.01, or 1.5, or 2.0, or 2.4, or 3.0, or 3.5, or 4, or 4.5, or 5, or 5.5, or 6, or 6.5, or 7, or 7.5, or 8, or 8.5, or 9, or 9.5, or 10.

[0102] In a preferred embodiment of this disclosure, the thickness of the N-type doped polysilicon layer 3 is 3 to 10 times the thickness of the P-type doped polysilicon layer 2, which can further increase the difference between the thickness of the N-type doped polysilicon layer 3 and the thickness of the P-type doped polysilicon layer 2, thereby improving the gettering effect of the N-type doped polysilicon layer 3.

[0103] As some embodiments of this disclosure, it also includes:

[0104] The first electrode 6 is in contact with the P-type doped polycrystalline silicon layer 2.

[0105] The second electrode 7 is in contact with the N-type doped polycrystalline silicon layer 3.

[0106] As some embodiments of this disclosure, it also includes:

[0107] A back passivation layer 8 covers a P-type doped polysilicon layer 2 and an N-type doped polysilicon layer 3. A first electrode 6 passes through the back passivation layer 8 and contacts the P-type doped polysilicon layer 2, and a second electrode 7 passes through the back passivation layer 8 and contacts the N-type doped polysilicon layer 3.

[0108] In this embodiment, the back passivation layer 8 includes at least one or a combination of multiple of the following: an aluminum oxide film layer, a silicon oxide film layer, a silicon nitride film layer, a silicon carbide film layer, and a silicon oxynitride film layer. For example, in some embodiments, the back passivation layer 8 may include an aluminum oxide film layer and a silicon nitride film layer stacked sequentially, and the specific details are not limited here.

[0109] Example 2

[0110] Please refer to Figure 2. An embodiment of this disclosure provides a solar cell, including:

[0111] The silicon substrate 1 includes a first region 111 and a second region 121, which are located on opposite sides of the silicon substrate 1.

[0112] A p-type doped polysilicon layer 2 is formed at least on the first region 111;

[0113] An N-type doped polysilicon layer 3 is formed at least on the second region 121;

[0114] Both the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3 contain metal impurities, including at least one of iron, copper, cobalt, nickel, and chromium. The N-type doped polycrystalline silicon layer 3 includes a first portion 31 close to the silicon substrate 1, and the P-type doped polycrystalline silicon layer 2 includes a third portion 21 close to the silicon substrate 1. The concentration of at least one metal impurity in the first portion 31 is greater than the concentration of the same metal impurity in the third portion 21.

[0115] In this embodiment of the present disclosure, the solar cell is a bifacial solar cell, and the first region 111 and the second region 121 are located on opposite sides of the silicon substrate 1, that is: the first region 111 is located on the light-facing side of the silicon substrate 1 and the second region 121 is located on the back-light side of the silicon substrate 1, or the first region 111 is located on the back-light side of the silicon substrate 1 and the second region 121 is located on the light-facing side of the silicon substrate 1.

[0116] In this embodiment, the N-type doped polysilicon layer 3 is divided along its thickness direction into a first portion 31 close to the silicon substrate 1 and a second portion 32 far from the silicon substrate 1; the P-type doped polysilicon layer 2 is divided along its thickness direction into a third portion 21 close to the silicon substrate 1 and a fourth portion 22 far from the silicon substrate 1. In Figure 2, the dashed line L3 is only used to distinguish the first portion 31 and the second portion 32 of the N-type doped polysilicon layer 3, and the dashed line L4 is used to distinguish the third portion 21 and the fourth portion 22 of the P-type doped polysilicon layer 2. The dashed lines L3 and L4 in Figure 2 do not actually exist.

[0117] In some embodiments, the first portion 31 and the second portion 32 of the N-type doped polysilicon layer 3 have equal thicknesses; in other embodiments, the first portion 31 and the second portion 32 of the N-type doped polysilicon layer 3 have unequal thicknesses, and the specific thicknesses of the first portion 31 and the second portion 32 are not limited. In some embodiments, the third portion 21 and the fourth portion 22 of the P-type doped polysilicon layer 2 have equal thicknesses; in other embodiments, the third portion 21 and the fourth portion 22 of the P-type doped polysilicon layer 2 have unequal thicknesses, and the specific thicknesses of the third portion 21 and the fourth portion 22 are not limited.

[0118] In this embodiment, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 contain metallic impurities, including at least one of iron, copper, cobalt, nickel, and chromium. The concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the third part 21. This can be understood as follows: compared to the same metallic impurities in the third part 21, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the corresponding same metallic impurity in the third part 21. For example, the concentration of iron in the first part 31 is greater than the concentration of iron in the third part 21; the concentration of copper in the first part 31 is greater than the concentration of copper in the third part 21; the concentration of nickel in the first part 31 is greater than the concentration of nickel in the third part 21. In some embodiments, the concentration of various metallic impurities in the first part 31 is greater than the concentration of the same metallic impurity in the third part 21, that is, the concentration of each metallic impurity in the first part 31 is greater than its concentration in the third part 21.

[0119] In this embodiment, since metal impurities such as iron, copper, cobalt, nickel, and chromium in the silicon substrate 1 have a smaller impact on the N-type doped polycrystalline silicon layer 3 than on the P-type doped polycrystalline silicon layer 2, the gettering effect on the silicon substrate 1 can be improved by increasing the gettering effect of the N-type doped polycrystalline silicon layer 3. That is, the gettering ability of the N-type doped polycrystalline silicon layer 3 on the silicon substrate 1 is greater than that of the P-type doped polycrystalline silicon layer. As a result, the concentration of the same metal impurity in the N-type doped polycrystalline silicon layer 3 is greater than that in the P-type doped polycrystalline silicon layer 2. Therefore, the concentration of metal impurities in the first part 31 of the N-type doped polycrystalline silicon layer 3 is greater than that in the third part 21 of the P-type doped polycrystalline silicon layer 2, which is beneficial to improving the minority carrier lifetime of the battery and thus improving the battery efficiency.

[0120] In this embodiment, the gettering effect of the N-type doped polysilicon layer 3 can be improved by adjusting the doping concentration, doping diffusion temperature, thickness, or grain size of the N-type doped polysilicon layer 3. This results in the N-type doped polysilicon layer 3 having a better gettering effect than the P-type doped polysilicon layer 2, making the concentration of metal impurities in the first part 31 of the N-type doped polysilicon layer 3 greater than the concentration of metal impurities in the third part 21 of the P-type doped polysilicon layer 2. In other words, more metal impurities such as iron, copper, cobalt, nickel, and chromium in the silicon substrate 1 enter the N-type doped polysilicon layer 3, which reduces the adverse effects of metal impurities on both the N-type and P-type doped polysilicon layers 3 and facilitates the absorption of metal impurities in the silicon substrate 1 by the doped polysilicon layer, thereby improving the minority carrier lifetime of the battery and increasing the battery efficiency.

[0121] As some embodiments of this disclosure, the silicon substrate 1 includes a first surface 11 and a second surface 12 disposed opposite to the first surface 11. The first surface 11 is provided with a plurality of first regions 111 and a plurality of third regions 112, which are alternately disposed in sequence. The second surface 12 has a plurality of second regions 121 and a plurality of fourth regions 122, which are alternately disposed in sequence. A P-type doped polysilicon layer 2 is disposed on the first regions 111 and does not cover the third regions 112. An N-type doped polysilicon layer 3 is disposed on the second regions 121 and does not cover the fourth regions 122.

[0122] In this embodiment, the first surface 11 and the second surface 12 are respectively the light-facing surface of the solar cell and the back-facing surface of the solar cell.

[0123] In this embodiment, the P-type doped polysilicon layer 2 only covers the first region 111 of the first surface 11 and does not cover the third region 112, and the N-type doped polysilicon layer 3 only covers the second region 121 of the second surface 12 and does not cover the fourth region 122. Since the first surface 11 of the silicon substrate 1 is not completely covered by the P-type doped polysilicon layer 2, and the second surface 12 of the silicon substrate 1 is not completely covered by the N-type doped polysilicon layer 3, the parasitic absorption of light by the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 can be effectively reduced, thereby improving the conversion efficiency.

[0124] In addition to this embodiment, in some embodiments, the first region 111 completely covers the first surface 11, and in other embodiments, the second region 121 completely covers the second surface 12.

[0125] As some embodiments of this disclosure, the sum of the areas of the N-type doped polysilicon layers 3 is greater than the sum of the areas of all the P-type doped polysilicon layers 2.

[0126] The sum of the areas of all the second regions 121 is greater than the sum of the areas of all the first regions 111, which helps to increase the total area of ​​the N-type doped polysilicon layer 3, thereby increasing the gettering ability of the N-type doped polysilicon layer 3 and improving the battery efficiency.

[0127] As some embodiments of this disclosure, the N-type doped polysilicon layer 3 includes a second portion 32 away from the silicon substrate 1; the P-type doped polysilicon layer 2 includes a fourth portion 22 close to the silicon substrate 1; and the concentration of at least one metal impurity in the second portion 32 is greater than the concentration of the same metal impurity in the fourth portion 22.

[0128] In this embodiment, the concentration of at least one metallic impurity in the second part 32 is greater than the concentration of the same metallic impurity in the fourth part 22. This can be understood as meaning that, compared to the same metallic impurities in the fourth part 22, the concentration of at least one metallic impurity in the second part 32 is greater than the concentration of the same metallic impurity in the fourth part 22. For example, the concentration of iron in the second part 32 is greater than the concentration of iron in the fourth part 22; the concentration of copper in the second part 32 is greater than the concentration of copper in the fourth part 22; the concentration of nickel in the second part 32 is greater than the concentration of nickel in the fourth part 22. In some embodiments, the concentration of various metallic impurities in the second part 32 is greater than the concentration of the same metallic impurity in the fourth part 22, that is, the concentration of each metallic impurity in the second part 32 is greater than its concentration in the fourth part 22.

[0129] In this embodiment, since the gettering effect of the N-type doped polysilicon layer 3 is better than that of the P-type doped polysilicon layer 2, the concentration of metal impurities in the second part 32 of the N-type doped polysilicon layer 3 is also greater than that in the fourth part 22 of the P-type doped polysilicon layer 2, which can further improve the gettering effect of the N-type doped polysilicon layer 3.

[0130] As some embodiments of this disclosure, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the second part 32.

[0131] In this embodiment, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the second part 32. This can be understood as the first part 31 having a higher concentration of at least one metallic impurity than the second part 32. For example, the concentration of iron in the first part 31 is greater than the concentration of iron in the second part 32; the concentration of copper in the first part 31 is greater than the concentration of copper in the second part 32; the concentration of nickel in the first part 31 is greater than the concentration of nickel in the second part 32. In some embodiments, the concentration of each metallic impurity in the first part 31 is greater than the concentration of the corresponding same metallic impurity in the second part 32, meaning the concentration of each metallic impurity in the second part 32 is greater than its concentration in the second part 32.

[0132] In this embodiment, since the first part 31 of the N-type doped polysilicon layer 3 is closer to the silicon substrate 1 than the second part 32, the concentration of metal impurities in the first part 31 is greater than the concentration of metal impurities in the second part 32 of the N-type doped polysilicon layer 3.

[0133] As some embodiments of this disclosure, the concentration of at least one metallic impurity in the third part 21 is greater than the concentration of the same metallic impurity in the fourth part 22.

[0134] In this embodiment, the concentration of at least one metallic impurity in the third part 21 is greater than the concentration of the same metallic impurity in the fourth part 22. This can be understood as follows: compared to the same metallic impurities in the fourth part 22, the concentration of at least one metallic impurity in the third part 21 is greater than the concentration of the same metallic impurity in the fourth part 22. For example, the concentration of iron in the third part 21 is greater than the concentration of iron in the fourth part 22; the concentration of copper in the third part 21 is greater than the concentration of copper in the fourth part 22; the concentration of nickel in the third part 21 is greater than the concentration of nickel in the fourth part 22. In some embodiments, the concentration of each metallic impurity in the third part 21 is greater than the concentration of the corresponding same metallic impurity in the fourth part 22, that is, the concentration of each metallic impurity in the third part 21 is greater than the concentration in the fourth part 22.

[0135] In this embodiment, since the third part 21 of the P-type doped polysilicon layer 2 is closer to the silicon substrate 1 than the fourth part 22, the concentration of metal impurities in the third part 21 is greater than the concentration of metal impurities in the fourth part 22.

[0136] As some embodiments of this disclosure, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 0.1 to 100 ppbw.

[0137] In some implementations, the concentration of metallic impurities is obtained by inductively coupled plasma mass spectrometry (ICP-MS).

[0138] In this embodiment, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 0.1–100 PPBW. This can be understood as the concentration of various metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 being 0.1–100 PPBW. Specifically, metal impurities such as iron, copper, cobalt, nickel, and chromium from the silicon substrate 1 enter the N-type doped polysilicon layer 3, and the concentration of these metal impurities within the N-type doped polysilicon layer 3 is 0.1–100 PPBW.

[0139] As some embodiments of this disclosure, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 10 to 100 ppbw.

[0140] In this embodiment, metal impurities such as iron, copper, cobalt, nickel, and chromium in the silicon substrate 1 enter the N-type doped polycrystalline silicon layer 3, and the concentration of metal impurities in the N-type doped polycrystalline silicon layer 3 is 10 to 100 PPBW, which further increases the concentration of metal impurities in the N-type doped polycrystalline silicon layer 3 and enhances the gettering ability of the N-type doped polycrystalline silicon layer 3.

[0141] As some embodiments of this disclosure, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 30 to 100 ppbw.

[0142] In this embodiment, the concentration of metal impurities in the N-type doped polysilicon layer 3 is further increased, thereby further enhancing the gettering ability of the N-type doped polysilicon layer 3.

[0143] As some embodiments of this disclosure, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 1 × 10⁻⁶. 11 ~8×10 13 atoms / cm 3In some embodiments, the concentration of the metal impurity is measured using secondary ion mass spectrometry (SIMS) or other more precise measuring instruments.

[0144] In this embodiment, the concentration of metal impurities in the first portion 31 of the N-type doped polysilicon layer 3 is 1×10⁻⁶. 11 ~8×10 13 atoms / cm 3 This can be understood as the concentration of various metal impurities in the first part 31 of the N-type doped polycrystalline silicon layer 3 being all within 1×10⁻⁶. 11 ~8×10 13 atoms / cm 3 Within the specified range, metallic impurities such as iron, copper, cobalt, nickel, and chromium from the silicon substrate 1 enter the first portion 31 of the N-type doped polycrystalline silicon layer 3, resulting in a concentration of 1 × 10⁻⁶ metallic impurities within the first portion 31 of the N-type doped polycrystalline silicon layer 3. 11 ~8×10 13 atoms / cm 3 .

[0145] As some embodiments of this disclosure, the concentration of metal impurities in the third portion 21 of the P-type doped polysilicon layer 2 is 0.6 × 10⁻⁶. 11 ~5×10 13 atoms / cm 3 In some embodiments, the concentration of the metal impurity is measured using secondary ion mass spectrometry (SIMS) or other more precise measuring instruments.

[0146] Among them, metallic impurities such as iron, copper, cobalt, nickel, and chromium in the silicon substrate 1 enter the third part 21 of the P-type doped polycrystalline silicon layer 2, so that the concentration of each metallic impurity in the third part 21 of the P-type doped polycrystalline silicon layer 2 is 0.6 × 10⁻⁶. 11 ~5×10 13 atoms / cm 3 .

[0147] As some embodiments of this disclosure, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the silicon substrate 1.

[0148] In this embodiment, the concentration of at least one metallic impurity in the first part 31 is greater than the concentration of the same metallic impurity in the silicon substrate 1. This can be understood as the first part 31 having a higher concentration of at least one metallic impurity compared to the silicon substrate 1. For example, the concentration of iron in the first part 31 is greater than the concentration of iron in the silicon substrate 1; the concentration of copper in the first part 31 is greater than the concentration of copper in the silicon substrate 1; and the concentration of nickel in the first part 31 is greater than the concentration of nickel in the silicon substrate 1. In some embodiments, the concentration of various metallic impurities in the first part 31 is greater than the concentration of the corresponding metallic impurity in the silicon substrate 1, meaning that the concentration of each metallic impurity in the first part 31 is greater than its concentration in the silicon substrate 1. In other words, a greater number of metallic impurities in the silicon substrate 1 are absorbed into the N-type doped polycrystalline silicon layer 3, achieving a good gettering effect in the silicon substrate 1.

[0149] As some embodiments of this disclosure, the ratio of the concentrations of the same metallic impurities in the first part 31 to the third part 21 is 1.5 to 100.

[0150] In this embodiment, the concentration ratio of the same metallic impurities in the first part 31 to the third part 21 is 1.5 to 100. This can be understood as the ratio of the concentration of metallic impurities in the first part 31 to the concentration of metallic impurities in the third part 21 being 1.5 to 100. Therefore, the gettering ability of the N-type doped polysilicon layer 3 is 1.5 to 100 times that of the P-type doped polysilicon layer 2, effectively improving the gettering ability of the N-type doped polysilicon layer 3 compared to the P-type doped polysilicon layer 2.

[0151] Furthermore, the ratio of the concentrations of the same metallic impurities in Part 31 to Part 21 is 10 to 100.

[0152] In some embodiments, the concentration ratio of the same metallic impurities in the first part 31 to the third part 21 is 50 to 100.

[0153] As some embodiments of this disclosure, it also includes:

[0154] The first tunneling layer 4 is disposed between the silicon substrate 1 and the P-type doped polycrystalline silicon layer 2;

[0155] The second tunneling layer 5 is disposed between the silicon substrate 1 and the N-type doped polysilicon layer 3;

[0156] The thickness of the second tunneling layer 5 is less than the thickness of the first tunneling layer 4.

[0157] In this embodiment, the first tunneling layer 4 and the second tunneling layer 5 achieve tunneling passivation, which can improve battery efficiency. Since the thickness of the second tunneling layer 5 is smaller than that of the first tunneling layer 4, it is easier for more impurities in the silicon substrate 1 to pass through the second tunneling layer 5 into the N-type doped polycrystalline silicon layer 3, thereby improving the gettering effect.

[0158] As some embodiments of this disclosure, the thickness of the second tunneling layer 5 is 0.1 to 0.9 times the thickness of the first tunneling layer 4.

[0159] In this embodiment, the thickness of the second tunneling layer 5 is 0.1 to 0.9 times the thickness of the first tunneling layer 4. This facilitates the passage of impurities in the silicon substrate 1 through the second tunneling layer 5 into the N-type doped polysilicon layer 3, and also allows the second tunneling layer 5 and the first tunneling layer 4 to maintain good tunneling passivation.

[0160] As some embodiments of this disclosure, both the second tunneling layer 5 and the first tunneling layer 4 are provided with holes, and the hole density of the second tunneling layer 5 is greater than that of the first tunneling layer 4.

[0161] In this embodiment, the pore density of the second tunneling layer 5 is greater than that of the first tunneling layer 4. This can be understood as the number of pores in the second tunneling layer 5 per unit area being greater than the number of pores in the first tunneling layer 4. Because the pore density of the second tunneling layer 5 is less than that of the first tunneling layer 4, it is easier for impurities to pass through the second tunneling layer 5 into the N-type doped polycrystalline silicon layer 3, and this improves the gettering effect of the N-type doped polycrystalline silicon layer 3, thus contributing to improved battery efficiency.

[0162] As some embodiments of this disclosure, both the second tunneling layer 5 and the first tunneling layer 4 are provided with holes, and the average size of the holes in the second tunneling layer 5 is larger than the average size of the holes in the first tunneling layer 4.

[0163] In some embodiments, the pore diameters of the pores in the second tunneling layer 5 are equal, while in other embodiments, the pore diameters of the pores in the second tunneling layer 5 are unequal. Similarly, in some embodiments, the pore diameters of the pores in the first tunneling layer 4 are equal, while in other embodiments, the pore diameters of the pores in the first tunneling layer 4 are unequal. The average pore diameter of the pores in the second tunneling layer 5 can be understood as the average pore diameter of all pores in the second tunneling layer 5; the average pore diameter of the pores in the first tunneling layer 4 can be understood as the average pore diameter of all pores in the first tunneling layer 4. By setting the average pore diameter of the pores in the second tunneling layer 5 to be larger than the average pore diameter of the pores in the first tunneling layer 4, it is beneficial for impurities to pass through the second tunneling layer 5 into the N-type doped polycrystalline silicon layer 3, and it is also beneficial to improve the gettering effect of the N-type doped polycrystalline silicon layer 3, which is conducive to improving the battery efficiency.

[0164] As some embodiments of this disclosure, the area of ​​the N-type doped polysilicon layer 3 is larger than the area of ​​the P-type doped polysilicon layer 2.

[0165] In this embodiment, since the area of ​​the N-type doped polycrystalline silicon layer 3 is larger than that of the P-type doped polycrystalline silicon layer 2, the area covered by the N-type doped polycrystalline silicon layer 3 on the silicon substrate 1 can be increased. This is beneficial for more impurities in the silicon substrate 1 to pass through into the N-type doped polycrystalline silicon layer 3, thereby improving the gettering effect of the N-type doped polycrystalline silicon layer 3 and improving the battery efficiency.

[0166] As some embodiments of this disclosure, the area of ​​the N-type doped polysilicon layer 3 is 1 to 10 times the area of ​​the P-type doped polysilicon layer 2.

[0167] In this embodiment, the area of ​​the N-type doped polysilicon layer 3 is the total area of ​​all N-type doped polysilicon layers 3; the area of ​​the P-type doped polysilicon layer 2 is the total area of ​​all P-type doped polysilicon layers 2. In other embodiments, the area of ​​the N-type doped polysilicon layer 3 is the area of ​​a single N-type doped polysilicon layer 3, and the area of ​​the P-type doped polysilicon layer 2 is the area of ​​a single P-type doped polysilicon layer 2.

[0168] In some embodiments, the ratio of the area of ​​the N-type doped polysilicon layer 3 to the area of ​​the P-type doped polysilicon layer 2 is: 1.01, or 1.5, or 2.0, or 2.4, or 3.0, or 3.5, or 4, or 4.5, or 5, or 5.5, or 6, or 6.5, or 7, or 7.5, or 8, or 8.5, or 9, or 9.5, or 10.

[0169] In a preferred embodiment of this disclosure, the area of ​​the N-type doped polysilicon layer 3 is 3 to 10 times the area of ​​the P-type doped polysilicon layer 2, which can further increase the difference between the area of ​​the N-type doped polysilicon layer 3 and the area of ​​the P-type doped polysilicon layer 2, and is beneficial to improving the gettering effect of the N-type doped polysilicon layer 3.

[0170] As some embodiments of this disclosure, the width of the N-type doped polysilicon layer 3 is greater than the width of the P-type doped polysilicon layer 2.

[0171] In this embodiment, the length of each N-type doped polysilicon layer 3 is equal to that of each P-type doped polysilicon layer 2, and the width of each N-type doped polysilicon layer 3 is greater than the width of each P-type doped polysilicon layer 2. Therefore, the area of ​​the N-type doped polysilicon layer 3 can be larger than the area of ​​the P-type doped polysilicon layer 2, which can increase the area of ​​the silicon substrate 1 covered by the N-type doped polysilicon layer 3. This is beneficial for more impurities in the silicon substrate 1 to pass through into the N-type doped polysilicon layer 3, thereby improving the gettering effect of the N-type doped polysilicon layer 3 and improving the battery efficiency.

[0172] As some embodiments of this disclosure, the thickness of the N-type doped polysilicon layer 3 is greater than the thickness of the P-type doped polysilicon layer 2.

[0173] In this embodiment, the thickness of each N-type doped polysilicon layer 3 is equal, and the thickness of each P-type doped polysilicon layer 2 is equal. Since the thickness of the N-type doped polysilicon layer 3 is greater than the thickness of the P-type doped polysilicon layer 2, the total volume of the N-type doped polysilicon layer 3 can be increased, thereby further increasing its gettering capacity. This facilitates the entry of more impurities from the silicon substrate 1 into the N-type doped polysilicon layer 3, improving the gettering effect of the N-type doped polysilicon layer 3 and ultimately enhancing battery efficiency.

[0174] As some embodiments of this disclosure, the thickness of the N-type doped polysilicon layer 3 is 1 to 10 times the thickness of the P-type doped polysilicon layer 2.

[0175] In this embodiment, the ratio of the thickness of the N-type doped polysilicon layer 3 to the thickness of the P-type doped polysilicon layer 2 is: 1.01, 1.5, 2.0, 2.4, 3.0, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.5, 9, 9.5, or 10.

[0176] In a preferred embodiment of this disclosure, the thickness of the N-type doped polysilicon layer 3 is 3 to 10 times the thickness of the P-type doped polysilicon layer 2, which can further increase the difference between the thickness of the N-type doped polysilicon layer 3 and the thickness of the P-type doped polysilicon layer 2, thereby improving the gettering effect of the N-type doped polysilicon layer 3.

[0177] As some embodiments of this disclosure, the volume of each N-type doped polysilicon layer 3 is larger than the volume of each P-type doped polysilicon layer 2, which is beneficial to increasing the total volume of the N-type doped polysilicon layer 3, thereby increasing the gettering ability of the N-type doped polysilicon layer 3 and improving battery efficiency.

[0178] As some embodiments of this disclosure, it also includes:

[0179] The first electrode 6 is in contact with the P-type doped polycrystalline silicon layer 2.

[0180] The second electrode 7 is in contact with the N-type doped polycrystalline silicon layer 3.

[0181] As some embodiments of this disclosure, it also includes:

[0182] A first passivation layer 9 covers the P-type doped polysilicon layer 2, and the first electrode 6 passes through the first passivation layer 9 to contact the P-type doped polysilicon layer 2.

[0183] A second passivation layer 10 covers the N-type doped polysilicon layer 3, and the second electrode 7 passes through the second passivation layer 10 to contact the N-type doped polysilicon layer 3.

[0184] In this embodiment, both the first passivation layer 9 and the second passivation layer 10 may include at least one or a combination of multiple of the following: aluminum oxide film, silicon oxide film, silicon nitride film, silicon carbide film, and silicon oxynitride film. For example, in some embodiments, the first passivation layer 9 and the second passivation layer 10 may include aluminum oxide film and silicon nitride film stacked sequentially, and no specific limitation is made here.

[0185] Example 3

[0186] This disclosure also provides a battery module, which includes the solar cell of Embodiment 1 or Embodiment 2 described above. It should be noted that this battery module has the same or similar beneficial effects as the solar cell, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0187] Example 4

[0188] This disclosure also provides a photovoltaic system, which includes the battery module of Embodiment 3 described above. It should be noted that this photovoltaic system has the same or similar beneficial effects as a solar cell, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0189] In an embodiment of this disclosure, the concentration of at least one metallic impurity in the first portion of the N-type doped polycrystalline silicon layer near the silicon substrate is greater than the concentration of the same metallic impurity in the third portion of the P-type doped polycrystalline silicon layer near the silicon substrate. Specifically, the amount of metallic impurities from the silicon substrate entering the first portion of the N-type doped polycrystalline silicon layer is greater than the amount entering the third portion of the P-type doped polycrystalline silicon layer. Therefore, the gettering effect of the N-type doped polycrystalline silicon layer on the silicon substrate is superior to that of the P-type doped polycrystalline silicon layer. This reduces the adverse effects of metallic impurities in the silicon substrate on both the N-type and P-type doped polycrystalline silicon layers and facilitates the absorption of metallic impurities from the silicon substrate by the doped polycrystalline silicon layer, thereby improving the minority carrier lifetime of the cell and ultimately increasing the cell efficiency.

[0190] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A solar cell, comprising: A silicon substrate, the silicon substrate including a first region and a second region, the first region and the second region being located on the same side of the silicon substrate, or the first region and the second region being located on opposite sides of the silicon substrate; A P-type doped polysilicon layer is formed at least in the first region; An N-type doped polysilicon layer is formed at least in the second region; Both the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer contain metal impurities, including at least one of iron, copper, cobalt, nickel, and chromium. The N-type doped polycrystalline silicon layer includes a first portion close to the silicon substrate, and the P-type doped polycrystalline silicon layer includes a third portion close to the silicon substrate. The concentration of at least one of the metal impurities in the first portion is greater than the concentration of the same metal impurity in the third portion.

2. The solar cell according to claim 1, wherein, The N-type doped polysilicon layer includes a second portion remote from the silicon substrate, and the P-type doped polysilicon layer includes a fourth portion remote from the silicon substrate, wherein the concentration of at least one of the metal impurities in the second portion is greater than the concentration of the same metal impurity in the fourth portion.

3. The solar cell according to claim 2, wherein, The concentration of at least one of the metallic impurities in the first part is greater than the concentration of the same metallic impurity in the second part.

4. The solar cell according to claim 2, wherein, The concentration of at least one of the metallic impurities in the third part is greater than the concentration of the same metallic impurity in the fourth part.

5. The solar cell according to claim 1, wherein, The concentration of the metal impurities in the first portion of the N-type doped polysilicon layer is 0.1 to 100 ppbw.

6. The solar cell according to claim 1, wherein, The concentration of the metal impurities in the first portion of the N-type doped polysilicon layer is 10 to 100 ppbw.

7. The solar cell according to claim 1, wherein, The concentration of the metal impurities in the first portion of the N-type doped polysilicon layer is 30–100 ppbw.

8. The solar cell according to claim 1, wherein, The concentration of at least one of the metal impurities in the first portion is greater than the concentration of the same metal impurity in the silicon substrate.

9. The solar cell according to claim 1, wherein, The ratio of the concentration of the same metallic impurities in the first part to that in the third part is 1.5 to 100.

10. The solar cell according to claim 1, wherein, Also includes: A first tunneling layer is disposed between the silicon substrate and the P-type doped polysilicon layer; A second tunneling layer is disposed between the silicon substrate and the N-type doped polysilicon layer; The thickness of the second tunneling layer is less than the thickness of the first tunneling layer.

11. The solar cell according to claim 10, wherein, The thickness of the second tunneling layer is 0.1 to 0.9 times the thickness of the first tunneling layer.

12. The solar cell according to claim 10, wherein, Both the second tunneling layer and the first tunneling layer have pores, and the pore density of the second tunneling layer is greater than that of the first tunneling layer.

13. The solar cell according to claim 10, wherein, Both the second tunneling layer and the first tunneling layer have holes, and the average size of the holes in the second tunneling layer is larger than the average size of the holes in the first tunneling layer.

14. The solar cell according to claim 1, wherein, The area of ​​the N-type doped polycrystalline silicon layer is larger than the area of ​​the P-type doped polycrystalline silicon layer.

15. The solar cell according to claim 1, wherein, The area of ​​the N-type doped polysilicon layer is 1 to 10 times the area of ​​the P-type doped polysilicon layer.

16. The solar cell according to claim 1, wherein, The thickness of the N-type doped polycrystalline silicon layer is greater than the thickness of the P-type doped polycrystalline silicon layer.

17. The solar cell according to claim 1, wherein, The thickness of the N-type doped polysilicon layer is 1 to 10 times the thickness of the P-type doped polysilicon layer.

18. The solar cell according to claim 1, wherein, The solar cell is a back-contact solar cell, and the first region and the second region are located on the same side of the silicon substrate.

19. The solar cell according to claim 1, wherein, The solar cell is a bifacial solar cell, with the first region and the second region located on opposite sides of the silicon substrate.

20. The solar cell according to claim 19, wherein, The silicon substrate includes a first surface and a second surface disposed opposite to the first surface. The first surface is provided with a plurality of first regions and a plurality of third regions, which are alternately arranged in sequence. The second surface is provided with a plurality of second regions and a plurality of fourth regions, which are alternately arranged in sequence. The P-type doped polycrystalline silicon layer is disposed on the first region and does not cover the third region. The N-type doped polycrystalline silicon layer is disposed on the second region and does not cover the fourth region.

21. A battery assembly comprising a solar cell as described in any one of claims 1 to 20.

22. A photovoltaic system comprising the battery module as described in claim 21.

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