Coding method and communication apparatus

Abstract

The present application provides a coding method and a communication apparatus. A sub-matrix of a core check region of a base graph of LDPC is designed, such that the sub-matrix of the core check region meets certain characteristics, and the minimum cycle length of the base graph corresponding to the core check region can be increased to the maximum value, thereby preventing the problem whereby when a core check sub-matrix of a base graph uses an IRA structure, numerous small-scale trapping sets are present and error floors are likely to occur at a plurality of lifting values. In addition, for the design of a core check sub-matrix, a corresponding coding method is further provided, so as to reduce the coding complexity when the core check sub-matrix provided in the present application is applied to coding.

Description

Encoding methods and communication devices

[0001] This application claims priority to Chinese Patent Application No. 202410938808.8, filed on July 12, 2024, entitled "Method and Communication Apparatus for Encoding", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of channel coding technology, and more specifically, to a coding method and a communication apparatus. Background Technology

[0003] Low-density parity-check (LDPC) codes are channel coding schemes that closely approximate the Shannon limit, offering advantages such as high performance and low complexity. Mainstream LDPCs employ a quasi-cyclic (QC) structure, avoiding short-cycle loops and improving code distance by adjusting the shift of each block. In fifth-generation (5G) systems, the LDPC base graph (BG) consists of BG1 and BG2, both sharing a common matrix structure that includes a high-rate core parity submatrix. In one existing implementation, the core parity submatrix can utilize an irregular repeat-accumulate (IRA) structure. The IRA structure is a double-diagonal design. The shift value design in the double-diagonal structure of the IRA code allows for simplified encoding. Specifically, all parity equations are XORed to obtain the parity bits for the three columns, and then the parity bits for other columns are determined sequentially based on the currently obtained parity bits until all parity bits are obtained.

[0004] While IRA structures are easy to encode, they generate trap sets. In ultra-reliable low-latency communications (URLLC) scenarios, LDPC requires very high reliability and cannot have significant error floors. However, the unique shift value characteristics of IRAs result in numerous small trap sets (TSs) at each lift value, easily leading to error floors. Furthermore, these trap sets do not change with increasing lift values. Eliminating or reducing trap sets at each lift value in the IRA structure is crucial for improving decoding performance. Therefore, how to avoid trap sets at each lift value in the IRA structure is an urgent problem to be solved. Summary of the Invention

[0005] This application provides an encoding method and a communication device that can maximize the minimum circle length of the base map corresponding to the core check region, thereby avoiding trap sets and improving decoding performance.

[0006] Firstly, an encoding method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, chip system, integrated circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). The method may include: obtaining a base matrix and a boost value L, wherein the base matrix includes a first submatrix corresponding to a core check region, the first submatrix being an n-order square matrix, the first submatrix including at least one column with a column weight of 3, the three shift values ​​corresponding to the column with a column weight of 3 being different, all shift values ​​in the first submatrix being integer multiples of M, n being an integer greater than 2, L = M × N, and M and N being positive integers greater than 2; and encoding the information bit sequence corresponding to the core check region based on the base matrix and the boost value L.

[0007] In the technical solution of this application, the submatrix corresponding to the core parity region of the base matrix is ​​designed to meet certain characteristics. Specifically, it includes at least one triple column, where the three translation values ​​corresponding to the triple column are different, and all translation values ​​in the first submatrix are integer multiples of M, where M is a non-true factor of the boost value L. This design increases the minimum circle length of the base graph corresponding to the core parity region, reaching its maximum value, thereby eliminating or reducing trap sets and improving decoding performance.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the encoding of the information bit sequence corresponding to the core check region based on the base matrix and the boost value L includes: determining a check matrix of dimension (n×L)×(n×L) according to two product factors M and N of the base matrix and the boost value L, wherein the check matrix includes M independent full-rank submatrices of dimension (n×N)×(n×N); and encoding the information bit sequence corresponding to the core check region based on the check matrix.

[0009] In this implementation, by decomposing the lift value L into two product factors M and N, and by ensuring that the translation value of the submatrix corresponding to the core check region satisfies a certain relationship with M, the encoding of the large-dimensional check matrix can be transformed into the independent encoding of M small-dimensional matrices, thereby reducing the encoding complexity.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the check matrix includes M independent full-rank sub-matrices of dimension (n×N)×(n×N), comprising: the M full-rank sub-matrices corresponding to M sets of check equations, each set of check equations including n×N check equations, the coefficients of the n×N check equations contained in each set of check equations forming a sub-matrix in the M full-rank sub-matrices, the n×N check equations of each set of check equations corresponding to solutions of n×N unknowns, the M sets of check equations collectively corresponding to solutions of n×N×M unknowns, and the solutions of the n×N×M unknowns being the n×L check bits corresponding to the check matrix.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, any one of the M sets of check equations M q The following operation is performed to obtain q, which is a value in [0,1,2,…,M-1]: the column position i after the expansion of the core check column in the base graph corresponding to the base matrix is ​​i = M×[0,1,2,…,N-1]+q, and is substituted into the check equation corresponding to each row in the n rows. Each row of the n rows yields N check equations, and the n×N check equations obtained from the n rows form a set of check equations. When q traverses all values ​​in [0,1,2,…,M-1], the M sets of check equations are obtained; wherein, each of the n rows of the first submatrix corresponds to a check equation, and the check equation of the j-th row of the n rows satisfies the following check relationship: the input information corresponding to the j-th row is XORed to obtain the input of the j-th row, 0≤j≤n-1, where j is an integer.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, any column in the first submatrix, after being added to or subtracted by the same offset, is an integer multiple of M.

[0013] In this implementation, for any column, all translation values ​​of that column, after being added to or subtracted from the same offset, are integer multiples of M.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the first submatrix conforms to the first structure, the first column of the first submatrix of the first structure has a column weight of 3, the remaining columns of the first submatrix of the first structure have a column weight of 2, one of the three translation values ​​corresponding to the first column has a translation value of zero, and the two translation values ​​corresponding to any one of the remaining columns are the same.

[0015] In this implementation, the submatrix corresponding to the core parity region (i.e., the first submatrix) has certain characteristics that differ from the IRA structure. The structural changes and shift values ​​of the submatrix corresponding to the core parity region, compared to the IRA structure, can eliminate or reduce the trap set, allowing the minimum circle length of the base graph corresponding to the core parity region to reach its maximum value, thereby improving decoding performance.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the two non-zero translation values ​​of the first column of the first submatrix of the first structure are the last two positions of the first column.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the first submatrix of the first structure is a 4th or 3rd order square matrix.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, each of the M sets of check equations includes N check equations, and the N check equations of each set of check equations correspond to the solutions of N unknowns. The M sets of check equations correspond to a total of N×M solutions of unknowns, and the solutions of the N×M unknowns are the L check bits corresponding to the check matrix.

[0019] In this implementation, the submatrix corresponding to the core verification region (i.e., the first submatrix) not only satisfies the characteristics of the translation values ​​of the three columns mentioned above, but also, under the condition that it conforms to the first structure, can further reduce the coding complexity.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, N is the smallest divisor among all divisors of the lift value L that can reach the maximum value of the minimum circle length of the base graph corresponding to the first submatrix.

[0021] It should be understood that in this application, the base map corresponding to the first submatrix refers to the part of a complete base map that corresponds to the core verification region.

[0022] In this implementation, when choosing the two product factors M and N for the lift value L, N is chosen as the smallest divisor of the minimum circle length of the base graph corresponding to the first submatrix, which can minimize the coding complexity.

[0023] Secondly, a communication device is provided, which has the function of implementing the method of the first aspect or any possible implementation thereof. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0024] Thirdly, this application provides a communication device including at least one processor coupled to at least one memory for storing computer programs or instructions, and the at least one processor for calling and running the computer programs or instructions from the at least one memory, causing the communication device to perform the methods of the first aspect or any possible implementation thereof.

[0025] Fourthly, this application provides a communication device, including a communication interface and a circuit. The communication interface is used to acquire a base matrix and a boost value L, and input the base matrix and the boost value L to the circuit. The circuit performs a method as described in the first aspect or any possible implementation thereof to encode a core check region of an information bit sequence based on the base matrix and the boost value L. Optionally, the communication interface is also used to output the encoded codeword.

[0026] In one example, the communication device described in the second to fourth aspects can be an encoding device, such as an encoder.

[0027] Optionally, the communication device described in the second to fourth aspects can be a chip. As an example, the chip can be a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip containing a modem, or a system-in-package (SIP) chip, etc., without limitation.

[0028] Fifthly, this application provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented.

[0029] In a sixth aspect, this application provides a computer program product comprising computer code or instructions that, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented.

[0030] A seventh aspect provides a wireless communication system, including a communication device as described in any one of the second to fourth aspects. Attached Figure Description

[0031] Figure 1 is a schematic diagram of the base matrix structure of 5G LDPC.

[0032] Figure 2 is a schematic diagram of the incremental redundancy region of the basis matrix of LDPC.

[0033] Figure 3 shows schematic diagrams of IRA structures of different sizes.

[0034] Figure 4 shows an example of an IRA structure generating a trap set.

[0035] Figure 5 shows an example of a communication system applicable to the technical solution of this application.

[0036] Figure 6 is a schematic diagram of the basic process of wireless communication.

[0037] Figure 7 is a schematic flowchart of the encoding method provided in this application.

[0038] Figure 8 is an example of a verification matrix provided according to an embodiment of this application.

[0039] Figure 9 is a schematic structural diagram of the communication device 1000 provided in this application.

[0040] Figure 10 is a schematic block diagram of another communication device 1100 provided in this application.

[0041] Figure 11 is a schematic diagram of the chip (or chip system) provided in this application. Detailed Implementation

[0042] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0043] Low-density parity-check (LDPC) codes are channel coding schemes very close to the Shannon limit and have been selected as the data channel coding scheme for the fifth generation (5G) system. The quasi-cyclic LDPC (QC-LDPC) actually used is represented by a base graph (BG). Elements in the BG are either 0 or 1. The 1s in the BG are expanded into a cyclic shift matrix, and the 0s are expanded into a zero matrix of the corresponding size. After expansion, the parity-check matrix is ​​obtained. There are two base graphs (BGs) for 5G LDPC: BG1 and BG2, which share a common matrix structure, as shown in Figure 1.

[0044] Figure 1 is a schematic diagram of the base matrix structure of 5G LDPC. The base matrix includes: part A, corresponding to the information column region of high code rate; part B, corresponding to the core check region of high code rate; part C, the all-zero region; part D, the incremental redundancy region corresponding to the low code rate matrix; and part E, corresponding to the raptor-like region.

[0045] Figure 2 is a schematic diagram of the incremental redundancy region of the LDPC base matrix. As shown in Figure 2, region E adopts a Raptor-like structure, which can be progressively expanded to a low code rate from a high code rate core matrix. Within region E, the row weight (the number of 1s in each row) is equal to 1, and the column weight (the number of 1s in each column) is equal to 1. In other words, region E is an identity matrix, or can be transformed into an identity matrix through row and column permutations. The advantage of this is that the parity check position of any row in E can be encoded quickly.

[0046] The BG graph model of the QC-LDPC code is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the check equation, F is the edge relationship, and the expansion factor is Z. c After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is its edge relationship, corresponding to the number of columns in the check matrix N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c |Y|, the number of non-zero elements in the parity check matrix is ​​|E|=Z|F|. BG can also be written in matrix form H. BG Based on the basis matrix and the lifting value Z c (Lifting size) can expand the basis matrix into a complete parity-check matrix for encoding or decoding. c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size. The lifting process involves lifting the elements of the basis matrix to a value of Z. c ×Z c The basis matrix is ​​a square matrix. The elements in the basis matrix take values ​​of 0 and 1. A value of 0 represents an empty element, and a value of 1 represents an edge in the basis graph, or an association between a corresponding check and a variable. Element 0 in the basis matrix is ​​promoted to Z. c ×Z c The 0 matrix is ​​promoted to an identity matrix by its element 1, and then cyclically shifted based on the shifting value (SV) corresponding to 1. This cyclic shift can be to the left or right, which is not limited in this application. Each element 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, and 3, and the shift is to the right, the resulting cyclically shifted matrix is ​​as follows:

[0047] If the translation value is 0, the corresponding cyclically shifted matrix is:

[0048] If the shift value is 1, the corresponding cyclically shifted matrix is:

[0049] If the shift value is 3, the corresponding cyclically shifted matrix is:

[0050] In one known implementation, part B of the base graph can adopt an irregular repeat-accumulate (IRA) structure. The IRA structure is characterized by unequal degrees of variable nodes or check nodes, and is a double-diagonal design.

[0051] Figure 3 shows schematic diagrams of IRA structures of different sizes. As shown in Figure 3, the main feature of the IRA structure is that it includes a double-diagonal structure and one triple column. The degree distribution consists of one triple column and the rest are double columns. In the IRA structure with QC structure, the two shift values ​​of the double column are the same, and two of the three lift values ​​of the triple column are the same (let's say 1), and the other shift value is different (let's say 0). The special property of the shift values ​​in the IRA structure ensures that it can be encoded in a simple way. The specific process is to XOR all the parity check equations to obtain the bit value of the parity check node corresponding to the triple column, and then obtain the bit value of the new parity check node according to the bit value of the currently obtained parity check bit, until the bit values ​​of all parity check nodes are obtained.

[0052] While IRAs are easy to encode, they can generate trap sets. In ultra-reliable low latency communications (URLLC) scenarios, LDPC requires very high reliability and cannot have obvious error layers. The special characteristics of the shift values ​​of the IRA structure cause it to form a large number of very small trap sets at each shift value, which is prone to error layers.

[0053] Trap sets are an important concept in communication coding, especially in LDPC research. A trap set is a set of non-empty variable nodes that have not been correctly decoded after a finite number of iterations by an iterative decoder. A (a,b) trap set corresponds to a Tanner-derived subgraph containing a variable nodes and b neighbor check nodes of odd degree. The size of the trap set is defined as the number of variable nodes in the trap set, i.e., a. An error floor refers to a level where, after the signal-to-noise ratio (SNR) increases to a certain extent, the bit error rate (BER) no longer decreases significantly with further increases in SNR, but rather tends to stabilize. This stable BER level is called the error floor.

[0054] Figure 4 shows an example of an IRA structure generating a trap set. As shown in Figure 4, the first row corresponds to four variable nodes (position indices starting from 1, labeled 1, 6, 11, 16 respectively). This row indicates whether the corresponding variable nodes are correct. The "wrong bits" in Figure 4 represent the assumption that all four variable nodes are wrong. If all four variable nodes are wrong, when verifying them, in the first row of the verification matrix, the first and sixth variable nodes are wrong, and this row cannot detect two wrong variable nodes, thus satisfying the verification. In the sixth row of the verification matrix, the sixth and eleventh variable nodes are wrong, and no error is detected, thus also satisfying the verification. Similarly, in the eleventh row of the verification matrix, three variable nodes are involved in the verification, but the eleventh and sixteenth variable nodes are wrong; in the sixteenth row, the first and sixteenth variable nodes are involved in the verification. Since both variable nodes involved in the verification are wrong, the verification relationship is satisfied. In row 15 of the parity check matrix, because three variable nodes participate in the check, a single bit error (at the first bit position) can be detected, indicating an unsatisfied check relationship. Meanwhile, since columns 6, 11, and 16 only involve two check equations, their errors cannot be detected. Only column 1 has three check equations; two satisfy the check equations, and one does not (i.e., the check equation corresponding to row 15), thus allowing the error to be detected. Therefore, if the IRA structure has errors in the four variable nodes shown in Figure 4, only one check equation among all the check relationships can detect this error, resulting in a TS(4,1) structure. The TS(4,1) structure represents a cycle of four variable nodes; if all four variables are incorrect, only one check equation can detect the error. This makes it difficult to correct the error, thus forming a trap set that does not change with the increase in the lift value.

[0055] In view of this, this application proposes an encoding method and a new structure for the core parity check matrix of the base graph, which can expand the minimum circle length of the core parity check matrix to its maximum value, thereby solving the problem of TS(4,1)-like structures existing in the current IRA structure and avoiding trap sets. Furthermore, for the new structure of the core parity check matrix provided in this application, this application also provides a corresponding encoding method for encoding the core parity check region, which can reduce the encoding complexity.

[0056] The technical solution of this application is described below.

[0057] The technical solutions of this application can be applied to various communication systems, including but not limited to: satellite communication systems, fifth-generation (5G) systems or new radio (NR) systems, long-term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. The technical solutions provided in this application can also be applied to future communication systems. Furthermore, they can be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0058] The communication system applicable to this application may include one or more transmitters and one or more receivers. Optionally, one of the transmitters and receivers may be a terminal device, and the other may be a network device.

[0059] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal device in the embodiments of this application may be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. Optionally, the UE may be used to act as a base station. For example, the UE may act as a scheduling entity, providing sidelink signals between UEs in V2X or SL, etc.

[0060] In this embodiment, the device for implementing the functions of the terminal device can be the terminal device itself, or any device capable of supporting the terminal device in implementing those functions, such as a chip, a chip system, hardware circuitry, software modules, or a combination of hardware circuitry and software modules. This device can be installed in or used in conjunction with the terminal device. A chip system can consist of chips or include chips and other discrete components. In this embodiment, the terminal device is used as an example to illustrate the device for implementing the functions of the terminal device.

[0061] The network device in this application embodiment may include a device for communicating with a terminal device. This network device may include an access network device or a radio access network device; for example, the network device may be a base station. In this application embodiment, the access network device may refer to a radio access network (RAN) node (or device) that connects the terminal device to the wireless network. A base station can broadly encompass, or be replaced by, various names such as: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication systems. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technologies or equipment forms used in the network equipment.

[0062] Base stations can be fixed or mobile. For example, an airplane, helicopter, or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, an airplane, helicopter, or drone can be configured as a device to communicate with another base station.

[0063] In some deployments, the network devices mentioned in the embodiments of this application may be devices including CU, DU, or CU and DU, or devices with control plane CU nodes (central unit-control plane (CU-CP)) and user plane CU nodes (central unit-user plane (CU-UP)) and DU nodes. For example, the network devices may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0064] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0065] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN / O-RAN) system, CU can also be called an open CU (open CU, O-CU), and DU can also be called an open DU (open DU, O-DU). CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0066] In this application embodiment, the device used to implement the function of the encoding device can be an encoding device, such as an encoder; or it can be a device that supports the encoding device in implementing the corresponding encoding function, such as a chip system, hardware circuit, software module, or a combination of hardware circuit and software module. This device can be installed in the encoding device or used in conjunction with the encoding device. Without loss of generality, the implementing entity in this application embodiment is described using the term "encoding device," meaning that the encoding device can refer to the encoding device itself, or to the encoder within the encoding device, or to a device that supports the encoding device in implementing the corresponding function, and does not constitute a limitation on the scheme of this application embodiment. As an example, the encoding device can be a network device or a terminal device.

[0067] The encoding method provided in this application can be applied to various communication scenarios. Figure 5 shows an example of a communication system applicable to the technical solution of this application. The encoding method provided in this application can be applied to communication between the network device and the terminal device shown in Figure 5, i.e., uplink communication or downlink communication. In this communication scenario, the encoding device in this paper can be a terminal device in uplink communication or a network device in downlink communication; correspondingly, the decoding device can be a network device in uplink communication or a terminal device in downlink communication. Furthermore, it can also be applied to other communication scenarios without limitation.

[0068] Figure 6 is a schematic diagram of the basic process of wireless communication. As shown in Figure 6, at the signal transmitting end, the signal source is transmitted after sequentially undergoing source coding, channel coding, and digital modulation. At the signal receiving end, the received signal is sequentially processed through digital demodulation, channel decoding, and source decoding before being output to the destination. Among these processes, channel coding and decoding is one of the core technologies in the field of wireless communication.

[0069] The encoding method, or channel coding scheme, provided in this application can be used in dedicated network devices or general-purpose devices. It can be applied to the various network devices (e.g., base stations) and the various terminal devices mentioned above. Specifically, the channel coding scheme is mainly implemented through channel coding units (e.g., encoders or devices that support the coding device in performing corresponding functions) in these devices.

[0070] Alternatively, the functionality of the encoding device can be implemented by application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or by software (e.g., program code in memory), without limitation.

[0071] The encoding method provided in this application is described below.

[0072] Figure 7 is a schematic flowchart of the encoding method provided in this application. Steps 710 to 720 in method 700 can be executed by an encoding device or by a device applied to the encoding device (e.g., a chip, chip system, circuit, hardware and software combined module, etc.). The following description uses an encoding device as an example.

[0073] 710. The encoding device obtains the base matrix and the boost value L.

[0074] The base matrix includes a first submatrix corresponding to the core verification region. The first submatrix is ​​an n-order square matrix, where n is an integer greater than 2. The first submatrix includes at least one column with a weight of 3. The three translation values ​​corresponding to this column with a weight of 3 are different, and all translation values ​​in the first submatrix are integer multiples of M, where L = M × N, and M and N are both positive integers greater than 2. M is a non-true factor of L.

[0075] As an example, the lift value L can be any value from the lifting size table, as shown in Table 1:

[0076] Table 1

[0077] Taking Table 1 as an example, the boost value list includes 8 groups, with 5 to 8 boost values ​​in each group. The j-th boost value in the i-th group is a. i,j =a i,0 ×2 j In this context, i and j are both integers. The row indices of the lift values ​​correspond one-to-one with the column indices of the shift values; that is, each row of the lift value list corresponds to a set of shift values. During rate matching, the lift values ​​are determined first, and then the corresponding shift values ​​are selected to construct the check matrix. The lift value L can be any lift value from any set.

[0078] Optionally, the boosting value list may differ from Table 1, or may satisfy a subset of the boosting value sets in Table 1, or may satisfy the value settings of a subset of boosting values ​​within a subset of boosting value sets; this is not limited. For example, the boosting value list may include fewer than 8 boosting value sets, or more than 8 boosting value sets; this is not limited.

[0079] 720. The encoding device encodes the information bit sequence corresponding to the core check region based on the base matrix and the boost value L.

[0080] As mentioned above, the basis matrix can also be represented as H BG The encoding device is based on the base matrix H BG And the boost value L, can be used to transform the basis matrix H BG The base matrix is ​​expanded into a complete parity-check matrix for encoding. The expansion of the base matrix involves adding H... BG The elements in the matrix are promoted to an L×L square matrix. Specifically, the basis matrix H is... BG Element 0 is promoted to an L×L zero matrix, and element 1 is promoted to an identity matrix (by cyclic shift P to the right or left). i,j The matrix. Where, P i,j SV is the shifting value (SV) corresponding to the i-th row and j-th column.

[0081] This application embodiment mainly focuses on the submatrix (referred to as the first submatrix) corresponding to the core check region in the base matrix. Further, in step 720, the main focus is on the encoding process of the encoding device encoding the information bit sequence corresponding to the core check region based on the first submatrix of the base matrix and the boost value L.

[0082] If the lift value L can be decomposed into product factors (or divisors) M and N, then the first submatrix must satisfy the following: the first submatrix contains at least a column with a column weight of 3, all translation values ​​in the first submatrix are integer multiples of M, or the translation value of any column of the first submatrix, plus or minus the same offset, is an integer multiple of M.

[0083] As an example, the first submatrix conforms to a first structure, where the first column of the first submatrix of the first structure has a column weight of 3, and the remaining columns of the first submatrix of the first structure have a column weight of 2. Specifically, the three translation values ​​corresponding to the first column are different, and one of them is zero. The two translation values ​​corresponding to any column in the remaining columns are the same. Optionally, the translation values ​​corresponding to the remaining columns (i.e., columns with a column weight of 2) can be the same or different. Taking a 4x4 submatrix as an example, with the first row being a column with a weight of 3 and the remaining columns being columns with a weight of 2, then columns 2 through 4 are each columns with a weight of 2, each corresponding to two translation values. The two translation values ​​corresponding to any column from the second to the fourth column are the same. However, the translation values ​​corresponding to different columns with a weight of 2 can be different. For example, the two translation values ​​corresponding to the second column are 0, the two translation values ​​corresponding to the third column are 1, and the two translation values ​​corresponding to the fourth column can be 0, 1, or other values, without limitation.

[0084] As an example, taking the first submatrix with 4 rows and 4 columns as an example, the translation values ​​in the first submatrix can be set as shown in Table 2.

[0085] Table 2

[0086] In Table 2, the translation values ​​for each column of the first submatrix are represented as [a, b, c], [d, e, f], [g, h, i], [j, k]. These translation values ​​must satisfy the following: If the lift value L is decomposed into L = M × N, where M and N are both integers greater than 2, then:

[0087] a = x1*M + o1, b = y1*M + o1, c = z1*M + o1. Where x1, y1, z1, and o1 are all integers.

[0088] Furthermore, [d,e,f], [g,h,i], and [j,k] can all be represented in a manner similar to [a,b,c]. For example, d = x² * M + o², b = y² * M + o², c = z² * M + o², where x², y², z², and o² are all integers; g = x³ * M + o³, h = y³ * M + o³, i = z³ * M + o³, where x³, y³, z³, and o³ are all integers; j = x⁴ * M + o⁴, h = y⁴ * M + o⁴, where x⁴, y⁴, and o⁴ are all integers. The x, y, z, and o values ​​of any two groups can be the same or different. For example, all translation values ​​a, b, and c in column 1, after being added to or subtracted from the same offset o¹, are integer multiples of M. As an example, o¹ = 0. For example, in column 2, all shift values ​​d, e, f are added to or subtracted from the same offset o2, resulting in an integer M. The remaining columns are similar.

[0089] Below are some more examples of the first submatrix.

[0090] Example 1

[0091] Assuming the first submatrix has 4 rows and 4 columns, the translation values ​​can be shown in Table 2:

[0092] Table 3

[0093] For example, L = 384 = M * N = 32 × 12, and we set a = 1 * M + 0 = 32, b = 4 * M + 0 = 128. Under this setting, the first submatrix of the 4x4 row is shown in Table 4:

[0094] Table 4

[0095] Under this setting, the minimum circle length of the base map corresponding to the core check region is increased to 18. 18 is the maximum value of the minimum circle length of the base map corresponding to a 4x4 core check region, and cannot be changed by expanding the boost value or altering the translation value. The value of A in the trap set TS(A,1) of the core check region is much greater than 4.

[0096] Example 2

[0097] Assuming the first submatrix is ​​3 rows and 3 columns, the translation values ​​can be shown in Table 5:

[0098] Table 5

[0099] For example, L = 288 = M * N = 32 × 9, and we set a = 1 * M + 0 = 32, b = 3 * M + 0 = 96. Under this setting, the first submatrix of the 3x3 matrix is ​​shown in Table 6.

[0100] Table 6

[0101] Under this setting, the minimum circle length of the base map corresponding to the core check region is increased to 14. 14 is the maximum value of the minimum circle length of the base map corresponding to a 3x3 core check region, and cannot be changed further by expanding the boost value or altering the translation value. The value of A in the trap set TS(A,1) of the core check region is much greater than 3.

[0102] It can be observed that the structure of the first submatrix in Example 1 or Example 2 is similar to the IRA structure described above, and is referred to as the first structure in this embodiment. The first submatrix of the first structure satisfies the following: the first column of the first submatrix is ​​a triple column, and the remaining columns are double columns. Specifically, the triple column corresponds to three different translation values, and two of these translation values ​​are integer multiples of M. In Example 1 or Example 2, these two translation values ​​among the three translation values ​​corresponding to the triple column are positive integer multiples of M, or they can be negative integer multiples. The two translation values ​​corresponding to each column in the double columns are equal. In Example 1 or Example 2, the translation values ​​corresponding to the double columns are all equal and are 0.

[0103] The structure of the submatrix of the core parity region of the base matrix has been described in detail above. Encoding the submatrix of the core parity region provided in this application has high encoding complexity. Therefore, this application further provides an encoding method for the submatrix of the core parity region in the base matrix provided in this application, which can reduce encoding complexity.

[0104] In step 720, the encoding device determines a parity check matrix of dimension (n×L)×(n×L) based on two product factors M and N of the base matrix and the boost value L. The parity check matrix includes M independent full-rank submatrices of dimension (n×N)×(n×N). "Independent" means that each of these M submatrices can be decoded independently. Furthermore, all M submatrices are full-rank. For simplicity, these M independent full-rank submatrices are described below as M submatrices. In this embodiment, the dimension of the matrix refers to the size or dimensions of the matrix; for example, a parity check matrix of dimension (n×L)×(n×L) means that the parity check matrix contains n×L rows and n×L columns.

[0105] As mentioned above, the submatrix corresponding to the core parity region of the basis matrix, i.e., the first submatrix, is a square matrix of dimension n. The M submatrices correspond to M sets of parity-check equations, each set containing n×N parity-check equations. The coefficients of the n×N parity-check equations in each set constitute one of the M submatrices, thus the M sets of parity-check equations form the M submatrices. Each set of parity-check equations contains n×N parity-check equations corresponding to solutions for n×N unknowns, thus the M sets of parity-check equations correspond to a total of n×N×M solutions for unknowns. These solutions for n×N×M unknowns are the n×L parity bits corresponding to the parity-check equations.

[0106] For ease of understanding, we will use a 4x4 submatrix as an example to illustrate how to construct M submatrices. Based on this example of constructing a single submatrix, those skilled in the art can then understand how to construct M submatrices.

[0107] Here, we take the core matrix of BG2, L=8, M=2, N=4, as an example. The base diagram is shown in Table 7:

[0108] Table 7

[0109] The translation values ​​are set according to the method in the embodiments of this application, as shown in Table 8 below.

[0110] Table 8

[0111] As you can see, all translation values ​​are multiples of M = 2.

[0112] The base map is expanded into a complete parity check matrix based on the lift and shift values, as shown in Figure 8.

[0113] Figure 8 is an example of a check matrix provided according to an embodiment of this application. The multiple rows of the check matrix H shown in Figure 8 can be represented as w(0)w(1)w(2)….,z(7) in sequence, and the multiple columns of the check matrix H can be represented as a(0)a(1)a(2)….,d(7) in sequence.

[0114] Based on the parity-check matrix, the following relationship exists:

[0115] H*[a(0)a(1)…b(0),b(1)…] T =[w(0)w(1)…x(0)x(1)…] T ;

[0116] Find the inverse of H: H -1 *H*[a(0)a(1)…b(0)b(1)…] T =H -1 *[w(0)w(1)…x(0)x(1)…] T ;

[0117] [a(0)a(1)…b(0),b(1)…] T =H -1 *[w(0)w(1)…x(0),x(1)…] T The encoding process can then be restored.

[0118] Simultaneously observing the verification matrix, extracting rows and columns 0, 2, 4, 6, ..., 30 reveals two completely independent, complementary, and correlated matrices.

[0119] That is, the intersection of the columns corresponding to a(0)a(2)a(4)a(6),b(0)b(2)b(4)b(6),c(0)c(2)c(4)c(6),d(0)d(2)d(4)d(6) with the columns corresponding to w(0)w(2)w(4)w(6),x(0)x(2)x(4)x(6),y(0)y(2)y(4)y(6),z(0)z(2)z(4)z(6) is taken out to obtain an H1 matrix. Take the intersection of the columns corresponding to a(1)a(3)a(5)a(7),b(1)b(3)b(5)b(7),c(1)c(3)c(4)c(7),d(1)d(3)d(5)d(7) with the columns corresponding to w(1)w(3)w(5)w(7),x(1)x(3)x(5)x(7),y(1)y(3)y(5)y(7),z(1)z(3)z(5)z(7) to obtain an H2 matrix. All parts outside these two matrices are 0, so there is no coupling relationship between the variables of the two matrices. And H1 and H2 are exactly the same, which are 16×16 matrices, and the size is 1 / 4 of the H matrix.

[0120] Therefore, it can be written as:

[0121] H1*[a(0)a(2)…b(0),b(2)…] T =[w(0)w(2)…x(0),x(2)…] T ;

[0122] H2*[a(1)a(3)…b(1),b(3)…] T =[w(1)w(3)…x(1),x(3)…] T ;

[0123] Invert either the parity check matrix H1 or H2 to obtain H1 -1 .

[0124] [a(0)a(2)…b(0),b(2)…] T =H1 -1 *[w(0)w(2)…x(0),x(2)…] T ;

[0125] [a(1)a(3)…b(1),b(3)…] T =H1 -1 [w(1)w(3)…x(1),x(3)…] T ;

[0126] Therefore, the original 32×32 system of equations can be simplified into two 16×16 systems of equations, halving the overall complexity (1 / M).

[0127] Each of the n rows of the first submatrix corresponds to a check equation. The check equation of the j-th row satisfies the following check relationship: the input information corresponding to the j-th row is XORed to obtain the input of the j-th row, 0≤j≤n-1, where j is an integer. The input of any row in the n rows is known.

[0128] For any one of the M check equation sets M q (where q is any value in [0, 1, 2, ..., N-1]) is obtained based on the following operation:

[0129] The column position i of the expanded core check column in the base graph corresponding to the base matrix takes the value i = M × [0,1,2,…,N-1] + q. Substituting this into the check equation corresponding to each row of the n rows of the first submatrix, each row of the n rows of the first submatrix yields N check equations, and the n rows yield a total of n × N check equations. These n × N check equations form a set of check equations. When q has traversed all values ​​in [0,1,2,…,N-1], M sets of check equations are obtained.

[0130] As explained above, encoding the core check region of the information bit sequence is essentially solving for the check bits of the core check submatrix (i.e., the first submatrix) of the check matrix. The check bits corresponding to the first submatrix satisfy a check relationship with the information bits. This check relationship is determined based on the check matrix, which is determined by expanding the base map using lift and shift values.

[0131] The encoding method provided in this application will be explained in detail below using the first submatrix of 4 rows and 4 columns as an example.

[0132] Example 3

[0133] Assuming the lift value L = 384, decompose the lift value L into M × N. For example, M = 32 and N = 12.

[0134] Assume the first submatrix is ​​as shown in Table 9 below.

[0135] Table 9

[0136] Based on the principle of expanding the base matrix, assuming the first submatrix is ​​4 rows and 4 columns, and the lift value L is 384, the expanded first submatrix has 4 × 384 columns, corresponding to the 4 × 384 parity bits of the core parity region, which are the unknowns to be solved. Therefore, there are 4 × 384 parity bits to solve. After obtaining the specific values ​​of these 4 × 384 parity bits through the parity equation, the parity bits of the core parity columns obtained after expanding the first submatrix by the lift value L are determined, thus completing the encoding of the core parity region.

[0137] For clarity of understanding, the four columns of the first submatrix are labeled a, b, c, and d, and the four rows are labeled w, x, y, and z. It should be understood that these labeling operations are solely for ease of understanding and are not required during actual encoding. Therefore, the first submatrix shown in Table 7 corresponds to these row and column labels as shown in Table 10.

[0138] Table 10

[0139] The process of solving the parity bits of the core parity region is as follows:

[0140] 1) It is known that each column of the first submatrix will be expanded to 384 columns. Therefore, each column of a, b, c and d above corresponds to the expanded 384 columns, which are represented as a(0-383), b(0-383), c(0-383) and d(0-383) respectively. It can be understood that a(0-383) corresponds to the first 384 columns of the expanded core check region, b(0-383) corresponds to the second 384 columns, c(0-383) corresponds to the third 384 columns, and d(0-383) corresponds to the fourth 384 columns. Similarly, each row of the first submatrix will be expanded to 384 rows. Therefore, each row of w, x, y, and z above corresponds to the expanded 384 rows, represented as w(0-383), x(0-383), y(0-383), and z(0-383), respectively. Among them, w(0-383) corresponds to the first 384 rows of the expanded core check region, x(0-383) corresponds to the second 384 rows, and so on. The dimension of the expanded check matrix is ​​(4×384)×(4×384).

[0141] 2) Based on the check relationship between the information bits and check bits in each of the four rows of the first submatrix, the following four check equations can be listed for the four rows of the first submatrix:

[0142] ①a(i)+b(i)+c(i)=w(i);

[0143] ②a(i-32)+b(i-64)+d(i)=x(i);

[0144] ③a(i)+c(i-128)+d(i-224)=y(i);

[0145] ④b(i)+c(i-160)+d(i)=z(i).

[0146] Here, 'i' represents the index of the column position after the expansion of the core check column of the base graph. It should be understood that since the base matrix contains 4 columns and the boost value L = 384, the expanded core check column of the base graph has a total of 4 × 384 columns. Therefore, 'i' is used to represent the column index of these 4 × 384 columns. These 4 × 384 column indices are represented by a(0-383), b(0-383), c(0-383), and d(0-383). Therefore, a(i) represents the i-th column in a(0-383), where i traverses [0,1,2,…,383], b(i) represents the i-th column in b(0-383), where i traverses [0,1,2,…,383], and so on. Further details are omitted.

[0147] Furthermore, since the check relationship between the input information and the check bits in each row is known, it can be determined based on the check matrix. Therefore, the right-hand sides w(i), x(i), y(i), and z(i) in the above check equations ①②③④ are all known.

[0148] It should be understood that each of the verification equations ①②③④ corresponds to 384 rows, and therefore corresponds to 384 verification equations. For example, verification equation ① is the general expression of the 384 verification equations corresponding to the first 384 rows after the core verification region of the base map is expanded; verification equation ② is the general expression of the 384 verification equations corresponding to the second 384 rows after the core verification region of the base map is expanded, and so on.

[0149] Therefore, the four check equations mentioned above actually represent a total of 384×4 check equations, corresponding to solutions for 384×4 unknowns. These 384×4 unknowns are the check bits of the 384×4 core check columns after the core check region of the base map is expanded. It can be seen that if the above 384×4 check equations are of full rank, then these 384×4 unknowns (i.e., the check bits of the 384×4 core check columns) must have solutions. However, the complexity of directly solving the check equations is 4×384×4×384.

[0150] Therefore, in this embodiment, since the lift value L = 32 × 12 and the translation values ​​in the first sub-matrix meet certain characteristics (see the description of the foregoing embodiment for details), the above 384 × 4 check equations can be divided into M = 32 groups, each containing n × N = 4 × 12 = 48 equations. The specific operation is as follows:

[0151] 3) Substitute the values ​​of i = 32 × [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11] into the above verification equations ①②③④ respectively. Since there are 12 possible values ​​for i (corresponding to 0 to N-1), each verification equation corresponds to 12 verification equations. The 4 verification equations correspond to a total of 12 × 4 verification equations. It can be found that the sum of all unknowns in these 12 × 4 verification equations is also 12 × 4, forming a set of verification equations.

[0152] Substituting the values ​​of i = 32 × [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11] + 1 into the above verification equations ①②③④, we obtain the second set of verification equations.

[0153] …

[0154] And so on.

[0155] As described in the above example, i = 32 × [0,1,2,3,4,5,6,7,8,9,10,11] + q, where q iterates through all values ​​in [0,1,2,…,M-1] to obtain all M sets of verification equations.

[0156] It should be noted that the order in which the M check equations are obtained is not restricted. In other words, when q has traversed all values ​​in [0,1,2,…,M-1], M check equations will be obtained. The order in which q traverses the values ​​in [0,1,2,…,M-1] is irrelevant and does not affect the resulting M check equations. For example, whether q traverses the values ​​in [0,1,2,…,M-1] by index (from smallest to largest, from largest to smallest), randomly, or according to a certain rule, the resulting M check equations will all be the same. Furthermore, the order of these M check equations is also irrelevant, as they can all be decoded independently.

[0157] Therefore, after q has traversed all 32 values ​​in [0,1,2,…,M-1], a total of 32 independent check equations will be obtained. Each check equation can be solved independently. The encoding complexity of these 32 check equations is the same; for a check equation, the encoding complexity is n×N×n×N=48×48.

[0158] As can be seen, using the encoding method provided in this application, the encoding of a high-complexity check equation with a large dimension can be achieved by independently encoding M independent low-complexity submatrices with small dimensions. This reduces the encoding complexity from the original 4×384×4×384 to 48×48×32, a reduction of 32 times (i.e., the complexity is reduced to 1 / 32; the following expressions of reduction factors also have a similar meaning and will not be repeated).

[0159] Here is another encoding example, as shown in Example 4 below.

[0160] Example 4

[0161] Assume the boost value is 384, M = 32, and N = 12.

[0162] In Example 4, assume the first submatrix is ​​4 rows and 4 columns, as shown in Table 4. Using a similar notation as in Example 3, the correspondence shown in Table 11 can be obtained.

[0163] Table 11

[0164] Similar to Example 3, since the boost value L = 324, after expansion, the core check region of the basemap includes 4 × 384 core check columns, corresponding to a total of 4 × 384 check bits. These 4 × 384 check bits are the unknowns to be solved. The solution process is as follows:

[0165] 1) Label these values ​​to be solved as a(0-383), b(0-383), c(0-383) and d(0-383), respectively; and label the 4×384 rows of the first submatrix after expansion as w(0-383), x(0-383), y(0-383) and z(0-383).

[0166] 2) Based on the check relationship between the information bits and check bits in each of the four rows of the first submatrix, the following four check equations can be listed for the four rows of the first submatrix:

[0167] ①a(i)+b(i)=w(i);

[0168] ②b(i)+c(i)=x(i);

[0169] ③a(i-32)+c(i)+d(i)=y(i);

[0170] ④a(i-128)+d(i)=z(i);

[0171] Where i is the index of the column position after the core validation column of the base graph is expanded.

[0172] It should be noted that, unlike in Example 3, in Example 4, due to the special design of the first submatrix, if the verification equation ①+②+③+④ (modulo 2 addition) is used, b(i), c(i), and d(i) on the left side of the verification equation are eliminated. Therefore, we have:

[0173] ⑤a(i)+a(i-32)+a(i-128)=w(i)+x(i)+y(i)+z(i).

[0174] It is evident that the only remaining unknown is the parity bit corresponding to a(0-383). Therefore, if the matrix corresponding to the 384 parity equations is full rank, then the solution to the 384 unknowns, a(0-383), can be obtained by applying parity equation ⑤ to the 384 parity equations.

[0175] 3) Substituting the values ​​of i = 32 × [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11] into verification equation ⑤, we can obtain 12 verification equations. We will find that the sum of all the unknowns in these 12 verification equations is also 12, forming a set of verification equations; at the same time, the other verification equations do not contain these 12 unknowns.

[0176] Substituting i = 32 × [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11] + 1 into the verification equation ⑤, we form the second set of equations; ..., and so on, resulting in a total of 32 independent sets of verification equations. Each set of verification equations can be solved independently to obtain a(0-383).

[0177] 4) After obtaining a(0-383), substitute a(0-383) into the check equations ① to ④ to solve for b(0-383), c(0-383), and d(0-383). That is, solve for all 4×384 check bits corresponding to the core check region, thus completing the encoding of the core check region.

[0178] As can be seen, in Example 4, the 384 check equations can be completed using 32 independent check equation sets, with each check equation set having a coding complexity of 12×12. Therefore, the coding complexity is reduced from the original 384×384 to 12×12×32, a decrease of 32 times.

[0179] As can be seen from the above embodiments, when the lift value L is decomposed into M and N, M represents the number of independent check equation sets, and N represents the number of check equations in each check equation set, representing the complexity of an independent encoding matrix. In the above example, M can be any non-1 proper factor among all divisors of L. N = 12 is chosen because among all divisors of 384 greater than 1, 12 is the smallest divisor that can reach the maximum value of the minimum circle length of the base graph corresponding to the first submatrix. Choosing such a smallest divisor minimizes the encoding complexity. Optionally, N can also be chosen to have other constraints on the lift value L. For example, choosing N = 24 does not change the encoding process, but the encoding complexity becomes 24 × 24 × 16, which is twice as much as 12 × 12 × 32. However, compared to 384 × 384, the encoding complexity is still reduced.

[0180] The above is a detailed description of the encoding method provided in this application. The following describes the communication device provided in this application.

[0181] Figure 9 is a schematic structural diagram of the communication device 1000 provided in this application. The communication device 1000 may be an encoding device, or a device applied to the encoding device and capable of realizing the corresponding function of the encoding device in the method embodiment of this application, such as a chip, chip system, or circuit.

[0182] Optionally, the communication device 1000 includes a processing module 1001, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 1000 is an encoding device or a device applied to an encoding device, the processing module 1001 is used to encode the information bit sequence corresponding to the core check region. For details of the process, please refer to the detailed description of the encoding method in the method embodiments; it will not be repeated here.

[0183] Optionally, the communication device 1000 further includes a communication module 1002, which may also be called a transceiver module, transceiver, transceiver unit, or transceiver device, etc., and is used to perform receiving (or input) and / or sending (or output) operations. For example, when the communication device 1000 is an encoding device or a device applied to an encoding device, the communication module 1002 can be used to obtain the base matrix, obtain the boost value L, etc. Optionally, after the processing module 1001 performs encoding corresponding to the core verification region and obtains the codeword, the communication module 1002 is also used to output the encoded codeword.

[0184] Furthermore, it should be noted that the aforementioned communication module and / or processing module can be implemented through virtual modules. For example, the processing module can be implemented through software functional units or virtual devices, and the communication module can be implemented through software functions or virtual devices. Alternatively, the processing module or communication module can also be implemented through physical devices, such as chips / circuits (e.g., integrated circuits or logic circuits). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., integrated circuits, logic circuits).

[0185] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0186] Figure 10 is a schematic block diagram of another communication device 1100 provided in this application. As shown in Figure 10, the communication device 1100 includes at least one processor 1110, which implements the functions of the encoding device described in the foregoing method embodiments.

[0187] Optionally, the processor 1110 is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. The communication device 1100 may also include at least one memory 1120. The memory 1120 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1110 can execute the computer programs, instructions, or data stored in the memory 1120 to complete the encoding method in any of the above method embodiments.

[0188] Optionally, the communication device 1100 may further include a communication interface 1130, through which the communication device 1100 can interact with other devices. For example, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other type of interface.

[0189] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1110 may operate in conjunction with the memory 1120 and the communication interface 1130. This application does not limit the specific connection medium between the processor 1110, the memory 1120, and the communication interface 1130.

[0190] Figure 11 is a schematic diagram of the chip (or chip system) provided in this application. The chip (or chip system) 30 may include a circuit 31 and an input / output interface 32. The circuit 31 may be a logic circuit, an integrated circuit, etc., and the input / output interface 32 may be an input / output circuit or an interface circuit, capable of inputting information (or receiving information) and outputting information (or sending information). Optionally, the chip system may be composed of a chip or may include chips and other discrete devices. The chip 30 can be used to execute the methods performed by the encoding device in the various embodiments of this application. For example, the input / output interface 32 is used to receive information indicating the base matrix, information indicating the boost value L, and a sequence of received information bits. Optionally, it is also used to output the encoded codeword. The circuit 31 is used to execute the encoding method in any of the above method embodiments.

[0191] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause operations and / or processes performed by an encoding device in the various method embodiments of this application to be executed.

[0192] This application also provides a computer program product, which includes computer program code or instructions that, when run on a computer, cause the operations and / or processes performed by the encoding device in the various method embodiments of this application to be executed.

[0193] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by an encoding device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface, or an interface circuit, etc. Further, the chip may also include the memory.

[0194] This application provides a communication system, including the encoding device in the above method embodiments.

[0195] In this application, the processor can be a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0196] The memory can be non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). Memory is any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited to this. The memory in this application can also be a circuit or any other device capable of implementing a storage function for storing program instructions and / or data.

[0197] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0198] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0199] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0200] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0201] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0202] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0203] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0204] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0205] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An encoding method, characterized in that, include: Obtain the base matrix and the boost value L. The base matrix includes the first sub-matrix corresponding to the core verification region. The first sub-matrix is ​​an n-order square matrix. The first sub-matrix includes at least one column with a column weight of 3. The three translation values ​​corresponding to the column with a column weight of 3 are different. All translation values ​​in the first sub-matrix are integer multiples of M, where n is an integer greater than 2, and L = M × N, where M and N are both positive integers greater than 2. Based on the base matrix and the boost value L, the information bit sequence is encoded according to the core check region.

2. The method according to claim 1, characterized in that, The encoding of the information bit sequence corresponding to the core check region based on the base matrix and the boost value L includes: Based on the base matrix and the two product factors M and N of the lift value L, a check matrix of dimension (n×L)×(n×L) is determined, the check matrix comprising M independent full-rank submatrices of dimension (n×N)×(n×N); The information bit sequence is encoded based on the check matrix, corresponding to the core check region.

3. The method according to claim 2, characterized in that, The verification matrix comprises M independent full-rank submatrices of dimension (n×N)×(n×N), including: The M full-rank submatrices correspond to M sets of check equations. Each set of check equations includes n×N check equations. The coefficients of the n×N check equations in each set of check equations constitute a submatrix in the M full-rank submatrices. The n×N check equations in each set of check equations correspond to the solutions of n×N unknowns. The M sets of check equations correspond to a total of n×N×M solutions of unknowns. The solutions of the n×N×M unknowns are the n×L check bits corresponding to the check matrix.

4. The method according to claim 3, characterized in that, Any one of the M check equation sets Mq is obtained based on the following operation, where q is a value in [0,1,2,…,M-1]: The column position i of the expanded core check column in the base graph corresponding to the base matrix is ​​i = M × [0,1,2,…,N-1] + q, and is substituted into the check equation corresponding to each of the n rows. Each row of the n rows yields N check equations, and the n × N check equations obtained from the n rows form a set of check equations. When q traverses all values ​​in [0,1,2,…,M-1], the M sets of check equations are obtained. In this submatrix, each of the n rows corresponds to a verification equation. The verification equation of the j-th row of the n rows satisfies the following verification relationship: the input information corresponding to the j-th row is XORed to obtain the input of the j-th row, 0≤j≤n-1, where j is an integer.

5. The method according to any one of claims 1 to 4, characterized in that, The translation value of any column in the first submatrix, after being added to or subtracted by the same offset, is an integer multiple of M.

6. The method according to any one of claims 1 to 5, characterized in that, The first submatrix conforms to a first structure. The first column of the first submatrix of the first structure has a column weight of 3, the remaining columns of the first submatrix of the first structure have a column weight of 2, one of the three translation values ​​corresponding to the first column has a translation value of zero, and the two translation values ​​corresponding to any one of the remaining columns are the same.

7. The method according to any one of claims 4 to 6, characterized in that, The first submatrix of the first structure is a 4th or 3rd order square matrix.

8. The method according to claim 6 or 7, characterized in that, Each of the M sets of check equations includes N check equations, and the N check equations in each set correspond to the solutions of N unknowns. The M sets of check equations correspond to a total of N×M solutions of unknowns, and the solutions of the N×M unknowns are the L check bits corresponding to the check matrix.

9. The method according to any one of claims 1 to 8, characterized in that, N is the smallest divisor among all divisors of the lift value L that can reach the maximum value of the minimum circle length of the base graph corresponding to the first submatrix.

10. A communication device, characterized in that, include: The communication module is used to obtain the base matrix and the boost value L. The base matrix includes a first sub-matrix corresponding to the core verification region. The first sub-matrix is ​​an n-order square matrix. The first sub-matrix includes at least one column with a column weight of 3. The three translation values ​​corresponding to the column with a column weight of 3 are different. All translation values ​​in the first sub-matrix are integer multiples of M, where n is an integer greater than 2, and L = M × N, where M and N are both positive integers greater than 2. The processing module is used to encode the information bit sequence corresponding to the core check region based on the base matrix and the boost value L.

11. The communication device according to claim 10, characterized in that, The processing module is used for: Based on the base matrix and the two product factors M and N of the lift value L, a check matrix of dimension (n×L)×(n×L) is determined, the check matrix comprising M independent full-rank submatrices of dimension (n×N)×(n×N); as well as The information bit sequence is encoded according to the core check region based on the check matrix.

12. The communication device according to claim 11, characterized in that, The verification matrix comprises M independent full-rank submatrices of dimension (n×N)×(n×N), including: The M full-rank submatrices correspond to M sets of check equations. Each set of check equations includes n×N check equations. The coefficients of the n×N check equations in each set of check equations constitute a submatrix in the M full-rank submatrices. The n×N check equations in each set of check equations correspond to the solutions of n×N unknowns. The M sets of check equations correspond to a total of n×N×M solutions of unknowns. The solutions of the n×N×M unknowns are the n×L check bits corresponding to the check matrix.

13. The communication device according to claim 12, characterized in that, Any one of the M sets of verification equations M q The following operation is performed to obtain q as a value in [0,1,2,…,M-1]: The column position i of the expanded core check column in the base graph corresponding to the base matrix is ​​i = M × [0,1,2,…,N-1] + q, and is substituted into the check equation corresponding to each of the n rows. Each row of the n rows yields N check equations, and the n × N check equations obtained from the n rows form a set of check equations. When q traverses all values ​​in [0,1,2,…,M-1], the M sets of check equations are obtained. In this submatrix, each of the n rows corresponds to a verification equation. The verification equation of the j-th row of the n rows satisfies the following verification relationship: the input information corresponding to the j-th row is XORed to obtain the input of the j-th row, 0≤j≤n-1, where j is an integer.

14. The communication device according to any one of claims 10 to 13, characterized in that, The translation value of any column in the first submatrix, after being added to or subtracted by the same offset, is an integer multiple of M.

15. The communication device according to any one of claims 10 to 14, characterized in that, The first submatrix conforms to a first structure. The first column of the first submatrix of the first structure has a column weight of 3. The remaining columns of the first submatrix of the first structure have a column weight of 2. One of the three translation values ​​corresponding to the column with a column weight of 3 has a translation value of zero. The two translation values ​​corresponding to any one of the remaining columns are the same.

16. The communication device according to any one of claims 13 to 15, characterized in that, The first submatrix of the first structure is a 4th or 3rd order square matrix.

17. The communication device according to claim 15 or 16, characterized in that, Each of the M sets of check equations includes N check equations, and the N check equations in each set correspond to the solutions of N unknowns. The M sets of check equations correspond to a total of N×M solutions of unknowns, and the solutions of the N×M unknowns are the L check bits corresponding to the check matrix.

18. The communication device according to any one of claims 10 to 17, characterized in that, N is the smallest divisor among all divisors of the lift value L that can reach the maximum value of the minimum circle length of the base graph corresponding to the first submatrix.

19. A communication device, characterized in that, Includes modules or units for performing the method as described in any one of claims 1-9.

20. A communication device, characterized in that, The system includes a communication interface and a circuit. The communication interface is used to acquire a base matrix and a boosting value L, and input the base matrix and the boosting value L to the circuit. The circuit is used to execute the method as described in any one of claims 1-9 to encode the information bit sequence based on the base matrix and the boosting value L, corresponding to the core check region in the base matrix. The communication interface is also used to output the encoded codewords.

21. A communication device, characterized in that, include: A processor coupled to a memory, the processor being configured to execute a computer program or instructions stored in the memory to cause the communication device to perform the method as described in any one of claims 1-9.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-9.

23. A computer program product, characterized in that, The computer program product includes computer code or instructions that, when executed on a computer, cause the method as described in any one of claims 1-9 to be implemented.

24. A wireless communication system, characterized in that, Includes the communication device as described in any one of claims 10 to 18.

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