Method applied to channel coding or channel decoding, and communication apparatus

Abstract

Provided in the present application are a method applied to channel coding or channel decoding, and a communication apparatus. By increasing lifting values used in the process of expanding an LDPC base matrix into a check matrix, the maximum value of the minimum cycle length of a base graph corresponding to a core check region can be increased, thereby eliminating trap sets under the lifting values, and improving decoding performance. On the basis of increasing lifting values, a method for nested use between different lifting values is designed. In addition, when the lifting values are large, choosing to use the same lifting value for expansion can avoid the problem that larger lifting values correspond to different coding structures, thus reducing coding complexity.

Description

Methods and communication devices applied to channel coding or channel decoding

[0001] This application claims priority to Chinese Patent Application No. 202410944034.X, filed on July 12, 2024, entitled "Method and Communication Apparatus for Channel Coding or Channel Decoding", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of channel coding and decoding, and more specifically, to a method and communication apparatus for channel coding or channel decoding. Background Technology

[0003] Low-density parity-check (LDPC) codes are channel coding schemes that closely approximate the Shannon limit, offering advantages such as high performance and low complexity. Mainstream LDPC applications employ a quasi-cyclic (QC) structure, using shift values ​​for each block to avoid short-cycle loops and improve code distance. In fifth-generation (5G) systems, the LDPC base graph (BG) consists of BG1 and BG2, both sharing a common matrix structure that includes a high-rate core parity check region. In one existing implementation, this core parity check region can be an irregular repeat-accumulate (IRA) structure. The IRA structure is a double-diagonal design. The shift value design in the double-diagonal IRA structure allows for simplified coding methods.

[0004] While IRA is easy to encode, it introduces traps. In ultra-reliable low-latency communications (URLLC) scenarios, LDPC requires very high reliability and cannot have significant error floors. However, the unique shift value characteristics of IRA result in numerous small trap sets (TS) at each lift value, easily leading to error floors, and these trap sets do not change as the lift value increases. Eliminating or reducing trap sets at each lift value is crucial for improving decoding performance. Therefore, how to avoid trap sets at each lift value in the base graph is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a method and communication apparatus for channel coding or channel decoding, which can expand the minimum circle length of the base map under different boost values, thereby avoiding trap sets and improving decoding performance.

[0006] Firstly, a method for channel coding or channel decoding is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, chip system, integrated circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). When the method is applied to channel coding, the communication device is also referred to as an encoding device; when the method is applied to channel decoding, the communication device is also referred to as a decoding device, without limitation. The method may include: obtaining a first boost value; and determining, based on the first reference boost value, a translation value corresponding to a first position of the first boost value in a base map, wherein the first reference boost value is any boost value less than the maximum boost value in the boost value group.

[0007] In the technical solution of this application, the translation value corresponding to a lift value at a certain position (e.g., the first position) in the base graph is determined based on a reference lift value (e.g., referred to as the first reference lift value). This first reference lift value is any lift value in its lift value group that is less than the maximum lift value. Compared to the use of an IRA structure in the core check region, the sub-matrix corresponding to the core check region in this embodiment of the application can make the minimum circle length of the base graph corresponding to the core check region reach the maximum value, which can improve the error flattening caused by trap sets under each lift value, thereby improving decoding performance. In addition, the technical solution of this application can be compatible with the determination of translation values ​​corresponding to other lift values ​​in the lift value group, or in other words, the translation value corresponding to the reference lift value can be nested within the lift value group where the reference lift value is located.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, determining the translation value corresponding to the first position of the first boost value in the base map based on the first benchmark boost value includes: determining the translation value corresponding to the first position of the first boost value in the base map based on the translation value corresponding to the first position of the first benchmark boost value in the base map; wherein, the first boost value and the first benchmark boost value belong to the same boost value group, or, the first boost value is an integer multiple of the first benchmark boost value and the first benchmark boost value is a positive integer power of 2.

[0009] In this implementation, the shift value of the first boost value at the first position of the base map can be determined based on the shift value corresponding to the first reference boost value at the first position of the base map. The first reference boost value is determined from multiple boost values ​​included in the boost value group. Under the reference boost value of this boost value group, the minimum circle length of the base map corresponding to the core check region can be boosted to its maximum value. Since the minimum circle length of the base map is an important parameter for evaluating LDPC decoding performance, a smaller circle length means that errors are more likely to propagate in the loop during decoding. When an error occurs in a bit, this error may propagate along the loop to other bit positions, leading to more errors. Therefore, a smaller circle length will reduce the decoding performance of LDPC and increase the bit error rate. Increasing the minimum circle length helps to reduce the propagation of errors during the iteration process and improves decoding performance. In this embodiment, under the reference boost value, using a reasonable offset value can increase the minimum circle length. For example, with a boost value of 9, the minimum circle length can be boosted to 18, reaching the maximum value of the minimum circle length achievable by the base map, thus improving decoding performance. Furthermore, regarding the structure of the core parity region sub-matrix provided in this application embodiment, the large-size parity matrix (referring to the size of the parity matrix, i.e., the number of rows and columns) can be decomposed into several independently decodeable small-size sub-matrices for encoding (or decoding). The encoding complexity is related to the square of the base boost value; therefore, the smaller the base boost value, the lower the encoding complexity. Thus, this application embodiment can improve decoding performance while maintaining compatibility with low-complexity encoding.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, when the first boost value is the first reference boost value, the translation value corresponding to the first position of the first boost value in the base map is the first translation value, and the first translation value is the translation value corresponding to the first position of the first reference boost value in the base map.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, when the first boost value and the first reference boost value among the plurality of reference values ​​are located in the same boost value group, and the first boost value is greater than the first reference boost value, the translation value corresponding to the first position of the first boost value in the base map is S·(B / A), where B is the first boost value, A is the first reference boost value, S is the translation value corresponding to the first position of the first reference boost value in the base map, and S, B and A are all positive integers.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, when the first boost value and the first benchmark boost value among the plurality of benchmark values ​​are located in the same boost value group, and the first boost value is less than the first benchmark boost value, the translation value corresponding to the first position of the first boost value in the base map is mod(S,B), where mod is the modulo operation, B is the first boost value, S is the translation value corresponding to the first position of the first benchmark boost value in the base map, and S and B are positive integers.

[0013] Trap sets refer to the set of non-empty variable nodes that are not correctly decoded after a finite number of iterations in an iterative decoder, and are one of the important reasons for LDPC decoding failure. Avoiding or eliminating trap sets can improve decoding performance. Smaller loop lengths may increase the likelihood of trap sets occurring. In the above implementation methods, by using a reasonable offset value, the minimum loop length at the first boost value can be increased to the maximum value, eliminating or reducing the trap set at the first boost value. In other words, by increasing the minimum loop length, trap sets are avoided or reduced, thus improving decoding performance. Furthermore, as mentioned above, in the embodiments of this application, the encoding complexity is related to the square of the base boost value; therefore, using a smaller base boost value can also accommodate very low encoding complexity.

[0014] In conjunction with the first aspect, in certain implementations of the first aspect, when the plurality of benchmark boost values ​​include 2 n And Q, Q = B / 2 n n is a positive integer greater than or equal to 2, Q is an integer greater than 1, B is the first boost value, and the first base boost value is determined to be 2. n The translation value corresponding to the first position of the first boost value on the base map is S·(B / 2). n ), where S is the offset of the first reference lift value at the first position on the base map.

[0015] In this implementation, when the boost value is large or very large, different boost values ​​can be extended using the same base boost value. This avoids the problem of high coding complexity caused by different coding structures corresponding to different boost values ​​when the boost value is large, and can reduce coding complexity.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the first position is any position of the base graph.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the first position is a partial position of the base map, and the translation value corresponding to other positions of the base map other than the first position is determined based on multiple reference lift values. The multiple reference lift values ​​correspond one-to-one with the multiple lift value groups, and each reference lift value is the maximum value in its respective lift value group.

[0018] In this implementation, only the base lift value corresponding to the translation value at some positions in the base graph is modified. This can be applied when there are many trap sets at certain positions, so that the lift value corresponding to the translation value is modified only for these positions with poor decoding performance.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the plurality of benchmark boost values ​​are preset.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the translation value corresponding to each of the plurality of reference lift values ​​at the first position in the base map is preset.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: expanding the base matrix based on the translation value corresponding to the first position of the base graph based on the first boost value to obtain a parity check matrix; encoding the information bit sequence based on the parity check matrix; and outputting the encoded codeword.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: expanding the base matrix based on the translation value corresponding to the first position of the base map based on the first boost value to obtain a parity check matrix; decoding the channel received sequence based on the parity check matrix; and outputting the decoding result.

[0023] Secondly, a communication device is provided, which has the function of implementing the method of the first aspect or any possible implementation thereof. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0024] Thirdly, a communication device is provided, comprising at least one processor configured to cause the communication device to perform the methods of the first aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and execute the computer program or instructions from the at least one memory, causing the communication device to perform the methods of the first aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or configured externally to the communication device. Optionally, the communication device further includes the at least one memory. Furthermore, optionally, the communication device further includes a communication interface coupled to the at least one processor, which can be used to input information and / or data to the at least one processor, or to output information and / or data from the at least one processor.

[0025] In one example, the communication device described in the third aspect may be an encoding device or a decoding device.

[0026] Optionally, the communication device of the third or fourth aspect can be a chip. As an example, the chip can be a modem chip, also known as a baseband chip, or a system-on-a-chip (SoC) chip containing a modem, or a system-in-package (SIP) chip, etc., without limitation.

[0027] Fourthly, a communication device is provided, including a communication interface and a circuit. In one possible implementation, the communication interface is used to acquire an information bit sequence; the circuit is used to execute an encoding method as described in a certain implementation of the first aspect to encode the information bit sequence and obtain a codeword. Optionally, the communication interface is further used to output the encoded codeword. The communication device can be an encoding device. Optionally, the communication device can be a chip. In another possible implementation, the communication interface is used to receive a channel received sequence; the circuit is used to execute a decoding method as described in a certain implementation of the second aspect to decode the channel received sequence and obtain a decoding result. Optionally, the communication interface is further used to output the decoding result. The communication device can be a decoding device. Optionally, the communication device can be a chip.

[0028] Fifthly, a computer-readable storage medium is provided, wherein computer program code or instructions are stored therein, which, when executed on a computer, cause the method as described in the first aspect or any possible implementation thereof to be implemented.

[0029] In a sixth aspect, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any of its possible implementations to be implemented.

[0030] A seventh aspect provides a wireless communication system including the communication apparatus as described in the first aspect. As an example, the communication system includes an encoding apparatus that performs an encoding method as described in some implementations of the first aspect, and a decoding apparatus that performs a decoding method as described in some implementations of the first aspect. Attached Figure Description

[0031] Figure 1 is a schematic diagram of the base matrix structure of 5G LDPC.

[0032] Figure 2 is a schematic diagram of the incremental redundancy region of the basis matrix of LDPC.

[0033] Figure 3 is a schematic diagram of the list of connection and translation values ​​for part BG1.

[0034] Figure 4 shows a schematic diagram of IRA structures of different sizes.

[0035] Figure 5 shows an example of an IRA structure generating a trap set.

[0036] Figure 6 shows an example of a communication system applicable to the technical solution of this application.

[0037] Figure 7 is a schematic diagram of the basic process of wireless communication.

[0038] Figure 8 is a schematic flowchart of the method 200 for channel coding or channel decoding provided in this application.

[0039] Figure 9 is a schematic structural diagram of a communication device provided in this application.

[0040] Figure 10 is another schematic block diagram of the communication device provided in this application.

[0041] Figure 11 is a schematic diagram of the chip (or chip system) provided in this application. Detailed Implementation

[0042] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0043] LDPC is a channel coding scheme very close to the Shannon limit and has been selected as the data channel coding scheme for the fifth generation (5G) system. The data channel in a 5G system supports a bit range of 1 to 8448. The standard describes two base graphs (BG) corresponding to the parity-check matrix: BG1 and BG2. The BG graph model of quasi-cyclic LDPC (QC-LDPC) is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the parity-check equation, and F represents the edge relationships, with a spread factor of Z. c After the QC extension, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is its edge relationship.

[0044] Tanner graphs consist of two types of nodes: variable nodes and check nodes. Variable nodes and check nodes are connected by lines based on the check matrix. In a Tanner graph, the cycle length refers to the number of edges along the shortest path from a given node, through a series of different nodes, and back to the starting node. This path is a cycle, meaning that no two nodes are repeated except for the starting and ending points. The minimum cycle length is the length of the shortest cycle among all cycle lengths in the Tanner graph. For LDPC performance evaluation, the minimum cycle length is often an important parameter.

[0045] The Tanner diagram corresponds to the parity-check matrix H, and the number of columns in the parity-check matrix N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c |Y|, the number of non-zero elements in the parity check matrix is ​​|E|=Z|F|. BG can also be written in matrix form H. BG Based on the basis matrix and lifting size Z c The basis matrix can be expanded into a complete parity-check matrix for encoding or decoding. c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size. The lifting process involves lifting the elements of the basis matrix to a value of Z. c ×Z c The basis matrix is ​​a square matrix. The elements in the basis matrix take values ​​of 0 and 1. A value of 0 represents an empty element, and a value of 1 represents an edge in the basis graph, or an association between a corresponding check and a variable. Element 0 in the basis matrix is ​​promoted to Z. c ×Z cThe zero matrix is ​​promoted to an identity matrix by its element 1, and then cyclically shifted based on the shifting value (SV) corresponding to 1. This cyclic shift can be to the left or right, which is not limited in this application. Each element 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, and 3, and the shift is to the right, the resulting cyclically shifted matrix is ​​as follows:

[0046] If the translation value is 0, the corresponding cyclically shifted matrix is:

[0047] If the shift value is 1, the corresponding cyclically shifted matrix is:

[0048] If the shift value is 3, the corresponding cyclically shifted matrix is:

[0049] The two base graphs of LDPC, BG1 and BG2, have a common matrix structure, as shown in Figure 1.

[0050] Figure 1 is a schematic diagram of the base matrix structure of 5G LDPC. The base matrix includes: part A corresponding to the information column region of high code rate; part B corresponding to the core check region of high code rate; part C of all-zero region; part D corresponding to the low code rate matrix of incremental redundancy region; and part E corresponding to the raptor-like region.

[0051] Figure 2 is a schematic diagram of the incremental redundancy region of the LDPC base matrix. As shown in Figure 2, region E adopts a Raptor-like structure, which can be progressively expanded to a low code rate from a high code rate core matrix. Within region E, the row weight (the number of 1s in each row) is equal to 1, and the column weight (the number of 1s in each column) is equal to 1. In other words, region E is an identity matrix, or can be transformed into an identity matrix through row and column permutations. The advantage of this is that the parity check position of any row in E can be encoded quickly.

[0052] In practice, QC-LDPC is represented using a base matrix BG, where each element is either 0 or 1. The 1s in the base matrix BG are expanded into a cyclic shift matrix, and the 0s are expanded into a zero matrix of the corresponding size. This expansion yields the parity check matrix.

[0053] The same BG needs to use different lifting sizes to adapt to rate matching of different code lengths. For this purpose, it is necessary to store a list of lifting sizes and a list of shift values ​​that correspond one-to-one with the rows of the lifting size list.

[0054] Table 1 is an example of a list of lift dimensions Z for LDPC.

[0055] Table 1: sets of LDPC lifting size Z

[0056] Key feature: The j-th row of the list of lifting sizes Where a j ∈{2,3,5,7,9,11,13,15}, max(k j The lift size is ∈ {7,7,6,5,5,5,4,4}; the row index of the lift size corresponds one-to-one with the column index of the shift value, that is, the lift size in each row of the lifting size list corresponds to a set of shift values. During rate matching, the lift size is determined first, and then the corresponding shift values ​​are selected to construct the check matrix.

[0057] Figure 3 is a schematic diagram of the list of edge connections and translation values ​​for part BG1. As shown in Figure 3, after selecting a lift value from the lift value list shown in Table 1, the index i corresponding to that lift value can be determined. LS According to index i LS This allows us to determine the translation values ​​corresponding to elements at different positions in the base graph. Taking Table 4 as an example, if the lift value is 96, the corresponding i... LS =1, based on i LS By querying the translation value list of the BG1 portion of the edges shown in Figure 4, we can determine that: the translation value corresponding to the element in row 0, column 0 of the base graph is 307; the translation value corresponding to the element in row 0, column 1 of the base graph is 19; the translation value corresponding to the element in row 0, column 2 of the base graph is 50, and so on. It should be understood that Figure 3 only shows the translation values ​​corresponding to a portion of the elements in row 0 of BG1.

[0058] Figure 4 shows schematic diagrams of IRA structures of different sizes. As shown in Figure 4, the main feature of the IRA structure is that it includes a double-diagonal structure and one triple column. The degree distribution consists of one triple column and the rest are double columns. In the IRA structure with QC structure, the two shift values ​​of the double column are the same, and two of the three lift values ​​of the triple column are the same (let's say 1), and the other shift value is different from this shift value (let's say 0).

[0059] As introduced in the background section, the IRA structure generates a large number of very small trapping sets at each boost value, which can easily lead to error flattening.

[0060] Figure 5 shows an example of an IRA structure generating a trap set. As shown in Figure 5, the first row corresponds to four variable nodes (position indices starting from 1, labeled 1, 6, 11, 16 respectively). This row indicates whether the corresponding variable nodes are correct. The "wrong bits" marked in Figure 4 represent the assumption that all four variable nodes are wrong. If all four variable nodes are wrong, when verifying them, in the first row of the verification matrix, the first and sixth variable nodes are both wrong, and this row cannot detect two wrong variable nodes, thus satisfying the verification. In the sixth row of the verification matrix, the sixth and eleventh variable nodes are both wrong, and no error can be detected, thus also satisfying the verification. Similarly, in the eleventh row of the verification matrix, three variable nodes participate in the verification, but the eleventh and sixteenth variable nodes are both wrong; in the sixteenth row of the verification matrix, the first and sixteenth variable nodes participate in the verification. Since both variable nodes participating in the verification are wrong, the verification relationship is satisfied. In row 15 of the parity check matrix, because three variable nodes participate in the check, a single bit error (at the first bit position) can be detected, indicating an unsatisfied check relationship. Similarly, since columns 6, 11, and 16 only involve two check equations, their errors cannot be detected. Only column 1 has three check equations; two satisfy the check equations, and one does not (i.e., the check equation corresponding to row 15), thus allowing the error to be detected. Therefore, if the IRA structure has errors in the four variable nodes shown in Figure 5, only one check equation among all the check relationships can detect this error, resulting in a TS(4,1) structure. The TS(4,1) structure represents a loop with four variable nodes. If all four variable nodes are incorrect, only one check equation can detect the error, making it difficult to correct. This creates a trap set that does not change with the increase in the lift value.

[0061] Therefore, this application provides a method for channel coding or channel decoding, which can be applied to scenarios where the boost value is increased to expand the minimum circle length of the base map under each boost value, thereby eliminating or reducing trap sets. The technical solution of this application mainly focuses on how to determine the shift values ​​of other boost values ​​within a group to their corresponding positions in the base map after determining the base boost value in each group.

[0062] Therefore, the technical problem this application aims to solve is: how to determine the baseline lift value in each group of lift values, and how to nest the translation values ​​corresponding to the baseline lift value among other lift values ​​in the same group. Nesting can reduce the size of the translation value table and decrease the storage overhead of the translation value table (e.g., the tables corresponding to BG1 and BG2). For example, BG1 contains 316 positions corresponding to translation values ​​under 51 lift values ​​(divided into 8 lift value groups, see Table 1 above), where 316 is the density of BG1. The size of the table corresponding to BG1 is 316*51. In the embodiments of this application, if a translation value group selects a lift value as the baseline lift value and stores the translation values ​​corresponding to the baseline lift value at 316 positions in the base map, then the size of the table corresponding to BG1 becomes 316*8. The translation values ​​corresponding to other lift values ​​in each position in the base map within each lift value group can be derived based on the translation values ​​corresponding to the baseline lift value at each position in the base map.

[0063] In summary, this application proposes the following design concept:

[0064] 1) In the lifting size table, select one from each group of lifting values ​​as the base lifting value A. The base lifting value A can be any lifting value in this group that is less than the maximum lifting value, such as the minimum lifting value, or a lifting value between the minimum lifting value and the maximum lifting value.

[0065] 2) Set the translation value S corresponding to the position X of the base lift value A in the base map;

[0066] 3) For lift value B, when lift value B is equal to the base lift value A, the translation value S is directly used as the translation value of lift value B at position X on the base map;

[0067] 4) For lift value B, when lift value B is in the same group as the base lift value A, and B is greater than A, the translation value corresponding to the position X of lift value B in the base map is equal to S*B / A.

[0068] 5) For lift value B, when lift value B is in the same group as the base lift value A, and B is less than A, the translation value corresponding to the position X of lift value B in the base map is equal to mod(S,B);

[0069] 6) Optionally, when the increase value is B / 2 n When B is a positive integer, that is, the boost value B is 2. n When the lift value B is an integer multiple of the base value, the translation value corresponding to the position X in the base map is 2. n Calculated using the aforementioned baseline A, the result is 2. n The translation value at position X in the base map is *B / 2 nn is a positive integer greater than or equal to 2. It should be noted that when n equals 1, the base boost is 2, resulting in more loops in the base map corresponding to the core parity region, leading to poor decoding performance. Therefore, in this embodiment, n is a positive integer greater than or equal to 2.

[0070] The above method for determining the translation value can be used in some areas of the base map, such as in the core verification area, while other areas can use the existing scheme, i.e., a hybrid approach.

[0071] The technical solutions of this application can be applied to various existing and future communication systems, including but not limited to: satellite communication systems, fifth-generation (5G) systems or new radio (NR) systems, long-term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. The technical solutions provided in this application can also be applied to future communication systems. Furthermore, they can be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems or other communication systems, etc., which are not limited herein.

[0072] The communication system applicable to this application may include one or more transmitters and one or more receivers. Optionally, one of the transmitters and receivers may be a terminal device, and the other may be a network device.

[0073] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal device in the embodiments of this application may be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. Optionally, the UE may be used as a base station. For example, the UE may act as a scheduling entity, providing sidelink signals between UEs in V2X or SL, etc.

[0074] In this embodiment, the device for implementing the functions of the terminal device can be the terminal device itself, or any device capable of supporting the terminal device in implementing those functions, such as a chip, a chip system, hardware circuitry, software modules, or a combination of hardware circuitry and software modules. This device can be installed in or used in conjunction with the terminal device. A chip system can consist of chips or include chips and other discrete components. In this embodiment, the terminal device is used as an example to illustrate the device for implementing the functions of the terminal device.

[0075] The network device in this application embodiment may include a device for communicating with a terminal device. This network device may include an access network device or a radio access network device; for example, the network device may be a base station. In this application embodiment, the access network device may refer to a radio access network (RAN) node (or device) that connects the terminal device to the wireless network. A base station can broadly encompass, or be replaced by, various names such as: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device performing base station functions in D2D, V2X, and M2M communications, a network device (e.g., a base station) in a future communication network, or a device performing network device functions. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0076] Base stations can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, a helicopter or drone can be configured as a device to communicate with another base station.

[0077] In some deployments, the network devices mentioned in the embodiments of this application may be devices including CU, DU, or CU and DU, or devices with control plane CU nodes (central unit-control plane (CU-CP)) and user plane CU nodes (central unit-user plane (CU-UP)) and DU nodes. For example, the network devices may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0078] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0079] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN / O-RAN) system, CU can also be called an open CU (open CU, O-CU), and DU can also be called an open DU (open DU, O-DU). CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0080] In this embodiment, the apparatus for implementing the functions of a network device can be a network device itself; it can also be an apparatus capable of supporting the network device in implementing those functions, such as a chip system, hardware circuitry, software module, or a combination of hardware circuitry and software module. This apparatus can be installed in or used in conjunction with the network device. In this embodiment, the example of a network device is used only to illustrate the apparatus for implementing the functions of the network device, and does not constitute a limitation on the solutions described in this embodiment.

[0081] The channel coding or decoding method provided in this application can be applied to various communication scenarios. Figure 6 shows an example of a communication system applicable to the technical solution of this application. The channel coding or decoding method provided in this application can be applied to communication between the network device and the terminal device shown in Figure 6, i.e., uplink communication or downlink communication. In this communication scenario, the transmitting end can be the terminal device in uplink communication or the network device in downlink communication, and the receiving end can be the network device in uplink communication or the terminal device in downlink communication. Furthermore, it can also be applied to other communication scenarios without limitation.

[0082] Figure 7 illustrates the basic process of wireless communication. As shown in Figure 7, at the signal transmitting end, the signal source sequentially undergoes source coding, channel coding, and digital modulation before being transmitted. At the signal receiving end, the received signal undergoes digital demodulation, channel decoding, and source decoding before being output to the destination. Among these processes, channel coding and decoding are one of the core technologies in the field of wireless communication.

[0083] The method provided in this application may specifically include an encoding method and a decoding method, i.e., a channel coding / decoding scheme, which can be used in dedicated network equipment or general-purpose equipment. It can be applied to the various network equipment (e.g., base stations) and the various terminal equipment mentioned above. Specifically, the channel coding scheme is mainly implemented through the channel coding unit (e.g., encoder) in these devices; while the channel decoding scheme is mainly implemented through the channel decoding unit (e.g., decoder) in these devices.

[0084] In the embodiments of this application, the functions of the transmitting end or the receiving end can be implemented by application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or by software (e.g., program code in memory), without limitation.

[0085] Figure 8 is a schematic flowchart of the method 200 for channel coding or channel decoding provided in this application. Steps 210-220 in method 200 can be executed by an encoding device or by a device applied to the encoding device (e.g., a chip, chip system, or circuit); alternatively, they can be executed by a decoding device or by a device applied to the decoding device (e.g., a chip, chip system, or circuit). The following embodiments use an encoding device or a decoding device as examples.

[0086] 210. Obtain the first boost value.

[0087] 220. Based on the first baseline lift value, determine the translation value corresponding to the first position of the first lift value in the base map. Wherein, the first baseline lift value is any lift value in the lift value group that is less than the maximum lift value.

[0088] In the technical solution of this application, for any boost value (e.g., a first boost value), the translation value corresponding to its position X (an example of a position) in the base map can be determined based on a reference boost value (e.g., referred to as a first reference boost value). As an example, the translation value corresponding to the position X of the first boost value in the base map is calculated based on the translation value corresponding to the position X of the first reference boost value in the base map.

[0089] As an example, there can be multiple boost values ​​for boosting the base graph to the parity check matrix. These boost values ​​can be divided into one or more boost value groups, such as the eight boost value groups shown in Table 1. Alternatively, there can be one boost value group, or other numbers of boost value groups, without limitation. For a boost value group, one boost value can be selected as the base boost value. The base boost value can be any boost value within the boost value group except for the largest boost value.

[0090] Optionally, when there are multiple lift value groups, each lift value group can have a base lift value set, thus resulting in multiple base lift values. These multiple base lift values ​​correspond one-to-one with the multiple lift value groups, and each base lift value is any lift value less than the maximum lift value in its respective group. For example, the base lift value can be the minimum value or any intermediate value. When determining the translation value corresponding to position X in the base map for a certain lift value (e.g., the first lift value), it can be determined based on one of these multiple base lift values. Specifically, a base lift value that conforms to a set relationship with the first lift value can be selected from the multiple base lift values, and then the translation value corresponding to position X in the base map for the first lift value can be determined based on the translation value corresponding to position X in the base map. In the embodiments of this application, position X is sometimes also referred to as the first position. Therefore, the translation value of the first lift value in the base map is determined based on the translation value of position X in the base map, and the translation values ​​of different lift values ​​at the same position in the base map conform to the nested characteristic.

[0091] In this embodiment of the application, as an example, the aforementioned plurality of boost value groups may refer to the eight boost value groups included in Table 1, each of which has a group index and contains several boost values. In another example, the plurality of boost value groups may also be different from the number of boost value groups in Table 1 above; this embodiment of the application does not limit this.

[0092] In some embodiments of this application, once the reference lift values ​​of multiple lift value groups are determined, the reference lift values ​​of each of the multiple lift value groups are known. Based on this, when determining the translation value corresponding to any lift value at a certain position (e.g., the first position, or position X) in the base map, it can be determined based on the translation value corresponding to the first reference lift value among the multiple reference lift values ​​at the first position in the base map.

[0093] Optionally, the first boost value can be determined from multiple boost values ​​based on the following conditions: In one example, if the first boost and the first boost value belong to the same group, the first boost value may be greater than or equal to the first boost value; in another example, the first boost value is an integer multiple of the first boost value, and the first boost value is a positive integer power of 2. In other words, if the first boost value is a positive integer power of 2, and a boost value 'a' among the multiple boost values ​​is a positive integer power of 2, then the boost value 'a' is used as the first boost value. Furthermore, as another example, the first boost value can also be a boost value itself.

[0094] In these different implementations, the translation value of the first lift value at the first position (i.e., position X) in the base graph can be determined based on the translation value of the first reference lift value at position X in the base graph. Some examples are given below. For clarity and ease of understanding in the description of the scheme, the eight lift value groups shown in Table 1 are used as examples of "multiple lift value groups" in the above embodiments. That is, the multiple lift value groups can be eight lift value groups, and the number and specific values ​​of the lift values ​​contained in each lift value group are shown in Table 1.

[0095] Furthermore, after determining the translation value corresponding to the first position of the first lift value in the base map, the encoding device or the decoding device can perform further operations based on the translation value, respectively.

[0096] As an example and as an optional step, the encoding device may perform one or more of steps 230 to 250.

[0097] 230. The basis matrix is ​​expanded based on the translation value corresponding to the first position of the first lift value in the base graph to obtain the parity matrix.

[0098] It should be noted that, in addition to determining the translation value corresponding to the first position of the first lift value in the base graph, the translation values ​​of other positions in the base graph besides the first position also need to be determined in order to expand the basis matrix and obtain the complete parity-check matrix. Here, if the first position is any position in the base graph, the translation value corresponding to any position in the base graph is determined according to the method provided in this application; if the first position is a partial position in the base graph, other methods can be used, such as the method in 5G for determining the translation value of a certain position in the base graph, to determine the translation values ​​corresponding to other positions besides the first position. Thus, after obtaining the translation value corresponding to each position (except for empty elements) in the base matrix, the basis matrix can be expanded based on the first lift value and the translation values ​​of these positions to obtain the parity-check matrix.

[0099] 240. Encode the information bit sequence based on the parity check matrix to obtain codewords.

[0100] 250. Output the codeword.

[0101] As an example and as an optional step, the decoding device may perform one or more of steps 260 to 280.

[0102] 260. The basis matrix is ​​expanded based on the translation value corresponding to the first position of the first lift value in the base graph to obtain the parity matrix.

[0103] See the explanation in step 230, which will not be repeated here.

[0104] 270. Decode the channel received sequence based on the parity check matrix.

[0105] 280. Output the decoding result.

[0106] In Figure 8, steps 230 and 260 are represented by a step box.

[0107] As can be seen from the above description, in some embodiments of this application, a group of boost values ​​can be set, and one boost value can be selected as the base boost value. Optionally, multiple groups of boost values ​​can also be set, and one boost value can be selected as the base boost value from the multiple boost values ​​contained in each group. The other boost values ​​in each boost value group, besides the base boost value, can be nested using the translation values ​​of the base boost value at the corresponding positions in the base map. Some specific examples are given below.

[0108] Example 1

[0109] The boost value groups are set as shown in Table 1 above. There are a total of 8 boost value groups, with each group containing 5 to 8 boost values. The j-th boost value in the i-th group is a. i,j =a i,0 ×2 jBoth i and j are integers.

[0110] In row 1, column 22 of BG1 (index starts with 0 as an example), set up Table 2 as follows.

[0111] Table 2

[0112] In row 3, column 22 of BG1 (index starts with 0 as an example), set Table 3 as follows.

[0113] Table 3

[0114] It should be understood that the first row and 22nd column of BG1 above is an example of the first position or position X in BG1, and the third row and 22nd column of BG1 is another example of the first position or position X in BG1. Obviously, position X can also be any other position in the base graph. When the position is changed, the method for determining the translation value corresponding to the corresponding position of the first lift value in the base graph is similar.

[0115] Suppose that the baseline boost value for this region is [16, 12, 10, 14, 9, 11, 13, 15]. These 8 baseline boost values ​​correspond one-to-one with the above 8 boost value groups. For example, 16 is the baseline boost value set in the boost value group with index 0, 12 is the baseline boost value set in the boost value group with index 1, and so on.

[0116] When the promotion value B is 224 (an example of the first promotion value), the promotion value 224 belongs to index 3 (i.e., i). LS =3) of the promotion value group, i LS The base lift value in the lift group corresponding to =3 is 14 (that is, the base lift value A = 14). In this case, if the first lift value and the base lift value A belong to the same group, and the first lift value B is greater than the base lift value A, then the translation value corresponding to the position X of the lift value B in the base map is equal to S*B / A. Here, S refers to the translation value corresponding to the position X of the base lift value A in the base map.

[0117] In BG1, at row 1, column 22, i LS =3 corresponds to a translation value S of 1. Therefore, the translation value of the lift value 224 in the 1st row and 22nd column of BG1 is S*B / A = 1 × 224 / 14 = 16; in the 3rd row and 22nd column of BG1, i LS =3 corresponds to a translation value S of 6; the translation value of the lift value 224 in the 3rd row and 22nd column of BG1 is S*B / A = 6 × 224 / 14 = 96.

[0118] At this point, the minimum circle length under this setting is the maximum value that the base graph corresponding to the core verification region can reach, which is 18.

[0119] In Example 1, the minimum circle length of the base graph corresponding to the core check region with an increase value of 224 is increased from 8 to 18, while still maintaining compatibility with low-complexity encoding.

[0120] Example 2

[0121] The boost value groups are set as shown in Table 1 above. There are a total of 8 boost value groups, with each group containing 5 to 8 boost values. The j-th boost value in the i-th group is a. i,j =a i,0 ×2 j , where i and j are both integers.

[0122] In row 1, column 22 of BG1 (index starts with 0 as an example), set Table 4 as follows.

[0123] Table 4

[0124] In row 3, column 22 of BG1 (index starts with 0 as an example), set Table 5 as follows.

[0125] Table 5

[0126] Suppose that the baseline lift value for this region is [16,12,10,14,9,11,13,15].

[0127] When the boost value B is 7, the boost value 7 belongs to i. LS =3 corresponds to the boost value group, i LS =3 corresponds to a base lift value of 14 in the lift value group. In this case, if the first lift value and the base lift value A belong to the same group, and the first lift value B is less than the base lift value A, then the translation value corresponding to the position X of the lift value B in the base map is equal to mod(S,B). Here, S refers to the translation value corresponding to the position X of the base lift value A in the base map.

[0128] In BG1, at row 1, column 22, i LS =3 corresponds to a translation value S of 1; at the 3rd row and 22nd column of BG1, i LS =3 corresponds to a shift value S of 6; the lift value 7 and the base lift value 14 are in the same group, and 7 is less than 14. Therefore, the shift value of the lift value 7 in the 1st row and 22nd column of BG1 is mod(S,B) = mod(1,7) = 1; the shift value of the lift value 7 in the 3rd row and 22nd column of BG1 is mod(S,B) = mod(6,7) = 6.

[0129] In Example 2, the minimum circle length of the base map corresponding to the core check region is increased from 8 to 16 when the boost value is 7. Given certain characteristics of the translation value corresponding to the core check region, the encoding process can be decomposed into B / A independent encodings of matrices of size A*A. Compared to encoding a larger-dimensional check matrix, the encoding complexity is very low because the code length is shorter. Furthermore, it can be seen that the encoding complexity depends on the size of the independently encoded matrices, that is, on the size of the base boost value A. Therefore, the smaller the base boost value A, the lower the encoding complexity.

[0130] Example 3

[0131] When determining the translation value at certain locations in the base map, the corresponding base lift value is modified, while the base lift value at other locations is not modified. That is, at other locations in the base map, the maximum lift value in each lift value group can be used as the base lift value.

[0132] For example, in 5G NR's BG1, suppose we set the translation values ​​for three positions (example of the first position) in the region of rows 0-3 and column 22, with corresponding base boost values ​​of [16, 12, 10, 14, 9, 11, 13, 15]. The base boost values ​​for other regions besides the first position remain [256, 384, 320, 224, 288, 352, 208, 240], meaning each base boost value is the maximum boost value in its respective boost value group. To shift the first position...

[0133] In this example, the use of reference boost values ​​at locations other than specific ones is compatible with current 5G methods.

[0134] Therefore, only the positions listed in Table 6 below use the boost value provided by this application, while other positions use the maximum boost value. Thus, only positions using the boost value provided by this application will trigger the method of determining the translation value provided by this application; other positions, because their boost values ​​are all less than the set maximum boost value, will perform a modulo operation.

[0135] Table 6

[0136] It should be noted that Table 6 lists the translation values ​​for the three positions mentioned above together. In Example 3, the lift values ​​for certain positions where the IRA structure circle is small and prone to causing incorrect leveling are modified, while the current maximum lift value is kept unchanged in other positions, thus maximizing compatibility with existing usage methods.

[0137] Example 4

[0138] When the boost value B is greater than 2 n And Q = B / 2 nWhen the value is an integer greater than 1, the shift of the lift value B at position X on the base map is: 2. n The corresponding shift value is multiplied by Q, where n is a positive integer greater than or equal to 2. In other words, when there are 2 among multiple baseline lift values... n And Q (Q = B / 2) n When choosing 2 n The first lift value is used as the first reference lift value to calculate the translation value of the first lift value at position X in the base map. Therefore, Example 4 is an implementation of selecting the first reference lift value from multiple reference lift values.

[0139] For example, at line 1, position 22 of BG1 (indexing starts from 0), the following table is set:

[0140] In row 3, column 22 of BG1 (using index 0 as an example), set the following table:

[0141] Meanwhile, the baseline lift value corresponding to the translation value of this region is [16,12,10,14,9,11,13,15].

[0142] When the boost value B is 224, the boost value 224 is 16 (16 = 2). 4 14 times that of i, 16 is i LS The baseline boost value in the boost value group where =0. At row 1, column 22 in BG1, i LS =0 corresponds to a translation value S of 1; at the 3rd row and 22nd column of BG1, i LS =0 corresponds to a shift value S of 6. Therefore, the shift value of the lift value B in the 1st row and 22nd column of BG1 is (224 / 16)×1=14; the lift value of the lift value B in the 3rd column and 22nd row of BG1 is (224 / 16)×4=56.

[0143] In the setup of Example 4, the minimum circle length of the base graph corresponding to the core check region is 18. The method in Example 4 can be used when the boost value is large, allowing different boost values ​​to use the same encoding structure, thus reducing encoding complexity.

[0144] Example 5

[0145] The boost value groups are set as shown in Table 1 above. There are a total of 8 boost value groups, with each group containing 5 to 8 boost values. The j-th boost value in the i-th group is a. i,j =a i,0 ×2 j , where i and j are both integers.

[0146] For example, in row 1, column 22 of BG1 (index starts from 0), set the following table:

[0147] In row 3, column 22 of BG1 (using index 0 as an example), set the following table:

[0148] Meanwhile, the lift value corresponding to the translation value of this region is [8, 12, 10, 7, 9, 11, 13, 15]. It can be observed that in Example 1, i LS The boost value when i = 0 is set to 16, i LS When i = 3, the boost value is set to 14; while in Example 5, i LS The boost value when i = 0 is set to 8, i LS The boost value for a value of 3 is set to 7.

[0149] When the boost value B is 224, 224 = 7 × 32, and at the same time, i LS =0 corresponds to a translation value of 1 in the 1st row and 22nd column of the base graph, i LS =3 corresponds to a translation value of 3 in the 3rd row and 22nd column of the base chart. Therefore, the translation value of the lift value B in the 1st row and 22nd column of the base chart is S*B / A = 1 × (224 / 7) = 32; the translation value of the lift value B in the 3rd row and 22nd column of the base chart is S*B / A = 3 × (224 / 7) × 3 = 96.

[0150] In this setup of Example 5, the baseline boost value is 8 or 7, or at 2... n When the base lift is a multiple of 12, 10, 9, 11, 13, 15, or 2 of these values, the minimum circle length of the base map can reach 16. n When the value is a multiple of the core check region, the base graph corresponding to the core check region can reach the maximum value of the minimum circle length in the corresponding dimension (referring to the size of the sub-matrix corresponding to the core check region, such as 4 rows and 4 columns or 3 rows and 3 columns, etc.). For example, the maximum value of the minimum circle length of the base graph corresponding to the 4 rows and 4 columns base matrix is ​​18, and the maximum value of the minimum circle length of the base graph corresponding to the 3 rows and 3 columns base matrix is ​​14.

[0151] For example, if we set the following table at row 1, column 22 of BG1 (index starts from 0):

[0152] In row 3, column 22 of BG1 (using index 0 as an example), set the following table:

[0153] Furthermore, if the shift value for this region corresponds to a lift value of [8,6,5,7,9,11,13,15], then under this setting, i LS The boost value when i = 1 is set to 6, i LS The boost value for a value of 2 is set to 5.

[0154] When the lift value B is 224, the shift of lift value B in the 1st row and 22nd column of the base chart is (224 / 7)×1 = 32; the shift of lift value B in the 3rd row and 22nd column of the base chart is (224 / 7)×3 = 96. Under this setting, the base lift value is 5 or 6, or 2 of their respective values. n When the base gain is a multiple of 14, the maximum value of the minimum circle length of the base map can reach 14. When the base gain is 8 or 7 or 2 of these values... n When the base map is a multiple of 16, the maximum value of the minimum circle length can reach 16. When the base lift is 9, 11, 13, 15, or 2 of these values... n When the value is a multiple of , the base map can reach the maximum value of the minimum circle length in the corresponding dimension.

[0155] The design used in Example 5 aims to achieve a minimum loop length of 14 that remains unchanged regardless of shift or boost values ​​when combined with the system bit matrix. Therefore, the loop length of 14 corresponding to the core check region has reached the overall minimum, or the loop length of 16 is slightly higher than the overall minimum, but may reach the overall minimum after combination. Simultaneously, a smaller baseline boost value results in lower coding complexity.

[0156] Example 6

[0157] Set when the boost value B is greater than 2 n Furthermore, the baseline boost values ​​set in each of the multiple boost value groups include 2. n And Q, Q = B / 2 n When n is a positive integer and Q is an integer greater than 1, use 2. n As the first baseline lift value, the translation value corresponding to the first position of the lift value B on the base map is S·(B / 2). n Unlike Example 4, the baseline boost value is set differently.

[0158] For example, at line 1, position 22 of BG1 (indexing starts from 0), the following table is set:

[0159] In row 3, column 22 of BG1 (using index 0 as an example), set the following table:

[0160] Suppose that the lift value corresponding to the translation value of this region is [8, 12, 10, 14, 9, 11, 13, 15]. It can be observed that in Example 4, i LS The boost value when i = 0 is set to 16, while in Example 6, i LS The lift value when =0 is set to 8. According to the rule for determining the translation value in Example 4, when the baseline lift value includes 2... n And Q = B / 2n The shift of the lift value B at position X on the base map is 2 n It is used as a baseline for calculation.

[0161] Therefore, when the lift value B is 224, 224 = 8 × 24. Thus, the translation value of the lift value B in the 1st row and 22nd column of the base chart is (224 / 8) × 1 = 14; the translation value of the lift value B in the 3rd row and 22nd column of the base chart is (224 / 8) × 3 = 64.

[0162] The minimum circle length under this setup is 16, which is already a relatively large circle length, and it is greater than the minimum circle length after combining with the system matrix. Furthermore, compared to Example 4, the complexity is reduced by half.

[0163] In the technical solution of this application, when determining the translation value corresponding to a certain boost value (e.g., a first boost value), it can be determined based on the translation value of the first reference boost value at that position in the base map. When the first boost value increases relative to the first reference boost value, for example, when it is a positive integer multiple of the first reference boost value, the translation value corresponding to the first boost value at position X in the base map is a multiplier of the translation value of the first reference boost value at position X in the base map; while when the first boost value decreases relative to the first reference boost value, the translation value corresponding to the first boost value at position X in the base map is modulo the translation value S of the first reference boost value at position X in the base map. Under different boost values, the minimum circle length corresponding to the core parity submatrix is ​​increased, which can improve or avoid trap sets and improve decoding performance.

[0164] The above is a detailed description of the method for channel coding or channel decoding provided in this application. The following describes the communication device provided in this application.

[0165] Figure 9 is a schematic structural diagram of the communication device 1000 provided in this application. The communication device 1000 can be an encoding device, or a device applied to an encoding device and capable of implementing the corresponding functions of the encoding device in the method embodiments of this application, such as a chip, chip system, or circuit. Alternatively, the communication device 1000 can be a decoding device, or a device applied to a decoding device and capable of implementing the corresponding functions of the decoding device in the method embodiments of this application, such as a chip, chip system, or circuit.

[0166] Optionally, the communication device 1000 includes a processing module 1001, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 1000 is an encoding device or a device applied to an encoding device, the processing module 1001 is used to determine the translation value corresponding to the first boost value at the first position in the base map based on the first boost value. Further, the processing module 1001 determines a parity check matrix based on the translation value corresponding to the first position in the base map and the base matrix. Optionally, the information bit sequence can also be encoded based on the parity check matrix to obtain codewords. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here. When the communication device 1000 is a decoding device or a device applied to a decoding device, the processing module 1001 is used to determine the translation value corresponding to the first boost value at the first position in the base map based on the first boost value. Further, the processing module 1001 determines a parity check matrix based on the translation value corresponding to the first position in the base map and the base matrix. Optionally, the channel received sequence can also be decoded (or decoded) based on the parity check matrix to obtain a decoding result. For details on the specific process, please refer to the detailed description of the corresponding steps in the method embodiment; they will not be repeated here.

[0167] Optionally, the communication device 1000 further includes a communication module 1002, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 1000 is an encoding device or a device applied to an encoding device, the communication module 1002 may be used to acquire one or more of the following: information indicating a first boost value, information indicating a translation value corresponding to a first position of the first reference boost value in the base map, information indicating the base matrix, etc., so as to send this information to the processing module 1001 for processing. Optionally, the communication module 1002 may also be used to output the codeword obtained by the processing module 1001 encoding the information bit sequence. When the communication device 1000 is a decoding device or a device applied to a decoding device, similarly, the communication module 1002 may be used to acquire one or more of the following: information indicating a first boost value, information indicating a translation value corresponding to a first position of the first reference boost value in the base map, information indicating the base matrix, etc., so as to send this information to the processing module 1001 for processing. Optionally, the communication module 1002 can also be used to output the decoding result determined by the processing module 1001.

[0168] Furthermore, it should be noted that the aforementioned communication module and / or processing module can be implemented through virtual modules. For example, the processing module can be implemented through software functional units or virtual devices, and the communication module can be implemented through software functions or virtual devices. Alternatively, the processing module or communication module can also be implemented through physical devices, such as chips / circuits (e.g., integrated circuits or logic circuits). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., integrated circuits, logic circuits).

[0169] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0170] Figure 10 is a schematic block diagram of another communication device 1100 provided in this application. As shown, the communication device 1100 includes at least one processor 1110, which implements the functions of the encoding or decoding device described in the foregoing method embodiments.

[0171] Optionally, the processor 1110 is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. The communication device 1100 may also include at least one memory 1120. The memory 1120 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1110 can execute the computer programs, instructions, or data stored in the memory 1120 to complete the method applied to channel coding or channel decoding in any of the above method embodiments.

[0172] Optionally, the communication device 1100 may further include a communication interface 1130, through which the communication device 1100 can interact with other devices. For example, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other type of interface.

[0173] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1110 may operate in conjunction with the memory 1120 and the communication interface 1130. This application does not limit the specific connection medium between the processor 1110, the memory 1120, and the communication interface 1130.

[0174] Figure 11 is a schematic diagram of the chip (or chip system) provided in this application. The chip (or chip system) 30 may include a circuit 31 and an input / output interface 32. The circuit 31 may be a logic circuit, an integrated circuit, etc., and the input / output interface 32 may be an input / output circuit or an interface circuit, capable of inputting information (or receiving information) and outputting information (or transmitting information). Optionally, the chip system may be composed of a chip or may include chips and other discrete devices. The chip 30 can be used to execute the channel coding method executed by the encoding device or the channel decoding method executed by the decoding device in the various embodiments of this application.

[0175] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause operations and / or processes performed by an encoding or decoding device in the various method embodiments of this application to be executed.

[0176] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the encoding or decoding device in the various method embodiments of this application are executed.

[0177] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by an encoding or decoding device in any method embodiment are performed.

[0178] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0179] This application provides a communication system, including the encoding device and decoding device in the above method embodiments.

[0180] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), or a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly embodied in the execution of the hardware processor, or executed by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0181] The memory can be non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). Memory is any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited to this. The memory in this application can also be a circuit or any other device capable of implementing a storage function for storing program instructions and / or data.

[0182] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0183] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0184] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0185] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0186] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0187] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0188] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0189] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0190] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for channel coding or channel decoding, characterized in that, include: Obtain the first boost value; Based on the first reference lift value, determine the translation value corresponding to the first position of the first lift value in the base map, wherein the first reference lift value is any lift value in the lift value group that is less than the maximum lift value.

2. The method according to claim 1, characterized in that, The step of determining the translation value corresponding to the first position of the first boost value in the base map based on the first benchmark boost value includes: A first benchmark boost value is determined from multiple benchmark boost values, wherein each of the multiple benchmark boost values ​​corresponds to a multiple boost value group; Based on the translation value corresponding to the first position of the first reference lift value in the base map, determine the translation value corresponding to the first position of the first lift value in the base map. Wherein, the first boost value and the first base boost value belong to the same boost value group, or the first boost value is an integer multiple of the first base boost value and the first base boost value is an integer power of 2.

3. The method according to claim 2, characterized in that, When the first boost value is the first benchmark boost value among the plurality of benchmark values, the translation value corresponding to the first position of the first boost value in the base map is the first translation value, and the first translation value is the translation value corresponding to the first position of the first benchmark boost value in the base map.

4. The method according to claim 2, characterized in that, When the first boost value and the first reference boost value among the plurality of reference values ​​are located in the same boost value group, and the first boost value is greater than the first reference boost value, the translation value corresponding to the first position of the first boost value in the base map is S·(B / A), where B is the first boost value, A is the first reference boost value, S is the translation value corresponding to the first position of the first reference boost value in the base map, and S, B and A are all positive integers.

5. The method according to claim 2, characterized in that, When the first boost value and the first reference boost value among the plurality of reference values ​​are in the same boost value group, and the first boost value is less than the first reference boost value, the translation value corresponding to the first position of the first boost value in the base map is mod(S,B), where mod is the modulo operation, B is the first boost value, S is the translation value corresponding to the first position of the first reference boost value in the base map, and S and B are positive integers.

6. The method according to claim 2, characterized in that, When the plurality of benchmark boost values ​​include 2 n And Q, Q = B / 2 n n is an integer greater than or equal to 2, Q is an integer greater than 1, B is the first boost value, and the first base boost value is determined to be 2. n The translation value corresponding to the first position of the first boost value on the base map is S·(B / 2). n ), where S is the offset of the first reference lift value at the first position on the base map.

7. The method according to any one of claims 1 to 6, characterized in that, The first position is any position in the base map.

8. The method according to any one of claims 1 to 6, characterized in that, The first position is a partial position of the base map. The translation values ​​corresponding to other positions of the base map other than the first position are determined based on multiple reference lift values. Each of the multiple reference lift values ​​corresponds to a multiple lift value group, and each reference lift value is the maximum value in its respective lift value group.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: Based on the translation value corresponding to the first position of the first lift value in the base graph, the base matrix is ​​expanded to obtain the parity matrix; The information bit sequence is encoded based on the aforementioned check matrix; Output the codeword obtained from the encoding.

10. The method according to any one of claims 1 to 8, characterized in that, The method further includes: Based on the translation value corresponding to the first position of the first lift value in the base graph, the base matrix is ​​expanded to obtain the parity matrix; The channel received sequence is decoded based on the aforementioned check matrix; Output the decoding result.

11. A communication device, characterized in that, include: The communication module is used to obtain the first boost value; The processing module is used to determine, based on the first reference lift value, the translation value corresponding to the first position of the first lift value in the base map, wherein the first reference lift value is any lift value in the lift value group that is less than the maximum lift value.

12. The communication device according to claim 11, characterized in that, The step of determining the translation value corresponding to the first position of the first boost value in the base map based on the first benchmark boost value includes: A first benchmark boost value is determined from the plurality of benchmark boost values, wherein each of the plurality of benchmark boost values ​​corresponds to a plurality of boost value groups; Based on the translation value corresponding to the first position of the first reference lift value in the base map, determine the translation value corresponding to the first position of the first lift value in the base map. Wherein, the first boost value and the first base boost value belong to the same boost value group, or the first boost value is an integer multiple of the first base boost value and the first base boost value is an integer power of 2.

13. The communication device according to claim 12, characterized in that, When the first boost value is the first benchmark boost value among the plurality of benchmark values, the translation value corresponding to the first position of the first boost value in the base map is the first translation value, and the first translation value is the translation value corresponding to the first position of the first benchmark boost value in the base map.

14. The communication device according to claim 12, characterized in that, When the first boost value and the first reference boost value among the plurality of reference values ​​are located in the same boost value group, and the first boost value is greater than the first reference boost value, the translation value corresponding to the first position of the first boost value in the base map is S·(B / A), where B is the first boost value, A is the first reference boost value, S is the translation value corresponding to the first position of the first reference boost value in the base map, and S, B and A are all positive integers.

15. The communication device according to claim 12, characterized in that, When the first boost value and the first reference boost value among the plurality of reference values ​​are in the same boost value group, and the first boost value is less than the first reference boost value, the translation value corresponding to the first position of the first boost value in the base map is mod(S,B), where mod is the modulo operation, B is the first boost value, S is the translation value corresponding to the first position of the first reference boost value in the base map, and S and B are positive integers.

16. The communication device according to claim 12, characterized in that, When the plurality of benchmark boost values ​​include 2 n And Q, Q = B / 2 n n is an integer greater than or equal to 2, Q is an integer greater than 1, B is the first boost value, and the first base boost value is determined to be 2. n The translation value corresponding to the first position of the first boost value on the base map is S·(B / 2). n ), where S is the offset of the first reference lift value at the first position on the base map.

17. The communication device according to any one of claims 11 to 16, characterized in that, The first position is any position in the base map.

18. The communication device according to any one of claims 11 to 16, characterized in that, The first position is a partial position of the base map. The translation values ​​corresponding to other positions of the base map other than the first position are determined based on multiple reference lift values. Each of the multiple reference lift values ​​corresponds to a multiple lift value group, and each reference lift value is the maximum value in its respective lift value group.

19. The communication device according to any one of claims 11 to 18, characterized in that, The processing module is also used for: Based on the first boost value and the translation value corresponding to the first position in the base graph, the base matrix is ​​expanded to obtain the parity matrix. The information bit sequence is encoded based on the aforementioned check matrix; Furthermore, the communication module is also used to: output the encoded codeword.

20. The communication device according to any one of claims 11 to 18, characterized in that, The processing module is also used for: Based on the first boost value and the translation value corresponding to the first position in the base graph, the base matrix is ​​expanded to obtain the parity matrix. The channel received sequence is decoded based on the aforementioned check matrix; In addition, the communication module is also used to output the decoding result.

21. A communication device, characterized in that, The device includes a communication interface and a circuit, wherein the communication interface is used to acquire information required to perform the method as described in any one of claims 1 to 10, and to send the information to the circuit; the circuit is used to perform the method as described in any one of claims 1 to 10 based on the received information.

22. A communication device, characterized in that, Includes modules or units for performing the method as described in any one of claims 1-10.

23. A communication device, characterized in that, The device includes a processor coupled to a memory, the processor being configured to execute a computer program or instructions stored in the memory to cause the communication device to perform the method as described in any one of claims 1-10.

24. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-10.

25. A wireless communication system, characterized in that, Includes the communication device as described in any one of claims 11-20.

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