Top electrode configuration in a semiconductor chip

Abstract

Herein is provided a semiconductor chip (100), comprising a device wafer portion (101) and a cap wafer portion (202) bonded together, wherein the chip (100) comprises a device (110) and a top electrode (202) located on different wafer portions Herein is further provided an apparatus comprising at least one semiconductor chip (100).

Description

[0001] TOP ELECTRODE CONFIGURATION IN A SEMICONDUCTOR CHIP

[0002] TECHNICAL FIELD

[0003] The present disclosure generally relates to the field of semiconductors. The disclosure relates particularly, though not exclusively, to top electrodes of semiconductor devices.

[0004] BACKGROUND

[0005] This section illustrates useful background information without admission of any technique described herein representative of the state of the art.

[0006] Ageing of materials implies changes of the original state of the materials. These changes can be, for instance, changes in material properties. Some materials experience ageing more than others. By way of an example, silicon is a rather stable material when it comes to ageing, but on the other hand certain metals experience changes in grain size due to ageing. In case the materials experiencing ageing changes are used in the context of semiconductors, the changes of material properties due to ageing may lead to changes in the semiconductor properties.

[0007] SUMMARY

[0008] The appended claims define the scope of protection. Any examples and technical descriptions of apparatuses, products and / or methods in the description and / or drawings not covered by the claims are presented not as embodiments of the invention but as background art or examples useful for understanding the invention.

[0009] It is an object of certain embodiments of the present disclosure to provide a scheme to solve at least one of the problems related to the prior art, or at least to provide an alternative to existing technology. Accordingly, certain disclosed embodiments provide for an ingenious semiconductor apparatus solving at least one of the problems related to the prior art. According to a first example aspect of the present disclosure there is provided a semiconductor chip, comprising a device wafer portion and a cap wafer portion bonded together, wherein the chip comprises a device and a top electrode located on different wafer portions.

[0010] In certain embodiments, the semiconductor chip comprises a bottom wafer portion and a cap wafer portion bonded together. As used herein, the bottom wafer portion is understood as a synonym for the device wafer portion in accordance with certain embodiments.

[0011] In certain embodiments, the device and the top electrode of the device are located on different wafer portions. In certain embodiments, the device and the top electrode thereof are located on different wafer portions. In certain embodiments, the device and its top electrode are located on different wafer portions.

[0012] In certain embodiments, the chip comprises a top electrode and a bottom electrode. In certain embodiments, the top electrode and the bottom electrode are located in different wafer portions. In certain embodiments, the top electrode and the bottom electrode are located in different wafer portions, one in the device wafer portion and the other in the cap wafer portion. In certain embodiments, the top electrode and the bottom electrode are located in different wafer portions, the bottom electrode in the device wafer portion and the top electrode in the cap wafer portion.

[0013] In certain embodiments, the device and the top electrode of said device are located on different wafer portions, and wherein said top electrode is electrically coupled over a gap to the opposing wafer portion. In certain embodiments, the device and the top electrode of said device are located on different wafer portions, and wherein said top electrode is electrically coupled over a gap to a piezoelectric layer.

[0014] In certain embodiments, the device and the top electrode are not in the same wafer portion. In certain embodiments, the device and the top electrode are located on different wafer portions, one on the device wafer portion and one on the cap wafer portion. In certain embodiments, the device is (located) in the device wafer portion and the top electrode is (located) in the cap wafer portion. In certain embodiments, the device wafer portion is absent of a top electrode. In certain embodiments, the device wafer portion is absent from a top electrode. In certain embodiments, the top electrode of the device is separated from the device itself. In certain embodiments, the top electrode of the device is separated from the device itself by providing the top electrode in a different wafer portion than the device. In certain embodiments, the top electrode of the device is separated from the device itself by an air gap.

[0015] In certain embodiments, the device wafer portion and the cap wafer portion are bonded together to form an enclosure for the device. In certain embodiments, the top electrode is arranged on the cap wafer portion inside the enclosure. In certain embodiments, the top electrode is arranged to face the device inside the enclosure.

[0016] According to certain embodiments, the bonding comprises a thermocompression bonding. In certain embodiments, the bonding comprises eutectic bonding, or flip-chip bonding. In certain alternative embodiments, the bonding comprises glass frit bonding, anodic bonding, or adhesive bonding. In certain embodiments, the bonding occurs in a vacuum. In certain embodiments, the enclosure between the cap wafer portion and the device wafer portion is in a vacuum.

[0017] In certain embodiments, the top electrode is electrically coupled over a gap to the device layer portion. In certain embodiments, the top electrode is electrically coupled over a gap to the topmost layer of the device layer portion. In certain embodiments, the top electrode is electrically coupled over a gap to the piezoelectric layer of the device layer portion. In certain embodiments, the top electrode is electrically coupled over a gap to the piezoelectric layer of the device. In certain embodiments, the top electrode allows current to be transferred (from the top electrode) to the device wafer portion. In certain embodiments, the top electrode is sufficiently close to the device wafer portion to allow current to travel over the gap (between the top electrode and the device wafer portion). In certain embodiments, charge carriers (electrical current, current, charges, flow of charge carriers) travel across the gap. In certain embodiments, charge carriers are configured to travel across the gap. In certain embodiments, charge carriers travel from the top electrode across the gap to the piezoelectric layer.

[0018] In certain embodiments, said top electrode is electrically coupled over a gap to a piezoelectric layer, such that current travels over the gap. In certain embodiments, said top electrode is electrically coupled over a gap to a piezoelectric layer, such that charge carriers travel over the gap. In certain embodiments, the gap between the top electrode and the device wafer portion (the topmost layer of the device wafer portion) is less than 500 nm, such as less than 400 nm. In certain preferred embodiments, the gap between the top electrode and the device wafer portion is less than 100 nm.

[0019] In certain embodiments, the device is bent (upwards). In certain embodiments, the top electrode is bent (downwards). In certain embodiments, the device and the top electrode are bent towards one another (to minimize the gap therebetween). In certain embodiments, the device is bent upwards and / or the top electrode is bent downwards to minimize the gap therebetween.

[0020] In certain embodiments, the chip comprises a point of controlled contact. In certain embodiments, the point of controlled contact is a raised feature. In certain embodiments, the point of controlled contact is a raised feature arranged onto the device (surface). In certain embodiments, the point of controlled contact is configured to localize contact between the top electrode and the device.

[0021] In certain embodiments, the point of controlled contact is provided in an area having lowest displacement of the device. In certain embodiments, the point of controlled contact is provided in an area having highest transduction of the device. In certain embodiments, the point of controlled contact is provided in a central (centre) area of the device. In certain embodiments, the point of controlled contact is provided in a (most) bent area of the device.

[0022] In certain embodiments, the top electrode is electrically coupled to a through silicon via, TSV. In certain embodiments, the bottom electrode is electrically coupled to another through silicon via, TSV. In certain embodiments, the semiconductor chip comprises through silicon vias, TSVs adapted to (configured to) provide electrical connection to the cap wafer portion and to the device wafer portion (respectively). In certain embodiments, the chip comprises through silicon vias, TSVs, configured to provide electrical connection from outside the chip through the cap wafer portion to both the cap wafer portion and to the bottom wafer portion. In certain embodiments, the chip comprises through silicon vias, TSVs, configured to provide electrical connection from outside the chip through the same wafer portion to both the cap wafer portion and to the bottom wafer portion. In certain embodiments, the through silicon vias, TSVs, are arranged both on (through, enter through) the cap wafer portion. In certain embodiments, the through silicon vias, TSVs, are arranged (enter the chip) both on the same side (not opposite sides of the chip). In certain embodiments, one of the through silicon vias, TSVs, (a first through silicon via) is configured to provide electrical connection through the cap wafer portion to the top electrode. In certain embodiments, one of the through silicon vias, TSVs, (a second through silicon via) is configured to provide electrical connection through the cap wafer portion to the device wafer portion (for the bottom electrode). In certain embodiments, the through silicon vias, TSVs are configured to provide electrical connection from outside the chip through the cap wafer portion to the device wafer portion.

[0023] In certain embodiments, the current (electrical flow) is configured to enter the chip via the first through silicon via through the cap wafer portion for the top electrode of the chip. In certain embodiments, the current (electrical flow) is configured to be transferred between the top electrode and the piezoelectric layer of the device, reaching the bottom electrode (a silicon layer) thereafter. In certain embodiments, the current is configured to exit the chip via the second through silicon via, from the bottom electrode through the cap wafer portion.

[0024] In certain embodiments, the chip (the device wafer portion, the cap wafer portion) is fabricated on a substrate. In certain embodiments, the substrate is a wafer. In certain embodiments, the substrate is a silicon wafer.

[0025] In certain embodiments, the substrate is a silicon-on-insulator, SOI, wafer. In certain embodiments, the substrate is a cavity silicon-on-insulator, CSOI, wafer. In certain embodiments, the substrate is a silicon-on-insulator, SOI, substrate, or a cavity silicon-on- insulator, CSOI, substrate.

[0026] In certain embodiments, the substrate comprises a buried oxide layer, BOX. In certain embodiments, the buried oxide layer is between a handle layer and a device layer. In certain embodiments, the handle layer and the device layer comprise silicon. In certain embodiments, the substrate comprises a cavity.

[0027] In certain embodiments, the device wafer portion comprises silicon (a silicon layer). In certain embodiments, the device wafer portion comprises silicon, preferably doped silicon, such as ultra-heavily doped, UHD, silicon. In certain embodiments, the cap wafer portion comprises silicon (a silicon layer). In certain embodiments, the cap wafer portion comprises silicon, preferably doped silicon, such as ultra-heavily doped, UHD, silicon. In certain preferred embodiments, the silicon is of single-crystal silicon.

[0028] In certain embodiments, the top electrode (layer) is implemented by a layer of metal. In certain embodiments, the top electrode comprises (is of) metal, preferably gold (Au). In certain embodiments, the top electrode is of gold, Au. In certain embodiments, the top electrode is of gold, preferably doped gold. In certain embodiments, the top electrode is of gold alloy. In certain embodiments, the top electrode (layer) is implemented by a layer of doped silicon. In certain embodiments, the silicon layer is of single-crystal silicon. In certain embodiments, the top electrode (layer) is implemented by a layer of doped polysilicon.

[0029] In certain embodiment, the top electrode is made of same material than a sealing ring. In certain embodiment, the top electrode is made of same material than a sealing ring of the cap wafer portion.

[0030] In certain embodiments, the device wafer portion is a portion of a device wafer. In certain embodiments, the cap wafer portion is a portion of a cap wafer.

[0031] In certain embodiments, the device wafer portion comprises a piezoelectric layer. In certain embodiments, the device wafer portion comprises a piezoelectric layer on the silicon layer (silicon body) of the device wafer portion. In certain embodiments, the piezoelectric layer (material) is of aluminum nitride, AIN.

[0032] In certain embodiments, the device wafer portion of the chip comprises a silicon layer, and a piezoelectric layer on top of the silicon layer. In certain embodiments, the device wafer portion of the chip comprises a silicon device layer, and a piezoelectric layer on top of the silicon device layer. In certain embodiments, the device wafer portion of the chip comprises a device layer (of silicon), and a piezoelectric layer on top of the device layer (of silicon). In certain embodiments, the device wafer portion of the chip comprises a material stack, the material stack comprising the silicon layer (the bottom electrode), and the piezoelectric layer on top of the silicon layer. In certain embodiments, the device wafer portion of the chip comprises a piezoelectric device. In certain embodiments, the bottom electrode of the device is implemented by a silicon layer (of the bottom wafer portion / of the chip).

[0033] In certain embodiments, the resonating element (the resonator) of the device wafer portion comprises a material stack, the material stack comprising the silicon layer (the bottom electrode), and the piezoelectric layer on top of the silicon layer. In certain embodiments, the resonator device (resonating element) comprises a silicon layer, and the piezoelectric layer on top of the silicon layer.

[0034] In certain embodiments, the device wafer portion of the chip comprises a piezoelectric device. In certain embodiments, the device is a piezoelectric device. In certain embodiments, the device is a piezoelectrically actuated device. In certain embodiments, the device supports piezoelectric actuation. In certain embodiments, the piezoelectric device is configured to be excited by piezoelectric forces. In certain embodiments, the resonance mode (shape) is a vertical mode. In certain embodiments, the resonance mode is a flexural resonance mode.

[0035] In certain embodiments, the device wafer portion of the chip comprises an electrostatic device. In certain embodiments, the electrostatic device is configured to be excited by attractive electrostatic forces. In certain embodiments, the resonance mode (shape) is a vertical mode. In certain embodiments, the resonance mode is a flexural resonance mode.

[0036] In certain embodiments, the silicon layer is configured to implement a bottom electrode of the chip. In certain embodiments, the silicon layer is a bottom electrode of the chip. In certain embodiments, the bottom electrode comprises silicon, preferably doped silicon, such as ultra-heavily doped, UHD, silicon. In certain preferred embodiments, the silicon is of singlecrystal silicon. In certain embodiments, the bottom electrode (layer) is implemented by an UHD silicon layer (of the device wafer portion).

[0037] In certain embodiments, the doping level of the silicon is above 1019cm-3. In certain embodiments, the doping level of the silicon is above 1 O20cm-3. In certain embodiments, the doped silicon is of N-type or P-type doping.

[0038] In certain embodiments, the chip comprises at least one device. In certain embodiments, the chip comprises a plurality of devices (such as two devices).

[0039] In certain embodiments, the device is a resonator. In certain embodiments, the device is a resonating device. In certain embodiments, the device is a resonator device. In certain embodiments, the device comprises a (at least one) resonating element. In certain embodiments, the device is a microelectromechanical systems, MEMS, resonator. In certain embodiments, the device is (part of) a semiconductor device. In certain embodiments, the device is configured to operate in a megahertz frequency area. In certain embodiments, the device is configured to operate at 32 MHz frequency.

[0040] In certain embodiments, the device comprises at least one resonating element. In certain embodiments, the resonating element is separated (from the substrate, from the device wafer portion) by trench(es). In certain embodiments, the resonating element is separated (from the substrate, from the device wafer portion) by trench(es) and a cavity. In certain embodiments, trench is a vertical trench. In certain embodiments, cavity is a horizontal cavity. In certain embodiments, a device (bottom) wafer portion and a cap wafer portion are bonded together, wherein the chip comprises a resonator device comprising at least one resonating element. In certain embodiments, a device (bottom) wafer portion and a cap wafer portion are bonded together, wherein the chip comprises a resonator device comprising at least one resonating element separated from a substrate (from the device / bottom wafer portion) by trench(es). In certain embodiments, a device (bottom) wafer portion and a cap wafer portion are bonded together, wherein the chip comprises a resonator device comprising at least one resonating element, anchored to its (the resonating element’s) surroundings by at least one anchor.

[0041] In certain embodiments, the device comprises a plurality of resonating element. In certain embodiments, the resonating element comprises a plurality of resonating beam elements. In certain embodiments, each beam element is a sub-element of the device.

[0042] In certain embodiments, the resonating element comprises a plurality of beam elements having a length and a width. In certain embodiments, the plurality of beam elements are positioned adjacent to each other. In certain embodiments, adjacent beam elements are mechanically connected to each other by connection elements.

[0043] In certain embodiments, the device is a stacked beam resonator. In certain embodiments, the stacked beam resonator comprises a plurality of beam elements positioned side-by-side in a plane. In certain embodiments, the plurality of beam elements are positions adjacent to each other in a width direction thereof. In certain embodiments, the plurality of beam elements are positioned adjacent to each other in a width direction of the device. In certain embodiments, the beam elements are separated by trenches. In certain embodiments, the beam elements are connected to each other by connection elements.

[0044] In certain embodiments, the resonating element of the device comprises a plurality of beam elements, such as seven, nine, or eleven beam elements. In certain embodiments, said adjacent beam elements are mechanically connected to each other by connection elements. In certain embodiments, the beam elements of the device are arranged in a rectangular array configuration.

[0045] In certain embodiments, the resonating element is in a shape of a rectangle. In certain embodiments, the resonating element is in a shape of an elongated rectangle (beamshaped). In certain embodiments, the resonating element has an aspect ratio (ratio of length to width, when observed from above) different from 1 . In certain embodiments, the resonating element of the device has a length-to-width aspect ratio of less than 1. In certain embodiments, the device is attached (supported, anchored, suspended) to a support structure. In certain embodiments, the resonating element is attached (supported, anchored, suspended) to a support structure. In certain embodiments, the resonating element is attached (supported, anchored, suspended) to a support structure by at least one anchor.

[0046] In certain embodiments, the device is attached to a support structure from the outermost beam elements of the device. In certain embodiments, the device comprises at least one anchor configured to connect the device to, and suspend the device from surrounding layers. In certain embodiments the at least one anchor comprises portions of the piezoelectric layer, the top electrode and the bottom electrode.

[0047] In certain embodiments, each beam element is in a shape of a (rectangular) beam. In certain embodiments, each beam element has an aspect ratio (ratio of length to width, when observed from above) different from 1. In certain embodiments, each beam element has a length-to-width aspect ratio of more than 1 .

[0048] In certain embodiments, the resonating beam element(s) are longitudinally aligned within 25 degrees of a <100> crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) are longitudinally aligned with a < 100> crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of each resonating beam is within 25 degrees of the <100> crystal direction of the silicon (of the bottom electrode).

[0049] In certain embodiments, the device is configured to resonate (operate, oscillate, vibrate) in an in-plane resonance mode. In certain embodiments, the device is configured to operate (resonate) in an in-plane length-extensional, LE, resonance mode. In certain embodiments, the length extensional resonance mode is configured to resonate parallel to the length direction of the device. In certain embodiments, the length extensional resonance mode is configured to resonate perpendicular to the width direction of the device.

[0050] In certain embodiments, the device is configured to resonate in a square-extensional, SE, resonance mode. In certain embodiments, the device is configured to resonate in a widthextensional, WE, resonance mode. In certain embodiments, the device is configured to resonate in a out-of-plane resonance mode. In certain embodiments, the device is configured to resonate in an out-of-plane flexural resonance mode.

[0051] In certain embodiments, the device is configured to resonate in a collective resonance mode. In certain embodiments, each resonating element of the device is configured to resonate in the (same) collective resonance mode. In certain embodiments, the device is configured to resonate in a desired (main) resonance mode. In certain embodiments, each beam element of the resonator is configured to resonate in the (same) desired resonance mode.

[0052] According to a second example aspect of the present disclosure there is provided an apparatus comprising at least one semiconductor chip according to the first aspect or any of its embodiments. What is disclosed in the context of the first aspect for the semiconductor chip applies also to the apparatus comprising at least one semiconductor chip.

[0053] In certain embodiments, the apparatus comprises a plurality of semiconductor chips, such as two semiconductor chips of the first aspect of any of its embodiments. In certain embodiments, the apparatus is a semiconductor apparatus (semiconductor device). In certain embodiments, the apparatus is a sensor device.

[0054] Different non-binding example aspects and embodiments have been illustrated in the foregoing. The embodiments in the foregoing are used merely to explain selected aspects or steps that may be utilized in different implementations. Some embodiments may be presented only with reference to certain example aspects. It should be appreciated that corresponding embodiments may apply to other example aspects as well. In particular, the embodiments described in the context of the first aspect are applicable to each further aspect. Any appropriate combinations of the embodiments may be formed.

[0055] BRIEF DESCRIPTION OF THE FIGURES

[0056] Some example embodiments will be described with reference to the accompanying figures, in which:

[0057] Fig. 1A schematically shows a chip according to an example embodiment;

[0058] Fig. 1 B schematically shows a chip having static deflection according to an example embodiment; Fig. 2A schematically shows a chip having static deflection flattened according to an example embodiment;

[0059] Fig. 2B schematically shows a chip having a point of controlled contact on a cross- sectional view according to an example embodiment;

[0060] Fig. 2C schematically shows a device having a point of controlled contact on a top view according to an example embodiment;

[0061] Fig. 3 schematically shows a chip having a cavity in a cap wafer portion according to an example embodiment;

[0062] Fig. 4A schematically shows a first step of providing the point of controlled contact according to an example embodiment;

[0063] Fig. 4B schematically shows a second step of providing the point of controlled contact according to an example embodiment;

[0064] Fig. 5A schematically shows a chip comprising trim material according to an example embodiment;

[0065] Fig. 5B schematically shows a chip comprising trim material according to another example embodiment; and

[0066] Fig. 6 schematically shows an example device according to an example embodiment.

[0067] DETAILED DESCRIPTION

[0068] In the following description, like reference signs denote like elements or steps.

[0069] As used herein, the term chip means a single package, i.e. one physical entity that comprises a resonator having resonating structure(s). According to certain embodiments of the present disclosure, the chip comprises a device wafer and a cap wafer bonded together to form the chip (the package).

[0070] As used herein, the term die means the part that is diced from a ready fabricated silicon wafer in the dicing operation. In dicing, the dies are separated from each other using a special equipment. In the context of the instant disclosure, the term die forms a synonym to the term chip. Other synonyms to the terms chip and die is the term component.

[0071] The axes x, y and z are denoted to each Figure to illustrate the direction of observing. The axes are interrelated, meaning that each of the notations x, y or z are to be understood as the same x, y or z direction in all the Figures. Fig. 1A schematically shows the chip 100 according to certain embodiments. The chip 100 comprises a cap wafer portion 201 (a top wafer portion) and a device wafer portion (bottom wafer portion) 101 . For the purposes of the present description, the device wafer portion is understood, for example, as a portion of a device wafer. For the purposes of the present description, the cap wafer portion is understood, for example, as a portion of a cap wafer.

[0072] The cap wafer portion 201 and the device wafer portion 101 are bonded together to form the chip 100. According to certain embodiments, the bonding used is a thermocompression bonding. Preferably, the cap wafer portion 201 and the device wafer portion 101 comprise silicon (layer), such as doped silicon, or ultra-heavily doped, UHD, silicon having the doping level above 1019cm-3, such as above 102° cm-3. In certain embodiments, the doped silicon is of N-type or P-type doping. In certain preferred embodiments, the silicon is of singlecrystal silicon.

[0073] In certain embodiments, the device wafer portion 101 and the cap wafer portion 201 are fabricated on a substrate (each on a different substrate). In certain embodiments, the substrate is a wafer, preferably a silicon wafer. In certain embodiments, the device wafer portion 101 is a portion diced of a device wafer. In certain embodiments, the cap wafer portion 201 is a portion diced of a cap wafer.

[0074] As shown in Fig. 1A, in certain embodiments, the device wafer portion 101 is fabricated on a cavity silicon-on-insulator, CSOI, substrate. In certain embodiments, the device wafer portion 101 comprises an insulator layer 103. As shown in Fig. 1A, in certain embodiments, the cap wafer portion 201 is fabricated on a plain silicon substrate.

[0075] As shown in Fig. 1A, in certain embodiments, the device wafer portion 101 comprises a handle layer 102 of silicon. In certain embodiments, the device wafer portion 101 comprises an insulator layer 103, such as a buried oxide layer, BOX, on the handle layer 102 in certain embodiments, the insulator layer 103 comprises silicon dioxide. In certain embodiments, the device wafer portion 101 comprises a device layer 104 of silicon, preferably comprising doped silicon. In certain embodiments, the device 110 is fabricated onto the device layer 104 (and onto the layer(s) on top of the device layer 104.

[0076] In certain embodiments, the device wafer portion 101 comprises a piezoelectric layer 105 on the device layer 104. In certain embodiments, the piezoelectric layer 105 is of aluminum nitride, AIN. In certain preferred embodiments, the device wafer portion 101 comprises a silicon device layer 104 of ultra-heavily doped, UHD, silicon, and a piezoelectric layer 105 of AIN on top of the silicon device layer 105. In certain embodiments, the doping level of the silicon device layer 104 is above 1019cm-3, preferably above 102° cm-3. In certain embodiments, the doped silicon is of N-type or P-type doping.

[0077] In certain embodiments, the device wafer portion 101 comprises a cavity 106. In certain embodiments, the device 110 is arranged at (above) the cavity 106. In certain embodiments, the device 110 is configured to resonate (oscillate, move) in the cavity 106.

[0078] In certain embodiments, the chip 100 comprises a bottom electrode. In certain embodiments, the bottom electrode is (located) on the device wafer portion 101. In certain embodiments, the silicon layer 104 is configured to implement a bottom electrode of the chip 100. In certain embodiments, the bottom electrode (layer 104) comprises silicon, preferably doped silicon, such as ultra-heavily doped, UHD, silicon (having the doping level above 1019cm-3, preferably above 102° cm-3). In certain preferred embodiments, the silicon is of single-crystal silicon.

[0079] In certain embodiments, the chip 100 comprises a top electrode 202. In certain embodiments, the top electrode 202 is implemented by a layer of metal, preferably gold (Au). In certain alternative embodiments, the top electrode 202 is implemented by a layer of silver (Ag), copper (Cu) or aluminum (Al).

[0080] In certain embodiments, the chip 100 comprises a device 110. In certain embodiments, the device 110 is a resonating (oscillating) device. In certain embodiments, the device wafer portion 101 and the cap wafer portion 201 bonded together form an enclosure for the device 110. In certain embodiments, the enclosure is in a vacuum.

[0081] In certain embodiments, through silicon vias TSVIN, TSVOUT (electrical vias) (are configured to) provide electrical connection through the cap wafer portion 201 (from the outside / backside of the cap wafer portion 201 to cap wafer portion 201 other side / front side / inner side).

[0082] In certain embodiments, the top electrode 202 is electrically coupled to a through silicon via TSVIN. In certain embodiments, the top electrode 202 is electrically coupled by a conductive material to a through silicon via TSVIN leading to an (external) pad XIN. In certain embodiment, the through silicon via TSVIN is filled with conductive material (to allow the electrical connection). In certain embodiments, the through silicon via TSVIN is configured to provide electrical connection (current, electrical flow) through the cap wafer portion 201 to the top electrode 202. In certain embodiments, the (external) pad XIN is configured to provide electrical connection to the top electrode 202 of the device 110 (via the through silicon via TSVIN of the cap wafer portion 201 ). In certain embodiments, the device 110 is electrically coupled to the top electrode 202 over a gap G. In certain embodiments, the device 110 electrical coupling to the top electrode 202 is formed through bond contact.

[0083] In certain embodiments, the silicon layer 104 (bottom electrode) is electrically coupled to another through silicon via TSVOUT. In certain embodiments, the silicon layer 104 (bottom electrode) is electrically coupled by a conductive material to another through silicon via TSVOUT leading to an (external) pad XOUT. In certain embodiment, the through silicon via TSVOUT is filled with conductive material (to allow the electrical connection).

[0084] In certain embodiments, the through silicon via TSVOUT is configured to provide electrical connection through the cap wafer portion 201 to silicon layer 104 (bottom electrode) via the contact hole in the piezoelectric layer 105.

[0085] In certain embodiments, the device 110 is electrically coupled to the silicon layer 104 (bottom electrode) via a contact hole in the piezoelectric layer 105.

[0086] In certain embodiments, the device 110 and the top electrode 202 are not in the same wafer portion 101 or 201. According to certain embodiments, the chip 100 comprising a device 110 and a top electrode 202 located on different wafer portion is understood, for example, such that the chip 100 comprises the device 110 located on (or in) one of the said portions (device wafer portion 101 , cap wafer portion 201 ) and the top electrode 202 located on (or in) the other portion. Accordingly, in certain embodiments, the device 110 and the top electrode 202 are located on different wafer portions, one on the device wafer portion 101 and one on the cap wafer portion 201. In certain preferred embodiments, the device 110 is located in the device wafer portion 101 and the top electrode is located in the cap wafer portion 201 .

[0087] In certain embodiments, the top electrode 202 is electrically coupled over a gap G to the device layer portion 101. According to certain embodiments, the top electrode 202 is electrically coupled over the gap G to the device 110, in particular to the piezoelectric layer 105 of the device 110. In certain embodiments, the top electrode arrangement of the chip

[0088] 100 allows current to be transferred from the top electrode 202 to the device wafer portion

[0089] 101 (over the gap G). In certain embodiments, the top electrode 202 is sufficiently close to the device 110 to allow current to travel between the top electrode 202 and the device 110. In certain embodiments, an electrical field exists between the top electrode 202 and the device 110. In certain embodiments, electromagnetic forces enable electrical flow through the gap G. In certain embodiments, the gap G is a vacuum gap.

[0090] In certain embodiments, the chip 100 comprises (essentially) a capacitor having two layers, a layer of piezoelectric material 105 and a gap G. In certain embodiments, the bottom electrode (silicon layer) 104 and the top electrode 202 comprise (‘are sandwiching’) a layer of piezoelectric material 105 and a gap G (a layer of vacuum / air) between themselves (between each other, between one another). In certain embodiments, the capacitor comprises electromagnetic conversion, such that electric field is converted into strain via piezoelectric effect. In certain embodiments, the gap G is a vacuum gap. In certain embodiments, the (vacuum) gap G is inert. In certain embodiments, the gap G is arranged as thin as possible so that the majority of the electric field is converted into strain via the piezoelectric effect. In certain embodiments, the (vacuum) gap G is essentially ‘diluting’ (decreasing, lessening) the effective electric field. This enables lowering the transduction factor, and increasing the equivalent series resistance, ESR.

[0091] In certain embodiments, the top electrode 202 is arranged as close as possible to the piezoelectric layer 105 of the device 110. In certain embodiments, the gap G between the top electrode and the piezoelectric layer 105 of the device 110 is less than 500 nm, such as less than 400 nm. In certain preferred embodiments, the gap G between the top electrode and the piezoelectric layer 105 of the device 110 is less than 100 nm. The equivalent series resistance, ESR of the device 110 is proportional to the gap G size squared and therefore, the gap G is designed as small as possible.

[0092] Accordingly, herein is provided a semiconductor chip 100, comprising a device wafer portion 101 and a cap wafer portion 201 bonded together, wherein the chip 100 comprises a device 110 and a top electrode 202 located on different wafer portions.

[0093] In certain embodiments, the top electrode 202 is arranged on the cap wafer portion 201 inside the enclosure. In certain embodiments, the top electrode 202 is arranged on the inside surface of the wafer level package, WLP (the enclosure). In certain embodiments, the top electrode 202 is a mechanically floating top electrode (mechanically ‘floats’, is suspended over the device 110, physical contact is not necessary). In certain embodiments, the top electrode 202 is arranged to face the device 110 inside the enclosure as shown in Fig. 1A.

[0094] Fig. 1 B schematically shows a chip 100 having static deflection according to an example embodiment. In certain embodiments, the static deflection occurs due to stress of the material layer. In certain embodiments, the top electrode 202 has static deflection (downwards in z-direction). In certain embodiments, the top electrode is of Au.

[0095] In certain embodiments, the material layer(s) of the device 110 have (comprise, result in) static deflection (upwards in z-direction). By way of an example, stress in a piezoelectric layer 105 is typically unavoidable, and results in a static deflection of the device 110 as shown in Fig. 1 B. In certain embodiments, the piezoelectric layer 105 is of AIN. In certain embodiments, the piezoelectric layer 105 is (is engineered to be, is configured to be) more compressive than device layer 104. In certain embodiments, the device layer 104 is of UHD silicon. In certain embodiments, the piezoelectric layer 105 being more compressive than the device layer 104 results in (makes, causes) the device 110 to bend upward (from its center) rather than downward.

[0096] In the embodiment shown in Fig. 1 B, the centre of the device 110 has maximum positive static deflection. In the embodiment shown in Fig. 1 B, the peripherals of the device 110 have maximum negative static deflection.

[0097] In certain embodiments, a region of the device 110 having high(est) transduction is arranged to be closest to the top electrode 202 (shown in gap size Gi). In certain embodiments, a region of the device 110 having low(est) displacement is arranged to be closest to the top electrode 202 (shown in gap size Gi). In the embodiment shown in Fig. 1 B, this region is in the centre of the device 110. This enables providing improved equivalent series resistance, ESR, for the device 110.

[0098] In certain embodiments, a region of the device 110 having low(est) transduction is arranged to be farthest from the top electrode 202 (shown in gap size G2). In certain embodiments, a region of the device 110 having high(est) displacement is arranged to be farthest to the top electrode 202 (shown in gap size G2). In the embodiment shown in Fig. 1 B, this region is in the peripherals of the device 110. In certain embodiments, the difference between gap sizes Gi and G2 is more than 50 nm (in z-direction). This enables minimizing the risk of collision of the device 110 to the top electrode during resonance. In certain embodiments, the device 110 is configured to resonate in an in-plane resonance mode. In certain embodiments, the device 110 is configured to resonate in an in-plane length-extensional, LE, resonance mode. In certain embodiments, the gap G between the top electrode 202 and the piezoelectric layer 105 of the device 110 is less than 100 nm (wide), such as less than 50 nm, in in-plane resonance modes. In certain preferred embodiments, the gap G between the top electrode 202 and the piezoelectric layer 105 of the device 110 is less than 10 nm, such as in between 2-3 nm, in in-plane resonance modes.

[0099] In certain alternative embodiments, the device 110 is configured to resonate in an out-ofplane resonance mode. In certain embodiments, the device 110 is configured to resonate in an out-of-plane flexural resonance mode.

[0100] In certain embodiments, the gap G (width, size) between the top electrode 202 and the device 110 is (engineered to be, configured to be) larger in larger than the maximum displacement of the out-of-plane resonance mode (to prevent the device 110 from hitting the top electrode 202). In certain embodiments, the gap G (width, size) is dependent on the frequency of the out-of-plane resonance mode.

[0101] In certain embodiments, the gap G between the top electrode 202 and the piezoelectric layer 105 is less than 100 nm, such as less than 50 nm, in out-of-plane resonance modes (having high frequencies). In certain embodiments, the gap G between the top electrode 202 and the piezoelectric layer 105 is less than 10 nm, such as in between 2-3 nm, in out- of-plane resonance modes (having high frequencies). In certain embodiments, the gap G between the top electrode and the piezoelectric layer 105 is in between 1-5 pm, such as in between 2-3 pm, in out-of-plane resonance modes (having low frequencies).

[0102] In certain embodiments, the gap G between the top electrode 202 and the piezoelectric layer 105 is made as small as possible by forcing a mechanical contact between the between the top electrode 202 and the piezoelectric layer 105. Accordingly, the gap Gi is essentially 0, where the contact is made. In embodiments where the contact is made in the area of the resonating element 110 having low(est) displacement and / or high(est) transduction, a small gap G2 remains in the area of the device 110 having low(est) transduction and / or high(est) displacement. In certain embodiments, the size of the gap G1 / G2 depends on the contact strength and / or the contact surface. As shown in embodiment of Fig. 1 B, the device 110 (surface) bends upwards and / or the cap wafer portion having the top electrode 202 bends downwards. In certain embodiments, the resonating element 110 is bent upwards by controlling the stress in piezoelectric layer 105. In these embodiments, the piezoelectric layer 105 undergoes compressive stress (that is, negative residual stress values, such as -100MPa). In certain embodiments, the increase of (compressive) stress of the piezoelectric layer 105 bends the resonating element 110. In certain embodiments, the stress of the piezoelectric layer 105 is controlled via sputter target lifetime and / or gas flow modulation during sputtering.

[0103] Fig. 2A schematically shows a chip 100 having static deflection flattened according to an example embodiment. In certain embodiments, the top electrode 202 is configured to contact (touch) the device 110. In certain embodiments, the top electrode 202 is configured to contact the topmost layer of the device 110, in this embodiment the piezoelectric layer 105. In certain embodiments, the contact occurs at the region of the device 110 having high(est) transduction and having low(est) displacement. In this embodiment, the contact occurs at the centre of the device 110.

[0104] In certain embodiments, the device 110 is configured to resonate in an in-plane resonance mode. The flattening of the static deflection by providing contact between the top electrode 202 and the device 110 enables preventing any spurious out-of-plane resonance from occurring. The flattening of the static deflection by providing contact between the top electrode 202 and the device 110 further enables making the gap G controlled (otherwise the gap G depends on the static deflection of the device 110 which can vary over the substrate).

[0105] In certain embodiments, the cap wafer portion 201 and the device wafer portion 101 are bonded together by a sealing ring 107. In certain embodiments, the sealing ring 107 is configured to encircle the device 110. In certain embodiments, the sealing ring 107 is configured to seal the device 110 into the enclosure upon bonding the cap wafer portion 201 and the device wafer portion 101 together.

[0106] In certain embodiments, the sealing ring 107 comprises a first part (portion) fabricated (deposited) onto the device wafer portion 101 (prior to bonding). In certain embodiments, the sealing ring 107 comprises a second part (portion) fabricated (deposited) onto the cap wafer portion 201 (prior to bonding). The first part and the second part of the sealing ring 107 are schematically shown herein as opposing direction dashed areas. In certain embodiments, the first part and the second part of the sealing ring 107 are configured to fuse together (deform) during bonding. In certain embodiments, the sealing ring 107 enables providing a hermetical seal for the enclosure (package).

[0107] In certain embodiments, the top electrode 202 thickness is (configured to be, engineered to be) equal to sealing ring 107 thickness. As used herein, the term equal is used to refer all the following: exactly equal, essentially equal, approximately equal, and as close as possible within the limits of the manufacturing processes. In certain embodiments, the top electrode 202 (and equally the sealing ring 107) has a thickness in the range of 100nm to 1 pm.

[0108] In certain embodiments, as shown e.g. in Fig. 2A, the cap wafer portion 201 comprises a deflection towards the device 110 (towards inside the enclosure, downwards deflection). The deflection of the cap wafer portion 201 is caused by the air pressure (due to the inside the enclosure / package being in vacuum). This enables aiding in making the contact between the top electrode 202 and the device 110 (post bonding).

[0109] Fig. 2B schematically shows a chip 100 having a point of controlled contact 108, PCC, (dimple, bump, raised feature) on a cross-sectional view according to an example embodiment. In certain embodiments, the top electrode 202 and the device 110 (more specifically, the topmost layer of the device 110, in this case, the piezoelectric layer 105) are configured to contact via a point of controlled contact 108. In certain embodiments, the PCC 108 is configured to localize the contact between the top electrode 202 and the device 110. In certain embodiments, the PCC 108 is of metal, preferably soft metal. In certain embodiments, the PCC 108 is of gold, Au. In certain embodiments, the PCC 108 is of tin, Sn. In certain embodiments, the PCC 108 is of non-metallic material. In certain embodiments, the PCC 108 is of aluminum nitride, AIN. In certain embodiments, the PCC 108 is of silicon dioxide, SiO2. In certain embodiments, the PCC 108 is of polysilicon, preferably doped polysilicon. In certain embodiments, the PCC 108 is configured to be “fused” (merged) with the top electrode layer 202 upon bonding the device wafer portion and the cap wafer portion.

[0110] In certain embodiments, the point of controlled contact 108 is fabricated onto device wafer portion 101. In certain embodiments, the point of controlled contact 108 is fabricated onto the device 110 surface. In certain embodiments, the PCC is placed (arranged) at a region of high(est) transduction and having low(est) displacement. In this embodiment, the PCC 108 is arranged on the centre (central area) of the device 110. In this embodiment, the device 110 is configured to resonate in an in-plane length-extensional resonance mode. This enables minimizing potential anchor losses.

[0111] In certain embodiments, the sealing ring 107 thickness is (configured to be, engineered to be) equal to the top electrode 202 thickness’ and the PCC 108 thickness’ sum.

[0112] Accordingly, in certain embodiments, the PCC 108 is patterned (provided) in the point of low(est) displacement of the device (resonating device) 110. This area is also the area having the high(est) dynamic stress. This ensures minimal acoustic losses, and provision of high Q value for the resonator 100.

[0113] Fig. 2C schematically shows a device 100 having a point of controlled contact 108 on a top view according to an example embodiment, and in particular, the same embodiment as shown in Fig. 2B (Fig. 2B showing a cross section) as a top view. In certain embodiments, the chip 100 comprises one PCC 108 per a device 110. By way of an example, in certain embodiments, the device 110 is a stacked beam resonator. As shown in Fig. 2C, a stacked beam resonator comprises a plurality of resonating beam-shaped elements positioned side- by-side in a plane, separated by trenches and connected by connection elements (a ladderlike configuration). In certain embodiments, the maximum static deflection of the stacked beam resonator occurs in the centre of the device 110. Therein, according to certain embodiments, one PCC 108 is arranged at the center of the centermost beam. In certain embodiments, the chip 100 comprises a plurality of PCCs 108 per a device 110 (not shown).

[0114] In certain embodiments, the piezoelectric layer 105 covers the device 110 surface (only) partially. In certain embodiments, the piezoelectric layer 105 is removed partially from the device 110 surface. In certain embodiments, the piezoelectric layer 105 covers the area of high(est) transduction and having low(est) displacement of the device 110 (not at the device 110 edges / peripheral areas). In this embodiment, the piezoelectric layer 105 covers only the center area of the device 110. In Fig. 2C, the piezoelectric layer 105 is removed everywhere outside the dash-lined area marked with 105. This enables providing improved figure of merit, FOM, for the device 110. Figure of merit, FOM, is defined by FOM = Q * C1 / C0 (wherein Q refers to quality factor, Ci refers to mechanical compliance, and Co refers to electrical capacitance). In certain embodiments, the top electrode 202 (on the cap wafer portion 201 ) is arranged (manufactured) slightly larger than the piezoelectric layer 105 area. This is shown as the dash-lined area marked with 202. In certain embodiments, the top electrode 202 floats above the device 110 on the cap wafer portion 201 .

[0115] According to certain embodiments, this enables providing a simple solution providing improvement in figure of merit, FOM, of the chip 100. There is no need to wire each resonating element to each other since since the top electrode 202 is floating above the device 110 and the piezoelectric layer is arranged (designed) at the centre for all resonating beams of a resonating element.

[0116] Further accordingly, the layout design(s) of top electrode 202 and / or the piezoelectric layer 105 as shown in Fig. 2C are enabled by the present solution. In certain embodiments, the coverage (layout, design) of the top electrode 202 and / or the piezoelectric layer 105 can be designed without constraints (of wiring the signal). Accordingly, in certain embodiments, the coverage of the top electrode 202 and / or the piezoelectric layer 105 is partial (do not cover entire device (resonating element) 110). In certain embodiments, the resonating element 110 comprises sections (areas) with no piezoelectric layer 105 coverage.

[0117] Fig. 3 schematically shows a chip 100 having a cavity 203 on the cap wafer portion 201 according to an example embodiment. In certain embodiments, the cap wafer portion 201 comprises a cavity 203 (can be also called a trench 203). In certain embodiments, the cavity 203 is arranged below (appears ‘above’ in z-direction of Fig. 3) the top-electrode 202. In certain embodiments, the cavity 203 is configured to increase flexibility of the top electrode 202 material portion by creating a spring. This enables alleviating anchor losses of the device 110 and limiting the device 110 static deflection correction. This further enables reducing wafer bonding problems. Namely, if the contact at the device 110 level is too strong during bonding, the sealing ring 107 may fail. The flexibility of the top electrode 202 alleviates the contacts at the device level 110. Further, this enables ensuring that when PCC 108 is in contact with the top electrode 202, the “spring” of the top electrode 202 (created by the cavity 203) receives the strain and the device (resonating element) 110 overall curvature is less perturbated.

[0118] In certain embodiments, the cavity 203 is fabricated onto the silicon layer of the cap wafer portion 201. In certain embodiments, the cavity 203 is provided via a CSOI substrate, or via oxide deposition and release method. In certain embodiments, the cavity 203 is an open cavity. In certain embodiments, the cavity 203 is connected to the enclosure between the cap wafer portion 201 and the device wafer portion 101 by a pathway 204. This enables increasing the volume inside the device 110 packaging.

[0119] CAPELE in contact with the MEMS could bring some reliability issue and it is good to have CAPELE on a spring as in slide 11 on the ppt.

[0120] Figs. 4A and 4B schematically show steps of providing the point of controlled contact 108 according to an example embodiment. Figs. 4A and 4B show a similar chip 100 configuration than Fig. 2B.

[0121] In certain embodiments, the chip 100 comprises a material layer of 108’ on the top electrode 202, as shown in Fig. 4A. In certain embodiments, the material layer 108’ is deposited onto the top electrode layer 202. In certain embodiments, the material layer 108’ is configured to provide increased (additional, extra) thickness onto the top electrode layer 202. In certain embodiments, the material layer 108’ is patterned (via lithography and etching) to a point of controlled contact, PCC, 108, as shown in Fig. 4B. What is disclosed about the PCC 108 in the context of Fig. 2B, applies herein as well. However, in contrast to what is disclosed in the context of Fig. 2B, in certain alternative embodiments, the point of controlled contact 108 is formed of a material layer 108’ fabricated (deposited) onto the cap wafer portion 201 (onto the top electrode layer 202). In certain embodiments, the PCC 108 is patterned (arranged) onto the top electrode layer 202 such that the PCC 108 is configured to contact the device 110 at a region of high(est) transduction and having low(est) displacement. In this embodiment, the PCC 108 is arranged to contact the centre (central area) of the device 110.

[0122] In certain embodiments, the sealing ring (area) comprises a cap material part (portion) 107A. In certain embodiments, the cap material part 107A is a cap metal part 107A. In certain embodiments, the cap material part 107A is deposited onto the cap wafer portion 201 (prior to bonding). In certain embodiments, the cap material part 107A and the top electrode layer 202 are of same thickness. In certain embodiments, the cap material part 107A is of same material than the top electrode layer 202, such as gold.

[0123] In certain embodiments, the sealing ring comprises a device material part (portion) 107B. In certain embodiments, the device material part 107B is a device metal part 107B. In certain embodiments, the device material part 107B is deposited onto the device wafer portion 101 (prior to bonding).

[0124] In certain embodiments, the cap material part 107A and device material part 107B of the sealing ring area are configured to fuse together (deform) during bonding.

[0125] Fig. 5A schematically shows a chip 100 comprising trim material 109 according to an example embodiment. In certain embodiments, trim material (layer(s), patches) 109 are arranged onto the device 110 to maximize the trimming effect. In certain embodiments, the trim material 109 is of metal, such as gold, Au, or tin, Sn.

[0126] In certain embodiments, the trim material is trimmed post-packaging (after bonding). In certain optional embodiments, a further cavity etched on the surface of the cap wafer portion 201 being outside the enclosure (not shown) enables trimming after bonding. In certain embodiments, the trimming is a laser trimming having a wavelength transparent to the cap wafer portion 201 material, in this embodiment transparent to silicon. In certain embodiments, the laser is configured to hit the top electrode 202 from ‘backside’ (from the side outside the enclosure). In some other embodiments, a cap wafer portion 201 is of glass to make laser trimming even easier.

[0127] In certain embodiments, the chip 100 comprises an extra layer (patch, deposit) of material 112 on the PCC 108. In certain embodiments, the chip 100 comprises an extra layer (patch, deposit) of material 107’ in between the first part and the second part of the sealing ring 107. This ensures that there is sufficient room in the enclosure for the trim material 109 on the device 110. This also enables utilizing the PCC 108 simultaneously as providing the trim material 109.

[0128] Fig. 5B schematically shows a chip comprising trim material according to another example embodiment. Fig. 5B shows a similar chip 100 configuration than Figs. 2B, 4A, 4B and 5A. In this embodiment, the extra layers of material 107’ and 112 are omitted.

[0129] In certain embodiments, the device 100 comprises trim material (layer(s), patches) 109 to maximize the trimming effect. In certain embodiments, the trim material 109 is arranged at the sealing ring (area). In certain embodiments, the trim material 109 is arranged (deposited) onto the device wafer portion 101 below the sealing ring (or below the device material part 107B of the sealing ring). In certain embodiments, the trim material 109 is of metal, such as gold, Au, or tin, Sn. Fig. 6 schematically shows a top view (from above, from up to down) of an example device 110 according to an example embodiment. In certain embodiments, the chip 100 comprises at least one device 110. In certain embodiments, the chip 100 comprises a plurality of devices 110 (not shown). In certain embodiments, the device 100 is a resonator, preferably a microelectromechanical systems, MEMS, resonator. In certain embodiments, the device 110 is configured to operate in a megahertz frequency area. In certain embodiments, the device 110 is configured to operate at 32 MHz frequency.

[0130] In certain embodiments, the device 110 comprises at least one resonating element 400. In certain embodiments, the resonating element 400 comprises a plurality of resonating elements 401 (not shown).

[0131] The resonating element 400 according to embodiment shown in Fig. 6 comprises a plurality of resonating beam elements 401 having a length L and a width W. In the embodiment shown in Fig. 6, the resonating element 400 comprises seven resonating beam elements 401 (the number of elements 401 may vary depending on the embodiment). In certain embodiments, the resonating beam elements 401 are longer L than they are wide W.

[0132] According to the example embodiment shown in Fig. 6, the plurality of resonating beam elements 401 are positioned adjacent to each other. In certain embodiments, the plurality of resonating beam elements 4101 form a ladder-like configuration (stacked beam resonator). In certain embodiments, the plurality of resonating beam elements 401 are positioned adjacent to each other in a width direction W thereof. The adjacent resonating beam elements 401 are mechanically connected to each other by connection elements 402. In certain embodiments, the resonating element 400 is formed of the plurality of resonating beam elements 401 and a plurality of connection elements 402. In certain embodiments, the adjacent resonating beam elements 401 are separated by trenches 404. In certain embodiments, the trenches 404 have a length TL (trench length). In certain embodiments, the length L of the beam element 401 comprises at least the length of the trench TL and the length of at least one connection element 402.

[0133] In certain preferred embodiments, the device 110 comprises a stacked beam resonator comprising a plurality of resonating beam elements 401 positioned side-by-side in a plane, separated by trenches 404 and connected by connection elements 402. In at least some stacked beam resonators, the resonating beam elements 401 are positioned in the same plane. In certain stacked beam resonators, no two resonating beam elements 401 are positioned atop each other.

[0134] In certain embodiments, the resonating beam elements 401 are arranged in a rectangular array configuration. In certain embodiments, resonating element 400 has a length L (which is equal to the length of the beam element 401 ). In certain embodiments, the resonating element 400 has a width RW (resonating element width).

[0135] In certain embodiments, the resonating element 400 is attached to a support structure (not shown). In certain embodiments, the resonating element 400 is attached to the support structure from the outermost resonating beam elements 401 by anchoring point(s) 403. In certain embodiments, the resonating element 400 comprises electrical terminal(s) at anchoring points 403.

[0136] In certain embodiments, the resonating element 400 is of an elongated shape (having the length L smaller than their width RW). In certain embodiments, the resonating element 400 is in the shape of a rectangle. In certain embodiments, the resonating element 400 has an aspect ratio (ratio of length L to width RW, when observed from above) of less than 1 .

[0137] In certain embodiments, the resonating beam elements 401 are of an elongated shape (having their length L larger than their width W). In certain embodiments, each resonating beam element 401 is in the shape of a rectangular beam (beam-shaped). In certain embodiments, each resonating beam element 101 has a length-to-width, L-to-W, aspect ratio of more than 1 . In certain example embodiments, each resonating beam element 401 has a length-to-width, L-to-W, aspect ratio of more than 2, such as 5, 8, or 10.

[0138] In certain embodiments, the resonating beam element(s) 401 are longitudinally aligned within 25 degrees of a <100> crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) 401 are longitudinally aligned with a <100> crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of each resonating beam 401 is within 25 degrees of the <100> crystal direction of the silicon (of the bottom electrode).

[0139] In certain embodiments, the resonating element(s) 400 of the device 110 is configured to resonate (operate, oscillate, vibrate) in an in-plane length-extensional, LE, resonance mode. In certain embodiments, resonating element 400 the device 110 is configured to resonate in a collective resonance mode, wherein each resonating beam element 401 is configured to resonate in the (same) collective resonance mode.

[0140] Without limiting the scope and the interpretation of the patent claims, certain technical effects of one or more of the example embodiments disclosed herein are listed in the following. A technical effect is providing a high frequency stability semiconductor apparatus.

[0141] Conventionally, the top electrode is deposited on top of the device / resonator itself. The top electrode material, such as metal (typically gold) deposited on top of the device experiences change in its material properties, such as in its grain size, with ageing. These changes translate into unwanted changes in the device / resonator properties, such as a resonance frequency drift. A technical effect is avoiding the harmful effect(s) to the device caused by the top electrode material ageing. By completely removing the contribution of the top electrode material to the resonance of the device, the ageing effect is avoided. Thus, any changes to top electrode material properties will not influence the properties of the device, such as the resonance frequency of the device. Thus, a further technical effect is reducing the frequency drift of the device and increasing the frequency stability of the chip.

[0142] A further technical effect is increasing the quality factor Q of the chip. According to certain embodiments, a further technical effect is reaching approximately 40 % increase in Q value in comparison to the top electrode being arranged directly onto the device (as conventionally is done). A further technical effect is providing a chip having a series resistance of top electrode that is negligible. A further technical effect is providing a simpler design for the chip, since no electrical connection is needed to be made from the cap wafer portion to the device wafer portion for the top electrode.

[0143] Various embodiments have been presented. It should be appreciated that in this document, words comprise, include, and contain are each used as open-ended expressions with no intended exclusivity.

[0144] The foregoing description has provided by way of non-limiting examples of particular implementations and embodiments a full and informative description of the best mode presently contemplated by the inventors for carrying out the invention. It is however clear to a person skilled in the art that the invention is not restricted to details of the embodiments presented in the foregoing, but that it can be implemented in other embodiments using equivalent means or in different combinations of embodiments without deviating from the characteristics of the invention.

[0145] Furthermore, some of the features of the afore-disclosed example embodiments may be used to advantage without the corresponding use of other features. As such, the foregoing description shall be considered as merely illustrative of the principles of the present invention, and not in limitation thereof. Hence, the scope of the invention is only restricted by the appended patent claims.

Claims

CLAIMS1 . A semiconductor chip (100), comprising a device wafer portion (101 ) and a cap wafer portion (201 ) bonded together, wherein the chip (100) comprises a device (110) and a top electrode (202) located on different wafer portions.

2. The semiconductor chip of claim 1 , wherein the device (110) is in the device wafer portion (101 ) and the top electrode (202) is in the cap wafer portion (201 ).

3. The semiconductor device of claim 1 or 2, wherein the device wafer portion (101 ) and the cap wafer portion (202) are bonded together to form an enclosure for the device (110).

4. The semiconductor chip of claim 2 or 3, wherein the top electrode (202) is arranged on the cap wafer portion (201 ) inside the enclosure.

5. The semiconductor chip of any preceding claim, wherein the top electrode (202) is electrically coupled over a gap (G) to the piezoelectric layer (105) of the device layer portion (101 ).

6. The semiconductor chip of any preceding claim, wherein the device (110) is a microelectromechanical systems, MEMS, resonator.

7. The semiconductor chip of any preceding claim, wherein the device (110) is configured to operate in an in-plane length-extensional, LE, resonance mode.

8. The semiconductor chip of any preceding claim, wherein the top electrode (202) is of gold, Au.

9. The semiconductor chip of any preceding claims, wherein the device wafer portion (101 ) of the chip (100) comprises a silicon layer (104), and a piezoelectric layer (105) on top of the silicon layer (104).

10. The semiconductor chip of claim 9, wherein the silicon layer (104) is configured to implement a bottom electrode of the chip (100).11 . The semiconductor chip of any preceding claim, comprising through silicon vias, TSVs (TSVIN, TSVOUT) adapted to provide electrical connection to the cap wafer portion (201 ) and to the device wafer portion (101 ).

12. The semiconductor apparatus of any preceding claim, wherein the device (110) is bent upwards and / or the top electrode (202) is bent downwards to minimize the gap (G) therebetween.

13. The semiconductor apparatus of any preceding claim, comprising a point of controlled contact (108), configured to localize contact between the top electrode (202) and the device (110).

14. The semiconductor apparatus of claim 13, wherein the point of controlled contact(108) is provided in an area having lowest displacement of the device (110).

15. An apparatus, comprising at least one semiconductor chip (100) according to any of claims 1-14.

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