Semiconductor device and vehicle

Abstract

The purpose of the present invention is to facilitate the task of interconnecting a main terminal of a semiconductor module and an external terminal of a capacitor module. This semiconductor device (1) comprises: a semiconductor module (2) in which an outer terminal part (1102) exposed on the outside of a first main terminal (11) and an outer terminal part (1202) exposed on the outside of a second main terminal (12) are posititioned adjacent to each other on a first surface of an insulating member (600); and a capacitor module (3) having a first external terminal (21) connected to the outer terminal part of the first main terminal, and a second external terminal (22) positioned between the first external terminal and the second main terminal and connected to the outer terminal part of the second main terminal. The first external terminal of the capacitor module has an opening region (2102) overlapping the outer terminal part of the second main terminal as seen in a plan view of a surface connecting with the outer terminal part of the first main terminal. The second external terminal of the capacitor module is connected to a region of the outer terminal part of the second main terminal that is within the opening region of the first external terminal as seen in plan view.

Description

Semiconductor device and vehicle

[0001] The present invention relates to a semiconductor device and a vehicle.

[0002] Some semiconductor devices used in power conversion devices include a semiconductor module in which an inverter circuit is formed and a capacitor module connected to the semiconductor module (Patent Documents 1 to 4).The semiconductor module used in this type of semiconductor device includes a first main terminal and a second main terminal connected to the first external terminal and the second external terminal, respectively, of the capacitor module, which are arranged along the direction in which the first external terminal and the second external terminal extend from the housing of the capacitor module.

[0003] JP 2018-190965 A JP 2010-219216 A JP 2023-62046 A JP 2009-5512 A

[0004] In the semiconductor device described above, connecting the main terminals of the semiconductor module to the external terminals of the capacitor module is time-consuming. The present invention has been made in view of this problem, and one object of the present invention is to facilitate the work of connecting the main terminals of the semiconductor module to the external terminals of the capacitor module.

[0005] A semiconductor device according to one aspect of the present invention includes a semiconductor module in which an external terminal portion of a first main terminal exposed to the outside and an external terminal portion of a second main terminal exposed to the outside are arranged adjacent to each other on a first surface of an insulating member, and a capacitor module having a first external terminal connected to the external terminal portion of the first main terminal and a second external terminal located between the first external terminal and the second main terminal and connected to the external terminal portion of the second main terminal, wherein the first external terminal of the capacitor module has a shape having an opening region that overlaps with the external terminal portion of the second main terminal in a plan view of a connection surface with the external terminal portion of the first main terminal, and the second external terminal of the capacitor module is connected to a region of the external terminal portion of the second main terminal that is within the opening region of the first external terminal in the plan view.

[0006] According to the present invention, the work of connecting the main terminals of the semiconductor module and the external terminals of the capacitor module can be facilitated.

[0007] 6A and 6B are partially enlarged top views illustrating another example of the shapes of the first and second main terminals of the semiconductor module and the first and second external terminals of the capacitor module. 6A and 6B are partially enlarged top views illustrating another example of the shapes of the first and second main terminals of the semiconductor module and the first and second external terminals of the capacitor module. 6B are partially enlarged top views (FIG. 7A) and 7B) illustrating a modified example of the first external terminal of the capacitor module. 6C are a bottom view (FIG. 8A) and 8C) illustrating a modified example of the second external terminal of the capacitor module. 6D are a top view illustrating another modified example of the semiconductor device. 6E are a circuit diagram illustrating an example of the circuit configuration of the semiconductor device of FIG. 6F. 6G are a schematic plan view illustrating an example of a vehicle to which the semiconductor device according to the embodiment is applied.

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the X-axis, Y-axis, and Z-axis in each of the referenced figures are shown for the purpose of defining planes and directions in the illustrated semiconductor device, etc. The X-axis, Y-axis, and Z-axis are orthogonal to one another and form a right-handed system. In the following description, the direction parallel to the X-axis will be referred to as the X-direction, the direction parallel to the Y-axis will be referred to as the Y-direction, and the direction parallel to the Z-axis will be referred to as the Z-direction. Furthermore, when relating the X-direction, Y-direction, and Z-direction to the directions of the arrows (positive and negative) of the X-axis, Y-axis, and Z-axis shown in the drawings, the "positive side" and "negative side" will be added.

[0009] In this specification, the Z direction may be referred to as the up-down direction. In this specification, "up" and "above" refer to the positive side of the Z direction relative to a reference surface, component, position, etc., and "down" and "below" refer to the negative side of the Z direction relative to a reference surface, component, position, etc. For example, when describing "component B is placed on component A," component B is placed on the positive side of the Z direction relative to component A. Furthermore, when describing the "top surface of component A," this surface is located at the end of component A on the positive side of the Z direction and faces the positive side of the Z direction. In this specification, "top view" refers to a planar view of a target item (e.g., a semiconductor device, etc.) as viewed from the positive side of the Z direction. In this specification, "side view" refers to a planar view of a target item as viewed from the negative side or positive side of the X direction. A planar view from the negative side of the X direction is sometimes referred to as a "left side view," and a planar view from the positive side of the X direction is sometimes referred to as a "right side view." These directions and surfaces are used for convenience of explanation, and their correspondence with the X-axis, Y-axis, and Z-axis directions may change depending on the mounting orientation of the semiconductor device. For example, in this specification, the surface of a semiconductor element facing the wiring board is referred to as the bottom surface, and the surface opposite the bottom surface is referred to as the top surface. However, this is not limited to this, and the surface facing the wiring board may be referred to as the top surface, and the surface opposite the bottom surface may be referred to as the bottom surface. The bottom and top surfaces of a semiconductor element may also be referred to as side surfaces. Furthermore, the aspect ratios and the size relationships between components in each figure are merely schematic representations and do not necessarily correspond to the relationships in an actually manufactured semiconductor device. For convenience of explanation, it is assumed that the size relationships between components may be exaggerated. Furthermore, for convenience of explanation, some cross-sectional views show the cross-sectional configuration of a semiconductor device cut along an imaginary cutting line that cannot be accurately shown in a top view (plan view). Furthermore, some cross-sectional views simply show portions of the semiconductor device located deep within the cross section.

[0010] Furthermore, the semiconductor device exemplified in the following description may be applied to, for example, a power conversion device for industrial or electrical equipment (e.g., automotive electrical equipment). Specifically, the semiconductor device exemplified in this specification includes a semiconductor module in which an inverter circuit is formed and a capacitor module electrically connected to the inverter circuit of the semiconductor module. Therefore, in the following description, detailed descriptions of the configuration, function, operation, manufacturing method, etc. of the exemplified semiconductor device that are the same as or similar to those of known semiconductor devices will be omitted.

[0011] FIG. 1 is a top view showing an example of the configuration of a semiconductor device according to one embodiment. FIG. 2 is a cross-sectional view illustrating an example of the cross-sectional configuration of the semiconductor device of FIG. 1. FIG. 3 is a perspective view illustrating an example of the configuration of a first main terminal and a second main terminal of a semiconductor module. FIG. 4 is a circuit diagram showing an example of the circuit configuration of the semiconductor device. The cross-sectional view of FIG. 2 may be a cross-sectional configuration taken along the dashed dotted line A-A' in the semiconductor device 1 illustrated in FIG. 1.

[0012] The semiconductor device 1 illustrated in FIGS. 1 and 2 includes a semiconductor module 2 and a capacitor module 3. The semiconductor module 2 includes three inverter circuits 200U, 200V, and 200W, each having the same circuit configuration. Each of the inverter circuits 200U, 200V, and 200W includes, for example, a half-bridge inverter circuit such as that shown in FIG. 4 . As an example, the inverter circuit 200 (e.g., the inverter circuit 200U) formed in the semiconductor module 2 may include a wiring board 5 and a case 6 arranged on the upper surface of the heat sink 4, semiconductor elements 7A and 7B arranged on the upper surface of the wiring board 5, and wiring members such as leads 8. The case 6 is provided with main terminals 11-13, control terminals 14A and 14B, and auxiliary control terminals 15A and 15B, which are used as external terminals of the inverter circuit 200.

[0013] The heat sink 4 is a thermally conductive component that conducts heat generated by the semiconductor elements 7A and 7B during operation to the cooler 9. It may be a metal plate with high thermal conductivity, such as aluminum or an aluminum alloy, copper or a copper alloy. The heat sink 4 may be a single (single) plate-like member shared by the three inverter circuits 200U, 200V, and 200W, or a plate-like member provided separately for each inverter circuit. The heat sink 4 may have heat dissipation fins on its underside. The heat sink 4 may be one of the components of the cooler 9, or a plate-like member provided separately from the cooler 9 that can be attached to the cooler 9. The cooler 9 applicable to the semiconductor device 1 of this embodiment is not limited to a specific cooling method or structure. That is, the cooler 9 is an optional component in the semiconductor device 1 of this embodiment, and the semiconductor device 1 may not include the cooler 9.

[0014] The wiring board 5 includes an insulating plate 500, conductor patterns 501 and 502 arranged on the upper surface of the insulating plate 500, and a metal plate 503 arranged on the lower surface of the insulating plate 500. A conductor pattern other than the conductor patterns 501 and 502 illustrated in FIG. 2 is also arranged on the upper surface of the insulating plate 500. The wiring board 5 may be, for example, a direct copper bonding (DCB) board or an active metal brazing (AMB) board, but is not limited to such boards. The wiring board 5 may also be called a laminated board, an insulating circuit board, or the like.

[0015] The insulating plate 500 is made of, for example, aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ ), or aluminum oxide (Al ２ O ３ ) and zirconium oxide (ZrO ２The insulating plate 500 may be a ceramic substrate formed of a ceramic material such as a composite material with a ceramic material (e.g., a ceramic substrate with a ceramic material such as a silicon dioxide particle or a silicon dioxide powder). The insulating plate 500 may be, for example, a substrate formed of an insulating resin such as an epoxy resin, a substrate formed by impregnating a substrate such as glass fiber with an insulating resin, or a substrate formed by coating the surface of a flat metal core with an insulating resin. The conductor patterns 501 and 502 arranged on the upper surface of the insulating plate 500, as well as other conductor patterns not shown, function as wiring within the inverter circuit 200 illustrated in FIG. 4. The conductor patterns arranged on the upper surface of the insulating plate 500, such as the conductor patterns 501 and 502, are formed of metal foil such as copper or aluminum. The conductor patterns may also be referred to as wiring patterns, conductive layers or plates, conductor layers or conductor plates, etc. The metal plate 503 arranged on the lower surface of the insulating plate 500 functions as a heat conducting component that conducts heat generated by the semiconductor elements 7A and 7B to the heat sink 4. The metal plate 503 is formed of metal foil such as copper or aluminum. The metal plate 503 is joined to the heat sink 4 with a joining material such as solder. For convenience, in this specification, the conductive layer disposed on the lower surface of insulating plate 500 is referred to as "metal plate 503" to distinguish it from a "conductor pattern" disposed on the upper surface of insulating plate 500 and used as wiring. Instead of wiring substrate 5, semiconductor module 2 may have a configuration in which, for example, an insulating resin layer corresponding to insulating plate 500 is formed on the upper surface of heat sink 4, and conductor patterns 501 and 502, etc. are disposed on the insulating resin layer.

[0016] The semiconductor elements 7A and 7B are circuit components sometimes called semiconductor chips or dies, and each may be, for example, an RC (reverse conducting)-IGBT element formed with an IGBT (insulated gate bipolar transistor) element 711, which is a switching element, and a diode element 712 connected in anti-parallel to the IGBT element 711 (see FIG. 4 ). The diode element 712 may also be called an FWD (free wheeling diode). The switching element of the semiconductor elements 7A and 7B is not limited to the IGBT element 711, and may be, for example, a power MOSFET (metal oxide semiconductor field effect transistor) element, a BJT (bipolar junction transistor) element, or the like. The diode element 712 of the semiconductor elements 7A and 7B may be, for example, a SBD (Schottky barrier diode), a JBS (junction barrier Schottky) diode element, an MPS (merged PN Schottky) diode element, a PN diode element, or the like.

[0017] Each of the semiconductor elements 7A and 7B has one of the electrodes (e.g., the collector electrode of the IGBT element 711 or the drain electrode of the power MOSFET element) on its underside, which conducts the main current to the switching element, and the electrode on the underside is joined to the conductor pattern of the wiring board 5 with a bonding material such as solder. The other of the electrodes (e.g., the emitter electrode of the IGBT element 711 or the source electrode of the power MOSFET element) on its upper side, which conducts the main current to the switching element, is connected to the conductor pattern of the wiring board 5 with a wiring member such as a lead 8. Furthermore, each of the semiconductor elements 7A and 7B has a gate electrode on its upper side, which controls the operation of the switching element. The gate electrodes of the semiconductor elements 7A and 7B are electrically connected to control terminals 14A and 14B, respectively, provided on the case 6 via a wiring member, the conductor pattern of the wiring board 5, and the like.

[0018] The semiconductor elements used in the inverter circuit 200 are not limited to those formed with switching elements such as RC-IGBT elements and diode elements. For example, the inverter circuit 200 may be configured such that semiconductor elements formed with switching elements such as IGBT elements and semiconductor elements formed with diode elements used as FWDs are connected by wiring members. Sets of IGBT elements 711 and diode elements 712 formed on multiple separate semiconductor elements may be connected in parallel between the first main terminal 11 and the third main terminal 13, and between the third main terminal 13 and the second main terminal 12. The semiconductor substrates on which the switching elements and diode elements of the semiconductor elements are formed are not limited to silicon (Si) substrates, and may be wide bandgap semiconductor substrates such as silicon carbide (SiC) substrates and gallium nitride (GaN) substrates.

[0019] The case 6 is integrally formed by insert molding of an insulating resin part 600 having a peripheral wall that surrounds the wiring board 5 and the semiconductor elements 7A and 7B in a plan view of the upper surface of the heat sink 4, and a plurality of terminal parts (e.g., main terminals 11 to 13, control terminals 14A and 14B, and auxiliary control terminals 15A and 15B). As described above, each of the terminal parts has an inner terminal part that extends into the space surrounded by the peripheral wall part of the insulating resin part 600, and an outer terminal part that is exposed along the upper surface of the insulating resin part 600.

[0020] The first main terminal 11 has an inner terminal portion 1101 connected to the collector electrode of the semiconductor element 7A and an outer terminal portion 1102 connected to the first external terminal 21 of the capacitor module 3 (see FIG. 4 ). The second main terminal 12 has an inner terminal portion 1201 connected to the emitter electrode of the semiconductor element 7B and an outer terminal portion 1202 connected to the second external terminal 22 of the capacitor module 3. The third main terminal 13 has an inner terminal portion connected to the emitter electrode of the semiconductor element 7A and the collector electrode of the semiconductor element 7B and an outer terminal portion connected to a load. The capacitor module 3 is connected in parallel with the inverter circuit 200 illustrated in FIG. 4 and includes a capacitor 23 that functions as a smoothing capacitor in a power conversion device including the semiconductor device 1. One electrode of the capacitor 23 is connected to the first external terminal 21 and the other electrode is connected to the second external terminal 22. The first external terminal 21 and the second external terminal 22 of the capacitor module 3 in the semiconductor device 1 of this embodiment each extend in the −Y direction from a side surface 301 of the housing that houses the capacitor 23 and that faces the semiconductor module 2. In the semiconductor device 1 illustrated in FIG. 1 , the first external terminal 21 extends from the side surface 301 of the housing as a single terminal shared by the three inverter circuits 200 of the semiconductor module 2, and the second external terminal 22 extends from the side surface 301 of the housing as separate terminals 22U, 22V, and 22W for each inverter circuit 200.

[0021] In the semiconductor module 2 of this embodiment, the outer terminal portion 1102 of the first main terminal 11 and the outer terminal portion 1202 of the second main terminal 12 are arranged along the Y direction in a portion of the insulating resin part 600 that is on the positive side in the Y direction of the space in which the semiconductor elements 7A and 7B, etc. are arranged. More specifically, in plan view, the outer terminal portion 1202 of the second main terminal 12 is arranged between the outer terminal portion 1102 of the first main terminal 11 and the edge of the insulating resin part 600 on the positive side in the Y direction. As illustrated in Fig. 3 , the outer terminal portion 1102 of the first main terminal 11 has a region that overlaps with a routing portion between the inner terminal portion 1201 and the outer terminal portion 1202 of the second main terminal 12 in plan view, and this overlapping region is insulated from the routing portion of the second main terminal 12 by the insulating resin part 600.

[0022] The control terminal 14A and the auxiliary control terminal 15A are connected to the gate electrode and the emitter electrode of the semiconductor element 7A, respectively. The outer terminal portions of the control terminal 14A and the auxiliary control terminal 15A are connected to a gate drive circuit that generates a control signal to be applied to the gate of the switching element (e.g., the IGBT element 711) of the semiconductor element 7A. The control terminal 14B and the auxiliary control terminal 15B are connected to the gate electrode and the emitter electrode of the semiconductor element 7B, respectively. The outer terminal portions of the control terminal 14B and the auxiliary control terminal 15B are connected to a gate drive circuit that generates a control signal to be applied to the gate of the switching element (e.g., the IGBT element 711) of the semiconductor element 7B. The auxiliary control terminals 15A and 15B may be called auxiliary emitter terminals, emitter sense terminals, etc. when the switching element is the IGBT element 711, or may be called auxiliary source terminals, etc. when the switching element is a power MOSFET element. The terminal components of the case 6 may include additional auxiliary control terminals connected to a temperature sensing section that may be included in the semiconductor device 1 and to temperature sensing electrodes that measure the temperatures of the semiconductor elements 7A and 7B.

[0023] 5 is a partially enlarged top view illustrating a first example of the shapes of the first and second main terminals of the semiconductor module and the first and second external terminals of the capacitor module. Fig. 5 also illustrates an enlarged view of the connection between the first and second main terminals 11 and 12 of the inverter circuit 200W at the right end of the semiconductor device 1 in Fig. 1 and the first and second external terminals 21 and 22W of the capacitor module 3. The connection between the first and second main terminals 11 and 12 of the other inverter circuits 200U (or 200V) and the first and second external terminals 21 and 22U (or 22V) of the capacitor module 3 may also have a similar configuration. In the following description, a "planar view" that does not specify a plane refers to an XY planar view.

[0024] The first external terminal 21 of the capacitor module 3 has a receptacle portion 2101 that overlaps the upper surface of the outer terminal portion 1102 of the first main terminal 11 of the inverter circuit 200W in a plan view of the top surface of the semiconductor module 2 and is connected to the first main terminal 11. The first external terminal 21 also has an opening region 2102 that includes at least a portion of the overlapping region between the outer terminal portion 1202 of the second main terminal 12 of the semiconductor module 2 and the receptacle portion of the second external terminal 22W of the capacitor module 3 in a plan view. The opening region 2102 of the first external terminal 21 is located between the receptacle portion 2101 and the side surface 301 of the capacitor module 3 in a plan view. The opening region 2102 illustrated in FIG. 5 is rectangular with sides extending in the X direction and sides extending in the Y direction, and the end on the positive side in the Y direction reaches the side surface 301 of the capacitor module 3. 5 , the second external terminal 22W, which is located behind the first external terminal 21 (on the negative side in the Z direction), has a first region that is within the opening region 2102 of the first external terminal 21 in a plan view, and regions that are located on the positive and negative X-direction sides of the first region and overlap with the first external terminal 21. In Fig. 5 , of the outline of the second external terminal 22W, sections that are visible in a plan view and pass through the opening region 2102 of the first external terminal 21 are indicated by solid lines, and sections that are not visible because of the first external terminal 21 are indicated by dashed lines. Also, in Fig. 5 , of the outlines of the semiconductor module 2, the first main terminal 11, and the second main terminal 12, sections that are visible in a plan view are indicated by solid lines, and sections that are not visible because they overlap with the first external terminal 21 and / or the second external terminal 22W are indicated by dotted lines.

[0025] As described above, the first external terminal 21 of the capacitor module 3 according to this embodiment has an opening region 2102 that exposes an overlapping region (connection region) between the second external terminal 22W located toward the back (negative side in the Z direction) of the first external terminal 21 in a plan view and the second main terminal 12, between the connected portion 2101 that is connected to the outer terminal portion 1102 of the first main terminal 11 of the semiconductor module 2 and the side surface 301 of the housing. Therefore, the outer terminal portion 1202 of the second main terminal 12 and the connected portion of the second external terminal 22W can be joined, for example, by laser welding in which a laser is irradiated onto the connected portion of the second external terminal 22W through the opening region 2102 of the first external terminal 21. In other words, by irradiating a laser within one joining area 25 contained in the opening area 2102 of the first external terminal 21 in a planar view, the outer terminal portion 1202 of the second main terminal 12 and the connected portion of the second external terminal 22W can be joined.

[0026] When the outer terminal portion 1202 of the second main terminal 12 and the connection portion of the second external terminal 22W are joined by laser welding, the opening region 2102 of the first external terminal 21 is formed with planar dimensions such that the joining region 25 of the second external terminal 22W and a rectangular annular clearance region surrounding the joining region 25 are contained within the opening region 2102 in a plan view. The joining region 25 is intended to be a rectangular region circumscribing the region irradiated with the laser, and the X-direction dimension X1 and the Y-direction dimension Y1 may be, for example, X1 = 15 mm and Y1 = 3 mm. The clearance region is an area secured to prevent a portion of the laser irradiated on the joining region 25 from hitting the first external terminal 21, and the X-direction width L1 may be, for example, 2 mm. In this case, the X-direction dimension X2 (= X1 + 2 × L1) of the opening region 2102 illustrated in FIG. 5 may be 19 mm.

[0027] 5 has an X-direction dimension X3 that is smaller than the X-direction dimension X4 of the outer terminal portion 1202 of the second main terminal 12 and larger than the X-direction dimension X2 of the opening region 2102 of the first external terminal 21. In this example, the X-direction dimension L2 of the region of the second external terminal 22W that overlaps with the first external terminal 21 at both ends in the X-direction may be, for example, 2 mm, and the difference (2×L3) between the X-direction dimension X3 of the second external terminal 22W and the X-direction dimension of the outer terminal portion 1202 of the second main terminal 12 may be, for example, 4 mm (i.e., dimension L3 is 2 mm). Therefore, if the X-direction dimension X1 of the bonding region 25 is 15 mm as described above, the X-direction dimension X4 of the outer terminal portion 1202 of the second main terminal 12 is approximately 27 mm.

[0028] Furthermore, the position in the Y direction of the end portion of the opening region 2102 of the first external terminal 21 on the negative side in the Y direction (in other words, the end portion located between the bonding region 24 and the bonding region 25) is set so that the distance from the bonding region 24 and the distance from the bonding region 25 satisfy a predetermined clearance. The bonding region 24 is a region in the connected portion 2101 of the first external terminal 21 that overlaps with the outer terminal portion 1102 of the first main terminal 11 in a plan view and is irradiated with a laser. The distance from the bonding region 24 can be, for example, a distance that prevents part of the laser from passing through the opening region 2102 of the first external terminal 21 and hitting an underlying member during the step of irradiating the bonding region 24 with a laser. The distance from the bonding region 25 can be a distance that prevents part of the laser irradiated into the bonding region 25 from hitting the first external terminal 21.

[0029] Furthermore, the position in the Y direction of the end of the first external terminal 21 on the positive side in the Y direction in the opening region 2102 (in other words, the end located between the bonding region 25 and the side surface 301 of the housing of the capacitor module 3) is preferably the position of the side surface 301 of the housing of the capacitor module 3, as illustrated in FIG. 5 . That is, by making the dimension in the Y direction of the opening region 2102 (the extension direction of the second external terminal 22W) as large as possible, the effect of preventing heat from being trapped between the first external terminal 21 and the second external terminal 22W that are stacked at a predetermined interval is enhanced. Note that the position of the end of the first external terminal 21 on the positive side in the Y direction in the opening region 2102 needs only to be set so that the distance from the bonding region 25 satisfies a predetermined clearance, and does not have to reach the side surface 301 of the housing of the capacitor module 3, as will be described later with reference to FIGS. 6A and 6B .

[0030] 5 is 3 mm, the Y-direction dimension Y2 of the overlapping region between the connected portion of the second external terminal 22W and the outer terminal portion 1202 of the second main terminal 12 can be set to, for example, 9 mm. The Y-direction dimension Y3 of the outer terminal portion 1202 of the second main terminal 12 can have a magnitude relationship with the Y-direction dimension Y2 of the overlapping region such that Y3 > Y2, as shown in FIG. 5, but is not limited to this, and the dimension difference Y3 - Y2 may also be 0.

[0031] 6A and 6B are partially enlarged top views illustrating other examples of the shapes of the first and second main terminals of the semiconductor module and the first and second external terminals of the capacitor module. In Figures 6A and 6B, the sections of the outlines of the semiconductor module 2, the first main terminal 11, and the second main terminal 12 that are visible in a plan view are indicated by solid lines, while the sections that are not visible because the first external terminal 21 or the second external terminal 22W overlaps them to the front (positive side in the Z direction) are indicated by dotted lines. Furthermore, the sections of the outline of the second external terminal 22W that are visible in a plan view are indicated by solid lines, while the sections that are not visible because the first external terminal 21 overlaps them to the front (positive side in the Z direction) are indicated by dashed lines.

[0032] In the first external terminal 21 of the capacitor module 3 illustrated in FIG. 6A , the X-direction dimension X2 of the opening region 2102 is larger than the X-direction dimension X4 of the outer terminal portion 1202 of the second main terminal 12 of the semiconductor module 2. In other words, the semiconductor module 2 illustrated in FIG. 6A can reduce the area of ​​the outer terminal portion 1202 of the second main terminal 12 based on the dimension of one bonding region 25 (see FIG. 5 ). Therefore, compared to a semiconductor device in which the dimensions, position, etc. of the outer terminal portion 1202 of the second main terminal 12 are adjusted to provide a bonding region that does not overlap with the first external terminal that does not have the opening region 2102 in a plan view, the amount (volume) of conductive material used to form the second main terminal 12 can be reduced, thereby reducing the manufacturing cost of the semiconductor module 2. Furthermore, as illustrated in FIG. 6A , the opening region 2102 of the first external terminal 21 may have an end on the positive Y-direction side closer to the bonding region than the side surface 301 of the housing of the capacitor module 3. Because such a first external terminal 21 is in the form of a single plate at the side surface 301 of the housing of the capacitor module 3, it is less likely to deform at the side surface 301 of the capacitor module 3 than when it is divided into multiple separate parts by the opening region 2102 at the side surface 301 of the capacitor module 3 as illustrated in Fig. 5. Therefore, it is possible to suppress, for example, a decrease in the accuracy of alignment between the connected portion of the first external terminal 21 and the outer terminal portion 1102 of the first main terminal 11 due to deformation of the first external terminal 21.

[0033] Furthermore, when the opening region 2102 of the first external terminal 21 is rectangular in plan view, the cross-sectional area of ​​the current path between the connected portion 2101 of the first external terminal 21 and the capacitor 23 (see FIG. 4 ) may be reduced around the end on the negative side in the Y direction (i.e., the end located between the bonding region 24 and the bonding region 25 in FIG. 5 ), making it difficult for current to flow. For this reason, the opening region 2102 of the first external terminal 21 may have a shape that prevents the cross-sectional area of ​​the first external terminal 21 from becoming smaller at the end on the negative side in the Y direction, located between the bonding region 24 and the bonding region 25, as shown in FIG. 6B , for example. The opening region 2102 illustrated in FIG. 6B has sections 2102 a and 2102 b inclined with respect to the X and Y directions at both ends in the X direction (the lower left and lower right corners in the figure) of the end on the negative side in the Y direction, thereby widening the width W in plan view and thereby preventing the cross-sectional area of ​​the first external terminal 21 from becoming smaller. The shape of the opening region 2102 for preventing the cross-sectional area of ​​the first external terminal 21 from becoming smaller can be changed within the range in which the outer terminal portion 1202 of the second main terminal 12 and the second external terminal 22W can be connected within the opening region 2102, and is not limited to a specific shape.

[0034] FIG. 7A is a partially enlarged top view illustrating a modified first external terminal of the capacitor module, and FIG. 7B is a cross-sectional view taken along dashed line B-B' in FIG. 7A . FIG. 8A is a bottom view illustrating a modified second external terminal of the capacitor module, and FIG. 8B is a cross-sectional view taken along dashed line C-C' in FIG. 8A . In FIG. 7A , solid lines indicate visible sections of the outlines of the semiconductor module 2, first main terminal 11, and second main terminal 12 in a plan view, while dotted lines indicate sections that are not visible because the first external terminal 21 or the second external terminal 22W overlaps them to the front (positive side in the Z direction). Furthermore, solid lines indicate visible sections of the outlines of the second external terminal 22W in a plan view. Furthermore, dashed lines indicate sections of the outlines of the first external terminal 21 and the second external terminal 22W that are not visible because they are inside the housing of the capacitor module 3.

[0035] The first external terminals 21 in the capacitor module 3 according to this embodiment are not limited to those manufactured by a specific manufacturing method. The first external terminals 21 illustrated in FIG. 5 and other figures may have opening regions 2102 formed by punching using a die (punch). However, the first external terminals 21 are not limited to such a method. As illustrated in FIGS. 7A and 7B , a portion or all of a portion that becomes unnecessary due to the formation of the opening region 2102 may be folded to form a connection portion 2101 to be joined to the outer terminal portion 1102 of the first main terminal 11. In the example illustrated in FIGS. 7A and 7B , when the opening region 2102 is formed in the first external terminal 21, both edges in the X direction and the edge on the positive side in the Y direction of the outline of the region to be the opening region 2102 are cut. Thereafter, the portion remaining within the region to be the opening region 2102 (e.g., the portion within the rectangular region indicated by the two-dot chain line in FIG. 7B ) is bent at the edge on the negative side in the Y direction of the outline of the region to be the opening region 2102 to provide the connection portion 2101 of the first external terminal 21. In this case, the portion bent to form the opening region 2102 may be bent upward instead of downward as illustrated in FIGS. 7A and 7B . In the first external terminal 21 illustrated in FIGS. 7A and 7B , the connection portion 2101 extending to the negative side in the Y direction from the annular region surrounding the opening region 2102 described with reference to FIG. 5 and the like is formed using a portion that becomes unnecessary after the opening region 2102 is formed. This reduces the planar dimensions of the conductive material required to form the first external terminal 21, thereby suppressing increases in the manufacturing cost of the capacitor module 3 (semiconductor device 1).

[0036] Furthermore, in the semiconductor device 1 of this embodiment, the second external terminal 22 of the capacitor module 3 is not limited to the shape extending from the side surface of the housing as the separate external terminals 22U, 22V, and 22W for each inverter circuit 200 described above. The second external terminal 22 of the capacitor module 3 may extend from the side surface 301 of the housing of the capacitor module 3 as a single (single) plate-like member shared by the three inverter circuits 200, as illustrated in FIGS. 8A and 8B . The regions of the second external terminal 22 indicated by the reference symbols 22U′, 22V′, and 22W′ in FIGS. 8A and 8B may respectively include the bonding regions with the second main terminal 12 of the semiconductor module 2 and the surrounding clearance regions of the external terminals 22U, 22V, and 22W illustrated in FIG. 1 . This increases the surface area of ​​the second external terminal 22, thereby improving the efficiency of heat dissipation from the second external terminal 22. 8A and 8B , when the second external terminal 22 is a single (single) plate-like member shared by three inverter circuits 200, an opening region 2202 may be formed in a region of the second external terminal 22 that does not overlap with the opening region 2102 of the first external terminal 21. Forming the opening region 2202 in the second external terminal 22 prevents heat from building up between the first external terminal 21 and the second external terminal 22 that are stacked.

[0037] Fig. 9 is a top view illustrating another configuration example of a semiconductor device. Fig. 10 is a circuit diagram illustrating a circuit configuration example of the semiconductor device of Fig. 9. Fig. 9 illustrates only a configuration example of a portion of the semiconductor device 1 in which one three-level inverter circuit 220U is formed. A configuration similar to that of the portion illustrated in Fig. 9 may be repeated in a portion (not shown) extending in the X direction from the portion illustrated in Fig. 9.

[0038] The semiconductor module 2 of the semiconductor device 1 of this embodiment is not limited to the one having three main terminals as illustrated in FIG. 1 , but may also have four main terminals as illustrated in FIG. 9 . In the semiconductor module 2 illustrated in FIG. 9 , the first main terminal 11, the second main terminal 12, and the intermediate terminal 16 are arranged in a portion of the insulating resin part 600 of the case 6 on the positive side in the Y direction relative to the space in which the semiconductor elements 7A to 7D are arranged. Specifically, in a plan view, the outer terminal portion 1102 of the first main terminal 11 and the outer terminal portion 1202 of the second main terminal 12 are arranged between the outer terminal portion 1602 of the intermediate terminal 16 and the edge of the insulating resin part 600 on the positive side in the Y direction. The outer terminal portion 1102 of the first main terminal 11 and the outer terminal portion 1202 of the second main terminal 12 are arranged in a direction (X direction) along the edge of the insulating resin part 600 on the positive side in the Y direction. The semiconductor module 2 illustrated in Fig. 9 is formed with, for example, a three-level inverter circuit 220U as shown in Fig. 10. While Fig. 10 illustrates a power MOSFET element as the switching element formed in each of the semiconductor elements 7A to 7D, the switching elements may also be IGBT elements or the like. Furthermore, a semiconductor element illustrated as a single semiconductor element (for example, semiconductor element 7A) may be a combination of a semiconductor element formed with a switching element and a semiconductor element formed with a diode element.

[0039] 9 includes a first external terminal 21 connected to the first main terminal 11, a second external terminal 22 connected to the second main terminal 12, and a third external terminal 26 connected to the intermediate terminal 16. A first capacitor 23A and a second capacitor 23B are disposed within the housing of the capacitor module 3. One electrode of the first capacitor 23A is connected to the first external terminal 21, and the other electrode is connected to the third external terminal 26. One electrode of the second capacitor 23B is connected to the third external terminal 26, and the other electrode is connected to the second external terminal 22.

[0040] 9 , for example, an opening region 2602 is formed in the third external terminal 26 that connects to the outer terminal portion of the intermediate terminal 16 that is farthest from the side surface 301 of the housing of the capacitor module 3 in the semiconductor module 2. The opening region 2602 of the third external terminal 26 is formed with dimensions that, when the connected portion 2601 located on the negative side of the Y direction from the opening region 2602 is connected to the intermediate terminal 16, include at least a portion of the overlapping region between the first main terminal 11 and the first external terminal 21 and at least a portion of the overlapping region between the second main terminal 12 and the second external terminal 22 in a plan view. Note that the opening region 2602 of the third external terminal 26, the first external terminal 21, and the second external terminal 22 may be formed with dimensions such that the end of the first external terminal 21 on the negative side in the X direction and the end of the second external terminal 22 on the positive side in the X direction overlap the third external terminal 26.

[0041] Although the semiconductor device 1 of the above-described embodiment is not limited to a specific application, the semiconductor device 1 equipped with the cooler 9 is particularly suitable for semiconductor elements that generate a large amount of heat during operation (operating at high temperatures). For example, the semiconductor device 1 of the above-described embodiment can be applied to a power conversion device such as an inverter device for an in-vehicle motor. A vehicle to which the semiconductor device 1 according to the present invention is applied will be described with reference to FIG. 11 .

[0042] 11 is a schematic plan view showing an example of a vehicle to which the semiconductor device according to the embodiment is applied. The vehicle 3001 shown in FIG. 11 is, for example, a four-wheeled vehicle having four wheels 3002. The vehicle 3001 may be, for example, an electric vehicle in which the wheels are driven by a motor or the like, or a hybrid vehicle that uses power from an internal combustion engine in addition to a motor. Furthermore, the vehicle to which the semiconductor device 1 is applied is not limited to a four-wheeled vehicle, and may also be a two-wheeled vehicle, a railroad vehicle, or the like.

[0043] The vehicle 3001 includes a drive unit 3003 that applies power to the wheels 3002, and a control device 3004 that controls the drive unit 3003. The drive unit 3003 may be configured with at least one of a motor and a hybrid of an engine and a motor, for example.

[0044] The control device 3004 controls (e.g., controls power) the drive unit 3003. The control device 3004 includes the semiconductor device 1 including the cooler 9 of the above-described embodiment. The semiconductor device 1 can be configured to control power to the drive unit 3003.

[0045] The semiconductor device 1 according to the above-described embodiment may be applied to industrial power conversion devices, such as inverter devices for driving motors in elevators, escalators, building air conditioning systems, etc. Furthermore, the circuit formed in the semiconductor module 2 is not limited to the half-bridge inverter circuit illustrated in FIG. 4 or the three-level inverter circuit illustrated in FIG. 10 . For example, the circuit formed in the semiconductor module 2 may include only one half-bridge inverter circuit out of the three half-bridge inverter circuits illustrated in FIG. 4 . The circuit formed in the semiconductor module 2 may also be a full-bridge inverter circuit. Furthermore, the circuit formed in the semiconductor module 2 is not limited to a power conversion circuit that converts direct current to alternating current, but may be another circuit, or may include a power conversion circuit and another circuit.

[0046] Furthermore, in the semiconductor device 1 of this embodiment, the connection between the first main terminal 11 and the second main terminal 12 of the semiconductor module 2 and the first external terminal 21 and the second external terminal 22 of the capacitor module 3 is not limited to the laser welding described above. For example, another connection method, such as ultrasonic bonding, may be used in which energy is directly applied to the connection portions 2101 of the first external terminal 21 and the connection portions of the second external terminal 22 to form a connection. Furthermore, for example, in a connection method in which bonding is performed by melting a bonding material such as solder, it is also possible to prevent misalignment of the connection portions by holding the connection portions 2101 of the first external terminal 21 and the connection portions of the second external terminal 22 with a jig.

[0047] The features of the above-described embodiment are summarized below: The semiconductor device according to the above-described embodiment includes a semiconductor module in which an external terminal portion of a first main terminal exposed to the outside and an external terminal portion of a second main terminal exposed to the outside are arranged adjacent to each other on a first surface of an insulating member, and a capacitor module having a first external terminal connected to the external terminal portion of the first main terminal and a second external terminal located between the first external terminal and the second main terminal and connected to the external terminal portion of the second main terminal, wherein the first external terminal of the capacitor module has a shape having an opening region that overlaps with the external terminal portion of the second main terminal in a plan view of a connection surface with the external terminal portion of the first main terminal, and the second external terminal of the capacitor module is connected to a region of the external terminal portion of the second main terminal that is within the opening region of the first external terminal in the plan view.

[0048] In the semiconductor device according to the above embodiment, multiple pairs of the first main terminal and the second main terminal are arranged on the first surface of the insulating member in the semiconductor module, and the first external terminal of the capacitor module is a single terminal whose portion extending from the housing is connected to multiple first main terminals.

[0049] In the semiconductor device according to the above embodiment, the semiconductor module comprises a semiconductor element connected in series between the first main terminal and the second main terminal, and a third main terminal connected between the semiconductor elements connected in series, and the third main terminal is arranged on the opposite side of the first main terminal and the second main terminal across the area in which the semiconductor element is arranged in the planar view.

[0050] In the semiconductor device according to the above embodiment, the semiconductor module further has a third main terminal, and the capacitor module further has a third external terminal located between the first external terminal and the third main terminal and connected to an outer terminal portion of the third main terminal of the semiconductor module, and the third external terminal of the capacitor module is connected to an area of ​​the outer terminal portion of the third main terminal that is within the opening area of ​​the first external terminal when viewed in a plane.

[0051] In the semiconductor device according to the above embodiment, the semiconductor module further includes a semiconductor element connected in series between the second main terminal and the third main terminal, and the first main terminal is connected between the semiconductor elements connected in series.

[0052] In the semiconductor device according to the above embodiment, the second external terminal of the capacitor module is a single terminal whose portion extending from the housing is connected to a plurality of the second main terminals.

[0053] The vehicle according to the above-described embodiment includes the semiconductor device according to the above-described embodiment.

[0054] As described above, the present invention can facilitate the connection work between the main terminals of a semiconductor module and the external terminals of a capacitor module, and in particular, by applying it to a semiconductor device in which the main terminals of the semiconductor module are arranged along the extension direction of the external terminals from the side of the housing facing the semiconductor module in the capacitor module, it is possible to reduce the cost of the connection work.

[0055] This application is based on Japanese Patent Application No. 2024-112491, filed on July 12, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device comprising: a semiconductor module in which an external terminal portion of a first main terminal exposed to the outside and an external terminal portion of a second main terminal exposed to the outside are arranged adjacent to each other on a first surface of an insulating member; and a capacitor module having a first external terminal connected to the external terminal portion of the first main terminal, and a second external terminal located between the first external terminal and the second main terminal and connected to the external terminal portion of the second main terminal, wherein the first external terminal of the capacitor module has a shape with an opening region that overlaps with the external terminal portion of the second main terminal in a planar view of the connection surface with the external terminal portion of the first main terminal, and the second external terminal of the capacitor module is connected to a region of the external terminal portion of the second main terminal that is within the opening region of the first external terminal in the planar view.

2. The semiconductor device according to claim 1, wherein a plurality of pairs of the first main terminal and the second main terminal are arranged on the first surface of the insulating member in the semiconductor module, and the first external terminal of the capacitor module is a single terminal whose portion extending from the housing is connected to a plurality of the first main terminals.

3. The semiconductor device according to claim 1, wherein the semiconductor module comprises a semiconductor element connected in series between the first main terminal and the second main terminal, and a third main terminal connected between the semiconductor elements connected in series, and the third main terminal is arranged on the opposite side of the first main terminal and the second main terminal across the area in which the semiconductor element is arranged in the plan view.

4. The semiconductor device according to claim 1, wherein the semiconductor module further has a third main terminal, and the capacitor module further has a third external terminal located between the first external terminal and the third main terminal and connected to an outer terminal portion of the third main terminal of the semiconductor module, and the third external terminal of the capacitor module is connected to an area of ​​the outer terminal portion of the third main terminal that is within the opening area of ​​the first external terminal in the plan view.

5. The semiconductor device according to claim 4, wherein the semiconductor module further comprises a semiconductor element connected in series between the second main terminal and the third main terminal, and the first main terminal is connected between the semiconductor elements connected in series.

6. The semiconductor device according to claim 2, wherein the second external terminal of the capacitor module is a single terminal whose portion extending from the housing is connected to a plurality of the second main terminals.

7. A vehicle equipped with a semiconductor device according to any one of claims 1 to 6.

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