Wiring board and method for inspecting same

Abstract

A wiring board according to the present invention comprises a carrier substrate, a release layer, an intermediate layer, and a rewiring layer. The rewiring layer includes a plurality of stacked insulating layers and a plurality of electroconductive layers. The plurality of electroconductive layers include: a first electroconductive layer and second electroconductive layer; a third electroconductive layer and fourth electroconductive layer located over the intermediate layer; at least one electroconductive layer constituting a first path electrically connecting the first electroconductive layer and the third electroconductive layer; at least one electroconductive layer constituting a second path electrically connecting the second electroconductive layer and the fourth electroconductive layer; and at least one electroconductive layer constituting a third path electrically connecting a portion of the first path and a portion of the second path. The intermediate layer includes at least a first island portion surrounding the third electroconductive layer in plan view.

Description

Wiring board and inspection method thereof

[0001] An embodiment of the present disclosure relates to a wiring board and an inspection method thereof.

[0002] Packaging technology that densely mounts multiple semiconductor elements with different functions, such as CPUs and memories, on a single substrate has been attracting attention. A structure that electrically connects multiple semiconductor elements is also called an interposer. An interposer includes, for example, a wiring layer that includes a conductive layer and an insulating layer. The wiring layer performs the function of, for example, relocating pads or terminals of the semiconductor elements to another location. Such a wiring layer is also called a rewiring layer.

[0003] The redistribution layer is formed on a carrier substrate made of a rigid material such as glass. Patent Document 1 discloses a technology for using the redistribution layer peeled from the carrier substrate as an interposer. A peeling layer is provided between the carrier substrate and the redistribution layer. In the process of peeling the redistribution layer from the carrier substrate, for example, light is irradiated onto the peeling layer. Then, the redistribution layer is separated from the carrier substrate.

[0004] Japanese Patent Application Laid-Open No. 2021-18997

[0005] The manufacturing process of the redistribution layer includes a step of inspecting the continuity and short circuit of the wiring in the redistribution layer, and the electrical characteristics used for the inspection include electrical resistance and capacitance.

[0006] A conductive layer may be disposed between the redistribution layer and the carrier substrate, which may affect the measurement results of the electrical properties of the redistribution layer.

[0007] An object of the embodiments of the present disclosure is to provide a wiring board and an inspection method thereof that can effectively solve such problems.

[0008] Embodiments of the present disclosure relate to the following [1] to

[15] .

[0009] [1] A wiring board comprising: a carrier substrate; a release layer including a first lower surface facing the carrier substrate and a first upper surface located opposite the first lower surface; an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located opposite the second lower surface; and a redistribution layer including a third lower surface at least partially facing the second upper surface and a third upper surface located opposite the third lower surface, wherein the redistribution layer comprises a plurality of stacked insulating layers and a plurality of conductive layers, each of the plurality of conductive layers being in contact with at least one of the plurality of insulating layers, a wiring board, wherein the plurality of conductive layers include a first conductive layer and a second conductive layer located on the third upper surface, a third conductive layer and a fourth conductive layer located on the intermediate layer, at least one conductive layer constituting a first path electrically connecting the first conductive layer and the third conductive layer, at least one conductive layer constituting a second path electrically connecting the second conductive layer and the fourth conductive layer, and at least one conductive layer constituting a third path electrically connecting a portion of the first path and a portion of the second path, the first path and the second path being independent of each other, the intermediate layer including at least a first island portion surrounding the third conductive layer in a planar view, and the first island portion not overlapping the fourth conductive layer in a planar view.

[0010] [2] In the wiring board according to [1], the intermediate layer may include a second island portion that surrounds the fourth conductive layer in a plan view.

[0011] [3] In the wiring board according to [2], the intermediate layer may include a sea portion that surrounds the first island portion and the second island portion in a plan view.

[0012] [4] In the wiring board according to [3], the plurality of conductive layers may include at least one dummy conductive layer located on the sea portion and covered by the insulating layer.

[0013] [5] A wiring board comprising: a carrier substrate; a release layer including a first lower surface facing the carrier substrate and a first upper surface located on the opposite side of the first lower surface; an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located on the opposite side of the second lower surface; and a redistribution layer including a third lower surface at least partially facing the second upper surface and a third upper surface located on the opposite side of the third lower surface, wherein the redistribution layer comprises a plurality of stacked insulating layers and a plurality of conductive layers, each of the plurality of conductive layers being in contact with at least one of the plurality of insulating layers, and the plurality of conductive layers including a first conductive layer and a second conductive layer located on the third upper surface, a third conductive layer located on the intermediate layer, at least one conductive layer forming a first path electrically connecting the first conductive layer and the third conductive layer, and at least one conductive layer forming a second path electrically connecting the second conductive layer and the third conductive layer, wherein the first path and the second path are independent of each other, The intermediate layer includes at least a first island portion that surrounds the third conductive layer in a plan view.

[0014] [6] In the wiring board according to [5], the intermediate layer may include a sea portion that surrounds the first island portion in a plan view.

[0015] [7] In the wiring board according to [6], the plurality of conductive layers may include at least one conductive layer located on the sea portion.

[0016] [8] A wiring board comprising: a carrier substrate; a release layer including a first lower surface facing the carrier substrate and a first upper surface located on the opposite side of the first lower surface; an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located on the opposite side of the second lower surface; and a redistribution layer including a third lower surface at least partially facing the second upper surface and a third upper surface located on the opposite side of the third lower surface, wherein the redistribution layer comprises a plurality of stacked insulating layers and a plurality of conductive layers, each of the plurality of conductive layers being in contact with at least one of the plurality of insulating layers, and the plurality of conductive layers including a first conductive layer and a second conductive layer located on the third upper surface, a third conductive layer and a fourth conductive layer located on the intermediate layer, at least one conductive layer constituting a first path electrically connecting the first conductive layer and the third conductive layer, and at least one conductive layer constituting a second path electrically connecting the second conductive layer and the fourth conductive layer, wherein the first path and the second path are independent of each other, the intermediate layer includes at least a first island portion surrounding the third conductive layer in a plan view, and the first island portion does not overlap the fourth conductive layer in a plan view.

[0017] [9] In the wiring board according to [8], the intermediate layer may include a second island portion that surrounds the fourth conductive layer in a plan view.

[0018]

[10] In the wiring board according to [9], the intermediate layer may include a sea portion that surrounds the first island portion and the second island portion in a plan view.

[0019]

[11] In the wiring board according to

[10] , the plurality of conductive layers may include at least one conductive layer located on the sea portion.

[0020]

[12] In the wiring board according to any one of [1] to

[11] , the release layer may be insulating, and the intermediate layer may be conductive.

[0021]

[13] In the wiring board according to any one of [1] to

[11] , the intermediate layer may contain an inorganic material having insulating properties.

[0022]

[14] A method for inspecting a wiring board, comprising: a step of preparing the wiring board according to any one of [1] to

[11] ; a step of contacting a first probe with the first conductive layer; a step of contacting a second probe with the second conductive layer; and a step of measuring electrical resistance between the first probe and the second probe.

[0023]

[15] A method for inspecting a wiring board, comprising the steps of: preparing a wiring board according to any one of [1] to

[11] ; bringing a first probe into contact with the first conductive layer; arranging an inspection electrode on a lower surface of the carrier substrate; and measuring a capacitance between the first probe and the inspection electrode, wherein the carrier substrate includes the lower surface and an upper surface located opposite the lower surface, and the upper surface of the carrier substrate faces the first lower surface of the release layer.

[0024] According to the embodiments of the present disclosure, it is possible to properly inspect the continuity and short circuits of the wiring in the redistribution layer.

[0025] 1 is a plan view showing a wiring board group according to an embodiment. FIG. 2 is a cross-sectional view of the wiring board group taken along line II-II of FIG. 1. FIG. 3 is a cross-sectional view showing an example of a rewiring layer and an intermediate layer. FIG. 4 is a cross-sectional view showing an example of a conductive layer. FIG. 5 is a cross-sectional view showing an example of a rewiring layer. FIG. 6 is a plan view showing an example of a first wiring layer and an intermediate layer. FIG. 7 is a cross-sectional view showing a step of forming a release layer. FIG. 8 is a cross-sectional view showing a step of forming an intermediate layer and a seed layer. FIG. 9 is a cross-sectional view showing a step of forming a first resist layer. FIG. 10 is a cross-sectional view showing a step of forming a plating layer. FIG. 11 is a cross-sectional view showing a step of partially removing a seed layer. FIG. 12 is a cross-sectional view showing a step of forming a second resist layer. FIG. 13 is a cross-sectional view showing a step of partially removing an intermediate layer. FIG. 14 is a cross-sectional view showing a step of forming a first opening and a second opening in an intermediate layer. FIG. 15 is a cross-sectional view showing a step of forming an insulating layer. FIG. 16 is a cross-sectional view showing a step of dividing a wiring board group. FIG. 17 is a diagram showing an example of an equivalent circuit of a wiring board. FIG. 18 is a cross-sectional view showing an example of a step of inspecting a wiring board. FIG. 19 is a cross-sectional view showing a step of cutting a part of a wiring board. FIG. 19 is a cross-sectional view showing a step of bonding a third upper surface of a rewiring layer to a first member. 10A and 10B are cross-sectional views showing a step of separating the redistribution layer from the carrier substrate; a cross-sectional view showing a step of removing the intermediate layer; a cross-sectional view showing a step of bonding the third lower surface of the redistribution layer to a second member; a cross-sectional view showing an example of the redistribution layer in the first modified example; a cross-sectional view showing a step of removing the intermediate layer in the first modified example; a plan view showing an example of the third lower surface of the redistribution layer in the first modified example; a cross-sectional view showing a state in which solder is piled on the conductive layer constituting the pad in the first modified example; a cross-sectional view showing an example of the redistribution layer in the second modified example; a cross-sectional view showing an example of the redistribution layer and the intermediate layer in the third modified example; a cross-sectional view showing a step of forming a second resist layer in the fourth modified example; a cross-sectional view showing a step of partially removing the intermediate layer in the fourth modified example; a cross-sectional view showing a step of cutting a part of the redistribution layer in the fifth modified example; a cross-sectional view showing a step of separating the redistribution layer from the carrier substrate in the fifth modified example; a cross-sectional view showing a step of removing the intermediate layer in the fifth modified example; a cross-sectional view showing a step of dividing the redistribution layer in the fifth modified example.10. A cross-sectional view showing an example of a rewiring layer and an intermediate layer in a sixth modified example. A cross-sectional view showing an example of a rewiring layer in a sixth modified example. A plan view showing an example of a first wiring layer and an intermediate layer in a sixth modified example. A cross-sectional view showing an example of a rewiring layer and an intermediate layer in a seventh modified example. A cross-sectional view showing an example of a rewiring layer in a seventh modified example. A plan view showing an example of a first wiring layer and an intermediate layer in a seventh modified example. A cross-sectional view showing an example of a rewiring layer in an eighth modified example. A cross-sectional view showing an example of a rewiring layer in an eighth modified example. A plan view showing an example of a first wiring layer and an intermediate ... step of inspecting a wiring substrate in an eighth modified example. A diagram showing an example of an equivalent circuit of a wiring substrate in an eighth modified example. A cross-sectional view showing an example of a rewiring layer in a ninth modified example. A cross-sectional view showing an example of a step of inspecting a wiring substrate in a tenth modified example. A diagram showing an example of an equivalent circuit of a wiring substrate in a tenth modified example. A diagram showing an example of a product on which a through electrode substrate is mounted.

[0026] The configuration of a wiring board and a manufacturing method thereof will be described in detail with reference to the drawings. The following embodiments are examples of embodiments of the present disclosure, and the present disclosure should not be construed as being limited to these embodiments. Terms such as "substrate," "base material," "sheet," and "film" are not distinguished from one another solely based on differences in name. For example, the concept of "substrate" includes members called sheets or films. A "surface" refers to a surface that coincides with the planar direction of a target plate-like member when viewed holistically and comprehensively. A normal direction used with respect to a plate-like member refers to a normal direction to the surface of the member. Terms or values ​​related to shape and geometric conditions used in this specification may be interpreted based on function or effect without being bound by strict meaning. Terms related to shape and geometric conditions include "parallel," "orthogonal," etc. Values ​​related to shape and geometric conditions include length, angle, etc.

[0027] In this specification, when multiple upper limit value candidates and multiple lower limit value candidates are listed for a certain parameter, the numerical range of the parameter may be constructed by combining any one upper limit value candidate with any one lower limit value candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or more, or may be A2 or more, or may be A3 or more. Parameter B is, for example, A4 or less, or may be A5 or less, or may be A6 or less." In this case, the numerical range of parameter B may be A1 or more and A4 or less, A1 or more and A5 or less, A1 or more and A6 or less, A2 or more and A4 or less, A2 or more and A5 or less, A2 or more and A6 or less, A3 or more and A4 or less, A3 or more and A5 or less, or A3 or more and A6 or less.

[0028] In the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same or similar reference numerals, and repeated explanations thereof may be omitted. The dimensional ratios of the drawings may differ from the actual ratios for the sake of explanation. Parts of the configuration may be omitted from the drawings.

[0029] Fig. 1 is a plan view showing an example of a wiring board group 10. Fig. 2A is a cross-sectional view of the wiring board group 10 taken along line II-II in Fig. 1. The wiring board group 10 includes a plurality of wiring boards having the same structure. As will be described later, a plurality of wiring boards are obtained by dividing the wiring board group 10.

[0030] The wiring board group 10 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the surface direction of the wiring board group 10. The first direction D1 is perpendicular to the second direction D2. The third direction D3 is the thickness direction of the wiring board group 10. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0031] The wiring board group 10 includes a carrier substrate 12, a release layer 13, an intermediate layer 14, and a plurality of redistribution layers 20. The release layer 13 and the intermediate layer 14 are located between the carrier substrate 12 and the redistribution layer 20 in the thickness direction of the wiring board group 10. The release layer 13 is located on the carrier substrate 12. The intermediate layer 14 is located between the release layer 13 and the redistribution layer 20.

[0032] Each component of the wiring board group 10 will be described.

[0033] (Redistribution Layer) The multiple redistribution layers 20 have the same structure as one another. For example, as shown in FIG. 1, the multiple redistribution layers 20 may have the same structure in a planar view. As shown in FIG. 1, the multiple redistribution layers 20 may be regularly arranged in the surface direction of the wiring substrate group 10. For example, the multiple redistribution layers 20 may be regularly arranged in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be directions parallel to the sides of the carrier substrate 12. "Planar view" means viewing an object along a third direction D3.

[0034] In FIG. 1, symbol P1 represents the arrangement pitch of the redistribution layers 20 in the first direction D1, and symbol P2 represents the arrangement pitch of the redistribution layers 20 in the second direction D2.

[0035] 2B is a cross-sectional view showing an example of the redistribution layer 20 and the intermediate layer 14. The redistribution layer 20 includes a third lower surface 201 and a third upper surface 202. The third lower surface 201 faces the carrier substrate 12. The third upper surface 202 is located opposite the third lower surface 201. The redistribution layer 20 includes a plurality of stacked insulating layers 21 and a plurality of conductive layers 22. Each of the plurality of conductive layers 22 is in contact with at least one of the plurality of insulating layers 21.

[0036] In this specification, a "lower surface" such as the third lower surface 201 means a surface facing the carrier substrate 12 in the state of the wiring substrate group 10. An "upper surface" means a surface located opposite the "lower surface" in the thickness direction.

[0037] Some of the multiple conductive layers 22 may be pads 24. The pads 24 may include upper or lower surfaces that are not in contact with an insulating material such as the insulating layer 21. For example, when the pads 24 are located on the third lower surface 201 of the redistribution layer 20, the lower surfaces of the pads 24 are not in contact with an insulating material. For example, when the pads 24 are located on the third upper surface 202 of the redistribution layer 20, the upper surfaces of the pads 24 are not in contact with an insulating material.

[0038] A part of the plurality of conductive layers 22 may be wiring 25. The wiring 25 extends in the first direction D1 or the second direction D2. Both the upper surface and the lower surface of the wiring 25 may be in contact with an insulating material such as the insulating layer 21. The insulating material has insulating properties. The insulating material may be an organic material or an inorganic material.

[0039] The redistribution layer 20 may include multiple stacked wiring layers. In the example shown in FIGS. 2A and 2B , the redistribution layer 20 includes a first wiring layer 20A, a second wiring layer 20B, and a third wiring layer 20C. Each of the multiple wiring layers may include an insulating layer 21 and multiple conductive layers 22. The first wiring layer 20A may form a third lower surface 201 of the redistribution layer 20. The insulating layer 21 of the third wiring layer 20C may form a third upper surface 202 of the redistribution layer 20. The wiring board group 10 may include a conductive layer 22 located on the insulating layer 21 of the third wiring layer 20C and constituting a pad 24.

[0040] Some of the plurality of conductive layers 22 may be through electrodes 26. The through electrodes 26 extend in the third direction D3. For example, the through electrodes 26 are located in openings formed in the insulating layer 21. The through electrodes 26 can electrically connect the conductive layers 22 of two wiring layers adjacent to each other in the third direction D3, for example.

[0041] The redistribution layer 20 has a thickness T1. The thickness T1 is, for example, 8 μm or more, and may be 20 μm or more, or 30 μm or more. The thickness T1 is, for example, 50 μm or less, and may be 45 μm or less. The thickness T1 is the distance in the third direction D3 from the third lower surface 201 to the third upper surface 202. The dimensions of the components of the wiring board group 10, such as the thickness T1, are calculated based on a cross-sectional image of the wiring board group 10 taken by a scanning electron microscope.

[0042] The thickness T2 of each of the multiple wiring layers in the redistribution layer 20 is, for example, 4.0 μm or more, and may be 6.0 μm or more. The thickness T2 of each of the multiple wiring layers in the redistribution layer 20 is, for example, 12.0 μm or less, and may be 10.0 μm or less. The thicknesses T2 of the multiple wiring layers may be the same or different.

[0043] 3 is a cross-sectional view showing an example of the conductive layer 22. The conductive layer 22 may include a seed layer 221 and a plating layer 222. The seed layer 221 is a conductive layer formed by physical film formation such as sputtering. The plating layer 222 is a conductive layer formed on the seed layer 221 by electrolytic plating.

[0044] The seed layer 221 may contain a metal material such as copper, gold, nickel, titanium, chromium, or zinc. The seed layer 221 may also contain a compound of these metal materials. The seed layer 221 may include multiple layers. The plating layer 222 may contain a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc, or an alloy using any of these metals.

[0045] The conductive layer 22 may contain a metal different from the metal constituting the intermediate layer 14. For example, the lower surface of the conductive layer 22 may contain a metal different from the metal constituting the intermediate layer 14 as a main component. In the example shown in FIG. 3 , the lower surface of the conductive layer 22 is formed by a seed layer 221. "The metal constituting the intermediate layer 14" means the metal that is the main component in the intermediate layer 14. "Main component" means the metal or alloy with the largest content.

[0046] For example, when the intermediate layer 14 contains titanium, nickel, molybdenum, tungsten, tantalum, chromium, or an alloy containing these metals as a main component, the conductive layer 22 may contain copper or a copper alloy as a main component.

[0047] The thickness T3 of the conductive layer 22 is, for example, 0.1 μm or more, or may be 0.5 μm or more, or 1.0 μm or more. The thickness T3 of the conductive layer 22 is, for example, 10.0 μm or less, or may be 6.0 μm or less.

[0048] The insulating layer 21 includes an insulating material having insulating properties. The insulating layer 21 may include an organic material or an inorganic material. The insulating layer 21 may include a first insulating layer including an organic material and a second insulating layer including an inorganic material. The organic material is, for example, polyimide or epoxy.

[0049] 2A and 2B , the insulating layer 21 may extend across multiple redistribution layers 20. In other words, in a first redistribution layer 20 and a second redistribution layer 20 that are adjacent to each other in a plan view, the insulating layer 21 of the first redistribution layer 20 and the insulating layer 21 of the second redistribution layer 20 may be connected to each other.

[0050] (Carrier Substrate) The carrier substrate 12 is a member that supports the redistribution layer 20. The carrier substrate 12 may include, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a metal substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO2) substrate, a lithium niobate substrate, or a tantalum niobate substrate. The resin substrate may include an organic material. For example, the resin substrate may include epoxy resin, polyethylene, polypropylene, or the like. The metal substrate includes a metal material. For example, the metal substrate may include copper, stainless steel, or the like. The thickness of the carrier substrate 12 is, for example, 100 μm or more, 200 μm or more, or 500 μm or more. The thickness of the carrier substrate 12 is, for example, 2 mm or less, 1.5 mm or less, or 1 mm or less.

[0051] (Peeling Layer) The peeling layer 13 is a layer that facilitates the operation of peeling the redistribution layer 20 from the carrier substrate 12. The peeling layer 13 includes a first lower surface 131 that faces the carrier substrate 12 and a first upper surface 132 that is located on the opposite side of the first lower surface 131. The peeling layer 13 includes, for example, a resin.

[0052] The release layer 13 is configured so that the adhesion between the release layer 13 and the redistribution layer 20 is reduced by some kind of trigger. The trigger may be irradiation of the release layer 13 with light of a specific wavelength. For example, the release layer 13 may be decomposed by being irradiated with light of a specific wavelength. The trigger may be heating the release layer 13. For example, the release layer 13 may contain a thermoplastic resin.

[0053] The thickness T4 of the release layer 13 is, for example, 0.1 μm or more, or may be 0.2 μm or more, or 0.3 μm or more. The thickness T4 of the release layer 13 is, for example, 1.0 μm or less, or may be 0.8 μm or less, or may be 0.5 μm or less.

[0054] (Intermediate Layer) The intermediate layer 14 is a layer located between the release layer 13 and the redistribution layer 20. The intermediate layer 14 includes a second lower surface 141 facing the first upper surface 132 of the release layer 13, and a second upper surface 142 located on the opposite side of the second lower surface 141. The second upper surface 142 faces the third lower surface 201 of the redistribution layer 20. The intermediate layer 14 extends to overlap the multiple conductive layers 22 in a planar view. For example, the intermediate layer 14 extends to overlap the multiple conductive layers 22 of one first wiring layer 20A in a planar view.

[0055] The intermediate layer 14 may be conductive. For example, the intermediate layer 14 may contain a metal. For example, the intermediate layer 14 may contain, as a main component, a metal different from the metal constituting the lower surface of the conductive layer 22. In this case, the intermediate layer 14 may function as a seed layer 221 for the conductive layer 22. When the intermediate layer 14 is conductive, a seed layer 221 separate from the intermediate layer 14 does not need to be provided. The intermediate layer 14 may include multiple layers as necessary.

[0056] Preferably, the intermediate layer 14 is configured so that the adhesion of the intermediate layer 14 to the release layer 13 is higher than the adhesion of the lower surface of the conductive layer 22 to the release layer 13. That is, preferably, a material that has higher adhesion to the release layer 13 than the material of the conductive layer 22 is used for the intermediate layer 14. By disposing the intermediate layer 14 between the lower surface of the conductive layer 22 and the release layer 13, peeling of the conductive layer 22 is suppressed.

[0057] The intermediate layer 14 may have a light-blocking property provided by a metal. When the intermediate layer 14 has a light-blocking property, the intermediate layer 14 prevents light irradiated onto the release layer 13 from reaching the redistribution layer 20. The light is irradiated onto the release layer 13, for example, in a peeling process in which the redistribution layer 20 is peeled off from the carrier substrate 12. When the intermediate layer 14 has a light-blocking property, for example, the state of the insulating layer 21 of the redistribution layer 20 is prevented from changing due to light irradiation. In the following description, such a function of the intermediate layer 14 is also referred to as a "first function of the intermediate layer 14."

[0058] The intermediate layer 14 may function to suppress the propagation of state changes that occur in the release layer 13 during the peeling process to the redistribution layer 20. If the insulating layer 21 of the redistribution layer 20 is in contact with the release layer 13 over a wide area, expansion, temperature rise, and the like that occur in the release layer 13 during the peeling process are likely to propagate to the insulating layer 21. As a result, it is conceivable that the characteristics of the redistribution layer 20 may be degraded or that the redistribution layer 20 may be difficult to peel from the release layer 13. By positioning the intermediate layer 14 between the release layer 13 and the redistribution layer 20, it is possible to suppress the occurrence of these problems. In the following description, such a function of the intermediate layer 14 is also referred to as the "second function of the intermediate layer 14."

[0059] The intermediate layer 14 may function to facilitate the operation of peeling the redistribution layer 20 from the carrier substrate 12. If the release layer 13 and the insulating layer 21 of the redistribution layer 20 contain the same resin, contact of the insulating layer 21 with the release layer 13 may hinder peeling. By positioning the intermediate layer 14 between the release layer 13 and the redistribution layer 20, it is possible to prevent such problems from occurring. In the following description, this function of the intermediate layer 14 is also referred to as the "third function of the intermediate layer 14."

[0060] The intermediate layer 14 may function to suppress damage to the release layer 13 caused by the process of forming the redistribution layer 20. The process of forming the insulating layer 21 of the redistribution layer 20 includes, for example, a process of applying a solution containing a resin and a solvent. When the solvent comes into contact with the release layer 13, the solvent may be absorbed into the release layer 13, causing the release layer 13 to expand. By positioning the intermediate layer 14 between the release layer 13 and the redistribution layer 20, it is possible to suppress the occurrence of such problems. In the following description, this function of the intermediate layer 14 is also referred to as the "fourth function of the intermediate layer 14."

[0061] In this embodiment, all of the first to fourth functions of the intermediate layer 14 described above may be realized, or some of the first to fourth functions may be realized.

[0062] The thickness T5 of the intermediate layer 14 is, for example, 30 nm or more, or may be 50 nm or more, or 100 nm or more. The thickness T5 of the intermediate layer 14 is, for example, 2.0 μm or less, or may be 1.0 μm or less, or may be 500 nm or less.

[0063] A detailed description will be given of the plurality of conductive layers 22 of the redistribution layer 20. FIG.

[0064] The plurality of conductive layers 22 may include a first conductive layer 22A, a second conductive layer 22B, and a third conductive layer 22C and a fourth conductive layer 22D. The first conductive layer 22A and the second conductive layer 22B are located on the third top surface 202. For example, the first conductive layer 22A and the second conductive layer 22B are pads located on the third top surface 202. The conductive layers located on the third top surface 202, such as the first conductive layer 22A and the second conductive layer 22B, are also referred to as top surface conductive layers.

[0065] The first conductive layer 22A and the second conductive layer 22B may be conductive layers 22 that contribute to signal transmission. For example, the potential of the first conductive layer 22A and the potential of the second conductive layer 22B may change over time. The first conductive layer 22A and the second conductive layer 22B may be conductive layers 22 that contribute to power transmission. For example, the potential of the first conductive layer 22A and the potential of the second conductive layer 22B may be constant regardless of time. The potential of the conductive layer 22 that contributes to power transmission may be a power supply potential or a ground potential.

[0066] The third conductive layer 22C and the fourth conductive layer 22D are located on the second upper surface 142 of the intermediate layer 14. As will be described later, when the intermediate layer 14 is removed, the third conductive layer 22C and the fourth conductive layer 22D may function as pads located on the third lower surface 201 of the redistribution layer 20. Conductive layers located on the third lower surface 201, such as the third conductive layer 22C and the fourth conductive layer 22D, are also referred to as lower surface conductive layers.

[0067] The redistribution layer 20 includes at least two paths that electrically connect the upper surface conductive layer and the lower surface conductive layer. The at least two paths include, for example, a first path RU1 and a second path RU2. In FIG. 4, the first path RU1 and the second path RU2 are indicated by dashed lines.

[0068] The first path RU1 electrically connects the first conductive layer 22A and the third conductive layer 22C. The first path RU1 includes at least one conductive layer 22 located between the first conductive layer 22A and the third conductive layer 22C. For example, the first path RU1 includes a plurality of conductive layers 22 located between the first conductive layer 22A and the third conductive layer 22C in the third direction D3, such as the through electrodes 26 of the second wiring layer 20B and the through electrodes 26 of the third wiring layer 20C.

[0069] The second path RU2 electrically connects the second conductive layer 22B and the fourth conductive layer 22D. The second path RU2 includes at least one conductive layer 22 located between the second conductive layer 22B and the fourth conductive layer 22D. For example, the second path RU2 includes a plurality of conductive layers 22 located between the second conductive layer 22B and the fourth conductive layer 22D in the third direction D3, such as the through electrode 26 of the second wiring layer 20B and the through electrode 26 of the third wiring layer 20C.

[0070] The first path RU1 and the second path RU2 are independent of each other, i.e., one or more conductive layers 22 constituting the first path RU1 are different from one or more conductive layers 22 constituting the second path RU2.

[0071] The redistribution layer 20 further includes a third path RU3 that electrically connects a portion of the first path RU1 and a portion of the second path RU2. For example, the third path RU3 electrically connects a third node N3 of the first path RU1 and a fourth node N4 of the second path RU2. The third node N3 is a branch point between the first path RU1 and the third path RU3. The fourth node N4 is a branch point between the second path RU2 and the third path RU3. In FIG. 4, the third path RU3 is indicated by a dotted line.

[0072] The third path RU3 includes at least one conductive layer 22. For example, the third path RU3 includes one or more wirings 25 extending in the direction D1 or the second direction D2. In the example shown in FIG. 4 , the third path RU3 includes wirings 25 in the second wiring layer 20B and wirings 25 in the third wiring layer 20C.

[0073] As described below, the manufacturing process of the wiring substrate 11 includes an inspection process for inspecting the electrical characteristics of the redistribution layer 20. In the inspection process, for example, the electrical resistance between the first conductive layer 22A and the second conductive layer 22B is measured. In a normal redistribution layer 20, the electrical resistance based on the electrical resistance of a portion of the first path RU1, the electrical resistance of a portion of the second path RU2, and the electrical resistance of the third path RU3 is measured. That is, proper conduction between the first conductive layer 22A and the second conductive layer 22B is confirmed. Meanwhile, the first path RU1 and the second path RU2 each reach the conductive layer 22 of the first wiring layer 20A. If multiple conductive layers 22 of the first wiring layer 20A are electrically short-circuited by the intermediate layer 14, the effect of the short circuit will appear in the measurement result of the electrical resistance. For example, it is conceivable that the measured electrical resistance will be smaller than the electrical resistance based on the electrical resistance of a portion of the first path RU1, the electrical resistance of a portion of the second path RU2, and the electrical resistance of the third path RU3.

[0074] In consideration of these issues, in the present embodiment, the portion of the intermediate layer 14 supporting the third conductive layer 22C is electrically insulated from the portion of the intermediate layer 14 supporting the fourth conductive layer 22D. For example, as shown in FIG. 4 , the intermediate layer 14 may include a first opening 145. The first opening 145 is a groove that penetrates the intermediate layer 14. The first opening 145 separates the intermediate layer 14 supporting the third conductive layer 22C from the other intermediate layers 14. The intermediate layer 14 supporting the third conductive layer 22C is electrically insulated from the other intermediate layers 14 by the first opening 145. This electrical insulation prevents the intermediate layer 14 from affecting the electrical resistance measurement results.

[0075] FIG. 5 is a plan view showing an example of the first wiring layer 20A and the intermediate layer 14. The first opening 145 may surround a portion of the intermediate layer 14 supporting the third conductive layer 22C in a plan view. The first opening 145 can physically separate the portion of the intermediate layer 14 supporting the third conductive layer 22C from the other portions of the intermediate layer 14. A portion of the intermediate layer 14 that is physically separated from the surrounding intermediate layer 14 is also referred to as an island portion 143. One island portion 143 supporting the third conductive layer 22C is also referred to as a first island portion 143. The first island portion 143 surrounds the third conductive layer 22C in a plan view. The island portion 143 supporting the third conductive layer 22C does not overlap the fourth conductive layer 22D in a plan view. These configurations can prevent the third conductive layer 22C from being electrically short-circuited to the fourth conductive layer 22D by the intermediate layer 14.

[0076] The symbol K1 represents the width of the first opening 145. The width K1 of the first opening 145 is measured in a direction perpendicular to the direction in which the first opening 145 extends. For example, the width K1 of the portion of the first opening 145 extending in the first direction D1 is measured in the second direction D2. The width K1 is, for example, 1.0 μm or more, may be 3.0 μm or more, or may be 5.0 μm or more. The width K1 is, for example, 500 μm or less, may be 300 μm or less, 100 μm or less, 50 μm or less, or may be 10 μm or less.

[0077] The symbol K3 represents the distance from the outer edge of the third conductive layer 22C to the outer edge of the first island portion 143 in a planar view. The distance K3 is, for example, 0 μm or more, and may be 0.1 μm or more, 3.0 μm or more, or 5.0 μm or more. The distance K3 is, for example, 500 μm or less, 300 μm or less, 100 μm or less, 50 μm or less, or 10 μm or less. The distance K3 is the average of the maximum and minimum values ​​of the distance from the outer edge of the third conductive layer 22C to the outer edge of the first island portion 143 in a planar view.

[0078] 5 , the intermediate layer 14 may include a first opening 145 that surrounds the portion of the intermediate layer 14 that supports the fourth conductive layer 22D in a plan view. That is, the portion of the intermediate layer 14 that supports the fourth conductive layer 22D may also be an island portion 143. The island portion 143 that supports the fourth conductive layer 22D surrounds the fourth conductive layer 22D in a plan view. The island portion 143 that supports the fourth conductive layer 22D is also referred to as a second island portion 143. The second island portion 143 is electrically insulated from the first island portion 143 that supports the third conductive layer 22C.

[0079] 5, the intermediate layer 14 may include a sea portion 144 that surrounds at least one island portion 143 in a plan view. In the example shown in FIG. 5, the sea portion 144 surrounds the first island portion 143 and the second island portion 143 in a plan view. Although not shown, the sea portion 144 may surround three or more island portions 143. The sea portion 144 may extend to the outer edge of the redistribution layer 20 in a plan view.

[0080] Openings such as the first opening 145 may have the effect of suppressing peeling of the intermediate layer 14 from the release layer 13. The release layer 13 may contain components with low boiling points, such as moisture and low-molecular-weight components. When the temperature of the release layer 13 increases due to the redistribution layer formation process, gas may be generated inside the release layer 13. Depending on the material, light or heat from the storage environment may cause a change in the molecular structure, resulting in the generation of gas. If this generated gas remains, for example, at the interface between the release layer 13 and the intermediate layer 14, there is a concern that the intermediate layer 14 may peel off from the release layer 13 at an unintended timing.

[0081] Gas generated inside the release layer 13 is discharged through openings such as the first opening 145. The openings can prevent the intermediate layer 14 from peeling off from the release layer 13 due to the gas.

[0082] 2A, 2B, and 4, the intermediate layer 14 may include a second opening 146 located between the first wiring layers 20A of two adjacent redistribution layers 20 in a plan view. The second opening 146 is a groove that penetrates the intermediate layer 14. The second opening 146 may extend along the boundary between the first wiring layers 20A of the two adjacent redistribution layers 20 in a plan view. For example, the second opening 146 may include a portion extending along the first direction D1 and a portion extending along the second direction D2.

[0083] The symbol K2 represents the width of the second opening 146. The width K2 of the second opening 146 is measured in a direction perpendicular to the direction in which the second opening 146 extends. The width K2 of the second opening 146 is, for example, 5 μm or more, and may be 10 μm or more. Gas generated inside the release layer 13 is properly discharged through the second opening 146. The width K2 of the second opening 146 is, for example, 500 μm or less, and may be 400 μm or less. The width of the openings in the intermediate layer 14, such as the second opening 146, is determined on the second lower surface 141.

[0084] The width K2 of the second opening 146 may be determined relative to the arrangement pitches P1, P2 of the redistribution layer 20. The ratios K2 / P1 and K2 / P2 of the width K2 to the arrangement pitches P1, P2 are, for example, 0.0010 or more, 0.0030 or more, or 0.010 or more. K2 / P1 and K2 / P2 are, for example, 0.10 or less, 0.050 or less, or 0.020 or less.

[0085] (Method for Manufacturing the Wiring Board Group) A method for manufacturing the wiring board group 10 will be described.

[0086] As shown in Fig. 6, a carrier substrate 12 is prepared. Subsequently, as shown in Fig. 6, a release layer 13 is formed on the carrier substrate 12. The process of forming the release layer 13 includes, for example, a coating process of coating a solution containing a resin and a solvent, and a drying process of evaporating the solvent after the coating process. Examples of the solvent include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying process includes, for example, a step of heating the carrier substrate 12.

[0087] 7, the intermediate layer 14 is formed on the first upper surface 132 of the release layer 13. For example, the intermediate layer 14 is formed by a sputtering process. Then, as shown in FIG. 7, the seed layer 221 is formed on the second upper surface 142 of the intermediate layer 14. For example, the seed layer 221 is formed by a sputtering process.

[0088] 8, a first resist layer 71 is formed on the seed layer 221. The first resist layer 71 has an opening 711 that penetrates the first resist layer 71 in the thickness direction. The opening 711 has a shape that corresponds to the plating layer 222 in a plan view.

[0089] Next, a plating step is performed. In the plating step, as shown in Fig. 9, a plating layer 222 is formed in the opening 711 by electrolytic plating. Next, as shown in Fig. 10, a step of removing the first resist layer 71 is performed. Next, as shown in Fig. 10, a step of removing the seed layer 221 that overlapped the first resist layer 71 is performed. In this manner, the conductive layer 22 including the seed layer 221 and the plating layer 222 is formed.

[0090] 11, a second resist layer 72 is formed on the second upper surface 142 of the intermediate layer 14. The second resist layer 72 has an opening 721 that penetrates the second resist layer 72 in the thickness direction.

[0091] 12 , a step of etching the intermediate layer 14 is performed. For example, the intermediate layer 14 located in the opening 721 is removed by, for example, dry etching or wet etching. By etching the intermediate layer 14, a first opening 145 and a second opening 146 are formed in the intermediate layer 14.

[0092] Next, a step of removing the second resist layer 72 is performed. Figure 13 is a cross-sectional view showing the release layer 13, the intermediate layer 14, and the conductive layer 22 after the second resist layer 72 has been removed. The first upper surface 132 of the release layer 13 is exposed in the first opening 145 and the second opening 146 of the intermediate layer 14.

[0093] 14 , a step of forming an insulating layer 21 is performed. The insulating layer 21 is formed so as to cover the intermediate layer 14 and the conductive layer 22. In this manner, a first wiring layer 20A including the insulating layer 21 and the conductive layer 22 is formed. A portion of the insulating layer 21 may contact the first upper surface 132 of the release layer 13 in the first opening 145 and the second opening 146.

[0094] The process of forming the insulating layer 21 includes, for example, a coating process of coating a solution containing a resin and a solvent, and a drying process of evaporating the solvent after the coating process. Examples of the solvent include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying process includes, for example, a step of heating the carrier substrate 12.

[0095] According to this embodiment, by forming the intermediate layer 14 on the release layer 13, it is possible to prevent the solvent from coming into contact with the release layer 13 in the process of forming the insulating layer 21. Therefore, the release layer 13 is prevented from swelling due to the solvent being absorbed into the release layer 13.

[0096] According to the present embodiment, openings such as first opening 145 and second opening 146 are formed in intermediate layer 14, so that gas generated inside release layer 13 can be easily discharged through the openings. This prevents intermediate layer 14 from peeling off from release layer 13 due to gas during the manufacturing process of wiring board group 10. Suppressing peeling can improve the yield of the manufacturing process of wiring board group 10. Gas is generated inside release layer 13, for example, during a process in which components of wiring board group 10 are heated. Processes in which the components are heated include, for example, a drying process in which the solvent in insulating layer 21 is evaporated, and a baking process in which high-temperature heating is performed.

[0097] After the formation of the first wiring layer 20A, a process of forming the second wiring layer 20B and the third wiring layer 20C may be performed. Also, a process of forming the conductive layer 22 constituting the pads 24 and the like on the third wiring layer 20C may be performed. In this manner, the wiring board group 10 shown in FIG. 2 is manufactured.

[0098] (Method for Manufacturing Wiring Board) A method for manufacturing the wiring board 11 will be described.

[0099] A wiring board group 10 is prepared. Subsequently, as shown in Fig. 15, a dividing process is carried out to divide the wiring board group 10. A plurality of wiring boards 11 are manufactured by the dividing process. The wiring board 11 includes a carrier substrate 12, a release layer 13 located on the carrier substrate 12, an intermediate layer 14 located on the release layer 13, and a rewiring layer 20 located on the intermediate layer 14.

[0100] In the dividing step, the insulating layer 21, the release layer 13, and the carrier substrate 12 of the redistribution layer 20 may be cut along the boundary between two adjacent redistribution layers 20 in a plan view. In Fig. 15, the two-dot chain line marked with symbol CL1 indicates the cutting position in the dividing step. The cutting position CL1 may be located at the second opening 146 of the intermediate layer 14. In this case, the intermediate layer 14 is not cut.

[0101] Although not shown, a semiconductor element may be mounted on each of the multiple redistribution layers 20 of the wiring substrate group 10 before the dividing step. The semiconductor element is mounted, for example, on a pad located on the third upper surface 202 of each redistribution layer 20. Also, a resin mold covering the semiconductor element may be formed before the dividing step. That is, the dividing step shown in FIG. 15 may be performed in a state where the semiconductor element, the resin mold, and the like are provided on each of the multiple redistribution layers 20. In this case, the inspection step described below may be performed before the dividing step.

[0102] Subsequently, an inspection step may be performed to inspect the wiring board 11. Fig. 16 is a cross-sectional view showing an example of the inspection step. Note that the inspection step may be performed on the wiring board group 10 before the dividing step is performed.

[0103] In the inspection process, a measuring device 90 is used. The measuring device 90 may include a first probe 91, a second probe 92, a measuring unit 95, and a stage 96. The stage 96 supports the wiring substrate 11. The first probe 91 is in contact with the first conductive layer 22A. The position where the first probe 91 is in contact with the first conductive layer 22A is also referred to as a first node N1. The second probe 92 is in contact with the second conductive layer 22B. The position where the second probe 92 is in contact with the second conductive layer 22B is also referred to as a second node N2. The measuring unit 95 measures the electrical resistance between the first probe 91 and the second probe 92. In the example shown in FIG. 16 , the electrical resistance between the first conductive layer 22A, which the first probe 91 contacts, and the second conductive layer 22B, which the second probe 92 contacts, is measured.

[0104] 17 is a diagram showing an example of an equivalent circuit of the wiring board 11. A path between the first node N1 and the third node N3, which is a part of the first path RU1, has an electrical resistance R1. A path between the second node N2 and the fourth node N4, which is a part of the second path RU2, has an electrical resistance R2. A third path RU3 located between the third node N3 and the fourth node N4 has an electrical resistance R3.

[0105] When the redistribution layer 20 is normal, the electrical resistance measured by the measuring device 90 is the sum of R1, R2, and R3. When an electrical short circuit occurs due to the intermediate layer 14, the electrical resistance measured by the measuring device 90 is smaller than the sum of R1, R2, and R3. When an electrical disconnection occurs in the path between the first node N1 and the third node N3, the path between the second node N2 and the fourth node N4, or the third path RU3, the electrical resistance measured by the measuring device 90 is larger than the sum of R1, R2, and R3.

[0106] The inspection step may include a determination step of determining whether the redistribution layer 20 is normal. For example, the determination step may determine that the redistribution layer 20 is normal when the electrical resistance of the redistribution layer 20 is 0.7 to 1.3 times the sum of R1, R2, and R3.

[0107] In the present embodiment, the intermediate layer 14 includes an island portion 143 that surrounds the third conductive layer 22C in a plan view. The island portion 143 can prevent the third conductive layer 22C from shorting to the surrounding conductive layer 22. Therefore, in the present embodiment, the electrical resistance of the redistribution layer 20 can be appropriately inspected.

[0108] 18 is a cross-sectional view showing an example of an inspection process. The measuring device 90 may include a probe unit 93. The probe unit 93 includes multiple probes, such as a first probe 91 and a second probe 92. When the probe unit 93 moves, the multiple probes of the probe unit 93 also move simultaneously. The multiple probes of the probe unit 93 can simultaneously contact multiple conductive layers located on the third upper surface 202 of the redistribution layer 20, such as the first conductive layer 22A and the second conductive layer 22B. By using the probe unit 93, the electrical resistance of multiple paths can be efficiently measured.

[0109] 19 , a trimming step may be performed to remove the outer peripheral portion of wiring substrate 11. In the trimming step, the outer peripheral portion of wiring substrate 11 may be separated by cutting from the portion of wiring substrate 11 located inside the outer peripheral portion. The trimming step does not necessarily have to be performed.

[0110] 19 , the two-dot chain line marked with the symbol CL2 indicates the cutting position in the trimming process. The cutting position CL2 may be located outside the conductive layer 22 and overlap the release layer 13 and the intermediate layer 14. In this case, the insulating layer 21 of the redistribution layer 20, the release layer 13, and the intermediate layer 14 are cut. As shown in FIG. 19 , the trimming process may be performed without dividing the carrier substrate 12.

[0111] 20 and 21 , after the trimming step, a first bonding step may be performed in which the wiring substrate 11 separated from the outer periphery is bonded to a first member 81. The first member 81 may include a substrate 811 and a plurality of terminals 812 located on the substrate 811. The first member 81 may include an adhesive layer 813 covering the plurality of terminals. The adhesive layer 813 may be provided on the wiring substrate 11. In the first bonding step, as shown in FIG. 21 , the conductive layer 22 located on the third upper surface 202 of the redistribution layer 20 and constituting the pad 24 may be electrically connected to the terminal 812 of the first member 81.

[0112] Next, as shown in FIGS. 21 and 22 , a peeling process may be performed to peel the redistribution layer 20 from the carrier substrate 12. The peeling process may include an irradiation process of irradiating the release layer 13 with light L, as shown in FIG. 21 . In the irradiation process, the light L may reach the release layer 13 after transmitting through the carrier substrate 12. The release layer 13 may be decomposed by heat generated by the irradiation of the light L. The decomposition reduces the adhesion between the carrier substrate 12 and the intermediate layer 14. As a result, as shown in FIG. 22 , the carrier substrate 12 is separated from the intermediate layer 14 and the redistribution layer 20. Thereafter, if residues of the release layer 13 are present on the intermediate layer 14, a process of removing the residues may be performed.

[0113] The peeling process may be performed by a method other than light irradiation. For example, the redistribution layer 20 may be mechanically peeled from the carrier substrate 12. For example, the redistribution layer 20 may be peeled from the carrier substrate 12 by heating the redistribution layer 20.

[0114] 23 , a step of removing the intermediate layer 14 may be performed. For example, the intermediate layer 14 may be removed by etching. By removing the intermediate layer 14, the third lower surface 201 of the redistribution layer 20 appears. In this case, the first wiring layer 20A constituting the third lower surface 201 may include a plurality of conductive layers 22 constituting the pads 24.

[0115] 24 , a second bonding step may be performed in which the conductive layer 22 of the first wiring layer 20A of the wiring board 11 is bonded to the second member 82. The second member 82 may include a substrate 821 and a plurality of terminals 822 located on the substrate 821. An adhesive layer 823 may be provided between the substrate 821 of the second member 82 and the first wiring layer 20A of the wiring board 11.

[0116] The second member 82 may be a semiconductor element. The semiconductor element includes a transistor formed of a semiconductor such as silicon. The semiconductor element is, for example, a CPU, a GPU, an FPGA, a sensor, a memory, etc. The semiconductor element may be a chiplet in which semiconductor elements such as a CPU, a GPU, an FPGA, a sensor, a memory, etc. are divided according to function.

[0117] According to this embodiment, the intermediate layer 14 can prevent the light L from reaching the redistribution layer 20 in the peeling step. Therefore, for example, it is possible to prevent the state of the insulating layer 21 of the redistribution layer 20 from changing due to light irradiation.

[0118] According to this embodiment, the intermediate layer 14 can prevent a change in state that occurs in the peeling layer 13 due to light irradiation or the like in the peeling process from propagating to the redistribution layer 20. Therefore, for example, a change in state of the insulating layer 21 of the redistribution layer 20 can be prevented.

[0119] According to this embodiment, the intermediate layer 14 can prevent the insulating layer 21 of the redistribution layer 20 from coming into close contact with the release layer 13. Therefore, the redistribution layer 20 can be easily peeled off from the release layer 13 in the peeling step.

[0120] The above-described embodiment can be modified in various ways. Modified examples will be described below with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. If it is clear that the effects obtained in the above-described embodiment can also be obtained in the modified examples, the description thereof may be omitted.

[0121] 25 is a cross-sectional view showing a redistribution layer 20 according to a first modification. The insulating layer 21 of the first wiring layer 20A located on the intermediate layer 14 may include a portion located in the first opening 145 of the intermediate layer 14. For example, as described in the process shown in FIG. 14 above, a portion of the insulating layer 21 may contact the first upper surface of the release layer 13 in the first opening 145.

[0122] 25 , the insulating layer 21 of the first wiring layer 20A located on the intermediate layer 14 may include a portion 211 located in the second opening 146 of the intermediate layer 14. For example, as described in the process shown in FIG. 14 above, a portion of the insulating layer 21 may contact the first upper surface of the release layer 13 in the second opening 146.

[0123] 26 is a cross-sectional view showing a step of removing the intermediate layer 14 after peeling the redistribution layer 20 from the carrier substrate 12 in the first modified example. A portion 211 of the insulating layer 21 located in the first opening 145 of the intermediate layer 14 protrudes from the third lower surface 201 of the redistribution layer 20. The portion 211 is also referred to as a protrusion.

[0124] The protrusions 211 have a height T6. The height T6 of the protrusions 211 may correspond to the thickness T5 of the intermediate layer 14. The height T6 of the protrusions 211 is, for example, 30 nm or more, 50 nm or more, or 100 nm or more. The height T6 of the protrusions 211 is, for example, 2.0 μm or less, 1.0 μm or less, or 500 nm or less.

[0125] The protrusion 211 has a width K4. The width K4 of the protrusion 211 is measured in a direction perpendicular to the direction in which the protrusion 211 extends in a plan view. The width K4 is, for example, 1.0 μm or more, may be 3.0 μm or more, or may be 5.0 μm or more. The width K4 is, for example, 500 μm or less, may be 300 μm or less, 100 μm or less, 50 μm or less, or may be 10 μm or less.

[0126] 27 is a plan view showing the third lower surface 201 of the redistribution layer 20. The protrusion 211 may extend so as to surround the conductive layer 22 constituting the pad. In the example shown in FIG. 27 , the insulating layer 21 includes a protrusion 211 surrounding the third conductive layer 22C, a protrusion 211 surrounding the conductive layer 22 adjacent to the third conductive layer 22C in plan view, and a protrusion 211 surrounding the fourth conductive layer 22D.

[0127] As shown in FIG. 27, the third conductive layer 22C, the conductive layer 22 adjacent to the third conductive layer 22C in a plan view, and the protrusion 211 surrounding them may have a circular outline.

[0128] 28 is a cross-sectional view of the redistribution layer 20 taken along line XXVIII-XXVIII in FIG. 27. The conductive layer 22 located on the third lower surface 201, such as the third conductive layer 22C, may be used as a pad. For example, as shown in FIG. 28, solder 83 may be piled on the conductive layer 22 located on the third lower surface 201.

[0129] In this modification, the conductive layers 22 located on the third lower surface 201, such as the third conductive layer 22C, are surrounded by the protruding portion 211 in a plan view. The protruding portion 211 can prevent the solder 83 from spreading along the third lower surface 201. As a result, the solder 83 located on two adjacent conductive layers 22 is prevented from being connected to each other.

[0130] 29 is a cross-sectional view showing a redistribution layer 20 according to a second modification. The third path RU3 electrically connecting the third node N3 of the first path RU1 and the fourth node N4 of the second path RU2 may be formed by a conductive layer 22 included in one wiring layer. In the example shown in FIG. 29, the third path RU3 is formed by the conductive layer 22 of the second wiring layer 20B.

[0131] The conductive layer 22 constituting the third path RU3 may extend over the entire area in the surface direction of the redistribution layer 20. Such a layer is also called a solid layer. In this case, the conductive layer 22 constituting the third path RU3 may contribute to the transmission of power. That is, the potential of the conductive layer 22 constituting the third path RU3 may be the power supply potential or the ground potential.

[0132] 29 , the conductive layer 22 may include pads 24 electrically connected to the conductive layer 22 constituting the third path RU3, in addition to the first conductive layer 22A and the second conductive layer 22B. These pads 24 are connected to the conductive layer 22 constituting the third path RU3 by, for example, through electrodes 26.

[0133] 30 is a cross-sectional view showing a wiring board group 10 according to a third modification. The redistribution layer 20 may include two pads 24 electrically connected to the wiring 25 of the second wiring layer 20B or the third wiring layer 20C by a through electrode 26. The two pads 24 do not have to be electrically connected to the conductive layer 22 of the first wiring layer 20A located on the intermediate layer 14.

[0134] (Fourth Modification) In the above-described embodiment, an example has been described in which the conductive layer 22 is formed on the intermediate layer 14, and then openings such as the first opening 145 and the second opening 146 are formed in the intermediate layer 14. In this modification, an example will be described in which the conductive layer 22 is formed on the intermediate layer 14, and then openings such as the first opening 145 and the second opening 146 are formed in the intermediate layer 14.

[0135] Similar to the above-described embodiment shown in Figures 6 and 7, a release layer 13 and an intermediate layer 14 are formed on a carrier substrate 12. Next, openings such as a first opening 145 and a second opening 146 are formed in the intermediate layer 14. For example, as shown in Figure 31, the above-described second resist layer 72 is formed on a second upper surface 142 of the intermediate layer 14. Next, as shown in Figure 32, a step of etching the intermediate layer 14 is performed. For example, the intermediate layer 14 located in the opening 721 is removed by dry etching. By etching the intermediate layer 14, the first opening 145 and the second opening 146 are formed in the intermediate layer 14.

[0136] Subsequently, a step of forming a seed layer on the second upper surface 142 of the intermediate layer 14 is performed. The seed layer may also be formed in openings such as the first opening 145 and the second opening 146.

[0137] Next, the above-mentioned first resist layer is formed on the seed layer. Next, a plating layer is formed in the openings of the first resist layer by electrolytic plating. Next, a step of removing the first resist layer is performed. Next, a step of removing the seed layer that was overlying the first resist layer is performed. In this manner, a conductive layer including the seed layer and the plating layer is formed.

[0138] (Fifth Modification) In the above-described embodiment, an example has been shown in which the peeling step of peeling the redistribution layer 20 from the carrier substrate 12 includes an irradiation step of irradiating the peeling layer 13 with light. That is, an example has been shown in which the redistribution layer 20 is peeled from the carrier substrate 12 by utilizing the fact that the peeling layer 13 is decomposed by light irradiation. In this modification, an example will be described in which the redistribution layer 20 is mechanically peeled from the carrier substrate 12.

[0139] Similar to the above-described embodiment, a wiring substrate group 10 is manufactured. Subsequently, as shown in FIG. 33 , a step of cutting a portion of the redistribution layer 20 may be performed. The two-dot chain line marked with the symbol CL3 indicates the cutting position of the redistribution layer 20. The cutting position CL3 is a certain distance from the outer edge of the redistribution layer 20. By cutting, unnecessary portions of the redistribution layer 20 that will not be used as a product are removed. As shown in FIG. 33 , the carrier substrate 12 may also be cut along with the redistribution layer 20. Although not shown, the carrier substrate 12 does not have to be cut.

[0140] 34 , a peeling process is performed to peel the redistribution layer 20 from the carrier substrate 12. In the peeling process, the redistribution layer 20 may be mechanically peeled from the carrier substrate 12. The peeling layer 13 may remain on the carrier substrate 12. The redistribution layer 20 shown in FIG. 34 includes a plurality of redistribution layer 20 products, and is also referred to as a redistribution layer group.

[0141] Thereafter, if any residue of the release layer 13 is present on the intermediate layer 14, a step of removing the residue may be carried out. For example, the residue of the release layer 13 is removed by dry etching.

[0142] 35 , a step of removing the intermediate layer 14 may be performed. For example, the intermediate layer 14 may be removed by etching. By removing the intermediate layer 14, the third lower surface 201 of the redistribution layer group appears. As in the first modified example described above, the insulating layer of the first wiring layer 20A may include a protrusion that was located in the first opening of the intermediate layer 14.

[0143] 36, a dividing step is carried out to divide the rewiring layer group, and a plurality of rewiring layers 20 are manufactured by the dividing step.

[0144] Although not shown, a semiconductor element may be mounted on each of the multiple redistribution layers 20 before the dividing step. The semiconductor element may be mounted on a pad located on the third upper surface 202 of each redistribution layer 20, or on a pad located on the third lower surface 201. Furthermore, a resin mold covering the semiconductor element may be formed before the dividing step. That is, the dividing step shown in FIG. 36 may be performed in a state in which a semiconductor element, a resin mold, and the like are provided on each of the multiple redistribution layers 20. In this case, the above-mentioned inspection step may be performed before the dividing step.

[0145] Although not shown, the steps shown in FIGS. 34 to 36 may be performed in a state where a substrate is connected to the third upper surface 202 of the redistribution layer group.

[0146] 37 is a cross-sectional view showing a wiring board group 10 according to this modification. Fig. 38 is a cross-sectional view showing a redistribution layer 20 according to this modification. The plurality of conductive layers 22 of the redistribution layer 20 may include at least one dummy conductive layer 22E located on the sea portion 144 of the intermediate layer 14.

[0147] The dummy conductive layer 22E is a conductive layer 22 that does not contribute to the transmission of signals and power. The dummy conductive layer 22E is not connected to other conductive layers 22. For example, as shown in Figures 37 and 38, the entire top surface and side surfaces of the dummy conductive layer 22E are covered with the insulating layer 21. For example, no through electrode 26 is connected to the dummy conductive layer 22E. A conductive layer 22 that is covered with the insulating layer 21 and to which no through electrode 26 is connected may be referred to as a dummy conductive layer.

[0148] 39 is a plan view showing the first wiring layer 20A and the intermediate layer 14 according to this modification. The redistribution layer 20 may include a plurality of dummy conductive layers 22E located on the sea portion 144.

[0149] The dummy conductive layer 22E is disposed in a region where the distribution density of the conductive layer 22 that contributes to the transmission of signals and power is low in a plan view. By disposing the dummy conductive layer 22E, variations in the distribution density of the conductive layer 22 in a plan view are suppressed.

[0150] When the distribution density of the conductive layer 22 varies in plan view, it is conceivable that the thickness of the plating layer 222 will vary. According to this modification, the variation in the thickness of the plating layer 222 is suppressed.

[0151] (Seventh Modification) Fig. 40 is a cross-sectional view showing a wiring board group 10 according to this modification. Fig. 41 is a cross-sectional view showing a rewiring layer 20 according to this modification.

[0152] The plurality of conductive layers 22 may include a first conductive layer 22A, a second conductive layer 22B, and a third conductive layer 22C. The first conductive layer 22A and the second conductive layer 22B are located on the third upper surface 202. The third conductive layer 22C is located on the second upper surface 142 of the intermediate layer 14.

[0153] The redistribution layer 20 includes a first path RU1 and a second path RU2. The first path RU1 electrically connects the first conductive layer 22A and the third conductive layer 22C. The second path RU2 electrically connects the second conductive layer 22B and the third conductive layer 22C. The first path RU1 and the second path RU2 are independent of each other.

[0154] The redistribution layer 20 further includes a third path RU3 that electrically connects the first path RU1 and the second path RU2. In this modification, a third conductive layer 22C forms the third path RU3.

[0155] 42 is a plan view showing an example of the first wiring layer 20A and the intermediate layer 14. The third conductive layer 22C is supported by one first island portion 143. In other words, the intermediate layer 14 includes one first island portion 143 that surrounds the third conductive layer 22C in a plan view. The first island portion 143 can prevent the third conductive layer 22C from being electrically short-circuited to the surrounding conductive layer 22. The conductive layer 22 around the third conductive layer 22C is, for example, a dummy conductive layer 22E. The dummy conductive layer 22E may be located on a sea portion 144.

[0156] If the third conductive layer 22C is electrically connected to the dummy conductive layer 22E by the intermediate layer 14, the dummy conductive layer 22E and the portion of the conductive layer 22 connecting the dummy conductive layer 22E and the third conductive layer 22C are stubs. A stub is an electrical path branching off from the first path RU1, the second path RU2, and the third path RU3 located between the first conductive layer 22A and the second conductive layer 22B. Stubs can cause signal disturbances, noise, and the like. For example, if a wiring is located near a stub, electromagnetic interference may occur between the stub and the wiring.

[0157] According to this modification, the third conductive layer 22C is insulated from the surrounding conductive layers 22 by the first island portion 143. This prevents the formation of stubs in the third conductive layer 22C. Since problems such as signal disturbance and noise are suppressed, this modification also allows the electrical resistance of the redistribution layer 20 to be properly inspected.

[0158] (Eighth Modification) Fig. 43 is a cross-sectional view showing a wiring board group 10 according to this modification. Fig. 44 is a cross-sectional view showing a rewiring layer 20 according to this modification.

[0159] The plurality of conductive layers 22 may include a first conductive layer 22A, a second conductive layer 22B, and a third conductive layer 22C and a fourth conductive layer 22D. The first conductive layer 22A and the second conductive layer 22B are located on the third upper surface 202. The third conductive layer 22C and the fourth conductive layer 22D are located on the second upper surface 142 of the intermediate layer 14.

[0160] The redistribution layer 20 includes a first path RU1 and a second path RU2. The first path RU1 electrically connects the first conductive layer 22A and the third conductive layer 22C. The second path RU2 electrically connects the second conductive layer 22B and the fourth conductive layer 22D. The first path RU1 and the second path RU2 are independent of each other.

[0161] FIG. 45 is a plan view showing an example of the first wiring layer 20A and the intermediate layer 14. The third conductive layer 22C is supported by one first island portion 143. In other words, the intermediate layer 14 includes one first island portion 143 that surrounds the third conductive layer 22C in a planar view. The one first island portion 143 that surrounds the third conductive layer 22C does not overlap the fourth conductive layer 22D in a planar view. The first island portion 143 can prevent the third conductive layer 22C from being electrically short-circuited to the surrounding conductive layer 22. As a result, the third conductive layer 22C is prevented from being electrically connected to the fourth conductive layer 22D. In other words, the first path RU1 and the second path RU2 are prevented from being electrically connected to each other.

[0162] The fourth conductive layer 22D may be supported by one second island portion 143. In other words, the intermediate layer 14 may include one second island portion 143 that surrounds the fourth conductive layer 22D in a planar view. The one second island portion 143 that surrounds the fourth conductive layer 22D does not overlap the third conductive layer 22C in a planar view. The second island portion 143 can prevent the fourth conductive layer 22D from being electrically short-circuited to the surrounding conductive layer 22.

[0163] The conductive layer 22 around the third conductive layer 22C and the conductive layer 22 around the fourth conductive layer 22D are, for example, dummy conductive layers 22E. The dummy conductive layers 22E may be located on the sea portion 144.

[0164] FIG. 46 is a cross-sectional view showing an example of an inspection step of the redistribution layer 20 in this modification.

[0165] The measuring device 90 may include a first probe 91, a measuring unit 95, a stage 96, and an inspection electrode 97. The stage 96 supports the wiring substrate 11. The inspection electrode 97 is located between the stage 96 and the lower surface of the carrier substrate 12. The position where the inspection electrode 97 contacts the lower surface of the carrier substrate 12 is also referred to as a seventh node N7. The lower surface of the carrier substrate 12 is located opposite the upper surface of the carrier substrate 12. The upper surface of the carrier substrate 12 faces the first lower surface of the release layer 13.

[0166] The first probe 91 is in contact with the first conductive layer 22A. The position where the first probe 91 is in contact with the first conductive layer 22A is also referred to as a first node N1.

[0167] The position where the third conductive layer 22C contacts the first island portion 143 is also referred to as a fifth node N5. The position where the fourth conductive layer 22D contacts the second island portion 143 is also referred to as a sixth node N6.

[0168] The measuring unit 95 measures the capacitance between the first probe 91 and the test electrode 97. In the example shown in Fig. 46, the capacitance is measured between the first conductive layer 22A that the first probe 91 contacts and the carrier substrate 12 that the test electrode 97 contacts.

[0169] 47 is a diagram showing an example of an equivalent circuit of the wiring board 11. The path between the first node N1 and the fifth node N5, which constitutes the first path RU1, has an electrical resistance R1. The path between the fifth node N5 and the seventh node N7 has a capacitance C1. The path between the second node N2 and the sixth node N6, which constitutes the second path RU2, has an electrical resistance R2. The path between the sixth node N6 and the seventh node N7 has a capacitance C2.

[0170] When the redistribution layer 20 is normal, the capacitance measured by the measuring device 90 is C1. When an electrical short circuit due to the intermediate layer 14 occurs between the first path RU1 and the second path RU2, the capacitance measured by the measuring device 90 is the sum of C1 and C2. When an electrical disconnection occurs in the first path RU1, the capacitance measured by the measuring device 90 is smaller than C1.

[0171] The inspection step may include a determination step of determining whether or not the redistribution layer 20 is normal. For example, the determination step may determine that the redistribution layer 20 is normal when the capacitance of the redistribution layer 20 is 0.7 times or more and 1.3 times or less than C1.

[0172] In this embodiment, the intermediate layer 14 includes a first island portion 143 that surrounds the third conductive layer 22C in a plan view. The first island portion 143 can prevent the third conductive layer 22C from shorting to the surrounding conductive layers 22. Therefore, this embodiment can appropriately test the capacitance of the redistribution layer 20.

[0173] The capacitance C is expressed by the following formula: C=ε ｒ ×ε ０ × (S / d) ε ｒ is the relative permittivity of the material between the electrodes, and ε ０ is the dielectric constant of a vacuum. S is the area of ​​the electrode, and d is the distance between the electrodes. The larger the area S of the electrode, the larger the capacitance C. The larger the capacitance C, the smaller the influence of noise contained in the measured value of capacitance C, and therefore the higher the measurement accuracy. Therefore, in order to improve the measurement accuracy, it is preferable that the area of ​​the island portion 143 is large.

[0174] The redistribution layer 20 may include a TEG for testing. TEG stands for Test Element Group. For example, the redistribution layer 20 may include a TEG located at each of the four corners in a plan view. The TEG may be, for example, a pad located on the third lower surface 201 and configured by an island portion 143 of the intermediate layer 14. The larger the area of ​​the TEG pad, the higher the accuracy of measuring the capacitance C. The area of ​​the TEG pad is, for example, 100 μm ２ or more, 200 μm ２ It may be 300 μm or more. ２ It may be more than that.

[0175] 48 is a cross-sectional view showing a redistribution layer 20 according to a ninth modification. The example shown in FIG. 48 differs from the example shown in FIG. 44 in that a first path RU1 electrically connecting the first conductive layer 22A and the third conductive layer 22C includes a wiring 25 in addition to the through electrode 26. The inclusion of the wiring 25 in the first path RU1 allows the position of the third conductive layer 22C to be different from the position of the first conductive layer 22A in a plan view.

[0176] 48 , the second path RU2 electrically connecting the second conductive layer 22B and the fourth conductive layer 22D may also include a wiring 25 in addition to the through electrode 26. By including the wiring 25 in the second path RU2, the position of the fourth conductive layer 22D can be made different from the position of the second conductive layer 22B in a plan view. As a result, for example, the distance between the third conductive layer 22C and the fourth conductive layer 22D can be made larger than the distance between the first conductive layer 22A and the second conductive layer 22B. In other words, fan-out of pads can be realized.

[0177] The first route RU1 and the second route RU2 are typically routes for transmitting signals.

[0178] 48, the wiring 25 of the first path RU1 and the second path RU2 is located in the second wiring layer 20B. Although not shown, the wiring 25 of the first path RU1 and the second path RU2 may be located in another wiring layer, such as the third wiring layer 20C.

[0179] In the example shown in FIG. 48, similarly to the above-described eighth modification, it may be determined whether the redistribution layer 20 is normal based on the measurement result of the capacitance.

[0180] 49 is a cross-sectional view showing an example of an inspection process for a wiring board 11 according to Modification 10. In this modification, capacitance measurement is performed on a wiring board 11 that includes a redistribution layer 20 including a third path RU3 that electrically connects a part of the first path RU1 and a part of the second path RU2, as shown in FIG.

[0181] The capacitance is measured in the same manner as in the eighth modified example. The first probe 91 is brought into contact with, for example, the first conductive layer 22A. The measurement unit 95 of the measurement device 90 measures the capacitance between the first conductive layer 22A with which the first probe 91 is in contact and the carrier substrate 12 with which the inspection electrode 97 is in contact. Figure 50 is a diagram showing an example of an equivalent circuit of the wiring substrate 11.

[0182] When the wiring board 11 is normal, the capacitance measured by the measuring device 90 is the sum of C1 and C2. When an electrical disconnection or short circuit occurs in the wiring board 11, the capacitance measured by the measuring device 90 changes compared to when the wiring board 11 is normal. For example, when an electrical disconnection occurs in the first path RU1 or the third path RU3, the capacitance decreases. The capacitance may also change when an electrical short circuit occurs due to the intermediate layer 14 or the like.

[0183] As in the case of the above-described eighth modified example, the inspection step may include a determination step of determining whether or not the redistribution layer 20 is normal. For example, the determination step may determine that the redistribution layer 20 is normal when the capacitance of the redistribution layer 20 is 0.7 to 1.3 times C1.

[0184] Although not shown, capacitance measurements may be performed on a wiring substrate 11 having a redistribution layer 20 in which a conductive layer located on an intermediate layer 14 forms a third path RU3, as shown in the above-mentioned Figure 40.

[0185] Although not shown, the electrical resistance may be measured as shown in Fig. 18 for a wiring board 11 including a redistribution layer 20 in which the first path RU1 and the second path RU2 are not electrically connected, as shown in Fig. 43. When an electrical short circuit occurs in the wiring board 11, the electrical resistance measured by the measuring device 90 becomes smaller than when the wiring board 11 is normal.

[0186] (Eleventh Modification) In the above-described embodiment, an example has been described in which the intermediate layer 14 is conductive. Although not shown, the intermediate layer 14 may be insulating. For example, the intermediate layer 14 may include an insulating inorganic material. Examples of the insulating inorganic material include metal oxides and metal nitrides.

[0187] In this modification, openings such as a first opening 145 and a second opening 146 are also formed in the intermediate layer 14. Therefore, gas generated inside the release layer 13 can be easily discharged through the openings.

[0188] 51 is a diagram showing an example of a product on which the wiring substrate 11 or the redistribution layer 20 is mounted. The wiring substrate 11 or the redistribution layer 20 can be used in a variety of products. For example, the wiring substrate 11 or the redistribution layer 20 is mounted in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, etc.

[0189] Although several modifications to the above-described embodiment have been described, it is of course possible to combine a plurality of modifications as appropriate and apply them to the above-described embodiment.

[0190] REFERENCE SIGNS LIST 10 wiring substrate group 11 wiring substrate 12 carrier substrate 13 peeling layer 14 intermediate layer 143 island portion 144 sea portion 145 first opening 146 second opening 20 rewiring layer 20A first wiring layer 20B second wiring layer 20C third wiring layer 21 insulating layer 211 protrusion 22 conductive layer 22A first conductive layer 22B second conductive layer 22C third conductive layer 22D fourth conductive layer 22E dummy conductive layer 24 pad 25 wiring 26 through electrode 90 measuring device 91 first probe 92 second probe 95 measuring unit 96 stage 97 inspection electrode

Claims

1. A wiring board comprising: a carrier substrate; a release layer including a first lower surface facing the carrier substrate and a first upper surface located opposite the first lower surface; an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located opposite the second lower surface; and a redistribution layer including a third lower surface at least partially facing the second upper surface and a third upper surface located opposite the third lower surface, wherein the redistribution layer comprises a plurality of stacked insulating layers and a plurality of conductive layers, each of the plurality of conductive layers being in contact with at least one of the plurality of insulating layers, a wiring board, wherein the plurality of conductive layers include a first conductive layer and a second conductive layer located on the third upper surface, a third conductive layer and a fourth conductive layer located on the intermediate layer, at least one conductive layer constituting a first path electrically connecting the first conductive layer and the third conductive layer, at least one conductive layer constituting a second path electrically connecting the second conductive layer and the fourth conductive layer, and at least one conductive layer constituting a third path electrically connecting a portion of the first path and a portion of the second path, the first path and the second path being independent of each other, the intermediate layer including at least a first island portion surrounding the third conductive layer in a planar view, and the first island portion not overlapping the fourth conductive layer in a planar view.

2. The wiring board according to claim 1, wherein the intermediate layer includes a second island portion that surrounds the fourth conductive layer in a plan view.

3. The wiring board according to claim 2, wherein the intermediate layer includes a sea portion that surrounds the first island portion and the second island portion in a plan view.

4. The wiring board according to claim 3, wherein said plurality of conductive layers includes at least one dummy conductive layer located on said sea portion and covered by said insulating layer.

5. A wiring board comprising: a carrier substrate; a release layer including a first lower surface facing the carrier substrate and a first upper surface located opposite the first lower surface; an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located opposite the second lower surface; and a redistribution layer including a third lower surface at least partially facing the second upper surface and a third upper surface located opposite the third lower surface, wherein the redistribution layer comprises a plurality of stacked insulating layers and a plurality of conductive layers, each of the plurality of conductive layers being in contact with at least one of the plurality of insulating layers, and the plurality of conductive layers including a first conductive layer and a second conductive layer located on the third upper surface, a third conductive layer located on the intermediate layer, at least one conductive layer constituting a first path electrically connecting the first conductive layer and the third conductive layer, and at least one conductive layer constituting a second path electrically connecting the second conductive layer and the third conductive layer, wherein the first path and the second path are independent of each other, The intermediate layer includes at least a first island portion that surrounds the third conductive layer in a plan view.

6. The wiring board according to claim 5, wherein the intermediate layer includes a sea portion that surrounds the first island portion in a plan view.

7. The wiring board according to claim 6, wherein said plurality of conductive layers includes at least one conductive layer located on said sea portion.

8. A wiring board comprising: a carrier substrate; a release layer including a first lower surface facing the carrier substrate and a first upper surface located on the opposite side of the first lower surface; an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located on the opposite side of the second lower surface; and a redistribution layer including a third lower surface at least partially facing the second upper surface and a third upper surface located on the opposite side of the third lower surface, wherein the redistribution layer comprises a plurality of stacked insulating layers and a plurality of conductive layers, each of the plurality of conductive layers being in contact with at least one of the plurality of insulating layers, and the plurality of conductive layers including a first conductive layer and a second conductive layer located on the third upper surface, a third conductive layer and a fourth conductive layer located on the intermediate layer, at least one conductive layer constituting a first path electrically connecting the first conductive layer and the third conductive layer, and at least one conductive layer constituting a second path electrically connecting the second conductive layer and the fourth conductive layer, wherein the first path and the second path are independent of each other, the intermediate layer includes at least a first island portion surrounding the third conductive layer in a plan view, and the first island portion does not overlap the fourth conductive layer in a plan view.

9. The wiring board according to claim 8, wherein the intermediate layer includes a second island portion that surrounds the fourth conductive layer in a plan view.

10. The wiring board according to claim 9, wherein the intermediate layer includes a sea portion that surrounds the first island portion and the second island portion in a plan view.

11. The wiring board according to claim 10, wherein the plurality of conductive layers includes at least one conductive layer located on the sea portion.

12. The wiring board according to any one of claims 1 to 11, wherein the release layer has insulating properties, and the intermediate layer has electrical conductivity.

13. The wiring board according to any one of claims 1 to 11, wherein the intermediate layer contains an inorganic material having insulating properties.

14. A method for inspecting a wiring board, comprising the steps of: preparing a wiring board according to any one of claims 1 to 11; bringing a first probe into contact with the first conductive layer; bringing a second probe into contact with the second conductive layer; and measuring the electrical resistance between the first probe and the second probe.

15. A method for inspecting a wiring board, comprising the steps of: preparing a wiring board according to any one of claims 1 to 11; bringing a first probe into contact with the first conductive layer; arranging an inspection electrode on the underside of the carrier substrate; and measuring the capacitance between the first probe and the inspection electrode, wherein the carrier substrate includes the underside and an upper side located opposite the underside, and the upper side of the carrier substrate faces the first lower side of the release layer.

Images