Crystalline oxide film, thin film transistor, and electronic apparatus

Abstract

The purpose of the present invention is to provide a crystalline oxide film, a thin film transistor, and an electronic apparatus that can control hysteresis. The present disclosure relates to a crystalline oxide film that contains In as a principal component and also contains at least two elements selected from the group that consists of Ga, Al, and Y and at least one element selected from the group that consists of Ce, Tb, Nd, Mn, Ru, Pd, and Pt.

Description

Crystalline oxide film, thin film transistor and electronic device

[0001] The present invention relates to a crystalline oxide film, a thin film transistor, and an electronic device.

[0002] In recent years, development of thin-film transistors (hereinafter sometimes referred to as "TFTs") using oxide semiconductor films as channels has progressed, replacing silicon semiconductor films such as amorphous silicon, low-temperature polysilicon, and single-crystal silicon. To improve the mobility and reliability of thin-film transistors containing oxide semiconductors, the use of polycrystalline oxide semiconductor films has been reported (e.g., Patent Documents 1 and 2). Polycrystalline oxide semiconductors generate numerous lattice defects at grain boundaries and within grains. To suppress the generation of these defects, methods have been reported in which water or hydrogen is introduced during sputtering film formation, or a metal element with a strong bond to oxygen is added. Thin-film transistors using oxide semiconductors as channels are used in a variety of applications, such as display devices, microprocessors, and memory circuits.

[0003] Japanese Patent No. 5373212 Japanese Patent Application Laid-Open No. 2018-107316

[0004] The thin film transistor for memory that stores data exhibits a memory function by utilizing the hysteresis phenomenon that occurs when charges are accumulated due to electrical traps.

[0005] On the other hand, it is desirable that the thin film transistors used in the display device have reduced hysteresis in order to suppress variations in image display.

[0006] Thin film transistors need to control the hysteresis phenomenon depending on their applications, and for this purpose, for example, defect generation is controlled. However, conventional methods for suppressing defect generation in polycrystalline oxide semiconductors have difficulty precisely controlling defects at grain boundaries and within grains while maintaining normally-off characteristics and high mobility. In other words, it has been difficult to control the hysteresis phenomenon while maintaining high mobility.

[0007] Therefore, an object of the present invention is to provide a crystalline oxide film, a thin film transistor, and an electronic device that are capable of controlling the hysteresis phenomenon.

[0008] The present invention includes the following embodiments. <1> A crystalline oxide film containing In as a main component, at least two elements selected from the group consisting of Ga, Al, and Y, and at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt. <2> The crystalline oxide film according to <1>, containing Ce. <3> The crystalline oxide film according to <2>, in which the content of Ce in the crystalline oxide film is 0.001 to 5.0 at% in terms of atomic ratio with respect to all metal elements. <4> The crystalline oxide film according to <2>, in which the content of Ce in the crystalline oxide film is 0.01 to 1.0 at% in terms of atomic ratio with respect to all metal elements. <5> The crystalline oxide film according to any one of <1> to <4>, containing Tb. <6> The crystalline oxide film according to <5>, in which the content of Tb in the crystalline oxide film is 0.001 to 7.0 at% in terms of atomic ratio with respect to all metal elements. <7> The crystalline oxide film according to <5>, wherein the content of Tb in the crystalline oxide film is 0.01 to 3.0 at% in terms of atomic ratio with respect to all metal elements. <8> The crystalline oxide film according to any one of <1> to <7>, containing Nd. <9> The crystalline oxide film according to <8>, wherein the content of Nd in the crystalline oxide film is 0.001 to 10 at% in terms of atomic ratio with respect to all metal elements. <10> The crystalline oxide film according to <8>, wherein the content of Nd in the crystalline oxide film is 0.01 to 5.0 at% in terms of atomic ratio with respect to all metal elements. <11> The crystalline oxide film according to any one of <1> to <10>, containing Ga and Al. <12> The crystalline oxide film according to any one of <1> to <11>, wherein the total content of Ga, Al, and Y in the crystalline oxide film is 5 to 25 at% in terms of atomic ratio with respect to all metal elements. <13> The crystalline oxide film according to any one of <1> to <11>, wherein the total content of Ga, Al, and Y in the crystalline oxide film is 7 to 20 at% in terms of atomic ratio with respect to all metal elements. <14> The crystalline oxide film according to any one of <1> to <13>, wherein the content of Al in the crystalline oxide film is 7 at% or less in terms of atomic ratio with respect to all metal elements, and the content of Y in the crystalline oxide film is 7 at% or less in terms of atomic ratio with respect to all metal elements. <15> A crystalline oxide film containing In as a main component. <16> The crystalline oxide film according to <15>, which contains Ga.<17> The crystalline oxide film according to <15> or <16>, containing at least two elements selected from the group consisting of Ga, Al, and Y. <18> The crystalline oxide film according to any one of <1> to <17>, wherein, in a planar TEM-EDS analysis of the crystalline oxide film, metal elements constituting the crystalline oxide film are not segregated at crystal grain boundaries in the film. <19> The crystalline oxide film according to any one of <1> to <18>, wherein the crystalline oxide film contains crystal grains with a bixbyite structure. <20> The crystalline oxide film according to <19>, wherein, in the particle size distribution of the bixbyite structure crystal grains contained in the crystalline oxide film, the average crystal grain size is 0.2 to 5 μm. <21> The crystalline oxide film according to <20>, wherein the average crystal grain size is 1.8 μm or less. <22> The crystalline oxide film according to any one of <1> to <21>, wherein the optical band gap is 3.0 eV or more. <23> The crystalline oxide film has a carrier concentration of 10. １８ cm －３ The crystalline oxide film according to any one of <1> to <22>, which is as follows: <24> A thin film transistor having an electrode and the crystalline oxide film according to any one of <1> to <23>. <25> An electronic device including the thin film transistor according to <24>. <26> A thin film transistor having an electrode and the crystalline oxide film according to any one of <1> to <23>, wherein the change in threshold voltage measured by the following measurement method before and after holding at 80°C for 7200 seconds while applying a gate voltage of +40 V is within a range of -3 to +3 V. (Measurement method) The Id-Vg characteristic is obtained by applying a drain voltage (Vd) of +20 V and measuring the current value Id while changing the gate voltage (Vg) from -40 V to +40 V in 0.2 V steps. Current value Id=10 －１０<27> A thin film transistor having an electrode and the crystalline oxide film according to any one of <1> to <23>, wherein the ratio (Id_after / Id_before) of the drain current value (Id_before) when the gate voltage (Vg) is +5 V in an Id-Vg curve obtained by measuring a current value Id while applying a drain voltage (Vd) of +0.1 V and varying the gate voltage (Vg) from −15 V to +15 V in 0.2 V steps to the drain current value (Id_after) when the gate voltage (Vg) is +5 V in an Id-Vg curve obtained under the same conditions as above after measuring the drain current value (Id_before), is 0.4 or more. <28> Use of the crystalline oxide film according to any one of <1> to <23> in a thin film transistor having excellent voltage resistance characteristics. <29> Use of the crystalline oxide film according to any one of <1> to <23> in a thin film transistor, in which the change in threshold voltage measured by the following measurement method before and after holding at 80°C for 7200 seconds while applying a gate voltage of +40 V is within the range of -3 to +3 V. (Measurement method) The Id-Vg characteristics are obtained by applying a drain voltage (Vd) of +20 V and measuring the current value Id by changing the gate voltage (Vg) from -40 V to +40 V in 0.2 V steps. Current value Id = 10 －１０<30> The crystalline oxide film according to any one of <1> to <23> is used in a thin film transistor, in which the ratio (Id_after / Id_before) of the drain current value (Id_before) when the gate voltage (Vg) is +5 V in an Id-Vg curve obtained by measuring the current value Id while applying a drain voltage (Vd) of +0.1 V and varying the gate voltage (Vg) from −15 V to +15 V in 0.2 V steps, to the drain current value (Id_after) when the gate voltage (Vg) is +5 V in an Id-Vg curve obtained under the same conditions as above after measuring the drain current value (Id_before), is 0.4 or more.

[0009] According to the present invention, it is possible to provide a crystalline oxide film, a thin film transistor, and an electronic device capable of controlling the hysteresis phenomenon.

[0010] 2A is a longitudinal sectional view showing a laminate according to the present embodiment; FIG. 2B is a longitudinal sectional view showing a state in which an oxide thin film is formed on a glass substrate; ２7 is a diagram showing a state in which a film has been formed. FIG. 8 is a longitudinal sectional view showing a thin film transistor according to the present embodiment. FIG. 9 is a longitudinal sectional view showing a thin film transistor according to the present embodiment. FIG. 10 is a longitudinal sectional view showing a thin film transistor according to the present embodiment. FIG. 11 is a longitudinal sectional view showing a quantum tunnel field effect transistor according to the present embodiment. FIG. 12 is a longitudinal sectional view showing another example of a quantum tunnel field effect transistor. FIG. 13 is a TEM (transmission electron microscope) photograph of a portion in FIG. 7 where a silicon oxide layer is formed between a p-type semiconductor layer and an n-type semiconductor layer. FIG. 14 is a longitudinal sectional view showing a quantum tunnel field effect transistor. FIG. 15 is a longitudinal sectional view showing a quantum tunnel field effect transistor. FIG. 16 is a longitudinal sectional view showing a quantum tunnel field effect transistor. FIG. 17 is a longitudinal sectional view showing a quantum tunnel field effect transistor. FIG. 18 is a longitudinal sectional view showing a quantum tunnel field effect transistor. FIG. 19 is a longitudinal sectional view showing a quantum tunnel field effect transistor. FIG. 19 is a longitudinal sectional view showing a quantum tunnel field effect transistor. 1 is a diagram showing the results of evaluating the resistance to high drain voltage in a thin film transistor using an amorphous oxide film or a crystalline oxide film.

[0011] The present invention will be described in detail below. Note that the present invention is not limited to the following embodiments (present embodiments), and can be practiced in various modifications within the scope of the gist thereof.

[0012] In the drawings, sizes, layer thicknesses, regions, etc. may be exaggerated for clarity. Therefore, the present invention is not limited to the illustrated sizes, layer thicknesses, regions, etc. Note that the drawings are schematic illustrations of ideal examples, and the present invention is not limited to the shapes, values, etc. shown in the drawings.

[0013] The ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion between components, and components that are not specified numerically are not limited in number.

[0014] In this specification and the like, the terms "film" and "layer" can be used interchangeably in some cases.

[0015] In the sintered body and oxide film of this specification and the like, the terms "compound" and "crystalline phase" can be interchangeable in some cases.

[0016] In this specification, the “oxide sintered body” may be simply referred to as the “sintered body.” In this specification, the “sputtering target” may be simply referred to as the “target.”

[0017] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes, wiring, switching elements (such as transistors), resistive elements, inductors, capacitors, and other elements with various functions.

[0018] In this specification, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms source and drain may be used interchangeably.

[0019] In this specification, a numerical range expressed using "to" means a range that includes the numerical value before "to" as the lower limit and the numerical value after "to" as the upper limit.

[0020] In the composition of the crystalline oxide, In is indium, Ga is gallium, Al is aluminum, Y is yttrium, and Ce is cerium. These elements coexist with oxygen in the crystalline oxide.

[0021] 1. Crystalline Oxide Film The crystalline oxide film according to this embodiment contains In as a main component, at least two elements selected from the group consisting of Ga, Al, and Y, and at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt. According to the above embodiment, a crystalline oxide film capable of controlling the hysteresis phenomenon can be obtained. It has been discovered that the hysteresis phenomenon can be obtained by including at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, preferably Ce, in the crystalline oxide film, and that the hysteresis phenomenon of the crystalline oxide film can be controlled by changing the content of these elements, preferably Ce. By adding at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, preferably Ce, it is possible to precisely control the defect level density at the bottom of the conductor of the oxide semiconductor depending on the amount of addition, and as a result, it is thought that it is possible to control hysteresis that occurs due to charge accumulation by electrical traps while maintaining normally-off characteristics and high mobility in a thin film transistor.

[0022] Note that controlling the hysteresis includes both increasing and decreasing the hysteresis. That is, since the crystalline oxide film according to this embodiment contains at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, preferably Ce, adjusting the content thereof can significantly increase or suppress the hysteresis phenomenon.

[0023] In addition, by containing at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, preferably Ce, the crystalline oxide film tends to exhibit a large S value. The S value is a value calculated from the Id-Vg characteristics after measuring a semiconductor transistor with a semiconductor parameter analyzer to obtain the Id-Vg characteristics. For more details, see the Examples described below. By using a thin film transistor with a large S value, a display device excellent in gray display control and gradation expression can be obtained (for example, SID Symposium Digest of Technical Papers. 2020. pp. 1358-1361; SID Symposium Digest of Technical Papers. 2022. pp. 314-317).

[0024] The contents of Ce, Tb, Nd, Mn, Ru, Pd, and Pt in the crystalline oxide film are each independently, in terms of atomic ratio to the total metal elements, preferably 0.001 to 10 at%, more preferably 0.005 to 7.0 at%, even more preferably 0.01 to 5.0 at%, even more preferably 0.01 to 3.0 at%, even more preferably 0.05 to 2.0 at%, and even more preferably 0.05 to 1.0 at%, from the viewpoint of controlling hysteresis. When the contents of Ce, Tb, Nd, Mn, Ru, Pd, and Pt are each independently, for example, 0.001 at% or more, the S value tends to be large. When the contents of Ce, Tb, Nd, Mn, Ru, Pd, and Pt are each independently, for example, 10 at% or less, better normally-off characteristics and higher mobility tend to be obtained. Furthermore, from the viewpoint of controlling hysteresis, obtaining better normally-off characteristics, and obtaining higher mobility, it is preferable that the total content of Ce, Tb, Nd, Mn, Ru, Pd, and Pt in the crystalline oxide film be within the above range.

[0025] The crystalline oxide film preferably contains Ce. When Ce is contained, the Ce content in the crystalline oxide film is, in terms of atomic ratio with respect to all metal elements, preferably 0.001 to 5.0 at%, more preferably 0.005 to 3.0 at%, even more preferably 0.01 to 2.0 at%, even more preferably 0.01 to 1.0 at%, even more preferably 0.05 to 0.5 at%, and even more preferably 0.05 to 0.2 at% from the viewpoint of controlling hysteresis. Furthermore, when the Ce content is, for example, 0.001 at% or more, the S value tends to increase. Furthermore, when the Ce content is, for example, 5.0 at% or less, better normally-off characteristics and higher mobility tend to be obtained.

[0026] The crystalline oxide film preferably contains Tb from the viewpoint of controlling hysteresis. When Tb is contained, the content of Tb in the crystalline oxide film is preferably 0.001 to 7.0 at%, more preferably 0.005 to 5.0 at%, and even more preferably 0.01 to 3.0 at%, in atomic ratio with respect to all metal elements from the viewpoint of controlling hysteresis.

[0027] From the viewpoint of controlling hysteresis, the crystalline oxide film also preferably contains Nd. When Nd is contained, the content of Nd in the crystalline oxide film is preferably 0.001 to 10 at %, more preferably 0.005 to 7.5 at %, and even more preferably 0.01 to 5.0 at %, in atomic ratio with respect to all metal elements, from the viewpoint of controlling hysteresis.

[0028] When the crystalline oxide film contains at least one element selected from the group consisting of Mn, Ru, Pd, and Pt, the contents of Mn, Ru, Pd, and Pt in the crystalline oxide film are each independently, in terms of atomic ratio relative to all metal elements, preferably 0.001 to 5.0 at%, more preferably 0.005 to 3.0 at%, even more preferably 0.01 to 2.0 at%, even more preferably 0.01 to 1.0 at%, even more preferably 0.05 to 0.5 at%, and even more preferably 0.05 to 0.3 at%, from the viewpoint of controlling hysteresis, achieving better normally-off characteristics, and achieving higher mobility. In this embodiment, it is also preferable that the total content of Mn, Ru, Pd, and Pt in the crystalline oxide film be within the above range.

[0029] The crystalline oxide film contains at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, and preferably contains at least one element selected from the group consisting of Ce, Tb, and Nd. Only one of these metal elements may be contained.

[0030] In this specification, "containing In... as a main component" means that 50 at % or more of the total number of atoms of the metal elements that constitute the crystalline oxide film is In.

[0031] The crystalline oxide film according to this embodiment may consist essentially of In as a main component, at least two selected from the group consisting of Ga, Al, and Y, at least one selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, and O. "Substantially" means that the crystalline oxide film according to this embodiment may contain other components, such as impurities described below, within the range in which the effects of the present invention resulting from the combination of In, Ga, Al, Y, Ce, Tb, Nd, Mn, Ru, Pd, Pt, and O are obtained.

[0032] The crystalline oxide film according to this embodiment may be substantially composed of In as a main component, at least two selected from the group consisting of Ga, Al, and Y, at least one selected from the group consisting of Ce, Tb, and Nd, and O. "Substantially" means that the crystalline oxide film according to this embodiment may contain other components, such as impurities described below, within the range in which the effects of the present invention resulting from the combination of In, Ga, Al, Y, Ce, Tb, Nd, and O are obtained.

[0033] The crystalline oxide film according to this embodiment may be substantially composed of In as a main component, at least two selected from the group consisting of Ga, Al, and Y, Ce, and O. "Substantially" means that the crystalline oxide film according to this embodiment may contain other components, such as impurities described below, within the range in which the effects of the present invention resulting from the combination of In, Ga, Al, Y, Ce, and O are obtained.

[0034] The crystalline oxide film according to this embodiment may be substantially composed of In as a main component, at least two selected from the group consisting of Ga, Al, and Y, Tb, and O. "Substantially" means that the crystalline oxide film according to this embodiment may contain other components, such as impurities described below, within the range in which the effects of the present invention resulting from the combination of In, Ga, Al, Y, Tb, and O are achieved.

[0035] The crystalline oxide film according to this embodiment may consist essentially of In as a main component, at least two selected from the group consisting of Ga, Al, and Y, Nd, and O. "Substantially" means that the crystalline oxide film according to this embodiment may contain other components, such as impurities described below, within the range in which the effects of the present invention resulting from the combination of In, Ga, Al, Y, Nd, and O are achieved.

[0036] The metal elements contained in the crystalline oxide film according to this embodiment may essentially consist of In, at least two selected from the group consisting of Ga, Al, and Y, and at least one selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt. The metal elements contained in the crystalline oxide film according to this embodiment may consist of 80 at % or more, 90 at % or more, 95 at % or more, 96 at % or more, 97 at % or more, 98 at % or more, or 99 at % or more of In, at least two selected from the group consisting of Ga, Al, and Y, and at least one selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt.

[0037] The metal elements contained in the crystalline oxide film according to this embodiment may essentially consist of In, at least two elements selected from the group consisting of Ga, Al, and Y, and at least one element selected from the group consisting of Ce, Tb, and Nd. The metal elements contained in the crystalline oxide film according to this embodiment may consist of 80 at % or more, 90 at % or more, 95 at % or more, 96 at % or more, 97 at % or more, 98 at % or more, or 99 at % or more of In, at least two elements selected from the group consisting of Ga, Al, and Y, and at least one element selected from the group consisting of Ce, Tb, and Nd.

[0038] The metal elements contained in the crystalline oxide film according to this embodiment may essentially consist of Ce, and at least two elements selected from the group consisting of In, Ga, Al, and Y. The metal elements contained in the crystalline oxide film according to this embodiment may consist of In, at least two elements selected from the group consisting of Ga, Al, and Y, and Ce at a ratio of 80 at % or more, 90 at % or more, 95 at % or more, 96 at % or more, 97 at % or more, 98 at % or more, or 99 at % or more.

[0039] The metal elements contained in the crystalline oxide film according to this embodiment may essentially consist of In, at least two elements selected from the group consisting of Ga, Al, and Y, and Tb. The metal elements contained in the crystalline oxide film according to this embodiment may consist of In, at least two elements selected from the group consisting of Ga, Al, and Y, and Tb at a ratio of 80 at % or more, 90 at % or more, 95 at % or more, 96 at % or more, 97 at % or more, 98 at % or more, or 99 at % or more.

[0040] The metal elements contained in the crystalline oxide film according to this embodiment may essentially consist of In, at least two elements selected from the group consisting of Ga, Al, and Y, and Nd. The metal elements contained in the crystalline oxide film according to this embodiment may consist of In, at least two elements selected from the group consisting of Ga, Al, and Y, and Nd at a ratio of 80 at % or more, 90 at % or more, 95 at % or more, 96 at % or more, 97 at % or more, 98 at % or more, or 99 at % or more.

[0041] The content of In in the crystalline oxide film is, in atomic ratio with respect to all metal elements, preferably 70 to 99 at%, preferably 75 to 99 at%, more preferably 80 to 98 at%, even more preferably 82 to 96 at%, and still more preferably 85 to 95 at%. Note that if the atomic ratio with respect to all metal elements in the crystalline oxide film is 50 at% or more, the crystalline oxide film according to this embodiment can exhibit sufficiently high saturated mobility when used in a TFT.

[0042] (Positive trivalent metal elements) Ga, Al, and Y are positive trivalent metal elements, and containing two of these elements makes it easier to control defect generation. For example, the crystalline oxide film preferably contains Ga and Al. This makes it easier to control defect generation. In this specification, "Ga, Al, and Y" are also collectively referred to as positive trivalent metal elements.

[0043] The total content of Ga, Al, and Y in the crystalline oxide film is, in atomic ratio with respect to all metal elements, preferably 5 to 25 at%, more preferably 7 to 20 at%, even more preferably 10 to 18 at%, and even more preferably 12 to 17 at%. If the total content of positive trivalent metal elements is 5% or more, columnar crystals perpendicular to the support tend to form after annealing the oxide film, resulting in excellent transistor characteristics. Furthermore, if the total content of positive trivalent metal elements is 25% or less, the crystallization temperature is lowered, making it easier to obtain a crystallized oxide film under the manufacturing conditions for thin film transistors.

[0044] The Ga content in the crystalline oxide film is preferably 3 to 25 at %, more preferably 5 to 18 at %, and even more preferably 7 to 15 at %, in atomic ratio relative to all metal elements.

[0045] The content of Al in the crystalline oxide film is preferably 7 at% or less, more preferably 0.1 to 6 at%, and even more preferably 0.5 to 5 at%, in atomic ratio relative to all metal elements. The content of Y in the crystalline oxide film is preferably 7 at% or less, more preferably 0.1 to 6 at%, and even more preferably 0.5 to 5 at%, in atomic ratio relative to all metal elements.

[0046] The crystalline oxide film may contain impurities. The impurities may be, for example, elements mixed in the raw materials or manufacturing process. The impurities may be, for example, elements contained in the target used to obtain the crystalline oxide film, or elements mixed in during the target manufacturing process, etc. Examples of impurities include alkali metal elements (such as Li (lithium), Na (sodium), K (potassium), and Rb (rubidium)), alkaline earth metal elements (such as Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium)), B (boron), C (carbon), N (nitrogen), F (fluorine), Si (silicon), Zr (zirconium), Fe (iron), Zn (zinc), Sn (tin), Al (aluminum), and Cl (chlorine).

[0047] The crystalline oxide film according to this embodiment may be composed of In as a main component, at least two elements selected from the group consisting of Ga, Al, and Y, Ce, O, and impurities in an atomic ratio of 0 to 1 at% relative to all metal elements. In this embodiment, "Ce" may be replaced with "at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt," or "at least one element selected from the group consisting of Ce, Tb, and Nd," or "Tb," or "Nd." The content of the impurities is not particularly limited, but may be preferably 0 to 1 at%, more preferably 0 to 0.1 at%, even more preferably 0 to 0.01 at%, and even more preferably 0 to 0.001 at%, relative to all metal elements. The concentration of the above-mentioned impurities can be analyzed by ICP (Inductive Coupled Plasma) measurement for the crystalline oxide film, and by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope for the crystalline oxide film in the TFT element.

[0048] The atomic ratios of the crystalline oxide film according to this embodiment preferably satisfy the conditions expressed by the following formulas (1'), (2'), (3'), and (4'): 0.70≦In / (In+Ga+Y+Al+M)≦0.99 (1') 0.03≦Ga / (In+Ga+Y+Al+M)≦0.25 (2') 0.001≦(Y+Al) / (In+Ga+Y+Al+M)≦0.07 (3') 0.00001≦M / (In+Ga+Y+Al+M)≦0.10 (4') Here, In, Ga, Y, Al, and M in formulas (1') to (4') represent the number of atoms of In, Ga, Y, Al, and metal element M contained in the crystalline oxide film, respectively. The metal element M is at least one selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd and Pt, and preferably at least one selected from the group consisting of Ce, Tb and Nd.

[0049] The effects obtained by satisfying the formulas (1') to (3') and the preferable and more preferable numerical ranges (preferable and more preferable upper and lower limits) are the same as those of the formulas (1) to (3) below.

[0050] When the atomic ratio shown in formula (4') is 0.00001 or more, a crystalline oxide film containing defects is obtained, and transistor characteristics exhibiting a large S value while having hysteresis in the TFT are obtained. When the atomic ratio shown in formula (4') is 0.10 or less, excessive generation of defect levels can be suppressed, making it easier to obtain a crystalline oxide film exhibiting excellent TFT characteristics. The atomic ratio shown in formula (4') is preferably 0.00005 to 0.07, more preferably 0.0001 to 0.05, more preferably 0.0001 to 0.03, more preferably 0.0005 to 0.02, and more preferably 0.0005 to 0.01.

[0051] When the crystalline oxide film according to this embodiment contains Ce, the atomic ratio of the crystalline oxide film preferably satisfies the conditions expressed by the following formulas (1), (2), (3), and (4): 0.70≦In / (In+Ga+Y+Al+Ce)≦0.99 (1) 0.03≦Ga / (In+Ga+Y+Al+Ce)≦0.25 (2) 0.001≦(Y+Al) / (In+Ga+Y+Al+Ce)≦0.07 (3) 0.00001≦Ce / (In+Ga+Y+Al+Ce)≦0.05 (4) Here, In, Ga, Y, Al, and Ce in formulas (1) to (4) represent the number of In, Ga, Y, Al, and Ce atoms contained in the crystalline oxide film, respectively. Furthermore, in formulas (1) to (4), the denominators of the fractions may be the total metal elements.

[0052] If the atomic ratio shown in formula (1) is 0.70 or more, when the crystalline oxide film according to this embodiment is used in a TFT, it can exhibit sufficiently high saturation mobility. If the atomic ratio shown in formula (1) is 0.99 or less, leakage current is unlikely to occur when a negative gate voltage is applied to the TFT, and transistor characteristics with excellent ON / OFF switching can be obtained. The atomic ratio shown in formula (1) is preferably 0.80 to 0.98, and more preferably 0.82 to 0.96.

[0053] If the atomic ratio shown in formula (2) is 0.03 or more, columnar crystals are formed perpendicular to the support after annealing the oxide film, resulting in better transistor characteristics. If the atomic ratio shown in formula (2) is 0.25 or less, the crystallization temperature is lowered, making it easier to obtain a crystallized oxide film under the manufacturing conditions for thin film transistors. The atomic ratio shown in formula (2) is preferably 0.05 to 0.18, and more preferably 0.07 to 0.15.

[0054] If the atomic ratio shown in formula (3) is 0.001 or more, the carrier concentration in the crystalline oxide film can be suppressed, leakage current is less likely to occur when a negative gate voltage is applied to the TFT, and transistor characteristics with better ON / OFF characteristics can be obtained. If the atomic ratio shown in formula (3) is 0.07 or less, when the crystalline oxide film according to this embodiment is used in a TFT, it can exhibit sufficiently high saturation mobility. The atomic ratio shown in formula (3) is preferably 0.001 to 0.06, and more preferably 0.005 to 0.05.

[0055] When the atomic ratio shown in formula (4) is 0.00001 or more, a crystalline oxide film containing defects is obtained, and transistor characteristics exhibiting a large S value while having hysteresis in the TFT are obtained. When the atomic ratio shown in formula (4) is 0.05 or less, excessive generation of defect levels can be suppressed, making it easier to obtain a crystalline oxide film exhibiting excellent TFT characteristics. The atomic ratio shown in formula (4) is preferably 0.00005 to 0.03, more preferably 0.0001 to 0.02, more preferably 0.0001 to 0.01, and more preferably 0.0005 to 0.005.

[0056] When the crystalline oxide film according to this embodiment contains Tb, the atomic ratio of the crystalline oxide film preferably satisfies the conditions represented by the following formulas (Tb-1), (Tb-2), (Tb-3), and (Tb-4). 0.70≦In / (In+Ga+Y+Al+Tb)≦0.99 (Tb-1) 0.03≦Ga / (In+Ga+Y+Al+Tb)≦0.25 (Tb-2) 0.001≦(Y+Al) / (In+Ga+Y+Al+Tb)≦0.07 (Tb-3) 0.00001≦Tb / (In+Ga+Y+Al+Tb)≦0.07 (Tb-4) Here, In, Ga, Y, Al, and Tb in formulas (Tb-1) to (Tb-4) represent the number of In, Ga, Y, Al, and Tb atoms contained in the crystalline oxide film, respectively. Also, in formulas (Tb-1) to (Tb-4), the denominator of the fraction may be the total metal elements.

[0057] When the crystalline oxide film according to this embodiment contains Nd, the atomic ratio of the crystalline oxide film preferably satisfies the conditions represented by the following formulas (Nd-1), (Nd-2), (Nd-3), and (Nd-4). 0.70≦In / (In+Ga+Y+Al+Nd)≦0.99 (Nd-1) 0.03≦Ga / (In+Ga+Y+Al+Nd)≦0.25 (Nd-2) 0.001≦(Y+Al) / (In+Ga+Y+Al+Nd)≦0.07 (Nd-3) 0.00001≦Nd / (In+Ga+Y+Al+Nd)≦0.10 (Nd-4) Here, In, Ga, Y, Al, and Nd in formulas (Nd-1) to (Nd-4) represent the number of In, Ga, Y, Al, and Nd atoms contained in the crystalline oxide film, respectively. Also, in formulas (Nd-1) to (Nd-4), the denominator of the fraction may be the total metal elements.

[0058] The effects obtained by satisfying formulas (Tb-1) to (Tb-3) and (Nd-1) to (Nd-3), and the preferable and more preferable numerical ranges (preferable and more preferable upper and lower limit values) are the same as those of formulas (1) to (3) above.

[0059] When the atomic ratio shown in formula (Tb-4) is 0.00001 or more, a crystalline oxide film containing defects is obtained, and transistor characteristics exhibiting a large S value while having hysteresis in the TFT are obtained. When the atomic ratio shown in formula (Tb-4) is 0.07 or less, excessive generation of defect levels can be suppressed, making it easier to obtain a crystalline oxide film exhibiting excellent TFT characteristics. The atomic ratio shown in formula (Tb-4) is preferably 0.00005 to 0.05, and more preferably 0.0001 to 0.03.

[0060] When the atomic ratio shown in formula (Nd-4) is 0.00001 or more, a crystalline oxide film containing defects is obtained, and transistor characteristics exhibiting a large S value while having hysteresis in the TFT are obtained. When the atomic ratio shown in formula (Nd-4) is 0.10 or less, excessive generation of defect levels can be suppressed, making it easier to obtain a crystalline oxide film exhibiting excellent TFT characteristics. The atomic ratio shown in formula (Nd-4) is preferably 0.00005 to 0.075, and more preferably 0.0001 to 0.05.

[0061] When the crystalline oxide film according to this embodiment is used in a TFT, the resulting TFT exhibits excellent voltage resistance characteristics due to its crystallinity. From the viewpoint of excellent voltage resistance characteristics, the crystalline oxide film according to this embodiment preferably contains In as a main component, more preferably contains In and Ga as main components, and even more preferably contains In and at least two selected from the group consisting of Ga, Al, and Y as main components. The contents of In, Ga, Al, and Y are as described above.

[0062] The content (atomic ratio) of each metal element in the crystalline oxide film can be determined by measuring the amount of each element by ICP (Inductive Coupled Plasma) measurement. For ICP measurement, an inductively coupled plasma emission spectrometer can be used.

[0063] The content (atomic ratio) of each metal element in the crystalline oxide film in the TFT element can be analyzed by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope.

[0064] "Total metal elements" refers to the metal elements contained in the crystalline oxide film. When the crystalline oxide film contains silicon element, the amount of silicon element is not included in the total metal elements.

[0065] The term "crystalline oxide film" means that diffraction points are observed by analyzing the electron diffraction pattern. More specifically, this can be confirmed by the method for determining whether the oxide is amorphous or crystalline by electron diffraction described in the Examples.

[0066] The crystalline oxide film according to this embodiment preferably contains crystal grains with a bixbyite structure. The presence of crystal grains with a bixbyite structure can be confirmed by analyzing the crystalline oxide film by electron diffraction. Since crystal grains with a bixbyite structure are cubic crystals with good symmetry, the inclusion of such crystal grains in the crystalline oxide film can suppress a decrease in TFT characteristics (mobility) even across crystal grain boundaries. Furthermore, the deterioration of transistor characteristics when a high gate voltage or a high drain voltage is applied can be suppressed.

[0067] In the particle size distribution of the bixbyite-structured crystal grains contained in the crystalline oxide film, the average crystal grain size is preferably 0.2 to 5 μm, more preferably 0.5 to 3.0 μm, even more preferably 0.7 to 2.0 μm, and even more preferably 0.7 to 1.8 μm. Controlling the average crystal grain size to 0.2 to 5 μm results in a crystalline oxide film with small variations in the carrier concentration distribution within each crystal grain. The average crystal grain size in the crystalline oxide film is measured based on a planar TEM observation image (also referred to as a "planar TEM image"). That is, it is calculated by analyzing the diameter of the crystal grains observed by a planar TEM observed at a magnification of 200,000 times using a transmission electron microscope.

[0068] In the crystalline oxide film according to this embodiment, it is preferable that the metal elements constituting the crystalline oxide film are not segregated at the grain boundaries in the film in planar TEM-EDS analysis. "Not segregated at the grain boundaries in the thin film" means that each metal element is uniformly distributed and there is no bias at the grain boundaries. When the metal elements constituting the crystalline oxide film are not segregated at the grain boundaries, the in-plane uniformity of the transistor characteristics is improved when a transistor is fabricated on a large-area substrate.

[0069] The optical band gap of the crystalline oxide film according to this embodiment is preferably 3.0 eV, more preferably 3.3 to 5.0 eV, and even more preferably 3.5 to 4.0 eV. When the optical band gap is in this range, the crystalline oxide film has semiconductor properties, and deterioration of the transistor properties when irradiated with visible light can be suppressed.

[0070] The carrier concentration in the crystalline oxide film according to this embodiment is preferably 10 １８ cm －３ or less, more preferably 1×10 １５ ~5 x 10 １７ cm －３ and more preferably 3 × 10 １６ ~3 x 10 １７ cm －３ When the carrier concentration is within this range, the controllability of the transistor characteristics by the threshold voltage is improved, leakage current is less likely to occur when a negative gate voltage is applied, and transistor characteristics with excellent ON / OFF characteristics can be obtained.

[0071] The thickness of the crystalline oxide film according to this embodiment is preferably 1 to 500 nm, more preferably 5 to 300 nm, and even more preferably 10 to 100 nm. By keeping the thickness within this range, crystal growth during film formation can be suppressed, and after annealing the oxide film, columnar crystals are formed in the direction perpendicular to the support, resulting in excellent transistor characteristics.

[0072] The crystalline oxide film according to this embodiment can be applied to various integrated circuits such as logic circuits, memory circuits, and differential amplifier circuits, and can be applied to electronic devices, etc. The crystalline oxide film according to this embodiment can also be applied as a partial layer of a solar cell, and a partial layer of a display device such as a liquid crystal element, an organic electroluminescence element, an inorganic electroluminescence element, a micro organic EL display, a micro LED (Light Emitting Diode) display, a mini LED display, and electronic paper. Furthermore, the oxide thin film according to this embodiment can be applied as a partial layer of a solid-state imaging element, an X-ray sensor, a power semiconductor element, a touch panel, an LSI (Large Scale Integrated Circuit), a resistance change type memory, a DRAM (Dynamic Random Access Memory), a ferroelectric memory, a BEOL (Back End of Line), and a microprocessor. The crystalline oxide film according to this embodiment can also be used as a semiconductor layer of a field-effect transistor, a static induction transistor, a quantum tunnel field-effect transistor, a Schottky barrier transistor, a Schottky diode, a PN diode, and a resistor element, or as a part of any of these layers.

[0073] 2. Method for Producing Crystalline Oxide Film The crystalline oxide film according to this embodiment can be formed using, for example, a sputtering target including an oxide sintered body containing In, a positive trivalent metal element, and at least one selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt. This sputtering target may be referred to as the sputtering target according to this embodiment. The oxide sintered body included in the sputtering target according to this embodiment may be referred to as the oxide sintered body according to this embodiment. In the oxide sintered body according to this embodiment, the positive trivalent metal element is at least two selected from the group consisting of Ga, Al, and Y. In the oxide sintered body according to this embodiment, In is preferably the main component.

[0074] An example of the method for producing a crystalline oxide film according to this embodiment is a production method including a step of forming an oxide film by sputtering using the sputtering target according to this embodiment. In the film formation step by sputtering, one or more gases selected from the group consisting of argon, oxygen, hydrogen, water vapor, and nitrogen, which are substantially free of impurity gases, are used as the sputtering gas. The "impurities" contained in the sputtering gas refer to trace elements that are not intentionally added and do not substantially affect sputtering performance.

[0075] The atomic composition ratio of the oxide film obtained by sputtering reflects the atomic composition ratio of the oxide sintered body in the sputtering target. Therefore, it is preferable to form the film using a sputtering target including an oxide sintered body having an atomic composition ratio similar to that of the desired oxide film. Therefore, the description of the content of each atom in the crystalline oxide film according to this embodiment can be used as the description of the content of each atom in the oxide sintered body in the sputtering target. The target used in the sputtering method preferably has an impurity metal content of 500 ppm or less, more preferably 100 ppm or less. In particular, by setting the content of tetravalent Sn in the target to 500 ppm or less, more preferably 100 ppm or less, even if Sn contained in the target remains as an impurity in the oxide film, it does not become an electron scattering source in the crystalline oxide semiconductor of this embodiment, and good TFT characteristics can be obtained. The content of impurity metals in the target can be measured by ICP (Inductive Coupled Plasma). The "impurities" contained in the target refer to trace elements that are mixed in the raw materials or during the manufacturing process and are not intentionally added, and that do not substantially affect the performance of the target or semiconductor. The "impurity metals" refer to metal elements among the elements considered as "impurities."

[0076] The crystalline oxide film according to this embodiment can also be manufactured as a part of a laminate including, for example, a crystalline oxide film and a protective film.

[0077] Examples of a method for manufacturing the laminate include a step of forming an oxide film, a step of applying a heat treatment to the oxide film to form a protective film on the oxide, or a step of forming a protective film on the oxide film without applying a heat treatment to the oxide film, and a step of applying a heat treatment to a laminate including the oxide film and the protective film.

[0078] The oxide film obtained by sputtering using a sputtering target mainly composed of indium oxide and one or more gases selected from the group consisting of argon, oxygen, hydrogen, water vapor, and nitrogen, which are substantially free of impurities, is an amorphous oxide film. This oxide film is patterned into islands by photolithography, and then heated and crystallized before forming a protective film, resulting in a crystalline oxide film in which the surface crystals have a single crystal orientation. Each step is described below.

[0079] (Oxide Film Formation Process) In the oxide film formation process, a TFT can be manufactured by forming an oxide film containing In as a main component on, for example, a substrate, a buffer layer, an insulating layer, or other lower layer constituting a TFT. The film formation method is not particularly limited, and examples thereof include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, ALD, PLD, MO-CVD, ICP-CVD, a sol-gel method, a coating method, and mist CVD. When forming a film by sputtering, the oxide film is formed by sputtering using a planar sputtering cathode apparatus or a rotary sputtering cathode apparatus using the sputtering target according to this embodiment, using one or more gases selected from the group consisting of argon, oxygen, hydrogen, water vapor, and nitrogen, which are substantially free of impurity gases, as a sputtering gas (see, for example, FIG. 2A ). FIG. 2A shows an oxide film 83 formed on a glass substrate 81.

[0080] The phrase "the sputtering gas is substantially free of impurity gases" means that impurity gases other than the gas to be used are not actively introduced, except for adsorbed water brought in with the gas introduction, and gases that cannot be eliminated (unavoidable impurity gases) such as gases leaking from the chamber or adsorbed gases. In this embodiment, for example, a commercially available mixed gas of high-purity argon and high-purity oxygen can be used as the sputtering gas. It is preferable to eliminate impurities from the sputtering gas if possible.

[0081] The proportion of impurity gas in the sputtering gas is preferably 0.1% by volume or less, more preferably 0.05% by volume or less. If the proportion of impurity gas is 0.1% by volume or less, crystallization of the oxide film proceeds without any problems. The purity of the high-purity argon and high-purity oxygen is preferably 99% by volume or more, more preferably 99.9% by volume or more, and even more preferably 99.99% by volume or more.

[0082] For example, when argon and oxygen are used, the oxygen partial pressure in the mixed gas is preferably greater than 0% by volume and less than 10% by volume, more preferably greater than 0% by volume and less than 5% by volume. If the oxygen partial pressure is greater than 0% by volume and less than 10% by volume, the oxide film easily crystallizes and becomes a semiconductor when heated. By changing the oxygen partial pressure, the degree of oxidation of the oxide film, i.e., the degree of crystallization, can be adjusted. The oxygen partial pressure can be selected appropriately as needed.

[0083] For example, when argon and water vapor are used, the water pressure in the mixed gas is preferably more than 0.03% by volume and not more than 10% by volume, and more preferably more than 0.03% by volume and not more than 5% by volume. If the water pressure is more than 0.03% by volume and not more than 5% by volume, the material easily crystallizes and becomes a semiconductor when heated. Alternatively, a mixed gas of hydrogen and oxygen may be used instead of water.

[0084] The magnetic flux density during sputtering is preferably 700 G or more. If the magnetic flux density during sputtering is 700 G or more, the plasma density during sputtering film formation can be increased, the density of the oxide film increases, and a well-crystallized oxide film can be obtained by heat treatment after patterning. Even if the magnetic flux density during sputtering is less than 700 G, the output density during sputtering can be set to 2.5 kW / cm. ２ By setting the temperature to the above level, the plasma density during sputtering deposition can be increased, resulting in a well-crystallized oxide film.

[0085] In the oxide film forming step, the sputtering target according to this embodiment is preferably mounted in an RF magnetron sputtering device or a DC magnetron sputtering device and sputtered.

[0086] The sputtering target according to this embodiment preferably contains indium, gallium, and a lanthanoid element. Adding not only indium but also gallium and a lanthanoid element to the sputtering target allows for a uniform amorphous structure during oxide film formation. The sputtering target according to this embodiment contains In, a positive trivalent metal element, and at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt. This allows for an amorphous oxide film to be formed during film formation without introducing anything other than a rare gas and oxygen (e.g., water) into the sputtering gas. By heating this oxide film in a heat treatment process described below, columnar crystals can be grown on the support. By applying the oxide film formed as described above to a TFT, excellent electron carrier injection during operation is achieved, resulting in a TFT element with high mobility while controlling hysteresis. The atomic ratios of In, Ga, Al, Y, and Ce in the sputtering target according to this embodiment may be the same as or approximately the same as the atomic ratios of In, Ga, Al, Y, and Ce in the crystalline oxide film according to this embodiment. The same applies to the atomic ratios of elements other than In, Ga, Al, Y, and Ce, such as Tb, Nd, Mn, Ru, Pd, and Pt.

[0087] (Protective Film Forming Step) When a protective film is formed on a crystalline oxide film, it is preferable to form the protective film on the oxide film after subjecting the obtained oxide film to a heat treatment in an oxidizing atmosphere. By performing the heat treatment before forming the protective film, oxygen is supplied to the surface of the oxide film, and a crystalline oxide film having a small amount of oxygen vacancy and exhibiting semiconductor properties can be obtained.

[0088] The protective film may be made of, for example, SiO ２ , SiN ｘ , SiON ｘ , Al ２ O ３ and Ga ２ O ３ The thickness of the protective film is usually 50 to 500 nm. Examples of the method for forming the protective film include CVD, sputtering, and coating. FIG. 2B shows a method for forming a protective film by depositing a SiO ２ The film 85 is shown formed.

[0089] (Heat Treatment Step) Next, after forming the oxide film or the protective film, a heat treatment is performed. This heat treatment is sometimes called annealing. For the heat treatment step, for example, a hot air oven, an IR oven, a lamp annealing device, a laser annealing device, a thermal plasma device, or the like can be used. The heat treatment temperature is preferably 250 to 500°C, more preferably 280 to 470°C, and even more preferably 300 to 450°C. If the heat treatment temperature after forming the oxide film is 250°C or higher, the oxide film is likely to crystallize. If the heat treatment temperature after forming the oxide film is 500°C or lower, abnormal crystal growth and enlargement of the crystal grains can be prevented, and the crystal grain size can be controlled to be small.

[0090] The heating time in the heat treatment step is preferably 0.1 to 5 hours, more preferably 0.3 to 3 hours, and even more preferably 0.5 to 2 hours. If the heating time in the heat treatment step is 0.1 hour or more, crystallization does not occur and the oxide film is likely to crystallize. If the heating time in the heat treatment step is 5 hours or less, it is economically efficient. "Heating time" refers to the time during which a predetermined maximum temperature is maintained (retention time) during heat treatment.

[0091] The temperature rise rate in the heat treatment step is preferably 2 to 40°C / min, more preferably 3 to 20°C / min. If the temperature rise rate in the heat treatment step is 2°C / min or more, the production efficiency of the oxide film is improved. If the temperature rise rate in the heat treatment step is 40°C / min or less, the metal elements are uniformly diffused during crystallization, and crystals can be formed in which metal does not segregate at the grain boundaries. Furthermore, the temperature rise rate in the heat treatment step is different from the value calculated from the set temperature and set time of the furnace, but is the value obtained by dividing the actual temperature of the oxide film by time. The actual temperature of the oxide film can be determined, for example, by measuring an area within 1 cm of the oxide film in the furnace with a thermocouple.

[0092] The heat treatment step is preferably carried out in an air atmosphere, more preferably in an air atmosphere with a humidity of 10% or more at 25° C. When the heat treatment step is carried out in an air atmosphere or an air atmosphere with a humidity of 10% or more, hydrogen and oxygen diffuse into the film during annealing, which can promote crystallization.

[0093] The heat treatment step is preferably performed after patterning the oxide film. Performing the heat treatment after patterning promotes crystallization while removing excess oxygen present in the film during film formation and organic matter attached during patterning. As a result, a film free of organic matter and excess oxygen within the crystal grains and with fewer crystal defects can be formed, resulting in an oxide film with fewer electron traps and excellent conductivity. A further heat treatment step is preferably performed after forming the gate insulating film and before forming the contact holes, or after forming the gate insulating film and the contact holes. The heat treatment step performed after patterning the oxide film is sometimes referred to as the first heat treatment step, and the heat treatment step performed after forming the gate insulating film and before forming the contact holes, or after forming the gate insulating film and the contact holes, is sometimes referred to as the second heat treatment step. The second heat treatment step is preferably performed at a higher annealing temperature than the first heat treatment step. Annealing after gate insulating film formation allows hydrogen contained in the gate insulating film to diffuse into the oxide film, terminating crystal defects present on the surface of the oxide film with hydroxyl groups, resulting in the formation of an oxide film with fewer electron traps and excellent conductivity.

[0094] According to the method for manufacturing a crystalline oxide film of this embodiment, it is possible to obtain a crystalline oxide film having the above-mentioned characteristics. Furthermore, TFTs having a crystalline oxide film formed by the method for manufacturing a crystalline oxide film of this embodiment have small variations in the characteristics of each TFT even when multiple TFTs are formed on a large substrate, and good in-plane uniformity can be obtained.

[0095] 3. Laminate The crystalline oxide film according to this embodiment can be used as a laminate. The laminate according to this embodiment includes the crystalline oxide film according to this embodiment and a support that supports the crystalline oxide film. FIG. 1 shows a schematic cross-sectional view of a laminate 10 as an example of this embodiment. The laminate 10 includes a crystalline oxide film 11 and a support 12 that supports the crystalline oxide film 11. In the laminate 10, the average grain boundary angle θsub formed between the surface of the support 12 and the grain boundaries in the crystalline oxide film 11 is 70° to 110°, and the average spacing D between the grain boundaries in the crystalline oxide film 11 is 110° to 110°. ２ The average grain boundary angle θsub between the surface of the support 12 and the grain boundaries in the crystalline oxide film 11 and the average spacing D between the grain boundaries are preferably 0.01 to 0.5 μm. ２ However, by satisfying the above range, it is possible to make the crystal grain boundaries densely present on the surface of the support 12 with which the crystalline oxide film 11 is in contact. As a result, when the crystalline oxide film 11 is in contact with an electrode (e.g., a source electrode) serving as a support, the crystal grain boundaries are densely present on the electrode surface. As a result, even when the contact area with the electrode is narrow (e.g., in a small TFT), electron injection into the crystalline oxide film can be ensured, and a decrease in mobility can be suppressed.

[0096] 4. Thin Film Transistor and Electronic Device The thin film transistor (TFT) according to this embodiment has electrodes, a crystalline oxide film, and an insulating film. The electrodes include a source electrode, a drain electrode, and a gate electrode, and the insulating film includes a gate insulating film and a protective film.

[0097] In the thin film transistor according to this embodiment, the crystalline oxide film is preferably the crystalline oxide film according to this embodiment.

[0098] The thin film transistor according to this embodiment preferably includes a source electrode, a drain electrode, a gate electrode, a gate insulating film, a protective insulating film, and an oxide semiconductor layer. The oxide semiconductor layer is located between the gate insulating film and the protective insulating film. The oxide semiconductor layer includes the crystalline oxide film according to this embodiment.

[0099] The TFT according to this embodiment may have, for example, a conventionally known structure.

[0100] The TFT according to this embodiment can be manufactured by employing the method for manufacturing a crystalline oxide film according to this embodiment. Specifically, the manufacturing method includes a step of forming an oxide film by sputtering using the sputtering target according to this embodiment and one or more gases selected from the group consisting of argon, oxygen, hydrogen, water vapor, and nitrogen, which are substantially free of impurity gases, as a sputtering gas (sometimes referred to as a film formation step), and a step of subjecting the oxide film to a heat treatment (sometimes referred to as a heat treatment step). The conditions for the film formation step and the heat treatment step are as described above. The source electrode, drain electrode, gate electrode, and gate insulating film can be formed using known materials and methods.

[0101] By using the crystalline oxide film according to this embodiment in the oxide semiconductor layer (channel layer) of a TFT, high mobility and stable control of the threshold voltage are possible. The mobility here is the mobility when Vg = 0.1 V is applied, and is calculated as linear mobility. Furthermore, the mobility when Vg = 10 V or Vg = 20 V is defined as saturated mobility. Specifically, these mobilities can be calculated by creating a transfer characteristic Id-Vg graph when each Vd is applied, calculating the transconductance (Gm) for each Vg, and calculating the mobility using the equation for the linear region or saturation region. The current Id is the current between the source and drain electrodes, the voltage Vd is the voltage applied between the source electrode and the drain electrode (drain voltage), and the voltage Vg is the voltage applied between the source electrode and the gate electrode (gate voltage). The linear mobility is 17 cm ２ / (V·s) or more is preferable, and 19 cm ２ It is more preferable that the resistance be / (V·s) or more.

[0102] Furthermore, the crystalline oxide film according to this embodiment can also be used to configure a Schottky barrier diode or a MES-FET by arranging an ohmic electrode of metal, ITO, IZO, or the like on one surface thereof and a Schottky electrode such as a metal or oxide electrode having a work function of 4.8 eV or more on the other surface thereof.

[0103] Furthermore, as will be described in detail later in the Examples, it has been revealed for the first time in this specification that thin-film transistors having a crystalline oxide film have superior voltage resistance characteristics compared to thin-film transistors having an amorphous oxide film. More specifically, thin-film transistors having a crystalline oxide film show only small changes in transistor characteristics such as mobility (e.g., saturation mobility) and S value even when a gate voltage with a large absolute value or a high drain voltage is applied.

[0104] Therefore, in the TFT according to this embodiment, the change in threshold voltage measured by the following measurement method before and after holding a gate voltage of +40 V at 80° C. for 7,200 seconds may be, for example, within a range of −3 to +3 V (preferably −2 to +2 V, more preferably −1.5 to +1.5 V, even more preferably −1 to +1 V, and more preferably −0.5 to +0.5 V). (Measurement Method) While applying a drain voltage (Vd) of +20 V, the gate voltage (Vg) is changed from −40 V to +40 V and the current value Id is measured in 0.2 V steps to obtain the Id-Vg characteristic. Current value Id=10 －１０ The value of the gate voltage (Vg) at [A] is defined as the threshold voltage (Vth).

[0105] Furthermore, in the TFT according to this embodiment, the ratio (Id_after / Id_before) of the drain current value (Id_before) when the gate voltage (Vg) is +5 V in an Id-Vg curve obtained by measuring the current value Id while applying a drain voltage (Vd) of +0.1 V and varying the gate voltage (Vg) from −15 V to +15 V in 0.2 V steps, to the drain current value (Id_after) when the gate voltage (Vg) is +5 V in an Id-Vg curve obtained under the same conditions as above after measuring the drain current value (Id_before), and then applying a drain voltage (Vd) of +50 V and a gate voltage (Vg) of +5 V at 25° C. for 1 second, may be, for example, 0.4 or more (preferably in the range of 0.4 to 1.5, more preferably 0.4 to 1.0, and even more preferably 0.5 to 1.0).

[0106] Furthermore, in the TFT according to this embodiment, the ratio (Id_after / Id_before) of the drain current value (Id_before) when the gate voltage (Vg) is +5 V in an Id-Vg curve obtained by measuring the current value Id while applying a drain voltage (Vd) of +0.1 V and varying the gate voltage (Vg) from −15 V to +15 V in 0.2 V steps, to the drain current value (Id_after) when the gate voltage (Vg) is +5 V in an Id-Vg curve obtained under the same conditions as above after measuring the drain current value (Id_before), and then applying a drain voltage (Vd) of +53 V and a gate voltage (Vg) of +5 V at 25° C. for 1 second, may be, for example, 0.4 or more (preferably in the range of 0.4 to 1.5, more preferably 0.4 to 1.0, and even more preferably 0.5 to 1.0).

[0107] Since a thin film transistor having a crystalline oxide film has superior voltage resistance characteristics compared to a thin film transistor having an amorphous oxide film, a TFT having the above-mentioned voltage resistance characteristics may have, as the crystalline oxide film, the above-mentioned crystalline oxide film containing In as a main component, at least two selected from the group consisting of Ga, Al, and Y, and at least one selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, or may have a crystalline oxide film other than the above-mentioned crystalline oxide film containing In as a main component, at least two selected from the group consisting of Ga, Al, and Y, and at least one selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt. Other examples of the crystalline oxide film include a crystalline oxide film containing In as a main component, a crystalline oxide film containing In and Ga as main components, and a crystalline oxide film according to the above-described embodiment that does not contain Ce, Tb, Nd, Mn, Ru, Pd, or Pt, or does not contain at least one of Al and Y.

[0108] Therefore, the present embodiment provides a use of a crystalline oxide film containing In as a main component for a thin film transistor having excellent voltage resistance characteristics, and also provides a use of a crystalline oxide film containing In as a main component for a thin film transistor having the above-mentioned voltage resistance characteristics. In this use, the crystalline oxide film may contain Ga in addition to In, or may contain at least two elements selected from the group consisting of Ga, Al, and Y, or may contain at least two elements selected from the group consisting of Ga, Al, and Y and at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt.

[0109] The shape of the thin film transistor according to this embodiment is not particularly limited, but a back channel etch type transistor, an etch stopper type transistor, a top gate type transistor, or the like is preferred.

[0110] Hereinafter, embodiments will be described with reference to the drawings, etc. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0111] Specific examples of thin film transistors are shown in Figures 3, 4, 5, and 6. As shown in Figure 3, a thin film transistor 100 includes a silicon wafer 20, a gate insulating film 30, an oxide film 40, a source electrode 50, a drain electrode 60, and interlayer insulating films 70 and 70A.

[0112] The silicon wafer 20 is a gate electrode, and is provided on the gate insulating film 30 so as to face the oxide film 40 with the gate insulating film 30 sandwiched therebetween. The gate insulating film 30 is an insulating film that blocks electrical conduction between the gate electrode and the oxide film 40, and is provided on the silicon wafer 20 and on one surface of the oxide film 40. The oxide film 40 is a channel layer, and is provided on the gate insulating film 30. The crystalline oxide film according to this embodiment is used for the oxide film 40. In this embodiment, when the thin film transistor 100 is a small TFT, the oxide film 40 serving as a channel layer for the source electrode 50 and the drain electrode 60 typically has a channel length (L length) of 1 to 50 μm and a channel width (W length) of 1 to 80 μm.

[0113] The source electrode 50 and the drain electrode 60 are conductive terminals for passing source current and drain current through the oxide film 40, and are provided so as to be in contact with the vicinity of both ends of the oxide film 40, and are electrically connected to the oxide film 40. The interlayer insulating film 70 is an insulating film that blocks conduction between the source electrode 50 and the drain electrode 60 and the oxide film 40 except at their contact portions. The interlayer insulating film 70A is an insulating film that blocks conduction between the source electrode 50 and the drain electrode 60 and the oxide film 40 except at their contact portions. The interlayer insulating film 70A also serves as an insulating film that blocks conduction between the source electrode 50 and the drain electrode 60. The interlayer insulating film 70A also serves as a channel layer protective layer.

[0114] 4, the structure of the thin-film transistor 100A is similar to that of the thin-film transistor 100, but differs from the thin-film transistor 100 in that the source electrode 50 and the drain electrode 60 are provided so as to be in contact with both the gate insulating film 30 and the oxide film 40. The thin-film transistor 100A also differs from the thin-film transistor 100 in that an interlayer insulating film 70B is provided integrally so as to cover the gate insulating film 30, the oxide film 40, the source electrode 50, and the drain electrode 60.

[0115] There are no particular limitations on the materials forming the drain electrode 60, the source electrode 50, and the gate electrode, and any commonly used material can be selected. In the examples shown in Figures 3 and 4, a silicon wafer is used as the substrate, and the silicon wafer also functions as the electrode, but the electrode material is not limited to silicon. For example, indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, and SnO ２ 3 and 4, a gate electrode may be formed on a substrate such as glass.

[0116] There is no particular limitation on the material for forming the interlayer insulating films 70, 70A, and 70B, and any commonly used material can be selected. Specific examples of the material for forming the interlayer insulating films 70, 70A, and 70B include SiO. ２ , SiN ｘ , Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO ２ , CeO ２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y ２ O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa２ O ６ , SrTiO ３ , Sm ２ O ３ Compounds such as GaN and AlN can be used.

[0117] When the thin film transistor according to this embodiment is a back channel etch type (bottom gate type), it is preferable to provide a protective film on the drain electrode, the source electrode, and the channel layer. By providing a protective film, the durability of the TFT is likely to be improved even when driven for a long time. In the case of a top gate type TFT, for example, it is more preferable to form a gate insulating film on the channel layer and to provide an interlayer insulating film on the drain electrode and the source electrode.

[0118] When the thin-film transistor according to this embodiment is a top-gate TFT, for example, it has a structure in which an interlayer insulating film is formed as a buffer layer on a substrate and a gate insulating film is formed on a channel layer. As shown in FIG. 5 , the thin-film transistor 100B includes a substrate 21, a buffer layer 22, a channel layer (oxide film) 11, a first low-resistance region 11A-1, a second low-resistance region 11A-2 (oxide film), a semiconductor region 11B (oxide film), a gate insulating film 24, a gate electrode 25, an interlayer insulating film 26, a source electrode 27, a drain electrode 28, and a protective film 29. In the thin-film transistor 100B, the first low-resistance region 11A-1 and the second low-resistance region 11A-2 are formed, for example, by ion implantation or a dry process such as plasma treatment. An electrode layer may also be provided between the substrate 21 and the buffer layer 22 as a write shield layer. The channel layer 11 is formed using the crystalline oxide film according to this embodiment.

[0119] 6 shows another example of a top-gate thin-film transistor according to the present embodiment. The thin-film transistor 100C has a similar structure to the thin-film transistor 100B, except that the interlayer insulating film 26 has a two-layer structure (a first interlayer insulating film 26-1 and a second interlayer insulating film 26-2). In the thin-film transistor 100C, the first low-resistance region 11A-1 and the second low-resistance region 11A-2 are formed by, for example, ion implantation.

[0120] The method for producing the protective film or insulating film is not particularly limited. Examples of the production method include PE-CVD, ALD, PLD, MO-CVD, RF sputtering, ICP sputtering, reactive sputtering, ICP-CVD, ion plating, the sol-gel method, the coating method, and mist CVD. The gas species used in PE-CVD include silane (SiH ４ Besides, tetraethoxysilane (TEOS) can also be used.

[0121] For example, when forming the gate insulating film by PE-CVD, the process may require high temperatures. Furthermore, since the protective film or insulating film often contains impurity gases immediately after film formation, it is preferable to perform a heat treatment (annealing treatment). Removing the impurity gases through the heat treatment results in a stable protective film or insulating film, facilitating the formation of highly durable TFT elements. Furthermore, by performing annealing after the formation of the gate insulating film, hydrogen contained in the gate insulating film diffuses into the oxide film, terminating crystal defects present on the surface of the oxide film with hydroxyl groups, resulting in the formation of an oxide film with few electron traps and good conductivity.

[0122] By using the oxide film according to this embodiment, the film is less susceptible to the effects of temperature in the PE-CVD process and subsequent heat treatment, and therefore the stability of TFT characteristics can be improved even when a protective film or insulating film is formed.

[0123] The threshold voltage (Vth) is preferably −3.0 to 3.0 V, more preferably −2.0 to 2.0 V, and even more preferably −1.0 to 1.0 V. When the threshold voltage (Vth) is −3.0 to 3.0 V, a Vth correction circuit can be installed in the TFT to correct Vth to 0 V. When the TFT thus obtained is installed in a panel, it is possible to drive a display without uneven brightness or burn-in.

[0124] The threshold voltage (Vth) is Id = 10 －１０ The on-off ratio is preferably 10 ６ ~10 １２ and more preferably 10 ７~10 １１ and more preferably 10 ８ ~10 １０ The on-off ratio is 10 ６ If the on-off ratio is 10 or more, the liquid crystal display can be driven. １２ When the on-off ratio is 10 or less, an organic EL element with high contrast can be driven. １２ If the off-state current is 10 －１２ A or less, and when used in the transfer transistor or reset transistor of a CMOS image sensor, it is possible to extend the image retention time and improve the sensitivity.

[0125] The on-off ratio is determined by determining the ratio [on current value / off current value], where the value of Id when Vg = -10 V is the off current value and the value of Id when Vg = 20 V is the on current value. －１０ A or less is preferable, and 10 －１１ A or less is more preferable, and 10 －１２ A or less is more preferable. －１０ When the resistance is A or less, it is possible to drive an organic EL device with high contrast. Furthermore, when used in the transfer transistor or reset transistor of a CMOS image sensor, it is possible to extend the image retention time and improve the sensitivity.

[0126] <Quantum Tunnel Field Effect Transistor> The crystalline oxide film according to this embodiment can also be used in a quantum tunnel field effect transistor (FET).

[0127] 7 is a schematic diagram (longitudinal cross-sectional view) of a quantum tunnel field effect transistor (FET) according to this embodiment. The quantum tunnel field effect transistor 501 includes a p-type semiconductor layer 503, an n-type semiconductor layer 507, a gate insulating film 509, a gate electrode 511, a source electrode 513, and a drain electrode 515.

[0128] The p-type semiconductor layer 503, the n-type semiconductor layer 507, the gate insulating film 509, and the gate electrode 511 are stacked in this order. The source electrode 513 is provided on the p-type semiconductor layer 503. The drain electrode 515 is provided on the n-type semiconductor layer 507. The p-type semiconductor layer 503 is a p-type Group IV semiconductor layer, and in this case is a p-type silicon layer. The n-type semiconductor layer 507 is an n-type oxide film used in the image sensor according to this embodiment. The source electrode 513 and the drain electrode 515 are conductive films.

[0129] 7, an insulating layer may be formed on the p-type semiconductor layer 503. In this case, the p-type semiconductor layer 503 and the n-type semiconductor layer 507 are connected via a contact hole, which is a region where the insulating layer is partially opened. Although not shown in FIG. 7, the quantum tunnel field effect transistor 501 may also have an interlayer insulating film covering its upper surface.

[0130] The quantum tunnel field effect transistor 501 is a quantum tunnel field effect transistor (FET) that performs current switching by controlling the current tunneling through an energy barrier formed by a p-type semiconductor layer 503 and an n-type semiconductor layer 507 using the voltage of a gate electrode 511. In this structure, the band gap of the oxide semiconductor that constitutes the n-type semiconductor layer 507 is large, and the off-current can be reduced.

[0131] FIG. 8 shows a schematic diagram (longitudinal cross-sectional view) of a quantum tunnel field-effect transistor 501A according to another embodiment. The quantum tunnel field-effect transistor 501A has the same configuration as the quantum tunnel field-effect transistor 501, except that a silicon oxide layer 505 is formed between a p-type semiconductor layer 503 and an n-type semiconductor layer 507. The presence of the silicon oxide layer reduces the off-state current. The thickness of the silicon oxide layer 505 is preferably 10 nm or less. A thickness of 10 nm or less can prevent tunneling current from flowing, energy barriers from being formed, and changes in barrier height, thereby preventing a decrease or change in the tunneling current. The thickness is preferably 8 nm or less, more preferably 5 nm or less, even more preferably 3 nm or less, and even more preferably 1 nm or less. FIG. 9 shows a TEM photograph of a portion where the silicon oxide layer 505 is formed between the p-type semiconductor layer 503 and the n-type semiconductor layer 507.

[0132] In the quantum tunnel field effect transistors 501 and 501A, the n-type semiconductor layer 507 is also an n-type oxide semiconductor.

[0133] The oxide semiconductor constituting the n-type semiconductor layer 507 may be amorphous. Being amorphous allows etching with an organic acid such as oxalic acid, which increases the difference in etching rate with other layers and allows for satisfactory etching without affecting metal layers such as wiring.

[0134] The oxide semiconductor constituting the n-type semiconductor layer 507 may be crystalline. When the oxide semiconductor constituting the n-type semiconductor layer 507 is crystalline, the band gap becomes larger than in the case of an amorphous material, and the off-current can be reduced. Since the work function can also be increased, it becomes easier to control the current tunneling through the energy barrier formed by the p-type Group IV semiconductor material and the n-type semiconductor layer 507.

[0135] The method for manufacturing the quantum tunnel field effect transistor 501 is not particularly limited, but the following method can be exemplified. First, as shown in Fig. 10A, an insulating film 505A is formed on a p-type semiconductor layer 503, and a part of the insulating film 505A is opened by etching or the like to form a contact hole 505B. Next, as shown in Fig. 10B, an n-type semiconductor layer 507 is formed on the p-type semiconductor layer 503 and the insulating film 505A. At this time, the p-type semiconductor layer 503 and the n-type semiconductor layer 507 are connected via the contact hole 505B.

[0136] 10C, a gate insulating film 509 and a gate electrode 511 are formed in this order on the n-type semiconductor layer 507. Next, as shown in Fig. 10D, an interlayer insulating film 519 is provided so as to cover the insulating film 505A, the n-type semiconductor layer 507, the gate insulating film 509, and the gate electrode 511.

[0137] 10E, a contact hole 519A is formed by opening a portion of the insulating film 505A and interlayer insulating film 519 on the p-type semiconductor layer 503, and a source electrode 513 is provided in the contact hole 519A. Furthermore, as shown in FIG. 10E, a contact hole 519B is formed by opening a portion of the gate insulating film 509 and interlayer insulating film 519 on the n-type semiconductor layer 507, and a drain electrode 515 is formed in the contact hole 519B. By the above procedure, the quantum tunnel field effect transistor 501 can be manufactured.

[0138] After forming n-type semiconductor layer 507 on p-type semiconductor layer 503, heat treatment is performed at a temperature of 150° C. or higher and 600° C. or lower, thereby forming silicon oxide layer 505 between p-type semiconductor layer 503 and n-type semiconductor layer 507. By adding this step, quantum tunnel field effect transistor 501A can be manufactured.

[0139] The TFT according to this embodiment can be suitably used in solar cells, liquid crystal devices, organic electroluminescence devices, inorganic electroluminescence devices, display devices such as electronic paper, power semiconductor devices, touch panels, and other electronic devices.

[0140] The thin-film transistor according to this embodiment can be applied to various integrated circuits such as field-effect transistors, logic circuits, memory circuits, and differential amplifier circuits, and these can be applied to electronic devices, etc. Furthermore, the thin-film transistor according to this embodiment can also be applied to static induction transistors and Schottky barrier transistors in addition to field-effect transistors. The thin-film transistor according to this embodiment can be suitably used in display devices such as portable or in-vehicle display devices and solid-state imaging devices. Furthermore, the thin-film transistor according to this embodiment can also be suitably used as a transistor for flat panel detectors for X-ray image sensors in medical applications. Furthermore, the crystalline oxide film according to this embodiment can also be applied to Schottky diodes, resistance change memory, and resistor elements. Below, the use of the thin-film transistor according to this embodiment in display devices and solid-state imaging devices will be described.

[0141] First, a case where the thin film transistor according to this embodiment is used in a display device will be described with reference to Fig. 11. Fig. 11A is a top view of the display device according to this embodiment. Fig. 11B is a circuit diagram for explaining the circuit of the pixel portion when a liquid crystal element is applied to the pixel portion of the display device according to this embodiment. Fig. 11C is a circuit diagram for explaining the circuit of the pixel portion when an organic EL element is applied to the pixel portion of the display device according to this embodiment.

[0142] The thin film transistor according to this embodiment can be used as a transistor disposed in a pixel portion. Since the thin film transistor according to this embodiment can be easily made into an n-channel type, part of a driver circuit that can be configured with an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. By using the thin film transistor described in this embodiment for the pixel portion or the driver circuit, a highly reliable display device can be provided.

[0143] 11A shows an example of a top view of an active matrix display device. A pixel portion 301, a first scanning line driver circuit 302, a second scanning line driver circuit 303, and a signal line driver circuit 304 are formed on a substrate 300 of the display device. A plurality of signal lines are arranged in the pixel portion 301, extending from the signal line driver circuit 304, and a plurality of scanning lines are arranged in the pixel portion 301, extending from the first scanning line driver circuit 302 and the second scanning line driver circuit 303. Pixels each having a display element are provided in a matrix at an intersection between the scanning lines and the signal lines. The substrate 300 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0144] 11A, the first scanning line driver circuit 302, the second scanning line driver circuit 303, and the signal line driver circuit 304 are formed on the same substrate 300 as the pixel portion 301. Therefore, the number of components such as driver circuits provided externally is reduced, which can reduce costs. Furthermore, if the driver circuits are provided externally to the substrate 300, it becomes necessary to extend the wiring, which increases the number of connections between the wiring. If the driver circuits are provided on the same substrate 300, the number of connections between the wiring can be reduced, which can improve reliability or yield.

[0145] 11B shows an example of a pixel circuit configuration, which is applicable to the pixel portion of a VA-type liquid crystal display device.

[0146] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrodes. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. This allows the signals applied to each pixel electrode of a multi-domain pixel to be controlled independently.

[0147] The gate wiring 312 of the transistor 316 and the gate wiring 313 of the transistor 317 are separated so as to receive different gate signals. On the other hand, the source or drain electrode 314 functioning as a data line is used in common by the transistors 316 and 317. The transistors according to this embodiment can be used for the transistors 316 and 317. This makes it possible to provide a highly reliable liquid crystal display device.

[0148] The transistor 316 is electrically connected to a first pixel electrode, and the transistor 317 is electrically connected to a second pixel electrode. The first pixel electrode and the second pixel electrode are separated from each other. The shapes of the first pixel electrode and the second pixel electrode are not particularly limited. For example, the first pixel electrode may be V-shaped.

[0149] The gate electrode of the transistor 316 is connected to the gate wiring 312, and the gate electrode of the transistor 317 is connected to the gate wiring 313. By applying different gate signals to the gate wiring 312 and the gate wiring 313, the operation timing of the transistors 316 and 317 can be made different, thereby controlling the alignment of the liquid crystal.

[0150] Furthermore, a storage capacitor may be formed by the capacitor wiring 310, a gate insulating film that functions as a dielectric, and a capacitor electrode that is electrically connected to the first pixel electrode or the second pixel electrode.

[0151] The multi-domain structure has one pixel having a first liquid crystal element 318 and a second liquid crystal element 319. The first liquid crystal element 318 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween, and the second liquid crystal element 319 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

[0152] The pixel portion is not limited to the configuration shown in Fig. 11B. A switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit may be added to the pixel portion shown in Fig. 11B.

[0153] Another example of the circuit configuration of a pixel is shown in Fig. 11C, which shows the structure of a pixel portion of a display device using an organic EL element.

[0154] 11C is a diagram showing an example of an applicable circuit for the pixel section 320. Here, an example is shown in which two n-channel transistors are used in one pixel. The crystalline oxide film according to this embodiment can be used in the channel formation region of the n-channel transistor. Digital time grayscale driving can be applied to the circuit for the pixel section.

[0155] The thin film transistor according to this embodiment can be used for the switching transistor 321 and the driving transistor 322. This makes it possible to provide a highly reliable organic EL display device.

[0156] The configuration of the circuit of the pixel portion is not limited to the configuration shown in Figure 11C. A switch, a resistive element, a capacitive element, a sensor, a transistor, or a logic circuit may be added to the circuit of the pixel portion shown in Figure 11C. Furthermore, in a display device using the thin film transistor according to this embodiment, both a Si-based transistor and the crystalline oxide transistor of this embodiment may be mounted. The above is a description of the case where the thin film transistor according to this embodiment is used in a display device.

[0157] Next, a case where the thin film transistor according to this embodiment is used in a solid-state imaging device will be described with reference to FIG.

[0158] A CMOS (Complementary Metal Oxide Semiconductor) image sensor is a solid-state imaging device that holds a potential in a signal charge storage section and outputs that potential to a vertical output line via an amplification transistor. If a leak current occurs in the reset transistor and / or transfer transistor included in the CMOS image sensor, the leak current causes charging or discharging, changing the potential of the signal charge storage section. When the potential of the signal charge storage section changes, the potential of the amplification transistor also changes, resulting in a value that deviates from the original potential, degrading the captured image.

[0159] The operational effect when the thin film transistor according to this embodiment is applied to the reset transistor and transfer transistor of a CMOS image sensor will be described below. Either a thin film transistor or a bulk transistor may be applied to the amplifying transistor.

[0160] 12 is a diagram showing an example of the pixel configuration of a CMOS image sensor. A pixel is composed of a photodiode 3002, which is a photoelectric conversion element, a transfer transistor 3004, a reset transistor 3006, an amplifier transistor 3008, and various wirings, and a plurality of pixels are arranged in a matrix to form a sensor. A selection transistor electrically connected to the amplifier transistor 3008 may be provided. The transistor symbols "OS" and "Si" represent oxide semiconductor and silicon, respectively, and represent materials that are preferable for use in the respective transistors. This also applies to the subsequent drawings.

[0161] The photodiode 3002 is connected to the source side of the transfer transistor 3004, and a signal charge storage region 3010 (also called a floating diffusion (FD)) is formed on the drain side of the transfer transistor 3004. The source of the reset transistor 3006 and the gate of the amplification transistor 3008 are connected to the signal charge storage region 3010. As an alternative configuration, the reset power supply line 3110 can be eliminated. For example, the drain of the reset transistor 3006 can be connected to the power supply line 3100 or the vertical output line 3120 instead of the reset power supply line 3110. Note that the crystalline oxide film according to this embodiment may be used for the photodiode 3002, and the same material as the oxide semiconductor film used for the transfer transistor 3004 and the reset transistor 3006 may be used. The above is a description of the case where the thin film transistor according to this embodiment is used in a solid-state imaging element.

[0162] The present embodiment will be described in more detail below with reference to examples, but the present embodiment is not limited to the following examples.

[0163] Various measurements were carried out as follows.

[0164] (Atomic Ratio (at%) of Crystalline Oxide (TEM-EDS Method)) The content (atomic ratio) of each metal element in the crystalline oxide thin film in the TFT element was analyzed by TEM-EDS using a JEM-ARM200F DualX (TEM, JEOL Ltd.) and a JED-2300 Analysis Station Plus (EDS, JEOL Ltd.). Specifically, first, an ion beam was applied using a focused ion beam (FIB) in the direction perpendicular to the film surface of the area where the crystalline oxide film of the TFT element was patterned, and a test piece was sampled. Then, the sampled test piece was subjected to Ar ion milling using a PIPS691 (Gatan Corporation) until the thickness of the flake was approximately 100 nm in the channel width direction perpendicular to the channel length and film thickness directions, and the thickness of the extracted sample was reduced. Using the processed sample, EDS point analysis was performed at an acceleration voltage of 80 kV and a beam spot size of approximately 0.15 nm in the region of the crystalline oxide film where the source electrode and drain electrode did not overlap with the crystalline oxide film and where the crystalline oxide film was located directly under the gate electrode, and the content (atomic ratio) of each metal element was analyzed. The EDS analysis was limited to the bulk (center in the film thickness direction) region of the crystalline oxide, and at least 15 points were obtained in the channel length direction, and the average value was used as the content (atomic ratio) of the metal element. Note that the amount of silicon element was not included in the total metal elements contained in the crystalline oxide film, and the content of each metal was calculated.

[0165] (Carrier Concentration) An oxide semiconductor thin film was formed on a glass substrate in the same manner as in "(1) Formation of oxide semiconductor thin film" in <Production of TFT>, and then heat treatment was carried out in the same manner as in "(3) Heat Treatment". The obtained sample crystalline oxide film was cut into 1 cm square pieces, and electrodes were attached to the four corners using In solder to form a Hall effect measurement element, and the carrier concentration was measured. The carrier concentration was determined by measuring the AC Hall effect at room temperature using a ResiTest 8400 model (manufactured by Toyo Corporation). The measurement conditions were as follows. For measurement accuracy, the value of the electron carrier concentration was adopted when the F value was 0.9 or more and the absolute value of the Hall voltage phase was 170° to 180°. Current value: 1×10－１２ ~1 x 10 －３ A Magnetic field strength: 0.36T

[0166] (Method for measuring the crystalline state of the cross section of a crystalline oxide film using a cross-sectional TEM) The crystalline state of the cross section of the crystalline oxide film in a TFT element was measured by pretreating the oxide thin film using a focused ion beam (FIB) device and observing the cross section of the pretreated oxide thin film using a transmission electron microscope (TEM). Specifically, an ion beam was first applied perpendicularly to the film surface of the patterned area of ​​the crystalline oxide film of the TFT element using an FIB (Hitachi High-Technologies Corporation "FB2100 type") device, and a test piece measuring 16 μm × 4 μm was sampled. Then, two samples were extracted from the sampled test piece in a 3 μm area extending from the end of the area where the source electrode or drain electrode and the oxide film overlap toward the area where they do not overlap in the channel length direction. The two extracted samples were then subjected to Ar ion milling until the thickness of the flakes reached approximately 100 nm in the channel width direction perpendicular to the channel length and film thickness directions, thereby thinning the two samples. When crystal grains could not be confirmed due to ion sputter damage during FIB processing, Ar ion milling (Gatan "Model 691") was performed using an ion gun voltage of 4 keV, and etching was repeated until crystal grains could be confirmed. Cross-sectional TEM images were taken using a transmission electron microscope (JEOL "JEM-2800") at an acceleration voltage of 200 kV, with observation magnifications of 200,000x (approximately 4 μm square area), 500,000x (approximately 800 nm square area), 2,000,000x (approximately 200 nm square area), and 10,000,000x (approximately 40 nm square area).

[0167] (Method for determining whether a sample is amorphous or crystalline by electron diffraction) The amorphous / crystalline state was determined by observing the electron diffraction pattern of a sample obtained by observing a cross-sectional TEM image. Specifically, using an electron microscope (JEOL Ltd., "JEM-2800 model"), the oxide film area observed in the cross-sectional TEM image was irradiated with an electron beam using a selected area aperture at an irradiation area of ​​approximately 100 nmφ and an acceleration voltage of 200 kV, and the camera length was set to 2 m to measure the diffraction pattern. An oxide film in which no clear diffraction spot was obtained in any three fields of view selected so that the observation points did not overlap in the L length direction of the cross-sectional TEM image sample was determined to be "amorphous." On the other hand, an oxide film in which a diffraction spot was observed was determined to be "crystalline."

[0168] (Crystallinity: Identification of crystal structure by electron beam diffraction) Whether the crystal structure of the oxide film is a bixbyite structure was evaluated by observing the electron beam diffraction pattern of the sample obtained by observing a cross-sectional TEM image. Specifically, using an electron microscope (JEOL Ltd. "JEM-2800 type"), the oxide film area observed in the cross-sectional TEM image was irradiated with an electron beam using a selected area aperture at an irradiation area of ​​approximately 100 nmφ and an acceleration voltage of 200 kV, and the camera length was set to 2 m to measure the diffraction pattern. Furthermore, to identify the crystal structure, electron beam diffraction simulation software ReciPro (free software ver. 4.641 (2019 / 03 / 04)) was used to measure the In ２ O ３A simulation of the electron diffraction pattern of the bixbyite structure was carried out. In the simulation, the crystal structure data of the bixbyite structure was 14388 from the Inorganic Crystal Structure Database (ICSD: Chemical Information Association), with a space group of Ia-3, a lattice constant of a = 10.17700 Å, and atomic coordinates of In site (0.250, 0.250, 0.250), In site (0.466, 0.000, 0.250), and O site (0.391, 0.156, 0.380). Furthermore, with a camera length of 2 mm, simulations were performed with 11 types of reciprocal lattice vectors (100), (111), (110), (211), (311), (221), (331), (210), (310), (321), and (230) as the incident electron beam directions. The electron diffraction pattern of the oxide film was compared with the diffraction spot results for the obtained simulation pattern, and if it matched any of the 11 types of simulation patterns, it was determined that the oxide film contained crystal grains with a bixbyite structure.

[0169] (Method for measuring the crystalline state of an oxide film using a planar TEM) The crystalline state of an oxide film in a TFT element viewed from a direction perpendicular to the film surface was measured by pretreating the film surface of the oxide film using a focused ion beam (FIB) device, and observing the pretreated film surface using a transmission electron microscope (TEM). Specifically, an ion beam was first applied using an FIB ("FB2100" manufactured by Hitachi High-Technologies Corporation) device in a direction parallel to the film surface in an area where the oxide semiconductor thin film of the TFT element was patterned, and a test piece measuring 12 μm × 4 μm was sampled. Then, for the sampled test piece, three 2 μm square (2 μm × 2 μm) areas (samples) were extracted in the channel direction from the edge of the area where the source electrode or drain electrode and the oxide film overlap toward the area where they do not overlap, and the three extracted areas were irradiated with a gallium ion beam until the thickness of the thin piece was approximately 100 nm, thereby thinning the thickness of the sample (the three extracted areas). Planar TEM images were observed using a transmission electron microscope (JEOL Ltd., "JEM-2800 model") at an acceleration voltage of 200 kV, and the magnification was increased until five or more crystal grains could be observed in each.

[0170] (Average grain size D １ ) Average crystal grain size D when observed from the film thickness direction of the oxide film １ The average crystal grain diameter D can be calculated by analyzing the diameter of the crystal grains observed by a planar TEM at a magnification of 200,000 times for three samples. The planar TEM images are analyzed using "SPIP, Version 4.3.2.0" manufactured by Image Metrology, Inc. １was calculated. For the planar TEM image, lines with color codes H0, S0, and V10 were drawn at the grain boundaries. Furthermore, image analysis software was used to quantify the contrast, and a height of (maximum density - minimum density) x 1 / 4 was set as the threshold. Next, regions showing a contrast equal to or greater than the threshold were defined as crystal grains, and the area of ​​each grain was calculated. The total area of ​​each particle obtained was calculated, and the resulting area was divided by the number of particles measured to obtain the average particle area S １ Furthermore, assuming that the crystal grains are circular, the average grain area S １ The diameter was calculated by the formula (A) and the average value of the average crystal grain size of the crystal grains was calculated. １ It was decided.

[0171]

[0172] (Band Gap) An oxide semiconductor thin film was formed on a quartz substrate in the same manner as in "(1) Formation of oxide semiconductor thin film" in <Production of TFT>, and then heat treatment was carried out in the same manner as in "(3) Heat treatment". The transmission spectrum of the obtained oxide semiconductor thin film was measured using a Shimadzu Corporation self-recording spectrophotometer "UV-3100PC", and the wavelength on the horizontal axis was converted to energy (eV) and the transmittance on the vertical axis was converted to the following formula (1), after which the spectrum was fitted to the part where absorption rises, and the eV value where it intersects with the baseline was calculated to be the band gap. (αhν) 2 ...(1) (In equation (1), α is the absorption coefficient, h is Planck's constant, and v is the frequency.)

[0173] (Metal Element Segregation (Method for Measuring Metal Element Segregation in Oxide Film by Planar TEM-EDS)) The metal dispersion state (metal element segregation) in the oxide film was measured by observing three fields of view of the sample obtained by planar TEM observation using a transmission electron microscope (TEM) / energy dispersive X-ray spectroscopy (EDS). Specifically, using an electron microscope (JEOL Ltd., "JEM-2800"), an observation range containing five or more crystal particles in the oxide film area observed in the planar TEM image was irradiated with an electron beam at an accelerating voltage of 200 kV, and EDS mapping measurement of each element was performed. As a result, when no bias in the metal elements was observed between crystal grains in the mapping of each element, it was judged as "no segregation", and when bias was observed for each crystal grain in the mapping, it was judged as "presence of segregation". The presence or absence of metal bias was judged by performing image analysis on the planar TEM-EDS mapping of each sample and each element using "SPIP, Version 4.3.2.0" manufactured by Image Metrology, Inc., and then digitizing it. Specifically, first, the contrast of each mapping image was digitized and expressed as 265 pixels x 265 pixels. Next, the average concentration I per pixel for the entire field of view was calculated. ａｖｅ Next, the planar TEM image and the planar TEM-EDS mapping are compared, and for five or more crystal grains from each field of view, the average crystal grain size D １ Select an area with a size of 1 / 2 of the square of the selected area. The average density of the selected area is I ｇｒａｉｎ The average density I obtained by such image analysis is calculated. ａｖｅ and area average concentration I ｇｒａｉｎ About I ａｖｅ <I ｇｒａｉｎ When there were two or more areas in one field of view that satisfied the relationship, it was determined that "segregation was present," and when there were fewer than two areas, it was determined that "segregation was not present."

[0174] (TFT Characteristics) The TFT characteristics of the obtained TFT elements were measured at room temperature in a light-shielded environment (inside a shielded box) using a semiconductor parameter analyzer ("B1500" manufactured by Agilent Technologies). A drain voltage (Vd) of 0.1 V was applied. For each Vd applied, the gate voltage (Vg) was changed from -5 V to +20 V in 0.2 V steps to measure the current value Id, thereby obtaining the Id-Vg characteristics. Furthermore, various parameters (maximum linear mobility at Vg = 0 to 20 V, S value, Vth, Vhys) calculated from the Id-Vg characteristics were calculated as follows:

[0175] (Maximum value of linear mobility when Vd = 0.1 V and Vg = 0 to 20 V) To determine the maximum value of linear mobility when Vd = 0.1 V is applied, a graph of Id-Vg characteristics is created, the transconductance (Gm) for each Vg is calculated, and the linear mobility (μlin) is derived using the equation for the linear region. Specifically, Gm is calculated by ∂(Id) / ∂(Vg). Furthermore, μlin is calculated using equation (b) for the linear region. μlin = (Gm L) / (W Ci Vd) ... (b) Furthermore, Ci in equation (b) is the capacitance of the gate insulating film, and is calculated using a 100 nm thick SiO ２ The relative dielectric constant of 3.9 and the dielectric constant of vacuum is 8.85 x 10 －１４ Ci calculated based on [F / cm] = 3.45 × 10 －８ [F / cm ２ In formula (b), L is the channel length (L length), and W is the channel width (W length). Furthermore, the maximum value of μlin at Vg = 0 to 20 V was calculated from each Vg-μlin graph. As a result, the maximum value of linear mobility at Vd = 0.1 V and Vg = 0 to 20 V in Examples 1 to 16 and Comparative Example 1 was 15 cm ２ / (V·s) or more.

[0176] (S value, threshold voltage (Vth) and hysteresis (Vhys)) The S value and threshold voltage (Vth) were evaluated from the graph of each Id-Vg characteristic. Specifically, when the current value Id was 10 －１１ ~10 －１０ In the [A] region, the value obtained by the following formula (d) was calculated as the S value.－１０ The Vg value at [A] was calculated as the threshold voltage (Vth). Furthermore, the difference in threshold voltage between the Id-Vg characteristics obtained by sweeping the gate voltage Vg from −5 V to +20 V in the forward direction and the Id-Vg characteristics obtained by sweeping the gate voltage Vg from +20 V to −5 V in the reverse direction was calculated as the hysteresis (Vhys).

[0177]

[0178] <Production of TFT>

[0179] Example 1 A thin film transistor was manufactured by the following steps. (1) Formation of Oxide Semiconductor Layer A sputtering target obtained from a raw material mixture having the composition ratios shown in Table 1-1 was used. The metal composition ratio (unit: at %) in the oxide sputtering target was calculated from the composition ratio of the raw material mixture and is shown in Table 1-1. Using this oxide sputtering target, a 30 nm thick oxide semiconductor thin film (oxide semiconductor layer) was formed by sputtering on a silicon wafer (gate electrode) with a 100 nm thick thermal oxide film (gate insulating film). The film formation conditions are as shown in Table 2. A mixed gas of high-purity argon and high-purity oxygen (impurity gas concentration: 0.01% by volume) was used as the sputtering gas.

[0180] (2) Semiconductor Patterning Next, the formed oxide semiconductor layer was patterned into islands by photolithography. First, a photoresist film was formed on the oxide semiconductor layer. AZ1500 (manufactured by AZ Electronic Materials) was used as the photoresist. After exposure through a photomask, development was performed using tetramethylammonium hydroxide (TMAH). After development, the oxide semiconductor layer was etched using oxalic acid. After etching, the photoresist was peeled off to obtain a substrate with a patterned oxide film.

[0181] (3) Annealing Next, the substrate with the patterned oxide film was placed in a furnace, and the temperature was raised to 400°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour. After the inside of the furnace was held at 400°C for 1 hour, it was allowed to cool naturally, and after the temperature inside the furnace returned to room temperature, the substrate with the oxide film was taken out of the furnace.

[0182] (4) Etch Stopper Patterning Subsequently, an image reversal resist was spin-coated on the semiconductor patterned surface of the annealed oxide film-coated substrate. AZ5214 (manufactured by AZ Electronic Materials) was used as the image reversal resist. After spin-coating, the resist was exposed through a photomask, and the entire surface of the image reversal resist AZ5214 was exposed after a reversal bake process and developed with TMAH. A 100 nm thick SiO was sputtered onto the patterned resist-coated substrate. ２ The sputtering conditions were as follows: substrate temperature: 25°C, ultimate pressure: 8.5 x 10 －５ Pa Atmospheric gas: Ar + O ２ (O ２ Flow rate 57%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF300W Distance between S (substrate) and T (target): 70 mm Then, SiO ２ The substrate on which the film was formed was lifted off in acetone to obtain SiO ２ was patterned.

[0183] (5) Formation of gate insulating film contact holes. ２ The substrate with the patterned oxide film was exposed to light through a photomask using photoresist AZ1500 (manufactured by AZ Electronic Materials), and then developed with tetramethylammonium hydroxide (TMAH). After development, the silicon wafer with the thermal oxide film was etched with buffered hydrofluoric acid (BHF) to form contact holes for connecting the gate electrodes. After the contact holes were formed, the substrate was annealed in air at 400°C for 1 hour.

[0184] (6) Formation of Source / Drain Electrodes Subsequently, the source / drain electrode layer was patterned by a lift-off process using image reversal resist AZ5214 and a photomask. The image reversal resist AZ5214 was exposed through a photomask, and after a reversal bake process, the entire surface was exposed and developed with TMAH. A Ti layer with a thickness of 150 nm was formed on the substrate with the patterned resist under the following sputtering conditions: Substrate temperature: 25°C Ultimate pressure: 8.5 × 10 －５ Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC 100 W Distance between S (substrate) and T (target): 70 mm Thereafter, the substrate on which the Ti layer was formed was lifted off in acetone to pattern the ohmic electrode layer.

[0185] (7) Final Annealing Finally, annealing was performed in air at 200° C. for 1 hour. The final shape of the obtained device (TFT) was as shown in Table 2 (L length: 14 μm, W length: 20.0 μm, Ls length of each of the source electrode and the drain electrode: 3 μm).

[0186]

[0187]

[0188]

[0189] Examples 2 to 16, Comparative Example 1 TFTs according to Examples 2 to 16 and Comparative Example 1 were produced in the same manner as in Example 1, except that the composition ratios of the sputtering targets were changed as shown in Table 1-1.

[0190] Examples 17 to 26 The TFTs according to Examples 17 to 26 were manufactured as follows.

[0191] The sputtering targets used were obtained from raw material mixtures having the composition ratios shown in Table 1-2. The metal composition ratios (unit: at%) in the oxide sputtering targets were calculated from the composition ratios of the raw material mixtures and are shown in Table 1-2.

[0192] Using the prepared sputtering target, a 50 nm thin film (oxide film 40) was formed via a metal mask on a silicon wafer 20 (gate electrode; see FIG. 14 ) with a thermal oxide film (gate insulating film 30) by sputtering under the film formation conditions shown in Table 4. In this case, sputtering was performed using a mixed gas of high-purity argon and 1% high-purity oxygen as the sputtering gas.

[0193] Next, the formed oxide semiconductor layer (oxide film 40) was patterned into islands by photolithography. First, a photoresist film was formed on the oxide semiconductor layer. AZ1500 (manufactured by AZ Electronic Materials) was used as the photoresist. After exposure through a photomask, development was performed using tetramethylammonium hydroxide (TMAH). After development, the oxide semiconductor layer was etched using oxalic acid. After etching, the photoresist was peeled off to obtain a substrate with a patterned oxide film.

[0194] Next, the substrate with the patterned oxide film was placed in a furnace and annealed under the conditions shown in the "intermediate annealing" column of Table 4.

[0195] Subsequently, an image reversal resist was spin-coated on the semiconductor patterned surface of the annealed oxide film-coated substrate. AZ5214 (manufactured by AZ Electronic Materials) was used as the image reversal resist. After spin-coating, the resist was exposed through a photomask, and the entire surface of the image reversal resist AZ5214 was exposed after a reversal bake process and developed with TMAH. A 100 nm thick SiO was sputtered onto the patterned resist-coated substrate. ２ The sputtering conditions were as follows: substrate temperature: 25°C, ultimate pressure: 8.5 x 10 －５ Pa Atmospheric gas: Ar + O ２ (O ２ Flow rate 57%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF300W Distance between S (substrate) and T (target): 70 mm Then, SiO ２ The substrate on which the film was formed was lifted off in acetone to obtain SiO２ was patterned.

[0196] Furthermore, SiO ２ The substrate with the patterned oxide film was exposed to light through a photomask using photoresist AZ1500 (manufactured by AZ Electronic Materials Co., Ltd.), and then developed with tetramethylammonium hydroxide (TMAH). After development, the silicon wafer with the thermal oxide film was etched with buffered hydrofluoric acid (BHF) to form contact holes for connecting the gate electrodes.

[0197] After the contact holes were formed, annealing was performed under the conditions shown in the "intermediate annealing" column of Table 4.

[0198] Next, titanium metal was sputtered using a metal mask with source and drain contact holes to form titanium electrodes as source and drain electrodes. The resulting laminate was heat-treated under the conditions listed in the "Final Annealing" column in Table 4 to produce a thin-film transistor (TFT) before the formation of a protective insulating film.

[0199] 14 shows cross-sectional views of the TFTs fabricated in Examples 17 to 26. The final shapes of the obtained elements (TFTs) were as shown in Table 4.

[0200] Various physical properties of the examples and comparative examples were measured and are shown in Tables 3-1 and 3-2. The oxide films of the TFTs prepared in the examples and comparative examples were all crystalline.

[0201]

[0202]

[0203]

[0204] For reference, the atomic ratio of Ce in the crystalline oxide film of the TFT fabricated in Example 3 was analyzed by TEM-EDS. As a result, the atomic ratio of Ce was found to be 0.08 at%. It is also empirically known that the composition ratios of In, Al, Ga, and Y in the sintered body of the target and the composition ratios of In, Al, Ga, and Y in the crystalline oxide film generally coincide. From the above, it was confirmed that the method shown in this example produced a crystalline oxide film having a composition ratio of metal elements corresponding to the composition ratio of the sintered body of the target.

[0205] From the results of the above examples and comparative examples, it can be seen that the crystalline oxide film according to this embodiment contains at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, preferably Ce, which causes hysteresis. Furthermore, it can be seen that the hysteresis can be controlled by controlling the content of at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, preferably Ce. Furthermore, it can be seen that the crystalline oxide film according to this embodiment contains at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, preferably Ce, which increases the S value. Furthermore, the crystalline oxide film according to this embodiment contains at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt, preferably Ce, which allows hysteresis to be controlled and a large S value to be obtained, but the maximum linear mobility remains high without a significant decrease.

[0206] [Reference Example] (Production of TFT using crystalline oxide film or amorphous oxide film) In ２ O ３ : Ga ２ O ３ A TFT was manufactured by depositing an amorphous oxide film using a target obtained from a raw material mixture having a composition ratio of ZnO:ZnO = 44.22:29.85:25.93 (mass ratio). The TFT was manufactured using the same process as in Example 1, except that the material composition of the sputtering target was changed. In addition, a TFT using a crystalline oxide film was manufactured using the same method as in Comparative Example 1.

[0207] (Measurement of Withstand Voltage Characteristics) The withstand voltage characteristics of the TFT elements using the crystalline oxide film or amorphous oxide film were evaluated as follows: The obtained TFT elements were measured in a light-shielded environment (in a shielded box) using a semiconductor parameter analyzer ("B1500" manufactured by Agilent).

[0208] First, the withstand voltage characteristics with respect to gate voltage were evaluated. First, a drain voltage (Vd) of +20 V was applied, and the current value Id was measured by varying the gate voltage (Vg) from -40 V to +40 V in 0.2 V increments to obtain the Id-Vg characteristics. Then, the device was maintained at 80°C for 7,200 seconds while applying a gate voltage of +40 V or -40 V, and the Id-Vg characteristics were measured under the aforementioned conditions. The results are shown in Figure 13A. In Figure 13A, the measurement results when a gate voltage of +40 V was applied are shown as PBTS (Positive Bias Temperature Stress), and the measurement results when a gate voltage of -40 V was applied are shown as NBTS (Negative Bias Temperature Stress).

[0209] 13A shows that the TFT element using the crystalline oxide film shows less change after applying a gate voltage of +40 V under high temperature conditions than the TFT element using the amorphous oxide film. In addition, in both elements, the change after applying a gate voltage of −40 V under high temperature conditions was small.

[0210] Next, the withstand voltage characteristics with respect to drain voltage were evaluated. First, the Id-Vg characteristics were obtained by applying a drain voltage (Vd) of +0.1 V and measuring the current value Id by varying the gate voltage (Vg) from -15 V to +15 V in 0.2 V increments. Then, a predetermined drain voltage (Vd) and a gate voltage (Vg) of +5 V were applied for 1 second at 25°C, and the Id-Vg characteristics were then obtained under the aforementioned conditions. The ratio of the drain current value at a gate voltage (Vg) of +5 V in the first Id-Vg characteristics measurement to the drain current value at a gate voltage (Vg) of +5 V in the second Id-Vg characteristics measurement was calculated and used as the "on-current ration." The drain voltage (Vd stress) applied between the first and second measurements was varied between +33 and +53 V, and the relationship between the applied drain voltage and the "on-current ration" is shown in Figure 13B.

[0211] It can be seen from FIG. 13B that the TFT element using the crystalline oxide film has higher resistance to the application of a high drain voltage than the TFT element using the amorphous oxide film.

[0212] The off-state current when a high drain voltage (Vd) was applied was also evaluated. The drain current value was measured for 7,200 seconds while applying a drain voltage (Vd) of +56 V and a gate voltage (Vg) of -10 V under the condition of 25°C. In both the TFT element using a crystalline oxide film and the TFT element using an amorphous oxide film, the off-state current was measured at 10 ―１１ A low drain current value of 1 A or less was maintained. This indicates that the TFT element using the crystalline oxide film has high voltage resistance, similar to the TFT element using the amorphous oxide film.

[0213] 10...Laminate, 11...Crystalline oxide thin film, 12...Support, 30...Gate insulating film, 50...Source electrode, 60...Drain electrode, 100...Thin film transistor, 100A...Thin film transistor, 511...Gate electrode, 513...Source electrode, 515...Drain electrode

Claims

1. A crystalline oxide film containing In as the main component, at least two elements selected from the group consisting of Ga, Al, and Y, and at least one element selected from the group consisting of Ce, Tb, Nd, Mn, Ru, Pd, and Pt.

2. The crystalline oxide film according to claim 1, which contains Ce.

3. The crystalline oxide film according to claim 2, wherein the content of Ce in said crystalline oxide film is 0.001 to 5.0 at % in terms of atomic ratio with respect to all metal elements.

4. The crystalline oxide film according to claim 2, wherein the content of Ce in said crystalline oxide film is 0.01 to 1.0 at % in terms of atomic ratio with respect to all metal elements.

5. The crystalline oxide film according to claim 1, which contains Tb.

6. The crystalline oxide film according to claim 5, wherein the content of Tb in said crystalline oxide film is 0.001 to 7.0 at % in terms of atomic ratio with respect to all metal elements.

7. The crystalline oxide film according to claim 5, wherein the content of Tb in said crystalline oxide film is 0.01 to 3.0 at % in terms of atomic ratio with respect to all metal elements.

8. The crystalline oxide film according to claim 1, which contains Nd.

9. The crystalline oxide film according to claim 8, wherein the content of Nd in said crystalline oxide film is 0.001 to 10 at % in terms of atomic ratio with respect to all metal elements.

10. The crystalline oxide film according to claim 8, wherein the content of Nd in said crystalline oxide film is 0.01 to 5.0 at % in terms of atomic ratio with respect to all metal elements.

11. A crystalline oxide film according to any one of claims 1 to 10, containing Ga and Al.

12. The crystalline oxide film according to any one of claims 1 to 11, wherein the total content of Ga, Al and Y in the crystalline oxide film is 5 to 25 at % in atomic ratio with respect to all metal elements.

13. The crystalline oxide film according to any one of claims 1 to 11, wherein the total content of Ga, Al and Y in the crystalline oxide film is 7 to 20 at % in atomic ratio with respect to all metal elements.

14. The crystalline oxide film according to any one of claims 1 to 13, wherein the content of Al in the crystalline oxide film is 7 at% or less in atomic ratio with respect to all metal elements, and the content of Y in the crystalline oxide film is 7 at% or less in atomic ratio with respect to all metal elements.

15. A crystalline oxide film according to any one of claims 1 to 14, wherein, in a planar TEM-EDS analysis of the crystalline oxide film, metal elements constituting the crystalline oxide film are not segregated at crystal grain boundaries within the film.

16. The crystalline oxide film according to any one of claims 1 to 15, wherein the crystalline oxide film contains crystal grains having a bixbyite structure.

17. The crystalline oxide film according to claim 16, wherein the bixbyite structure crystal grains contained in the crystalline oxide film have an average crystal grain size of 0.2 to 5 μm in the grain size distribution.

18. The crystalline oxide film according to claim 17, wherein the average crystal grain size is 1.8 μm or less.

19. A crystalline oxide film according to any one of claims 1 to 18, having an optical band gap of 3.0 eV or more.

20. The carrier concentration in the crystalline oxide film is 10 １８ cm －３ 20. The crystalline oxide film according to claim 1, wherein:

21. A thin film transistor having an electrode and the crystalline oxide film according to any one of claims 1 to 20.

22. An electronic device comprising the thin film transistor of claim 21.

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