Wafer-level chip manufacturing method

Abstract

Disclosed in the present invention is a wafer-level chip manufacturing method, comprising: providing a first wafer; forming a first bonding layer on the first wafer; providing a second wafer and at least four second chips; bonding the second chips on the second wafer; continuing to form a first dielectric layer on the second wafer where the second chips are bonded; etching the first dielectric layer to form through holes, and depositing a conductive material in the through holes to form first vertical conductive plugs interconnected with electrodes of the second chips; forming, on the first dielectric layer, horizontal conductive structures interconnected with the first vertical conductive plugs; continuing to form a second dielectric layer on the first dielectric layer and the horizontal conductive structures so as to form a second reconstructed wafer; bonding the second reconstructed wafer and the first wafer; removing the second wafer; and etching the first dielectric layer and the second dielectric layer. The integration level of system in package is improved, and a better line width and a higher yield are achieved.

Description

Wafer-level chip manufacturing methods Technical Field

[0001] This invention relates to the field of semiconductor device packaging, and more particularly to a wafer-level chip manufacturing method. Background Technology

[0002] System-in-Package (SiP) combines multiple active components with different functions, as well as passive components, microelectromechanical systems (MEMS), optical components, and other components, into a single unit to form a system or subsystem that can provide multiple functions, allowing for the integration of heterogeneous ICs. It effectively solves the problem that System-on-Chip (SoC) cannot integrate analog, radio frequency, and digital functions. SiP integration is relatively simple, with shorter design and time-to-market cycles, lower costs, and the ability to implement more complex systems.

[0003] In existing technologies, during chip packaging, the chip is first bonded to one side of the wafer without electrical connection. Then, a molding process is performed to seal and fix the chip. Finally, a via (with a conductive structure within it) is formed on the other side of the wafer to lead out the chip's electrical signals. However, the molding process results in significant wafer warpage, making it difficult to achieve small linewidths during photolithography and causing issues with the wafer's grip on the packaging equipment. Therefore, improving system-in-package integration to achieve better linewidths and higher yields is a current research focus. Summary of the Invention

[0004] To address the aforementioned problems, the present invention aims to provide a wafer-level chip manufacturing method comprising:

[0005] A first wafer is provided, the first wafer comprising at least two identical first bare dies arranged in an array, the surface of the bare dies having I / O metal pads;

[0006] A first bonding layer is formed on the first wafer;

[0007] A second wafer and at least four second chips are provided, the second chips having electrode layers connected to device layers;

[0008] The second chip is bonded to the second wafer, and the positions of at least two second chips correspond to the positions of the first bare chip, with the electrode layer of the second chip facing away from the second wafer;

[0009] A first dielectric layer is formed on the second wafer to which the second chip is bonded;

[0010] The first dielectric layer is etched to form a via, and a conductive material is deposited in the via to form a first vertical conductive plug that interconnects with the electrodes of the second chip;

[0011] A horizontal conductive structure interconnected with the first vertical conductive plug is formed on the first dielectric layer;

[0012] A second dielectric layer is formed on the first dielectric layer and the horizontal conductive interconnect structure to form a second reconstructed wafer;

[0013] The second reconstructed wafer is bonded to the first wafer, the second dielectric layer of the second reconstructed wafer is opposite to the first bonding layer of the first wafer, and at least every two second chips correspond to the first bare chip;

[0014] Remove the second wafer;

[0015] The first and second dielectric layers are etched to form vias that expose horizontal conductive structures and I / O metal pads. Conductive material is formed in the vias to form a second vertical conductive plug.

[0016] This invention achieves interconnection of devices under different semiconductor processes by reconstructing the second wafer and interconnecting the second wafer with the first wafer, thereby reducing the chip area and increasing the reliability of the devices. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 is a schematic flowchart of a wafer-level chip manufacturing method according to an embodiment of the present invention;

[0019] Figures 2 to 6 are cross-sectional schematic diagrams of a wafer-level chip manufacturing method according to an embodiment of the present invention. Detailed Implementation

[0020] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0021] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Since this invention pertains to electrical devices, connection and interconnection both refer to conductive interconnections. Because the accompanying drawings describe the same device, the same reference numerals denote the same components.

[0022] One embodiment of the present invention provides a wafer-level chip manufacturing method, which includes:

[0023] A first wafer is provided, the first wafer comprising at least two identical first bare dies arranged in an array, the surface of the bare dies having I / O metal pads;

[0024] A first bonding layer is formed on the first wafer;

[0025] A second wafer and at least four second chips are provided, the second chips having electrode layers connected to device layers;

[0026] The second chip is bonded to the second wafer, and the positions of at least two second chips correspond to the positions of the first bare chip, with the electrode layer of the second chip facing away from the second wafer;

[0027] A first dielectric layer is formed on the second wafer to which the second chip is bonded;

[0028] The first dielectric layer is etched to form a via, and a conductive material is deposited in the via to form a first vertical conductive plug that interconnects with the electrodes of the second chip;

[0029] A horizontal conductive structure interconnected with the first vertical conductive plug is formed on the first dielectric layer;

[0030] A second dielectric layer is formed on the first dielectric layer and the horizontal conductive interconnect structure to form a second reconstructed wafer;

[0031] The second wafer and the first wafer are bonded together, with the second dielectric layer of the second reconstructed wafer facing the first bonding layer of the first wafer, and at least every two second chips correspond to the first bare chip;

[0032] Remove the second wafer;

[0033] The first and second dielectric layers are etched to form vias that expose horizontal conductive structures and I / O metal pads. Conductive material is formed in the vias to form a second vertical conductive plug.

[0034] In one embodiment, the material of the second dielectric layer is the same as the material of the first bonding layer, and the first bonding layer and the second bonding layer are bonded together in the step of bonding the first wafer and the second wafer.

[0035] In one embodiment, a second bonding layer is further formed on the second dielectric layer.

[0036] In one embodiment, the first wafer and the second wafer are identical, and their edges overlap during the bonding process.

[0037] In one embodiment, after removing the second wafer, the bonding material between the second chip and the second wafer is also removed.

[0038] In one embodiment, the first dielectric layer and the second dielectric layer are made of different materials.

[0039] In one embodiment, the step of etching the first dielectric layer and the second dielectric layer to form a via includes:

[0040] Etching the second dielectric layer forms the first sub-via that exposes the edge of the horizontally conductive structure;

[0041] Continue etching to form a second sub-via that communicates with the first sub-via. The second sub-via stops at the surface of the I / O metal pad, and the cross-sectional area of ​​the second sub-via is larger than the area of ​​the exposed horizontal conductive structure.

[0042] In one embodiment, the step of etching the first and second dielectric layers to form a via requires optical alignment.

[0043] In one embodiment, the first dielectric layer is silicon dioxide and the second dielectric layer is silicon nitride.

[0044] In one embodiment, the second vertical conductive plug is located in the peripheral region of the second chip.

[0045] In one embodiment, the method further includes the following steps before etching the first dielectric layer and the second dielectric layer to form a via:

[0046] A third wafer substrate and a third chip are provided, the third chip having an electrode layer connected to the device layer;

[0047] The third chip is bonded to the third wafer substrate. The position of the third chip corresponds to the positions of the first bare chip and the second chip. The electrode layer of the third chip is away from the third wafer.

[0048] The first dielectric layer is formed on the third wafer substrate on which the third chip is bonded;

[0049] The first dielectric layer is etched to form a via, and conductive material is deposited in the via to form a first vertical conductive plug that interconnects with the electrodes of the third chip;

[0050] A horizontal conductive structure interconnected with the first vertical conductive plug is formed on the first dielectric layer;

[0051] A second dielectric layer is formed on the first dielectric layer and the horizontal conductive interconnect structure to form a third wafer;

[0052] A third bonding layer is formed on the second wafer;

[0053] The third wafer and the second wafer are bonded together, with the second dielectric layer of the third wafer facing each other and the third bonding layer of the first wafer.

[0054] Remove the third wafer.

[0055] The embodiments will be described in detail below with reference to the accompanying drawings. Figure 1 is a flowchart of a wafer-level chip manufacturing method according to an embodiment of the present invention. Referring to Figure 1, the wafer-level chip manufacturing method is as follows:

[0056] S10: Provide a first wafer, the first wafer comprising at least two identical first bare dies arranged in an array, the surface of the bare dies having I / O metal pads.

[0057] Specifically, in this embodiment, as shown in FIG2, the first wafer 100 includes a semiconductor substrate 100, which is silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. In this embodiment, it is a silicon substrate, on which an epitaxial layer 101 is formed. Multiple first bare chips 102, arranged in an array, constituting semiconductor devices, are formed in the epitaxial layer 101 and the silicon substrate 100. For example, the first bare chips 102 can be logic circuits composed of MOS transistors or semiconductor devices such as MEMS and sensors. An insulating layer 103 is also formed on the epitaxial layer 101. The insulating layer is made of materials such as silicon dioxide and silicon nitride, and covers the semiconductor devices. The insulating layer has metal solder joints 104 interconnecting with the semiconductor devices. For example, in this embodiment, the I / O metal solder joints are interconnected with the semiconductor devices through contact holes 105.

[0058] S20: Form the first bonding layer on the first wafer.

[0059] Specifically, the first bonding layer can be silicon dioxide. It will become molten when heated.

[0060] S30: Provide a second wafer and at least four second chips, the second chips having electrode layers connected to device layers.

[0061] Specifically, the second wafer can be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductor wafers. In this embodiment, it is a silicon wafer. The second chip can be a logic circuit composed of MOS transistors or a semiconductor device such as a MEMS or sensor. In this embodiment, it is preferable to use a device formed by a different semiconductor process than the first bare chip, thereby solving the problem that chips with different process processes cannot be formed on the same production line, and the problem of increased size caused by packaging chips with different processes, through wafer packaging.

[0062] S40: Bond the second chip onto the second wafer, with at least two positions of the second chip corresponding to the positions of the first bare chip, and the electrode layer of the second chip facing away from the second wafer.

[0063] As shown in Figure 3, a second bonding layer can be formed on the second wafer 200. This second bonding layer can be a thermally degradable film or a photodegradable film. The thermally degradable film loses its adhesiveness when the temperature exceeds a set limit. Different thermally degradable films lose their adhesiveness at different temperatures; for example, some fail at 70-80 degrees Celsius, some at around 200 degrees Celsius, and some fail at temperatures above 400 degrees Celsius. The photodegradable film loses its adhesiveness when irradiated with ultraviolet light. Next, the second chip 300 is bonded to the second wafer 200. It should be noted that since the second wafer 200 serves as a carrier for bonding the second chip 210 and the first bare chip, the position of the first bare chip on the first wafer needs to be matched when bonding the second chip 210. Specifically, the second chip 210 is placed on the second bonding layer for bonding, with the electrode layer 201 located on the surface.

[0064] S50: A first dielectric layer 220 is formed on the second wafer 200 on which the second chip 210 is bonded.

[0065] Specifically, referring to Figure 3, in this embodiment, after bonding the second chip 210, a dielectric material is filled into the second wafer 200 to form a first dielectric layer 220. The first dielectric layer 220 serves as protection and support for the second chip 210, and is also used for subsequent bonding and interconnection. The first dielectric layer 220 can specifically be one or a combination of two or more of the following: silicon dioxide, silicon nitride, epoxy resin, silicone, polyimide, benzocyclobutene, silicon oxide, phosphosilicate glass, and fluorinated glass.

[0066] S60: Etch the first dielectric layer 220 to form a via, and deposit conductive material in the via to form a first vertical conductive plug 230 that is interconnected with the electrode 201 of the second chip.

[0067] Specifically, referring to Figure 4, the first dielectric layer can be etched using either dry or wet etching methods to form vias in the first dielectric layer corresponding to the electrodes that need to connect and work with the first chip. Then, the vias are filled using chemical vapor deposition, physical vapor deposition, or electroplating. In this embodiment, the deposited conductive material can be one of the following metals: molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), or palladium (Pd), or a stack of these metals. The conductive material can be formed using physical vapor deposition methods such as magnetron sputtering or evaporation, or chemical vapor deposition methods.

[0068] S70: A horizontal conductive structure interconnected with a first vertical conductive plug is formed on the first dielectric layer.

[0069] Referring again to Figure 3, a horizontal conductive structure 240 interconnecting with the first vertical conductive plug 230 is formed on the first dielectric layer. This can be achieved using chemical vapor deposition, physical vapor deposition, or electroplating. The deposited conductive material can be one of the following metals: molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), or palladium (Pd), or a stack of the above metals. The conductive material can be formed using physical vapor deposition or chemical vapor deposition methods such as magnetron sputtering or evaporation.

[0070] In this embodiment, one end of the horizontal conductive structure 240 extends to the periphery of the second chip 210 for subsequent interconnection with the first bare chip.

[0071] S80: A second dielectric layer 260 is formed on the first dielectric layer 220 and the horizontal conductive interconnect structure 240 to form a second reconstructed wafer.

[0072] Referring to Figure 4, specifically, a second dielectric layer 250 is filled on the first dielectric layer 220 to provide interlayer support and facilitate subsequent bonding and interconnection. The second dielectric layer 250 can be one or more of the following: silicon dioxide, silicon nitride, epoxy resin, silicone, polyimide, benzocyclobutene, silicon oxide, phosphosilicate glass, and fluorinated glass. In this embodiment, preferably, the second dielectric layer and the first dielectric layer are made of different materials. For example, the first dielectric layer is a silicon dioxide layer, and the second dielectric layer is silicon nitride or a photoresist material. This allows for step-by-step etching to form vias with different morphologies, facilitating subsequent interconnection.

[0073] S90: Referring to Figure 5, the second reconstructed wafer and the first wafer are bonded together, with the second dielectric layer of the second reconstructed wafer facing each other and the first bonding layer of the first wafer being opposite each other, and at least every two second chips and the first bare chip corresponding to each other.

[0074] Specifically, since this invention is a novel chip wafer-level manufacturing method, in this embodiment, the first wafer and the second wafer are of the same size. When bonding the first wafer and the second reconstructed wafer, the edges of the first wafer and the second wafer need to overlap, and then the first bare chip and the second chip that need to be interconnected need to be optically aligned. In the direction perpendicular to the wafer surface, the I / O metal pads and horizontal conductive structures of the first wafer overlap or partially overlap. For example, as shown in Figure 6, one horizontal conductive structure 2011 projects in the direction perpendicular to the first wafer to completely cover the I / O metal pads, and another horizontal conductive structure 2012 projects in the direction perpendicular to the first wafer to partially cover the I / O metal pads.

[0075] Specifically, a third bonding layer is formed on the second reconstructed wafer, and the third bonding layer can be made of the same material as the first bonding layer. Specifically, the first bonding layer of the first wafer and the third bonding layer of the second reconstructed wafer can be bonded together by high-temperature heating, causing the first and third bonding layers to melt.

[0076] S100: Remove the second wafer.

[0077] Referring to Figure 6, specifically in this embodiment, the second bonding layer is a photolytic or thermally degradable film, thus losing its adhesiveness at high temperatures during the removal of the second wafer. Different thermally degradable films lose their adhesiveness at varying temperatures; for example, some fail at 70-80 degrees Celsius, some at around 200 degrees Celsius, and others at temperatures above 400 degrees Celsius. The photolytic film loses its adhesiveness when irradiated with ultraviolet light.

[0078] S110: Etch the first dielectric layer and the second dielectric layer to form a via that exposes the horizontal conductive structure and the I / O metal pad. Form conductive material in the via to form a second vertical conductive plug.

[0079] Referring again to Figure 6, specifically in this embodiment, optical alignment is used to etch the first dielectric layer to form a first sub-via, exposing the horizontal conductive structure 2011. The bottom surface of the first sub-via is completely projected onto the horizontal conductive structure 2011. Then, the second dielectric layer is etched to form a second sub-via, exposing the IO metal pad. The bottom surface of the second sub-via is completely projected onto the IO metal pad. In other words, the first and second sub-vias are completely through-hole structures with the same radial dimension. In another embodiment, the radial dimensions of the first and second sub-vias may be different.

[0080] In another horizontally conductive region 2012, using optical alignment, the first dielectric layer is etched to form a first sub-via, exposing the horizontally conductive structure 2012. The bottom surface of the first sub-via is projected onto the horizontally conductive structure 2012. Then, the second dielectric layer is etched to form a second sub-via, exposing the IO metal pad. The bottom surface of the second sub-via is completely projected onto the IO metal pad. In other words, the first and second sub-vias are completely through-hole structures with the same radial dimension. In another embodiment, the first and second sub-vias have different radial dimensions. The first sub-via is etched down to the second dielectric layer from the position where it reaches the first dielectric layer, and stops at the surface of the horizontally conductive structure, thereby achieving interconnection without damaging the horizontally conductive structure.

[0081] Then, the conductive material deposited into the first and second sub-contact holes using chemical vapor deposition, physical vapor deposition, or electroplating can be one of the following metals: molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), or palladium (Pd), or a stack formed from the above metals. The conductive material can be formed by physical vapor deposition or chemical vapor deposition methods such as magnetron sputtering or evaporation.

[0082] In one embodiment, the method further includes the following steps before etching the first dielectric layer and the second dielectric layer to form a via:

[0083] A third wafer substrate and a third chip are provided, the third chip having an electrode layer connected to the device layer;

[0084] The third chip is bonded to the third wafer substrate. The position of the third chip corresponds to the positions of the first bare chip and the second chip. The electrode layer of the third chip is away from the third wafer.

[0085] The first dielectric layer is formed on the third wafer substrate on which the third chip is bonded;

[0086] The first dielectric layer is etched to form a via, and conductive material is deposited in the via to form a first vertical conductive plug that interconnects with the electrodes of the third chip;

[0087] A horizontal conductive structure interconnected with the first vertical conductive plug is formed on the first dielectric layer;

[0088] A second dielectric layer is formed on the first dielectric layer and the horizontal conductive interconnect structure to form a third wafer;

[0089] A third bonding layer is formed on the second reconstructed wafer;

[0090] The third wafer and the second reconstructed wafer are bonded together, with the second dielectric layer of the third wafer facing the third bonding layer of the first wafer;

[0091] Remove the third wafer.

[0092] In one embodiment, the method further includes dicing the first wafer and the second wafer to form a plurality of devices, each device including at least one first bare chip and at least two second chips.

[0093] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A wafer level chip manufacturing method, characterized by, comprising: providing a first wafer comprising at least two identically first die arranged in an array, the die surface having I / O metal pads; forming a first bonding layer on the first wafer; providing a second wafer and at least four second dies, the second dies having a device layer and an electrode layer attached to the device layer; bonding the second dies on the second wafer, the position of at least two second dies corresponding to the position of the first die, the electrode layer of the second dies facing away from the second wafer; continuing to form a first dielectric layer on the second wafer with the second dies bonded thereon; etching the first dielectric layer to form a via and depositing a conductive material in the via to form a first vertical conductive plug interconnecting the electrode of the second dies; forming a horizontal conductive structure on the first dielectric layer interconnecting the first vertical conductive plug; continuing to form a second dielectric layer on the first dielectric layer and the horizontal conductive interconnection structure to form a second reconstituted wafer; bonding the second reconstituted wafer and the first wafer, the second dielectric layer of the second reconstituted wafer and the first bonding layer of the first wafer facing each other, and at least each two second dies and first die corresponding; removing the second wafer; etching the first dielectric layer and the second dielectric layer to form a via exposing the horizontal conductive structure and the I / O metal pads, and forming a second vertical conductive plug in the via.

2. The wafer level fabrication method of claim 1, wherein, the material of the second dielectric layer is the same as the material of the first bonding layer, and the first bonding layer and the second bonding layer are attached in the step of bonding the second reconstituted wafer and the first wafer.

3. The wafer level fabrication method of claim 1, wherein, further comprising continuing to form a second bonding layer on the second dielectric layer.

4. The wafer level fabrication method of claim 2, wherein, the size of the first wafer and the second wafer is the same, and the edges are coincident in the bonding process.

5. The wafer level fabrication method of claim 3, wherein, after removing the second wafer, further comprising removing the bonding material between the second dies and the second wafer.

6. The wafer level fabrication method of claim 4, wherein, the material of the first dielectric layer is different from the material of the second dielectric layer.

7. The wafer level fabrication method of claim 5, wherein, the step of etching the first dielectric layer and the second dielectric layer to form a via comprises: etching the second dielectric layer to form a first sub-via exposing the edge of the horizontal conductive structure; continuing to etch to form a second sub-via communicating with the first sub-via, the second sub-via stopping at the surface of the I / O metal pads, the cross-sectional area of the second sub-via being larger than the area of the exposed horizontal conductive structure.

8. The wafer level fabrication method of claim 6, wherein, the step of etching the first dielectric layer and the second dielectric layer to form a via requires optical alignment.

9. The wafer level fabrication method of claim 7, wherein, the second vertical conductive plug is located in the peripheral region of the second die.

10. The wafer level fabrication method of claim 8, wherein, before the step of etching the first dielectric layer and the second dielectric layer to form a via, further comprising: providing a third wafer substrate and a third die, the third die having a device layer and an electrode layer attached to the device layer; bonding the third die on the third wafer substrate, the position of the third die corresponding to the position of the first die and the second die, the electrode layer of the third die facing away from the third wafer; continuing to form a first dielectric layer on the third wafer substrate with the third die bonded thereon; etching the first dielectric layer to form a via and depositing a conductive material in the via to form a first vertical conductive plug interconnecting the electrode of the third die; forming a horizontal conductive structure on the first dielectric layer interconnecting the first vertical conductive plug; continuing to form a second dielectric layer on the first dielectric layer and the horizontal conductive interconnection structure to form a third wafer; forming a third bonding layer on the second reconstituted wafer; bonding a third wafer to the second reconstituted wafer, the second dielectric layer of the third wafer opposing the third bonding layer of the first wafer; removing the third wafer.

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