Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a plurality of sub-pixels, a plurality of data lines and a plurality of data line leads, which are located in a display area, and a plurality of pads, which are located in a first frame area, wherein each pad comprises a first insulating layer, a first metal layer, and a second insulating layer. The first insulating layer is provided with a first opening; the first metal layer is electrically connected to the plurality of data line leads via the first opening, and the first metal layer comprises a first bottom and a stepped portion surrounding the first bottom, wherein the first bottom is electrically connected to the plurality of data line leads, and the stepped portion comprises a first stepped portion and a second stepped portion, the second stepped portion being connected to the first bottom and the first stepped portion; and the second insulating layer comprises a second opening exposing at least part of the first bottom.

Description

Display substrate and display device

[0001] This application claims priority to PCT International Application No. PCT / CN2024 / 105414, filed on July 15, 2024, to Chinese Patent Application No. 202411488488.7, filed on October 23, 2024, the contents of which are to be understood as incorporated by reference into this application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of the present disclosure provide a display substrate, comprising:

[0006] a substrate substrate comprising a display area and a first frame area located at least one side of the display area;

[0007] a plurality of sub-pixels located at one side of the substrate substrate and in the display area;

[0008] a plurality of data lines located in the display area and electrically connected with the plurality of sub-pixels;

[0009] a plurality of data line leads located in the first frame area and electrically connected with the plurality of data lines;

[0010] a plurality of pads located in the first frame area and electrically connected with the plurality of data line leads; wherein,

[0011] At least one of the plurality of pads comprises:

[0012] A first insulating layer is located on a side of the plurality of data line leads away from the substrate substrate, and the first insulating layer comprises a first opening exposing at least a portion of at least one of the plurality of data line leads;

[0013] A first metal layer is located on a side of the plurality of data line leads away from the substrate substrate, and is electrically connected to at least one of the plurality of data line leads through the first opening; wherein the first metal layer comprises a first bottom and a stepped portion surrounding the first bottom, a projection of the first bottom on the substrate substrate is located within a projection of the first opening on the substrate substrate, the first bottom is electrically connected to at least one of the plurality of data line leads, the stepped portion comprises a first stepped portion located on a side of the first insulating layer away from the substrate substrate and a second stepped portion at an angle to the first stepped portion, the second stepped portion connects the first bottom and the first stepped portion, and a projection of the second stepped portion on the substrate substrate is located in a projection of the first opening on the substrate substrate;

[0014] A second insulating layer is located on a side of the first metal layer and the first insulating layer away from the substrate substrate, wherein the second insulating layer comprises a second opening exposing at least a portion of the first bottom of the first metal layer.

[0015] In an exemplary embodiment, the side of the first stepped portion away from the substrate substrate is uniformly covered by the second insulating layer.

[0016] In an exemplary embodiment, a projection of the first stepped portion on the substrate substrate and a projection of the second insulating layer on the substrate substrate do not have an overlapping area, and a projection of the second opening on the substrate substrate covers projections of the first opening, the first stepped portion and the first bottom on the substrate substrate.

[0017] Alternatively, a projection of the first stepped portion on the substrate substrate is covered by a projection of the second insulating layer on the substrate substrate, and a projection of the second opening on the substrate substrate is located within a projection of the first opening on the substrate substrate.

[0018] In an exemplary embodiment, the display substrate further comprises:

[0019] a second metal layer located on a side of the first metal layer and the second insulating layer away from the substrate, wherein the second metal layer is electrically connected with the first metal layer through the second opening, and a projection of the second metal layer on the substrate at least partially overlaps with a projection of the second opening on the substrate.

[0020] In an exemplary embodiment, a projection of the second metal layer on the substrate covers projections of the first metal layer and the second opening on the substrate; or,

[0021] a projection of the second metal layer on the substrate does not overlap with a projection of the first step portion of the first metal layer on the substrate, and a projection of the second metal layer on the substrate covers a projection of the second opening on the substrate; or,

[0022] a projection of the second metal layer on the substrate does not overlap with a projection of the first step portion of the first metal layer on the substrate, and a projection of the second metal layer on the substrate is within a range of a projection of the second opening on the substrate.

[0023] In an exemplary embodiment, the display substrate further comprises:

[0024] a third metal layer located on a side of the second metal layer away from the substrate, wherein the third metal layer is electrically connected with the second metal layer, and a projection of the third metal layer on the substrate covers a projection of the second metal layer on the substrate.

[0025] In an exemplary embodiment, the display substrate further comprises:

[0026] a third insulating layer located on a side of the third metal layer away from the substrate, wherein the third insulating layer comprises a third opening;

[0027] a projection of the third opening on the substrate is within projections of the first opening and the second opening on the substrate; or,

[0028] projections of the first opening and the second opening on the substrate are within a projection of the third opening on the substrate; or,

[0029] a projection of the third opening on the substrate is within a range of a projection of the second opening on the substrate, and a projection of the first opening on the substrate is within a range of a projection of the third opening on the substrate.

[0030] In an exemplary embodiment, the third insulating layer includes at least one of an inorganic insulating layer and an organic insulating layer.

[0031] In an exemplary embodiment, the third insulating layer includes a first insulating sub-layer and a second insulating sub-layer, the second insulating sub-layer is located on a side of the first insulating sub-layer away from the substrate;

[0032] The material of the first insulating sub-layer is an organic material, the material of the second insulating sub-layer is an inorganic material, the orthographic projection of the first insulating sub-layer on the substrate does not overlap at least part of the orthographic projection of the step portion on the substrate, and the orthographic projection of the second insulating sub-layer on the substrate covers at least part of the orthographic projection of the step portion on the substrate.

[0033] In an exemplary embodiment, the display substrate further includes:

[0034] A fourth metal layer is located on a side of the third insulating layer away from the substrate, wherein the fourth metal layer is electrically connected to the third metal layer through the third opening, and the orthographic projection of the fourth metal layer on the substrate at least partially overlaps the orthographic projection of the third metal layer on the substrate.

[0035] In an exemplary embodiment, the display substrate further includes:

[0036] A fourth insulating layer is located between the third insulating layer and the fourth metal layer in a direction perpendicular to the plane on which the substrate is located, wherein the fourth insulating layer includes a fourth opening, the orthographic projection of the fourth opening on the substrate is located within the orthographic projection of the third opening on the substrate, and the fourth metal layer is electrically connected to the third metal layer through the third opening and the fourth opening.

[0037] In an exemplary embodiment, the first metal layer further includes a second bottom portion surrounding the step portion, the step portion further includes a third step portion at an angle with the first step portion, the third step portion connects the second bottom portion and the first step portion, and the orthographic projection of the second insulating layer on the substrate at least partially overlaps the orthographic projection of the second bottom portion on the substrate.

[0038] In an exemplary embodiment, the orthographic projection of the second insulating layer on the substrate partially overlaps the orthographic projection of the first bottom portion on the substrate, and the orthographic projection of the second opening on the substrate is located in the orthographic projection of the first opening on the substrate; or,

[0039] A normal projection of the second insulating layer on the substrate is not overlapped with normal projections of the first bottom and the step portion on the substrate, and a normal projection of the second opening on the substrate covers a normal projection of the first opening on the substrate.

[0040] In an exemplary embodiment, a size of the first opening along a width direction is 3 micrometers to 11 micrometers.

[0041] In an exemplary embodiment, a size of the first opening along a width direction is 5 micrometers to 8 micrometers.

[0042] In an exemplary embodiment, the third metal layer is a single-layer structure, or the third metal layer is a multi-layer composite structure.

[0043] In the single-layer structure of the third metal layer, a metal activity in a metal layer closest to the third metal layer in the second metal layer is not less than a metal activity in the third metal layer.

[0044] In the multi-layer composite structure of the third metal layer, in a direction perpendicular to a plane in which the substrate is located, a metal activity in a metal layer farthest from the second metal layer in the third metal layer is not greater than a metal activity in a metal layer between the farthest metal layer and the second metal layer.

[0045] In an exemplary embodiment, the substrate includes a packaging region and an edge region located around the packaging region, the edge region includes a binding region on a side of at least one edge of the substrate, and the binding region is located in the first frame region.

[0046] A plurality of inorganic film layers are located on one side of the substrate and are stacked.

[0047] A plurality of first grooves are located in the edge region and are sequentially and spaced apart in a direction away from the packaging region, and partially surround the packaging region, wherein each of the first grooves penetrates at least one inorganic film layer of the plurality of inorganic film layers, and a normal projection of the plurality of first grooves on the substrate is not overlapped with the binding region.

[0048] An organic layer is covered on the plurality of first grooves.

[0049] In an exemplary embodiment, the organic layer includes a first flat layer and a second flat layer sequentially and stacked in a direction away from the substrate, the first flat layer covers the plurality of first grooves, and the second flat layer is located on a side of the first flat layer away from the substrate.

[0050] In an exemplary embodiment, the first insulating layer comprises: a gate insulating layer and an interlayer dielectric layer which are sequentially stacked in a direction away from the substrate base plate, and the at least one inorganic film layer comprises the gate insulating layer and the interlayer dielectric layer.

[0051] In an exemplary embodiment, the inorganic film layer between each two adjacent first grooves constitutes a barrier portion; the plurality of inorganic film layers further comprise: a buffer layer between the substrate base plate and the gate insulating layer in a direction perpendicular to the plane in which the substrate base plate is located, and the at least one inorganic film layer further comprises at least part of the buffer layer.

[0052] In an exemplary embodiment, the plurality of inorganic film layers further comprise: a barrier layer between the substrate base plate and the buffer layer in a direction perpendicular to the plane in which the substrate base plate is located, and the at least one inorganic film layer further comprises at least part of the barrier layer.

[0053] In an exemplary embodiment, the display area of the display substrate comprises: a gate metal layer on the substrate base plate, a gate insulating layer on a side of the gate metal layer away from the substrate base plate, and a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer sequentially arranged on a side of the gate insulating layer away from the substrate base plate;

[0054] In a direction perpendicular to the plane in which the substrate base plate is located, the first planar layer is between the first source-drain metal layer and the second source-drain metal layer, and the second planar layer is between the second source-drain metal layer and the third source-drain metal layer;

[0055] The plurality of data line leads are arranged in the same layer as the gate metal layer, the first insulating layer is arranged in the same layer as the gate insulating layer, the first metal layer is arranged in the same layer as the first source-drain metal layer, the second metal layer is arranged in the same layer as the second source-drain metal layer, and the third metal layer is arranged in the same layer as the third source-drain metal layer.

[0056] In a second aspect, the present disclosure further provides a display device comprising the display substrate described in any of the above embodiments.

[0057] In a third aspect, the embodiments of the present disclosure further provide a method for manufacturing the display substrate described in any of the above embodiments, which can comprise:

[0058] A substrate base plate is provided, which comprises a display area and a first frame area on at least one side of the display area;

[0059] A plurality of sub-pixels, a plurality of data lines and a plurality of data line leads are prepared on one side of the substrate, the plurality of sub-pixels and the plurality of data lines are located in the display area and the plurality of sub-pixels are electrically connected to the plurality of data lines, and the plurality of data line leads are located in the first frame area and are electrically connected to the plurality of data lines;

[0060] A plurality of pads are made in the first frame area, and the step of making at least one pad in the plurality of pads includes:

[0061] A first insulating layer is formed on the side of the plurality of data line leads away from the substrate, and the first insulating layer includes a first opening exposing at least a portion of at least one data line lead in the plurality of data line leads;

[0062] A first metal layer is formed on the side of the plurality of data line leads away from the substrate, and the first metal layer is electrically connected to at least one data line lead in the plurality of data line leads through the first opening, wherein the first metal layer includes a first bottom and a stepped portion surrounding the first bottom, a projection of the first bottom on the substrate is located within a projection of the first opening on the substrate, the first bottom is electrically connected to at least one data line lead in the plurality of data line leads, the stepped portion includes a first stepped portion on the side of the first insulating layer away from the substrate and a second stepped portion at an angle to the first stepped portion, the second stepped portion connects the first bottom and the first stepped portion, and a projection of the second stepped portion on the substrate is located in a projection of the first opening on the substrate.

[0063] A second insulating layer is formed on the side of the first metal layer and the first insulating layer away from the substrate, wherein the second insulating layer includes a second opening exposing at least a portion of the first bottom of the first metal layer, and the side of the first stepped portion away from the substrate is covered by the second insulating layer in a uniform manner.

[0064] In an exemplary embodiment, a projection of the first stepped portion on the substrate does not overlap with a projection of the second insulating layer on the substrate, and a projection of the second opening on the substrate covers projections of the first opening, the first stepped portion and the first bottom on the substrate; or, a projection of the first stepped portion on the substrate is covered by a projection of the second insulating layer on the substrate, and a projection of the second opening on the substrate is located within a projection of the first opening on the substrate.

[0065] In an exemplary embodiment, the method further includes:

[0066] forming a second metal layer on a side of the second metal layer distal from the substrate, wherein the second metal layer is electrically connected with the first metal layer through the second opening, and a footprint of the second metal layer on the substrate at least partially overlaps with a footprint of the second opening on the substrate;

[0067] forming a third metal layer on a side of the second metal layer distal from the substrate, wherein the third metal layer is electrically connected with the second metal layer, and a footprint of the third metal layer on the substrate covers a footprint of the second metal layer on the substrate.

[0068] In an example embodiment, the method further comprises:

[0069] forming a third insulating layer on a side of the third metal layer distal from the substrate, wherein the third insulating layer comprises a third opening;

[0070] a footprint of the third opening on the substrate is within footprints of the first opening and the second opening on the substrate, or the footprints of the first opening and the second opening on the substrate are within a footprint of the third opening on the substrate, or the footprint of the third opening on the substrate is within a footprint of the second opening on the substrate, and a footprint of the first opening on the substrate is within a footprint of the third opening on the substrate.

[0071] In an example embodiment, the method further comprises:

[0072] forming a third insulating layer on a side of the third metal layer distal from the substrate, wherein the third insulating layer comprises a third opening, a footprint of the third insulating layer on the substrate covers a footprint of the step portion and a portion of the first bottom portion on the substrate, and a footprint of the third opening on the substrate is within a footprint of the first opening on the substrate;

[0073] forming an anode conductive layer on a side of the third insulating layer distal from the substrate, wherein the anode conductive layer comprises a plurality of anodes;

[0074] forming a fourth insulating layer on a side of the anode conductive layer distal to the substrate, the fourth insulating layer comprising a fourth opening, a projection of the fourth opening on the substrate being within a projection of the third opening on the substrate, and forming a third opening in the third insulating layer corresponding to a third sub-opening, a projection of the third sub-opening on the substrate being within a projection of the corresponding third opening on the substrate.

[0075] In an exemplary embodiment, a width dimension of the third sub-opening is 2-5 microns, and a width dimension of the third opening is 5-9 microns.

[0076] In an exemplary embodiment, the first metal layer further comprises a second bottom portion surrounding the step portion, the step portion further comprises a third step portion at an angle with the first step portion, the third step portion connecting the second bottom portion and the first step portion, and a projection of the second insulating layer on the substrate at least partially overlaps a projection of the second bottom portion on the substrate.

[0077] In an exemplary embodiment, a projection of the second insulating layer on the substrate partially overlaps a projection of the first bottom portion on the substrate, and a projection of the second opening on the substrate is within a projection of the first opening on the substrate; or, a projection of the second insulating layer on the substrate does not overlap a projection of the first bottom portion and the step portion on the substrate, and a projection of the second opening on the substrate covers a projection of the first opening on the substrate.

[0078] In an exemplary embodiment, the substrate comprises a packaging region and a peripheral region surrounding the packaging region, the peripheral region comprises a binding region on a side of at least one edge of the substrate, and the binding region is located in the first frame region; the method further comprises:

[0079] forming a plurality of inorganic film layers on a side of the substrate by using inorganic materials;

[0080] forming a plurality of first grooves in the peripheral region and in a direction distal to the packaging region, the plurality of first grooves being sequentially spaced and extending along a periphery of the substrate, each of the plurality of first grooves penetrating at least one of the plurality of inorganic film layers, and a projection of the plurality of first grooves on the substrate does not overlap the binding region;

[0081] forming an organic layer covering the plurality of first grooves by using organic materials.

[0082] In an exemplary embodiment, the organic layer includes: a first planarization layer and a second planarization layer sequentially stacked along a direction away from the substrate, wherein the first planarization layer and the second planarization layer are located on the side of the plurality of inorganic film layers away from the substrate;

[0083] The first insulating layer includes a gate insulating layer and an interlayer dielectric layer sequentially stacked along a direction away from the substrate, and the at least one inorganic film layer includes the gate insulating layer and the interlayer dielectric layer.

[0084] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0085] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0086] Figure 1a is a schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0087] Figure 1b is another schematic diagram of the display substrate according to an embodiment of the present disclosure;

[0088] Figure 2 is a cross-sectional view of the display area of ​​the display substrate shown in Figure 1a, taken along line aa'.

[0089] Figure 3 is a partial schematic diagram of the first signal access area according to an embodiment of this disclosure;

[0090] Figure 4 is a magnified view of the details of region S in Figure 2;

[0091] Figure 5a is a schematic cross-sectional structure of position AA in Figure 4;

[0092] Figure 5b is a schematic cross-sectional structure of position AA in Figure 4;

[0093] Figure 5c is a schematic cross-sectional structure of position AA in Figure 4;

[0094] Figure 6 is a schematic cross-sectional structure of position AA in Figure 4;

[0095] Figure 7 is a schematic cross-sectional structure of position AA in Figure 4;

[0096] Figure 8a is a schematic cross-sectional structure of position AA in Figure 4;

[0097] Figure 8b is a schematic cross-sectional structure of position AA in Figure 4;

[0098] Figure 8c is a schematic cross-sectional structure of position AA in Figure 4;

[0099] Figure 9a is a schematic cross-sectional structure of position AA in Figure 4;

[0100] Figure 9b is a schematic cross-sectional structure of position AA in Figure 4;

[0101] Figure 9c is a schematic cross-sectional structure of position AA in Figure 4;

[0102] Figure 9d is a schematic cross-sectional structure of position AA in Figure 4;

[0103] Figure 10a is a schematic diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0104] Figure 10b is a schematic diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0105] Figure 11a is a schematic cross-sectional structure of position M1-M1 in Figures 10a and 10b;

[0106] Figure 11b is a schematic cross-sectional structure of position M1-M1 in Figures 10a and 10b;

[0107] Figure 11c is a schematic cross-sectional structure of position M1-M1 in Figures 10a and 10b;

[0108] Figure 11d is a schematic cross-sectional structure of position M1-M1 in Figures 10a and 10b;

[0109] Figure 12a is a schematic cross-sectional structure of position M2-M2 in Figures 10a and 10b;

[0110] Figure 12b is a schematic cross-sectional structure of position M2-M2 in Figures 10a and 10b;

[0111] Figure 12c is a schematic cross-sectional structure of the M2-M2 position in Figures 10a and 10b;

[0112] Figure 13a is a schematic cross-sectional view of the structure after the first insulating layer in the pad is formed;

[0113] Figure 13b is a schematic cross-sectional view of the structure after the first metal layer in the pad is formed;

[0114] Figure 13c is a schematic cross-sectional view of the structure after the second insulating layer in the pad is formed;

[0115] Figure 13d is a schematic cross-sectional view of the structure after the second metal layer in the pad is formed;

[0116] Figure 13e is a schematic cross-sectional structure after the third metal layer in the pad is formed;

[0117] Figure 13f is a schematic cross-sectional view of the structure after the third insulating layer in the pad is formed;

[0118] Figure 13g is a schematic cross-sectional structure diagram after the fourth insulating layer in the pad is formed;

[0119] Figure 14 is a schematic cross-sectional structure after the fourth insulating layer in the pad is formed;

[0120] Figure 15 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0121] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0122] It is understood that the various figures in the embodiments of this disclosure are only used to schematically show the connection relationship between the various components. The dimensions of the various components in the figures are not drawn to scale, and their relative positional relationship may not completely correspond to the actual position.

[0123] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0124] In this disclosure, "electrical connection" includes the situation where components are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected components. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0125] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0126] The "patterning process" as described in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0127] Figure 1a is a schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1b is another schematic diagram of a display substrate according to an embodiment of the present disclosure. Both Figures 1a and 1b show planar schematic diagrams of the display substrate before the bending process.

[0128] In some examples, as shown in Figures 1a and 1b, the display substrate may include a display area AA and a border area BB surrounding the display area AA. For example, the border area BB may include a first border area B1 located on one side of the display area AA, and border areas located on other sides of the display area AA (e.g., a second border area B2, a third border area B3, and a fourth border area B4). The first border area B1 may be, for example, the bottom border of the display substrate; the second border area B2 may be, for example, the top border of the display substrate; the third border area B3 may be, for example, the left border of the display substrate; and the fourth border area B4 may be, for example, the right border of the display substrate.

[0129] In some examples, as shown in Figures 1a and 1b, the display area AA can be a flat area comprising multiple sub-pixels PX that make up a pixel array. These sub-pixels PX can be configured to display moving or still images. The display area AA can be referred to as the active area. In some examples, the display area AA can be rectangular. However, this embodiment is not limited to this. For example, the display area AA can be other shapes such as circular or elliptical. In some examples, the display substrate can be a flexible panel, and therefore the display substrate can be deformable, such as rolled, bent, folded, or rolled up.

[0130] In some examples, as shown in Figures 1a and 1b, the display area AA may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a first direction X, and the multiple data lines DL may extend along a second direction Y. The orthogonal projections of the multiple gate lines GL and the multiple data lines DL onto the substrate may intersect to form multiple sub-pixel regions, each of which may contain one sub-pixel PX. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signals may include scan signals and light emission control signals, or may include scan signals, or may include scan signals, reset control signals, and light emission control signals.

[0131] In some examples, as shown in Figures 1a and 1b, the first direction X can be the extension direction of the grid line GL in the display area AA (e.g., the row direction), and the second direction Y can be the extension direction of the data line DL in the display area AA (e.g., the column direction). The first direction X and the second direction Y can intersect each other, for example, they can be perpendicular to each other.

[0132] In some examples, a pixel unit of the display area AA may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0133] In some examples, the shape of the subpixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three subpixels, the three subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four subpixels, the four subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0134] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit (indicated by L in FIG1a; note that for simplicity, the light-emitting element L is shown in only one sub-pixel PX in FIG1a, which does not represent a limitation of this disclosure). The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, T in the above circuit structure refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. However, this embodiment is not limited to this.

[0135] In some examples, multiple transistors in the pixel circuit can be employed as low-temperature polysilicon (LTPS) thin-film transistors (TFTs) and oxide (OPT) thin-film transistors (OTPTs). The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPT TFTs offer advantages such as low leakage current. Integrating LTPS and OPT TFTs onto a single display substrate, i.e., an LTPS+Opide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0136] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0137] In some examples, the display substrate can integrate a touch structure. The display substrate may include an organic light-emitting diode (OLED) display structure, a plasma display structure, or an electrophoretic display structure. For example, the display substrate may include an OLED display structure and a touch structure. The touch structure can be disposed on the encapsulation layer of the display structure, forming a Touch on Thin Film Encapsulation (TFE) structure. The integration of the display structure and the touch structure offers advantages such as thinness, lightness, and foldability, meeting the product requirements for flexible folding and narrow bezels.

[0138] In some examples, the touch structure on thin-film encapsulation mainly includes the Flexible Multi-Layer On Cell (FMLOC) structure and the Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure operates based on mutual capacitance detection, typically using two metal layers to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) detects the mutual capacitance between the driving and sensing electrodes to achieve touch action. The FSLOC structure operates based on self-capacitance (or voltage) detection, typically using a single metal layer to form the touch electrode. The integrated circuit detects the self-capacitance (or voltage) of the touch electrode to achieve touch action.

[0139] Figure 2 is a schematic cross-sectional view of the display area of ​​the display substrate shown in Figure 1a, taken along line aa'. Figure 2 illustrates the structure of a sub-pixel in the display area as an example. In this example, multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OPS). In other examples, the multiple transistors in the pixel circuit can be both LTPS and OPS. Furthermore, this example illustrates the integration of a mutual capacitance touch structure into the display substrate to form an FMLOC structure.

[0140] In some examples, as shown in Figure 2, in the direction Z perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 100, and a circuit structure layer 20, a light-emitting structure layer 30, an encapsulation structure layer 40, a touch structure layer 50, and a color filter layer 60 sequentially disposed on the substrate 100. The display structure layer may include at least the circuit structure layer 20 and the light-emitting structure layer 30. The circuit structure layer 20 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 30 may include at least light-emitting elements for multiple sub-pixels.

[0141] In some examples, Figure 2 illustrates an example where each sub-pixel includes a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 20 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 202 may be disposed between the first gate metal layer and the second gate metal layer; an interlayer insulating layer 203 may be disposed between the second gate metal layer and the first source-drain metal layer; a passivation layer 204 and a first planarization layer 205 may be disposed between the first source-drain metal layer and the second source-drain metal layer; a second planarization layer 206 may be disposed between the second source-drain metal layer and the third source-drain metal layer; and a third planarization layer 207 may be disposed on the side of the third source-drain metal layer away from the substrate 100. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, while the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 may be organic insulating layers. However, this embodiment is not limited to these limitations. In other examples, a buffer layer may be disposed on the side of the semiconductor layer closest to the substrate. This buffer layer prevents harmful substances from the substrate from penetrating the interior of the display substrate and also increases the adhesion of the film layers in the display substrate to the substrate. In still other examples, a bottom shielding metal layer (BSM) may be disposed on the side of the buffer layer closest to the substrate. This bottom shielding metal layer may be configured to at least partially cover the active layer of the thin-film transistor in the pixel circuitry to prevent external light from affecting the performance of the thin-film transistor. In still other examples, a passivation layer may be omitted between the first and second source-drain metal layers, and only a first planarization layer may be disposed between the first and second source-drain metal layers.

[0142] In some examples, as shown in FIG2, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 100. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 203 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 204 and the first planarization layer 205. The third source-drain metal layer may include at least a second transition electrode 232. The second transition electrode 232 can be electrically connected to the first transition electrode 231 located in the second source-drain metal layer through a fourth pixel via formed by the second planarization layer 206. The second transition electrode 232 can be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element through a fifth pixel via formed by the third planarization layer 207. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 231 and the second transition electrode 232.

[0143] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer or the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer; and the high-potential power lines of the display area may be located, for example, in at least one of the second and third source-drain metal layers. This embodiment is not limited in this respect. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0144] In some examples, as shown in Figure 2, the light-emitting structure layer 30 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on a third planarization layer 207 and electrically connected to a second transition electrode 232 through a fifth pixel via formed in the third planarization layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planarization layer 207, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer may also be provided on the side of the pixel definition layer 304 away from the substrate 100, and the isolation pillar layer may include multiple isolation pillars (PS).

[0145] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0146] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0147] In some examples, as shown in Figure 2, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked in a direction perpendicular to the substrate. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be made of organic materials and may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 402 may be made of organic materials, for example, a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have intruded into the interior. However, this embodiment is not limited in this respect. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0148] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0149] In some examples, as shown in Figure 2, the touch structure layer 50 of the display area may include, in the direction perpendicular to the substrate, a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, arranged sequentially. The touch buffer layer 501 and the touch interlayer insulating layer 502 can be inorganic insulating layers, such as SiNx layers. For example, the first touch conductive layer 511 may include multiple first touch electrodes, multiple second touch electrodes, and multiple first connection portions. The first touch electrodes and the first connection portions can be an integrally connected structure. The second touch conductive layer 512 may include multiple second connection portions. The second connection portions can be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0150] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0151] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0152] In some examples, as shown in FIG2, in a direction perpendicular to the substrate, the color filter on encapsulation (COE) 60 may include an insulating layer 601, a color filter layer, and an overcoat 602 disposed sequentially. The color filter layer includes a black matrix 610 and color filter units 611 disposed between the black matrix 610. The color filter units 611 may be, for example, red filter units, green filter units, or blue filter units.

[0153] In some examples, as shown in Figure 1a, the first border region B1 of the display substrate may include a fan-out trace region B11 and a signal access region B12 arranged sequentially along a direction away from the display region AA. Figure 1a only illustrates a few traces within the first border region for illustrative purposes. This example does not limit the number of traces in the first border region.

[0154] In some examples, as shown in Figure 1a, the fan-out routing area B11 can be connected between the display area AA and the signal access area B12. The fan-out routing area B11 can have at least multiple data fan-out lines 42. These multiple data fan-out lines 42 can be electrically connected to multiple data lines DL within the display area AA; for example, the multiple data fan-out lines 42 and multiple data lines DL can be electrically connected in a one-to-one correspondence. The multiple data fan-out lines 42 can extend into the signal access area B12 using a fan-out routing method. The multiple data fan-out lines 42 and the multiple data lines DL can be located in different film layers, and the data fan-out lines 42 can be connected to the data lines DL through vias formed in the insulating layer.

[0155] In some examples, as shown in FIG1a, the signal access area B12 may include at least one first signal access area B121. This example illustrates and describes one first signal access area. In other examples, the display substrate is a large-size panel, and the display substrate may include multiple first signal access areas, which may be arranged sequentially along a first direction X.

[0156] In some examples, as shown in Figure 1a, the first signal access area B121 can also be referred to as a driver chip (IC) setting area. The first signal access area B121 may be provided with multiple pads 31, which can be configured to be bonded to at least one driver chip. The driver chip can be configured to generate drive signals required to drive sub-pixels and provide the drive signals to the data lines DL of the display area AA. For example, the drive signals can be data signals for driving sub-pixels. In some examples, the driver chip can be a central processing unit, a digital signal processor, a system-on-a-chip (SoC), etc. For example, the driver chip can also include hardware circuitry and computer-executable code. The hardware circuitry can include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuitry can also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0157] In some examples, as shown in Figure 1a, the signal access area B12 may be provided with at least a plurality of data line leads 101, which can be electrically connected to a plurality of data fan-out lines 42 in the fan-out routing area B11, for example, in a one-to-one correspondence. For example, the data line leads 101 and the connected data fan-out lines 42 can be an integrated structure interconnected. That is, the plurality of data line leads 101 are electrically connected to a plurality of data lines DL through the plurality of data fan-out lines 42, for example, in a one-to-one correspondence. The plurality of data line leads 101 can extend into the first signal access area B121 and be electrically connected to a plurality of pads 31 within the first signal access area B121. For example, the plurality of data line leads 101 and the plurality of pads 31 can be electrically connected in a one-to-one correspondence, or one data line lead 101 can be electrically connected to at least one pad 31. The data line leads 101 and the data fan-out lines 42 can transmit the data signals provided by the driver chip to the data lines DL of the display area.

[0158] In some examples, as shown in Figure 1b, the first border region B1 of the display substrate may include: a fan-out trace region B11, a bending region B13, and a signal access region B12 arranged sequentially along a direction away from the display region AA. Figure 1b only illustrates a few traces within the first border region for illustrative purposes. This example does not limit the number of traces in the first border region.

[0159] In some examples, as shown in Figure 1b, the bending region B13 can connect the fan-out trace region B11 and the signal access region B12, and can be configured to bend the signal access region B12 to the back of the display region AA. The bending region B13 can have at least multiple data bending connection lines 43. One end of the data bending connection line 43 can be connected to the data fan-out line 42 in the fan-out trace region B11, and the other end can be connected to the data line lead 101 in the signal access region B12. The multiple data bending connection lines 43 can be in the same layer, for example, located in the first source-drain metal layer or the second source-drain metal layer. The remaining structure of the first border region B1 in this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0160] As shown in Figures 1a and 1b, the signal access area B12 may further include a second signal access area B122, in which a plurality of contact pads 32 are provided for bonding with the flexible circuit board. The pads referred to below in this disclosure refer to the pads 31 of the first signal access area B121, which are used for bonding with at least one driver chip.

[0161] Figure 3 is a partial enlarged view of the first signal access area according to an embodiment of the present disclosure. In some examples, as shown in Figure 3, the plurality of pads 31 of the first signal access area B121 can be arranged in multiple rows (e.g., four rows). The plurality of pads 31 in each row can be arranged sequentially along a first direction X, and the multiple rows of pads 31 can be arranged sequentially along a second direction Y. The pads 31 in adjacent rows can be staggered in the first direction X. However, this embodiment is not limited to this. In other examples, the plurality of pads of the first signal access area B121 can be arranged in a single row.

[0162] In some examples, the multiple pads 31 in the first signal access area can be divided into at least two groups. Figure 3 illustrates and explains two groups of pads (e.g., the first group of pads 31A and the second group of pads 31B). The second group of pads 31B can be located on the side of the first group of pads 31A away from the display area. The first group of pads 31A can include three rows of multiple pads 311 arranged along the first direction X. The second group of pads 31B can include one row of multiple pads 312 arranged along the first direction X. In some examples, the second group of pads 31B is used for input signals, which are converted by the bonded IC and output to the first group of pads 31A. The first group of pads 31A then transmits the signals (e.g., data signals) to multiple sub-pixels PX through multiple signal lines (e.g., multiple data lines DL). The first group of pads 31A and the second group of pads 31B can be staggered in the first direction X. For example, the pads in the first group of pads 31A and the second group of pads 31B may not be aligned in the second direction Y. There are gaps between adjacent pads within the same group, and gaps between pads in adjacent groups. In some embodiments, a group of pads may be one row, two rows, or three rows of pads. This disclosure does not limit the number of rows of pads or the number of pads in each row.

[0163] Figure 4 is a magnified view of region S in Figure 3. In some examples, as shown in Figure 4, multiple data line leads 101 can extend approximately along the second direction Y between multiple pads 31. For example, two data line leads 101 can be provided between two adjacent pads 31 in a set of pads. A data line lead 101 can be electrically connected to at least one pad 31, for example, a data line lead 101 can be connected to one pad 31.

[0164] As the number of signal lines in a display substrate increases, achieving a narrow bezel effect typically requires layering the signal lines. For example, three source-drain metal layers can be fabricated, allowing signal lines to be routed separately within each layer, reducing the load on a single layer and effectively minimizing the bezel size. In the bezel area of ​​the display substrate, some pads used to connect to the driver chip (driver IC) are fabricated simultaneously using the three source-drain metal layers. During the substrate fabrication process, cracks can easily appear in the third source-drain metal layer of the pads, exposing metal (such as aluminum). This aluminum replaces silver ions (Ag+) in the wet etching solution of the first electrode 301, forming silver particles. During the wet etching process of the first electrode 301 (which can act as the anode) and subsequent washing processes (such as cleaning the fabricated anode), these silver particles are washed to the anode (i.e., the first electrode 301) opening (i.e., the pixel opening), causing a short circuit between the anode (i.e., the first electrode 301) and the cathode (i.e., the second electrode 302) within the display area, resulting in dark spots.

[0165] This disclosure provides a display substrate, which may include:

[0166] A substrate, the substrate including a display area and a first border area located on at least one side of the display area;

[0167] Multiple sub-pixels are located on one side of the substrate and in the display area;

[0168] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels;

[0169] Multiple data line leads are located in the first frame area and are electrically connected to the multiple data lines;

[0170] Multiple pads are located in the first frame area and are electrically connected to the multiple data line leads; wherein...

[0171] At least one of the plurality of pads includes:

[0172] A first insulating layer is located on the side of the plurality of data line leads away from the substrate, the first insulating layer including a first opening that exposes at least a portion of at least one of the plurality of data line leads;

[0173] A first metal layer is located on the side of the plurality of data line leads away from the substrate and is electrically connected to at least one of the plurality of data line leads through the first opening; wherein, the first metal layer includes a first bottom and a stepped portion surrounding the first bottom, the orthographic projection of the first bottom on the substrate lies within the orthographic projection of the first opening on the substrate, the first bottom is electrically connected to at least one of the plurality of data line leads, the stepped portion includes a first stepped portion located on the side of the first insulating layer away from the substrate and a second stepped portion forming an angle with the first stepped portion, the second stepped portion connects the first bottom and the first stepped portion, and the orthographic projection of the second stepped portion on the substrate lies within the orthographic projection of the first opening on the substrate;

[0174] A second insulating layer is located on the side of the first metal layer and the first insulating layer facing away from the substrate, wherein the second insulating layer includes a second opening that exposes at least a portion of the first bottom of the first metal layer.

[0175] In an exemplary embodiment, the side of the first stepped portion away from the substrate is covered by the second insulating layer in the same manner.

[0176] The display substrate provided in this embodiment includes multiple data lines and multiple sub-pixels located in the display area, as well as multiple data line leads and multiple pads located in the first border area. The multiple data lines are electrically connected to the multiple sub-pixels, and the multiple data line leads are electrically connected to the multiple data lines and the multiple pads. At least one of the multiple pads includes a first insulating layer, a first metal layer, and a second insulating layer sequentially stacked on the side of the data line lead away from the substrate. The first insulating layer has a first opening, and the first metal layer is electrically connected to at least one of the multiple data line leads through the first opening. The first metal layer includes a first bottom and a layer surrounding the first bottom. The stepped portion has a first bottom portion whose orthogonal projection on the substrate is located within the orthogonal projection of the first opening on the substrate. The first bottom portion is electrically connected to at least one of the multiple data line leads. The stepped portion includes a first stepped portion and a second stepped portion that forms an angle with the first stepped portion. The second stepped portion connects the first bottom portion and the first stepped portion. The orthogonal projection of the second stepped portion on the substrate is located within the orthogonal projection of the first opening on the substrate. The second insulating layer includes a second opening that exposes at least a portion of the first bottom portion. The technical solution provided by the embodiments of this disclosure can, to a certain extent, reduce or avoid the formation of dark spots due to short circuits between the anode and cathode in the display area.

[0177] As shown in Figures 1a, 1b, and 3 to 9b, Figures 1a and 1b are schematic diagrams of the planar structure of the display substrate, Figure 3 is a partially enlarged schematic diagram of the first signal access area B121 in Figures 1a and 1b, Figure 4 is an enlarged view of area S in Figure 3, and Figures 5a to 9b are schematic diagrams of several cross-sectional structures at position AA in Figure 4. As shown in Figures 1a, 1b, 3 to 9b, the display substrate may include:

[0178] The substrate 100 may include a display area AA and a first border area B1 located on at least one side of the display area AA.

[0179] Multiple sub-pixels PX are located on one side of the substrate 100 and in the display area AA;

[0180] Multiple data lines DL are located in the display area AA and are electrically connected to multiple sub-pixels PX;

[0181] Multiple data line leads 101 are located in the first frame area B1 and are electrically connected to multiple data lines DL;

[0182] Multiple pads 31 are located in the first border region B1 and are electrically connected to multiple data line leads 101; among them,

[0183] At least one of the plurality of pads 31 includes:

[0184] A first insulating layer 102 is located on the side of the plurality of data line leads 101 facing away from the substrate 100. The first insulating layer 102 includes a first opening 110 that exposes at least a portion of at least one of the plurality of data line leads 101.

[0185] A first metal layer 1031 is located on the side of the plurality of data line leads 101 facing away from the substrate 100, and is electrically connected to at least one of the plurality of data line leads 101 through a first opening 110; wherein, the first metal layer 1031 includes a first bottom 1031a and a stepped portion surrounding the first bottom 1031a, the orthographic projection of the first bottom 1031a on the substrate 100 lies within the orthographic projection of the first opening 110 on the substrate 100, and the first bottom 1031a and... At least one of the multiple data line leads 101 is electrically connected. The stepped portion includes a first stepped portion 1031b located on the side of the first insulating layer 102 away from the substrate 100 and a second stepped portion 1031c forming an angle with the first stepped portion 1031b. The second stepped portion 1031c connects the first bottom 1031a and the first stepped portion 1031b. The orthographic projection of the second stepped portion 1031c on the substrate 100 is located in the orthographic projection of the first opening 110 on the substrate 100.

[0186] The second insulating layer 104 is located on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100, wherein the second insulating layer 104 includes a second opening 120 that exposes at least a portion of the first bottom 1031a of the first metal layer 1031.

[0187] In the exemplary embodiment, the side of the first step portion 1031b away from the substrate 100 is covered by the second insulating layer 104 in the same manner.

[0188] In an exemplary embodiment, as shown in Figures 5a to 7 and Figures 9a to 9b, the orthographic projection of the first step portion 1031b on the substrate 100 does not overlap with the orthographic projection of the second insulating layer 104 on the substrate 100. The orthographic projection of the second opening 120 on the substrate 100 covers the orthographic projections of the first opening 110, the first step portion 1031b, and the first bottom 1031a on the substrate 100.

[0189] In an exemplary embodiment, as shown in Figures 8a to 8c, the orthographic projection of the first step portion 1031b on the substrate 100 is covered by the orthographic projection of the second insulating layer 104 on the substrate 100, and the orthographic projection of the second opening 120 on the substrate 100 is located within the range of the orthographic projection of the first opening 110 on the substrate 100.

[0190] In the structures shown in Figures 5a to 9b, the side of the first step portion 1031b away from the substrate 100 is covered by the second insulating layer 104 in a consistent manner (for example, in Figures 5a to 7 and Figures 9a to 9b, the side of the first step portion 1031b away from the substrate 100 is covered by the second insulating layer 104, while in Figures 8a to 8c, the side of the first step portion 1031b away from the substrate 100 is not covered by the second insulating layer 104). The side of the first step portion 1031b away from the substrate is basically flat and without protrusions, which can avoid the formation of subsequent metal layers (such as the subsequent formation of the second metal layer). The third metal layer has a large step difference due to the protrusion on the surface of the first step portion 1031b, which causes cracks. This can prevent the metal layer formed later from being exposed on the side close to the substrate 100 through the cracks. For example, it can prevent the metal of the second metal layer or the metal of the intermediate film layer of the third metal layer from being exposed through the cracks formed by the third metal layer. This can prevent the metal material of the second metal layer (e.g., aluminum) from being replaced by silver ions in the wet etching solution to form silver particles during the etching anode process. It can also prevent the silver particles from being washed into the display area during the etching anode process and the subsequent water washing process, causing a short circuit between the anode and cathode and forming dark spots.

[0191] In an exemplary embodiment, as shown in Figures 5a to 9b, the display substrate may further include:

[0192] The second metal layer 1032 is located on the side of the first metal layer 1031 and the second insulating layer 104 away from the substrate 100. The second metal layer 1032 is electrically connected to the first metal layer 1031 through the second opening 120. The orthographic projection of the second metal layer 1032 on the substrate 100 at least partially overlaps with the orthographic projection of the second opening 120 on the substrate 100.

[0193] In an exemplary embodiment, as shown in Figures 5a to 5b, 6 to 8a, and 9a to 9b, the orthogonal projection of the second metal layer 1032 on the substrate 100 can cover the orthogonal projection of the first metal layer 1031 and the second opening 120 on the substrate 100.

[0194] In an exemplary embodiment, as shown in Figures 5c and 8b to 8c, the orthographic projection of the second metal layer 1032 on the substrate 100 does not overlap with the orthographic projection of the first step portion 1031b of the first metal layer 1031 on the substrate 100; in an exemplary embodiment, as shown in Figures 8b to 8c, the orthographic projection of the second metal layer 1032 on the substrate 100 covers the orthographic projection of the second opening 120 on the substrate 100; in an exemplary embodiment, as shown in Figure 5c, the orthographic projection of the second metal layer 1032 on the substrate 100 is located within the range of the orthographic projection of the second opening 120 on the substrate 100.

[0195] In an exemplary embodiment, as shown in Figures 5a to 9b, the display substrate may further include:

[0196] The third metal layer 1033 is located on the side of the second metal layer 1032 away from the substrate 100. The third metal layer 1033 is electrically connected to the second metal layer 1032, and the orthogonal projection of the third metal layer 1033 on the substrate 100 covers the orthogonal projection of the second metal layer 1032 on the substrate 100.

[0197] In an exemplary embodiment, as shown in Figures 5a to 9b, the display substrate may further include:

[0198] The third insulating layer 106 is located on the side of the third metal layer 1033 facing away from the substrate 100, and the third insulating layer 106 includes a third opening 130.

[0199] As shown in Figures 5b, 6, and 7, the orthographic projection of the third opening 130 on the substrate 100 lies within the orthographic projections of the first opening 110 and the second opening 120 on the substrate 100; or, as shown in Figures 8a to 8c, the orthographic projections of the first opening 110 and the second opening 120 on the substrate 100 lie within the orthographic projection of the third opening 130 on the substrate 100; or, as shown in Figures 5a, 5c, and 9a to 9b, the orthographic projection of the third opening 130 on the substrate 100 lies within the range of the orthographic projection of the second opening 120 on the substrate 100, and the orthographic projection of the first opening 110 on the substrate 100 lies within the range of the orthographic projection of the third opening 130 on the substrate 100.

[0200] In an exemplary embodiment, the third insulating layer 106 may include at least one of an inorganic insulating layer and an organic insulating layer.

[0201] In an exemplary embodiment, as shown in Figures 5a to 8b and 9a to 9b, the first metal layer 1031 may further include a second bottom 1031e surrounding the step portion, and the step portion may further include a third step portion 1031d forming an angle with the first step portion 1031b. The third step portion 1031d connects the second bottom 1031e and the first step portion 1031b. The orthographic projection of the second insulating layer 104 on the substrate 100 at least partially overlaps with the orthographic projection of the second bottom 1031e on the substrate 100.

[0202] In an exemplary embodiment, as shown in Figures 9a and 9b, the third insulating layer 106 may include a first insulator layer 1061 and a second insulator layer 1062, wherein the second insulator layer 1062 is located on the side of the first insulator layer 1061 that is away from the substrate 100.

[0203] In an exemplary embodiment, as shown in FIG9a, the material of the first insulator layer 1061 may be an organic material, and the material of the second insulator layer 1062 may be an inorganic material. The orthographic projection of the first insulator layer 1061 on the substrate 100 does not overlap with the orthographic projection of the step portion (e.g., the first step portion 1031b, the second step portion 1031c, and the third step portion 1031d in the step portion) on the substrate 100. The orthographic projection of the second insulator layer 1062 on the substrate 100 covers at least a portion of the orthographic projection of the step portion (e.g., the first step portion 1031b and a portion of the third step portion 1031d in the step portion) on the substrate 100.

[0204] In an exemplary embodiment, as shown in FIG9b, the materials of the first insulator layer 1061 and the second insulator layer 1062 may be organic materials. The orthographic projection of the first insulator layer 1061 on the substrate 100 does not overlap with the orthographic projection of at least a portion of the step portion (e.g., the first step portion 1031b and the second step portion 1031c in the step portion) on the substrate 100. The orthographic projection of the second insulator layer 1062 on the substrate 100 covers the orthographic projection of at least a portion of the step portion (e.g., the first step portion 1031b and the third step portion 1031d in the step portion) on the substrate 100.

[0205] In an exemplary embodiment, as shown in FIG9a, the orthographic projection of the first insulator layer 1061 on the substrate 100 may not overlap with the orthographic projection of the second bottom layer 1031e on the substrate 100; as shown in FIG9b, the orthographic projection of the first insulator layer 1061 on the substrate 100 may overlap with the orthographic projections of the second bottom layer 1031e and at least a portion of the third step portion 1031d on the substrate 100.

[0206] In an exemplary embodiment, as shown in Figures 5a, 5c to 9b, the display substrate may further include:

[0207] The fourth metal layer 108 is located on the side of the third metal layer 1033 and the third insulating layer 106 away from the substrate 100. The fourth metal layer 108 can be electrically connected to the third metal layer 1033 through the third opening 130. The orthographic projection of the fourth metal layer 108 on the substrate 100 at least partially overlaps with the orthographic projection of the third metal layer 1033 on the substrate 100. For example, the orthographic projection of the fourth metal layer 108 on the substrate 100 can cover the orthographic projection of the third metal layer 1033 on the substrate 100.

[0208] In an exemplary embodiment, as shown in Figures 5a, 5c to 9b, the display substrate may further include:

[0209] The fourth insulating layer 107 is located in the direction Z perpendicular to the plane of the substrate 100. The fourth insulating layer 107 may be located between the third insulating layer 106 and the fourth metal layer 108. The fourth insulating layer 107 may include a fourth opening 140. The orthographic projection of the fourth opening 140 on the substrate 100 is located within the orthographic projection of the third opening 130 on the substrate 100. The fourth metal layer 108 may be electrically connected to the third metal layer 1033 through the third opening 130 and the fourth opening 140.

[0210] In an exemplary embodiment, as shown in 8c, a structural schematic diagram of the first metal layer 1031 without the second bottom 1031e and the third step portion 1031d is provided.

[0211] In an exemplary embodiment, as shown in Figures 8a to 8c, the orthographic projection of the second insulating layer 104 on the substrate 100 partially overlaps with the orthographic projection of the first bottom layer 1031a on the substrate 100, and the orthographic projection of the second opening 120 on the substrate 100 is located within the orthographic projection of the first opening 110 on the substrate 100.

[0212] In an exemplary embodiment, as shown in Figures 5a to 7 and Figures 9a to 9b, the orthographic projection of the second insulating layer 104 on the substrate 100 does not overlap with the orthographic projections of the first bottom 1031a and the step portion on the substrate 100, and the orthographic projection of the second opening 120 on the substrate 100 covers the orthographic projection of the first opening 110 on the substrate 100.

[0213] In an exemplary embodiment, as shown in Figures 5a to 9b, the size d1 of the first opening 110 along the width direction (i.e., along the first direction X) can be 3 micrometers to 11 micrometers.

[0214] In an exemplary embodiment, as shown in Figures 5a to 6 and Figures 8a to 9b, the dimension d1 of the first opening 110 along the width direction can be 3 micrometers to 6 micrometers. For example, the dimension d1 of the first opening 110 along the width direction can be 6.8 micrometers.

[0215] In an exemplary embodiment, as shown in FIG7, the dimension d1 of the first opening 110 along the width direction can be 5 micrometers to 8 micrometers, for example, the dimension d1 of the first opening 110 along the width direction can be 6.8 micrometers. In the structure shown in FIG7, the dimension d1 of the first opening 110 along the width direction is enlarged compared with the width dimension d1 of the first opening 110 shown in FIG5a to FIG6 and FIG8a to FIG9b. This allows the stacking structure of the third metal layer 1033 subsequently formed in the pad 31 to be consistent at the step portion (e.g., the first step portion 1031b and the second step portion 1031c). This avoids cracks in the second metal layer 1032 and the third metal layer 1033 formed after the first metal layer 1031 due to process waveguide, and minimizes the exposure of the second metal layer 1032 due to cracks in the third metal layer 1033.

[0216] In an exemplary embodiment, in the direction Z perpendicular to the plane of the substrate 100, among the multiple metal film layers located between the substrate 100 and the first electrode 301 (anode) in the pad 31, the metal particles in the metal film layer closest to the first electrode 301 have the lowest activity. This avoids the metal particles in the metal film layer closest to the first electrode 301 being replaced by metal ions in the wet etching solution during the etching process of the first electrode 301 (e.g., replacing silver ions in the wet etching solution with silver particles). In an exemplary embodiment, the activity of the metal particles in the metal film layer closest to the first electrode 301 is not greater than the activity of the metal ions in the wet etching solution for etching the first electrode 301. For example, if the metal film layer closest to the first electrode 301 is the third metal layer 1033, then the activity of the metal particles in the metal layer closest to the first electrode 301 in the third metal layer 1033 is not greater than the activity of the metal corresponding to the metal ions in the subsequent wet etching solution for the first electrode 301 (e.g., the metallic silver corresponding to silver ions in the wet etching solution).

[0217] In an exemplary embodiment, the third metal layer 1033 can be a single-layer structure, and the metal activity in the metal layer of the second metal layer 1032 closest to the third metal layer 1033 is not less than the metal activity in the third metal layer 1033. For example, in a structure where the first metal layer 1031, the second metal layer 1032, and the third metal layer 1033 are all single-layer structures, the activity of the metal particles in the third metal layer 1033 is less than the activity of the metal particles in the first metal layer 1031 and the second metal layer 1032. For example, the first metal layer 1031 and the second metal layer 1032 can be made of aluminum, and the third metal layer 1033 can be made of titanium or molybdenum. In a multilayer composite structure where the first metal layer 1031 and the second metal layer 1032 are multilayered and the third metal layer 1033 is a single layer, the metal activity in the third metal layer 1033 is not greater than the metal activity in the metal layer of the second metal layer 1032 that is closest to the third metal layer 1033. For example, the first metal layer 1031 and the second metal layer 1032 are multilayer composite structures using Ti / Al / Ti, and the material of the third metal layer 1033 can be titanium or molybdenum.

[0218] In an exemplary embodiment, the third metal layer 1033 can be a multilayer composite structure. In the direction Z perpendicular to the plane of the substrate, the metal activity in the metal layer of the third metal layer 1033 that is farthest from the second metal layer 1032 is not greater than the metal activity in the metal layer between the farthest metal layer and the second metal layer 1032. As shown in FIG9d, the third metal layer 1033 may include a first third metal sublayer 10331, a second third metal sublayer 10332, and a third third metal sublayer 10333. Then, the metal activity in the third third metal sublayer 10333 is not greater than the metal activities in the first third metal sublayer 10331 and the second third metal sublayer 10332. For example, the metal activity in the first third metal sublayer 10331 is less than the metal activity in the second third metal sublayer 10332. In an exemplary embodiment, the metals of the first third metal sublayer 10331 and the third third metal sublayer 10333 can be titanium (Ti), and the metal of the second third metal sublayer 10332 can be aluminum (Al), that is, the third metal layer 1033 is a multilayer composite structure using Ti / Al / Ti. In an exemplary embodiment, the activity of the metal material in the metal layer closest to the first electrode 301 in the third metal layer 1033 is not greater than the activity of the metal ions in the wet etching solution of the etching anode. This can prevent the metal in the metal layer closest to the first electrode 301 in the third metal layer 1033 from being replaced by the metal ions in the wet etching solution to form corresponding metal particles. This can prevent the replaced metal particles from being washed into the display area during the etching of the anode and subsequent water washing processes (such as cleaning the fabricated anode), causing a short circuit between the anode and cathode.

[0219] In the structures shown in Figures 9c and 9d, a bump structure composed of a first metal layer 1031, a second metal layer 1032, and a third metal layer 1033 is formed around the edge of the first opening 110. The surface of the first step portion 1031b away from the substrate 100 is covered by the second insulating layer 104 in an inconsistent manner; that is, part of the surface of the first step portion 1031b away from the substrate 100 is covered by the second insulating layer 104, and part is not covered by the second insulating layer 104. This results in a large step difference in the third metal layer 1033 at the edge of the first opening 110 (also near the first step portion 1031b), leading to... The three-metal layer 1033 is prone to cracks Q1 at the first step 1031b, exposing the second metal layer 1032 (as shown in Figure 9c) or the more active metal layer in the middle of the third metal layer 1033 (as shown in Figure 9d). This causes the exposed second metal layer 1032 or the more active metal layer in the middle of the exposed third metal layer 1033 to replace the silver ions in the wet etching solution during the anode manufacturing process to form silver particles. The silver particles flow to the anode opening position of the display area AA under the scouring of the wet etching solution or the subsequent scouring of the anode washing solution, causing a short circuit between the anode (i.e., the first electrode 301) and the cathode (i.e., the second electrode 302) in the display area, forming a dark spot. In this embodiment of the disclosure, the surface of the first step portion 1031b away from the substrate 100 is covered by the second insulating layer 104 in a consistent manner through the structure shown in Figures 5a to 9b. This can largely avoid the problem of cracks in the third metal layer 1033 due to the large positional difference of the first step 1031b, thereby reducing the risk of dark spots in the display area AA caused by cracks in the third metal layer 1033.

[0220] In an exemplary embodiment, as shown in Figures 2 and 5a to 9b, the first insulating layer 102 can be disposed in the same layer as the interlayer insulating layer 203 and the second gate insulating layer 202; the second insulating layer 104 can be disposed in the same layer as the passivation layer 204; the third insulating layer 106 can be disposed in the same layer as the third planarization layer 207; and the fourth insulating layer 107 can be disposed in the same layer as at least one of the touch interlayer insulating layer 502 and the pixel definition layer 304. Between the substrate and the multiple data line leads (i.e., the gate metal layers), a barrier layer, a buffer layer, etc., can also be arranged, as indicated by film layer 105 in Figures 5a to 9b. The first metal layer 1031 can be disposed in the same layer as the first source-drain metal layer; the second metal layer 1032 can be disposed in the same layer as the second source-drain metal layer; the third metal layer 1033 can be disposed in the same layer as the third source-drain metal layer; and the fourth metal layer 108 can be disposed in the same layer as one of the first touch conductive layer and the second touch conductive layer. In exemplary embodiments, the third insulating layer 106 is not limited to being disposed in the same layer as the third planarization layer 207. For example, as shown in Figures 9a and 9b, the first insulator layer 1061 may be disposed in the same layer as the third planarization layer 207 (the opening of the third planarization layer 207 at the pad 31 position covers the second opening 120 of the second insulator layer 1062 at the pad 31 position), or, in the direction Z perpendicular to the plane of the substrate 100, the first insulator layer 1061 may be located between the third planarization layer 207 and the second insulator layer 1062; as shown in Figures 5a to 8c, the third insulating layer 106 may be disposed in the same layer as the third planarization layer 207, or, in the direction Z perpendicular to the plane of the substrate 100, the third insulating layer 106 may be located between the third planarization layer 207 and the first electrode 301 (i.e., the anode).

[0221] In an exemplary embodiment, the substrate 100 may be a flexible substrate, such as PEN resin, silicone resin, polyimide, etc. The first insulating layer, the second insulating layer, and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The first planarization layer, the second planarization layer, and the third planarization layer may be made of organic materials, such as PEN resin, silicone resin, polyimide, etc. The data cable leads, the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti, Mo / Cu / Mo, etc. In an exemplary embodiment, where the first metal layer, the second metal layer, and the third metal layer are single-layer structures, the metal activity of the third metal layer is not greater than that of the first metal layer and the second metal layer, and the metal activity of the third metal layer is not greater than that of the metal ions in the wet etching solution used to fabricate the anode. For example, the first metal layer and the second metal layer can be made of aluminum, and the third metal layer can be made of silver. In a multilayer composite structure consisting of a first metal layer, a second metal layer, and a third metal layer, if the third metal layer is a two-layer structure, the metal activity in the layer away from the second metal layer is less than that in the layer closer to the second metal layer. If the third metal layer is a three-layer structure, in the direction perpendicular to the plane of the substrate, the metal activity in the middle metal layer is greater than that in the metal layers on both sides. For example, in the direction perpendicular to the plane of the substrate, the third metal layer may include a titanium (Ti) film layer, an aluminum (Al) film layer, and a titanium (Ti) film layer sequentially disposed on the side of the second metal layer away from the substrate, i.e., the third metal layer adopts a Ti-Al-Ti three-layer composite structure. In an exemplary embodiment, the first metal layer, the second metal layer, and the third metal layer can all adopt a Ti-Al-Ti three-layer composite structure, and the data line lead 101 can adopt a molybdenum (Mo) or aluminum (Al) single-layer structure.

[0222] In an exemplary embodiment, metal activity refers to the tendency of a metal element to lose electrons and generate metal cations in an aqueous solution. The easier a metal is to lose electrons and generate metal cations, the greater its activity. For example, silver (Ag) has less activity than titanium (Ti), and titanium (Ti) has less activity than aluminum (Al).

[0223] In an exemplary embodiment, as shown in Figures 10a to 12b, Figures 10a and 10b are schematic diagrams of a planar structure of a display substrate, Figures 11a to 11d are schematic diagrams of several cross-sectional structures at position M1-M1 in Figures 10a and 10b, and Figures 12a to 12c are schematic diagrams of several cross-sectional structures at position M2-M2 in Figures 10a and 10b. The substrate 100 may include an encapsulation region A1 and an edge region BB2 located around the encapsulation region A1. The edge region BB2 includes a bonding region B0 on ​​the side where at least one edge of the substrate 100 is located, and the bonding region B0 is located in the first border region B1.

[0224] Multiple inorganic film layers are stacked on one side of the substrate 100;

[0225] A plurality of first grooves C1 are located in the edge region BB2 and are arranged sequentially at intervals in the direction away from the encapsulation region A1, and partially surround the encapsulation region A1. Each first groove C1 penetrates at least one of the plurality of inorganic film layers, and the orthographic projection of the plurality of first grooves C1 on the substrate 100 does not overlap with the bonding region.

[0226] Organic layer 03 covers multiple first grooves C1.

[0227] In an exemplary embodiment, as shown in FIG10a, the bonding area B0 may include a fan-out routing area B11 and a signal access area B12. In an exemplary embodiment, as shown in FIG10b, the bonding area B0 may include a fan-out routing area B11, a signal access area B12, and a bending area B13.

[0228] In an exemplary embodiment, as shown in FIG12a, the organic layer 03 may include a first planarization layer 205 and a second planarization layer 206 sequentially stacked along a direction Z away from the substrate 100. The first planarization layer 205 covers a plurality of first grooves C1, and the second planarization layer 206 is located on the side of the first planarization layer 205 away from the substrate 100.

[0229] In an exemplary embodiment, as shown in FIG12b, the organic layer 03 covering the first groove C1 only has a first planarization layer 205 and no second planarization layer 206. There is usually residue ML of the first metal layer 1031 at the location of the first groove C1. If the thickness of the first planarization layer 205 is insufficient, the residue ML will pierce the first planarization layer 205 and be exposed. During the etching of the first electrode 301 (anode), the residue ML replaces silver ions in the wet etching solution to form silver particles. The silver particles will be washed to the opening position of the anode during the etching of the first electrode 301 and the subsequent water washing process (such as cleaning the completed anode), causing a short circuit between the anode and the cathode in the display area to form a dark spot. In the structures shown in Figures 12a and 12c, the organic layer 03 covering the first groove C1 may include a first planarization layer 205 and a second planarization layer 206. The residue ML is generally unable to pierce the second planarization layer 206 (which can prevent the residue ML from being exposed), thereby preventing the residue ML at the location of the first groove C1 from being exposed and reducing the risk of forming a dark spot due to a short circuit between the anode and cathode caused by the residue in the first groove C1.

[0230] In an exemplary embodiment, as shown in FIG11b and FIG12a, the first insulating layer 102 may include a gate insulating layer (which may include a second gate insulating layer 202) and an interlayer dielectric layer 203 sequentially stacked along a direction Z away from the substrate 100, and at least one inorganic film layer may include a gate insulating layer (which may include a first gate insulating layer 201 and a second gate insulating layer 202) and an interlayer dielectric layer 203.

[0231] In an exemplary embodiment, as shown in Figures 11a to 12a, an inorganic film layer between each two adjacent first grooves C1 constitutes a blocking portion ZL; the plurality of inorganic film layers may further include: a buffer layer 1502 located between the substrate 100 and the gate insulating layer 201 in a direction Z perpendicular to the plane of the substrate 100, as shown in Figures 11c and 11d, at least one inorganic film layer may further include at least a portion of the buffer layer 1502.

[0232] In an exemplary embodiment, since the plurality of first grooves C1 are located within the edge region BB2 and there is a gap between them and the encapsulation region A1, the plurality of first grooves C1 can block cracks that appear at the edge of the display substrate, preventing the cracks from extending into the encapsulation region A1. Since the plurality of first grooves C1 can block the extension of cracks, the inorganic film layer between two adjacent first grooves C1 can form a blocking part ZL, which can also be called a crack dam.

[0233] In an exemplary embodiment, as shown in Figures 11a to 12a, the plurality of inorganic film layers may further include a barrier layer 1501 located between the substrate 100 and the buffer layer in a direction Z perpendicular to the plane of the substrate 100. As shown in Figure 11d, at least one inorganic film layer may further include at least a partial barrier layer. By first forming a barrier layer 1501 made of inorganic material on the side away from the substrate 100, water vapor or oxygen can be effectively blocked from entering the substrate 100, thereby improving the water-blocking, oxygen-blocking, and scratch-resistant properties of the substrate 100.

[0234] Referring to Figures 10a and 10b, it can be seen that the orthographic projection of each first groove C1 on the substrate 100 can be an annular shape with an opening k0 (i.e., the first groove C1 does not overlap with the bonding region B0, and the opening k0 is formed in the bonding region B0). For example, referring to Figures 10a and 10b, it is shown that there are two first grooves C1 with openings in annular shape. Figures 11a and 12a show that there are five first grooves C1. The number of first grooves C1 is not limited to two or five. It can be set according to the actual product. The number of first grooves C1 at different positions in the edge region BB2 can be the same or different (for example, the number of first grooves C1 in the edge region BB2 located in the second border region B2 can be the same or different from the number of first grooves C1 in the edge region BB2 located in the third border region B3 and the fourth border region). Each annular shape (i.e., each first groove C1) can surround the packaging region A1, and the orthographic projection of each opening k0 on the substrate 100 can at least partially overlap with the bonding region B0, that is, the width of each opening (the dimension along the first direction X) can be greater than the width of the bonding region B0. In an exemplary embodiment, the first slot C1 can be disconnected at the opening k0 position (i.e., the first slot C1 can be disconnected in the binding area B0), and the area outside the opening k0 of the first slot C1 can also be disconnected.

[0235] In an exemplary embodiment, as shown in FIG2, the display area of ​​the display substrate may include: a gate metal layer on the substrate 100, a gate insulating layer (201, 202) on the side of the gate metal layer away from the substrate 100, and a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged sequentially on the side of the gate insulating layer (201, 202) away from the substrate 100.

[0236] In the direction Z perpendicular to the plane of the substrate 100, the first planarization layer 205 may be located between the first source / drain metal layer and the second source / drain metal layer, and the second planarization layer may be located between the second source / drain metal layer and the third source / drain metal layer.

[0237] In an exemplary embodiment, as shown in FIG2, a plurality of data line leads 101 may be disposed in the same layer as the gate metal layer, a first insulating layer 102 may be disposed in the same layer as the gate insulating layer, a first metal layer 1031 may be disposed in the same layer as the first source-drain metal layer, a second metal layer 1032 may be disposed in the same layer as the second source-drain metal layer, and a third metal layer 1033 may be disposed in the same layer as the third source-drain metal layer.

[0238] In an exemplary embodiment, as shown in Figures 10a to 12a, the plurality of first grooves C1 in the display substrate can be arranged at equal intervals, that is, the distance between any two adjacent first grooves C1 can be a fixed value. By arranging the plurality of first grooves C1 at intervals, the propagation of cracks can be further effectively avoided, ensuring the quality of the display substrate.

[0239] In an exemplary embodiment, the difference between FIG12a and FIG2 is that FIG12a does not have a third source / drain metal layer and a third planarization layer 207. Since the third source / drain metal layer is not provided in the structure shown in FIG12a, the structure of the corresponding pad 31 may include a first metal layer 1031 and a second metal layer 1032.

[0240] In an exemplary embodiment, as shown in Figures 10a, 10b, and 12a, the encapsulation region A1 may include a display region AA and a peripheral region BB1 surrounding the display region AA. The border region BB may include the peripheral region BB1 and an edge region BB2. The peripheral region BB1 may be provided with peripheral circuitry, and the edge region BB2 may be provided with a first recess C1. In Figure 12a, T1 is one transistor located in the display region AA, T2 and T3 are two transistors located in the peripheral region BB1, and 22-1 and 22-2 are two capacitors located in the peripheral region BB1. In the peripheral region BB1, the low-voltage line VGL is electrically connected to the second electrode 303 through the third transition electrode 233 and the fourth transition electrode 234.

[0241] In an exemplary embodiment, as shown in Figures 10a, 10b, and 12a, a barrier dam 04 can be provided in the peripheral region BB1. This barrier dam 04 can also be made of organic material. The orthographic projection of the organic layer 03 onto the substrate 01 does not need to overlap with the orthographic projection of the barrier dam 04 onto the substrate 01. Since the barrier dam 04 is located within the peripheral region BB1, a gap D11 exists between the barrier dam 04 and the display region AA. This effectively prevents the organic material from flowing out of the encapsulation region AA when forming the organic encapsulation film layer in the encapsulation film using organic materials. Furthermore, it effectively prevents moisture in the air from entering the display region due to the hydrophilic properties of the organic material, thus affecting the display region's quality and further ensuring the quality of the display substrate.

[0242] In an exemplary embodiment, as shown in Figures 10a, 10b, and 12a, the barrier dam 04 may include at least one closed annular structure 041, each annular structure 041 surrounding the display area AA of the substrate 100. By surrounding the display area AA with the annular structures 041, effective protection of the display area AA can be achieved.

[0243] In an exemplary embodiment, as shown in Figures 10a, 10b, and 12a, the barrier dam 04 may include a plurality of spaced-apart annular structures 041. For example, Figures 10a and 10b both show a barrier dam 04 including two annular structures 041. Furthermore, the plurality of annular structures 041 may be equally spaced, meaning the spacing between any two adjacent annular structures 041 may be a fixed value. By spaced-aparting the plurality of annular structures 041, effective protection of the display area AA can be further improved. For example, the barrier dam 04 may be formed by deposition.

[0244] In this embodiment, the substrate 100 can be made of a flexible material. This flexible material can be polyimide (PI), which has good properties such as high temperature resistance, low temperature resistance, and oxidation resistance.

[0245] In an exemplary embodiment, as shown in Figures 10a and 10b, the edge region BB2 of the substrate 100 may also be provided with a cutting line L1 surrounding the first groove C1. After an inorganic film layer with multiple first grooves C1 is formed on one side of the substrate 01, it can be cut along the cutting line L1 to obtain a display substrate. Accordingly, the annular first groove C1 can be designed along the shape of the cutting line L1. Since cracks are prone to appear at the edge of the display substrate during the cutting operation, by designing the first groove C1 along the shape of the cutting line L1, the cracks generated during the cutting operation can be effectively blocked, that is, the extension of cracks that occur during the cutting operation can be effectively avoided.

[0246] Taking the structure in Figure 5a as an example, the fabrication method of the pad 31 in the display substrate is described as follows: A metal thin film, such as a gate metal thin film, is fabricated on one side of the substrate 100. Data line leads 101 as shown in Figure 13a are formed by a patterning process. Then, a first insulating layer 102 is fabricated. The first insulating layer 102 can be an insulating layer composed of a gate insulating layer and an interlayer insulating layer. A first opening 110 is etched on the first insulating layer 102 to expose at least a portion of the data line leads. Next, a first source-drain metal thin film is formed on the side of the data line leads 101 and the first insulating layer 102 away from the substrate 100. The first source-drain metal thin film is patterned by a patterning process to form a first metal layer 1031 as shown in Figure 13b. Next, a second insulating layer 104 as shown in Figure 13c is formed on the sidewall of the first metal layer 1031 to prevent metal elements (e.g., Al) in the first metal layer from being exposed and causing corrosion or dark spots. The second insulating layer 104 has a second opening 120 that exposes the first metal layer 1031. Next, a second source / drain metal thin film is formed. The second source / drain metal thin film is patterned using a patterning process to form a second metal layer 1032 as shown in FIG13d. Next, a third source / drain metal thin film is formed. The third source / drain metal thin film is patterned using a patterning process to form a third metal layer 1033 as shown in FIG13e. Next, a third insulating layer 106 as shown in FIG13f is prepared on the side of the third metal layer 1033 away from the substrate 100. The third insulating layer 106 can be disposed on the same layer as the third planarization layer. A third sub-opening 1301 exposing the third metal layer 1033 is etched on the third insulating layer 106. The orthographic projection of the third sub-opening 1301 onto the substrate 100 is located within the area of ​​the first opening 110 within the substrate 100. Next... In the process of forming the pixel definition layer 30 of the light-emitting structure layer 30, the encapsulation structure layer 40, and the touch structure layer 50 in the display area AA on the side of the third insulating layer 106 away from the substrate 100, a fourth insulating layer 107 in the pad 31 as shown in FIG13g is formed during the process of forming the pixel definition layer 304 of the light-emitting structure layer 30 or the touch interlayer insulating layer (TLD) 502 of the touch structure layer 50. A third opening 130 is formed at the same time as forming the fourth opening 140 in the fourth insulating layer 107. A fourth metal layer 108 as shown in FIG5a is formed during the process of forming the second touch conductive layer 512 in the touch structure layer 50.In the preparation process shown in Figures 13a to 13f, before the anode is formed, the third insulating layer 106 can wrap the third metal layer 1033 at the position corresponding to the first step 1301b. This can prevent the second metal layer 1032 exposed by the cracks in the third metal layer 1033 during the anode preparation process, or the more active metal film layer in the middle of the exposed third metal layer 1033, from being replaced by metal ions in the anode wet etching solution to form metal particles. This can prevent metal particles from washing over the display area, causing a short circuit between the anode and cathode and forming dark spots.

[0247] Taking the structure in Figure 6 as an example, the method of preparing the pad 31 in the display substrate is explained as follows: The method of forming the data line lead 101 to forming the third insulating layer 106 is the same as that in Figures 13a to 13f. The third sub-opening 1301 in Figure 13f can be used as the third opening 130. The light-emitting structure layer 30, the encapsulation structure layer 40, and the touch structure layer 50 in the display area AA are prepared on the side of the third insulating layer 106 away from the substrate 100. During the process of forming the pixel definition layer 304 of the light-emitting structure layer 30 or the touch interlayer insulating layer (TLD) 502 of the touch structure layer 50, the fourth insulating layer 107 in the pad 31 as shown in Figure 14 is formed. The fourth opening 140 is formed on the fourth insulating layer 107. During the process of preparing the second touch conductive layer 512 in the touch structure layer 50, the fourth metal layer 108 as shown in Figure 6 is formed. The orthographic projection of the third opening 130 on the substrate is within the range of the orthographic projection of the first opening 110 on the substrate. Before forming the anode, the third insulating layer 106 can wrap the third metal layer 1033 at the position corresponding to the first step 1301b. This can prevent the second metal layer 1032 exposed by the cracks in the third metal layer 1033 during the anode preparation process, or the more active metal film layer in the middle of the exposed third metal layer 1033, from being replaced by metal ions in the anode wet etching solution to form metal particles. This can prevent metal particles from scouring the display area and causing a short circuit between the anode and cathode, resulting in dark spots.

[0248] This disclosure also provides a method for manufacturing a display substrate as described in any of the above embodiments, forming a display substrate as shown in FIG1a, FIG1b, and FIG3 to FIG9b, the method including:

[0249] A substrate 100 is provided, the substrate 100 including a display area AA and a first border area B1 located on at least one side of the display area AA;

[0250] Multiple sub-pixels PX, multiple data lines DL, and multiple data line leads 101 are prepared on one side of the substrate 100. The multiple sub-pixels PX and multiple data lines DL are located in the display area AA and the multiple sub-pixels PX are electrically connected to the multiple data lines DL. The multiple data line leads 101 are located in the first border area B1 and are electrically connected to the multiple data lines DL.

[0251] The steps of creating a plurality of pads 31 in the first border region B1, wherein the steps of creating at least one pad 31 of the plurality of pads 31 include:

[0252] A first insulating layer 102 is formed on the side of the plurality of data line leads 101 away from the substrate 100. The first insulating layer 102 includes a first opening 110 that exposes at least a portion of at least one of the plurality of data line leads 101.

[0253] A first metal layer 1031 is formed on the side of the plurality of data line leads 101 facing away from the substrate 100. The first metal layer 1031 is electrically connected to at least one of the plurality of data line leads 101 through a first opening 110. The first metal layer 1031 includes a first bottom 1031a and a stepped portion surrounding the first bottom 1031a. The orthographic projection of the first bottom 1031a on the substrate 100 lies within the orthographic projection of the first opening 110 on the substrate 100. 031a is electrically connected to one of the multiple data line leads 101. The stepped portion includes a first stepped portion 1031b located on the side of the first insulating layer 102 away from the substrate 100 and a second stepped portion 1031c forming an angle with the first stepped portion 1031b. The second stepped portion 1031c connects the first bottom 1031a and the first stepped portion 1031b. The orthographic projection of the second stepped portion 1031c on the substrate 100 is located in the orthographic projection of the first opening 110 on the substrate 100.

[0254] A second insulating layer 104 is formed on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100. The second insulating layer 104 includes a second opening 120 that exposes at least a portion of the first bottom 1031a of the first metal layer 1031, and the side of the first step portion 1031b away from the substrate 100 is covered by the second insulating layer 104 in the same manner.

[0255] In an exemplary embodiment, as shown in Figures 5a to 7 and Figures 9a to 9b, the orthographic projection of the first step portion 1031b on the substrate 100 does not overlap with the orthographic projection of the second insulating layer 104 on the substrate 100. The orthographic projection of the second opening 120 on the substrate 100 covers the orthographic projections of the first opening 110, the first step portion 1031b, and the first bottom 1031a on the substrate 100.

[0256] In an exemplary embodiment, as shown in Figures 8a to 8c, the orthographic projection of the first step portion 1031b on the substrate 100 is covered by the orthographic projection of the second insulating layer 104 on the substrate 100, and the orthographic projection of the second opening 120 on the substrate 100 is located within the range of the orthographic projection of the first opening 110 on the substrate 100.

[0257] In an exemplary embodiment, the method may further include:

[0258] A second metal layer 1032 is formed on the side of the first metal layer 1031 and the second insulating layer 104 away from the substrate 100. The second metal layer 1032 is electrically connected to the first metal layer 1031 through a second opening 120. The orthographic projection of the second metal layer 1032 on the substrate 100 at least partially overlaps with the orthographic projection of the second opening 120 on the substrate 100. The resulting display substrate is shown in Figures 5a to 9b.

[0259] In an exemplary embodiment, the method may further include:

[0260] A third metal layer 1033 is formed on the side of the second metal layer 1032 away from the substrate 100. The third metal layer 1033 is electrically connected to the second metal layer 1032. The orthographic projection of the third metal layer 1033 on the substrate 100 covers the orthographic projection of the second metal layer 1032 on the substrate 100. The resulting display substrate is shown in Figures 5a to 9b.

[0261] In an exemplary embodiment, the method may further include:

[0262] A third insulating layer 106 is formed on the side of the third metal layer 1033 facing away from the substrate 100, wherein the third insulating layer 106 includes a third opening 130.

[0263] As shown in Figures 5b, 6, and 7, the orthographic projection of the third opening 130 on the substrate 100 lies within the orthographic projections of the first opening 110 and the second opening 120 on the substrate 100; or, as shown in Figures 8a to 8c, the orthographic projections of the first opening 110 and the second opening 120 on the substrate 100 lie within the orthographic projection of the third opening 130 on the substrate 100; or, as shown in Figures 5a, 5c, and 9a to 9b, the orthographic projection of the third opening 130 on the substrate 100 lies within the range of the orthographic projection of the second opening 120 on the substrate 100, and the orthographic projection of the first opening 110 on the substrate 100 lies within the range of the orthographic projection of the third opening 130 on the substrate 100.

[0264] In an exemplary embodiment, the method may further include:

[0265] A third insulating layer 106, as shown in FIG13f, is formed on the side of the third metal layer 1033 facing away from the substrate 100. The third insulating layer 106 includes a third sub-opening 1301. The orthographic projection of the third insulating layer 106 on the substrate 100 covers the step portion (e.g., the first step portion 1031b, the second step portion 1031c and the third step portion 1031d in the step portion) and part of the first bottom portion 1031a on the substrate 100. The orthographic projection of the third sub-opening 1301 on the substrate 100 is located within the orthographic projection of the first opening 110 on the substrate 100.

[0266] An anode conductive layer is formed on the side of the third insulating layer 106 away from the substrate 100. The anode conductive layer includes a plurality of anodes (i.e., the first electrode 301).

[0267] A fourth insulating layer 107, as shown in FIG13g, is formed on the side of the anode conductive layer away from the substrate 100, and a third opening 130 corresponding to the third sub-opening 1301 is formed in the third insulating layer 106. The fourth insulating layer 107 includes a fourth opening 140. The orthographic projection of the fourth opening 140 on the substrate 100 is located within the orthographic projection of the third opening 130 on the substrate 100. The orthographic projection of the third sub-opening 1301 on the substrate 100 is located within the orthographic projection of the corresponding third opening 130 on the substrate 100.

[0268] In an exemplary embodiment, the orthographic projection of the third sub-opening 1301 on the substrate 100 is located within the orthographic projection of the corresponding third opening 130 on the substrate 100. During the fabrication of the anode (i.e., the first electrode 301), the third insulating layer 106 can wrap the third metal layer 1033 at the position corresponding to the first step 1301b. This can prevent the second metal layer 1032 exposed by the cracks in the third metal layer 1033 during the anode fabrication process, or the highly active metal film layer in the middle of the exposed third metal layer 1033, from being replaced by metal ions in the anode wet etching solution to form metal particles. This can prevent metal particles from scouring the display area and causing a short circuit between the anode and cathode, resulting in dark spots.

[0269] In an exemplary embodiment, as shown in FIG13f, the width dimension d3 of the third sub-opening 1301 can be 2 micrometers to 5 micrometers, and as shown in FIG13g and FIG5a, the width dimension d4 of the third opening 130 can be 5 micrometers to 9 micrometers.

[0270] In an exemplary embodiment, in the structures shown in FIG6 and FIG5b, the width dimension d4 of the third opening 130 can be 2 micrometers to 6 micrometers.

[0271] In an exemplary embodiment, as shown in Figures 5a to 8b and 9a to 9b, the first metal layer 1031 may further include a second bottom 1031e surrounding the step portion, and the step portion may further include a third step portion 1031d forming an angle with the first step portion 1031b. The third step portion 1031d connects the second bottom 1031e and the first step portion 1031b, and the orthographic projection of the second insulating layer 104 on the substrate 100 at least partially overlaps with the orthographic projection of the second bottom 1031e on the substrate 100.

[0272] In an exemplary embodiment, as shown in Figures 8a to 8c, the orthographic projection of the second insulating layer 104 on the substrate 100 partially overlaps with the orthographic projection of the first bottom layer 1031a on the substrate 100, and the orthographic projection of the second opening 120 on the substrate 100 is located within the orthographic projection of the first opening 110 on the substrate 100.

[0273] In an exemplary embodiment, as shown in Figures 5a to 7 and Figures 9a to 9b, the orthographic projection of the second insulating layer 104 on the substrate 100 does not overlap with the orthographic projections of the first bottom 1031a and the stepped portions (e.g., the first stepped portion 1031b, the second stepped portion 1031c, and the third stepped portion 1031d) on the substrate 100, and the orthographic projection of the second opening 120 on the substrate 100 covers the orthographic projection of the first opening 110 on the substrate 100.

[0274] In an exemplary embodiment, as shown in Figures 10a to 12b, the substrate 100 may include a packaging region A1 and an edge region BB2 surrounding the packaging region A1. The edge region BB2 includes a bonding region on the side where at least one edge of the substrate 100 is located, and the bonding region is located in the first border region B1. The method may further include:

[0275] Multiple stacked inorganic film layers are formed on one side of the substrate 100 using inorganic materials;

[0276] A plurality of first grooves C1 are formed in the edge region BB2 and in the direction away from the encapsulation region A1, and are spaced apart and extend along the periphery of the substrate 100. Each first groove C1 penetrates at least one of the plurality of inorganic film layers. The orthographic projection of the plurality of first grooves C1 on the substrate 100 does not overlap with the bonding region.

[0277] An organic layer 03 is formed by using organic materials to cover multiple first grooves C1.

[0278] In an exemplary embodiment, as shown in FIG12a, the organic layer 03 may include a first planarization layer 205 and a second planarization layer 206 sequentially stacked along a direction Z away from the substrate 100, wherein the first planarization layer 205 and the second planarization layer 206 are located on the side of the plurality of inorganic film layers away from the substrate 100.

[0279] The first insulating layer 102 may include a gate insulating layer (201 / 202) and an interlayer dielectric layer (203) sequentially stacked along the direction Z away from the substrate 100, and at least one inorganic film layer may include the gate insulating layer (201 / 202) and the interlayer dielectric layer 203.

[0280] This disclosure also provides a display device, as shown in FIG15, which may include a display substrate. The display substrate may be any of the display substrates provided in the foregoing embodiments, and the implementation principle and effect are similar, and will not be described again here.

[0281] In one exemplary embodiment, the display device can be a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED), or a Light Emitting Diode (LED) display device. The display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0282] The display substrate and display device provided in this disclosure include a plurality of data lines and a plurality of sub-pixels located in a display area, and a plurality of data line leads and a plurality of pads located in a first border area. The plurality of data lines are electrically connected to the plurality of sub-pixels, and the plurality of data line leads are electrically connected to the plurality of data lines and the plurality of pads. At least one of the plurality of pads includes a first insulating layer, a first metal layer, and a second insulating layer sequentially stacked on the side of the data line leads away from the substrate. The first insulating layer has a first opening, and the first metal layer is electrically connected to at least one of the plurality of data line leads through the first opening. The first metal layer includes a first bottom and a surrounding layer. The first bottom has a stepped portion, the orthographic projection of the first bottom onto the substrate is located within the orthographic projection of the first opening onto the substrate, the first bottom is electrically connected to at least one of the multiple data line leads, the stepped portion includes a first stepped portion and a second stepped portion forming an angle with the first stepped portion, the second stepped portion connects the first bottom and the first stepped portion, the orthographic projection of the second stepped portion onto the substrate is located within the orthographic projection of the first opening onto the substrate, the second insulating layer includes a second opening exposing at least a portion of the first bottom; the technical solution provided by the embodiments of this disclosure can, to a certain extent, reduce or avoid the formation of dark spots due to short circuits between the anode and cathode in the display area.

[0283] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0284] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0285] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit them. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: a substrate substrate comprising a display area and a first frame area located at least one side of the display area; a plurality of sub-pixels located at one side of the substrate substrate and in the display area; a plurality of data lines located in the display area and electrically connected with the plurality of sub-pixels; a plurality of data line leads located in the first frame area and electrically connected with the plurality of data lines; a plurality of pads located in the first frame area and electrically connected with the plurality of data line leads; wherein at least one pad of the plurality of pads comprises: a first insulating layer located at one side of the plurality of data line leads away from the substrate substrate, the first insulating layer comprising a first opening exposing at least a portion of at least one data line lead of the plurality of data line leads; a first metal layer located at one side of the plurality of data line leads away from the substrate substrate and electrically connected with at least one data line lead of the plurality of data line leads through the first opening; wherein the first metal layer comprises a first bottom and a stepped portion surrounding the first bottom, a projection of the first bottom on the substrate substrate is located within a projection of the first opening on the substrate substrate, the first bottom is electrically connected with at least one data line lead of the plurality of data line leads, the stepped portion comprises a first stepped portion located at one side of the first insulating layer away from the substrate substrate and a second stepped portion at an included angle with the first stepped portion, the second stepped portion connecting the first bottom and the first stepped portion, a projection of the second stepped portion on the substrate substrate is located in a projection of the first opening on the substrate substrate; a second insulating layer located at one side of the first metal layer and the first insulating layer away from the substrate substrate, wherein the second insulating layer comprises a second opening exposing at least a portion of the first bottom of the first metal layer. 2.The display substrate of claim 1, wherein, a projection of the first stepped portion on the substrate substrate has no overlapping area with a projection of the second insulating layer on the substrate substrate, a projection of the second opening on the substrate substrate covers projections of the first opening, the first stepped portion and the first bottom on the substrate substrate; or, a projection of the first stepped portion on the substrate substrate is covered by a projection of the second insulating layer on the substrate substrate, a projection of the second opening on the substrate substrate is located within a projection of the first opening on the substrate substrate.

3. The display substrate of claim 1, further comprising: a second metal layer located at one side of the first metal layer and the second insulating layer away from the substrate substrate, wherein the second metal layer is electrically connected with the first metal layer through the second opening, a projection of the second metal layer on the substrate substrate at least partially overlaps with a projection of the second opening on the substrate substrate. 4.The display substrate of claim 3, wherein, a projection of the second metal layer on the substrate substrate covers projections of the first metal layer and the second opening on the substrate substrate; or, A normal projection of the second metal layer on the substrate substrate does not overlap with a normal projection of the first step portion of the first metal layer on the substrate substrate, and the normal projection of the second metal layer on the substrate substrate covers a normal projection of the second opening on the substrate substrate. Or, A normal projection of the second metal layer on the substrate substrate does not overlap with a normal projection of the first step portion of the first metal layer on the substrate substrate, and the normal projection of the second metal layer on the substrate substrate is within a range of the normal projection of the second opening on the substrate substrate.

5. The display substrate of claim 3, further comprising: a third metal layer located on a side of the second metal layer away from the substrate substrate, wherein the third metal layer is electrically connected with the second metal layer, and a normal projection of the third metal layer on the substrate substrate covers a normal projection of the second metal layer on the substrate substrate.

6. The display substrate of claim 5, further comprising: a third insulating layer located on a side of the third metal layer away from the substrate substrate, the third insulating layer comprising a third opening; wherein a normal projection of the third opening on the substrate substrate is within normal projections of the first opening and the second opening on the substrate substrate; or, the normal projections of the first opening and the second opening on the substrate substrate are within a normal projection of the third opening on the substrate substrate; or, a normal projection of the third opening on the substrate substrate is within a range of a normal projection of the second opening on the substrate substrate, and a normal projection of the first opening on the substrate substrate is within a range of a normal projection of the third opening on the substrate substrate. 7.The display substrate of claim 6, wherein, The third insulating layer comprises at least one of an inorganic insulating layer and an organic insulating layer. 8.The display substrate of claim 7, wherein, The third insulating layer comprises a first insulating sub-layer and a second insulating sub-layer, the second insulating sub-layer being located on a side of the first insulating sub-layer away from the substrate substrate; a material of the first insulating sub-layer is an organic material, a material of the second insulating sub-layer is an inorganic material, a normal projection of the first insulating sub-layer on the substrate substrate does not overlap with at least part of a normal projection of the step portion on the substrate substrate, and a normal projection of the second insulating sub-layer on the substrate substrate covers at least part of the normal projection of the step portion on the substrate substrate.

9. The display substrate of claim 6, further comprising: a fourth metal layer located on a side of the third metal layer and the third insulating layer away from the substrate substrate, wherein the fourth metal layer is electrically connected with the third metal layer through the third opening, and a normal projection of the fourth metal layer on the substrate substrate at least partially overlaps with a normal projection of the third metal layer on the substrate substrate.

10. The display substrate of claim 9, further comprising: A fourth insulating layer is located between the third insulating layer and the fourth metal layer in a direction perpendicular to a plane where the substrate substrate is located, wherein the fourth insulating layer comprises a fourth opening, a projection of the fourth opening on the substrate substrate is located within a projection of the third opening on the substrate substrate, and the fourth metal layer is electrically connected to the third metal layer through the third opening and the fourth opening. 11.The display substrate of any one of claims 1-6, wherein, The first metal layer further comprises a second bottom portion surrounding the step portion, the step portion further comprises a third step portion at an angle with the first step portion, the third step portion connects the second bottom portion and the first step portion, and a projection of the second insulating layer on the substrate substrate at least partially overlaps with a projection of the second bottom portion on the substrate substrate. 12.The display substrate of claim 11, wherein, A projection of the second insulating layer on the substrate substrate partially overlaps with a projection of the first bottom portion on the substrate substrate, and a projection of the second opening on the substrate substrate is located in a projection of the first opening on the substrate substrate. Alternatively, A projection of the second insulating layer on the substrate substrate does not overlap with projections of the first bottom portion and the step portion on the substrate substrate, and a projection of the second opening on the substrate substrate covers a projection of the first opening on the substrate substrate.

13. The display substrate according to any one of claims 1 to 6, wherein, The first opening has a size of 3 microns to 11 microns in a width direction. 14.The display substrate of claim 13, wherein, The first opening has a size of 5 microns to 8 microns in a width direction.

15. The display substrate according to any one of claims 1 to 6, wherein, The third metal layer has a single-layer structure, or the third metal layer has a multi-layer composite structure. In the single-layer structure of the third metal layer, a metal activity in a metal layer closest to the third metal layer in the second metal layer is not less than a metal activity in the third metal layer. In the multi-layer composite structure of the third metal layer, in a direction perpendicular to a plane where the substrate substrate is located, a metal activity in a metal layer farthest from the second metal layer in the third metal layer is not greater than a metal activity in a metal layer between the farthest metal layer and the second metal layer.

16. The display substrate according to any one of claims 1 to 6, wherein, The substrate substrate comprises a packaging region and an edge region located around the packaging region, the edge region comprises a binding region on a side of at least one edge of the substrate substrate, and the binding region is located in the first frame region. A plurality of inorganic film layers are located on one side of the substrate substrate and are arranged in a stack. A plurality of first grooves are located in the edge region and are arranged in sequence and in a spaced manner in a direction away from the packaging region, and partially surround the packaging region, wherein each of the first grooves penetrates at least one inorganic film layer of the plurality of inorganic film layers, and a projection of the plurality of first grooves on the substrate substrate does not overlap with the binding region. An organic layer covers the plurality of first grooves. 17.The display substrate of claim 16, wherein, The organic layer comprises a first flat layer and a second flat layer arranged in a stack in a direction away from the substrate substrate in sequence, the first flat layer covers the plurality of first grooves, and the second flat layer is located on a side of the first flat layer away from the substrate substrate. 18.The display substrate of claim 17, wherein, The first insulating layer comprises a gate insulating layer and an interlayer dielectric layer which are sequentially stacked in a direction away from the substrate base plate, and the at least one inorganic film layer comprises the gate insulating layer and the interlayer dielectric layer.

19. The display substrate of claim 18, wherein, The inorganic film layer between each two adjacent first grooves forms a barrier portion; the plurality of inorganic film layers further comprise a buffer layer between the substrate base plate and the gate insulating layer in a direction perpendicular to the plane in which the substrate base plate lies, and the at least one inorganic film layer further comprises at least part of the buffer layer. 20.The display substrate of claim 19, wherein, The plurality of inorganic film layers further comprise a barrier layer between the substrate base plate and the buffer layer in a direction perpendicular to the plane in which the substrate base plate lies, and the at least one inorganic film layer further comprises at least part of the barrier layer. 21.The display substrate of claim 17, wherein, The display region of the display substrate comprises a gate metal layer on the substrate base plate, a gate insulating layer on the side of the gate metal layer away from the substrate base plate, and a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer sequentially arranged on the side of the gate insulating layer away from the substrate base plate; In a direction perpendicular to the plane in which the substrate base plate lies, the first planar layer is between the first source-drain metal layer and the second source-drain metal layer, and the second planar layer is between the second source-drain metal layer and the third source-drain metal layer; The plurality of data line leads are arranged in the same layer as the gate metal layer, the first insulating layer is arranged in the same layer as the gate insulating layer, the first metal layer is arranged in the same layer as the first source-drain metal layer, the second metal layer is arranged in the same layer as the second source-drain metal layer, and the third metal layer is arranged in the same layer as the third source-drain metal layer.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

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