Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a display region and a first bezel region, wherein the first bezel region is provided with a plurality of first-type data output lines, a plurality of first-type multiplexer circuits, a plurality of second-type multiplexer circuits, and a plurality of second-type data output lines that are at least partially located in the first bezel region; in a first direction, the plurality of first-type multiplexer circuits are located between the plurality of second-type multiplexer circuits; the end of each first-type data output line that is close to the display region is electrically connected to the corresponding first-type multiplexer circuit; and at least a segment of each second-type data output line is located in the display region, one end of each second-type data output line is electrically connected to the corresponding second-type multiplexer circuit, and the other end of each second-type data output line is located in the first bezel region and is connected to a corresponding second-type driving pad.

Description

Display substrate, display device

[0001] This application claims priority to Chinese Patent Application No. 202410962204.7, filed on July 17, 2024, entitled "Display Substrate, Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0004] With the development of OLED display technology, consumers have higher and higher requirements for the display effect of display products. Ultra-narrow bezels have become a new trend in the development of display products. Therefore, the narrowing of bezels or even the design of bezel-less products are receiving more and more attention in the design of OLED display products. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] In a first aspect, embodiments of the present disclosure provide a display substrate, including a display area and a first border area located on one side of the display area;

[0007] Multiple sub-pixels are located in the display area;

[0008] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, and the multiple data lines are configured to provide data signals to the multiple sub-pixels;

[0009] Multiple data output lines are electrically connected to the multiple data lines;

[0010] Multiple multiplexing circuits are located in the first frame area. Each of the multiple multiplexing circuits is electrically connected to one of the multiple data output lines and at least two of the multiple data lines. Each of the multiple multiplexing circuits is configured to provide the signal provided by the one data output line to the at least two data lines in a time-division manner.

[0011] Multiple driving pads are located in the first frame area and on the side of the multiple multiplexer circuits away from the display area. The multiple driving pads include multiple first-type driving pads and multiple second-type driving pads, and the multiple second-type driving pads are located between the multiple first-type driving pads.

[0012] The plurality of data output lines include a plurality of first-type data output lines and a plurality of second-type data output lines. The plurality of multiplexer circuits include a plurality of first-type multiplexer circuits and a plurality of second-type multiplexer circuits. In a first direction, the plurality of first-type multiplexer circuits are located between the plurality of second-type multiplexer circuits. The plurality of first-type data output lines are located in the first border area and extend along a second direction, which intersects the first direction. One end of each first-type data output line near the display area is electrically connected to the corresponding first-type multiplexer circuit, and the other end away from the display area is connected to the corresponding first-type driver pad. At least a portion of each second-type data output line is located in the display area. One end of each second-type data output line is electrically connected to the corresponding second-type multiplexer circuit, and the other end is located in the first border area and connected to the corresponding second-type driver pad.

[0013] In an exemplary embodiment, the second type of data output line includes a first structural portion, a second structural portion, and a third structural portion that are electrically connected in sequence, with the second structural portion located between the first structural portion and the third structural portion;

[0014] The first structural portion extends along the second direction and extends from the first border area to the display area. The end of the first structural portion located in the display area away from the first border area is electrically connected to the second structural portion. The end of the first structural portion located in the first border area away from the display area is located between two adjacent first type data output lines in the first direction.

[0015] The second structural portion is located in the display area and extends along the first direction, and both ends of the second structural portion are electrically connected to the first structural portion and the third structural portion, respectively;

[0016] The third structural part extends along the second direction and from the first border area to the display area. The end of the third structural part located in the display area away from the first border area is connected to the second structural part, and the end of the third structural part located in the first border area away from the display area is electrically connected to the corresponding second type multiplexing circuit.

[0017] In an exemplary embodiment, the second structural portion and the data line are located on different conductive layers in a direction perpendicular to the plane of the display substrate.

[0018] In an exemplary embodiment, the first structural portion located in the display area, the third structural portion located in the display area, and the data line are located on the same conductive layer or on different conductive layers.

[0019] In an exemplary embodiment, the display substrate includes a substrate. In a direction perpendicular to the plane of the display substrate, a plurality of sub-pixels are disposed on one side of the substrate. At least one of the plurality of sub-pixels includes a thin-film transistor, a planarization layer, and a light-emitting element. The planarization layer is located on the side of the thin-film transistor away from the substrate to cover the thin-film transistor. The light-emitting element is located on the side of the planarization layer away from the substrate. The planarization layer includes a first planarization layer via. The thin-film transistor includes an active layer on the substrate, a gate on the active layer away from the substrate, a source and a drain on the gate away from the substrate, and a transition electrode on the source and drain away from the substrate. One of the source and the drain is electrically connected to the transition electrode through a via. The transition electrode is electrically connected to the light-emitting element through the first planarization layer via.

[0020] The second structural portion is disposed on the same layer as the source and the drain, and the data line is disposed on the same layer as the transition electrode; or, the second structural portion is disposed on the same layer as the transition electrode, and the data line is disposed on the same layer as the source and the drain.

[0021] In an exemplary embodiment, in a structure in which the second structural portion is disposed on the same layer as the source and the drain, and the data line is disposed on the same layer as the adapter electrode: the first structural portion located in the display area and the third structural portion located in the display area are disposed on the same layer as the source and the drain, and are connected to the second structural portion; or, the first structural portion located in the display area and the third structural portion located in the display area are disposed on the same layer as the adapter electrode, and are connected to the second structural portion through a via.

[0022] In an exemplary embodiment, in a structure where the second structural portion is disposed on the same layer as the transition electrode and the data line is disposed on the same layer as the source and the drain: the first structural portion located in the display area and the third structural portion located in the display area are disposed on the same layer as the transition electrode and connected to the second structural portion; or, the first structural portion located in the display area and the third structural portion located in the display area are disposed on the same layer as the source and the drain and connected to the second structural portion through a via.

[0023] In an exemplary embodiment, the first border region includes a bend area;

[0024] In the first structural part and the first type of data output line located in the first frame area, the same data output line includes a first part, a second part and a third part that are electrically connected in sequence. In the plane where the display substrate is located, in the second direction, the second part is located in the bending area, the first part is located on the side of the bending area closer to the display area, and the third part is located on the side of the bending area away from the display area.

[0025] In an exemplary embodiment, the first portion is disposed on the same layer as the source and the drain, the second portion is disposed on the same layer as the transition electrode, and the third portion is disposed on the same layer as the gate or on the same layer as the source and the drain; in the same data output line, the second portion is electrically connected to the first portion through a second via, and the second portion is electrically connected to the third portion through a third via.

[0026] In an exemplary embodiment, the direction from the display area to the first border area, the first border area includes a multiplexed circuit area, the bending area, and the bonding area arranged sequentially; the plurality of multiplexer circuits are located in the multiplexed circuit area, and the plurality of drive pads are located in the bonding area; the first part extends from the multiplexed circuit area to the bending area, and the third part extends from the bending area to the bonding area.

[0027] In an exemplary embodiment, the second structural portion is located on the side of the display area close to the first border area; the display substrate includes a base, and the second structural portion is disposed on one side of the base in a direction perpendicular to the plane of the display substrate.

[0028] In an exemplary embodiment, the plurality of sub-pixels form multiple rows, and the second structural portion is located in at least one sub-pixel row on the side of the display area near the first border area; or the second structural portion is located in at least one first interval area on the side of the display area near the first border area, wherein the first interval area is the area between two adjacent rows of sub-pixels.

[0029] In an exemplary embodiment, on the same side of the first center line in the first direction, the second type of multiplexing circuit is located on the side of the first type of multiplexing circuit away from the first center line, and the first center line is the center line of the display area extending along the second direction.

[0030] In an exemplary embodiment, on the same side of the first centerline in the first direction, in the direction from the second type multiplexing circuit to the first type multiplexing circuit, the first structural part corresponding to the first second type multiplexing circuit to the last first structural part corresponding to the second type multiplexing circuit are arranged in sequence, and the third structural part corresponding to the first second type multiplexing circuit to the last third structural part corresponding to the second type multiplexing circuit are arranged in sequence.

[0031] In an exemplary embodiment, on the same side of the first centerline in the first direction, in the direction from the second type multiplexing circuit to the first type multiplexing circuit, the second structural parts corresponding to the first to last second type multiplexing circuits are arranged sequentially along the direction from the first border area to the display area, or sequentially along the direction from the display area to the first border area.

[0032] On the same side of the first centerline in the first direction, in the direction from the display area to the first border area, the third structural portion corresponding to the second structural portion away from the first border area at least partially overlaps with the orthographic projection of the second structural portion close to the first border area on the substrate, and the second structural portion and the third structural portion are located in different conductive layers.

[0033] In an exemplary embodiment, on the same side of the first centerline in the first direction, in the direction from the second type multiplexing circuit to the first type multiplexing circuit, the first structural part corresponding to the last second type multiplexing circuit is arranged sequentially to the first structural part corresponding to the first second type multiplexing circuit, and the third structural part corresponding to the first second type multiplexing circuit is arranged sequentially to the third structural part corresponding to the last second type multiplexing circuit.

[0034] In an exemplary embodiment, on the same side of the first centerline in the first direction, in the direction from the second type multiplexing circuit to the first type multiplexing circuit, the second structural parts corresponding to the last to the first second type multiplexing circuit are arranged sequentially along the direction from the first border area to the display area.

[0035] On the same side of the first centerline in the first direction, in the direction from the display area to the first border area, the third structural part corresponding to the second structural part away from the first border area does not overlap with the orthographic projection of the second structural part close to the first border area on the substrate, and the second structural part and the third structural part are located in different conductive layers or the same conductive layer.

[0036] In an exemplary embodiment, the display substrate further includes:

[0037] At least two data selection lines: located within the first border area;

[0038] The multiplexing circuit is electrically connected to the at least two data selection lines, and each multiplexing circuit is configured to provide the signal of one data output line to the at least two data lines in a time-division manner under the control of the at least two data selection lines.

[0039] In an exemplary embodiment, the display substrate includes a substrate, the plurality of data lines and the data selection lines are located on one side of the substrate, and the at least two data selection lines extend along the first direction and are spaced apart along the second direction;

[0040] The third structural portion is located on a different conductive layer from the data selection line, and the third structural portion overlaps with the orthographic projection of the at least two data selection lines onto the substrate.

[0041] In an exemplary embodiment, the number of data lines is M, the number of data output lines is k, and the number of data selection lines is z, where k = M / z, M and k are both positive integers, and z is an integer greater than or equal to 2.

[0042] Each of the multiplexing circuits is electrically connected to the adjacent z data lines and is configured to provide the signal of one data output line to the corresponding z data lines in a time-division manner under the control of the z data selection lines.

[0043] In an exemplary embodiment, the plurality of sub-pixels form N columns of sub-pixels, the M data lines include N pairs of data lines, at least one pair of data lines includes a first data line and a second data line, k = 2N / z, N is a positive integer, and M = 2N;

[0044] Among multiple sub-pixels located in the same column of sub-pixels, two adjacent sub-pixels are electrically connected to the first data line and the second data line of a pair of data lines, respectively.

[0045] In an exemplary embodiment, the value of z is 4, and each of the multiplexing circuits is electrically connected to four data lines in two adjacent pairs of data lines, configured to provide the signal of one data output line to the corresponding four data lines in a time-division manner under the control of the four data selection lines.

[0046] In an exemplary embodiment, the multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; in the same multiplexing circuit, the first multiplexing sub-circuit is electrically connected to one of a pair of data lines, and the second multiplexing sub-circuit is electrically connected to another adjacent pair of data lines.

[0047] In an exemplary embodiment, the four data selection lines include a first data selection line, a second data selection line, a third data selection line, and a fourth data selection line; the first multiplexing sub-circuit includes a first multiplexing transistor, a third multiplexing transistor, and a fifth multiplexing transistor; and the second multiplexing sub-circuit includes a second multiplexing transistor, a fourth multiplexing transistor, and a sixth multiplexing transistor.

[0048] The first terminal of the first multiplexed transistor and the first terminal of the second multiplexed transistor are electrically connected to one of the data output lines. The second terminal of the first multiplexed transistor is electrically connected to the first terminals of the third multiplexed transistor and the fifth multiplexed transistor. The second terminal of the second multiplexed transistor is electrically connected to the first terminals of the fourth multiplexed transistor and the sixth multiplexed transistor. The second terminals of the third multiplexed transistor, the fourth multiplexed transistor, the fifth multiplexed transistor, and the sixth multiplexed transistor are electrically connected to four adjacent data lines in the display area. The control terminal of the first multiplexed transistor is electrically connected to the first data selection line. The control terminal of the second multiplexed transistor is electrically connected to the second data selection line. The control terminals of the third and fourth multiplexed transistors are electrically connected to the third data selection line. The control terminals of the fifth and sixth multiplexed transistors are electrically connected to the fourth data selection line.

[0049] In an exemplary embodiment, the value of z is 2, and each of the multiplexing circuits is electrically connected to two of the data lines in one of the pairs of data lines, configured to provide the signal of one data output line to the corresponding two data lines in a time-division manner under the control of the two data selection lines.

[0050] In an exemplary embodiment, the plurality of sub-pixels form M columns of sub-pixels, and the plurality of sub-pixels located in the same column of sub-pixels are electrically connected to one of the data lines.

[0051] In an exemplary embodiment, the value of z is 2, and each of the multiplexing circuits is electrically connected to two adjacent data lines, configured to provide the signal of one data output line to the corresponding two data lines in a time-division manner under the control of the two data selection lines.

[0052] In an exemplary embodiment, the two data selection lines include a first data selection line and a second data selection line, and the multiplexing circuit includes a first multiplexing transistor and a second multiplexing transistor;

[0053] The first electrode of the first multiplexed transistor and the first electrode of the second multiplexed transistor are electrically connected to one of the data output lines, and the second electrodes of the first multiplexed transistor and the second multiplexed transistor are respectively electrically connected to two adjacent data lines located in the display area; the control electrode of the first multiplexed transistor is electrically connected to the first data selection line, and the control electrode of the second multiplexed transistor is electrically connected to the second data selection line.

[0054] In an exemplary embodiment, the value of z is 4, and each of the multiplexing circuits is electrically connected to four adjacent data lines, configured to provide the signal of one data output line to the corresponding four data lines in a time-division manner under the control of the four data selection lines.

[0055] Secondly, this disclosure also provides a display device, including the display substrate described in any of the above embodiments.

[0056] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0057] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0058] Figure 1 shows a schematic diagram of a display device;

[0059] Figure 2 shows a schematic diagram of a display substrate structure;

[0060] Figure 3 shows an enlarged structural diagram of the first border region;

[0061] Figure 4 is a schematic diagram of the structure of a display substrate;

[0062] Figure 5 is a schematic diagram of a planar structure of a display substrate;

[0063] Figure 6 shows a schematic diagram of a display substrate structure;

[0064] Figure 7a shows a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0065] Figure 7b is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0066] Figure 8a shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0067] Figure 8b is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0068] Figure 8c shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0069] Figure 8d is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0070] Figure 9a shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0071] Figure 9b is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0072] Figure 9c shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0073] Figure 9d is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0074] Figure 10a shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0075] Figure 10b shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0076] Figure 10c shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0077] Figure 10d shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0078] Figure 11a shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0079] Figure 11b shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0080] Figure 11c shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0081] Figure 12 is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0082] Figure 13a shows a schematic diagram of the planar structure of a multiplexing circuit provided in an exemplary embodiment of the present disclosure;

[0083] Figure 13b shows a schematic diagram of the planar structure of a multiplexing circuit provided in an exemplary embodiment of the present disclosure;

[0084] Figure 14a shows a cross-sectional view of the structure at position A1-A2 in Figure 13a;

[0085] Figure 14b shows a schematic cross-sectional view of the W1-W2 position in Figure 13a;

[0086] Figure 15 shows a cross-sectional structural diagram of the location of the second structural part of the display area provided in an exemplary embodiment of the present disclosure;

[0087] Figure 16 shows a cross-sectional view of the location of the second structural part of the display area provided in an exemplary embodiment of the present disclosure;

[0088] Figure 17 shows a cross-sectional view of the location of the second structural part of the display area provided in an exemplary embodiment of the present disclosure;

[0089] Figure 18 shows a cross-sectional view of the location of the second structural part of the display area provided in an exemplary embodiment of the present disclosure;

[0090] Figure 19a shows a schematic diagram of the planar structure of the active layer of a multiplexing circuit provided in an exemplary embodiment of the present disclosure.

[0091] Figure 19b shows a schematic diagram of the planar structure of a multiplexing circuit after forming the first conductive layer, according to an exemplary embodiment of the present disclosure.

[0092] Figure 19c shows a schematic diagram of the planar structure of a multiplexing circuit provided in an exemplary embodiment of the present disclosure;

[0093] Figure 19d shows a planar structural schematic diagram of a multiplexing circuit provided in an exemplary embodiment of the present disclosure;

[0094] Figure 20 is a cross-sectional structural diagram of a display area provided in an exemplary embodiment of the present disclosure;

[0095] Figure 21 shows a schematic diagram of the structure of the display device provided in an embodiment of this disclosure. Detailed Implementation

[0096] The embodiments described in this disclosure can be implemented in many different forms. Those skilled in the art will readily understand that the implementation methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0097] In the accompanying drawings, the size of constituent elements, the thickness of layers, or areas may sometimes be exaggerated for clarity. Therefore, any implementation of this disclosure is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and any implementation of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0098] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, rather than to limit the quantity.

[0099] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships when describing the positional relationships of constituent elements with reference to the accompanying drawings. This is solely for the purpose of facilitating the description of embodiments and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the orientation of the described constituent elements. Therefore, the use of terms not limited to those described herein can be appropriately replaced as appropriate.

[0100] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0101] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (or drain terminal, drain connection region, or drain electrode) and the source electrode (or source terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0102] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" can sometimes be interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged. In this disclosure, the control electrode can be the gate electrode.

[0103] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "component having a certain electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0104] Figure 1 shows a schematic diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0105] Figure 2 shows a schematic diagram of a display panel structure. As shown in Figure 2, the display panel may include a display area AA and a border area BB surrounding the display area AA. In some examples, the border area BB may include: a first border (lower border) B1 and a second border (upper border) arranged opposite each other in the second direction Y, and a third border (left border) B3 and a fourth border (right border) B4 arranged opposite each other in the first direction X. The first border B1 is connected to the third border B3 and the fourth border B4, and the second border B2 is connected to the third border B3 and the fourth border B4. In some examples, the display area AA may include a first edge (lower edge) and a second edge (upper edge) arranged opposite each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged opposite each other in the first direction X. The display area AA may include a plurality of regularly arranged sub-pixels Pxij. The sub-pixels may include pixel driving circuits and light-emitting devices. The first border B1 may include a bonding circuit that connects signal lines to an external driving device. The third border B3 and the fourth border B4 may include gate driving circuits and a second power supply line VSS that transmits voltage signals to the plurality of sub-pixels.

[0106] Figure 3 shows a schematic diagram of the planar structure of the first bezel region B1. In a plane parallel to the display substrate, the first bezel region B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, and a bonding area 14 arranged sequentially along the direction away from the display area AA. The bonding area 14 may include a driver chip area 141 and a bonding electrode area 142 arranged sequentially along the direction away from the bending area 12 of the second fan-out area 13. The first fan-out area 11 may include a data fan-out line, a first power line, and a second power line VSS. The data fan-out line is located in the middle of the first fan-out area 11 and includes multiple data connection lines. The multiple data connection lines are configured to connect to the data lines of the display area AA in a fanout routing manner. The first power line is configured to connect to the high-voltage power line (VDD) of the display area AA. The second power line is a low-voltage power line (VSS) located in the third bezel region B3 and the fourth bezel region B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display area AA (as shown in FIG. 4). The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The driver chip area 141 may house an integrated circuit (IC) 20, configured to be connected to the multiple data connection lines. The bonding electrode area 142 includes multiple bonding pads, configured to be bonded to a flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 may be bonded to the driver chip area 141, and the flexible printed circuit (FPC) 30 may be bonded to the bonding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit) may generate driving signals required to drive sub-pixels and may provide the driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 142 may be provided with a pad including a plurality of pins, and the flexible circuit board 30 may be bonded to the pad.

[0107] In an exemplary embodiment, as shown in FIG4, the bending region 12 can reverse the surface of the bonding region 14, that is, the upward-facing surface of the bonding region 14 can be transformed to face downward by bending the bending region 12. In an exemplary embodiment, when the bending region 12 is bent, the bonding region 14 can overlap with the display region AA in the thickness direction of the display panel.

[0108] In exemplary embodiments, for large-size display substrates, multiple data driver ICs (also known as driver ICs or driver integrated circuits) and multiple FPCs can be provided. The multiple FPCs are respectively bound to and connected to the multiple data driver ICs. For example, four data driver ICs can be provided, each bound to one of the four FPCs. This disclosure is not limited to four ICs and four FPCs; for example, two data driver ICs and two FPCs can be provided. For small-size display substrates, one or two data driver ICs can be provided. In this disclosure, the number of data driver ICs and FPCs can be set according to the size and functional requirements of the display substrate, and this disclosure does not limit this number.

[0109] With the development of display technology, people have increasingly higher requirements for high refresh rates and narrow bezels. Existing display substrates, while meeting high refresh rates, struggle to further narrow bezels, presenting a significant challenge in bezel-narrowing design. To improve the refresh rate of the display substrate while simultaneously satisfying its threshold voltage (Vth) compensation capability, a dual-source structure can be employed. This dual-source structure, also known as dual-data-link (DDL) technology, increases the threshold voltage compensation time and improves display quality. Figure 5 shows a schematic diagram of a dual-source display panel. The panel comprises M*N display units arranged in an array, defined by M gate lines and N pairs of data lines, where M and N are integers greater than or equal to 2. Each pair of data lines includes a first data line DA and a second data line DB, respectively positioned on opposite sides of its respective display column. For the m-th display row (m = 1, 2, ..., M), all N display units in the m-th row are connected to the m-th gate line G(m). For the nth display column, n = 1, 2, ..., N, two data lines of the nth data line D(n) are connected to the display units of the odd-numbered display rows and the even-numbered display rows, respectively. That is, the display units of the odd-numbered display rows in the nth display column are connected to the first data line DA, and the display units of the even-numbered display rows are connected to the second data line DB; or the display units of the even-numbered display rows are connected to the first data line DA, and the display units of the odd-numbered display rows are connected to the second data line DB. During the operation of this display panel, within one row cycle of the scan signal output by the mth gate line G(m), all the second data lines DB write display data to all display units of the mth display row. Within one row cycle of the scan signal output by the (m+1)th gate line G(m+1), all the first data lines DA write display data to all display units of the (m+1)th display row.

[0110] In the display panel shown in Figure 5, the dual data line structure increases the number of data lines, resulting in a larger size of the first bezel B1 along the second direction Y. This presents a challenge in achieving high refresh rates and high display quality by making the bezel narrowing design difficult. The dual data line structure (DDL technology) increases the number of data lines, while the number of driver IC pins is limited. A data selector (MUX, or multiplexer) can be used to reduce the number of driver IC pins, which can reduce the number of driver ICs and lower costs in some cases. As shown in Figure 6, with MUX technology, the first bezel area B1 also needs additional space to accommodate the data selector (MUX) 40, increasing the size of the first bezel B1 along the second direction Y. To reduce the width of the bottom bezel, some display substrates use FIAA (Fanout in AA) or FIP (Fanout in Panel). Panel (FIP) technology involves adding signal traces to the display area AA. A portion of the data signals from the data lines are transmitted through these new traces, reducing the size of the first fan-out area 11 along the second direction Y, thereby reducing the width of the first bezel B1 (i.e., the size of the first bezel B1 along the second direction Y). However, in a dual-data-line structure, the number of data lines in the display area AA is relatively dense, making it difficult to add too many signal traces. Therefore, FIAA or FIP cannot be used to reduce the bezel in a dual-data-line structure. In a single-data-line structure, especially in high-PPI structures, the line density of the display area AA is also very high, making it difficult to add too many signal traces. This also presents the technical problem of not being able to use FIAA or FIP to reduce the bezel. Furthermore, in structures using FIAA or FIP, the increased line density of the display area AA reduces light transmittance.

[0111] As can be seen from the above, there is a technical problem in display substrates where narrowing the bezel is difficult.

[0112] This disclosure provides a display substrate that may include a display area and a first border area located on one side of the display area;

[0113] Multiple sub-pixels are located in the display area;

[0114] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, and the multiple data lines are configured to provide data signals to the multiple sub-pixels;

[0115] Multiple data output lines are electrically connected to the multiple data lines;

[0116] Multiple multiplexing circuits are located in the first frame area. Each of the multiple multiplexing circuits is electrically connected to one of the multiple data output lines and at least two of the multiple data lines. Each of the multiple multiplexing circuits is configured to provide the signal provided by the one data output line to the at least two data lines in a time-division manner.

[0117] Multiple driving pads are located in the first frame area and on the side of the multiple multiplexer circuits away from the display area. The multiple driving pads include multiple first-type driving pads and multiple second-type driving pads, and the multiple second-type driving pads are located between the multiple first-type driving pads.

[0118] The plurality of data output lines include a plurality of first-type data output lines and a plurality of second-type data output lines. The plurality of multiplexer circuits include a plurality of first-type multiplexer circuits and a plurality of second-type multiplexer circuits. In a first direction, the plurality of first-type multiplexer circuits are located between the plurality of second-type multiplexer circuits. The plurality of first-type data output lines are located in the first border area and extend along a second direction, which intersects the first direction. One end of each first-type data output line near the display area is electrically connected to the corresponding first-type multiplexer circuit, and the other end away from the display area is connected to the corresponding first-type driver pad. At least a portion of each second-type data output line is located in the display area. One end of each second-type data output line is electrically connected to the corresponding second-type multiplexer circuit, and the other end is located in the first border area and connected to the corresponding second-type driver pad.

[0119] The display substrate provided in this embodiment includes a display area and a first border area located on one side of the display area. The display area includes multiple sub-pixels and multiple data lines. The first border area includes multiple multiplexing circuits and multiple driving pads. The display substrate also includes multiple data output lines, wherein the multiple data output lines include multiple first-type data output lines and multiple second-type data output lines, and the multiple multiplexing circuits include multiple first-type multiplexing circuits and multiple second-type multiplexing circuits. In a first direction, the multiple first-type multiplexing circuits are located between the multiple second-type multiplexing circuits. The multiple first-type data output lines are located in the first border area and extend along a second direction. One end of each first-type data output line near the display area is electrically connected to the corresponding first-type multiplexing circuit, and the other end away from the display area is connected to the corresponding first-type driving pad. At least a portion of each second-type data output line is located in the display area, one end of each second-type data output line is electrically connected to the corresponding second-type multiplexing circuit, and the other end is located in the first border area and connected to the corresponding second-type driving pad. The display substrate provided in this embodiment can reduce the size of the first border area along the column direction, thus overcoming the technical problem of the difficulty in narrowing the border of the display substrate.

[0120] As shown in FIG7a, it is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure. The display substrate may include a display area AA and a first border area B1 located on one side of the display area AA.

[0121] Multiple sub-pixels Pxij are located in the display area AA;

[0122] Multiple data lines DL are located in the display area AA and are electrically connected to multiple sub-pixels Pxij. The multiple data lines DL are configured to provide data signals to the multiple sub-pixels Pxij.

[0123] Multiple data output lines DT are electrically connected to multiple data lines DL;

[0124] Multiple multiplexer circuits 40 are located in the first frame region B1. Each of the multiple multiplexer circuits 40 is electrically connected to one of the multiple data output lines DT and at least two of the multiple data lines DL. Each multiplexer circuit 40 is configured to provide the signal provided by one data output line DT to at least two data lines DL in a time-division manner.

[0125] Multiple drive pads are located in the first frame area B1 and on the side of the multiple multiplexer circuits 40 away from the display area AA. The multiple drive pads include multiple first type drive pads and multiple second type drive pads, with the multiple second type drive pads located between the multiple first type drive pads.

[0126] The system includes multiple data output lines DT, comprising multiple first-type data output lines DT and multiple second-type data output lines DT. Multiple multiplexing circuits 40 include multiple first-type multiplexing circuits 40 and multiple second-type multiplexing circuits 40. In the first direction X, the multiple first-type multiplexing circuits 40 are located between the multiple second-type multiplexing circuits 40. The multiple first-type data output lines DT are located in the first frame region B1 and extend along the second direction Y, where the first direction X and the second direction Y intersect. Each first-type data output line DT has one end near the display area AA electrically connected to the corresponding first-type multiplexing circuit 40, and the other end away from the display area AA connected to the corresponding first-type driver pad. At least a portion of each second-type data output line DT is located in the display area AA, with one end electrically connected to the corresponding second-type multiplexing circuit 40 and the other end located in the first frame region B1 and connected to the corresponding second-type driver pad.

[0127] In an exemplary embodiment, in the structure shown in FIG7a, the multiplexing circuit 40 electrically connected to the driving circuit 20 may include a first multiplexing circuit 401 to a tenth multiplexing circuit 410. In the first direction X, the second type multiplexing circuits 42 located on both sides may include: a first multiplexing circuit 401, a second multiplexing circuit 402, a ninth multiplexing circuit 409, and a tenth multiplexing circuit 410; the first type multiplexing circuit 41 located in the middle may include a third multiplexing circuit 403 to an eighth multiplexing circuit 408. The second type data output line DT may include a first data output line DT1, a second data output line DT2, a ninth data output line DT9, and a tenth data output line DT10. The first type data output line DT may include a third data output line DT3 to an eighth data output line DT8. The first data output lines DT1 to DT10 are electrically connected to the first multiplexing circuit 401 to the tenth multiplexing circuit 410, respectively. Figure 7a is shown for illustrative purposes, with the number of data output lines DT and multiplexer circuits 40 both indicated as ten. The actual number of data output lines DT may be more than ten. For example, in the first direction X, multiple first-type data output lines DT can be set between the fifth data output line DT5 and the sixth data output line DT6. Multiple first-type multiplexer circuits 41 can be set between the fifth multiplexer circuit 405 and the sixth multiplexer circuit 406. Multiple second-type multiplexer circuits 42 can be set on the side of the first multiplexer circuit 401 away from the second multiplexer circuit 402. Multiple second-type multiplexer circuits 42 can be set on the side of the tenth multiplexer circuit 410 away from the ninth multiplexer circuit 409.

[0128] In this embodiment, in the first direction X, the first type data output line DT is located in the middle area, and the second type data output line DT is located on both sides. The first type data output line DT extends along the second direction Y and is electrically connected to the corresponding first type multiplexing circuit 41. At least a portion of the second type data output line DT located on both sides is located in the display area AA. One end is inserted between adjacent first type data output lines DT and connected to the corresponding second type drive pad. The other end is electrically connected to the corresponding second type multiplexing circuit 42. In the first frame area B1, the first type data output line and the second type data output line extend along the second direction Y. The first frame area B1 saves the routing space of the middle part of the second type data output line located in the display area AA and the end connected to the second type multiplexing circuit, which can reduce the size of the first frame area B1 along the second direction Y.

[0129] In an exemplary embodiment, as shown in FIG7b, the display substrate may further include:

[0130] At least two data selection lines MUX: located in the first frame area B1; wherein, the multiplexing circuit 40 is electrically connected to the at least two data selection lines MUX, and each multiplexing circuit 40 is configured to provide the signal of one data output line DT to the corresponding at least two data lines in a time-division manner under the control of the at least two data selection lines.

[0131] In an exemplary embodiment, the number of data lines DL is M, the number of data output lines DT is k, and the number of data selection lines MUX is z, where k = M / z, M and k are both positive integers, and z is an integer greater than or equal to 2.

[0132] Each multiplexer circuit 40 is electrically connected to the adjacent z data lines DL, and is configured to provide the signal of one data output line DT to the corresponding z data lines DL in a time-division manner under the control of the z data selection lines MUX.

[0133] In an exemplary embodiment, as shown in Figures 7a to 9c, multiple sub-pixels Pxij can form N columns of sub-pixels and M data lines DL can include N pairs of data lines DL, at least one pair of data lines including a first data line DL1 and a second data line DL2, k = 2N / z, N is a positive integer, and M = 2N.

[0134] Among multiple sub-pixels Pxij located in the same column of sub-pixels, two adjacent sub-pixels Pxij are electrically connected to the first data line DL1 and the second data line DL2 of a pair of data lines, respectively.

[0135] In an exemplary embodiment, as shown in Figures 10a to 11b, multiple sub-pixels Pxij can form M columns of sub-pixels, and multiple sub-pixels Pxij located in the same column of sub-pixels are electrically connected to one of the data lines DL.

[0136] The technical solutions of the embodiments of this disclosure are described in detail below through specific examples:

[0137] As shown in Figures 8a to 8d, a planar structure schematic diagram of a display substrate provided in an exemplary embodiment of the present disclosure is provided. Within the plane of the display substrate, the display substrate may include a display area AA and a border area BB located around the display area AA. In the second direction Y, the border area BB may include a first border area B1 and a second border area B2 located on both sides of the display area AA. The display area AA may include N columns of sub-pixels Pxij and N pairs of data lines DL respectively connected to the N columns of sub-pixels Pxij. The first border area B1 may include a multiplexed circuit 400 and k data output lines D arranged sequentially along the second direction Y. T, driving circuit 20, at least one pair of data lines DL including a first data line DL1 and a second data line DL2, N and k are positive integers; among multiple sub-pixels Pxij located in the same column of sub-pixels, two adjacent sub-pixels Pxij are electrically connected to the first data line DL1 and the second data line DL2 of the pair of data lines DL respectively; in the plane where the display substrate is located, multiple data lines DL in the N pairs of data lines DL extend along the second direction Y and are arranged at intervals along the first direction X, and the portion of k data output lines DT located in the first border area B1 extends along the second direction Y and is arranged at intervals along the first direction X, the first direction X intersects the second direction Y;

[0138] Among them, the data line DL located in the display area AA is electrically connected to the multiplexing circuit 400. The multiplexing circuit 400 may include k multiplexing circuits (which may be called multiplexers) 40. The k multiplexing circuits 40 are electrically connected to the driving circuit (which may be called the driving chip) 20 through k data output lines DT respectively. The driving circuit 20 can be bound to the first frame area B1 in a binding manner (for example, the driving circuit 20 can be bound to the binding area in the first frame area B1).

[0139] As shown in Figures 8a and 8b, the number of data output lines DT electrically connected to the driving circuit 20 can be ten (for simplicity, the number of data output lines DT and multiplexer circuits 40 is 10; the actual number may be more than ten). The driving circuit 20 can be electrically connected to ten multiplexer circuits 40 respectively through the ten data output lines DT. The data lines DL in the display area AA are electrically connected to the multiplexing circuit 400 at the position where the display area AA is adjacent to the first frame area B1 (for example, at the position where the first frame area B1 is adjacent to the display area AA). In the first direction X, they are electrically connected to the driving circuit 20. Among the multiple multiplexer circuits 40 connected to the drive circuit 20, the six first-type multiplexer circuits 41 located in the middle can be electrically connected to the drive circuit 20 via the first-type data output line DT, and the four second-type multiplexer circuits 42 located on both sides can be electrically connected to the drive circuit 20 via the second-type data output line DT. The shape of the first-type data output line DT can be a straight line or a strip extending along the second direction Y, and the shape of the second-type data output line DT can be an "L" shape or a "J" shape. For example, in the first direction X, the first multiplexer circuit 401 to the tenth multiplexer circuit 410 are arranged sequentially and connected to the drive circuit 20. Of the ten data output lines DT electrically connected to circuit 20, the third data output line DT3 to the eighth data output line DT8, which are respectively connected to the third to eighth multiplexer circuits 403 and 408 located in the middle, can be straight or strip-shaped first-type data output lines DT extending along the second direction Y. One end of each of the six first-type data output lines DT is electrically connected to the six drive pads located in the middle (electrically connected to drive circuit 20 through drive pads), and the other end is electrically connected to the corresponding first-type multiplexer circuit 40; and to the first multiplexer circuit 401, the second multiplexer circuit 408, and the third data output line DT8, which are connected to the drive circuit 20, can be straight or strip-shaped first-type data output lines DT. 02. The four data output lines DT connected to the ninth multiplexer circuit 409 and the tenth multiplexer circuit 410 can be of the second type of data output lines DT. The shape of the first data output line DT1 connected to the first multiplexer circuit 401 and the second data output line DT2 connected to the second multiplexer circuit 402 can be an "L" shape rotated 180° clockwise. The shape of the ninth data output line DT9 connected to the ninth multiplexer circuit 401 and the tenth data output line DT10 connected to the tenth multiplexer circuit 410 can be an "L" shape flipped along the first direction X.

[0140] In an exemplary embodiment, Figures 8a to 8d show a dual data line structure, wherein Figures 8a to 8b show a schematic diagram of a structure based on a dual source mux 1:4, and Figures 8c to 8d show a schematic diagram of a structure based on a dual source mux 1:2. In the exemplary embodiment, in the structures shown in Figures 8a and 8c, the multiple second-type data output lines DT located in the display area AA do not intersect; in the structures shown in Figures 8b and 8d, at least some of the multiple second-type data output lines DT located in the display area AA intersect.

[0141] In an exemplary embodiment, in the structure shown in FIG8a, at one end of the multiple data output lines DT in the first frame region B1 connected to the driving circuit 20, the first data output line DT1 electrically connected to the first multiplexer circuit 401 is located between the fourth data output line DT4 and the fifth data output line DT5, and the second data output line DT2 electrically connected to the second multiplexer circuit 402 is located between the fourth data output line DT4 and the third data output line DT3. That is, in the first frame region B1, in the first direction X, on the side of the center line extending along the second direction Y of the driving circuit 20, among the multiple first structural parts a1 (as shown in FIG9a and FIG9b, the first structural part a1 is a part of the second type data output line DT electrically connected to the corresponding second type multiplexer circuit), in the direction of the display area AA pointing to the frame region (third frame region B3 or fourth frame region B4) on that side, the first first structural part a1 to the last first structural part a1 are arranged sequentially. In the display area AA, multiple second type The data output lines DT of type 2 do not overlap in their orthographic projections on the substrate; this structure can be called reverse order. In the structure shown in Figure 8b, at the end of the first frame region B1 where multiple data output lines DT are connected to the driving circuit 20, the first data output line DT1, which is electrically connected to the first multiplexer circuit 401, is located between the fourth data output line DT4 and the third data output line DT3. The second data output line DT2, which is electrically connected to the second multiplexer circuit 402, is located between the fourth data output line DT4 and the fifth data output line DT5. That is, in the first frame region B1, among the multiple first structural parts a1 located on the side of the centerline extending from the driving circuit 20 along the second direction Y in the first direction X, the first first structural part a1 to the last first structural part a1 are arranged sequentially in the direction from the frame region (third frame region B3 or fourth frame region B4) on that side to the display region AA. In the display region AA, the orthographic projections of multiple second-type data output lines DT overlap on the substrate; this structure can be called forward order.

[0142] In an exemplary embodiment, as shown in Figures 9a and 9b (enlarged structural diagrams of Figure 8a), the value of z can be 4. Each multiplexer circuit 40 can be electrically connected to four data lines DL in two adjacent pairs of data lines, configured to provide the signal of the corresponding data output line DT to the corresponding four data lines DL in a time-division manner under the control of the four data selection lines. In an exemplary embodiment, in Figure 9a, among the segments of the second type of data output line DT connected to the drive pad, the segment located in the display area AA and the segment located in the first frame area B1 near the display area AA are located on the same conductive layer; in Figure 9b, among the segments of the second type of data output line DT connected to the drive pad, the segment located in the display area AA and the segment located in the first frame area B1 are located on different conductive layers and can be electrically connected through the fourth via V4.

[0143] In an exemplary embodiment, as shown in Figures 9a, 9b, 9d, 11b, and 11c, the multiplexing circuit 40 may include a first multiplexing sub-circuit 4001 and a second multiplexing sub-circuit 4002. In the same multiplexing circuit 40, the first multiplexing sub-circuit 4001 is electrically connected to one of the pairs of data lines, and the second multiplexing sub-circuit 4002 is electrically connected to the adjacent other pair of data lines.

[0144] In an exemplary embodiment, as shown in FIG9c, which is an enlarged structural schematic diagram of FIG8c, the value of z can be 2. Each multiplexer circuit 40 can be electrically connected to two data lines DL in one of the pairs of data lines, and is configured to provide the signal of the corresponding data output line DT to the corresponding two data lines DL in a time-division manner under the control of the two data selection lines MUX.

[0145] In an exemplary embodiment, as shown in Figures 10a to 10d, multiple sub-pixels can form M columns of sub-pixels, the number of data lines DL is M, the number of data output lines DT is k, and the number of data selection lines is z. N, z, and k are all positive integers, k = N / z, and the value of z is greater than or equal to 2. Multiple sub-pixels located in the same column of sub-pixels are electrically connected to one of the data lines DL.

[0146] In an exemplary embodiment, Figures 10a to 10d show a single data line structure, wherein Figures 10a to 10b show a schematic diagram of a structure based on a Single source mux 1:2, and Figures 10c to 10d show a schematic diagram of a structure based on a Single source mux 1:4. In the exemplary embodiment, in the structures shown in Figures 10a and 10c, the multiple second-type data output lines DT located in the display area AA do not intersect; in the structures shown in Figures 10b and 10d, at least some of the multiple second-type data output lines DT located in the display area AA intersect.

[0147] In an exemplary embodiment, as shown in FIG11a, which is an enlarged structural schematic diagram of FIG10a, the value of z can be 2. Each multiplexer circuit 40 is electrically connected to two adjacent data lines DL, and is configured to provide the signal of the corresponding data output line DT to the corresponding two data lines DL in a time-division manner under the control of the two data selection lines.

[0148] In an exemplary embodiment, as shown in Figures 11a and 9c, when the value of z is 2, the two data selection lines may include a first data selection line MUX1 and a second data selection line MUX2, and the multiplexing circuit may include a first multiplexing transistor MT1 and a second multiplexing transistor MT2.

[0149] The first terminal C11 of the first multiplexed transistor MT1 and the first terminal C12 of the second multiplexed transistor MT2 are electrically connected to one of the data output lines DT. The second terminals C21 of the first multiplexed transistor MT1 and C22 of the second multiplexed transistor MT2 are electrically connected to two adjacent data lines DL located in the display area, respectively. The control terminal of the first multiplexed transistor MT1 is electrically connected to the first data selection line MUX1, and the control terminal of the second multiplexed transistor MT2 is electrically connected to the second data selection line MUX2.

[0150] In an exemplary embodiment, in the structure shown in FIG9c, the same multiplexer circuit 40 can be electrically connected to two of the pair of data lines DL; in the structure shown in FIG11a, the same multiplexer circuit 40 can be electrically connected to two adjacent data lines DL.

[0151] In an exemplary embodiment, as shown in FIG11b, it is an enlarged structural schematic diagram of the R1 position in FIG10c, and as shown in FIG11c, it is another enlarged structural schematic diagram of the R1 position in FIG10c. The value of z can be 4. Each multiplexer circuit 40 can be electrically connected to the four adjacent data lines DL, and is configured to provide the corresponding data output line DT to the corresponding four data lines DL in a time-division manner under the control of the four data selection lines.

[0152] In an exemplary embodiment, as shown in Figures 11b and 11c, the multiplexing circuit 40 may include a first multiplexing sub-circuit 4001 and a second multiplexing sub-circuit 4002. In the same multiplexing circuit 40, the first multiplexing sub-circuit is electrically connected to two adjacent data lines DL out of four adjacent data lines DL, and the second multiplexing sub-circuit is electrically connected to the other two adjacent data lines DL out of four adjacent data lines DL.

[0153] In an exemplary embodiment, as shown in Figures 9a, 9b, and 11b, the four data selection lines may include a first data selection line MUX1, a second data selection line MUX2, a third data selection line MUX3, and a fourth data selection line MUX4. At least a portion of the multiplexing circuit 40 may include a first multiplexed transistor MT1, a second multiplexed transistor MT2, a third multiplexed transistor MT3, a fourth multiplexed transistor MT4, a fifth multiplexed transistor MT5, and a sixth multiplexed transistor MT6. A first multiplexing sub-circuit 4001 may include the first multiplexed transistor MT1, the third multiplexed transistor MT3, and the fifth multiplexed transistor MT5, and a second multiplexing sub-circuit 4002 may include the second multiplexed transistor MT2, the fourth multiplexed transistor MT4, and the sixth multiplexed transistor MT6. In an exemplary embodiment, the first terminal of the first multiplexed transistor MT1 and the first terminal of the second multiplexed transistor MT2 are electrically connected to one of the data output lines DT. The second terminal of the first multiplexed transistor MT1 is electrically connected to the first terminals of the third multiplexed transistor MT3 and the fifth multiplexed transistor MT5. The second terminal of the second multiplexed transistor MT2 is electrically connected to the first terminals of the fourth multiplexed transistor MT4 and the sixth multiplexed transistor MT6. The second terminals of the third multiplexed transistor MT3, the fourth multiplexed transistor MT4, the fifth multiplexed transistor MT5, and the sixth multiplexed transistor MT6 are electrically connected to four adjacent data lines DL in the display area AA. The control terminal of the first multiplexed transistor MT1 is electrically connected to the first data selection line MUX1. The control terminal of the second multiplexed transistor MT2 is electrically connected to the second data selection line MUX2. The control terminals of the third multiplexed transistor MT3 and the fourth multiplexed transistor MT4 are electrically connected to the third data selection line MUX3. The control terminals of the fifth multiplexed transistor MT5 and the sixth multiplexed transistor MT6 are electrically connected to the fourth data selection line MUX4.

[0154] In an exemplary embodiment, as shown in Figures 9c and 11c, the four data selection lines may include a first data selection line MUX1, a second data selection line MUX2, a third data selection line MUX3, and a fourth data selection line MUX4. At least a portion of the multiplexing circuit 40 may include a first multiplexed transistor MT1, a second multiplexed transistor MT2, a third multiplexed transistor MT3, and a fourth multiplexed transistor MT4. The first multiplexing sub-circuit 4001 may include the first multiplexed transistor MT1 and the second multiplexed transistor MT2, and the second multiplexing sub-circuit 4002 may include the third multiplexed transistor MT3 and the fourth multiplexed transistor MT4. In an exemplary embodiment, the first terminals of the first multiplexed transistor MT1 to the first terminals of the fourth multiplexed transistor MT4 are interconnected and electrically connected to one of the data output lines DT. The second terminals of the first multiplexed transistor MT1 to the second terminals of the fourth multiplexed transistor MT2 are respectively electrically connected to the four adjacent data lines DL. The control terminal of the first multiplexed transistor MT1 is electrically connected to the first data select line MUX1, the control terminal of the second multiplexed transistor MT2 is electrically connected to the second data select line MUX2, the control terminal of the third multiplexed transistor MT3 is electrically connected to the third data select line MUX3, and the control terminal of the fourth multiplexed transistor MT4 is electrically connected to the fourth data select line MUX4.

[0155] In an exemplary embodiment, as shown in Figures 9a to 9c, 11a and 11b, the second type of data output line DT may include a first structural part a1, a second structural part a2 and a third structural part a3 connected in sequence, with the second structural part a2 located between the first structural part a1 and the third structural part a3.

[0156] The first structural part a1 extends along the second direction Y and extends from the first border area B1 to the display area AA. The end of the first border area B1 that is away from the display area AA is located between two adjacent first type data output lines in the first direction X and is connected to the corresponding second type drive pad. The end of the display area AA that is away from the first border area B1 is electrically connected to the second structural part a2.

[0157] The second structural part a2 is located in the display area AA and extends along the first direction X. The two ends of the second structural part a2 are electrically connected to the first structural part a1 and the third structural part a3, respectively.

[0158] The third structural part a3 extends along the second direction Y and extends from the first border area B1 to the display area AA. The end of the display area AA located away from the first border area B1 is connected to the second structural part a2, and the end of the first border area B1 located away from the display area AA is electrically connected to the corresponding second type multiplexing circuit 42.

[0159] In an exemplary embodiment, in the first direction X, one end of the second type data output line DT connected to the driving circuit 20 can be located between two adjacent first type data output lines DT. As shown in FIG8a, the second type data output lines DT are inserted in reverse order between two adjacent first type data output lines DT in the first direction X. There is no overlap between the multiple second type data output lines DT. For example, in the first border area B1, in the first direction X, the first data output line DT1 can be located between the fourth data output line DT4 and the fifth data output line DT5; the second data output line DT2 can be located between the third data output line DT3 and the fourth data output line DT4; the ninth data output line DT9 can be located between the seventh data output line DT7 and the eighth data output line DT8; and the tenth data output line DT10 can be located between the sixth data output line DT6 and the seventh data output line DT7.

[0160] In an exemplary embodiment, as shown in Figures 11a and 12, a binding area 14 is provided on the side of the first border area B1 away from the display area AA. The first border area B1 can be called the data binding end DP (Data Pad, abbreviated as DP), and the second border area B2 can be called the data binding peer DPO (Data Pad Opposite, abbreviated as DPO).

[0161] In an exemplary embodiment, the display area AA may further include multiple scan signal lines GL extending along a first direction X and spaced apart along a second direction Y, with N columns of sub-pixels Pxij forming multiple rows, and the scan signal lines GL connected to at least some of the sub-pixels in one row of sub-pixels Pxij, configured to provide scan signals to the sub-pixels Pxij connected thereto.

[0162] In an exemplary embodiment, in the structures shown in Figures 9a, 9b, and 11b, the multiplexing circuit 40 may further include a first connection electrode c31, a second connection electrode c32, and a third connection electrode c33. The first electrode c11 of the first multiplexed transistor MT1 and the first electrode c12 of the second multiplexed transistor MT2, located in the same multiplexing circuit 40, are electrically connected to the first connection electrode c31, and the first connection electrode c31 is electrically connected to the corresponding data output line DT. The first electrode c13 of the third multiplexed transistor MT3 and the first electrode c15 of the fifth multiplexed transistor MT5 are electrically connected to the second connection electrode c32, and the second connection electrode c32 is electrically connected to the second electrode c21 of the first multiplexed transistor MT1. The first electrode c14 of the fourth multiplexed transistor MT4 and the first electrode c16 of the sixth multiplexed transistor MT6 are electrically connected to the third connection electrode c33, and the third connection electrode c33 is electrically connected to the second electrode c22 of the second multiplexed transistor MT2.

[0163] In an exemplary embodiment, in the structures shown in Figures 9a, 9b and 11b, the multiple multiplexing circuits 40 in the multiplexing circuit 400 can be arranged sequentially along the first direction X; in the same multiplexing circuit 40, the second terminal c26 of the sixth multiplexing transistor MT6, the second terminal c24 of the fourth multiplexing transistor MT4, the second terminal c25 of the fifth multiplexing transistor MT5, and the second terminal c23 of the third multiplexing transistor MT3 can be arranged sequentially along the first direction X, and are respectively electrically connected to four data lines DL in two adjacent pairs of data lines located in the display area AA.

[0164] In an exemplary embodiment, in the structures shown in Figures 9a, 9b, and 11b, the second terminals of the third multiplexed transistor MT3 to the sixth multiplexed transistor MT6 located in the same multiplexing circuit 40 can be electrically connected to four adjacent data lines DL in the display area AA through four first vias V1, respectively. Specifically, the third multiplexed transistor MT3 and the fifth multiplexed transistor MT5 in the first multiplexing sub-circuit are electrically connected to two of the pair of data lines DL, respectively. The fourth multiplexed transistor MT4 and the sixth multiplexed transistor MT5 in the second multiplexing sub-circuit... T6 is electrically connected to two data lines DL in a pair of data lines DL. For example, four adjacent data lines DL electrically connected to the same multiplexer circuit 40 are two adjacent pairs of data lines. The third multiplexer transistor MT3 is electrically connected to the second data line DL2 in one pair of data lines DL, and the fifth multiplexer transistor MT5 is electrically connected to the first data line DL1 in that pair of data lines DL. The fourth multiplexer transistor MT4 is electrically connected to the second data line DL2 in another pair of data lines DL, and the sixth multiplexer transistor MT6 is electrically connected to the first data line DL1 in that pair of data lines DL. In an exemplary embodiment, in the first direction X, the sixth multiplexer transistor MT6, the fourth multiplexer transistor MT4, the fifth multiplexer transistor MT5, and the third multiplexer transistor MT3 located in the same multiplexer circuit 40 are sequentially electrically connected to four data lines DL in two adjacent pairs of data lines DL.

[0165] In an exemplary embodiment, when the second electrode c26 of the sixth multiplexed transistor MT6, the second electrode c24 of the fourth multiplexed transistor MT4, the second electrode c25 of the fifth multiplexed transistor MT5, and the second electrode c23 of the third multiplexed transistor MT3 are located on the same conductive layer as the data line DL, the second electrodes c26 of the sixth multiplexed transistor MT6, the second electrode c24 of the fourth multiplexed transistor MT4, the second electrode c25 of the fifth multiplexed transistor MT5, and the second electrode c23 of the third multiplexed transistor MT3 can be integrally formed with the corresponding data line DL, without needing to be electrically connected through the first via V1. In an exemplary embodiment, when the second terminal c26 of the sixth multiplexed transistor MT6, the second terminal c24 of the fourth multiplexed transistor MT4, the second terminal c25 of the fifth multiplexed transistor MT5, and the second terminal c23 of the third multiplexed transistor MT3 are not located on the same conductive layer as the data line DL, the second terminals c26 of the sixth multiplexed transistor MT6, the second terminal c24 of the fourth multiplexed transistor MT4, the second terminal c25 of the fifth multiplexed transistor MT5, and the second terminal c23 of the third multiplexed transistor MT3 can be electrically connected to the corresponding data line DL through the first via V1.

[0166] In an exemplary embodiment, in the structures shown in Figures 9a, 9b, and 11b, the first data selection line MUX1 can be electrically connected to the control electrode of a plurality of first multiplexed transistors MT1 in the multiplexing circuit 400, the second data selection line MUX2 can be electrically connected to the control electrode of a plurality of second multiplexed transistors MT2 in the multiplexing circuit 400, the third data selection line MUX3 can be electrically connected to the control electrode of a plurality of third multiplexed transistors MT3 and a plurality of fourth multiplexed transistors MT4 in the multiplexing circuit 400, and the fourth data selection line MUX4 can be electrically connected to the control electrode of a plurality of fifth multiplexed transistors MT5 and a plurality of sixth multiplexed transistors MT6 in the multiplexing circuit 400.

[0167] In an exemplary embodiment, as shown in Figures 8a to 11b, the multiplexing circuit 400 can be located near the first border area B1 and the display area AA. The data line DL is electrically connected to the corresponding multiplexing circuit 40 as soon as it exits the display area AA. This can reduce the space occupied by the data line DL in the first border area B1 and reduce the size of the first border area B1 along the second direction Y.

[0168] In an exemplary embodiment, the second structural portion a2 and the data line DL are located on different conductive layers in a direction perpendicular to the plane of the display substrate, so as to avoid short circuit between the second structural portion a2 and the data line DL.

[0169] In an exemplary embodiment, the first structural part a1 located in the display area, the third structural part a3 located in the display area, and the data line DL may be located in the same conductive layer or in different conductive layers.

[0170] In an exemplary embodiment, the display substrate may include a substrate. In a direction Z perpendicular to the plane of the display substrate, a plurality of sub-pixels are disposed on one side of the substrate. At least one of the plurality of sub-pixels includes a thin film transistor, a planarization layer, and a light-emitting element. The planarization layer is located on the side of the thin film transistor away from the substrate to cover the thin film transistor. The light-emitting element is located on the side of the planarization layer away from the substrate. The planarization layer includes a first planarization layer via. The thin film transistor includes an active layer on the substrate, a gate on the side of the active layer away from the substrate, a source and a drain on the side of the gate away from the substrate, and a transition electrode on the side of the source and drain away from the substrate. One of the source and drain is electrically connected to the transition electrode through a via. The transition electrode is electrically connected to the light-emitting element through the first planarization layer via.

[0171] The second structural part a2 can be arranged on the same layer as the source and drain, and the data line DL can be arranged on the same layer as the transition electrode. Alternatively, the second structural part a2 can be arranged on the same layer as the transition electrode, and the data line DL can be arranged on the same layer as the source and drain.

[0172] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the display substrate may include a substrate and an active layer disposed on the substrate, a first conductive layer (Gate1 layer, which may be referred to as the first gate conductive layer or the first gate metal layer), a second conductive layer (Gate2 layer, which may be referred to as the second gate conductive layer or the second gate metal layer), a third conductive layer (SD1 layer, which may be referred to as the first source drain conductive layer or the first source drain metal layer), and a fourth conductive layer (SD2 layer, which may be referred to as the second source drain conductive layer or the second source drain metal layer).

[0173] In an exemplary embodiment, a third gate conductive layer (Gate3 layer, which may be referred to as the third gate metal layer) may be disposed between the second conductive layer and the third conductive layer in a direction perpendicular to the plane of the display substrate. In an exemplary embodiment, the active layer of the thin-film transistor may be located in the active layer, the gate of the thin-film transistor may be located in the first gate metal layer or the third gate metal layer, the source and drain of the thin-film transistor may be located in the first source-drain metal layer, and the transition electrode of the thin-film transistor may be located in the second source-drain metal layer.

[0174] In an exemplary embodiment, in the structure shown in Figures 8a to 11b, the data selection line may be located in the first conductive layer, and the scan signal line GL may be located in the first conductive layer (Gate1 layer) or the second conductive layer (Gate2 layer).

[0175] In an exemplary embodiment, in the structures shown in Figures 8a to 11b, the second structural part a2 may be located in the third conductive layer, and the data line DL may be located in the fourth conductive layer; alternatively, the second structural part a2 may be located in the fourth conductive layer, and the data line DL may be located in the third conductive layer.

[0176] In an exemplary embodiment, in a structure where the second structural portion a2 is disposed on the same layer as the source and drain, and the data line DL is disposed on the same layer as the transfer electrode: the first structural portion a1 located in the display area AA and the third structural portion a3 located in the display area AA can be disposed on the same layer as the source and drain, and connected to the second structural portion a2; or, the first structural portion a1 located in the display area AA and the third structural portion a3 located in the display area AA can be disposed on the same layer as the transfer electrode, and connected to the second structural portion a2 through a via.

[0177] In an exemplary embodiment, in a structure where the second structural portion a2 is disposed on the same layer as the transfer electrode and the data line DL is disposed on the same layer as the source and drain electrodes: the first structural portion a1 located in the display area AA and the third structural portion a3 located in the display area AA can be disposed on the same layer as the transfer electrode and connected to the second structural portion a2; or, the first structural portion a1 located in the display area AA and the third structural portion a3 located in the display area AA can be disposed on the same layer as the source and drain electrodes and connected to the second structural portion a2 through a via.

[0178] In an exemplary embodiment, the second structural part a2 and the data line DL are located in different conductive layers. The second structural part a2, the third structural part a3 located in the display area AA, and the first structural part a1 located in the display area AA may be located in the same conductive layer and in a different conductive layer from the data line DL; or the third structural part a3 located in the display area AA and the first structural part a1 located in the display area AA may be located in the same conductive layer, and the second structural part a2 is located in another conductive layer. In an exemplary embodiment, the second structural portion a2 of the second type of data output line DT, the third structural portion a3 located in the display area AA, and the first structural portion a1 located in the display area AA can be located in the third conductive layer, and the data line DL can be located in the fourth conductive layer; or the data line DL, the third structural portion a3 located in the display area AA, and the first structural portion a1 located in the display area AA can be located in the fourth conductive layer, and the second structural portion a2 located in the third conductive layer. In the structure where the third structural portion a3 located in the display area AA and the first structural portion a1 located in the display area AA are located in the fourth conductive layer, as shown in FIG10, in the same first structural portion a1, the portion located in the display area and the portion located in the first border area B1 can be electrically connected through the fourth via V4; in the same third structural portion a3, the portion located in the display area and the portion located in the first border area B1 can be electrically connected through the fifth via V5.

[0179] In an exemplary embodiment, as shown in Figures 9a to 9c, 11a, and 11b, the first border region B1 may include a bending region. Among the first type of data output line DT and the second type of data output line DT located in the first border region B1, the same data output line DT may include a first portion b1, a second portion b2, and a third portion b3 electrically connected in sequence. Specifically, in the plane of the display substrate, in the second direction Y, the second portion b2 may be located in the bending region 12, the first portion b1 may be located on the side of the bending region 12 closer to the display region AA, and the third portion b3 may be located on the side of the bending region 12 away from the display region AA. That is, the first structural portion a1 in the second type of data output line may include the first portion b1, the second portion b2, and the third portion b3 electrically connected in sequence, and the first type of data output line may include the first portion b1, the second portion b2, and the third portion b3 electrically connected in sequence.

[0180] In an exemplary embodiment, the first part b1 can be disposed on the same layer as the source and drain, the second part b2 can be disposed on the same layer as the transition electrode, and the third part b3 can be disposed on the same layer as the gate or on the same layer as the source and drain; in the same data output line DT, the second part b2 can be electrically connected to the first part b1 through the second via V2, and the second part b2 can be electrically connected to the third part b3 through the third via V3.

[0181] In an exemplary embodiment, as shown in FIG11a, the first frame region B1, pointing from the display area AA to the first frame region B1, may include a multiplexed circuit area 15, a bending area 12, and a bonding area 14 arranged sequentially. Multiple multiplexer circuits 40 may be located in the multiplexed circuit area, and multiple drive pads 2001 may be located in the bonding area 14. A first portion b1 extends from the multiplexed circuit area 15 to the bending area 12, and a third portion b3 extends from the bending area 12 to the bonding area 14, and is connected to the corresponding drive pad 2001. Compared with the structure shown in FIG6, the first frame region B1 in FIG11a saves space in the first fan-out area 11 and the second fan-out area 13, reduces the size of the first frame region B1 along the second direction Y (i.e., reduces the width of the first frame region B1), and reduces the frame of the display substrate.

[0182] In an exemplary embodiment, the display substrate may include a substrate, and multiple data lines DL and data selection lines MUX may be located on one side of the substrate. At least two data selection lines MUX may extend along a first direction X and be spaced apart along a second direction Y. The third structural portion a3 may be located in a different conductive layer from the data selection lines MUX, and the orthographic projections of the third structural portion a3 and the at least two data selection lines MUX on the substrate overlap. In an exemplary embodiment, when z is 4, the first data selection lines MUX1 to the fourth data selection lines MUX4 may be located in the first conductive layer; when z is 2, the first data selection lines MUX1 to the second data selection lines MUX2 may be located in the first conductive layer.

[0183] In an exemplary embodiment, in a structure where z is 4, the first and second electrodes of the first multiplexed transistor MT1 to the sixth multiplexed transistor MT6, and the first connection electrode c31 to the third connection electrode c33, can be located in one of the conductive layers: the third conductive layer, the fourth conductive layer, and the third gate conductive layer. In an exemplary embodiment, as shown in FIG12, in the first direction X, the display substrate may include a third border region B3 and a fourth border region B4 located on both sides of the display area. The third border region B3 and the fourth border region B4 may include a first power line VDD and multiple gate driving circuits 50. The gate driving circuits 50 typically employ a Gate Driver on Array (GOA) circuit. In the first direction X, in a border region (third border region B3 or fourth border region B4) located on one side of the display area AA, the first power line VDD can be located between the gate driving circuit 50 and the display area AA. The first power line VDD can extend along the extension direction of the border region, and the multiple gate driving circuits 50 can be arranged sequentially along the extension direction of the border region. In an exemplary embodiment, the gate drive circuit 50 may be electrically connected to at least one scan signal line GL and configured to provide a scan signal to the scan signal line GL to which it is electrically connected.

[0184] In an exemplary embodiment, as shown in FIG12, at least a portion of the gate drive circuit 50 may be arranged to the first frame region B1 and the second frame region B2, and the first power line VDD may extend to the first frame region B1 and the second frame region B2. In the first frame region B1, in the plane where the display substrate is located, the first power line VDD may be located between the display region AA and the bonding region 14 in the second direction Y. In the direction perpendicular to the plane where the display substrate is located, the orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projection of the multiplexing circuit 400 on the substrate.

[0185] In an exemplary embodiment, as shown in FIG12, the first border region B1 may further include a second power line VSS. In the plane where the display substrate is located, the first power line VDD may be located between the display region AA and the bonding region 14 in the second direction Y. In the direction perpendicular to the plane where the display substrate is located, the orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projection of the multiplexing circuit 400 on the substrate. In the first border region B1, in the first direction X, the second power line VSS may be located between the two first power lines VDD.

[0186] In an exemplary embodiment, both the first power line VDD and the second power line VSS are electrically connected to the driving circuit 20. For example, the first power line VDD and the second power line VSS can be electrically connected to the driving circuit 20 through the bonding region 14. In an exemplary embodiment, the first power line VDD and the second power line VSS can be located in the fourth conductive layer.

[0187] In an exemplary embodiment, the first terminals of the first multiplexed transistor MT1 and the second multiplexed transistor MT2 can be electrically connected through an active layer. As shown in Figures 13a and 13b, Figure 13a is a planar structural schematic diagram of the second type multiplexing circuit 42, and Figure 13b is a planar structural schematic diagram of the first type multiplexing circuit 41. The active layers of the first multiplexed transistor MT1 to the sixth multiplexed transistor MT6 can be interconnected.

[0188] In an exemplary embodiment, as shown in Figures 14a and 14b, a cross-sectional view of the first border region B1 is provided. Figure 14a is a cross-sectional view along position A1-A1 in Figure 13a, and Figure 14b is a cross-sectional view along position W1-W2 in Figure 13a. In these figures, 101 is the substrate, 102 is the active layer, 103 is the first conductive layer, 104 is the third conductive layer, 105 is the fourth conductive layer, M1 is the first insulating layer, M2 is the second insulating layer, and M3 is the third insulating layer and the first planarization layer.

[0189] In an exemplary embodiment, as shown in Figures 7a to 12, the second structural portion a2 can be located on the side of the display area AA near the first border area B1, minimizing the obstruction of the data output line DT on the display area AA and improving the transmittance of the display substrate. In an exemplary embodiment, the display substrate may include a substrate, and the second structural portion a2 can be disposed on one side of the substrate in a direction perpendicular to the plane of the display substrate.

[0190] In an exemplary embodiment, as shown in Figures 7a to 12, multiple sub-pixels Pxij form multiple rows, and the second structural part a2 may be located in at least one sub-pixel row on the side of the display area AA near the first border area B1; or the second structural part a2 may be located in at least one first interval area on the side of the display area AA near the first border area B1, where the first interval area is the area between two adjacent rows of sub-pixels.

[0191] In an exemplary embodiment, as shown in Figures 7a to 12, in the first direction X, the second type multiplexing circuit 42 can be located on both sides of the first type multiplexing circuit 41. On the same side of the first center line OO in the first direction X, the second type multiplexing circuit 42 is located on the side of the first type multiplexing circuit 41 away from the first center line OO. The first center line OO is the center line of the display area AA extending along the second direction Y.

[0192] In an exemplary embodiment, as shown in Figures 8b, 8d, 10b, and 10d, on the same side of the first centerline OO in the first direction X, in the direction from the second type multiplexing circuit 42 to the first type multiplexing circuit 41, the first structural part a1 corresponding to the first second type multiplexing circuit 42 to the last second type multiplexing circuit 42 are arranged sequentially, and the third structural part a3 corresponding to the first second type multiplexing circuit 42 to the last second type multiplexing circuit 42 are arranged sequentially.

[0193] In an exemplary embodiment, as shown in Figures 8b, 8d, 10b and 10d, on the same side of the first centerline OO in the first direction X, in the direction from the second type multiplexing circuit 42 to the first type multiplexing circuit 41, the second structural parts a2 corresponding to the first to last second type multiplexing circuit 42 are arranged sequentially in the direction from the first border area B1 to the display area AA, or sequentially in the direction from the display area AA to the first border area B1.

[0194] On the same side of the first centerline OO in the first direction X, in the direction from the display area AA to the first border area B1, the third structure a3 corresponding to the second structure a2 away from the first border area B1 at least partially overlaps with the orthographic projection of the second structure a2 close to the first border area B1 on the substrate, and the second structure a2 and the third structure a3 are located in different conductive layers.

[0195] In an exemplary embodiment, as shown in Figures 7a, 7b, 8a, 8c, 10a, and 10c, on the same side of the first centerline OO in the first direction X, in the direction from the second type multiplexing circuit 42 to the first type multiplexing circuit 41, the first structural part a1 corresponding to the last second type multiplexing circuit 42 to the first structural part a1 corresponding to the first second type multiplexing circuit 42 are arranged sequentially, and the third structural part a3 corresponding to the first second type multiplexing circuit 42 to the third structural part a3 corresponding to the last second type multiplexing circuit 42 are arranged sequentially.

[0196] In an exemplary embodiment, as shown in Figures 7a, 7b, 8a, 8c, 10a and 10c, on the same side of the first center line OO in the first direction X, in the direction from the second type multiplexing circuit 42 to the first type multiplexing circuit 41, the second structural parts a2 corresponding to the last to the first second type multiplexing circuit 42 are arranged sequentially in the direction from the first border area B1 to the display area AA.

[0197] On the same side of the first centerline OO in the first direction X, in the direction from the display area AA to the first border area B1, the third structure a3 corresponding to the second structure a2 away from the first border area B1 does not overlap with the orthographic projection of the second structure a2 close to the first border area B1 on the substrate. The second structure a2 and the third structure a3 are located in different conductive layers or the same conductive layer.

[0198] In an exemplary embodiment, as shown in Figures 8a and 8b, two schematic diagrams of a dual source mux 1:4 structure are presented. Figure 8a shows the second type of data output line DT inserted in reverse order, and Figure 8b shows the second type of data output line DT inserted in forward order. In an exemplary embodiment, as shown in Figures 8c and 8d, two schematic diagrams of a dual source mux 1:2 structure are presented. Figure 8c shows the second type of data output line DT inserted in reverse order, and Figure 8d shows the second type of data output line DT inserted in forward order.

[0199] In an exemplary embodiment, as shown in Figures 10a and 10b, two schematic diagrams of a Single source MUX 1:2 structure are presented. Figure 10a shows the second type of data output line DT inserted in reverse order, and Figure 10b shows the second type of data output line DT inserted in forward order. In the single data line structure, multiple sub-pixels in a column of sub-pixels are electrically connected to one of the data lines DL. In an exemplary embodiment, as shown in Figures 10c and 10d, two schematic diagrams of a Single source MUX 1:4 structure are presented. Figure 10c shows the second type of data output line DT inserted in reverse order, and Figure 10d shows the second type of data output line DT inserted in forward order. In the single data line structure, multiple sub-pixels in a column of sub-pixels are electrically connected to one of the data lines DL.

[0200] In an exemplary embodiment, as shown in Figures 9a, 9b, 11a, and 11b, the data line DL extends out of the display area AA and is electrically connected to the corresponding multiplexer circuit 40. Compared to the structure shown in Figure 6, the size of the first fan-out area 11 along the second direction Y is reduced. The line of the first part b1 connects to the corresponding third part b3 via the second part b2. The first part b1 and the third part b3 are essentially straight lines extending along the second direction Y, which can further reduce the size of the first border area B1 along the second direction Y. In addition, compared to Figure 6, the third part b3 is essentially a straight line drawn down to the bonding area (the area bonded to the drive circuit 20), eliminating the need for a large second fan-out area 13 as shown in Figure 6, thus saving space in the second fan-out area 13. That is, compared to Figure 6, the structures shown in Figures 9a, 9b, 11a, and 11b have significantly reduced positions of the first fan-out area 11 and the second fan-out area 13 along the second direction Y, greatly reducing the size of the first border area B1 along the second direction Y and thus reducing the width of the first border area B1.

[0201] In an exemplary embodiment, as shown in FIG15, which is a cross-sectional view of the location of the second structural portion a2 in the display area AA, a second planarization layer M4 and a pixel definition layer PDL are further provided on the side of the fourth conductive layer 105 away from the substrate 101 in the direction Z perpendicular to the plane where the display substrate is located. The pixel definition layer PDL is located on the side of the second planarization layer M4 away from the fourth conductive layer 105. In the structure shown in FIG15, the data line DL is located in the fourth conductive layer 105, the second structural portion a2 is located in the third conductive layer 104, and the first structural portion a1 and the third structural portion a3 in the display area AA are located in the third conductive layer 104.

[0202] In an exemplary embodiment, as shown in FIG16, another cross-sectional view of the location of the second structural part a2 in the display area AA is provided. The difference between FIG16 and FIG15 is that in the structure shown in FIG16, the third structural part a3 and the first structural part a1 are located in the fourth conductive layer 105 in the display area AA. The third structural part a3 and the first structural part a1 can be electrically connected to the corresponding second structural part a2 located in the third conductive layer 104 through vias.

[0203] In an exemplary embodiment, as shown in FIG17, another cross-sectional view of the location of the second structural part a2 in the display area AA is provided. The difference between FIG17 and FIG15 is that in the structure shown in FIG17, the second structural part a2, the third structural part a3 and the first structural part a1 in the display area AA are located in the fourth conductive layer 105, and the data line DL is located in the third conductive layer 104.

[0204] In an exemplary embodiment, as shown in FIG18, another cross-sectional view of the location of the second structural part a2 in the display area AA is provided. The difference between FIG18 and FIG17 is that in the structure shown in FIG18, the third structural part a3 and the first structural part a1 are located in the third conductive layer 104 in the display area AA, and the third structural part a3 and the first structural part a1 are electrically connected to the corresponding second structural part a2 through vias.

[0205] In an exemplary embodiment, as shown in Figures 19a to 19d, Figures 19a to 19c are planar structural schematic diagrams of the second type multiplexing circuit 42 in Figures 9d and 11c, and Figure 19d is a planar structural schematic diagram of the first type multiplexing circuit 41 in Figures 9d and 11c. In the structures shown in Figures 19c to 19d, each of the first multiplexed transistors MT1 to the fourth multiplexed transistor MT4 is composed of two transistors connected in parallel, which can increase the output capability and improve the output stability. In Figure 19a, AT1 is the active layer of the first multiplexed transistor MT1, AT2 is the active layer of the second multiplexed transistor MT2, AT3 is the active layer of the third multiplexed transistor MT3, and AT4 is the active layer of the fourth multiplexed transistor MT4.

[0206] In an exemplary embodiment, as shown in FIG20, a partial cross-sectional schematic diagram of the display area of ​​a display panel according to at least one embodiment of the present disclosure is provided. FIG20 illustrates the structure of a sub-pixel of the display area as an example. In this example, it is illustrated that the multiple transistors in the pixel circuit are of the same type. For example, the multiple transistors in the pixel circuit may all be low-temperature polycrystalline silicon thin-film transistors or all be oxide thin-film transistors. In other examples, the multiple transistors in the pixel circuit may be low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors. In addition, this example shows that the display panel can integrate a mutual capacitance touch structure to form an FMLOC structure.

[0207] In some examples, as shown in Figure 20, the display area of ​​the display panel may include, in a direction perpendicular to the display panel, a substrate 101 (which may be referred to as a base), and a circuit structure layer 200, a light-emitting structure layer 300, an encapsulation structure layer 400, a touch structure layer 500, and a color filter layer 600 sequentially disposed on the substrate 101. The display structure layer may include at least the circuit structure layer 200 and the light-emitting structure layer 300. The circuit structure layer 200 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 300 may include at least light-emitting elements for multiple sub-pixels.

[0208] In some examples, Figure 20 illustrates a scenario where each sub-pixel includes a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 200 of the display area may include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 101. The multiple display area metal layers of the display structure layer in this example may include a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer. A first insulating layer M1 (which may be referred to as the first gate insulating layer) may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer M02 may be disposed between the first gate metal layer and the second gate metal layer; an interlayer insulating layer M2 (which may be referred to as the aforementioned second insulating layer) may be disposed between the second gate metal layer and the first source / drain metal layer; a passivation layer M31 (which may be referred to as the third insulating layer) and a first planarization layer M32 may be disposed between the first source / drain metal layer and the second source / drain metal layer; a second planarization layer M4 may be disposed between the second source / drain metal layer and the third source / drain metal layer; and a third planarization layer M5 may be disposed on the side of the third source / drain metal layer away from the substrate 101. The first insulating layer M1 (which may be referred to as the first gate insulating layer), the second gate insulating layer M02, the interlayer insulating layer M2, and the passivation layer M31 may be inorganic insulating layers, while the first planarization layer M32, the second planarization layer M4, and the third planarization layer M5 may be organic insulating layers. However, this embodiment is not limited in this respect. In other examples, a buffer layer may be disposed on the side of the semiconductor layer near the substrate. This buffer layer prevents harmful substances from the substrate from penetrating the interior of the display panel and increases the adhesion of the film layers in the display panel to the substrate. In still other examples, a bottom shielding metal layer (BSM) may be disposed on the side of the buffer layer near the substrate. This bottom shielding metal layer may be configured to at least partially cover the active layer of the thin-film transistors of the pixel circuitry to prevent external light from affecting the performance of the thin-film transistors. In still other examples, a passivation layer may be omitted between the first and second source / drain metal layers, and only a first planarization layer may be disposed between the first and second source / drain metal layers.

[0209] In some examples, as shown in FIG20, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 101 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 101. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 101 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer M2 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer M2, the second gate insulating layer M02, and the first gate insulating layer M1 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. Similarly, the interlayer insulating layer M2, the second gate insulating layer M02, and the first gate insulating layer M1 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer M31 and the first planarization layer M32. The third source-drain metal layer may include at least a second transition electrode 232 (the transition electrode mentioned above may include the first transition electrode 231 and the second transition electrode 232). The second transition electrode 232 can be electrically connected to the first transition electrode 231 located in the second source-drain metal layer through a fourth pixel via formed by the second planarization layer M4. The second transition electrode 232 can be electrically connected to the first electrode 301 (e.g., the anode) of the light-emitting element through a fifth pixel via formed by the third planarization layer M5. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 231 and the second transition electrode 232.

[0210] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer; the data lines of the display area may be located, for example, in the second or third source-drain metal layer; and the high-potential power lines of the display area (e.g., the first power line VDD) may be located, for example, in at least one of the second and third source-drain metal layers. This embodiment is not limited in this respect. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0211] In some examples, as shown in Figure 20, the light-emitting structure layer 300 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on the third planarization layer 107 and electrically connected to the second transition electrode 232 through a fifth pixel via formed in the third planarization layer M5. The pixel definition layer 304 is disposed on the first electrode 301 and the third planarization layer M5, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer may also be provided on the side of the pixel definition layer 304 away from the substrate 101, and the isolation pillar layer may include multiple isolation pillars (PS).

[0212] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0213] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0214] In some examples, as shown in Figure 19, the encapsulation structure layer 400 may include a first encapsulation layer 4001, a second encapsulation layer 4002, and a third encapsulation layer 4003 stacked together. The first encapsulation layer 4001 and the third encapsulation layer 4003 may be made of inorganic materials, while the second encapsulation layer 4002 may be made of organic materials. The second encapsulation layer 4002 may be disposed between the first encapsulation layer 4001 and the third encapsulation layer 4003 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0215] This disclosure also provides a display device, as shown in FIG21, which may include a display substrate.

[0216] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0217] In one exemplary embodiment, the display device can be a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED), or a Light Emitting Diode (LED) display device. The display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0218] The display substrate and display device provided in this disclosure include a display area and a first border area located on one side of the display area. The display area includes multiple sub-pixels and multiple data lines. The first border area includes multiple multiplexing circuits and multiple driving pads. The display substrate also includes multiple data output lines, wherein the multiple data output lines include multiple first-type data output lines and multiple second-type data output lines, and the multiple multiplexing circuits include multiple first-type multiplexing circuits and multiple second-type multiplexing circuits. In a first direction, the multiple first-type multiplexing circuits are located between the multiple second-type multiplexing circuits. The multiple first-type data output lines are located in the first border area and extend along a second direction. One end of each first-type data output line near the display area is electrically connected to the corresponding first-type multiplexing circuit, and the other end away from the display area is connected to the corresponding first-type driving pad. At least a portion of each second-type data output line is located in the display area, one end of each second-type data output line is electrically connected to the corresponding second-type multiplexing circuit, and the other end is located in the first border area and connected to the corresponding second-type driving pad. The display substrate provided in this embodiment can reduce the size of the first border area along the column direction, thus overcoming the technical problem of the difficulty in narrowing the border of the display substrate.

[0219] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0220] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0221] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit them. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a display area and a first border area located on one side of the display area; Multiple sub-pixels are located in the display area; Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, and the multiple data lines are configured to provide data signals to the multiple sub-pixels; Multiple data output lines are electrically connected to the multiple data lines; Multiple multiplexing circuits are located in the first frame area. Each of the multiple multiplexing circuits is electrically connected to one of the multiple data output lines and at least two of the multiple data lines. Each of the multiple multiplexing circuits is configured to provide the signal provided by the one data output line to the at least two data lines in a time-division manner. Multiple driving pads are located in the first frame area and on the side of the multiple multiplexer circuits away from the display area. The multiple driving pads include multiple first-type driving pads and multiple second-type driving pads, and the multiple second-type driving pads are located between the multiple first-type driving pads. The plurality of data output lines include a plurality of first-type data output lines and a plurality of second-type data output lines. The plurality of multiplexer circuits include a plurality of first-type multiplexer circuits and a plurality of second-type multiplexer circuits. In a first direction, the plurality of first-type multiplexer circuits are located between the plurality of second-type multiplexer circuits. The plurality of first-type data output lines are located in the first border area and extend along a second direction, which intersects the first direction. One end of each first-type data output line near the display area is electrically connected to the corresponding first-type multiplexer circuit, and the other end away from the display area is connected to the corresponding first-type driver pad. At least a portion of each second-type data output line is located in the display area. One end of each second-type data output line is electrically connected to the corresponding second-type multiplexer circuit, and the other end is located in the first border area and connected to the corresponding second-type driver pad. 2.The display substrate of claim 1, wherein, The second type of data output line includes a first structural part, a second structural part, and a third structural part that are electrically connected in sequence, with the second structural part located between the first structural part and the third structural part; The first structural portion extends along the second direction and extends from the first border area to the display area. The end of the first structural portion located in the display area away from the first border area is electrically connected to the second structural portion. The end of the first structural portion located in the first border area away from the display area is located between two adjacent first type data output lines in the first direction. The second structural portion is located in the display area and extends along the first direction, and both ends of the second structural portion are electrically connected to the first structural portion and the third structural portion, respectively; The third structural part extends along the second direction and from the first border area to the display area. The end of the third structural part located in the display area away from the first border area is connected to the second structural part, and the end of the third structural part located in the first border area away from the display area is electrically connected to the corresponding second type multiplexing circuit. 3.The display substrate of claim 2, wherein, In a direction perpendicular to the plane of the display substrate, the second structural part and the data line are located in different conductive layers. 4.The display substrate of claim 3, wherein, The first structural portion located in the display area, the third structural portion located in the display area, and the data line are located on the same conductive layer or on different conductive layers. 5.The display substrate of claim 4, wherein, The display substrate includes a substrate. In a direction perpendicular to the plane of the display substrate, a plurality of sub-pixels are disposed on one side of the substrate. At least one of the plurality of sub-pixels includes a thin-film transistor, a planarization layer, and a light-emitting element. The planarization layer is located on the side of the thin-film transistor away from the substrate to cover the thin-film transistor. The light-emitting element is located on the side of the planarization layer away from the substrate. The planarization layer includes a first planarization layer via. The thin-film transistor includes an active layer on the substrate, a gate on the side of the active layer away from the substrate, a source and a drain on the side of the gate away from the substrate, and a transition electrode on the side of the source and the drain away from the substrate. One of the source and the drain is electrically connected to the transition electrode through a via. The transition electrode is electrically connected to the light-emitting element through the first planarization layer via. The second structural portion is disposed on the same layer as the source and the drain, and the data line is disposed on the same layer as the transition electrode; or, the second structural portion is disposed on the same layer as the transition electrode, and the data line is disposed on the same layer as the source and the drain. 6.The display substrate of claim 5, wherein, In a structure in which the second structural portion is disposed on the same layer as the source and the drain, and the data line is disposed on the same layer as the adapter electrode: the first structural portion located in the display area and the third structural portion located in the display area are disposed on the same layer as the source and the drain, and are connected to the second structural portion; or, the first structural portion located in the display area and the third structural portion located in the display area are disposed on the same layer as the adapter electrode, and are connected to the second structural portion through a via. 7.The display substrate of claim 5, wherein, In a structure in which the second structural portion is disposed on the same layer as the transition electrode and the data line is disposed on the same layer as the source and the drain: the first structural portion located in the display area and the third structural portion located in the display area are disposed on the same layer as the transition electrode and are connected to the second structural portion; or, the first structural portion located in the display area and the third structural portion located in the display area are disposed on the same layer as the source and the drain and are connected to the second structural portion through a via. 8.The display substrate of claim 5, wherein, The first border area includes a bend area; In the first structural part and the first type of data output line located in the first frame area, the same data output line includes a first part, a second part and a third part that are electrically connected in sequence. In the plane where the display substrate is located, in the second direction, the second part is located in the bending area, the first part is located on the side of the bending area closer to the display area, and the third part is located on the side of the bending area away from the display area. 9.The display substrate of claim 8, wherein, The first part is disposed on the same layer as the source and the drain, the second part is disposed on the same layer as the transition electrode, and the third part is disposed on the same layer as the gate or on the same layer as the source and the drain; In the same data output line, the second part is electrically connected to the first part through a second via, and the second part is electrically connected to the third part through a third via. 10.The display substrate of claim 8, wherein, The first border area includes a multiplexed circuit area, a bending area, and a bonding area arranged sequentially from the display area to the first border area; the plurality of multiplexer circuits are located in the multiplexed circuit area, and the plurality of drive pads are located in the bonding area; the first part extends from the multiplexed circuit area to the bending area, and the third part extends from the bending area to the bonding area. 11.The display substrate of claim 2, wherein, The second structural portion is located on the side of the display area close to the first frame area; the display substrate includes a base, and the second structural portion is disposed on one side of the base in a direction perpendicular to the plane of the display substrate. 12.The display substrate of claim 11, wherein, The plurality of sub-pixels form multiple rows, and the second structural part is located in at least one sub-pixel row on the side of the display area near the first border area; or the second structural part is located in at least one first interval area on the side of the display area near the first border area, the first interval area being the area between two adjacent rows of sub-pixels. 13.The display substrate of claim 12, wherein, On the same side of the first center line in the first direction, the second type of multiplexing circuit is located on the side of the first type of multiplexing circuit away from the first center line, where the first center line is the center line of the display area extending along the second direction. 14.The display substrate of claim 13, wherein, On the same side of the first centerline in the first direction, in the direction from the second type multiplexing circuit to the first type multiplexing circuit, the first structural part corresponding to the first second type multiplexing circuit to the last first structural part corresponding to the second type multiplexing circuit are arranged in sequence, and the third structural part corresponding to the first second type multiplexing circuit to the last third structural part corresponding to the second type multiplexing circuit are arranged in sequence. 15.The display substrate of claim 14, wherein, On the same side of the first centerline in the first direction, in the direction from the second type multiplexing circuit to the first type multiplexing circuit, the second structural parts corresponding to the first to last second type multiplexing circuits are arranged sequentially along the direction from the first border area to the display area, or sequentially along the direction from the display area to the first border area. On the same side of the first centerline in the first direction, in the direction from the display area to the first border area, the third structural portion corresponding to the second structural portion away from the first border area at least partially overlaps with the orthographic projection of the second structural portion close to the first border area on the substrate, and the second structural portion and the third structural portion are located in different conductive layers. 16.The display substrate of claim 13, wherein, On the same side of the first centerline in the first direction, in the direction from the second type multiplexing circuit to the first type multiplexing circuit, the first structural part corresponding to the last second type multiplexing circuit is arranged sequentially to the first structural part corresponding to the first second type multiplexing circuit, and the third structural part corresponding to the first second type multiplexing circuit is arranged sequentially to the third structural part corresponding to the last second type multiplexing circuit. 17.The display substrate of claim 16, wherein, On the same side of the first centerline in the first direction, in the direction from the second type multiplexing circuit to the first type multiplexing circuit, the second structural parts corresponding to the last to the first second type multiplexing circuit are arranged sequentially along the direction from the first border area to the display area. On the same side of the first centerline in the first direction, in the direction from the display area to the first border area, the third structural part corresponding to the second structural part away from the first border area does not overlap with the orthographic projection of the second structural part close to the first border area on the substrate, and the second structural part and the third structural part are located in different conductive layers or the same conductive layer.

18. The display substrate according to any one of claims 2 to 17, further comprising: At least two data selection lines: located within the first border area; The multiplexing circuit is electrically connected to the at least two data selection lines, and each multiplexing circuit is configured to provide the signal of one data output line to the at least two data lines in a time-division manner under the control of the at least two data selection lines.

19. The display substrate of claim 18, wherein, The display substrate includes a base, the plurality of data lines and the data selection lines are located on one side of the base, and the at least two data selection lines extend along the first direction and are arranged at intervals along the second direction; The third structural portion is located on a different conductive layer from the data selection line, and the third structural portion overlaps with the orthographic projection of the at least two data selection lines onto the substrate.

20. The display substrate of claim 18, wherein, The number of data lines is M, the number of data output lines is k, and the number of data selection lines is z, where k = M / z, M and k are both positive integers, and z is an integer greater than or equal to 2. Each of the multiplexing circuits is electrically connected to the adjacent z data lines and is configured to provide the signal of one data output line to the corresponding z data lines in a time-division manner under the control of the z data selection lines. 21.The display substrate of claim 20, wherein, The plurality of sub-pixels form N columns of sub-pixels, the M data lines include N pairs of data lines, at least one pair of data lines includes a first data line and a second data line, k = 2N / z, N is a positive integer, and M = 2N; Among multiple sub-pixels located in the same column of sub-pixels, two adjacent sub-pixels are electrically connected to the first data line and the second data line of a pair of data lines, respectively.

22. The display substrate of claim 21, wherein, The value of z is 4. Each of the multiplexing circuits is electrically connected to four of the two adjacent pairs of data lines. It is configured to provide the signal of one data output line to the corresponding four data lines in a time-division manner under the control of the four data selection lines.

23. The display substrate of claim 22, wherein, The multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; in the same multiplexing circuit, the first multiplexing sub-circuit is electrically connected to one of the pairs of data lines, and the second multiplexing sub-circuit is electrically connected to the other adjacent pair of data lines.

24. The display substrate of claim 23, wherein, The four data selection lines include a first data selection line, a second data selection line, a third data selection line, and a fourth data selection line. The first multiplexing sub-circuit includes a first multiplexing transistor, a third multiplexing transistor, and a fifth multiplexing transistor. The second multiplexing sub-circuit includes a second multiplexing transistor, a fourth multiplexing transistor, and a sixth multiplexing transistor. The first terminal of the first multiplexed transistor and the first terminal of the second multiplexed transistor are electrically connected to one of the data output lines. The second terminal of the first multiplexed transistor is electrically connected to the first terminals of the third multiplexed transistor and the fifth multiplexed transistor. The second terminal of the second multiplexed transistor is electrically connected to the first terminals of the fourth multiplexed transistor and the sixth multiplexed transistor. The second terminals of the third multiplexed transistor, the fourth multiplexed transistor, the fifth multiplexed transistor, and the sixth multiplexed transistor are electrically connected to four adjacent data lines in the display area. The control terminal of the first multiplexed transistor is electrically connected to the first data selection line. The control terminal of the second multiplexed transistor is electrically connected to the second data selection line. The control terminals of the third and fourth multiplexed transistors are electrically connected to the third data selection line. The control terminals of the fifth and sixth multiplexed transistors are electrically connected to the fourth data selection line. 25.The display substrate of claim 21, wherein, The value of z is 2. Each of the multiplexing circuits is electrically connected to two of the data lines in one of the pairs of data lines, and is configured to provide the signal of one data output line to the corresponding two data lines in a time-division manner under the control of the two data selection lines.

26. The display substrate of claim 20, wherein, The plurality of sub-pixels form M columns of sub-pixels, and the plurality of sub-pixels located in the same column of sub-pixels are electrically connected to one of the data lines. 27.The display substrate of claim 26, wherein, The value of z is 2. Each of the multiplexing circuits is electrically connected to two adjacent data lines and is configured to provide the signal of one data output line to the corresponding two data lines in a time-division manner under the control of the two data selection lines. 28.The display substrate according to claim 26 or 27, wherein The two data selection lines include a first data selection line and a second data selection line, and the multiplexing circuit includes a first multiplexing transistor and a second multiplexing transistor; The first pole of the first multiplexing transistor and the first pole of the second multiplexing transistor are electrically connected with one of the data output lines, the second pole of the first multiplexing transistor and the second pole of the second multiplexing transistor are respectively electrically connected with two adjacent data lines in the display area; the control pole of the first multiplexing transistor is electrically connected with the first data selection line, and the control pole of the second multiplexing transistor is electrically connected with the second data selection line.

29. A display device, comprising the display substrate according to any one of claims 1 to 28.

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