Wafer and preparation method therefor, wafer stack, light-emitting device, and terminal

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide a wafer and a preparation method therefor, a wafer stack, a light-emitting device, and a terminal, for use in optimizing performance of light-emitting devices. The light-emitting device comprises a transparent conductive layer, an adhesive layer, a metal reflective layer, a barrier layer, a seed layer, and a metal bonding layer that are stacked. The seed layer having the same crystal phase as the metal bonding layer is provided in the light-emitting device, and the seed layer can control the crystal growth process in the metal bonding layer, thereby ensuring the crystallization quality of the metal bonding layer and then improving the bonding effect of the metal bonding layer. In addition, the seed layer is located on the side of the barrier layer distant from the metal reflective layer, and when the metal reflective layer and the metal bonding layer deform at a high temperature, the seed layer having high rigidity can exert a reaction force on the barrier layer to prevent breakage of the barrier layer. That is, the seed layer can mitigate the problem of metal diffusion caused by holes generated after breakage of the barrier layer, and further enhance the barrier's effect against metal diffusion. In this way, the effect of optimizing performance of the light-emitting device is achieved.

Description

Wafer, preparation method thereof, wafer stack, light-emitting device, and terminal

[0001] The present application claims priority to the Chinese Patent Application No. 202410955876.5, filed on July 16, 2024, and entitled "Wafer, preparation method thereof, wafer stack, light-emitting device, and terminal", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, and in particular to a wafer, a preparation method thereof, a wafer stack, a light-emitting device, and a terminal. BACKGROUND

[0003] With the development of microfabrication technology, light-emitting diode (LED) devices have been gradually widely used in lighting and display fields. As the basic light-emitting unit of a terminal, the performance of the light-emitting diode device directly affects the performance of the terminal. The performance of the light-emitting diode device in the terminal is affected by many factors, including the preparation process, the film layer material, and the device structure. These factors ultimately affect the performance and service life of the terminal.

[0004] Therefore, optimizing the performance of the light-emitting diode device is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0005] The present application provides a wafer, a preparation method thereof, a wafer stack, a light-emitting device, and a terminal, for optimizing the performance of the light-emitting device.

[0006] In a first aspect, the present application provides a wafer, the wafer comprising a first semiconductor layer, an active layer, a second semiconductor layer, a seed layer, and a first metal bonding layer stacked. The active layer is located between the first semiconductor layer and the second semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. The seed layer is arranged on the side of the second semiconductor layer away from the active layer, and the first metal bonding layer is arranged on the surface of the seed layer away from the second semiconductor layer. The material of the seed layer comprises a conductive dielectric material, and the crystal phase of the material of the seed layer is the same as the crystal phase of the material of the first metal bonding layer.

[0007] In the embodiments of the present application, the seed layer having the same crystal phase as the first metal bonding layer is arranged in the wafer. When the first metal bonding layer is formed on the surface of the seed layer, the seed layer can control the crystal growth process of the first metal bonding layer due to the lattice matching between the seed layer and the first metal bonding layer, so that the first metal bonding layer has small lattice distortion and small grain surface roughness, thereby ensuring the crystallization quality of the first metal bonding layer and improving the bonding effect of the first metal bonding layer. In addition, the seed layer is located on the side of the barrier layer away from the metal reflection layer. When the metal reflection layer and the first metal bonding layer are deformed at high temperature, the seed layer with high rigidity can provide a counteracting force to the barrier layer to prevent the barrier layer from breaking. That is, the seed layer can improve the problem of the barrier layer breaking to form holes and causing metal diffusion, and further strengthen the effect of preventing metal diffusion.

[0008] In a possible implementation, the material of the first metal bonding layer includes a first metal element, the material of the seed layer includes a second metal element, the material of the first metal bonding layer does not include the second metal element, and the material of the seed layer does not include the first metal element. The seed layer provided in the embodiments of the present application is made of a conductive dielectric material. The conductive dielectric material can prevent metal diffusion, the first metal element in the first metal bonding layer cannot diffuse into the seed layer, the second metal element in the seed layer cannot diffuse into the first metal bonding layer, and the first metal bonding layer and the seed layer cannot form an alloy, thereby ensuring the bonding effect of the first metal bonding layer.

[0009] In a possible implementation, the wafer further includes a barrier layer; the barrier layer is arranged on the side of the seed layer away from the first metal bonding layer; and the material of the barrier layer includes a conductive dielectric material. The conductive dielectric material with certain rigidity, high structural density, small crystal structure defects and small pores can effectively prevent metal atoms from diffusing and has good barrier effect. In addition, the conductive dielectric material is not easy to form recrystallization with metal during wafer bonding, and has better barrier effect. Therefore, the problem that the metal reflection layer forms an alloy with other metals to form holes in the metal reflection layer and cause the reflectivity and stability of the metal reflection layer to decrease can be improved, so that the finally formed light emitting device has better stability and visible light utilization rate. In addition, compared with the metal barrier layer with high ductility, the rigid conductive dielectric barrier layer with good chemical stability can effectively prevent the metal reflection layer from deforming and prevent the metal reflection layer from causing diffuse reflection and thus reducing the reflectivity, thereby effectively improving the visible light utilization rate of the finally formed light emitting device.

[0010] In a possible implementation, the material of the barrier layer includes a third metal element, the material of the seed layer includes a second metal element, the material of the barrier layer does not include the second metal element, and the material of the seed layer does not include the third metal element. The seed layer provided in this embodiment of this application is made of a conductive dielectric material, which can prevent metal diffusion, the third metal element in the barrier layer, and the second metal element in the conductive dielectric material, so that the third metal element in the barrier layer cannot diffuse into the seed layer, the second metal element in the seed layer cannot diffuse into the barrier layer, and the barrier layer and the seed layer cannot form an alloy, thereby ensuring the reflection effect of the metal reflection layer.

[0011] In a possible implementation, the wafer includes multiple barrier layers arranged in a stack. By arranging multiple barrier layers away from the adhesion layer on the side of the metal reflection layer, the structural compactness of the multiple conductive dielectric layers can further prevent metal atom diffusion. In addition, arranging multiple barrier layers can improve the problem of reduced barrier effect caused by the fracture or presence of cavities in a single barrier layer. A better barrier effect can be achieved, and the stability of the wafer can be improved.

[0012] In a possible implementation, the materials of at least two barrier layers in the multiple barrier layers are different. Since different materials have different fracture inducements, the barrier layers made of different materials can reduce the probability of simultaneous fracture of barrier layers made of different materials, and further improve the barrier effect of the barrier layers.

[0013] In a possible implementation, the wafer further includes a transparent conductive layer, an adhesion layer, and a metal reflection layer arranged in sequence on the side of the second semiconductor layer facing the seed layer; and the material of the adhesion layer includes a conductive dielectric material. The performance of the conductive dielectric material is between that of the metal oxide of the transparent conductive layer and that of the metal of the metal reflection layer, which can improve the adhesion between the transparent conductive layer and the metal reflection layer, and improve the stability of the stacked structure in subsequent flow processing, for example, preventing the delamination and falling off of the stacked material in subsequent ultrasonic cleaning and chemical mechanical polishing, thereby improving the stability of the wafer. In addition, the conductive dielectric material has better light transmittance and thermal stability than metal materials, which can reduce light efficiency loss.

[0014] In a possible implementation, the resistivity of the material of the adhesion layer is less than 70 μΩ·cm. In this way, the adhesion between the transparent conductive layer and the metal reflection layer can be improved, and at the same time, the adhesion layer can form a good ohmic contact, thereby improving the electrical performance of a subsequently formed light emitting device.

[0015] In a possible implementation, the extinction coefficient of the adhesion layer for the visible light band is less than 3.0. In this way, the adhesion between the transparent conductive layer and the metal reflection layer can be improved, and at the same time, the adhesion layer has good light transmittance, thereby improving the light extraction efficiency of a subsequently formed light emitting device.

[0016] In a possible implementation, the wafer further includes a metal reflection layer arranged on the side of the second semiconductor layer facing the seed layer, and the reflectivity of the metal reflection layer to the visible light band is greater than 70%. The high reflectivity of the metal reflection layer to the visible light band achieves high reflection of the light emitted by the active layer, and improves the utilization rate of the visible light of the light-emitting device formed subsequently.

[0017] In a possible implementation, the material of the seed layer includes InN, TaN, TiB2, TiN, ZrN, or VN. This is a material with relatively good performance.

[0018] In a possible implementation, the thickness of the seed layer is 10 nm-50 nm. If the thickness of the seed layer is too small, the first metal bonding layer cannot be formed. If the thickness of the seed layer is too large, cracks are likely to occur. Limiting the thickness of the seed layer to 10 nm-50 nm can optimize the performance of the seed layer.

[0019] In a possible implementation, the thickness of the barrier layer is 10 nm-50 nm. If the thickness of the barrier layer is too small, the barrier layer cannot be flat and cannot play a barrier effect. If the thickness of the barrier layer is too large, the barrier layer itself will crack and cannot play a barrier effect. Limiting the thickness of the barrier layer to 10 nm-50 nm can optimize the barrier effect of the barrier layer.

[0020] In a possible implementation, the material of the barrier layer includes TiN, InN, ZrN, TaN, VN, HfN2, NbN, CrN, MoN, WN, TaC, ZrC, Cr3C2, TiB2, or ZrB2. This is a material with relatively good performance.

[0021] In a possible implementation, the thickness of the metal reflection layer is 10 nm-500 nm. If the thickness of the metal reflection layer is too small, the reflection effect is not ideal. If the thickness of the metal reflection layer is too large, the reflection effect cannot be further optimized. Limiting the thickness of the metal reflection layer to 10 nm-500 nm can make the reflection effect of the metal reflection layer relatively good, and does not excessively increase the thickness of the wafer.

[0022] In a possible implementation, the material of the metal reflection layer includes Al, Ag, Pt, Au, Cu, or Rh. This is a material with relatively good performance.

[0023] In a second aspect, the embodiment of the present application provides a wafer, which includes: a first semiconductor layer, an active layer, and a second semiconductor layer arranged in sequence; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. A metal reflection layer, a barrier layer, and a first metal bonding layer are arranged in sequence on the side of the second semiconductor layer away from the active layer, and the material of the barrier layer includes a conductive dielectric material.

[0024] The conductive dielectric material used as the barrier layer has certain rigidity, high structural density, small crystal structure defects and small pores, and can effectively block the diffusion of metal atoms and has good barrier effect. The conductive dielectric material is not easy to form recrystallization with the metal in the wafer bonding process, and has better barrier effect. Therefore, the problem that the metal reflective layer is alloyed with other metals to form cavities in the metal reflective layer, resulting in reduced reflectivity and stability of the metal reflective layer, can be improved, and the finally formed light emitting device has better stability and visible light utilization. In addition, compared with the metal barrier layer with strong ductility, the rigid conductive dielectric barrier layer with good chemical stability can effectively inhibit the deformation of the metal reflective layer and prevent the metal reflective layer from occurring diffuse reflection to reduce the reflectivity, thereby effectively improving the visible light utilization of the finally formed light emitting device.

[0025] In a possible implementation, the thickness of the barrier layer is 10 nm-50 nm.

[0026] In a possible implementation, the material of the barrier layer includes TiN, InN, ZrN, TaN, VN, HfN2, NbN, CrN, MoN, WN, TaC, ZrC, Cr3C2, TiB2 or ZrB2.

[0027] In a possible implementation, the reflectivity of the metal reflective layer to the visible light band is greater than 70%.

[0028] In a possible implementation, the thickness of the metal reflective layer is 10 nm-500 nm.

[0029] In a possible implementation, the material of the metal reflective layer includes Al, Ag, Pt, Au, Cu or Rh.

[0030] In a possible implementation, the wafer further includes an adhesion layer and a transparent conductive layer arranged in sequence on the side of the metal reflective layer away from the second semiconductor layer; the material of the adhesion layer includes the conductive dielectric material.

[0031] In a possible implementation, the resistivity of the material of the adhesion layer is less than 70 μΩ·cm, or the extinction coefficient of the adhesion layer to the visible light band is less than 3.0.

[0032] In a third aspect, the application provides a wafer, comprising: a first semiconductor layer, an active layer, and a second semiconductor layer stacked; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer; a metal reflection layer, an adhesion layer, and a transparent conductive layer are sequentially arranged on a side of the second semiconductor layer away from the active layer; the material of the adhesion layer comprises a conductive dielectric material, and the material resistivity of the adhesion layer is less than 70 μΩ·cm, and the extinction coefficient of the adhesion layer in a visible light band is less than 3.0.

[0033] The conductive dielectric material has a performance between the metal oxide of the transparent conductive layer and the metal of the metal reflection layer, can improve the adhesion between the transparent conductive layer and the metal reflection layer, and can improve the stability of the stacked structure in subsequent flow processing, for example, can prevent the delamination and falling off of the stacked material in subsequent ultrasonic cleaning and chemical mechanical polishing, thereby improving the stability of the wafer. In addition, the conductive dielectric material has better light transmittance and thermal stability than the metal material, and can reduce light efficiency loss.

[0034] In a possible implementation, the material resistivity of the adhesion layer is less than 70 μΩ·cm, or the extinction coefficient of the adhesion layer in a visible light band is less than 3.0.

[0035] In a possible implementation, the reflectivity of the metal reflection layer in a visible light band is greater than 70%.

[0036] In a possible implementation, the thickness of the metal reflection layer is 10 nm-500 nm.

[0037] In a possible implementation, the material of the metal reflection layer comprises Al, Ag, Pt, Au, Cu, or Rh.

[0038] In a fourth aspect, the application provides a wafer stack, comprising a wafer and a driving substrate, the wafer comprising the wafer of any one of the first aspect, the second aspect, or the third aspect; and a metal bonding layer bonded to the driving substrate.

[0039] In a fifth aspect, the application provides a light emitting device, obtained by pixelizing the wafer stack of the fourth aspect.

[0040] In a sixth aspect, the application provides a terminal, comprising a light emitting device and a housing, the light emitting device being arranged in the housing, and the light emitting device comprising the light emitting device of the fifth aspect.

[0041] In a seventh aspect, the present application provides a wafer preparation method, which comprises: forming a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer; forming a seed layer on a side of the second semiconductor layer away from the active layer; and forming a metal bonding layer on a surface of the seed layer away from the second semiconductor layer; wherein the material of the seed layer comprises a conductive dielectric material, and the crystal phase of the material of the seed layer is the same as that of the material of the metal bonding layer.

[0042] In a possible implementation, the material of the seed layer comprises InN, TaN, TiB2, TiN, ZrN or VN.

[0043] In a possible implementation, the thickness of the seed layer is 10-50 nm.

[0044] In a possible implementation, before forming the seed layer, the preparation method further comprises: forming a barrier layer on a side of the second semiconductor layer away from the active layer, and the material of the barrier layer comprises a conductive dielectric material.

[0045] In a possible implementation, the thickness of the barrier layer is 10-50 nm.

[0046] In a possible implementation, the material of the barrier layer comprises TiN, InN, ZrN, TaN, VN, HfN2, NbN, CrN, MoN, WN, TaC, ZrC, Cr3C2, TiB2 or ZrB2.

[0047] In a possible implementation, before forming the seed layer, the preparation method further comprises: sequentially forming a transparent conductive layer, an adhesion layer and a metal reflection layer on a side of the second semiconductor layer away from the active layer; and the material of the adhesion layer has a resistivity less than 70 μΩ·cm and an extinction coefficient in a visible light band less than 3.0.

[0048] In a possible implementation, the material of the seed layer comprises InN, TaN, TiB2, TiN, ZrN or VN.

[0049] In a possible implementation, the thickness of the seed layer is 10-50 nm.

[0050] In a possible implementation, the metal reflection layer has a reflectivity greater than 70% in the visible light band.

[0051] In a possible implementation, the thickness of the metal reflection layer is 10-500 nm.

[0052] In a possible implementation, the material of the metal reflection layer comprises Al, Ag, Pt, Au, Cu or Rh. BRIEF DESCRIPTION OF DRAWINGS

[0053] FIG. 1A is a schematic diagram of an AR glass according to an embodiment of the present application;

[0054] FIG. 1B is a schematic diagram of a display screen according to an embodiment of the present application;

[0055] FIG. 2A and FIG. 2B are schematic diagrams of a light emitting device according to an embodiment of the present application;

[0056] FIG. 3 is a schematic diagram of a wafer stack according to an embodiment of the present application;

[0057] FIG. 4 is a schematic diagram of a wafer according to an embodiment of the present application;

[0058] FIG. 5A and FIG. 5B are schematic diagrams of another wafer according to an embodiment of the present application;

[0059] FIG. 6A and FIG. 6B are sectional views of a wafer according to an embodiment of the present application;

[0060] FIG. 7A is an interface diagram of a metal bonding layer according to an embodiment of the present application;

[0061] FIG. 7B is a bonding interface diagram of a metal bonding layer according to an embodiment of the present application;

[0062] FIG. 8A is an interface diagram of another metal bonding layer according to an embodiment of the present application;

[0063] FIG. 8B is a bonding interface diagram of another metal bonding layer according to an embodiment of the present application;

[0064] FIG. 9 is a flowchart of a method for preparing a wafer stack according to an embodiment of the present application;

[0065] FIG. 10-FIG. 20 are schematic diagrams of a preparation process of a wafer stack according to an embodiment of the present application;

[0066] FIG. 21 is a top view of a wafer stack according to an embodiment of the present application;

[0067] FIG. 22 is a schematic diagram of a light emitting device according to an embodiment of the present application;

[0068] FIG. 23 is a schematic diagram of another wafer according to an embodiment of the present application;

[0069] FIG. 24 is a schematic diagram of a light emitting device according to an embodiment of the present application;

[0070] FIG. 25 is a schematic diagram of another wafer according to an embodiment of the present application;

[0071] FIG. 26 is a structural schematic diagram of a light-emitting device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0073] Hereinafter, the terms "second", "first", and the like are only used for description convenience, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "second", "first", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0074] In addition, in the embodiments of the present application, the orientation terms such as "upper", "lower", "left", "right", and the like can include, but are not limited to, the orientation defined by the relative position of the components in the drawings. It should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the position of the components in the drawings.

[0075] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through an intermediate medium. In addition, the term "coupling" can be direct electrical connection, or indirect electrical connection through an intermediate medium. The term "contact" can be direct contact, or indirect contact through an intermediate medium.

[0076] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, wherein A and B can be singular or plural. The character " / " generally represents that the associated objects before and after the character are in an "or" relationship.

[0077] Embodiments of the present application provide a terminal, which can be, for example, an electronic device, a light emitting device, or other products that need to use a light source. The electronic device can be, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial electronic product. The consumer electronic product can be, for example, a mobile phone, a pad, a notebook computer, an e-reader, a personal computer (PC), a personal digital assistant (PDA), a desktop display, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, a drone, or the like. The home electronic product can be, for example, a smart door lock, a television, a refrigerator, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), or the like. The vehicle-mounted electronic product can be, for example, a vehicle-mounted navigator, a vehicle-mounted DVD, or the like. The financial electronic product can be, for example, an ATM machine, a self-service electronic device, or the like. The light emitting device can be, for example, a flashlight, a car lamp, an illuminating lamp, a colored lamp, or the like. Other products that need to use a light source can be, for example, a printer, or the like.

[0078] Taking an AR head-mounted display device as an example of the electronic device, the AR head-mounted display device can include AR glasses or an AR helmet, and the like. For ease of illustration, refer to FIG. 1A, which is a schematic diagram of AR glasses provided by an embodiment of the present application.

[0079] The AR glasses include a frame 101, a temple 102, and a lens 103. The lens 103 is mounted on the frame 101, and the temple 102 is connected to the frame 101. The temple 102 and the frame 101 can be worn in front of the eyes of a user. A display screen 200 is arranged in the temple 102, and can display an image or other content. The lens 103 is a light waveguide lens. The image or other content displayed by the display screen 200 can be transmitted to the lens 103 through light waveguide to be displayed and imaged in front of the eyes of the user.

[0080] The display screen 200 in the temple 102 can be a micro light emitting diode (Micro LED) display screen, a mini light emitting diode (Mini LED) display screen, a light emitting diode (LED) display screen, or the like.

[0081] FIG. 1B is a schematic diagram of a display screen provided by an embodiment of the present application.

[0082] As shown in FIG. IB, the display screen 200 includes a substrate 2 and a plurality of light emitting devices 3 arranged on the substrate 2. The plurality of light emitting devices 3 may, for example, include a light emitting device for emitting red light, a light emitting device for emitting green light, and a light emitting device for emitting blue light to realize a three-primary color display of the display screen 200.

[0083] When the terminal is a flashlight or the like that emits white light, the light emitting device 3 arranged on the substrate can be a light emitting device for emitting white light. The light emitting color of the light emitting device is not limited in the embodiments of the present application in combination with the specific structure of the terminal.

[0084] FIGS. 2A and 2B are schematic diagrams of a structure of a light emitting device according to an embodiment of the present application.

[0085] In some embodiments, as shown in FIG. 2A, the light emitting device 3 includes a first semiconductor layer 31, an active layer 32, a second semiconductor layer 33, a transparent conductive layer 34, a metal adhesion layer 35', a metal bonding layer 38', and a driving substrate 40 arranged in layers.

[0086] One of the first semiconductor layer 31 and the second semiconductor layer 33 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. For example, the first semiconductor layer 31 is an N-type semiconductor layer, and the second semiconductor layer 33 is a P-type semiconductor layer. Alternatively, for example, the first semiconductor layer 31 is a P-type semiconductor layer, and the second semiconductor layer 33 is an N-type semiconductor layer.

[0087] Since the material of the transparent conductive layer 34 is generally a metal oxide, the material of the metal bonding layer 38' includes a metal. Therefore, the metal adhesion layer 35' is arranged between the transparent conductive layer 34 and the metal bonding layer 38' to solve the problem of poor adhesion between the transparent conductive layer 34 and the metal bonding layer 38'.

[0088] The active layer 32 of the common light emitting device 3 is isotropic light emission. As shown in FIG. 2A, about 50% of the light is emitted upward and utilized. About 50% of the light is emitted downward and absorbed by the lower film layer and cannot be utilized.

[0089] In other embodiments, as shown in FIG. 2B, the light emitting device 3 further includes a metal reflection layer 36 between the metal adhesion layer 35' and the metal bonding layer 38', so that the downward light is reflected upward by the metal reflection layer 36 and utilized.

[0090] Since the transparent conductive layer 34 and the metal reflection layer 36 generally have poor adhesion, the metal adhesion layer 35' is arranged between the transparent conductive layer 34 and the metal reflection layer 36.

[0091] The metal adhesion layer 35' needs to have good conductivity and light transmittance while improving the adhesion of the transparent conductive layer 34 and the metal reflective layer 36. Common metal adhesion layer 35' materials include chromium (Cr), platinum (Pt), and other metal materials. However, metal materials generally have poor light transmittance and thermal stability problems, for example, the light transmittance of Cr with a thickness of more than 10 nm is less than 60%, resulting in a decrease in the efficiency of the active layer 32.

[0092] Embodiments of the present application provide a light emitting device 3 for improving the above problems and optimizing the performance of the light emitting device 3. The light emitting device 3 provided by the embodiments of the present application is obtained by pixelizing the wafer stack provided by the embodiments of the present application. Pixelization can be understood as the process of cutting the wafer stack into light emitting devices 3. For example, pixelization includes steps such as photolithography, etching, passivation, etc.

[0093] The wafer stack provided by the embodiments of the present application is schematically described below.

[0094] FIG. 3 is a structural schematic diagram of a wafer stack provided by an embodiment of the present application.

[0095] As shown in FIG. 3, the wafer stack 300 includes a wafer 30 and a driving substrate 40, and the wafer 30 and the driving substrate 40 are bonded.

[0096] The driving substrate 40 includes, for example, a substrate 41, a plurality of driving circuits 42 disposed on the substrate 41, a plurality of second electrodes 43 corresponding to the plurality of driving circuits 42, and a second metal bonding layer 44 disposed on the side of the plurality of second electrodes 43 away from the substrate 41, and the second electrodes 43 are coupled to the second metal bonding layer 44.

[0097] The material of the substrate 41 can be a semiconductor material such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc., or a non-conductive material such as glass, plastic, or sapphire wafer, etc.

[0098] In some embodiments, as shown in FIG. 3, the wafer stack 300 further includes a first electrode 50 disposed on the side of the wafer 30 away from the driving substrate 40.

[0099] FIG. 4 is a structural schematic diagram of a wafer provided by an embodiment of the present application.

[0100] Embodiments of the present application provide a wafer 30, as shown in FIG. 4, the wafer 30 includes an epitaxial stack formed on an epitaxial substrate, and the epitaxial stack includes a first semiconductor layer 31, an active layer 32, and a second semiconductor layer 33 which are sequentially stacked.

[0101] One of the first semiconductor layer 31 and the second semiconductor layer 33 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. The doping types of the two semiconductor layers are opposite. If the first semiconductor layer 31 is doped with N-type, the second semiconductor layer 33 is doped with P-type. If the first semiconductor layer 31 is doped with P-type, the second semiconductor layer 33 is doped with N-type. Both of the above structures can be applied in specific implementations.

[0102] For example, the first semiconductor layer 31 can be doped with P-type or N-type in a semiconductor material (such as gallium oxide or the like), so that the first semiconductor layer 31 can provide holes or electrons. The active layer 32 can adopt a multi-quantum well layer to improve the light emitting efficiency. The second semiconductor layer 33 can be doped with N-type or P-type in a semiconductor material (such as gallium oxide or the like), so that the second semiconductor layer 33 can provide electrons or holes.

[0103] The base material of the first semiconductor layer 31 and the second semiconductor layer 33 includes gallium nitride (GaN), aluminum gallium indium phosphide (AlGaInP), or the like.

[0104] In some embodiments, the wafer 30 further includes a transparent conductive layer 34, which is disposed on the side of the second semiconductor layer 33 away from the first semiconductor layer 31.

[0105] The material of the transparent conductive layer 34 includes a transparent conductive material. For example, the material of the transparent conductive layer 34 includes a metal oxide. For example, the material of the transparent conductive layer 34 includes indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (ZnO:Al, AZO), fluorine-doped tin oxide (SnO2:F, FTO), or the like.

[0106] For example, the thickness of the transparent conductive layer 34 is 10 nm to 500 nm. For example, the thickness of the transparent conductive layer 34 is 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm.

[0107] In some embodiments, the wafer 30 further includes an adhesion layer 35 and a metal reflective layer 36, the adhesion layer 35 is disposed on the side of the transparent conductive layer 34 away from the second semiconductor layer 33, and the metal reflective layer 36 is disposed on the side of the adhesion layer 35 away from the second semiconductor layer 33.

[0108] In some embodiments, the material of the adhesion layer 35 includes a metal material such as Cr or Pt.

[0109] In other embodiments, the material of the adhesion layer 35 includes a conductive dielectric material.

[0110] The conductive dielectric material can be understood as an inorganic non-metallic conductive compound, and includes a compound of a non-metallic element and one metallic element. Alternatively, the conductive dielectric material includes a solid solution compound of a non-metallic element and multiple metallic elements.

[0111] The conductive dielectric material has a performance between the metal oxide of the transparent conductive layer 34 and the metal of the metal reflective layer 36, can improve the adhesion between the transparent conductive layer 34 and the metal reflective layer 36, and can improve the stability of the stacked structure in subsequent flow processing, for example, can prevent the delamination of the stacked material in subsequent ultrasonic cleaning and chemical mechanical polishing processes, thereby improving the stability of the wafer 30. Moreover, the conductive dielectric material has better light transmittance and thermal stability than the metal material, and can reduce the loss of light efficiency.

[0112] Optionally, the resistivity of the material of the adhesion layer 35 is less than 70 μΩ·cm. For example, the resistivity of the material of the adhesion layer 35 is less than 65 μΩ·cm, 60 μΩ·cm, 55 μΩ·cm, 50 μΩ·cm, 45 μΩ·cm, 40 μΩ·cm, 35 μΩ·cm, or 30 μΩ·cm, etc.

[0113] In this way, the adhesion between the transparent conductive layer 34 and the metal reflective layer 36 can be improved, and the adhesion layer 35 can form a good ohmic contact, thereby improving the electrical performance of the wafer 30.

[0114] Optionally, the extinction coefficient of the adhesion layer 35 to the visible light band is less than 3.0. For example, the extinction coefficient of the adhesion layer 35 to the visible light band is less than 2.5, 2.0, 1.5, 1.0, etc.

[0115] In this way, the adhesion between the transparent conductive layer 34 and the metal reflective layer 36 can be improved, and the adhesion layer 35 can have good light transmittance, thereby improving the light extraction efficiency of the wafer 30.

[0116] For example, the material of the adhesion layer 35 includes TiN. This is a material with relatively good performance.

[0117] In some embodiments, the thickness of the adhesion layer 35 is 1 nm-10 nm. For example, the thickness of the adhesion layer 35 is 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm.

[0118] The adhesion layer 35 needs to have relatively strong light transmittance. If the thickness of the adhesion layer 35 is too thick, the adhesion layer 35 is not transparent, and if the thickness of the adhesion layer 35 is too thin, the adhesion layer 35 has no adhesion effect. By setting the thickness of the adhesion layer 35 to be in the range of 1 nm-10 nm, the adhesion and light transmittance of the adhesion layer 35 can be relatively good.

[0119] In some embodiments, the metal reflective layer 36 has a reflectivity greater than 70% in the visible light band. For example, the metal reflective layer 36 has a reflectivity greater than 75%, 80%, 85%, 90% in the visible light band.

[0120] The high reflectivity of the metal reflective layer 36 in the visible light band itself achieves a high reflection effect on the light emitted by the active layer 32, and improves the visible light utilization of the wafer 30.

[0121] For example, the material of the metal reflective layer 36 includes aluminum (Al), silver (Ag), platinum (Pt), gold (Au), copper (Cu), or rhodium (Rh), etc. The metal reflective layer 36 formed by these materials has high reflectivity and low cost.

[0122] In some embodiments, the thickness of the metal reflective layer 36 is 10 nm-500 nm. For example, the thickness of the metal reflective layer 36 is 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm.

[0123] If the thickness of the metal reflective layer 36 is too thin, the reflection effect is not ideal, and if the thickness of the metal reflective layer 36 is too thick, the reflection effect cannot be further optimized. By limiting the thickness of the metal reflective layer 36 to the range of 10 nm-500 nm, the reflection effect of the metal reflective layer 36 is relatively optimal, and the thickness of the wafer 30 is not excessively increased.

[0124] In some embodiments, the wafer 30 further includes a barrier layer 37, which is disposed on the side of the metal reflective layer 36 away from the second semiconductor layer 33.

[0125] For example, the material of the barrier layer 37 includes metal materials such as platinum (Pt) and Cu.

[0126] Alternatively, for example, the material of the barrier layer 37 includes conductive dielectric materials.

[0127] For example, the material of the barrier layer 37 includes titanium nitride (TiN), indium nitride (InN), zirconium nitride (ZrN), tantalum nitride (TaN), vanadium nitride (VN), hafnium nitride (HfN2), niobium nitride (NbN), chromium nitride (CrN), molybdenum nitride (MoN), tungsten nitride (WN), tantalum carbide (TaC), zirconium carbide (ZrC), chromium carbide (Cr3C2), titanium diboride (TiB2), or zirconium diboride (ZrB2).

[0128] The crystal phase of the material of the barrier layer 37 includes, but is not limited to, pure phases such as tetragonal, cubic, or hexagonal phases, or the crystal phase of the material of the barrier layer 37 includes a mixed phase of two or more.

[0129] The barrier layer 37 formed by the materials has good barrier effect and low cost.

[0130] FIGS. 5A and 5B are structural schematic diagrams of another wafer provided by the embodiments of the present application.

[0131] In some embodiments, as shown in FIG. 5A, the wafer 30 includes multiple barrier layers 37 stacked.

[0132] For example, the materials of the multiple barrier layers 37 are the same.

[0133] Alternatively, for example, the materials of at least two barrier layers 37 in the multiple barrier layers 37 are different.

[0134] For example, as shown in FIG. 5A, the multiple barrier layers 37 include a first barrier layer 371 and a second barrier layer 372, the first barrier layer 371 and the second barrier layer 372 form a repeating unit, and the wafer 30 includes multiple repeating units.

[0135] Alternatively, for example, as shown in FIG. 5B, the multiple barrier layers 37 are stacked irregularly. The materials of the multiple barrier layers 37 can be different, and the materials of some barrier layers 37 in the multiple barrier layers 37 can be the same.

[0136] By arranging the multiple barrier layers 37 on the side of the metal reflection layer 36 away from the adhesion layer 35, the structural compactness of the multiple conductive media can be used to further prevent the diffusion of metal atoms. Moreover, the arrangement of the multiple barrier layers 37 can improve the problem of reduced barrier effect caused by the fracture or presence of cavities in the single barrier layer 37. Better barrier effect can be achieved, and the stability of the wafer 30 can be improved. Since different materials have different fracture inducements, the use of different materials for the multiple barrier layers 37 can reduce the probability of simultaneous fracture of barrier layers 37 made of different materials, and further improve the barrier effect.

[0137] In some embodiments, the thickness of each barrier layer 37 is 10 nm-50 nm. For example, the thickness of the barrier layer 37 is 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm.

[0138] If the thickness of the barrier layer 37 is too thin, the barrier layer 37 cannot be laid flat, and the barrier effect cannot be achieved. If the thickness of the barrier layer 37 is too thick, the barrier layer 37 itself will crack, and the barrier effect cannot be achieved. Limiting the thickness of the barrier layer 37 to the range of 10 nm-50 nm can optimize the barrier effect of the barrier layer 37.

[0139] FIGS. 6A and 6B are sectional views of a wafer provided by the embodiments of the present application.

[0140] As shown in FIG. 6A, when the barrier layer 37 is a metal material such as molybdenum (Mo) and tantalum (Ta), a large number of holes exist in the conductive stack below the second semiconductor layer 33 due to poor barrier effect of the metal atoms. In addition, the metal reflective layer 36 is deformed during the high-temperature process due to the ductility of the metal itself, and thus the metal reflective layer 36 is diffused and the reflectivity is reduced.

[0141] As shown in FIG. 6B, when the barrier layer 37 is a conductive dielectric material, the conductive stack below the second semiconductor layer 33 has a clear interface, and no holes or recrystallization phenomenon occurs. In addition, the metal reflective layer 36 is not deformed during the wafer bonding process.

[0142] The conductive dielectric material with certain rigidity, high structural density, small crystal structure defects, and small pores as the barrier layer 37 can effectively block the diffusion of metal atoms and has good barrier effect. In addition, the conductive dielectric material is not easy to form recrystallization with the metal during the wafer bonding process, and has better barrier effect. Therefore, the problem that the metal reflective layer 36 is alloyed with other metals to form holes, resulting in reduced reflectivity and stability of the metal reflective layer 36, can be solved, and the final formed light emitting device has better stability and visible light utilization rate. In addition, compared with the metal barrier layer with strong ductility, the rigid conductive dielectric barrier layer with good chemical stability can effectively prevent the metal reflective layer 36 from being deformed, prevent the metal reflective layer 36 from being diffused and the reflectivity from being reduced, and thus the visible light utilization rate of the final formed light emitting device can be effectively improved.

[0143] As shown in FIG. 4, in some embodiments, the wafer 30 further includes a seed layer 39 and a metal bonding layer (referred to as a first metal bonding layer 38 in the embodiments of the present application), the seed layer 39 is disposed on the side of the barrier layer 37 away from the active layer 32, and the first metal bonding layer 38 is disposed on the surface of the seed layer 39 away from the second semiconductor layer 33.

[0144] In some embodiments, the material of the first metal bonding layer 38 includes Au, Ag, Cu, Ti, Al, and the like.

[0145] In some embodiments, the thickness of the first metal bonding layer 38 is 10 nm-500 nm. For example, the thickness of the first metal bonding layer 38 is 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm.

[0146] In some embodiments, the material of the seed layer 39 comprises a conductive dielectric material, and the crystal phase of the material of the seed layer 39 is the same as that of the material of the first metal bonding layer 38. For example, the crystal phase of the material of the seed layer 39 is the same as that of the material of the first metal bonding layer 38 below 500 DEG C. After the bonding of the first metal bonding layer 38, the crystal phase may change under the influence of high temperature, resulting in the crystal phase of the material of the seed layer 39 being different from that of the material of the first metal bonding layer 38. However, the material selected for the first metal bonding layer 38 is not bonded (below 500 DEG C), and the crystal phase of the material of the seed layer 39 is the same as that of the material of the first metal bonding layer 38.

[0147] FIG. 7A is an interface diagram of a metal bonding layer according to an embodiment of the present application, and FIG. 7B is a bonding interface diagram of a metal bonding layer according to an embodiment of the present application.

[0148] As shown in FIG. 7A, when the seed layer 39 is not provided in the wafer 30, the grains of the metal in the first metal bonding layer 38 are coarse, resulting in a large surface roughness of the first metal bonding layer 38, a poor bonding effect, and a failed bonding. As shown in FIG. 7B, there are many bubbles at the bonding interface between the wafer 30 and the driving substrate 40.

[0149] FIG. 8A is an interface diagram of another metal bonding layer according to an embodiment of the present application, and FIG. 8B is a bonding interface diagram of another metal bonding layer according to an embodiment of the present application.

[0150] As shown in FIG. 8A, after the seed layer 39 is provided in the wafer 30, the growth of the metal grains in the first metal bonding layer 38 is controlled, the size of the metal grains is uniform, the surface roughness of the first metal bonding layer 38 is small, the bonding effect is good, and the bonding success rate is improved. As shown in FIG. 8B, the bonding interface between the wafer 30 and the driving substrate 40 is full, and there are no bubbles or the bubbles are reduced and decreased.

[0151] In the embodiments of the present application, the seed layer 39 having the same crystal phase as the first metal bonding layer 38 is provided in the wafer 30. When the first metal bonding layer 38 is formed on the surface of the seed layer 39, the seed layer 39 and the first metal bonding layer 38 are lattice matched, so that the seed layer 39 can control the crystal growth process of the first metal bonding layer 38, the lattice distortion of the grown first metal bonding layer 38 is small, the surface roughness of the grains is small, the crystallization quality of the first metal bonding layer 38 is ensured, and the bonding effect of the first metal bonding layer 38 is improved. In addition, the seed layer 39 is located on the side of the barrier layer 37 away from the metal reflection layer 36. When the metal reflection layer 36 and the first metal bonding layer 38 are deformed at high temperature, the seed layer 39 having a large stiffness can provide a reverse force to the barrier layer 37, preventing the barrier layer 37 from breaking. That is, the seed layer 39 can improve the problem that the barrier layer 37 breaks to form holes and causes metal diffusion, and further strengthen the effect of preventing metal diffusion.

[0152] In some embodiments, the material of the seed layer 39 includes InN, TaN, TiB2, TiN, ZrN, or VN. The seed layer 39 of these materials can make the first metal bonding layer 38 have better bonding effect.

[0153] For example, the material of the first metal bonding layer 38 is Ti, adopts hexagonal crystal phase, and the material of the seed layer 39 includes InN, TaN, TiB2, etc.

[0154] For another example, the material of the first metal bonding layer 38 is Cu, Ag, Au, or Al, adopts face-centered cubic crystal phase, and the material of the seed layer 39 includes TiN, ZrN, or VN.

[0155] In some embodiments, the thickness of the seed layer 39 is 10 nm-50 nm. For example, the thickness of the seed layer 39 is 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm.

[0156] If the thickness of the seed layer 39 is too thin, it is not conducive to the formation of the first metal bonding layer 38. If the thickness of the seed layer 39 is too thick, cracks are prone to occur. Limiting the thickness of the seed layer 39 to 10 nm-50 nm can optimize the performance of the seed layer 39.

[0157] In some embodiments, the material of the first metal bonding layer 38 includes a first metal element, the material of the seed layer 39 includes a second metal element, the material of the seed layer 39 does not include the first metal element, and the material of the first metal bonding layer 38 does not include the second metal element.

[0158] The seed layer 39 provided by the embodiments of the present application is selected from a conductive medium material. The conductive medium material can prevent metal diffusion. The first metal bonding layer 38 includes a first metal element, the conductive medium material includes a second metal element, the first metal element in the first metal bonding layer 38 will not diffuse into the seed layer 39, the second metal element in the seed layer 39 will not diffuse into the first metal bonding layer 38, and the first metal bonding layer 38 and the seed layer 39 will not form an alloy, so as to ensure the bonding effect of the first metal bonding layer 38.

[0159] In some embodiments, the material of the barrier layer 37 includes a third metal element, the material of the seed layer 39 includes a second metal element, the material of the seed layer 39 does not include the third metal element, and the material of the barrier layer 37 does not include the second metal element.

[0160] The seed layer 39 provided by the embodiment of the present application is made of a conductive medium material, which can prevent metal diffusion. The barrier layer 37 includes a third metal element, and the conductive medium material includes a second metal element. The third metal element in the barrier layer 37 cannot diffuse into the seed layer 39, and the second metal element in the seed layer 39 cannot diffuse into the barrier layer 37. The barrier layer 37 and the seed layer 39 cannot form an alloy, so as to ensure the reflection effect of the metal reflection layer 36.

[0161] FIG. 9 is a flowchart of a preparation method of a wafer stack provided by an embodiment of the present application. FIGS. 10-20 are schematic diagrams of a preparation process of a wafer stack provided by an embodiment of the present application.

[0162] The embodiment of the present application further provides a preparation method of a wafer stack, which is used for preparing the wafer stack 300. As shown in FIG. 9, the preparation method of the wafer stack includes the following steps.

[0163] S10, as shown in FIG. 10, a first semiconductor layer 31, an active layer 32 and a second semiconductor layer 33 are sequentially formed on an epitaxial substrate.

[0164] For example, the epitaxial process is adopted to sequentially form the first semiconductor layer 31, the active layer 32 and the second semiconductor layer 33 on the epitaxial substrate.

[0165] S20, as shown in FIG. 11, a transparent conductive layer 34 is formed on the side of the second semiconductor layer 33 away from the active layer 32.

[0166] For example, the plating film process such as sputtering or electron beam evaporation is adopted to form the transparent conductive layer 34 on the surface of the second semiconductor layer 33.

[0167] S30, as shown in FIG. 12, an adhesion layer 35 is formed on the side of the transparent conductive layer 34 away from the second semiconductor layer 33.

[0168] For example, the process such as magnetron sputtering or atomic layer deposition (ALD) is adopted to form the adhesion layer 35 on the surface of the transparent conductive layer 34.

[0169] S40, as shown in FIG. 13, a metal reflection layer 36 is formed on the side of the adhesion layer 35 away from the second semiconductor layer 33.

[0170] For example, the process such as magnetron sputtering, electron beam evaporation or thermal evaporation is adopted to form the metal reflection layer 36 on the surface of the adhesion layer 35.

[0171] S50, as shown in FIG. 14, a barrier layer 37 is formed on the side of the metal reflection layer 36 away from the second semiconductor layer 33.

[0172] For example, the barrier layer 37 is formed on the surface of the metal reflective layer 36 by using a process such as magnetron sputtering, atomic layer deposition, etc.

[0173] When the wafer 30 includes one layer of the barrier layer 37, the step S50 is performed once. When the wafer 30 includes multiple layers of the barrier layer 37, the step S50 is performed multiple times.

[0174] S60, as shown in FIG. 15, a seed layer 39 is formed on the side of the barrier layer 37 away from the second semiconductor layer 33.

[0175] For example, the seed layer 39 is formed on the surface of the barrier layer 37 by using a process such as magnetron sputtering, atomic layer deposition, etc.

[0176] S70, as shown in FIG. 16, a first metal bonding layer 38 is formed on the surface of the seed layer 39 away from the second semiconductor layer 33.

[0177] For example, the first metal bonding layer 38 is formed on the surface of the seed layer 39 by using a process such as magnetron sputtering, electron beam evaporation, or thermal evaporation, etc. The material of the first metal bonding layer 38 can be the same as the material of the metal bonding layer 38' in the wafer 30.

[0178] For example, before the step S90 is performed, the surface of the first metal bonding layer 38 is planarized by using a chemical mechanical polishing (CMP) process, so that the surface roughness (root mean square, RMS) of the first metal bonding layer 38 is less than 0.8 nm.

[0179] In the embodiment, the adhesion layer 35, the metal reflective layer 36, the barrier layer 37, the seed layer 39, and the first metal bonding layer 38 in the stack structure obtained in the step S70 constitute a part of a bonding stack. The steps S10-S70 are a wafer preparation method provided in the embodiment, and after the steps S10-S70 are performed, the wafer 300 provided in the embodiment can be obtained.

[0180] S80, as shown in FIG. 17, a drive substrate 40 including a second metal bonding layer 44 is formed.

[0181] For example, the second metal bonding layer 44 is formed on the surface of the drive substrate 40 by using a process such as magnetron sputtering, electron beam evaporation, or thermal evaporation, etc. The material of the second metal bonding layer 44 can be the same as the material of the metal bonding layer 38' in the wafer 30.

[0182] For example, before performing the following step S90, the surface of the second metal bonding layer 44 is planarized by a chemical mechanical polishing process, so that the surface roughness (root mean square, RMS) of the second metal bonding layer 44 is less than 0.8 nm.

[0183] Steps S10-S70 are used to prepare the wafer 300, and step S80 is used to prepare the driving substrate 40. There is no order limitation between steps S10-S70 and step S80. Steps S10-S70 can be performed first, and then step S80 can be performed. Alternatively, step S80 can be performed first, and then steps S10-S70 can be performed. Alternatively, steps S10-S70 and step S80 can be performed simultaneously.

[0184] S90, as shown in FIG. 18, the wafer 30 obtained in step S70 and the driving substrate 40 obtained in step S80 are bonded, and the first metal bonding layer 38 and the second metal bonding layer 44 are bonded.

[0185] For example, the stacked structure obtained in step S70 and the stacked structure obtained in step S80 are bonded by a wafer bonding device, the bonding temperature is 300-500°C, the bonding time is 1-10 h, and the bonding pressure is 0-20 kN.

[0186] S100, as shown in FIG. 19, the epitaxial substrate is removed.

[0187] For example, the epitaxial substrate is removed by laser peeling, chemical etching, or inductively coupled plasma (ICP) etching.

[0188] S110, as shown in FIG. 20, a first electrode 50 is formed on the side of the first semiconductor layer 31 away from the active layer 32.

[0189] After performing step S110, the wafer stack 300 provided in the embodiments of the present application is obtained.

[0190] FIG. 21 is a top view of a wafer stack provided in an embodiment of the present application.

[0191] As shown in FIG. 21, the wafer stack 300 includes a plurality of light emitting devices 3. After the wafer stack 300 is prepared, the wafer stack 300 is pixelated to obtain the light emitting device 3 provided in the embodiments of the present application.

[0192] FIG. 22 is a structural schematic view of a light emitting device provided in an embodiment of the present application.

[0193] In some embodiments, as shown in FIG. 22, the light emitting device 3 provided by the embodiments of the present application comprises, in sequence, a first electrode 50, a first semiconductor layer 31, an active layer 32, a second semiconductor layer 33, a transparent conductive layer 34, an adhesion layer 35, a metal reflective layer 36, a barrier layer 37, a seed layer 39, a metal bonding layer 38', a second electrode 43, a driving circuit 42, and a substrate 41.

[0194] The structural characteristics of each film layer can refer to the above description of the wafer stack 300, which will not be repeated here.

[0195] FIG. 23 is a structural schematic diagram of another wafer provided by the embodiments of the present application, and FIG. 24 is a structural schematic diagram of a light emitting device provided by the embodiments of the present application.

[0196] As shown in FIG. 23, the embodiments of the present application also provide a wafer 30, which is different from the wafer 30 shown in FIG. 4 in that the wafer 30 does not include a seed layer 39, and the material of the barrier layer 37 can only be a conductive medium material, but cannot be a metal material.

[0197] The structures and materials of other film layers in the wafer 30 can be the same as described above, which will not be repeated here. The preparation method of the wafer 30 can also be the same as described above, and the step of preparing the seed layer 39 can be omitted.

[0198] The wafer 30 shown in FIG. 23 can also be applied to the wafer stack 300 provided by the embodiments of the present application. After pixelization processing of the wafer stack 300, another light emitting device 3 provided by the embodiments of the present application can be obtained (as shown in FIG. 24).

[0199] FIG. 25 is a structural schematic diagram of another wafer provided by the embodiments of the present application, and FIG. 26 is a structural schematic diagram of a light emitting device provided by the embodiments of the present application.

[0200] As shown in FIG. 25, the embodiments of the present application also provide a wafer 30, which is different from the wafer 30 shown in FIG. 4 in that the wafer 30 does not include a seed layer 39, and the material of the adhesion layer 35 can only be a conductive medium material, but cannot be a metal material.

[0201] The structures and materials of other film layers in the wafer 30 can be the same as described above, which will not be repeated here. The preparation method of the wafer 30 can also be the same as described above, and the step of preparing the seed layer 39 can be omitted.

[0202] The wafer 30 shown in FIG. 25 can also be applied to the wafer stack 300 provided by the embodiments of the present application. After pixelization processing of the wafer stack 300, another light emitting device 3 provided by the embodiments of the present application can be obtained (as shown in FIG. 26).

[0203] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

A wafer, characterized by The wafer comprises: a first semiconductor layer, an active layer, and a second semiconductor layer which are stacked; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer; a seed layer which is disposed on a side of the second semiconductor layer away from the active layer; a first metal bonding layer which is disposed on a surface of the seed layer away from the second semiconductor layer; The material of the seed layer comprises a conductive dielectric material, and the crystal phase of the material of the seed layer is the same as that of the material of the first metal bonding layer. The wafer according to claim 1, wherein The material of the first metal bonding layer comprises a first metal element, the material of the seed layer comprises a second metal element, the material of the first metal bonding layer does not comprise the second metal element, and the material of the seed layer does not comprise the first metal element. The wafer according to claim 1 or 2, characterized in that The wafer further comprises a barrier layer; the barrier layer is disposed on a side of the seed layer away from the first metal bonding layer; and the material of the barrier layer comprises a conductive dielectric material. The wafer according to claim 3, wherein The material of the barrier layer comprises a third metal element, the material of the seed layer comprises a second metal element, the material of the barrier layer does not comprise the second metal element, and the material of the seed layer does not comprise the third metal element. Wafer according to claim 3 or 4, characterized in that The wafer comprises a plurality of layers of the barrier layer which are stacked; the materials of at least two layers of the barrier layer are different. The wafer according to any one of claims 1 to 5, wherein The wafer further comprises, in sequence, a transparent conductive layer, an adhesion layer, and a metal reflective layer which are disposed on a side of the second semiconductor layer toward the seed layer; and the material of the adhesion layer comprises a conductive dielectric material. The wafer according to claim 6, wherein The resistivity of the material of the adhesion layer is less than 70 mu omega cm, or the extinction coefficient of the adhesion layer for a visible light band is less than 3.

0. Wafer according to any one of claims 1 to 7, characterized in that The wafer further comprises a metal reflective layer which is disposed on a side of the second semiconductor layer toward the seed layer, and the reflectivity of the metal reflective layer for a visible light band is greater than 70%. Wafer according to any one of claims 1 to 8, characterized in that The thickness of the seed layer is 10 nm-50 nm. The wafer according to any one of claims 3-9, wherein The thickness of the barrier layer is 10 nm-50 nm. Wafer according to any one of claims 7-10, characterized in that The thickness of the metal reflective layer is 10 nm-500 nm. A wafer, characterized by The wafer comprises: a first semiconductor layer, an active layer, and a second semiconductor layer which are stacked; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer; a metal reflective layer, a barrier layer, and a first metal bonding layer which are disposed in sequence on a side of the second semiconductor layer away from the active layer; and the material of the barrier layer comprises a conductive dielectric material. The wafer according to claim 12, wherein The reflectivity of the metal reflective layer for a visible light band is greater than 70%. The wafer according to claim 12 or 13, characterized in that The wafer further comprises, in sequence, an adhesion layer and a transparent conductive layer which are disposed on a side of the metal reflective layer away from the second semiconductor layer; and the material of the adhesion layer comprises a conductive dielectric material. A wafer, characterized by The wafer comprises: a first semiconductor layer, an active layer, and a second semiconductor layer which are stacked; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer; A metal reflecting layer, an adhesion layer and a transparent conductive layer are sequentially arranged on the side of the second semiconductor layer away from the active layer; the material of the adhesion layer comprises a conductive dielectric material, the material resistivity of the adhesion layer is less than 70 μΩ·cm, and the extinction coefficient of the adhesion layer in the visible light band is less than 3.

0. The wafer according to claim 15, wherein The reflectivity of the metal reflecting layer to the visible light band is greater than 70%. A wafer stack, characterized in that A wafer and a driving substrate, the wafer comprising the wafer of any one of claims 1-16; the metal bonding layer is bonded to the driving substrate. A light emitting device characterized by comprising: The wafer stack of claim 17 is pixelated. A terminal, characterized by comprising: A light emitting device and a housing, the light emitting device being arranged in the housing, the light emitting device comprising the light emitting device of claim 18. A method of manufacturing a wafer, characterized by, The preparation method of the wafer comprises: A first semiconductor layer, an active layer and a second semiconductor layer are sequentially formed; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer; A seed layer is formed on the side of the second semiconductor layer away from the active layer; A metal bonding layer is formed on the surface of the seed layer away from the second semiconductor layer; The material of the seed layer comprises a conductive dielectric material, and the crystal phase of the material of the seed layer is the same as that of the material of the metal bonding layer. The production method according to claim 20, wherein Before forming the seed layer, the preparation method further comprises: A barrier layer is formed on the side of the second semiconductor layer away from the active layer, and the material of the barrier layer comprises a conductive dielectric material. The production method according to claim 20 or 21, characterized in that Before forming the seed layer, the preparation method further comprises: A transparent conductive layer, an adhesion layer and a metal reflecting layer are sequentially formed on the side of the second semiconductor layer away from the active layer; the material resistivity of the adhesion layer is less than 70 μΩ·cm, and the extinction coefficient of the adhesion layer in the visible light band is less than 3.

0. The production method according to claim 22, wherein The reflectivity of the metal reflecting layer to the visible light band is greater than 70%.

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