Method for processing an analogue signal and associated system

Abstract

The invention relates to a method for processing an analogue signal comprising: - detecting the analogue signal, this detection comprising generating a first time reference signal, in particular a reference pulse, if an amplitude of the analogue signal exceeds a predefined threshold; - generating a series of time windows over a plurality of channels (V1, V2, V3, V4) on the basis of the first time reference signal, the time windows of the series of time windows being successive and / or having different durations; - generating signal waveforms on each of the channels (V1, V2, V3, V4) by multiplying each of these time windows by the analogue signal as such or converted into a baseband signal; and - a step of generating parallel output signals.

Description

[0001] Description

[0002] Title: Analog signal processing method and associated system.

[0003] technical field

[0004] The present invention relates to the encoding of an analog signal, for example electrical, in series into parallel output signals.

[0005] An analog signal is understood to be an analog signal of an electrical nature.

[0006] Previous technique

[0007] Currently, such encoding is implemented conventionally by sampling the analog signal using a clock. This requires that a clock signal be active when the analog signal has a non-zero amplitude and that this clock signal be synchronized with the signal's characteristics.

[0008] This results in processing latency and energy consumption at rest (i.e., when there is no signal), which is detrimental to performance.

[0009] Description of the invention

[0010] To overcome this drawback, the invention relates to a method for processing an analog signal (electrical, for example, a voltage or a current) (for example, representative of a voltage (electrical) or an intensity (electrical)) (in other words: a serial electrical signal) comprising an encoding step (in other words: a conversion step) (asynchronous) (for example, continuous-time) of the analog signal into parallel output signals, the (asynchronous) encoding step comprising the following steps:

[0011] - A detection (for example in continuous time) of the analog (non-zero) signal, this detection including the generation of a first time reference signal, in particular, a reference pulse, notably through (in other words: generated by) a first artificial impulse neuron, provided that an amplitude of the analog signal exceeds a predefined threshold, (then)

[0012] - A generation of a series of time windows (electrical), on several channels (in other words: lines) (electrical), from the first time reference signal (for example, by dilation or extension (temporal) of the first reference signal or of the reference pulse and in particular convolution), the time windows of the series of time windows being for example successive (and / or time-shifted between them) and / or of different durations;

[0013] - A generation of signal shapes (in other words, or for example: waveforms) (electrical), on each of the channels, by multiplying each of these time windows by the analog signal as is or converted into a baseband signal; and (in other words: then),

[0014] - A step of generating parallel output signals (in other words: a conversion step) (asynchronous) from the signal shapes.

[0015] Thus, thanks to the invention:

[0016] - Encoding is implemented asynchronously,

[0017] - The electronic components are inactive when the analog signal is absent.

[0018] - and in particular, detection and / or encoding can be done continuously. Thus, no period of reception of the analog signal would escape the processing method (in other words: the encoding stage).

[0019] This results in analog signal processing with high energy efficiency and reduced latency.

[0020] According to one variant, during the detection stage, the first reference signal, which is for example, but not limited to, a reference pulse, can be generated by a circuit consisting of logic gates and delay components (such as capacitors). According to one embodiment, the generation stage (in other words, the training stage) of the parallel output signals includes a quantization (in other words: a transformation) of each of these signal forms to form the parallel output signals (on each of the channels).

[0021] In general, the quantization of a signal is known to the person skilled in the art, and there are many ways to implement such quantization.

[0022] Alternatively, the parallel output signals are the signal shapes, particularly (but not exclusively) in cases where detection includes, prior to the generation of the first time reference signal, a step of converting the analog signal into a baseband signal. The step of generating the parallel output signals is, in this case, the step of generating the signal shapes. According to one embodiment, quantization includes a conversion:

[0023] - A voltage representative of the average or instantaneous energy of each of these signal forms (in other words: a conversion of each of these signal forms) into a physical quantity of the analog signal, or

[0024] - Of a current representative of the average or instantaneous energy of each of these signal forms (in other words: a conversion, of each of these signal forms,) into a physical quantity of the analog signal.

[0025] For example, the instantaneous energy of each of these signal forms can be obtained by a nonlinear circuit (for example, by a circuit that raises each of these signal forms to the square).

[0026] For example, the average energy of each of these signal forms can be obtained by a low-pass smoothing circuit.

[0027] According to one embodiment, quantization includes a conversion of the voltage or current representing the average or instantaneous energy of each of these signal forms (in other words: a conversion of each of these signal forms) into output pulses by a second artificial pulsed neuron, for example called a "Leaky Integrate-and-Fire neuron".

[0028] Such a conversion is familiar to those skilled in the art. For example, see the article:

[0029] - Melpomeni Dimopoulou, Marc Antonini. Signal Quantization using a Leaky Integrate-and-Fire neuron GRETSI 2017, Sep 2017, Juan-Les-Pins, France.

[0030] For example, the first artificial impulse neuron and / or the second artificial impulse neuron (and / or the third artificial impulse neuron below) can be, for example, of the type called, in English, "Leaky Integrate-and-Fire neuron".

[0031] For example, the first artificial impulse neuron and / or the second artificial impulse neuron (and / or the third artificial impulse neuron below) may include transistors (e.g., Metal-Oxide-Silicon) operating below the conduction threshold. Thus, the energy consumed during the process will be a few picowatts.

[0032] According to one embodiment, the process includes a step of stimulating a neural network with output pulses.

[0033] In this case, the second impulse neuron can be part of the input layer of the impulse neural network. The neural network is, for example, capable of controlling the emission of an alarm signal, for example via a radio frequency transmitter.

[0034] Alternatively, the process includes a step of converting the output pulses into a binary format, for example, by an asynchronous pulse counter (known to a person skilled in the art).

[0035] Alternatively, depending on the application, quantization includes a conversion of the voltage or current representing the average or instantaneous energy into (in other words: a conversion, of each of these signal forms):

[0036] - A voltage across the terminals of a capacitor, or

[0037] - A high or low state of static RAM or a D flip-flop, or

[0038] - A result of an asynchronous analog-to-digital conversion, or

[0039] - A number of pulses, or a pulse frequency.

[0040] In one embodiment, the detection process includes, for example, prior to the generation of the first time reference signal, a step of converting the analog signal into a baseband signal using a method known to those skilled in the art (for example, using a low-noise amplifier and an envelope detector). In this case, the windows of the time window series are multiplied by the resulting baseband signal during the signal waveform generation step. The signal waveforms are then straight lines.

[0041] Thus, the shapes of signals can be curves or straight lines.

[0042] According to one embodiment, the analog signal comes from a sensor of a physical quantity (for example: a temperature or a pressure) or from a radio frequency receiver.

[0043] For example, the radio frequency receiver includes a receiving antenna for a radio frequency signal constituting the analog signal, a low noise amplifier and an envelope detector, and is capable of converting the radio frequency signal into the baseband signal (all-none modulated or according to another modulation).

[0044] A reference pulse is understood, for example, to be a signal with a non-zero amplitude and a duration between 1 picosecond and 100 milliseconds.

[0045] A time window is defined as a signal (electrical), preferably (for example, a voltage or a current) with a non-zero amplitude (or one greater than a threshold) throughout a continuous period. The time window ends when the period ends (for example, when the amplitude becomes zero).

[0046] According to one embodiment, the first impulse neuron includes a refractory period (of a duration greater than or equal to that of the analog signal, i.e.: at the input of the system).

[0047] More generally, the generation of a first time reference signal is followed by an inhibition of a new generation of first reference signal (for a duration greater than or equal to that of the analog signal).

[0048] For example, during the generation of the series of time windows, the reference pulse can be dilated by a low-pass frequency filter, and the dilated reference pulse can inhibit (by counter-feedback) the first artificial neuron for the duration of the dilated reference pulse (for example, by pumping the charging current from the membrane capacitance of the first neuron, preventing it from generating a pulse during the period in which the first pulsed neuron receives the dilated reference pulse).

[0049] Alternatively, whether the generation of a first time reference signal is implemented by the first neuron or another component, a time counter triggered by the reference pulse or more generally the first time reference signal can be used: the principle then consists of prohibiting the consideration of signals until the counting is completed.

[0050] According to one embodiment, during the generation of the series of time windows, each time window of the series of time windows is obtained by time dilation (in other words: by time extension) (in other words, by convolution) of a third time reference signal (which can be a reference pulse) implemented by a frequency-pass switching filter among N frequency-pass switching filters, N being an integer greater than or equal to 1.

[0051] Thus, the generation of each time window in the series of time windows can be implemented by N switching low-pass frequency filters.

[0052] For example, N is equal to the number of windows in the series of time windows.

[0053] The third reference signal can be the first reference signal above or the second reference signal below. Alternatively, each time window can be obtained by another method: using a logic circuit triggered by the reference pulse, whose output is held high (1) for a duration determined by a time counter. Once the countdown is reached, the output of the logic circuit goes low (0): thus, this logic circuit provides at its output the time window resulting from the time dilation of the reference pulse.

[0054] In other words, the third reference signal being a non-zero signal (of amplitude or intensity) between a time t0 and a time t1, each time window, said to be a signal (for example, a voltage or a current) of non-zero amplitude (for example, of constant or decreasing amplitude) throughout the period extending from time t0 to time t2, time t1 being between time t0 and time t2. The period can be of the same or different duration for each of the time windows in the series of time windows.

[0055] According to one embodiment, the time separating time t2 from time t0 can be between 10 picoseconds and 10 seconds.

[0056] For example :

[0057] - the generation of time windows is carried out in continuous time and / or;

[0058] - the analog signal as such or the baseband signal is duplicated (on said multiple channels) into as many replicas as the number of time windows generated for the purpose of multiplying each replica by a time window to obtain the signal shapes.

[0059] For example, the time windows (in other words: the amplitude of the time windows) have a rectangular shape, or alternatively a shape of a decreasing exponential function or some other shape.

[0060] According to one embodiment, where the time windows of the series of time windows are successive (and / or temporally offset from each other) (and for example of identical durations), the generation of the series of time windows comprises:

[0061] - Upon detection that a first time window is ending (in other words; that its amplitude decreases below a predefined threshold or more generally, decreases), generation of a second reference time signal, in particular a reference pulse, notably by means of a third artificial impulse neuron, then - Generation of a second time window (following the first time window in the series of time windows) (for example, by time dilation (in other words: by time extension) (by convolution)) from the second reference signal.

[0062] Of course, in this case; the first time window of the series is generated (directly) from the reference signal.

[0063] In a variant detailed later, still in the case where the time windows are successive (and "possibly of identical duration"), the time windows can be generated by frequency low-pass filters in series.

[0064] Alternatively, since the time windows in the time window series are of different durations, each time window in the time window series starts at the same instant and with an equal duration k * p (i.e., k times p), where p is an identical time step for each time window in the time window series and k is a different integer for each time window in the time window series, between 1 and an integer F, if the time window series includes F windows.

[0065] This embodiment can be implemented by filtering and amplification (in other words: convolution) as described previously, using capacities configured to obtain time windows of different durations (by the N sequential filters).

[0066] Of course, other temporal arrangements of the series of time windows are possible, particularly in the case where the time windows of the series of time windows are of different durations.

[0067] The invention also relates to an asynchronous coding system configured to implement the steps of the process according to the invention (in particular according to the process claims), in particular the encoding step.

[0068] The invention also relates to an asynchronous encoding (or conversion) system for an analog (electrical) signal (for example, representing a voltage (electrical) or current (electrical) (in other words: a serial electrical signal) (input to the encoding system) into parallel output signals (in particular, for implementing the method according to the invention), comprising:

[0069] - A detector (in continuous time) of a non-zero analog signal generating a first time reference signal, provided that an amplitude of the analog signal exceeds a predefined threshold; - A generator of a series of time windows, on several channels (i.e., lines) (electrical), from the first time reference signal (for example, by (temporal) expansion or dilation of the first reference signal or the reference pulse, and in particular convolution), the time windows of the series of time windows being, for example, successive (and / or time-shifted from each other) and / or of different durations

[0070] - A signal shape generator (in other words, or for example: waveform generator) (electrical), on each of the channels, by multiplying each of these time windows by the analog signal as is or converted into a baseband signal; and

[0071] - A generator of parallel output signals (in other words: a conversion step) (asynchronous) from the signal shapes.

[0072] According to one embodiment, the parallel output signal generator includes a quantizer of these signal shapes capable of quantifying the signal shapes to generate the parallel output signals (on each of the channels) from the signal shapes.

[0073] According to one embodiment, the detector includes a threshold-triggered pulse generator configured to generate a reference pulse (in other words: the reference pulse, or more generally the first reference signal) when the amplitude of the analog signal exceeds a predefined threshold.

[0074] According to one embodiment, the pulse generator is a first artificial pulse neuron, in particular of the "Leaky Integrate and Fire" type and / or comprising MOS transistors operating below the conduction threshold.

[0075] For example, the first impulse neuron includes a refractory period of a duration greater than that of the analog signal (i.e., at the input of the system).

[0076] In one embodiment, the generator of the time window series comprises N switching low-pass frequency filters (for example, made of transistors operating below the conduction threshold), N being an integer greater than or equal to 1, for example, capable of temporally dilating the first time reference signal (by convolution) and thus generating each time window of the time window series (during the time window series generation step). In another embodiment of the method and system according to the invention, the N low-pass frequency filters comprise:

[0077] - A control transistor,

[0078] - A capacitor associated with the control transistor,

[0079] - A leaky transistor, and

[0080] -At least two inverters.

[0081] According to one embodiment, of course, of the process and system according to the invention, the N low-pass frequency filters comprise:

[0082] - The control transistor, for example of the so-called MOS type, configured as a switch and controlled by the first reference signal, the drain of this transistor being preferentially connected to a supply voltage;

[0083] - The capacitor associated with the control transistor, connected in series with it at a midpoint and having one terminal connected to a supply voltage;

[0084] - The leakage transistor, mounted in parallel with the capacitor associated with the control transistor, so as to allow the latter to discharge through the leakage transistor, the gate of the leakage transistor being controlled by an adjustable voltage in order to control the discharge current of said capacitor, the source of the leakage transistor being connected to the supply voltage, and

[0085] - An input of a first inverter among said at least two inverters being connected to the midpoint.

[0086] For example, the control transistor being of the so-called NMOS type, its gate being connected to the reference signal.

[0087] For example, the capacity has the same value for N filters.

[0088] Alternatively, for example, the control transistor, for example of the so-called PMOS type, has its gate connected to the complementary signal of the reference signal, this complementary signal coming in particular from the output of a logic inverter having the reference signal as its input, the N low-pass frequency filters each having in addition a second transistor, for example of the so-called NMOS type, mounted in series with the leakage transistor, the source of the second transistor, for example of the so-called NMOS type, being connected to the midpoint, its drain being connected to the drain of the leakage transistor and its gate being connected to the output of the first inverter.According to one embodiment, N being greater than 1, the time window series comprises N (successive) time windows, the N frequency low-pass filters being connected in cascade for the (or a) (successive) generation of the N time windows, each frequency low-pass filter of rank i of the N frequency low-pass filters, 1 < i < Nl, being connected to the filter of rank i+1 via two connecting inverters and a delay capacitor.

[0089] For example, the first connecting inverter (of the two connecting inverters) has as its input the output of the rank i filter and as its output the drain of the control transistor (for example the aforementioned control transistor) of the rank i+1 filter, the second connecting inverter (of the two connecting inverters) has as its input the output of one of the two at least inverting inverters (for example, the first aforementioned inverter) of the rank i filter and as its output the gate of the control transistor of the rank i+1 filter, the delay capacitor being connected between the gate of the control transistor of the rank i+1 filter and the supply voltage.

[0090] It is worth recalling that a D flip-flop is a flip-flop comprising;

[0091] - A single data entry, denoted entry D,

[0092] - A clock input receiving a clock signal,

[0093] - One output, denoted Q, and a complementary output of Q.

[0094] In such a D flip-flop, at each clock edge of the clock signal on the clock input, data received at input D is copied to output Q, and the complement of this data is copied to the complementary output of Q.

[0095] According to one embodiment, the N frequency-pass low-pass filters consist of a single frequency-pass low-pass filter, N being equal to 1, the series of time windows comprising M time windows, M being an integer strictly greater than 1, the system further comprising:

[0096] - A connecting transistor (for example, of the so-called "MOS" type),

[0097] - A capacity for delay,

[0098] - Two connection inverters,

[0099] - A log2(M) to M demultiplexer, receiving as input the output signals from a log2(M) bit counter and generating as output the M time windows; and

[0100] - The log2(M) bit counter has log2(M) D flip-flops connected together, the Q outputs of these D flip-flops corresponding to the output signals of the counter, the clock signal of a first D flip-flop among the log2(M) D flip-flops receiving the output signal of the single low-pass frequency filter, the clock signal of a flip-flop of rank j, 1 < j < log2(M)-1, corresponding to the output of the flip-flop of rank j-1, the complementary output of Q of each flip-flop looping back to the D input of that same flip-flop.

[0101] For example, a first connecting inverter, among the two connecting inverters, has as its input the output of the single low-pass frequency filter and as its output the drain or source of the connecting transistor, and the second connecting inverter, among the two connecting inverters, has as its input the output of the first inverter (for example the first inverter mentioned above) of the filter and as its output the gate of the connecting transistor, the third terminal of the latter being connected to the midpoint of the filter, the delay capacitor being connected between the gate of the connecting transistor and the supply voltage.

[0102] According to one embodiment, the signal shape generator includes at least one multiplier for multiplying the analog signal as is or after its baseband conversion by each window of the time window series.

[0103] For example, the multiplier is configured to perform linear multiplication, the multiplier being, for example, a Gilbert cell.

[0104] Alternatively, the multiplier is a transistor.

[0105] Alternatively, the signal shape generator includes at least one D flip-flop, capable of implementing multiplication, receiving the baseband signal at its data input and having as its clock signal a time window from the series of time windows.

[0106] For example, the time window is chosen so that the falling edge of the time window occurs between the beginning and the end of the duration of the bit to be extracted, preferably in the middle of the duration of the bit to be extracted.

[0107] The features and advantages of the method and system are identical to those of the method according to the invention; therefore, when a feature has been introduced for one category of object (e.g., the method), the invention also relates to the other category of object (e.g., the system) mutatis mutandis, without it being necessary to explicitly introduce this feature for the other category of object in this description. When the encoding system, the (continuous-time) analog signal detector, the time-window series generator, the signal shape generators, the quantizer, or the N frequency-low-pass filters, or any other element, is "configured to" or "intended to" (or "suitable to" or "is configured to") perform or implement a step or operation, this implies, for example, that the element includes means for performing the step or operation.The means preferably include electronic means, for example a computer program, data in memory, specialized electronic circuits, wired or wireless connections, a microprocessor and / or a microcontroller.

[0108] Brief description of the drawings

[0109] Other features and advantages of the present invention will become more apparent upon reading the following detailed description, which includes embodiments of the invention given by way of non-limiting examples and illustrated by the accompanying drawings, in which:

[0110] [Fig. 1] represents an encoding system according to the invention.

[0111] [Fig. 2] represents, during the implementation of the process of figure 7, electrical signals at the input and output of the encoding system of figure 1, as well as signals internal to the encoding system of figure 1.

[0112] [Fig. 3] represents a variant of a series of time windows.

[0113] [Fig. 4] represents an electrical diagram of a low-frequency filter of the generator of the series of time windows included in the encoding system of Figure 1.

[0114] [Fig. 5] represents an electrical diagram of two successive low-frequency filters of the generator of the series of time windows included in the encoding system of Figure 1.

[0115] [Fig. 6] represents a variant of the generator of the series of time windows included in the encoding system of Figure 1.

[0116] [Fig. 7] represents an implementation of the process according to the invention, according to an example of an embodiment, by encoding system of figure 1.

[0117] Detailed description Figure 1 represents a SYS 100 encoding system comprising, connected in series:

[0118] - A DETEC100 continuous-time analog signal detector,

[0119] - A WIN100 generator for a series of time windows,

[0120] - a waveform generator Ml 00,

[0121] - An INPI entry 00,

[0122] - VI, V2, V3 and V4 channels extending from the output of the SYS100 encoding system.

[0123] To facilitate reading the figures, the SYS100 encoding system is represented as comprising 4 electrical channels, but of course, this number of channels can be any number.

[0124] With reference to Figure 7 and Figure 2, at step S 10, the DETEC100 detector generates the REF1 pulse, at the moment when the amplitude of the analog signal SigAnalOO, at the INPI 00 input, exceeds the SI threshold.

[0125] For example, the analog signal SigAnalOO comes from a sensor of a physical quantity (for example: a temperature or a pressure) or from a radio frequency receiver.

[0126] At step S20, the WIN100 generator then generates the successive Winl, Win2, Win3, and Win4 windows on channels VI, V2, V3, V4 from the REF1 pulse.

[0127] At step S30, the M100 generator produces, on each of the channels VI, V2, V3, and V4, the signal shapes Ondl, Ond2, Ond3, and Ond4, by multiplying each of these time windows Winl, Win2, Win3, and Win4 by the analog signal SigAnalOO. These signal shapes then constitute parallel output signals of the SYS 100 encoding system.

[0128] At step S50, the signal shapes Ondl, Ond2, Ond3 and Ond4 are then processed by the TRAIT100 processing device which receives the signal shapes Ondl, Ond2, Ond3 and Ond4 as input.

[0129] According to the invention, in general, many variants of function (or application) and architectures are conceivable for such a TRAIT 100 processing device.

[0130] As a general example, the TRAIT100 processing device is an artificial neural network, for example the parallel output signals of the SYS 100 encoding system being inputs to the artificial neural network.

[0131] For example, a neural network can be used to control the transmission of an alarm signal, for instance, via a radio frequency transmitter. In one embodiment, the SYS 100 encoding system includes a low-noise amplifier and an envelope detector, and step S10 is preceded by step S00 during which the analog signal SigAnalOO is converted into a baseband signal, in a manner known to those skilled in the art, by the low-noise amplifier and the envelope detector. In this case, at step S30, the generator M100 generates, on each of channels VI, V2, V3, and V4, signal shapes in the form of a baseband signal, by multiplying each of these time windows Win1, Win2, Win3, and Win4 by this baseband signal. These signal shapes then constitute parallel output signals of the SYS 100 encoding system.The processing circuit can then be, for example, a specific logic circuit (for example an asynchronous counter), or an artificial neural network.

[0132] For example, at step S10, the REF1 pulse is generated by an artificial pulse neuron, for example of the so-called "Leaky Integrate-and-Fire neuron" type which operates below the conduction threshold.

[0133] According to one embodiment, the impulse neuron includes a refractory period, of a duration greater than or equal to that of the analog signal SigAnalOO. For example, during the generation of the time windows, the REF1 impulse can be dilated by a low-pass frequency filter (similar to the low-pass frequency filter), and the reference impulse thus dilated can inhibit this artificial impulse neuron for the duration of the dilated reference impulse (for example, by pumping the charging current from the membrane capacitance of the neuron, preventing it from generating an impulse during the period during which the first impulse neuron receives the dilated reference impulse).

[0134] According to one embodiment, the signal shapes Ondl, Ond2, Ond3 and Ond4 can be quantified at step S40, by a quantifier (not shown) prior to their reception by the TRAIT100 processing device.

[0135] This quantization process may involve passing each of the signal shapes Ondl, Ond2, Ond3, and Ond4 through a low-pass frequency filter and / or a nonlinear circuit (for example, by squaring each of these signal shapes), and then through an artificial impulse neuron, for example, a Leaky Integrate-and-Fire neuron operating below the conduction threshold, to convert each of the signal shapes Ondl, Ond2, Ond3, and Ond4 into output pulses. This neuron may be part of an input layer of the TRAIT 100 processing device's artificial neural network, for example, an impulse neural network.

[0136] Such a conversion is familiar to those skilled in the art. For example, see the article:

[0137] - Melpomeni Dimopoulou, Marc Antonini. Signal Quantization using a Leaky Integrate-and-Fire neuron GRETSI 2017, Sep 2017, Juan-Les-Pins, France.

[0138] For example, in step S20, the WIN100 generator generates the time windows Win1, Win2, Win3 and Win4, by dilating a time reference signal, using 4 switching low-pass frequency filters (not shown).

[0139] The REF1 pulse can be used directly to generate the time windows in Figure 3, all starting at the same instant, and having a duration equal to k * pl (that is, k times p), pl being an identical time step for each time window, and k being a different integer for each time window, Win1, Win2, Win3 and Win4 between 1 and 4 (In Figures 2 and 3, "t" represents the time axis, of course).

[0140] This embodiment can be implemented by 4 low-pass frequency filters, an example of which is given below, with reference to Figure 4, these 4 low-pass frequency filters having capacities (Cl) configured to obtain time windows of duration equal to k * pl.

[0141] In another embodiment:

[0142] - Upon detection that a first time window, among the time windows Win1, Win2, Win3 and Win4, is ending (in other words; that its amplitude decreases below a predefined threshold or more generally, decreases), the WIN100 generator can generate another reference time signal, for example another pulse, notably via another artificial pulse neuron (for example, of the so-called "Leaky Integrate-and-Fire" type), then

[0143] - the WIN100 generator can generate a second time window from among the time windows Win1, Win2, Win3 and Win4 (following the first time window) from the other pulse, always using one of the 4 low-pass frequency filters, an example of which is given below, with reference to figure 4.

[0144] In this case, the four frequency-domain low-pass filters have capacitances Cl configured to obtain time windows of equal duration, for example. In a variant detailed later, with reference to Figure 5, and again assuming that the time windows Winl, Win2, Win3, and Win4 are successive and of identical duration, the time windows Winl, Win2, Win3, and Win4 can be generated by sequential low-pass filters in series.

[0145] We now refer to Figure 4 to describe in more detail each of the 4 low-pass frequency filters, which therefore include:

[0146] - A NI control transistor, for example of the so-called MOS type, configured as a switch and controlled by the first reference signal REF1 at input In 100, the drain of this transistor being preferentially connected to a supply voltage VDD;

[0147] - A capacitor Cl associated with the control transistor NI, connected in series with it at a midpoint and having one terminal connected to a supply voltage VCC;

[0148] - The leakage transistor N2, for example of the so-called NMOS type, is connected in parallel with the capacitor Cl associated with the control transistor Cl, so as to allow the latter to discharge through the leakage transistor N2. The gate of the leakage transistor N2 is controlled by an adjustable voltage to control the discharge current of the capacitor Cl, and the source of the leakage transistor N2 is connected to the supply voltage VCC; and

[0149] - The two inverters INV1, INV2 in series, the input of a first inverter INV1 being connected to the midpoint.

[0150] Alternatively, for example, the control transistor, for example of the so-called PMOS type, has its gate connected to the complementary signal of the reference signal, this complementary signal coming in particular from the output of a logic inverter having as input the reference signal REF1, the N low-pass frequency filters each having in addition a second transistor, for example of the so-called NMOS type, mounted in series with the leakage transistor, the source of the second transistor, for example of the so-called NMOS type, being connected to the midpoint, its drain being connected to the drain of the leakage transistor and its gate being connected to the output of the first inverter.

[0151] According to one embodiment, with reference to Figure 5, 4 frequency low-pass filters, identical to that described with reference to Figure 4, are connected in cascade for the successive generation of the 4 time windows Win1, Win2, Win3 and Win4, each frequency low-pass filter of rank i Fli of the 4 frequency low-pass filters, 1 < i < 3, being connected to the filter of rank i+1 Fli via two connecting inverters and a delay capacitor CRI'.

[0152] For example, the INV1C connection inverter has as its input the output of the i-rank filter Fli and as its output the drain of the Nli+1 control transistor of the i+1-rank filter Fli+1, the second INV2C connection inverter has as its input the output of an inverter, identical to the aforementioned INV1 inverter in Figure 4, of the i-rank filter Fli and as its output the gate of the Nli+1 control transistor of the i+1-rank filter Fli+1, the CRI delay capacitor being connected, between the gate of the Nli+1 control transistor of the i+1-rank filter Fli+1, and the supply voltage VS S.

[0153] According to one variant, as shown in Figure 6, a single low-pass frequency filter Fl is used to generate the four time windows Win1, Win2, Win3, and Win4. The WIN100 generator then comprises:

[0154] - A connecting transistor (for example, of the so-called "MOS" type) NIC',

[0155] - A CRU delay capability,

[0156] - Two INVIC' and INV2C' connection inverters,

[0157] - A DEMUX1 2-to-4 demultiplexer, receiving as input the output signals from a 2-bit counter and generating as output the time windows Win1, Win2, Win3, and Win4 on channels VI, V2, V3, and V4; and

[0158] - The 2-bit counter has 2 flip-flops D, B0 and Bl, connected together, the Q outputs of these D flip-flops corresponding to the output signals of the counter, the clock signal of the B0 flip-flop receiving the output signal of the single low-pass frequency filter Fl, the clock signal of the Bl flip-flop, corresponding to the Q output of the B1 flip-flop, the complementary Q output of each flip-flop looping back to the D input of that same flip-flop.

[0159] For example, the first connecting inverter INV1C' has as its input the output of the single low-pass frequency filter Fl, and as its output the drain or source of the connecting transistor NIC', and the second connecting inverter INV2C' has as its input the output of an inverter of the single low-pass frequency filter Fl, identical to the aforementioned inverter INV1 in Figure 4, and as its output the gate of the connecting transistor NIC', the third terminal of the latter being connected to the midpoint of the filter, the delay capacitor CRI' being connected between the gate of the connecting transistor NIC' and the supply voltage VSS. For example, the generator M1 00 comprises 4 multipliers M1, M2, M3 and M4.

[0160] Thus, at step S30, the signal shapes Ondl, Ond2, Ond3 and Ond4 on each of the channels VI, V2, V3, and V4 are generated by a multiplication of the analog signal SigAnalOO by the time windows Winl, Win2, Win3 and Win4 respectively, implemented respectively by the multipliers Ml, M2, M3 and M4

[0161] These signal forms then constitute parallel output signals of the SYS100 encoding system.

[0162] For example, each of the multipliers M1, M2, M3, and M4 is a Gilbert cell or a transistor. Alternatively, the multiplication is implemented by a D flip-flop, capable of receiving, at its data input D, the aforementioned baseband signal and having as its clock signal a time window Win1, Win2, Win3, or Win4. For example, in this case, the time windows Win1, Win2, Win3, and Win4 are chosen so that the falling edge of the time windows Win1, Win2, Win3, and Win4 occurs between the beginning and end of the duration of the bit to be extracted, preferably in the middle of the bit's duration.

Claims

Demands 1. A method for processing an analog signal (SigAnalOO) comprising an asynchronous encoding step of the analog signal (SigAnalOO) into parallel output signals, the asynchronous encoding step comprising: - Continuous time detection of the analog signal (SigAnalOO), this detection including the generation of a first time reference signal (REF1), in particular a reference pulse, provided that an amplitude of the analog signal (SigAnalOO) exceeds a predefined threshold (SI); - A generation of a series of time windows, on several channels (VI, V2, V3, V4), from the first time reference signal (REF1), the time windows (Winl, Win2, Win3, Win4) of the series of time windows being successive and / or of different durations; - A generation of signal shapes (Ondl, Ond2, Ond3, Ond4), on each of the channels (VI, V2, V3, V4), by multiplying each of these time windows (Winl, Win2, Win3, Win4) by the analog signal (SigAnalOO) as is or converted into a baseband signal; and, - A step of generating parallel output signals from the signal shapes (Ondl, Ond2, Ond3, Ond4).

2. A method according to the preceding claim, wherein the step of generating the parallel output signals comprises a quantization of each of these signal forms to form the parallel output signals.

3. Method according to the preceding claim, the quantification comprising a conversion: - A voltage representative of the average or instantaneous energy of each of these signal forms (Ondl, Ond2, Ond3, Ond4) in a physical quantity of the analog signal, or - Of a current representative of the average or instantaneous energy of each of these signal forms (Ondl, Ond2, Ond3, Ond4) in a physical quantity of the analog signal.

4. A method according to the preceding claim, the quantification comprising a conversion of a voltage or current representative of the average or instantaneous energy of each of these signal forms (Ondl, Ond2, Ond3, Ond4), into output pulses, by a second artificial pulse neuron.

5. A method according to any one of the preceding claims in which the analog signal is derived from a sensor of a physical quantity or from a radio frequency receiver.

6. A method according to any one of the preceding claims, wherein, during the generation of the series of time windows, each time window (Win1, Win2, Win3, Win4) of the series of time windows is obtained by time dilation of a third time reference signal implemented by a frequency-pass switching filter among N frequency-pass switching filters, N being an integer greater than or equal to 1.

7. A method according to any one of the preceding claims, wherein, the time windows of the series of time windows being successive, the generation of the series of time windows comprises: - Upon detection that a first time window is ending, a second reference time signal is generated, in particular a reference pulse, notably via a third artificial impulse neuron, then - Generation of a second time window from the second reference signal.

8. A method according to any one of the preceding claims, wherein the time windows of the series of time windows are of different durations, in which each time window of the series of time windows starts at the same instant and at an equal duration of k * p, p being an identical time step for each time window of the series of time windows and k being a different integer for each time window of the series of time windows, between 1 and an integer F, if the series of time windows comprises F windows.

9. Asynchronous encoding system (SYS 100) of an analog signal (SigAnalOO) into parallel output signals, comprising: - A continuous-time detector (DETEC100) of an analog signal (SigAnalOO) generating a first time reference signal (REF1), provided that an amplitude of the analog signal (SigAnalOO) exceeds a predefined threshold (SI); - A generator (WIN100) of a series of time windows, on several channels (VI, V2, V3, V4), from the first time reference signal (REF1), the time windows (Winl, Win2, Win3, Win4) of the series of time windows being successive and / or of different durations; - A signal waveform generator (Ml 00) (Ondl, Ond2, Ond3, Ond4) on each of the channels (VI, V2, V3, V4), by multiplying each of these time windows (Winl, Win2, Win3, Win4) by the analog signal (SigAnalOO) as is or converted into a baseband signal; and - A generator of parallel output signals from the signal shapes (Ondl, Ond2, Ond3, Ond4).

10. System according to the preceding claim in which the parallel output signal generator comprises a quantizer of these signal forms (Ondl, Ond2, Ond3, Ond4) capable of quantifying these signal forms to generate the parallel output signals.

11. System according to claim 9 or 10, the detector (DETEC100) comprising a threshold-triggered pulse generator configured to generate a reference pulse when the amplitude of the analog signal (SigAnalOO) exceeds a predefined threshold (SI).

12. System according to the preceding claim, the pulse generator being a first artificial pulse neuron.

13. System according to the preceding claim in which the first artificial impulse neuron comprises a refractory period of a duration greater than that of the analog signal.

14. System according to any one of claims 9 to 13, the generator (WIN100) of the series of time windows comprising N switching low-pass frequency filters, N being an integer greater than or equal to 1, capable of temporally dilating the first time reference signal (REF1), and thus of generating each time window (Win1, Win2, Win3, Win4) of the series of time windows.

15. System according to the preceding claim in which the N low-pass frequency filters comprise: - A control transistor (NI), - A capacitor (Cl) associated with the control transistor (NI), - A leakage transistor (N2), and -At least two inverters (INV1, INV2).

16. System according to the preceding claim in which the N low-pass frequency filters comprise: - The control transistor (NI) configured as a switch and controlled by the first time reference signal (REF1), the drain of this transistor being preferentially connected to a supply voltage (VDD); - The capacitor (Cl) associated with the control transistor (NI), connected in series with it at a midpoint and having one terminal connected to a supply voltage (VCC); - The leakage transistor (N2), mounted in parallel with the capacitor (Cl) associated with the control transistor (Cl), so as to allow the discharge of the latter through the leakage transistor (N2), the gate of the leakage transistor (N2) being controlled by an adjustable voltage so as to control the discharge current of said capacitor (Cl), the source of the leakage transistor (N2) being connected to the supply voltage (VCC), and - An input of a first inverter (INV1) among said at least two inverters (INV1, INV2) being connected to the midpoint.

17. System according to any one of claims 14 to 16, N being greater than 1, the time window series comprising N time windows (Win1, Win2, Win3, Win4), the N frequency low-pass filters being cascaded for successive generation of the N time windows, each frequency low-pass filter of rank i (F11) of the N frequency low-pass filters, 1 < i < N1, being connected to the filter of rank i+1 (F11+1) via two connection inverters and a delay capacitor (CRU).

18. A system according to any one of claims 14 to 16, the N frequency-low-pass filters consisting of a single frequency-low-pass filter (FUI), N being equal to 1, the time window series comprising M time windows, M being an integer strictly greater than 1, the system further comprising: - A connecting transistor (NIC'), - A delay capacity (CRU), - Two connection inverters, and - A log2(M) bit counter comprising log2(M) D flip-flops (B1, B2) connected together, the Q outputs of these D flip-flops corresponding to the output signals of the counter, the clock signal of a first D flip-flop (BO) among the log2(M) D flip-flops receiving the output signal of the single low-pass frequency filter (FUI), the clock signal of a flip-flop of rank j (B1), 1 < j < log2(M)-1, corresponding to the Q output of a flip-flop of rank j-1, the complementary Q output of each flip-flop looping back to the D input of that same flip-flop. - A log2(M) to M demultiplexer (DEMUX1), receiving as input the output signals from the log2(M) bit counter and generating as output the M time windows.

19. System according to any one of claims 9 to 18, the generator (Ml 00) of signal forms comprising at least one multiplier to multiply the analog signal (SigAnalOO) as is or after its baseband conversion by each window of the time window series.

20. System according to any one of claims 9 to 18, the signal shape generator (Ml 00) comprising at least one D flip-flop, capable of implementing multiplication, receiving at its data input the baseband signal and having as its clock signal a time window (Win1, Win2, Win3, Win4) from the series of time windows.

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