Switching element drive circuit and power conversion device

Abstract

The present invention addresses the problem of suppressing a decrease in the voltage of a capacitor of a bootstrap circuit. A switching element drive circuit (2) comprises an auxiliary circuit (5) which is connected to a plurality of second bootstrap circuits (72). The auxiliary circuit (5) includes: a third switching element (Q3); a fifth gate driver (65); a third capacitor (C3); a first diode (D6); a plurality of second diodes (D7); and a plurality of third diodes (D8). A fifth switching element (Q5) has a first main terminal, a second main terminal and a gate terminal. The first main terminal is connected to an intermediate potential point (M1). The fifth gate driver (65) is connected to the gate terminal and the second main terminal of the fifth switching element (Q5) and drives the fifth switching element (Q5).

Description

Switching element drive circuit and power conversion device

[0001] The present disclosure relates to a switching element drive circuit and a power conversion device, and more particularly to a switching element drive circuit that drives four switching elements of a T-type three-level inverter, and a power conversion device including the switching element drive circuit.

[0002] Patent Document 1 discloses a power conversion device including a DC power supply (DC power supply unit), a plurality of T-type three-level inverters, and a switching element drive circuit. In the power conversion device disclosed in Patent Document 1, the number of control power supplies (DC voltage sources) in the switching element drive circuit can be reduced to one.

[0003] In the power conversion device disclosed in Patent Document 1, a T-type three-level inverter includes a first semiconductor switch (second switching element), a second semiconductor switch (first switching element), a third semiconductor switch (fourth switching element), and a fourth semiconductor switch (third switching element). In the power conversion device disclosed in Patent Document 1, the third semiconductor switch and the fourth semiconductor switch form a bidirectional semiconductor switch. The power conversion device disclosed in Patent Document 1 also includes a first bootstrap circuit including a semiconductor switch capacitor (first capacitor) charged from a control power supply, and a second bootstrap circuit including a bidirectional switch capacitor (second capacitor).

[0004] In the power conversion device disclosed in Patent Document 1, when the load current is positive, the first capacitor of the first bootstrap circuit and the second capacitor of the second bootstrap circuit cannot be charged, and therefore the voltages of the first capacitor and the second capacitor may become too low.

[0005] Japanese Patent Application Laid-Open No. 2020-72540

[0006] An object of the present disclosure is to provide a switching element drive circuit and a power conversion device that can suppress a voltage drop in a capacitor of a bootstrap circuit while keeping the number of DC voltage sources to one.

[0007] A switching element drive circuit according to one aspect of the present disclosure drives a plurality of T-type three-level inverters. The plurality of T-type three-level inverters include a plurality of first switching elements, a plurality of second switching elements, a plurality of third switching elements, and a plurality of fourth switching elements. The plurality of first switching elements are connected to the positive electrode of a DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point. The plurality of second switching elements are connected in series to the plurality of first switching elements and connected to the negative electrode. The plurality of third switching elements are connected to the intermediate potential point. The plurality of fourth switching elements are connected in series to the plurality of third switching elements and connected to output points of corresponding T-type three-level inverters among the plurality of T-type three-level inverters. The switching element drive circuit includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, a plurality of second bootstrap circuits, a DC voltage source, a control device, and an auxiliary circuit. The plurality of first gate drivers respectively drive the plurality of first switching elements. The plurality of second gate drivers respectively drive the plurality of second switching elements. The plurality of third gate drivers respectively drive the plurality of third switching elements. The plurality of fourth gate drivers respectively drive the plurality of fourth switching elements. The plurality of first bootstrap circuits correspond one-to-one to the plurality of first gate drivers. Each of the plurality of first bootstrap circuits includes a first capacitor connected in parallel to the corresponding first gate driver. Each of the plurality of second bootstrap circuits includes a second capacitor connected in parallel to a corresponding third gate driver of the plurality of third gate drivers and a corresponding fourth gate driver of the plurality of fourth gate drivers. The DC voltage source is connected in parallel to the plurality of second gate drivers.The control device outputs a plurality of first control signals, a plurality of second control signals, a plurality of third control signals, and a plurality of fourth control signals to the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers, respectively. The auxiliary circuit is connected to the plurality of second bootstrap circuits. Each of the plurality of first bootstrap circuits further includes a bootstrap diode. The bootstrap diode has a cathode connected to the high potential end of the first capacitor and an anode connected to the high potential end of the second capacitor of a corresponding second bootstrap circuit among the plurality of second bootstrap circuits. The auxiliary circuit includes a fifth switching element, a fifth gate driver, a third capacitor, a first diode, a plurality of second diodes, and a plurality of third diodes. The fifth switching element has a first main terminal, a second main terminal, and a gate terminal, and the first main terminal is connected to the intermediate potential point. The fifth gate driver is connected to the gate terminal and the second main terminal of the fifth switching element to drive the fifth switching element. The third capacitor is connected in parallel to the fifth gate driver. The first diode has a first cathode connected to the high potential end of the third capacitor and a first anode connected to the positive terminal of the DC voltage source. The second diodes have second cathodes connected to the high potential ends of the second capacitors of the second bootstrap circuits, respectively, and second anodes connected to the high potential end of the third capacitor. The third diodes have third cathodes connected to the low potential ends of the second capacitors of the second bootstrap circuits, respectively, and third anodes connected to the low potential ends of the third capacitor.

[0008] A power conversion device according to one aspect of the present disclosure includes the switching element drive circuit according to the above aspect and the plurality of T-type three-level inverters.

[0009] FIG. 1 is a circuit diagram of a power conversion device including a switching element drive circuit according to a first embodiment. FIG. 2 is an explanatory diagram of a current path when an inverter circuit in the power conversion device is in a first switching state. FIG. 3 is an explanatory diagram of a current path when an inverter circuit in the power conversion device is in a second switching state. FIG. 4 is an explanatory diagram of a current path when an inverter circuit in the power conversion device is in a third switching state. FIG. 5 is an explanatory diagram of a current path when an inverter circuit in the power conversion device is in a second switching state. FIG. 6 is an explanatory diagram of a voltage command value for each phase in the power conversion device. FIG. 7 is an explanatory diagram of a group of voltage vectors related to the power conversion device. FIG. 8 is a more detailed explanatory diagram of a group of voltage vectors related to the power conversion device. FIG. 9 is a vector diagram for explaining the operation of a control device in the power conversion device. FIG. 10 is a time chart of the switching states of each phase in the power conversion device. FIG. 11 is a time chart of the on / off states of first to fourth switching elements in the power conversion device. FIG. 12 is a waveform diagram of an output current from the power conversion device. Fig. 13 is an explanatory diagram of the operation of the above power conversion device. Fig. 14 is an explanatory diagram of a charging path when a fifth switching element in an auxiliary circuit of a switching element drive circuit in the above power conversion device is off. Fig. 15 is an explanatory diagram of a charging path when a fifth switching element in an auxiliary circuit of a switching element drive circuit in the above power conversion device is on. Fig. 16 is an explanatory diagram of the operation of the above power conversion device. Fig. 17 is a circuit diagram of a power conversion device including a switching element drive circuit according to a second embodiment. Fig. 18 is a circuit diagram of a power conversion device including a switching element drive circuit according to a third embodiment. Fig. 19 is an explanatory diagram of the operation of the above switching element drive circuit.

[0010] First Embodiment A power conversion device 100 including a switching element drive circuit 2 according to a first embodiment will be described below with reference to FIGS. 1 to 16. FIG.

[0011] (1) Configuration of the Switching Element Drive Circuit and the Power Conversion Device The switching element drive circuit 2 according to the first embodiment is a circuit that drives a plurality of (three in the example of FIG. 1 ) T-type three-level inverters 1 (hereinafter also referred to as inverter circuits 1).

[0012] The multiple T-type three-level inverters 1 include multiple (three in the example of FIG. 1 ) first switching elements Q1, multiple (three in the example of FIG. 1 ) second switching elements Q2, multiple (three in the example of FIG. 1 ) third switching elements Q3, and multiple (three in the example of FIG. 1 ) fourth switching elements Q4. The multiple first switching elements Q1 are connected to a positive electrode P1 of a DC power supply unit 3 having a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The "intermediate potential point M1" is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3. The multiple second switching elements Q2 are connected in series to the multiple first switching elements Q1, respectively, and connected to the negative electrode N1. The multiple third switching elements Q3 are connected to the intermediate potential point M1. The multiple fourth switching elements Q4 are connected in series to the multiple third switching elements Q3, respectively, and connected to an output point 13 of a corresponding T-type three-level inverter 1 among the multiple T-type three-level inverters 1.

[0013] The switching element drive circuit 2 includes a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, a plurality of fourth gate drivers 64, a plurality of first bootstrap circuits 71, a plurality of second bootstrap circuits 72, a DC voltage source 6, a control device 4, and an auxiliary circuit 5.

[0014] The plurality of first gate drivers 61 respectively drive the plurality of first switching elements Q1. The plurality of second gate drivers 62 respectively drive the plurality of second switching elements Q2. The plurality of third gate drivers 63 respectively drive the plurality of third switching elements Q3. The plurality of fourth gate drivers 64 respectively drive the plurality of fourth switching elements Q4.

[0015] The multiple first bootstrap circuits 71 correspond one-to-one to the multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 includes a first capacitor C1 connected in parallel to the corresponding first gate driver 61. Each of the multiple second bootstrap circuits 72 includes a second capacitor C2 connected in parallel to a corresponding third gate driver 63 of the multiple third gate drivers 63 and a corresponding fourth gate driver 64 of the multiple fourth gate drivers 64.

[0016] The DC voltage source 6 is connected in parallel to a plurality of second gate drivers 62 .

[0017] The control device 4 outputs a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3 and a plurality of fourth control signals S4 to be given to a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63 and a plurality of fourth gate drivers 64, respectively.

[0018] The auxiliary circuit 5 is connected to a plurality of second bootstrap circuits 72 .

[0019] Each of the first bootstrap circuits 71 further includes a diode D11 (bootstrap diode). The cathode of the diode D11 is connected to the high potential end of the first capacitor C1, and the anode of the diode D11 is connected to the high potential end of the second capacitor C2 of a corresponding one of the second bootstrap circuits 72.

[0020] The auxiliary circuit 5 includes a fifth switching element Q5, a fifth gate driver 65, a third capacitor C3, a first diode D6, multiple second diodes D7, and multiple third diodes D8. The fifth switching element Q5 has a first main terminal, a second main terminal, and a gate terminal, with the first main terminal connected to the intermediate potential point M1. The fifth gate driver 65 is connected to the gate terminal and the second main terminal of the fifth switching element Q5 and drives the fifth switching element Q5. The third capacitor C3 is connected in parallel to the fifth gate driver 65. "The third capacitor C3 is connected in parallel to the fifth gate driver 65" means that the third capacitor C3 is connected between two power supply terminals (high-potential output terminal and low-potential output terminal) of the fifth gate driver 65. The first diode D6 has a first cathode connected to the high-potential end of the third capacitor C3 and a first anode connected to the positive terminal of the DC voltage source 6. The second diodes D7 have their second cathodes connected to the high potential ends of the second capacitors C2 of the second bootstrap circuits 72, and their second anodes connected to the high potential ends of the third capacitors C3. The third diodes D8 have their third cathodes connected to the low potential ends of the second capacitors C2 of the second bootstrap circuits 72, and their third anodes connected to the low potential ends of the third capacitors C3. The first capacitor C1, the second capacitor C2, and the third capacitor C3 each function as a bootstrap capacitor. The auxiliary circuit 5 includes a third bootstrap circuit 73 including the third capacitor C3 and a first diode D6.

[0021] The power conversion device 100 according to the first embodiment includes a switching element drive circuit 2 and a plurality of (three in FIG. 1 ) T-type three-level inverters 1 .

[0022] (2) Details of the Switching Element Drive Circuit and the Power Conversion Device As shown in Fig. 1 , the power conversion device 100 includes, for example, a DC power supply unit 3, a plurality of (three in the example of Fig. 1 ) inverter circuits 1, and a switching element drive circuit 2. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3.

[0023] The DC power supply unit 3 includes a fourth capacitor C31 and a fifth capacitor C32. Each of the fourth capacitor C31 and the fifth capacitor C32 functions as a smoothing capacitor. In the DC power supply unit 3, the fourth capacitor C31 and the fifth capacitor C32 are connected in series. The DC power supply unit 3 further includes a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. In the DC power supply unit 3, a first end of the fourth capacitor C31 is connected to the first DC terminal 31, a second end of the fourth capacitor C31 is connected to a first end of the fifth capacitor C32, and a second end of the fifth capacitor C32 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the fourth capacitor C31 and the fifth capacitor C32 is an intermediate potential point M1. For example, an external power supply E1 (see FIG. 2 ) that outputs a DC output voltage Vdc is connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage Vdc of the external power supply E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the fifth capacitor C32 is the same as the capacitance of the fourth capacitor C31. The phrase "the capacitance of the fifth capacitor C32 is the same as the capacitance of the fourth capacitor C31" does not necessarily mean that the capacitance of the fifth capacitor C32 exactly matches the capacitance of the fourth capacitor C31, but may mean that the capacitance of the fifth capacitor C32 is within a range of 90% to 110% of the capacitance of the fourth capacitor C31.

[0024] The power conversion device 100 is a T-type three-level three-phase inverter. In the power conversion device 100, each of a plurality of inverter circuits 1 has an output terminal 8. In the power conversion device 100, AC loads are connected to a plurality of (three in the example of FIG. 1 ) output terminals 8.

[0025] The AC load is, for example, a three-phase servo motor. In the power conversion device 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining is an inverter circuit 1W that outputs a W-phase voltage. For convenience of explanation, hereinafter, of the multiple output terminals 8, the output terminal 8 included in the inverter circuit 1U will be referred to as the output terminal 8U, the output terminal 8 included in the inverter circuit 1V will be referred to as the output terminal 8V, and the output terminal 8 included in the inverter circuit 1W will be referred to as the output terminal 8W.

[0026] Each of the inverter circuits 1 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. In each of the inverter circuits 1, the first switching element Q1 and the second switching element Q2 are connected in series from the positive electrode P1 to the negative electrode N1 in that order. That is, in each of the inverter circuits 1, as shown in FIG. 2 , a first circuit 11 including a series circuit of the first switching element Q1 and the second switching element Q2 is connected between the positive electrode P1 and the negative electrode N1. In each of the inverter circuits 1, a second circuit 12 including a series circuit of the third switching element Q3 and the fourth switching element Q4 is connected between an intermediate potential point M1 and an output point 13. The output point 13 is the connection point between the first switching element Q1 and the second switching element Q2. Each of the multiple inverter circuits 1 has a diode D1 connected in anti-parallel to the first switching element Q1, a diode D2 connected in anti-parallel to the second switching element Q2, a diode D3 connected in anti-parallel to the third switching element Q3, and a diode D4 connected in anti-parallel to the fourth switching element Q4.

[0027] The second circuit 12 has a bidirectional switch including a third switching element Q3, a fourth switching element Q4, a diode D3 and a diode D4.

[0028] Each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each inverter circuit 1 has a control terminal, a first main terminal, and a second main terminal. Each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each inverter circuit 1 is, for example, an insulated gate bipolar transistor (IGBT). Therefore, the control terminal, the first main terminal, and the second main terminal of each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each inverter circuit 1 are a gate terminal, a collector terminal, and an emitter terminal, respectively.

[0029] A control terminal of the first switching element Q1 of each inverter circuit 1 is connected to a corresponding one of the plurality of first gate drivers 61. A control terminal of the second switching element Q2 of each inverter circuit 1 is connected to a corresponding one of the plurality of second gate drivers 62. A control terminal of the third switching element Q3 of each inverter circuit 1 is connected to a corresponding one of the plurality of third gate drivers 63. A control terminal of the fourth switching element Q4 of each inverter circuit 1 is connected to a corresponding one of the plurality of fourth gate drivers 64.

[0030] In each inverter circuit 1, a first main terminal of a first switching element Q1 is connected to a positive electrode P1 of a DC power supply 3, a second main terminal of the first switching element Q1 is connected to a first main terminal of a second switching element Q2, and a second main terminal of the second switching element Q2 is connected to a negative electrode N1 of the DC power supply 3.

[0031] In each inverter circuit 1, the first main terminal of the third switching element Q3 is connected to the intermediate potential point M1, the second main terminal of the third switching element Q3 is connected to the second main terminal of the fourth switching element Q4, and the first main terminal of the fourth switching element Q4 is connected to the output point 13. Therefore, the bidirectional switch of the second circuit 12 (see FIG. 2 ) is a common-emitter bidirectional switch in which the second main terminal (emitter terminal) of the third switching element Q3 and the second main terminal (emitter terminal) of the fourth switching element Q4 are connected.

[0032] In the inverter circuit 1U, an output point 13 (a connection point between the first switching element Q1 and the second switching element Q2) is connected to the output terminal 8U. In the inverter circuit 1V, an output point 13 (a connection point between the first switching element Q1 and the second switching element Q2) is connected to the output terminal 8V. In the inverter circuit 1W, an output point 13 (a connection point between the first switching element Q1 and the second switching element Q2) is connected to the output terminal 8W. For example, a U-phase terminal of an AC load is connected to the output point 13 of the inverter circuit 1U via the output terminal 8U. In addition, for example, a V-phase terminal of an AC load is connected to the output point 13 of the inverter circuit 1V via the output terminal 8V. In addition, for example, a W-phase terminal of an AC load is connected to the output point 13 of the inverter circuit 1W via the output terminal 8W.

[0033] In each inverter circuit 1, the anode of diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In each inverter circuit 1, the anode of diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In each inverter circuit 1, the anode of diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. In each inverter circuit 1, the anode of diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0034] In each inverter circuit 1, the diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. In each inverter circuit 1, the diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2. In each inverter circuit 1, the diode D3 may be substituted with a parasitic diode of the IGBT that constitutes the third switching element Q3. In each inverter circuit 1, the diode D4 may be substituted with a parasitic diode of the IGBT that constitutes the fourth switching element Q4.

[0035] The plurality of first gate drivers 61 correspond one-to-one to the plurality of first switching elements Q1. Each of the plurality of first gate drivers 61 is connected to a control terminal of a corresponding first switching element Q1. Each of the plurality of first gate drivers 61 drives a corresponding first switching element Q1. The plurality of first gate drivers 61 are connected to a control device 4. The control device 4 outputs a plurality of first control signals S1 that correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first gate drivers 61 controls the on / off of the first switching element Q1 based on the provided first control signal S1.

[0036] The second gate drivers 62 correspond one-to-one to the second switching elements Q2. Each of the second gate drivers 62 is connected to a control terminal of a corresponding second switching element Q2. Each of the second gate drivers 62 drives a corresponding second switching element Q2. The second gate drivers 62 are connected to a control device 4. The control device 4 outputs second control signals S2 that correspond one-to-one to the second gate drivers 62. Each of the second gate drivers 62 controls the on / off of the second switching element Q2 based on the second control signal S2 provided thereto.

[0037] The plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3. Each of the plurality of third gate drivers 63 is connected to a control terminal of a corresponding third switching element Q3. Each of the plurality of third gate drivers 63 drives a corresponding third switching element Q3. The plurality of third gate drivers 63 are connected to a control device 4. The control device 4 outputs a plurality of third control signals S3 corresponding one-to-one to the plurality of third gate drivers 63. Each of the plurality of third gate drivers 63 controls the on / off of the third switching element Q3 based on the provided third control signal S3.

[0038] The plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4. Each of the plurality of fourth gate drivers 64 is connected to a control terminal of a corresponding fourth switching element Q4. Each of the plurality of fourth gate drivers 64 drives a corresponding fourth switching element Q4. The plurality of fourth gate drivers 64 are connected to a control device 4. The control device 4 outputs a plurality of fourth control signals S4 that correspond one-to-one to the plurality of fourth gate drivers 64. Each of the plurality of fourth gate drivers 64 controls the on / off of the fourth switching element Q4 based on the received fourth control signal S4.

[0039] Each of the multiple first bootstrap circuits 71 supplies a voltage to a corresponding one of the multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 includes a diode D11 in addition to a first capacitor C1. In each first bootstrap circuit 71, the anode of the diode D11 is connected to the high-potential end (first terminal) of the second capacitor C2, and the cathode of the diode D11 is connected to the high-potential end (first terminal) of the first capacitor C1. The high-potential end of the first capacitor C1 is connected to the positive terminal of the DC voltage source 6 via the diode D11 and a second diode D7. In each first bootstrap circuit 71, the high-potential end of the first capacitor C1 is connected to the high-potential power supply terminal of the first gate driver 61, and the low-potential end (second terminal) of the first capacitor C1 is connected to the low-potential power supply terminal of the first gate driver 61. The first bootstrap circuit 71 supplies the first gate driver 61 with a voltage (a voltage greater than the threshold voltage of the first switching element Q1) required to turn on the first switching element Q1 in the first gate driver 61.

[0040] The multiple second bootstrap circuits 72 correspond to the multiple third gate drivers 63 and the multiple fourth gate drivers 64. Each of the multiple second bootstrap circuits 72 supplies a voltage to the corresponding third gate driver 63 and the corresponding fourth gate driver 64. Each of the multiple second bootstrap circuits 72 includes a second capacitor C2. In each second bootstrap circuit 72, the high-potential end of the second capacitor C2 is connected to the positive terminal of the DC voltage source 6 via a second diode D7. In each second bootstrap circuit 72, the high-potential end (first end) of the second capacitor C2 is connected to the high-potential power supply terminal of the third gate driver 63 and the high-potential power supply terminal of the fourth gate driver 64, and the low-potential end (second end) of the second capacitor C2 is connected to the low-potential power supply terminal of the third gate driver 63 and the low-potential power supply terminal of the fourth gate driver 64. Each of the multiple second bootstrap circuits 72 supplies a voltage (a voltage greater than the threshold voltage of the third switching element Q3) required to turn on the third switching element Q3 in the corresponding third gate driver 63, and also supplies a voltage (a voltage greater than the threshold voltage of the fourth switching element Q4) required to turn on the fourth switching element Q4 in the corresponding fourth gate driver 64.

[0041] The DC voltage source 6 is, for example, a DC power supply including an isolated DC-DC converter. In this embodiment, the positive terminal of the DC voltage source 6 is connected to the high-potential power supply terminals of the plurality of second gate drivers 62. The positive terminal of the DC voltage source 6 is also connected to the high-potential end of the third capacitor C3 via a first diode D6. The high-potential end of the third capacitor C3 is connected to the high-potential end of the second capacitor C2 via a second diode D7 for each of the plurality of second bootstrap circuits 72. The negative terminal of the DC voltage source 6 is connected to the low-potential power supply terminals of the plurality of second gate drivers 62. The negative terminal of the DC voltage source 6 is also connected to the negative electrode N1 of the DC power supply unit 3.

[0042] The control device 4 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. Thus, the control device 4 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control device 4 includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control device 4 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The electronic circuits may be integrated into a single chip or distributed across multiple chips. The plurality of chips may be integrated into one device, or may be distributed among a plurality of devices.

[0043] The control device 4 outputs a plurality (three) of first control signals S1 for controlling a plurality (three) of first switching elements Q1. The control device 4 also outputs a plurality (three) of second control signals S2 for controlling a plurality (three) of second switching elements Q2. The control device 4 also outputs a plurality (three) of third control signals S3 for controlling a plurality of third switching elements Q3. The control device 4 also outputs a plurality (three) of fourth control signals S4 for controlling a plurality (three) of fourth switching elements Q4.

[0044] The three first control signals S1 include a first control signal US1 that controls the first switching element Q1 of the inverter circuit 1U, a first control signal VS1 that controls the first switching element Q1 of the inverter circuit 1V, and a first control signal WS1 that controls the first switching element Q1 of the inverter circuit 1W.

[0045] The three second control signals S2 include a second control signal US2 that controls the second switching element Q2 of the inverter circuit 1U, a second control signal VS2 that controls the second switching element Q2 of the inverter circuit 1V, and a second control signal WS2 that controls the second switching element Q2 of the inverter circuit 1W.

[0046] The three third control signals S3 include a third control signal US3 that controls the third switching element Q3 of the inverter circuit 1U, a third control signal VS3 that controls the third switching element Q3 of the inverter circuit 1V, and a third control signal WS3 that controls the third switching element Q3 of the inverter circuit 1W.

[0047] The three fourth control signals S4 include a fourth control signal US4 that controls the fourth switching element Q4 of the inverter circuit 1U, a fourth control signal VS4 that controls the fourth switching element Q4 of the inverter circuit 1V, and a fourth control signal WS4 that controls the fourth switching element Q4 of the inverter circuit 1W.

[0048] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3 and the plurality of fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level.

[0049] The first potential level is, for example, 0 V, and the second potential level is a potential level greater than the gate threshold voltage of the IGBT. That is, for each of the plurality of control signals (the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning off the switching element corresponding to that control signal, and the second potential level is a potential level for turning on the switching element corresponding to that control signal.

[0050] Each of the plurality of first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level and turned off when it is at a low level. Each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level and turned off when it is at a low level. Each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level and turned off when it is at a low level. Each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level and turned off when it is at a low level.

[0051] As described above, the auxiliary circuit 5 includes the fifth switching element Q5, the fifth gate driver 65, the third capacitor C3, the first diode D6, a plurality of second diodes D7, and a plurality of third diodes D8, and further includes a logical product element (AND element) 51.

[0052] The fifth switching element Q5 has a first main terminal, a second main terminal, and a gate terminal, with the first main terminal connected to the intermediate potential point M1. The fifth switching element Q5 is, for example, an insulated gate bipolar transistor (IGBT). Therefore, the control terminal, the first main terminal, and the second main terminal of the fifth switching element Q5 are the gate terminal, the collector terminal, and the emitter terminal, respectively. The auxiliary circuit 5 further includes a diode D5 connected in anti-parallel to the fifth switching element Q5. The diode D5 may be substituted by a parasitic diode of the IGBT constituting the fifth switching element Q5.

[0053] The fifth gate driver 65 has a high-potential power supply terminal, a low-potential power supply terminal, and an output terminal, and the high-potential power supply terminal is connected to the high-potential end of the third capacitor C3, the low-potential output terminal is connected to the low-potential end of the third capacitor C3 and the second main terminal of the fifth switching element Q5, and the output terminal is connected to the gate terminal of the fifth switching element Q5. The fifth gate driver 65 drives the fifth switching element Q5.

[0054] The third bootstrap circuit 73 includes a third capacitor C3 and a first diode D6. The third capacitor C3 is connected in parallel to the fifth gate driver 65. The first diode D6 has a cathode connected to the high-potential end (first end) of the third capacitor C3 and an anode connected to the positive terminal of the DC voltage source 6. The low-potential end of the third capacitor C3 is connected to the low-potential power supply terminal of the fifth gate driver 65 and the second main terminal of the fifth switching element Q5. The third capacitor C3 supplies the fifth gate driver 65 with a voltage (a voltage greater than the threshold voltage of the fifth switching element Q5) required to turn on the fifth switching element Q5 in the fifth gate driver 65.

[0055] The second diodes D7 have their anodes connected to the high potential end of the third capacitor C3, and their cathodes connected to the high potential ends of the second capacitors C2 of the second bootstrap circuits 72, respectively.

[0056] The plurality of third diodes D8 have their anodes connected to the low potential ends (second ends) of the third capacitor C3, and their cathodes connected to the low potential ends of the second capacitors C2 of the plurality of second bootstrap circuits 72.

[0057] The AND element 51 has a plurality of input terminals (three in the example of FIG. 1 ) and one output terminal. The input terminals of the AND element 51 are connected to the control device 4. The output terminal of the AND element 51 is connected to the fifth gate driver 65. A plurality of third control signals S3 are input to the input terminals of the AND element 51 from the control device 4. Each of the input terminals of the AND element 51 is connected to a wiring section between the control device 4 and each of the third gate drivers 63.

[0058] (3) Operation of the Power Conversion Device In the power conversion device 100, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the power conversion device 100, the switching state of each of the three inverter circuits 1U, 1V, and 1W is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state differ from one another. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1 to Q4. Note that with regard to the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with one another.

[0059] The first switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are in the ON state and both the second switching element Q2 and the fourth switching element Q4 are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the first switching state, the potential of the output point 13 becomes the potential level (e.g., Vdc) of the positive electrode P1 of the DC power supply unit 3.

[0060] The second switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state. When controlled to the second switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1 in the second switching state, the potential of the output point 13 becomes the potential level of the intermediate potential point M1 (e.g., Vdc / 2).

[0061] The third switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are in the OFF state and both the second switching element Q2 and the fourth switching element Q4 are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the third switching state, the potential of the output point 13 becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., 0).

[0062] The first switching state, the second switching state, and the third switching state will be described below with reference to Figures 1 to 5. Note that Figures 2 to 5 show only one of the three inverter circuits 1, and omit the illustration of the remaining two inverter circuits 1. Also, Figures 2 to 5 omit the illustration of the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, the plurality of fourth gate drivers 64, the plurality of first bootstrap circuits 71, the plurality of second bootstrap circuits 72, the DC voltage source 6, the control device 4, and the auxiliary circuit 5.

[0063] 2, when the inverter circuit 1 is in the first switching state, a current I1 flows through a path from the positive electrode P1 of the DC power supply unit 3 to the first switching element Q1, the output point 13, and the output terminal 8, and the voltage value of the output voltage to the AC load becomes approximately Vdc. Also, when the inverter circuit 1 is in the first switching state, a voltage required for turning on the first switching element Q1 is supplied from the first capacitor C1 of the first bootstrap circuit 71 (see FIG. 1) to the first gate driver 61 by the first gate driver 61.

[0064] 3, for example, a current I1 flows through a path of the intermediate potential point M1 of the DC power supply unit 3, the third switching element Q3, the fourth switching element Q4, the output point 13, and the output terminal 8, and the voltage value of the output voltage to the AC load becomes approximately Vdc / 2. More specifically, when the inverter circuits 1U, 1V, and 1W (see FIG. 1) are in the second switching state, the third switching state, and the third switching state, respectively, a current I1 flows through a path of the intermediate potential point M1 of the DC power supply unit 3, the third switching element Q3 of the inverter circuit 1U, the fourth switching element Q4 of the inverter circuit 1U, the output point 13, and the output terminal 8U.

[0065] Furthermore, when the inverter circuit 1 is in the second switching state, a voltage required to turn on the third switching element Q3 is supplied from the second capacitor C2 of the second bootstrap circuit 72 (see FIG. 1) to the third gate driver 63 by the third gate driver 63. Furthermore, when the inverter circuit 1 is in the second switching state, a voltage required to turn on the fourth switching element Q4 is supplied from the second capacitor C2 of the second bootstrap circuit 72 to the fourth gate driver 64 by the fourth gate driver 64.

[0066] Furthermore, when the inverter circuit 1 is in the third switching state, as shown in FIG. 4, a current I1 flows through the path of the output terminal 8 - the output point 13 - the second switching element Q2 - the negative pole N1 of the DC power supply unit 3, and the voltage value of the output voltage to the AC load becomes approximately 0.

[0067] Furthermore, when the inverter circuit 1 is in the second switching state (when it changes from the third switching state to the second switching state), for example, as shown in Fig. 5, a current I1 flows through a path of the output terminal 8-output point 13-fourth switching element Q4-third switching element Q3-midpoint potential point M1, and the voltage value of the output voltage to the AC load is approximately Vdc / 2. More specifically, when the inverter circuits 1U, 1V, and 1W (see Fig. 1) are in the second switching state, the second switching state, and the first switching state, respectively, a current flows through a path of the output terminal 8U of the inverter circuit 1U-output point 13-fourth switching element Q4-third switching element Q3-midpoint potential point M1, and the voltage value of the output voltage to the AC load is approximately Vdc / 2.

[0068] The control device 4 (see FIG. 1) generates first to fourth control signals S1 to S4 (US1 to US4) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U, first to fourth control signals S1 to S4 (VS1 to VS4) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V, and first to fourth control signals S1 to S4 (WS1 to WS4) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W, based on voltage commands Vu, Vv, and Vw (see FIG. 6) related to the output voltages of the inverter circuits 1U, 1V, and 1W, respectively.

[0069] As shown in FIG. 6 , the voltage commands Vu, Vv, and Vw are sinusoidal signals whose phases are, for example, 120° apart, and whose values ​​(voltage command values) change over time. The voltage commands Vu, Vv, and Vw have the same cycle length. The control device 4 (see FIG. 1 ) may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detector that detects the state of the AC load. When the AC load is a three-phase servo motor, the information output from the detector includes, for example, at least one of the following: information on the detection results from multiple current sensors that detect the output currents flowing through the U, V, and W phases of the AC load; and information on the detection results from an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.

[0070] The output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other.

[0071] In this embodiment, the control device 4 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing space vector modulation (hereinafter also referred to as voltage vector control).

[0072] The voltage vector control by the control device 4 will be described in more detail below.

[0073] The control device 4 stores a group of voltage vectors in advance. Each of the group of voltage vectors is determined by a combination of the potential levels of the output points 13 between the first switching elements Q1 and the second switching elements Q2 of the multiple inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the inverter circuit 1U corresponding to the U phase, the switching state of the inverter circuit 1V corresponding to the V phase, and the switching state of the inverter circuit 1W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 3. ３ = 27 pieces.

[0074] The group of voltage vectors includes three zero vectors V0p, V0z, and V0n, each of which has a magnitude of zero, as shown in the three-level space vector diagram (space vector modulation diagram) in Figure 7. The group of voltage vectors also includes three zero vectors V0p, V0z, and V0n, each of which has a magnitude of (2 / 3) １／２ The group of voltage vectors includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which is 2 Vdc and points in different directions. The magnitude of each of the voltage vectors is (2 / 3) １／２ The group of voltage vectors includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2 / 3) １／２ ・3 １／２ Six voltage vectors V13, V14, V15, V16, V17, and V18 are Vdc and have different directions. １／２ Vdc is the reference magnitude. In Figure 7, the angle between two adjacent voltage vectors of the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between two adjacent voltage vectors of the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees. Note that Figure 7 is a three-level space vector diagram illustrating a group of voltage vectors on an orthogonal α-β coordinate system.

[0075] A group of voltage vectors can be expressed as a three-level space vector diagram (space vector modulation diagram) shown in FIG. 8 by expressing the first switching state, the second switching state, and the third switching state with the symbols “P,” “0,” and “N,” respectively, and notating them in the order of U phase, V phase, and W phase.

[0076] 8, the three zero vectors V0p, V0z, and V0n can be expressed as V0p[PPP], V0z

[000] , and V0n[NNN], respectively. For example, V0p[PPP] represents that, with respect to the zero vector V0p, the switching state of the U-phase inverter circuit 1U is "P," the switching state of the V-phase inverter circuit 1V is "P," and the switching state of the W-phase inverter circuit 1W is "P." Furthermore, V0z

[000] represents that, with respect to the zero vector V0z, the switching state of the U-phase inverter circuit 1U is "0," the switching state of the V-phase inverter circuit 1V is "0," and the switching state of the W-phase inverter circuit 1W is "0." Furthermore, V0n[NNN] represents that, with respect to the zero vector V0n, the switching state of the U-phase inverter circuit 1U is "N", the switching state of the V-phase inverter circuit 1V is "N", and the switching state of the W-phase inverter circuit 1W is "N". When the switching state of the inverter circuit 1 is "P", the potential of the output point 13 in the inverter circuit 1 becomes the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the inverter circuit 1 is "N", the potential of the output point 13 in the inverter circuit 1 becomes the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the inverter circuit 1 is "0", the potential of the output point 13 in the inverter circuit 1 becomes the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0077] Furthermore, a voltage vector with a "p" suffix, such as V10p, includes a "P" but does not include an "N". This also applies below. Furthermore, a voltage vector with an "n" suffix, such as V10n, includes an "N" but does not include a "P". This also applies below.

[0078] The six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors without "p," "n," or "z" after the number attached to "V," such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the switching states of the three phases. The group of voltage vectors includes six voltage vectors V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], each of which has a magnitude twice the reference magnitude.

[0079] Furthermore, the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively. Therefore, the group of voltage vectors includes 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], each of which has a reference magnitude as a voltage vector (reference vector).

[0080] The six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0], respectively. １／２ The voltage vectors having double the magnitude include six voltage vectors V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0].

[0081] The control device 4 converts into a command voltage vector Vref (see FIG. 9 ) the instantaneous value of the command voltage related to the output voltage of each of the multiple inverter circuits 1. If the α-axis component of the command voltage vector Vref on the orthogonal α-β coordinate system is Vα and the β-axis component of the command voltage vector Vref on the orthogonal α-β coordinate system is Vβ, the command voltage vector Vref can be calculated using equation (1).

[0082]

[0083] The control device 4 selects a first voltage vector Va, a second voltage vector Vb, and a third voltage vector Vc corresponding to the vertices of an equilateral triangle surrounding the command voltage vector Vref as multiple voltage vectors to be used within the control period Ts (see Figures 10 and 11) from the group of voltage vectors, and determines a first allocation time T0 for the first voltage vector Va, a second allocation time T1 for the second voltage vector Vb, and a third allocation time T2 for the third voltage vector Vc so that the composite vector of the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc matches the command voltage vector Vref.

[0084] The control device 4 determines the first allocated time T0, the second allocated time T1, and the third allocated time T2 so as to satisfy equations (2) and (3), where the voltage vectors at the vertices of an equilateral triangle surrounding the command voltage vector Vref are the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc, and the magnitude and angle of the command voltage vector Vref are V and θ, respectively. "j" in equation (2) is the imaginary unit. The angle between the first voltage vector Va, which is closest to the command voltage vector Vref, and the command voltage vector Vref is smaller than 30 degrees.

[0085]

[0086]

[0087] In addition, the control device 4 distributes the first distribution time T0 to each first voltage vector Va based on the number of times the first voltage vector Va is used within the control period Ts, distributes the second distribution time T1 to each second voltage vector Vb based on the number of times the second voltage vector Vb is used within the control period Ts, and distributes the third distribution time T2 to each third voltage vector Vc based on the number of times the third voltage vector Vc is used within the control period Ts.

[0088] In the example shown in Fig. 9, the first voltage vector Va is a voltage vector V8p[PP0] and a voltage vector V8n[00N], the second voltage vector Vb is a voltage vector V13[P0N], and the third voltage vector Vc is a voltage vector V7p[P00]. Fig. 10 shows the switching states of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W when the control device 4 sequentially uses eight voltage vectors within a control period Ts. Fig. 11 shows the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the U-phase inverter circuit 1U when the control device 4 sequentially uses eight voltage vectors within a control period Ts. 10 illustrates an example in which the allocated time of the first voltage vector Va (voltage vector V8p[PP0] and voltage vector V8n[00N]) is set to a first allocated time T0, the allocated time of the second voltage vector Vb (voltage vector V13[P0N]) is set to a second allocated time T1, and the allocated time of the third voltage vector Vc (voltage vector V7p[P00]) is set to a third allocated time T2 during a control period Ts. The control period Ts is one period of the carrier signal.

[0089] When changing the switching state of two adjacent voltage vectors among the eight voltage vectors arranged in time series within a control period Ts, the control device 4 changes the switching state of the inverter circuit 1 of only one phase among the U phase, V phase, and W phase between "P" and "0" or between "0" and "N", and uses the same voltage vector twice. In Fig. 10, the control device 4 uses the voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N] in this order. 10 , the control device 4 uses the first voltage vector Va four times, and therefore the allocation time for each of the first voltage vector Va (voltage vector V8n[00N]) used first within the control period Ts, the first voltage vector Va (voltage vector V8p[PP0]) used fourth, the first voltage vector Va (voltage vector V8p[PP0]) used fifth, and the first voltage vector Va (voltage vector V8n[00N]) used eighth within the control period Ts is set to T0 / 4. Also, in the example of FIG. 10 , the control device 4 uses the second voltage vector Vb twice, and therefore the allocation time for each of the second voltage vector Vb (voltage vector V13[P0N]) used second within the control period Ts and the second voltage vector Vb (voltage vector V13[P0N]) used seventh within the control period Ts is set to T1 / 2. 10, the control device 4 uses the third voltage vector Vc twice, and therefore the allocation time of each of the third voltage vector Vc (voltage vector V7p[P00]) used third and the third voltage vector Vc (voltage vector V7p[P00]) used sixth within the control period Ts is set to T2 / 2. Note that even if the command voltage vector Vref is the same as in FIG. 9, the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.

[0090] The control device 4 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 within a predetermined control period Ts (see FIG. 10) so as to match the resultant vector of the first voltage vector Va (in the example shown in FIG. 9, voltage vector V8p[PP0] and voltage vector V8n[00N]), the second voltage vector Vb (in the example shown in FIG. 9, voltage vector V13[P0N]), and the third voltage vector Vc (in the example shown in FIG. 9, voltage vector V7p[P00]) with the command voltage vector Vref.

[0091] The output current of the inverter circuit 1 has a sinusoidal waveform as shown in Figure 12. The polarity of the output current of the inverter circuit 1 is defined as positive when it flows from the output point 13 to the output terminal 8, and negative when it flows from the output terminal 8 to the output point 13. During a period in which the polarity of the output current of the inverter circuit 1 is positive, the control device 4 may control the inverter circuit 1 to the first switching state or the second switching state, but never to the third switching state. Furthermore, during a period in which the polarity of the output current of the inverter circuit 1 is negative, the control device 4 may control the inverter circuit 1 to the second switching state or the third switching state, but never to the first switching state.

[0092] In the comparative example switching element drive circuit not including the auxiliary circuit 5, the first capacitor of the first bootstrap circuit and the second capacitor of the second bootstrap circuit corresponding to the first switching element of the inverter circuit cannot be charged during a period when the polarity of the output current of the inverter circuit is positive. As a result, in the comparative example switching element drive circuit, the voltage of the first capacitor may fall below the threshold voltage of the first switching element, making it impossible to stably drive the first switching element. Also, in the comparative example switching element drive circuit, the voltage of the second capacitor may fall below the respective threshold voltages of the third switching element and the fourth switching element, making it impossible to stably drive the third switching element and the fourth switching element.

[0093] In contrast, the switching element drive circuit 2 (see FIG. 1) of this embodiment is equipped with an auxiliary circuit 5, and therefore is able to charge the first capacitor C1 and the second capacitor C2 even during periods when the polarity of the output current of the inverter circuit 1 is positive, making it possible to stably drive each of the first switching element Q1, the third switching element Q3, and the fourth switching element Q4.

[0094] The operation of the auxiliary circuit 5 will be described below in relation to the operation of the control device 4 with reference to FIGS.

[0095] 13 illustrates voltage commands Vu, Vv, and Vw for each phase (U phase, V phase, and W phase), three third control signals US3, VS3, and WS3 output from the control device 4, and a fifth control signal S5 output from the output terminal of the AND element 51. The fifth control signal S5 is provided to the fifth gate driver 65. Note that in FIG. 13, for each of the three third control signals US3, VS3, and WS3 and the fifth control signal S5, a high level is represented as "H" and a low level is represented as "L."

[0096] In the auxiliary circuit 5, the third control signal US3 is input to one of the multiple (three in the example of FIG. 1 ) input terminals of the AND element 51, the third control signal VS3 is input to another input terminal, and the third control signal WS3 is input to the remaining input terminal. In the auxiliary circuit 5, when all of the multiple (three in the example of FIG. 1 ) third control signals US3, VS3, and WS3 are at high level H, the fifth control signal S5 goes to high level H. Furthermore, in the auxiliary circuit 5, when at least one of the multiple third control signals US3, VS3, and WS3 is at low level L, the fifth control signal S5 goes to low level L.

[0097] In the power conversion device 100, when the fifth control signal S5 is at low level L, the fifth switching element Q5 is turned off and the second switching element Q2 is turned on in one of the three inverter circuits 1. Therefore, in the power conversion device 100, power is supplied from the DC voltage source 6 to the third capacitor C3 of the third bootstrap circuit 73. In the power conversion device 100, for example, when the second switching element Q2 is turned on in the U-phase inverter circuit 1U, the third capacitor C3 is charged from the DC voltage source 6 via a charging path Ru3 shown in FIG. 14. The charging path Ru3 is a path from the positive terminal of the DC voltage source 6 to the first diode D6 to the third capacitor C3 to the third diode D8 to the diode D4 to the second switching element Q2 to the negative terminal of the DC voltage source 6.

[0098] In the power conversion device 100, the fifth control signal S5 becomes high level H when the voltage vector generated by the control device 4 is any of the seven voltage vectors V0n[NNN], V7p[P00], V8p[PP0], V9P[0P0], V10p[0PP], V11p[00P], and V12n[0N0] enclosed in a square in FIG. 8 . In the power conversion device 100, when the fifth control signal S5 is high level H, the fifth switching element Q5 is turned on and the third switching element Q3 is turned on in all three inverter circuits 1. Therefore, in the power conversion device 100, power is supplied from the third capacitor C3 of the third bootstrap circuit 73 to the first capacitor C1 of the three first bootstrap circuits 71 and the second capacitor C2 of the three second bootstrap circuits 72. In the power conversion device 100, the first capacitor C1 of the first bootstrap circuit 71 corresponding to the U-phase inverter circuit 1U is charged from the third capacitor C3 via a charging path Ru1 shown in FIG. 15. The charging path Ru1 is a path from the high potential end of the third capacitor C3 to the second diode D7, diode D11, the first capacitor C1, the fourth switching element Q4, the third switching element Q3, the fifth switching element Q5, and the low potential end of the third capacitor C3. In the power conversion device 100, the second capacitor C2 of the second bootstrap circuit 72 corresponding to the U-phase inverter circuit 1U is charged from the third capacitor C3 via a charging path Ru2 shown in FIG. 15. The charging path Ru2 is a path from the high potential end of the third capacitor C3 to the second diode D7, the second capacitor C2, the third switching element Q3, the fifth switching element Q5, and the low potential end of the third capacitor C3.

[0099] FIG. 16 shows waveforms of the output current of the U-phase inverter circuit 1U, the voltage VC1 across the first capacitor C1 of the first bootstrap circuit 71 corresponding to the first switching element Q1 of the inverter circuit 1U (see FIGS. 14 and 15), and the voltage VC2 across the second capacitor C2 of the second bootstrap circuit 72 corresponding to the third switching element Q3 and the fourth switching element Q4 of the inverter circuit 1U (see FIGS. 14 and 15).

[0100] 16 shows that in the switching element drive circuit 2 according to the first embodiment, the voltage VC1 of the first capacitor C1 and the voltage VC2 of the second capacitor C2 are suppressed during periods when the output current of the inverter circuit 1U is positive. In the switching element drive circuit of the comparative example described above, during periods when the output current of the inverter circuit is positive, the voltages of the first capacitor C1 and the second capacitor C2 are suppressed to 7 V or less, reducing the difference between the voltages and the gate threshold voltages of the IGBTs. This may cause the operation of the first switching element, the third switching element, and the fourth switching element to become unstable. Note that, during periods when the output current of the inverter circuit 1V and the output current of the inverter circuit 1W are positive, the voltages VC1 of the first capacitor C1 and the voltage VC2 of the second capacitor C2 are suppressed, just as in the periods when the output current of the inverter circuit 1U is positive.

[0101] (4) Advantages The switching element drive circuit 2 according to the first embodiment includes an auxiliary circuit 5 connected to a plurality of third bootstrap circuits 73. Each of the plurality of first bootstrap circuits 71 further includes a diode D11 (bootstrap diode). The diode D11 has a cathode connected to the high-potential end of the first capacitor C1 and an anode connected to the high-potential end of the second capacitor C2 of a corresponding one of the plurality of second bootstrap circuits 72. The auxiliary circuit 5 includes a fifth switching element Q5, a fifth gate driver 65, a third capacitor C3, a first diode D6, a plurality of second diodes D7, and a plurality of third diodes D8. The fifth switching element Q5 has a first main terminal, a second main terminal, and a gate terminal, and the first main terminal is connected to the intermediate potential point M1. The fifth gate driver 65 is connected to the gate terminal and the second main terminal of the fifth switching element Q5 to drive the fifth switching element Q5. The third capacitor C3 is connected in parallel to the fifth gate driver 65. The first diode D6 has its cathode connected to the high potential end of the third capacitor C3 and its anode connected to the positive terminal of the DC voltage source 6. The second diodes D7 have their cathodes connected to the high potential ends of the second capacitors C2 of the second bootstrap circuits 72 and their anodes connected to the high potential ends of the third capacitor C3. The third diodes D8 have their cathodes connected to the low potential ends of the second capacitors C2 of the second bootstrap circuits 72 and their anodes connected to the low potential ends of the third capacitor C3.

[0102] The above configuration makes it possible to suppress a decrease in the voltage VC1 across the first capacitor C1 of each of the multiple first bootstrap circuits 71 and the voltage VC2 across the second capacitor C2 of each of the multiple second bootstrap circuits 72. More specifically, with the above configuration, when the multiple second switching elements Q2 are off, the multiple third switching elements Q3 are on, and the load current is positive, the fifth switching element Q5 is turned on, so that the first capacitor C1 of each of the multiple first bootstrap circuits 71 and the second capacitor C2 of each of the multiple second bootstrap circuits 72 can be charged from the third capacitor C3. This makes it possible to suppress a decrease in the voltage VC1 across the first capacitor C1 of each of the multiple first bootstrap circuits 71 and the voltage VC2 across the second capacitor C2 of each of the multiple second bootstrap circuits 72.

[0103] In the switching element drive circuit 2 according to the first embodiment, the auxiliary circuit 5 further includes an AND element 51. The AND element 51 has a plurality of input terminals and an output terminal, the plurality of input terminals being connected to the control device 4, and the output terminal being connected to the fifth gate driver 65. In the auxiliary circuit 5, a plurality of third control signals S3 are input to the plurality of input terminals of the AND element 51.

[0104] According to the above configuration, it is possible to suppress a decrease in the voltage VC1 of the first capacitor C1 of each of the plurality of first bootstrap circuits 71 and the voltage VC2 of the second capacitor C2 of each of the plurality of second bootstrap circuits 72 without performing any special control in the control device 4.

[0105] The power conversion device 100 according to the first embodiment also includes a switching element drive circuit 2 and a plurality of T-type three-level inverters 1 .

[0106] According to the above configuration, it is possible to suppress a decrease in the voltage VC1 of the first capacitor C1 of each of the multiple first bootstrap circuits 71 and the voltage VC2 of the second capacitor C2 of each of the multiple second bootstrap circuits 72.

[0107] Second Embodiment A power conversion device 100A according to a second embodiment will be described with reference to FIG.

[0108] (1) Configuration The power conversion device 100A according to the second embodiment is substantially the same as the power conversion device 100 according to the first embodiment (see FIG. 1), but differs from the power conversion device 100 according to the first embodiment in that it includes a switching element drive circuit 2A instead of the switching element drive circuit 2 according to the first embodiment (see FIG. 1). Note that, with respect to the power conversion device 100A according to the second embodiment, components similar to those of the power conversion device 100 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted. Also, with respect to the switching element drive circuit 2A according to the second embodiment, components similar to those of the switching element drive circuit 2 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0109] The switching element drive circuit 2A according to the second embodiment differs from the switching element drive circuit 2 according to the first embodiment in that it further includes a plurality of diodes D9 (three in the example of FIG. 17 ) connected between the positive terminal of the DC voltage source 6 and the anodes of the diodes D11 of each of the plurality of first bootstrap circuits 71 (three in the example of FIG. 17 ). The anodes of the plurality of diodes D9 are connected to the positive terminal of the DC voltage source 6. The plurality of diodes D9 correspond one-to-one to the plurality of diodes D11. The cathode of each of the plurality of diodes D9 is connected to the anode of a corresponding one of the plurality of diodes D11.

[0110] (2) Operation of the Power Conversion Device The operation of the power conversion device 100A including the switching element drive circuit 2A according to the second embodiment is similar to the operation of the power conversion device 100 according to the first embodiment, and therefore a description thereof will be omitted.

[0111] (3) Advantages The switching element drive circuit 2A according to the second embodiment includes the auxiliary circuit 5, similar to the switching element drive circuit 2 according to the first embodiment. This makes it possible to suppress a decrease in the voltage VC1 across the first capacitor C1 of each of the plurality of first bootstrap circuits 71 (see FIGS. 14 and 15) and the voltage VC2 across the second capacitor C2 of each of the plurality of second bootstrap circuits 72 (see FIGS. 14 and 15).

[0112] Moreover, the power conversion device 100A according to the second embodiment includes a switching element drive circuit 2A and a plurality of T-type three-level inverters 1.

[0113] According to the above configuration, it is possible to suppress a decrease in the voltage VC1 of the first capacitor C1 of each of the multiple first bootstrap circuits 71 and the voltage VC2 of the second capacitor C2 of each of the multiple second bootstrap circuits 72.

[0114] Third Embodiment A switching element drive circuit 2B and a power conversion device 100B according to a third embodiment will be described with reference to FIGS. 18 and 19. FIG.

[0115] (1) Configuration The power conversion device 100B according to the third embodiment is substantially the same as the power conversion device 100 according to the first embodiment (see FIG. 1), but differs from the power conversion device 100 according to the first embodiment in that it includes a switching element drive circuit 2B instead of the switching element drive circuit 2 according to the first embodiment (see FIG. 1). Note that, with respect to the power conversion device 100B according to the third embodiment, components similar to those of the power conversion device 100 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted. Also, with respect to the switching element drive circuit 2B according to the third embodiment, components similar to those of the switching element drive circuit 2 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0116] (2) Operation of the Power Conversion Device The switching element drive circuit 2B according to the third embodiment differs from the switching element drive circuit 2 according to the first embodiment in that the control device 4 performs triangular wave PWM control instead of voltage vector control.

[0117] As shown in FIG. 19 , for each T-type three-level inverter 1 (inverter circuit 1), the control device 4 compares the output voltage command value Vout at the output terminal 8 (see FIG. 18 ) with a triangular-wave first carrier wave CA1 to generate a first control signal S1 consisting of a PWM signal. The control device 4 also generates a third control signal S3 consisting of a PWM signal obtained by inverting the PWM signal constituting the first control signal S1. Therefore, in the inverter circuit 1, the first switching element Q1 and the third switching element Q3 operate complementarily. As shown in FIG. 19 , the control device 4 also compares the output voltage command value Vout at the output terminal 8 (see FIG. 18 ) with a triangular-wave second carrier wave CA2 to generate a second control signal S2 consisting of a PWM signal. The control device 4 also generates a fourth control signal S4 consisting of a PWM signal obtained by inverting the PWM signal constituting the second control signal S2. Therefore, in the inverter circuit 1, the second switching element Q2 and the fourth switching element Q4 operate complementarily. In FIG. 19, regarding the potential levels of each of the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4, a low level is represented as "L" and a high level is represented as "H".

[0118] (3) Advantages The switching element drive circuit 2B according to the third embodiment includes the auxiliary circuit 5, similar to the switching element drive circuit 2 according to the first embodiment. This makes it possible to suppress a decrease in the voltage VC1 across the first capacitor C1 of each of the plurality of first bootstrap circuits 71 (see FIGS. 14 and 15) and the voltage VC2 across the second capacitor C2 of each of the plurality of second bootstrap circuits 72 (see FIGS. 14 and 15).

[0119] Moreover, the power conversion device 100B according to the third embodiment includes a switching element drive circuit 2B and a plurality of T-type three-level inverters 1.

[0120] According to the above configuration, it is possible to suppress a decrease in the voltage VC1 of the first capacitor C1 of each of the multiple first bootstrap circuits 71 and the voltage VC2 of the second capacitor C2 of each of the multiple second bootstrap circuits 72.

[0121] (Modifications) The above-described first to third embodiments are merely examples of various embodiments of the present disclosure. The above-described first to third embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0122] For example, in the switching element drive circuit 2A according to the second embodiment, the control device 4 may be configured to perform triangular wave PWM control instead of voltage vector control.

[0123] Furthermore, in the switching element drive circuit 2 of embodiment 1 or the switching element drive circuit 2A of embodiment 2, the control device 4 may include a logical product element 51, or the control device 4 may have a function similar to that of the logical product element 51.

[0124] Furthermore, the third capacitor C3 of the auxiliary circuit 5 is not limited to one capacitor, but may be configured by connecting two capacitors in parallel, for example.

[0125] Furthermore, each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, the fourth switching elements Q4, and the fifth switching elements Q5 is not limited to an IGBT but may be a MOSFET. In this case, the control terminal, the first main terminal, and the second main terminal of each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, the fourth switching elements Q4, and the fifth switching elements Q5 are a gate terminal, a drain terminal, and a source terminal, respectively. Each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, the fourth switching elements Q4, and the fifth switching elements Q5 may be a gate injection transistor (GIT). The GIT is, for example, a GaN-based GIT.

[0126] Each of the first bootstrap circuits 71 may further include a first Zener diode connected in parallel to the first capacitor C1. In this case, the cathode of the first Zener diode is connected to the high potential end of the first capacitor C1, and the anode of the first Zener diode is connected to the low potential end of the first capacitor C1. Each of the second bootstrap circuits 72 may further include a second Zener diode connected in parallel to the second capacitor C2. In this case, the cathode of the second Zener diode is connected to the high potential end of the second capacitor C2, and the anode of the second Zener diode is connected to the low potential end of the second capacitor C2. The auxiliary circuit 5 may further include a third Zener diode connected in parallel to the third capacitor C3. In this case, the cathode of the third Zener diode is connected to the high potential end of the third capacitor C3, and the anode of the third Zener diode is connected to the low potential end of the third capacitor C3.

[0127] Each of the first bootstrap circuits 71 may include a resistor (first resistor) connected between the cathode of the diode D11 and the high potential end of the first capacitor C1. Each of the second bootstrap circuits 72 may include a resistor (second resistor) connected between the cathode of the second diode D7 and the high potential end of the second capacitor C2. The auxiliary circuit 5 may include a resistor (third resistor) connected between the cathode of the first diode D6 and the high potential end of the third capacitor C3.

[0128] Furthermore, the power conversion devices 100, 100A, and 100B are not limited to configurations having three T-type three-level inverters 1, but may be configurations having two T-type three-level inverters 1, or configurations having four or more T-type three-level inverters 1.

[0129] (Aspects) The following aspects are disclosed in this specification.

[0130] A switching element drive circuit (2; 2A; 2B) according to a first aspect drives a plurality of T-type three-level inverters (1). The plurality of T-type three-level inverters (1) include a plurality of first switching elements (Q1), a plurality of second switching elements (Q2), a plurality of third switching elements (Q3), and a plurality of fourth switching elements (Q4). The plurality of first switching elements (Q1) are connected to a positive electrode (P1) of a DC power supply unit (3) having a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The plurality of second switching elements (Q2) are each connected in series to the plurality of first switching elements (Q1) and connected to the negative electrode (N1). The plurality of third switching elements (Q3) are connected to the intermediate potential point (M1). The plurality of fourth switching elements (Q4) are respectively connected in series to the plurality of third switching elements (Q3) and connected to output points (13) of corresponding T-type three-level inverters (1) among the plurality of T-type three-level inverters (1). The switching element drive circuit (2; 2A; 2B) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a DC voltage source (6), a control device (4), and an auxiliary circuit (5). The plurality of first gate drivers (61) respectively drive the plurality of first switching elements (Q1). The plurality of second gate drivers (62) respectively drive the plurality of second switching elements (Q2). The plurality of third gate drivers (63) respectively drive the plurality of third switching elements (Q3). The plurality of fourth gate drivers (64) respectively drive the plurality of fourth switching elements (Q4). The plurality of first bootstrap circuits (71) correspond one-to-one to the plurality of first gate drivers (61). Each of the plurality of first bootstrap circuits (71) includes a first capacitor (C1) connected in parallel to the corresponding first gate driver (61).Each of the multiple second bootstrap circuits (72) includes a second capacitor (C2) connected in parallel to a corresponding third gate driver (63) among the multiple third gate drivers (63) and a corresponding fourth gate driver (64) among the multiple fourth gate drivers (64). The DC voltage source (6) is connected in parallel to the multiple second gate drivers (62). The control device (4) outputs multiple first control signals (S1), multiple second control signals (S2), multiple third control signals (S3), and multiple fourth control signals (S4) to the multiple first gate drivers (61), multiple second gate drivers (62), multiple third gate drivers (63), and multiple fourth gate drivers (64), respectively. The auxiliary circuit (5) is connected to the multiple second bootstrap circuits (72). Each of the multiple first bootstrap circuits (71) further includes a bootstrap diode (diode D11). The bootstrap diode has a cathode connected to the high potential end of the first capacitor (C1) and an anode connected to the high potential end of the second capacitor (C2) of a corresponding one of the plurality of second bootstrap circuits (72). The auxiliary circuit (5) includes a fifth switching element (Q5), a fifth gate driver (65), a third capacitor (C3), a first diode (D6), a plurality of second diodes (D7), and a plurality of third diodes (D8). The fifth switching element (Q5) has a first main terminal, a second main terminal, and a gate terminal, and the first main terminal is connected to the intermediate potential point (M1). The fifth gate driver (65) is connected to the gate terminal and the second main terminal of the fifth switching element (Q5) and drives the fifth switching element (Q5). The third capacitor (C3) is connected in parallel to the fifth gate driver (65). The first diode (D6) has a first cathode connected to the high potential end of the third capacitor (C3) and a first anode connected to the positive terminal of the DC voltage source (6). The second diodes (D7) have second cathodes connected to the high potential ends of the second capacitors (C2) of the second bootstrap circuits (72), respectively, and second anodes connected to the high potential ends of the third capacitors (C3).The third diodes (D8) have third cathodes connected to the low potential ends of the second capacitors (C2) of the second bootstrap circuits (72), and third anodes connected to the low potential ends of the third capacitors (C3).

[0131] According to this aspect, it is possible to suppress a decrease in the voltage (VC1) of the first capacitor (C1) of each of the plurality of first bootstrap circuits (71) and the voltage (VC2) of the second capacitor (C2) of each of the plurality of second bootstrap circuits (72).

[0132] In the switching element drive circuit (2; 2A; 2B) according to the second aspect, in the first aspect, the auxiliary circuit (5) further includes a logical product element (51). The logical product element (51) has a plurality of input terminals and an output terminal, the plurality of input terminals being connected to the control device (4) and the output terminal being connected to a fifth gate driver (65). In the auxiliary circuit (5), a plurality of third control signals (S3) are input to the plurality of input terminals of the logical product element (51).

[0133] According to this aspect, it is possible to suppress a decrease in the voltage (VC1) of the first capacitor (C1) of each of the plurality of first bootstrap circuits (71) and the voltage (VC2) of the second capacitor (C2) of each of the plurality of second bootstrap circuits (72) without performing any special control in the control device (4).

[0134] In the switching element drive circuit (2; 2A) according to the third aspect, in the first or second aspect, the control device (4) generates a plurality of first control signals (S1), a plurality of second control signals (S2), a plurality of third control signals (S3), and a plurality of fourth control signals (S4) by space vector modulation.

[0135] In the switching element drive circuit (2B) according to the fourth aspect, in the first or second aspect, the control device (4) generates a plurality of first control signals (S1), a plurality of second control signals (S2), a plurality of third control signals (S3), and a plurality of fourth control signals (S4) by triangular wave PWM control.

[0136] In a switching element drive circuit (2; 2A; 2B) according to a fifth aspect, in any one of the first to fourth aspects, the fifth switching element (Q5) is an insulated gate bipolar transistor, a MOSFET, or a gate injection transistor.

[0137] A power conversion device (100; 100A; 100B) according to a sixth aspect includes a switching element drive circuit (2; 2A; 2B) according to any one of the first to fifth aspects and a plurality of T-type three-level inverters (1).

[0138] According to this aspect, it is possible to suppress a decrease in the voltage (VC1) of the first capacitor (C1) of each of the plurality of first bootstrap circuits (71) and the voltage (VC2) of the second capacitor (C2) of each of the plurality of second bootstrap circuits (72).

[0139] In the power conversion device (100; 100A; 100B) according to the seventh aspect, in the sixth aspect, each of the plurality of first switching elements (Q1), the plurality of second switching elements (Q2), the plurality of third switching elements (Q3), and the plurality of fourth switching elements (Q4) is an insulated gate bipolar transistor, a MOSFET, or a gate injection transistor.

[0140] REFERENCE SIGNS LIST 1 T-type three-level inverter (inverter circuit) 2, 2A, 2B Switching element drive circuit 3 DC power supply unit 4 Control device 5 Auxiliary circuit 51 AND element 6 DC voltage source 61 First gate driver 62 Second gate driver 63 Third gate driver 64 Fourth gate driver 65 Fifth gate driver 13 Output point 71 First bootstrap circuit 72 Second bootstrap circuit 73 Third bootstrap circuit 100, 100A, 100B Power conversion device C1 First capacitor C2 Second capacitor C3 Third capacitor D6 First diode D7 Second diode D8 Third diode D11 Diode (bootstrap diode) M1 Midpoint potential point N1 Negative pole P1 Positive pole Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element Q5 Fifth switching element S1 First control signal S2: Second control signal S3: Third control signal S4: Fourth control signal S5: Fifth control signal

Claims

1. A switching element drive circuit for driving a plurality of T-type three-level inverters, wherein the plurality of T-type three-level inverters comprise: a plurality of first switching elements connected to the positive electrode of a DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point; a plurality of second switching elements connected in series to the plurality of first switching elements respectively and connected to the negative electrode; a plurality of third switching elements connected to the intermediate potential point; and a plurality of fourth switching elements connected in series to the plurality of third switching elements respectively and connected to output points of corresponding T-type three-level inverters among the plurality of T-type three-level inverters, wherein the switching element drive circuit comprises: a plurality of first gate drivers for driving the plurality of first switching elements respectively; a plurality of second gate drivers for driving the plurality of second switching elements respectively; a plurality of third gate drivers for driving the plurality of third switching elements respectively; a plurality of fourth gate drivers for driving the plurality of fourth switching elements respectively; a plurality of first bootstrap circuits each corresponding to the plurality of first gate drivers and including first capacitors connected in parallel to the corresponding first gate drivers; the plurality of second bootstrap circuits each including a second capacitor connected in parallel to a corresponding third gate driver among the plurality of third gate drivers and a corresponding fourth gate driver among the plurality of fourth gate drivers; a DC voltage source connected in parallel to the plurality of second gate drivers; a control device that outputs a plurality of first control signals, a plurality of second control signals, a plurality of third control signals and a plurality of fourth control signals to be provided to the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers and the plurality of fourth gate drivers, respectively; and an auxiliary circuit connected to the plurality of second bootstrap circuits, wherein each of the plurality of first bootstrap circuits further includes a bootstrap diode having a cathode connected to the high potential end of the first capacitor and an anode connected to the high potential end of the second capacitor of a corresponding second bootstrap circuit among the plurality of second bootstrap circuits,the auxiliary circuit includes: a fifth switching element having a first main terminal, a second main terminal, and a gate terminal, the first main terminal being connected to the intermediate potential point; a fifth gate driver connected to the gate terminal and the second main terminal of the fifth switching element and driving the fifth switching element; a third capacitor connected in parallel to the fifth gate driver; a first diode having a first cathode connected to a high potential end of the third capacitor and a first anode connected to a positive terminal of the DC voltage source; a plurality of second diodes having second cathodes connected to the high potential ends of the second capacitors of the plurality of second bootstrap circuits and second anodes connected to the high potential end of the third capacitor; and a plurality of third diodes having third cathodes connected to low potential ends of the second capacitors of the plurality of second bootstrap circuits and third anodes connected to the low potential end of the third capacitor.

2. The switching element drive circuit according to claim 1, wherein the auxiliary circuit further includes an AND element having a plurality of input terminals and an output terminal, the plurality of input terminals being connected to the control device and the output terminal being connected to the fifth gate driver, and the plurality of third control signals are input to the plurality of input terminals of the AND element.

3. The switching element drive circuit according to claim 1 or 2, wherein the control device generates the plurality of first control signals, the plurality of second control signals, the plurality of third control signals, and the plurality of fourth control signals by space vector modulation.

4. The switching element drive circuit according to claim 1 or 2, wherein the control device generates the plurality of first control signals, the plurality of second control signals, the plurality of third control signals, and the plurality of fourth control signals by triangular wave PWM control.

5. A switching element drive circuit according to any one of claims 1 to 4, wherein the fifth switching element is an insulated gate bipolar transistor, a MOSFET, or a gate injection transistor.

6. A power conversion device comprising: the switching element drive circuit according to any one of claims 1 to 5; and a plurality of T-type three-level inverters.

7. The power conversion device according to claim 6, wherein each of the plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, and the plurality of fourth switching elements is an insulated gate bipolar transistor, a MOSFET, or a gate injection transistor.

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