Stacked memory and integrated module

Abstract

Provided are a stacked memory that can cope with heat generated by the stacked memory, and an integrated module in which the same is used. A stacked memory 10 is configured by providing a memory controller 11, a first memory part 12 configured from one or more first memory dies 12a, and a second memory part 13 configured from one or more second memory dies 13a, in the stated order. The first memory part 12 does not include any second memory die, and the second memory part 13 does not include any first memory die. The first memory die 12a is superior to the second memory die 13a in terms of at least one of heat resistance, read power, and power consumption.

Description

Stacked Memory and Integrated Modules

[0001] The present invention relates to stacked memories and integrated modules.

[0002] High Bandwidth Memory (HBM) is a stacked memory composed of multiple DRAM (Dynamic Random Access Memory) dies. It is used in conjunction with a CPU (Central Processing Unit) or GPU (Graphics Processing Unit). HBM uses 3D stacking technology to vertically stack memory chips, resulting in a high-density, compact module. Furthermore, a silicon interposer is used to connect the memory chips to the processor, achieving high-speed data transfer and low latency. Because of its extremely high bandwidth, HBM can process large amounts of data quickly, demonstrating excellent performance, especially in graphics processing and high-performance computing. It also consumes less power and is more energy efficient than conventional memory technologies.

[0003] HBM also plays an important role in AI (Artificial Intelligence) applications such as neural networks and machine learning. Training and inference of AI models requires massive amounts of data, which requires fast and efficient memory access. HBM's high bandwidth and low latency make it ideal for performing these AI processes quickly and effectively. HBM is widely used in high-performance graphics cards, supercomputers, and dedicated AI hardware.

[0004] The technology of stacking one or more logic dies and HBM dies on an interposer for implementation is known as 2.5D HBM. Patent Document 1 discloses an intelligent high-bandwidth memory system. Specifically, the intelligent high-bandwidth memory system includes a first HBM stack, a host (CPU or GPU), a second HBM stack, and an interposer. The interposer connects the first HBM stack, the host, and the second HBM stack, and the second HBM stack is disposed on both the left and right sides of the first HBM stack and the host. One HBM stack is constructed by stacking multiple HBM modules on a logic die.

[0005] Patent Document 2 discloses a technology for stacking multiple DRAMs and SOCs (System on Chip) within a single integrated circuit package. Specifically, a first DRAM die and a second DRAM die are provided on a first package substrate, a third DRAM die and a fourth DRAM die are provided on a second package substrate, and the third and fourth DRAM dies are vertically stacked on top of the first and second DRAM dies. A fifth and sixth DRAM die are disposed on top of the third and fourth DRAM dies. A heat sink is disposed above the fifth and sixth DRAM dies with a heat spreader interposed therebetween.

[0006] US2019 / 0050325A1WO2013 / 028745

[0007] In conventional stacked memories such as HBMs, which are constructed by stacking multiple DRAMs, the temperature rise of the stacked memory has been suppressed by arranging the stacked memory alongside the CPU or GPU as in Patent Document 1, or by providing a heat sink to the CPU or GPU as in Patent Document 2, in order to deal with heat generated from logic dies such as a CPU or GPU.

[0008] As the amount of data going in and out of stacked memory and the data transfer rate increase, heat generated by the stacked memory itself becomes a problem, specifically heat generated by the memory controller or the memory die itself.

[0009] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a stacked memory that can cope with heat generated from the stacked memory, and an integrated module using the same.

[0010] The present invention has the following concepts. [1] A stacked memory comprising: a memory controller; a first memory unit comprising one or more first memory dies; and a second memory unit comprising one or more second memory dies, arranged in this order; the first memory unit does not include the second memory die, and the second memory unit does not include the first memory die, and the first memory die is superior to the second memory die in at least one of heat resistance, read power, and power consumption. [2] The stacked memory according to [1], in which the first memory unit and the second memory unit are arranged repeatedly in this order. [3] The stacked memory according to [2], in which the number of first memory dies included in the first memory unit is equal to or greater than the number of second memory dies included in the second memory unit. [4] The stacked memory according to any one of [1] to [3], in which the first memory die and the second memory die are connected by through-wiring. [5] The stacked memory according to any one of [1] to [4], wherein the first memory die is an MRAM die, and the second memory die is a DRAM die. [6] The stacked memory according to any one of [1] to [5], wherein the stacked memory is for an integrated module having a certain maximum bandwidth per stack formed by stacking the first memory unit and the second memory unit, the certain maximum bandwidth being 256 GB / s or more. [7] An integrated module comprising: the stacked memory according to any one of [1] to [5]; and a logic die. [8] The integrated module according to [7], wherein the first memory die is configured to store weight coefficients that are input to the logic die and required for inference in an AI model, and the second memory die is configured to store input data that is input to the logic die and required for inference in the AI ​​model. [9] The integrated module according to [7] or [8], wherein the stacked memory is arranged vertically or horizontally with the logic die, and the stacked memory is wired to the logic die.

[10] The integrated module according to any one of [7] to [9], wherein each stack formed by stacking the first memory unit and the second memory unit has a bandwidth of a certain maximum value, and the certain maximum value is 256 GB / s or more.

[0011] According to the present invention, the first memory die is superior to the second memory die in at least one of heat resistance, read power, and power consumption, and the first memory section is disposed closer to the memory controller than the second memory section, thereby providing a stacked memory that can cope with heat generated from the stacked memory and an integrated module using the same.

[0012] FIG. 1A is a diagram schematically illustrating a stacked memory according to a first embodiment of the present invention. FIG. 1B is a diagram schematically illustrating a stacked memory according to a first embodiment of the present invention, different from FIG. 1A. FIG. 1C is a diagram schematically illustrating a stacked memory according to a first embodiment of the present invention, different from FIGS. 1A and 1B. FIG. 1D is a diagram schematically illustrating a stacked memory according to a first embodiment of the present invention, different from FIGS. 1A to 1C. FIG. 2A is a diagram schematically illustrating a stacked memory according to a second embodiment of the present invention. FIG. 2B is a diagram schematically illustrating a stacked memory according to a second embodiment of the present invention, different from FIG. 2A. FIG. 2C is a diagram schematically illustrating a stacked memory according to a second embodiment of the present invention, which is a modification of FIG. 2B. FIG. 2D is a diagram schematically illustrating a stacked memory according to a second embodiment of the present invention, which is different from FIGS. 2A to 2C. FIG. 2E is a diagram schematically illustrating a stacked memory according to a second embodiment of the present invention, which is a modification of FIG. 2D. FIG. 2F is a diagram generally schematically illustrating a stacked memory according to a second embodiment of the present invention. FIG. 3A is a diagram schematically illustrating a stacked memory according to a specific embodiment of the present invention. FIG. 3B is a diagram schematically illustrating a stacked memory according to a specific embodiment of the present invention, different from FIG. 3A . FIG. 3C is a plan view schematically illustrating a stacked memory according to a specific embodiment of the present invention, different from FIGS. 3A and 3B . FIG. 4 is a diagram schematically illustrating an integrated module according to a third embodiment of the present invention. FIG. 5A is a diagram schematically illustrating an integrated module according to a fourth embodiment of the present invention. FIG. 5B is a detailed view of FIG. 5A . FIG. 5C is a detailed view of FIG. 5A , different from FIG. 5B . FIG. 6 is a conceptual diagram illustrating a scheme of an AI system (AI model) realized as a fifth embodiment. FIG. 7 is a diagram schematically illustrating a specific example of the stacked memory according to the first embodiment. FIG. 8 is a diagram schematically illustrating a specific example of the stacked memory according to the first embodiment, different from FIG. 7 . FIG. 9 is a diagram schematically illustrating a specific example of the stacked memory according to the first embodiment, different from FIGS. 7 and 8 . FIG. 10 is a diagram schematically illustrating a specific example of the stacked memory according to the first embodiment, different from FIGS. 7 to 9 . FIG. 11 is a diagram schematically showing a specific example of the stacked memory according to the first embodiment, which is different from FIGS. 7 to 10. In FIG.FIG. 12 is a diagram schematically illustrating a specific example of the stacked memory according to the first embodiment, which is different from FIGS. 7 to 11 . FIG. 13 is a diagram schematically illustrating a modified example of the stacked memory according to the second embodiment. FIG. 14 is a diagram schematically illustrating a specific example of the stacked memory according to the second embodiment. FIG. 15 is a diagram schematically illustrating a specific example of the stacked memory according to the second embodiment, which is different from FIG. 14 . FIG. 16 is a diagram schematically illustrating a specific example of the stacked memory according to the second embodiment, which is different from FIGS. 14 and 15 . FIG. 17 is a diagram schematically illustrating a specific example of the stacked memory according to the second embodiment, which is different from FIGS. 14 to 16 . FIG. 18 is a diagram schematically illustrating a modified example of the stacked memory according to the second embodiment, which is different from FIG. 13 . FIG. 19 is a diagram schematically illustrating a stacked memory according to a sixth embodiment of the present invention. FIG. 20 is a diagram schematically illustrating a stacked memory according to a seventh embodiment of the present invention. FIG. 21 is a diagram schematically illustrating a stacked memory according to an eighth embodiment of the present invention.

[0013] Hereinafter, several embodiments of the present invention will be described in detail with reference to the drawings. The matters described in the embodiments of the present invention can be appropriately modified in design without changing the scope of the present invention.

[0014] 1A is a diagram schematically illustrating a stacked memory 10 according to a first embodiment of the present invention. The stacked memory 10 is configured by providing a memory controller 11, a first memory unit 12, and a second memory unit 13 in this order. That is, in the stacked memory 10, the memory controller 11 is provided on a first surface of the first memory unit 12, and the second memory unit 13 is provided on a second surface that is different in the thickness direction from the first surface of the first memory unit 12.

[0015] The memory controller 11 is configured to control data flow to and from the first memory unit 12 and the second memory unit 13. The first memory unit 12 includes one or more first memory dies 12a. The second memory unit 13 includes one or more second memory dies 13a. In FIG. 1A, the first memory unit 12 includes four first memory dies 12a, and the second memory unit 13 includes four second memory dies 13a. As described below, the first memory unit 12 may include one first memory die 12a, and the second memory unit 13 may include one second memory die 13a (see FIG. 7).

[0016] In the first embodiment of the present invention, the first memory die 12a is characterized by being superior to the second memory die 13a in at least one of heat resistance, read power, and power consumption. Here, "heat resistance" refers to the ability of a memory module and its components to continue to operate normally even in a high-temperature environment. Specifically, it refers to the characteristic of a memory functioning stably within a certain temperature range without deformation, deterioration, or performance degradation due to heat. The memory module includes a stacked memory 10 and integrated modules 20 and 30, which will be described later. For example, if the error rate during memory operation is 10 －６ If the error rate during memory operation is less than 10, it can be determined that the memory is heat resistant. －７ If it is less than 10, it is more preferable －８ If it is less than 10, it is more preferable －９ If it is below this, it can be determined that it is heat resistant.

[0017] If the first memory die 12a has better heat resistance than the second memory die 13a, placing the first memory die 12a closer to the memory controller 11 can prevent degradation of memory function due to heat from the memory controller 11.

[0018] If the first memory die 12a has a smaller read power than the second memory die 13a, even if data is read for the same time, the amount of heat generated from the first memory die 12a will be smaller than that of the second memory die, and the first memory die 12a can suppress malfunctions of the memory controller 11 due to heat.

[0019] If the first memory die 12a has lower power consumption than the second memory die 13a, even if data processing is performed for the same time, the amount of heat generated from the first memory die 12a will be smaller than that of the second memory die 13a, and malfunctions of the first memory die 12a due to heat can be suppressed. Here, power consumption refers to power evaluated comprehensively from the number of read and write operations in the design specifications, taking into account the read power and write power.

[0020] In the first embodiment of the present invention, the first memory die 12a is superior to the second memory die 13a in at least one of heat resistance, read power, and power consumption, preferably in two aspects, and more preferably in three aspects.

[0021] Conventionally, in stacked memories configured by stacking multiple memory dies on a memory controller, in order to deal with heat generated from logic dies such as a CPU or GPU, the stacked memory has been placed alongside the CPU or GPU, or a heat sink has been provided on the CPU or GPU to suppress temperature increases in the stacked memory due to the CPU or GPU.

[0022] In the first embodiment of the present invention, including the embodiments described later, a first memory die 12a is located near the memory controller 11, and a second memory die 13a is stacked on the first memory die 12a. The first memory die 12a is superior to the second memory die 13a in at least one of heat resistance, read power, and power consumption.

[0023] Therefore, even if the stacked memory 10, i.e., the stacked memory 10 configured by stacking one or more first memory dies 12a and one or more second memory dies 13a relative to the memory controller 11, is designed to have a large amount of data input and output and a large data transfer rate, it can accommodate heat generated by the memory controller 11, and there is little chance of any limitations being placed on the amount of data or the data transfer rate.

[0024] 1A illustrates a case where the number of first memory dies 12a in the first memory unit 12 is the same as the number of second memory dies 13a in the second memory unit 13. The number is arbitrary.

[0025] 1B is a schematic diagram illustrating a stacked memory 10 according to a first embodiment of the present invention, which is different from FIG. 1A . Unlike FIG. 1A , the stacked memory 10 illustrated in FIG. 1B has a larger number of second memory dies 13a in the second memory unit 13 than the number of first memory dies 12a in the first memory unit 12. As long as this condition is met, the number of first memory dies 12a in the first memory unit 12 and the number of second memory dies 13a in the second memory unit 13 are both arbitrary. In FIG. 1B , the first memory unit 12 includes two first memory dies 12a, and the second memory unit 13 includes four second memory dies 13a.

[0026] 1A and 1B , the stacked memory 10 according to the first embodiment of the present invention is different from the stacked memory 10 shown in FIG. 1C . Unlike the stacked memory 10 shown in FIG. 1A and 1B , the number of second memory dies 13a in the second memory unit 13 is less than the number of first memory dies 12a in the first memory unit 12. As long as this condition is met, the number of first memory dies 12a in the first memory unit 12 and the number of second memory dies 13a in the second memory unit 13 are both arbitrary. In FIG. 1C , the first memory unit 12 includes four first memory dies 12a, and the second memory unit 13 includes two second memory dies 13a.

[0027] 1A to 1C, a stacked memory 10 is configured by providing a memory controller 11, a first memory unit 12, and a second memory unit 13 in this order. That is, in the stacked memory 10, the memory controller 11 is provided on a first surface of the first memory unit 12, and the second memory unit 13 is provided on a second surface that is different in the thickness direction from the first surface of the first memory unit 12.

[0028] The memory controller 11 is configured to control data flowing in and out of the first memory unit 12 and the second memory unit 13. The first memory unit 12 includes one or more first memory dies 12a. The second memory unit 13 includes one or more second memory dies 13a.

[0029] As already described, in the stacked memory 10 according to the first embodiment, the first memory die 12a is superior to the second memory die 13a in at least one of heat resistance, read power, and power consumption, preferably in two of the three aspects, and more preferably in all three aspects.

[0030] 1A, the number of first memory dies 12a in the first memory unit 12 may be the same as the number of second memory dies 13a in the second memory unit 13, as shown in FIG. 1B, the number of second memory dies 13a in the second memory unit 13 may be greater than the number of first memory dies 12a in the first memory unit 12, or as shown in FIG. 1C, the number of second memory dies 13a in the second memory unit 13 may be less than the number of first memory dies 12a in the first memory unit 12. As long as the relevant conditions are met, the number of first memory dies 12a in the first memory unit 12 and the number of second memory dies 13a in the second memory unit 13 are each arbitrary.

[0031] As shown in FIG. 1D , the stacked memory 10 according to the first embodiment includes a memory controller 11, a first memory unit 12, and a second memory unit 13. A third memory unit 14 may be provided on the second memory unit 13 sandwiched between the first memory unit 12, as shown in FIG. 1A to FIG. 1C . The third memory unit 14 may be of a different type from the first memory die 12a of the first memory unit 12 and the second memory die 13a of the second memory unit 13. The number of memory dies constituting each of the first memory unit 12, the second memory unit 13, and the third memory unit 14 may be any number. A fourth memory unit may be provided on the third memory unit 14.

[0032] Second Embodiment In the second embodiment, the first memory unit 12 and the second memory unit 13 in the first embodiment are provided repeatedly in this order. The number of repetitions is arbitrary.

[0033] The number of first memory dies 12 a included in the first memory unit 12 does not need to depend on the number of second memory dies 13 a included in the second memory unit 13 .

[0034] 2A is a diagram schematically illustrating a stacked memory 10 according to a second embodiment of the present invention. The stacked memory 10 is configured by providing a memory controller 11, a first memory unit 12, a second memory unit 13, and a first memory unit 12 and a second memory unit 13 in this order. That is, the first memory unit 12 and the second memory unit 13 are repeatedly provided in one direction of the memory controller 11 (above in the drawing). FIG. 2A illustrates a case where the repetition is two times.

[0035] The first memory section 12 includes one or more first memory dies 12a, and the second memory section 13 includes one or more second memory dies 13a.

[0036] In the second embodiment of the present invention, similarly to the first embodiment, the first memory die 12a is characterized by being superior to the second memory die 13a in at least one of heat resistance, read power, and power consumption, preferably in two of these aspects, and more preferably in three of these aspects, as explained in the first embodiment and will not be repeated here.

[0037] The first memory die 12a constituting the first memory unit 12 is superior to the second memory die 13a constituting the second memory unit 13 in at least one of heat resistance, read power, and power consumption. The stacked memory 10 is provided with a first memory unit 12 including one or more first memory dies 12a and a second memory unit 13 including one or more second memory dies 13a, arranged in an alternating pattern. As a result, when the stacked memory 10 is viewed as a whole, the number of dies in each of the first memory unit 12 and the second memory unit 13 can be adjusted depending on the amount of heat generated in the first memory unit 12 and the amount of heat generated in the second memory unit 13. This allows the balance of heat accumulation within the stack of the stacked memory 10 to be adjusted.

[0038] 2A , the number of second memory dies 13a in the second memory unit 13 is greater than the number of first memory dies 12a in the first memory unit 12. As long as this condition is met, the number of first memory dies 12a in the first memory unit 12 and the number of second memory dies 13a in the second memory unit 13 are each arbitrary. In FIG. 2A , each first memory unit 12 includes one first memory die 12a, and each second memory unit 13 includes two second memory dies 13a.

[0039] 2B is a diagram schematically illustrating a stacked memory 10 according to a second embodiment of the present invention, which is different from that of FIG. 2A. Similar to FIG. 2A, the stacked memory 10 illustrated in FIG. 2B includes a memory controller 11, a first memory unit 12, a second memory unit 13, and a first memory unit 12 and a second memory unit 13, arranged in this order. The number of repetitions of the first memory unit 12 and the second memory unit 13 is two.

[0040] 2B , the number of second memory dies 13 a in the second memory unit 13 is the same as the number of first memory dies 12 a in the first memory unit 12, and the number of second memory dies 13 a in the second memory unit 13 is arbitrary. In FIG. 2B , the number of first memory dies 12 a in the first memory unit 12 and the number of second memory dies 13 a in the second memory unit 13 are one.

[0041] 2C is a modified example of FIG. 2B and is a diagram schematically illustrating a stacked memory 10 according to a second embodiment of the present invention. The stacked memory 10 is configured by a memory controller 11, a first memory unit 12, a second memory unit 13, a first memory unit 12, a second memory unit 13, a first memory unit 12, a second memory unit 13, and a first memory unit 12, a second memory unit 13, all arranged in this order. In other words, the stacked memory 10 is configured by repeating the first memory unit 12 and the second memory unit 13 in one direction (above in the illustrated example) of one memory controller 11. The number of repetitions of the first memory unit 12 and the second memory unit 13 is four.

[0042] 2A to 2C , the stacked memory 10 shown in FIG. 2D is a diagram schematically illustrating a stacked memory 10 according to a second embodiment of the present invention. Similar to the stacked memory 10 shown in FIG. 2A to 2C , the stacked memory 10 shown in FIG. 2D includes a memory controller 11, a first memory unit 12, a second memory unit 13, and a first memory unit 12 and a second memory unit 13, arranged in this order. The number of repetitions of the first memory unit 12 and the second memory unit 13 is two.

[0043] In the stacked memory 10 shown in Figure 2D, the number of second memory dies 13a in the second memory unit 13 is less than the number of first memory dies 12a in the first memory unit 12. As long as this condition is met, the number of first memory dies 12a in the first memory unit 12 and the number of second memory dies 13a in the second memory unit 13 are each arbitrary. In Figure 2D, the number of first memory dies 12a in the first memory unit 12 is two, and the number of second memory die 13a in the second memory unit 13 is one.

[0044] 2E is a modified example of FIG. 2D and is a diagram schematically illustrating a stacked memory 10 according to a second embodiment of the present invention. The stacked memory 10 is configured by providing a memory controller 11, a first memory unit 12, a second memory unit 13, a first memory unit 12, a second memory unit 13, a first memory unit 12, a second memory unit 13, and a first memory unit 12, a second memory unit 13, in this order. In other words, in the stacked memory 10, the first memory unit 12 and the second memory unit 13 are repeated in one direction (upward in the illustrated example) of one memory controller 11, and the number of repetitions is four.

[0045] In the stacked memory 10 shown in Figure 2E, the number of second memory dies 13a in the second memory unit 13 is less than the number of first memory dies 12a in the first memory unit 12. As long as this condition is met, the number of first memory dies 12a in the first memory unit 12 and the number of second memory dies 13a in the second memory unit 13 are each arbitrary. In Figure 2E, the number of first memory dies 12a in the first memory unit 12 is two, and the number of second memory die 13a in the second memory unit 13 is one.

[0046] 2A to 2E , in a second embodiment of the present invention, a stacked memory 10 is configured by repeatedly arranging first memory units 12 and second memory units 13 in one direction (above in the illustrated example) of a single memory controller 11. When viewed in units of the first memory die 12a constituting the first memory unit 12 and the second memory die 13a constituting the second memory unit 13, one or more first memory dies 12a and one or more second memory dies 13a are repeatedly arranged in a periodic structure. By adjusting the ratio between the number of first memory dies 12a and the number of second memory dies 13a, the balance of heat accumulation within the stack of the stacked memory 10 can be adjusted.

[0047] The ratio of the number of first memory dies 12a to the number of second memory dies 13a is 1:2 in Figure 2A, 1:1 in Figures 2B and 2C, and 2:1 in Figures 2D and 2E. This ratio is set arbitrarily.

[0048] A second embodiment will now be generally described with reference to Figures 2A to 2E. Figure 2F is a diagram generally illustrating a stacked memory according to a second embodiment of the present invention. The stacked memory 10 according to the second embodiment includes a memory controller 11, a first memory unit 12 including one or more first memory dies, and a second memory unit 13 including one or more second memory dies, arranged in this order, with the first memory unit 12 and the second memory unit 13 being arranged repeatedly in this order. The first memory unit 12 and the second memory unit 13 may be repeated any number of times. The first memory unit 12 includes any number of first memory dies 12a. The second memory unit 13 includes any number of second memory dies 13a.

[0049] The plurality of first memory units 12 may each include the same number of first memory dies 12a, or may each include a different number of first memory dies 12a.

[0050] The plurality of second memory units 13 may each include the same number of second memory dies 13a, or may each include a different number of second memory dies 13a.

[0051] 2F, the stacked memory 10 according to the second embodiment is configured by repeatedly providing a first memory unit 12 and a second memory unit 13 in this order on a memory controller 11. Counting from the memory controller 11, the first memory unit 12 (12A) and the second memory unit 13 (13A) are provided in the first repetition, then the first memory unit 12 (12B) and the second memory unit 13 (13B) are provided in the second repetition, and then the first memory unit 12 (12C) and the second memory unit 13 (13C) are provided in the third repetition.

[0052] The first memory section 12 (12B) in the second repetition may include the same number of first memory dies 12a as the first memory section 12 (12A) in the first repetition, or may include a different number of first memory dies 12a than the first memory dies 12a included in the first memory section 12 (12A) in the first repetition.

[0053] The second memory section 13 (13B) in the second repetition may include the same number of second memory dies 13a as the second memory section 13 (13A) in the first repetition, or may include a different number of second memory dies 13a than the second memory dies 13a included in the second memory section 13 (13A) in the first repetition.

[0054] The number of first memory dies 12 a in a certain first memory unit 12 (e.g., first memory unit 12C) in the third or later repetition may be the same as or different from the number of first memory dies 12 a in the previous first memory unit 12 (e.g., first memory unit 12B). The number of second memory dies 13 a in a certain second memory unit 13 (e.g., second memory unit 13C) in the third or later repetition may be the same as or different from the number of second memory dies 13 a in the previous second memory unit 13 (e.g., second memory unit 13B).

[0055] <First Item Common to the First and Second Embodiments> Next, the connection between memory dies will be described. This applies to both the first and second embodiments, but will be described in the case of the first embodiment. Those skilled in the art will easily understand that this also applies to the second embodiment.

[0056] 3A is a schematic diagram illustrating a stacked memory 10 according to a specific embodiment of the present invention. The stacked memory 10 is characterized in that one or more first memory dies 12a in the first memory portion 12 and one or more second memory dies 13a in the second memory portion 13 are connected to each other by through-holes 15. The through-holes 15 in each die may be connected in any manner as long as they are connected. The through-holes 15 in a given memory die are not limited to being connected to the through-holes 15 in an adjacent memory die above by microbumps or to the through-holes 15 in an adjacent memory die below by microbumps. This increases the data transfer speed between the first memory dies 12a in the first memory portion 12, between the second memory dies in the second memory portion 13, and between the first memory die 12a and the second memory die 13a.

[0057] <Second Item Common to the First and Second Embodiments> In the configuration shown in FIG. 3B , the top surface of the second memory unit 13 (the surface facing the opposite direction in the stacking direction to the surface facing the first memory unit 12) in the configuration shown in FIG. 3A is the surface on which the heat sink 17 is mounted. A cooler such as the heat sink 17 is disposed on the top surface of the second memory unit 13, if necessary, via a layer 16 made of a thermal interface material (TMI). The through wiring 15 is preferably configured so that its top end reaches the layer 16 made of the thermal interface material. Heat generated in the memory controller 11 is transferred to the top end of the through wiring 15 via the through wiring 15, spreads in a planar form by the layer 16 made of the thermal interface material, and is dissipated by a cooler such as the heat sink 17.

[0058] The through wires 15 connect adjacent memory dies in the vertical stacking direction and electrically connect the internal wiring of adjacent memory dies. In addition to these through wires 15, a plurality of through wires 15 for heat transfer may be separately provided, and the through wires 15 for heat transfer may connect adjacent memory dies in the vertical stacking direction but may not electrically connect the internal wiring of adjacent memory dies.

[0059] Depending on the specifications of the stacked memory 10, the through wirings 15 may be arranged in the vertical direction so that at least the lower ends of the through wirings 15 reach the upper surface of the memory controller 11 (the surface adjacent to the first memory unit 12), regardless of whether they are for heat transfer or not. In this case, a cooler such as a heat sink 17 may or may not be provided. The upper ends of the through wirings 15 may reach the upper surface of the stacked memory 10.

[0060] 3C is a plan view schematically illustrating a stacked memory 10 according to a specific embodiment of the present invention. As shown in FIG. 3C , a plurality of through-holes 15a extending in the stacking direction may be arranged along the entire periphery of the outer periphery of the second memory unit 13 in a plan view, so that the stacked memory 10 is cooled from the left, right, front, rear, and / or right. Of course, a plurality of through-holes 15a may be arranged along at least one of the front, rear, left, and / or right surfaces, rather than along the entire periphery of the outer periphery of the second memory unit 13 in a plan view, so that the stacked memory 10 is cooled from at least one of the front, rear, left, and / or right surfaces. The plurality of through-holes 15a do not need to be arranged from one end to the other on one of the front, rear, left, or right surfaces.

[0061] <Third Item Common to the First and Second Embodiments> In the stacked memory 10 according to the first and second embodiments, the first memory die 12 a of the first memory unit 12 is a Magnetoresistive Random Access Memory (MRAM) die, and the second memory die 13 a of the second memory unit 13 is a DRAM die.

[0062] It is known that DRAM dies are more likely to lose their memory function at temperatures of approximately 85° C. In contrast, MRAM dies have higher heat resistance than DRAM dies. Specifically, MRAM dies can withstand temperatures of approximately 120° C. or higher.

[0063] 4 is a diagram schematically illustrating an integrated module 20 according to a third embodiment of the present invention. The integrated module 20 includes a wiring connection board 22 provided on a substrate (e.g., a package substrate) 21, and a stacked memory 10 and a logic die 23 arranged horizontally on the wiring connection board 22. A heat sink (not shown) may be provided on the logic die 23 on the surface opposite to the surface facing the stacked memory 10.

[0064] More specifically, integrated module 20 has wiring 22a provided within wiring connection substrate 22, and wiring 22a connects logic die 23 and memory controller 11 of stacked memory 10 via solder balls 24a and 24b, respectively, enabling high-speed data transfer between logic die 23 and stacked memory 10. Substrate 21 and wiring connection substrate 22 are connected via solder balls 25, and substrate 21 is further connected to the outside via solder balls 26, enabling data input / output, power input, and signal line connections to the outside of integrated module 20.

[0065] In the integrated module 20 shown in FIG. 4, the logic die 23 does not overlap the stacked memories 10 in a top view, so that only the logic die 23 can be cooled by air cooling or the like.

[0066] The logic die 23 performs logical operation processing of data in the stacked memory 10. The logic die 23 includes a CPU, an application specific integrated circuit (ASIC), a GPU, a field programmable gate array (FPGA), or the like as a microprocessor.

[0067] The stacked memory 10 in the integrated module 20 shown in FIG. 4 has the configuration shown in FIG. 1, but the present invention is applicable to any of the stacked memories 10 described above or below.

[0068] 5A is a schematic diagram illustrating an integrated module 30 according to a fourth embodiment of the present invention. The integrated module 30 is configured by stacking stacked memories 10 and logic die 33 on a substrate (e.g., a package substrate) 31, with a wiring connection substrate (not shown) provided as needed. The stacked memories 10 and logic die 33 are arranged side by side in the vertical direction. A heat sink 37 may be provided on the surface of the logic die 33 opposite the surface facing the stacked memories 10 to facilitate heat dissipation from the logic die 33.

[0069] More specifically, in the integrated module 30, a logic die 33 is provided on the top surface (first surface) of the stacked memory 10, and the stacked memory 10 and the logic die 33 are connected by through-wires 35. This configuration allows high-speed data transfer between the logic die 33 and the stacked memory 10.

[0070] 5B is a detailed view of FIG. 5A. The stacked memory 10 is configured by stacking a memory controller 11, a first memory unit 12, and a second memory unit 13 in this order, and a logic die 33 is further stacked on the second memory unit 13. A heat sink 37 may be provided on the surface of the logic die 33 opposite to the surface facing the stacked memory 10 to facilitate heat dissipation from the logic die 33.

[0071] 5A and 5B , in the integrated module 30 according to the fourth embodiment, the through wiring 35 is coupled to the substrate 31 by the solder balls 32, and the substrate 31 is electrically connected to the outside by the solder balls 36. A wire, a clip, or the like may be provided between the logic die 33 and the substrate 31.

[0072] The logic die 33 performs logical operation processing of data in the stacked memory 10. The logic die 33 includes a CPU, an ASIC, a GPU, an FPGA, or the like as a microprocessor.

[0073] 5C is a detailed view of FIG. 5A that differs from FIG. 5B. The stacked memory 10 is configured by stacking the second memory unit 13, the first memory unit 12, and the memory controller 11 in this order, and the logic die 33 is further stacked on the memory controller 11. In the configuration shown in FIG. 5C, the memory controller 11, the first memory unit 12, and the second memory unit 13 are also provided facing downward in this order. A heat sink 37 may be provided on the surface of the logic die 33 opposite the surface facing the stacked memory 10. This is to facilitate heat dissipation from the logic die 33.

[0074] In the integrated module 30 according to the fourth embodiment, as shown in FIGS. 5A and 5C, the through wiring 35 is coupled to the substrate 31 by the solder balls 32, and the substrate 31 is electrically connected to the outside by the solder balls 36.

[0075] The logic die 33 performs logical operation processing of data in the stacked memory 10. The logic die 33 includes a CPU, an ASIC, a GPU, an FPGA, or the like as a microprocessor.

[0076] A heat sink 37 facilitates the dissipation of heat from the logic die 33 and the memory controller 11. The logic die 33 and the memory controller 11 do not need to be separate and may be a single die. In this case, the processing of the memory controller 11 includes the processing of the logic die 33, or conversely, the processing of the logic die 33 includes the processing of the memory controller 11.

[0077] The stacked memory 10 in the integrated module 30 shown in FIG. 5C is a configuration in which the configuration shown in FIG. 1A is turned upside down, but this configuration is applicable to any of the stacked memories 10 described above or below.

[0078] Fifth Embodiment An AI system implemented in the integrated module 20 according to the third embodiment and the integrated module 30 according to the fourth embodiment will be described. FIG. 6 is a conceptual diagram of the scheme of an AI system (AI model) implemented as the fifth embodiment. The AI ​​system uses, for example, a neural network 40 as follows. The neural network is composed of an input layer 41, an intermediate layer 42, and an output layer 43. The input layer 41, the intermediate layer 42, and the output layer 43 each comprise a plurality of neurons, which are connected by synapses from the input layer 41 through the intermediate layer 42 to the output layer 43. Various types of data, such as images, videos, audio, and text, are input to each neuron in the input layer 41. At least two processes are performed in the intermediate layer 42. The first process multiplies the output value of a neuron from the previous layer by its corresponding weighting coefficient, and the resulting sum is calculated as a weighted sum. Of course, a bias value or other calculation may also be added. The second process passes the calculated weighted sum through an activation function, and the output value is transmitted to the next layer as the final output value. These two processes are repeated until the output layer 43 is reached. The output layer 43 outputs the value input from the nearest intermediate layer.

[0079] Here, in the AI ​​system, once learning is completed, the weighting coefficients are not frequently rewritten, whereas the input data (data input to the first memory die 12a from outside the AI ​​system) is rewritten much more frequently than the weighting coefficients.

[0080] Therefore, the first memory die 12a is configured to store weight coefficients that are input to the logic dies 23 and 33 and are required for inference in the AI ​​model. The second memory die 13a is configured to store input data that is input to the logic die 33 and is required for inference in the AI ​​model. In this case, the first memory die 12a stores the weight coefficients in a manner that allows them to be rewritten by the logic dies 23 and 33.

[0081] The use of the stacked memory 10 according to the first embodiment makes it possible to cope with heat generated by the memory controller 11 and transmitted to the first memory unit 12 and the second memory unit 13. The use of the stacked memory 10 according to the second embodiment makes it possible to cope with heat generated by the first memory die 12a and the second memory die 13a (the first memory unit 12 and the second memory unit 13) themselves.

[0082] In the AI ​​system according to the fifth embodiment, the stacked memory 10 according to the first embodiment is employed, thereby making it possible to deal with heat generated by the memory controller 11 and applied to the first memory unit 12 and the second memory unit 13. That is, the first memory unit 12 and the second memory unit 13 are stacked, and the first memory die 12a in the first memory unit 12 is superior to the second memory die 13a in the second memory unit 13 in at least one of heat resistance, read power, and power consumption. Therefore, since the first memory die 12a is closer to the memory controller 11 and the logic die 33 than the second memory die 13a, it is possible to suppress degradation of memory function due to heat from the memory controller 11 and the logic die 33.

[0083] In the AI ​​system according to the fifth embodiment, the stacked memory 10 according to the second embodiment is employed, thereby making it possible to balance the heat accumulation of the first memory unit 12 and the second memory unit 13. It is possible to maintain a large amount of data and a high processing speed.

[0084] A system using the integrated module 20 according to the third embodiment of the present invention and the integrated module 30 according to the fourth embodiment of the present invention has a maximum bandwidth per stack formed by stacking the first memory section 12 and the second memory section 13, and this maximum bandwidth is 256 GB / s or more.

[0085] Here, bandwidth refers to the amount of data that a memory can process per unit time, specifically, the total amount of data transferred between a memory and a processor (e.g., a CPU, a GPU, etc.) per unit time.

[0086] Bandwidth is determined by the clock speed, the number of memory channels, the data rate, and the data bus width.

[0087] The clock speed is the rate at which the memory transfers data. For example, a memory operating at a 2 Gbps transfer rate transfers 2 gigabits of data per second.

[0088] The number of memory channels is the number of channels that the memory has between the processor and the memory, and each channel transfers data independently. For example, there are four or eight channels.

[0089] Data rate is the amount of data that each channel can transfer in one clock cycle. For example, in the case of DDR (Double Data Rate), two bits of data are transferred per clock cycle.

[0090] The width of the data bus is the bit width of each channel. For example, the width of the data bus per channel of the stacked memory is 128 bits.

[0091] In one embodiment of the present invention, bandwidth is calculated as follows: Bandwidth = Clock Speed ​​x Data Rate x Data Bus Width x Number of Memory Channels For example, if the clock speed is 1 Gbps, the data rate is 2 (for DDR), the data bus width is 128 bits, and the number of channels is 8, then: 1 Gbps x 2 x 128 bits x 8 channels = 2,048 Gbps = 256 GB / s In this way, systems using the integrated module 20 according to the fifth embodiment and the integrated module 30 according to the sixth embodiment of the present invention can exhibit significantly better performance than conventional memory technologies due to their wide bandwidth in applications requiring GPUs or high-speed data processing.

[0092] Each stack formed by stacking the first memory section 12 and the second memory section 13 has a maximum bandwidth, which is 256 GB / s, preferably 512 GB / s or more, and more preferably 1024 GB / s or more.

[0093] The stacked memory 10 according to the first and second embodiments of the present invention is for an integrated module, and by integrating it like the integrated module 20 according to the third embodiment of the present invention and the integrated module 30 according to the fourth embodiment of the present invention and transferring data with a processor, each stack formed by stacking the first memory unit 12 and the second memory unit 13 has a maximum bandwidth of 256 GB / s or more, preferably 512 GB / s or more, and more preferably 1024 GB / s or more.

[0094] In this specification, the first memory die 12a is superior in terms of heat resistance compared to the second memory die 13a if the first memory die 12a does not exceed the error rate standard (for example, 10 －６ It may also mean that the condition satisfies the following conditions.

[0095] Such a system can achieve data rates of 2 Gbps or higher, preferably 3.2 Gbps or higher.

[0096] <Specific Example of First Embodiment> In a first specific example of the first embodiment, the stacked memory 10 is configured by stacking a memory controller 11, a first memory unit 12, and a second memory unit 13 in this order.

[0097] 7 is a diagram schematically illustrating a specific example of the stacked memory 10 according to the first embodiment. The stacked memory 10 is configured by stacking one memory controller 11, one first memory die 12a, and one second memory die 13a in this order. That is, the first memory unit 12 includes one first memory die 12a, and the second memory unit 13 includes one second memory die 13a.

[0098] 8 is a diagram schematically illustrating a specific example of the stacked memory 10 according to the first embodiment, which is different from FIG. 7. The stacked memory 10 is configured by stacking one memory controller 11, two first memory dies 12a, and one second memory die 13a in this order. That is, the first memory unit 12 includes two first memory dies 12a, and the second memory unit 13 includes one second memory die 13a.

[0099] 9 is a diagram schematically illustrating a specific example of the stacked memory 10 according to the first embodiment, which is different from those in FIGS. 7 and 8. The stacked memory 10 is configured by stacking one memory controller 11, one first memory die 12a, and two second memory dies 13a in this order. That is, the first memory unit 12 includes one first memory die 12a, and the second memory unit 13 includes two second memory dies 13a.

[0100] 10 is a diagram schematically illustrating a specific example of the stacked memory 10 according to the first embodiment, which is different from those illustrated in FIGS. 7 to 9. The stacked memory 10 is configured by stacking one memory controller 11, two first memory dies 12a, and two second memory dies 13a in this order. That is, the first memory unit 12 includes two first memory dies 12a, and the second memory unit 13 includes two second memory dies 13a.

[0101] 11 is a diagram schematically illustrating a specific example of the stacked memory 10 according to the first embodiment, which is different from FIGS. 7 to 10 . The stacked memory 10 is configured by stacking one memory controller 11, N first memory dies 12a, and N second memory dies 13a in this order. That is, the first memory unit 12 includes N first memory dies 12a, and the second memory unit 13 includes N second memory dies 13a. Here, N is any natural number. FIG. 11 illustrates the case where N=3.

[0102] FIG. 12 is a schematic diagram illustrating a specific example of the stacked memory 10 according to the first embodiment, which is different from FIGS. 7 to 11 . The stacked memory 10 is configured by stacking one memory controller 11, K first memory dies 12a, L second memory dies 13a, and M third memory dies 14a in this order. Here, K, L, and M are any natural numbers satisfying the relationship K≧L≧M. That is, the first memory unit 12 includes K first memory dies 12a, the second memory unit 13 includes L second memory dies 13a, and the third memory unit 14 includes M third memory dies 14a. The diagram illustrates a case where K=4, L=3, and M=2. Alternatively, K=L=M=1 may be used. The first memory die 12a is superior to the second memory die 13a in at least one, preferably two, and more preferably all, of heat resistance, read power, and power consumption. 12, three types of memory dies are stacked. Four or more types of memory dies may be stacked. Furthermore, the closer the memory die is to the memory controller 11, the better it may be in at least one of heat resistance, read power, and power consumption, preferably in two of these, and more preferably in all of these.

[0103] <Specific Examples and Modifications of Second Embodiment> Next, specific examples and modifications of the stacked memory 10 according to the second embodiment will be described. The stacked memory 10 is configured by stacking a memory controller 11, a first memory unit 12, and a second memory unit 13 in this order, and further stacking at least the first memory unit 12.

[0104] FIG. 13 is a schematic diagram illustrating a modified example of the stacked memory 10 according to the second embodiment. The stacked memory 10 is configured by stacking one memory controller 11, one first memory die 12a, one second memory die 13a, and one first memory die 12a in this order. That is, the stacked memory 10 is configured by stacking the memory controller 11, the first memory unit 12, the second memory unit 13, and the first memory unit 12 in this order. The first memory unit 12 includes one first memory die 12a, and the second memory unit 13 includes one second memory die 13a. Note that the first memory unit 12 may include the same number of first memory dies as the number of second memory dies in the second memory unit 13, and the number may be set arbitrarily.

[0105] FIG. 14 is a diagram schematically illustrating a specific example of a stacked memory 10 according to the second embodiment. The stacked memory 10 is configured by stacking one memory controller 11, one first memory die 12a, one second memory die 13a, one first memory die 12a, and one second memory die 13a in this order. That is, the stacked memory 10 is configured by stacking the memory controller 11, the first memory unit 12, the second memory unit 13, and the first memory unit 12 and the second memory unit 13 in this order. The first memory unit 12 includes one first memory die 12a, and the second memory unit 13 includes one second memory die 13a. The stacked memory 10 may also be configured by alternately stacking the first memory units 12 and the second memory units 13.

[0106] FIG. 15 is a diagram schematically illustrating a specific example of a stacked memory 10 according to the second embodiment, which is different from FIG. 14 . The stacked memory 10 is configured by stacking one memory controller 11, two first memory dies 12a, one second memory die 13a, two first memory dies 12a, and one second memory die 13a in this order. That is, the stacked memory 10 is configured by stacking the memory controller 11, the first memory unit 12, the second memory unit 13, and the first memory unit 12 and the second memory unit 13 in this order. The first memory unit 12 includes two first memory dies 12a, and the second memory unit 13 includes one second memory die 13a. The stacked memory 10 may also be configured by alternately stacking the first memory units 12 and the second memory units 13.

[0107] The first memory unit 12 may include more first memory dies than the second memory dies of the second memory unit 13. In other words, as long as the number of first memory dies 12a in the first memory unit 12 is equal to or greater than the number of second memory dies 13a in the second memory unit 13, the number of first memory dies 12a in the first memory unit 12 and the number of second memory dies 13a in the second memory unit 13 can be set arbitrarily.

[0108] 16 is a diagram schematically illustrating a specific example of a stacked memory 10 according to a second embodiment of the present invention, which is different from FIG. 13 . The stacked memory 10 is configured by stacking one memory controller 11, four first memory dies 12 a, four second memory dies 13 a, four first memory dies 12 a, and four second memory dies 13 a in this order. That is, the stacked memory 10 is configured by stacking the memory controller 11, the first memory unit 12, the second memory unit 13, the first memory unit 12, and the second memory unit 13 in this order. The first memory unit 12 includes four first memory dies 12 a, and the second memory unit 13 includes four second memory dies 13 a.

[0109] 17 is a diagram schematically illustrating a specific example of a stacked memory 10 according to the second embodiment, which is different from those illustrated in FIGS. 14 to 16 . The stacked memory 10 is configured such that three first memory units 12 and three second memory units 13 are stacked in order on a first memory controller 11a, and then a first memory unit 12 and a second memory controller 11b are stacked on top of the first memory controller 11b. Four first memory units 12 and four second memory units 13 are stacked in order on top of the second memory controller 11b. The number of repetitions of the first memory units 12 and the second memory units 13 between the first memory controller 11a and the second memory controller 11b is arbitrary. The number of repetitions of the first memory units 12 and the second memory units 13 above the second memory controller 11b is arbitrary. The number of repetitions of the first memory unit 12 and the second memory unit 13 above the second memory controller 11b may be the same as or different from the number of repetitions of the first memory unit 12 and the second memory unit 13 between the first memory controller 11a and the second memory controller 11b.

[0110] 17, the first memory unit 12 includes one first memory die 12a, and the second memory unit 13 includes one second memory die 13a. The number of first memory dies 12a included in the first memory unit 12 and the number of second memory dies 13a included in the second memory unit 13 are both arbitrary, as long as the first memory unit 12 includes more first memory dies 12a than the number of second memory dies 13a in the second memory unit 13. The first memory controller 11a is provided on the substrate 31.

[0111] As shown in FIG. 17, the stacked memory 10 is configured by repeatedly stacking a first memory unit 12 and a second memory unit 13 in this order on a first memory controller 11a, stacking the first memory unit 12 and a second memory controller 11b, and further repeatedly stacking the first memory unit 12 and the second memory unit 13 in this order.

[0112] In this way, a memory controller (second memory controller 11b) is provided between the two first memory units 12, and the first memory unit 12 and the second memory unit 13 are stacked in this order on the memory controller (second memory controller 11b).

[0113] Fig. 18 is a diagram schematically illustrating a modification of the stacked memory according to the second embodiment, which is different from Fig. 13. The stacked memory 10 is configured by stacking a first memory unit 12 and a second memory controller 11b in this order on a first memory controller 11a, and by stacking the first memory unit 12 and a second memory unit 13 in this order on the second memory controller 11b.

[0114] Furthermore, as shown in FIG. 18, the second memory unit 13 may be provided with a third memory controller 11c.

[0115] The first memory unit 12 between the first memory controller 11a and the second memory controller 11b includes one or more first memory dies 12a. The first memory unit 12 between the second memory controller 11b and the second memory unit 13 includes one or more first memory dies 12a. The second memory unit 13 includes one or more second memory dies 13a. The first memory unit 12 adjacent to the third memory controller 11c includes one or more first memory dies 12a. The first memory controller 11a is provided on a substrate 31.

[0116] The embodiments and specific design examples of the present invention are not limited to the aspects shown in the drawings, and can be modified as appropriate.

[0117] In the description of this specification and the claims, a configuration in which a memory controller, a first memory unit consisting of one or more first memory dies, and a second memory unit consisting of one or more second memory dies are arranged in this order includes not only a case in which the first memory unit and the second memory unit are stacked in this order on the memory controller, but also a case in which the first memory unit and the memory controller are stacked in this order on the second memory unit.

[0118] <Sixth Embodiment> Figure 19 is a diagram schematically illustrating a stacked memory 10 according to a sixth embodiment of the present invention. The stacked memory 10 according to the sixth embodiment of the present invention is configured such that, compared to the stacked memory 10 according to the first embodiment, a heat transfer section 18 is sandwiched between a first memory section 12 and a second memory section 13. The heat transfer section 18 overlaps with the second memory section 13 in a plan view, and at least one of the front, rear, left, and right ends protrudes from the corresponding surfaces of the first memory section 12 and the second memory section 13. In the embodiment shown in Figure 19, each of the four front, rear, left, and right ends protrudes outward.

[0119] In this way, since the heat transfer section 18 is sandwiched between the first memory section 12 and the second memory section 13, even if heat that may be generated in the memory controller 11 is transferred via the first memory section 12, it is diffused in a planar manner by the heat transfer section 18 and can be released to the outside of the stacked memory 10 through the ends protruding from the first memory section 12 and the second memory section 13.

[0120] In the sixth embodiment, although not shown in FIG. 19, it is preferable that the first memory dies 12a of the first memory unit 12, the second memory dies 13a of the second memory unit 13, and the first memory die 12a and the second memory die 13a are connected by through wirings 15 (not shown), as shown in FIGS. 3A and 3B.

[0121] The heat transfer portion 18 may be made of an insulating material, or may be made of a heat transfer material such that the upper and lower surfaces are electrically insulated from each other. Graphite or the like may be used as the heat transfer material.

[0122] In addition to the above-described configuration, the heat transfer unit 18 may have microchannels disposed therein, and the microchannels may be arranged in a zigzag pattern along the front, rear, left, and right sides in a plan view. For example, in the heat transfer unit 18, one end of the microchannel may be provided at an end protruding from the front, rear, left, and right sides of the second memory die 13a in a plan view, and the other end of the microchannel may be provided at another end. A circulation system may be configured in which a coolant flows from one end of the microchannel and is collected from the other end of the microchannel. In this case, the heat transfer unit 18 also functions as a heat dissipation unit. Of course, the microchannels are configured so as not to overlap with wiring extending in the vertical direction in a plan view.

[0123] Seventh Embodiment FIG. 20 is a diagram schematically illustrating a stacked memory 10 according to a seventh embodiment of the present invention. The stacked memory 10 according to the seventh embodiment of the present invention is configured such that, compared to the stacked memory 10 according to the first embodiment, heat transfer units 18 are provided adjacent to at least one of the left, right, front, and rear sides of the first memory unit 12. The heat transfer units 18 are provided on at least one of the left, right, front, and rear sides of the first memory unit 12, and on at least one of the left, right, front, and rear sides of the first memory unit 12 and the second memory unit 13, from the bottom surface of the memory controller 11 to the top surface of the second memory unit 13. As shown in FIG. 20 , heat transfer units 18 a, 18 a may be provided on both sides of the first memory unit 12 and the second memory unit 13 in either the front, back, left, or right direction. The heat transfer unit 18 is configured by these heat transfer units 18 a. Although not shown in the figure, the heat transfer section 18 may be arranged to surround the first memory section 12 and the second memory section 13 on four sides, i.e., the front, back, left and right, of the first memory section 12 and the second memory section 13.

[0124] In this way, by providing the heat transfer unit 18 adjacent to at least one of the front, rear, left, and right sides of the first memory unit 12, heat that may be generated in the memory controller 11 is released to the outside of the stacked memory 10 at the side of the first memory unit 12. By providing the heat transfer unit 18 adjacent to at least one of the front, rear, left, and right sides of the first memory unit 12 and the second memory unit 13, heat that may be generated in the memory controller 11 is released to the outside of the stacked memory 10 at the side of the first memory unit 12 and the second memory unit 13. In the former case, by sandwiching the first memory unit 12 between the memory controller 11 and the second memory unit 13, heat from the memory controller 11 is released by the heat transfer unit 18, making it less likely for the heat to reach the second memory unit 13, which is preferable.

[0125] The stacked memory 10 of the seventh embodiment can be said to have a configuration similar to that of the third embodiment described above, in which the through wiring 15a for heat transfer is provided on the sides of the first memory section 12 and the second memory section 13.

[0126] Furthermore, when the stacked memory 10 according to the seventh embodiment is installed in a cavity of a substrate having a cavity, the memory controller 11 is electrically connected to the substrate, and the memory controller 11 is molded in the cavity with resin or the like, the stacked memory 10 is adjacent to the front, rear, left, and right of the stacked memory 10 with molded parts, and the molded parts may function as the heat transfer parts 18. This can be realized in a stacked module including a substrate having such a cavity.

[0127] Eighth Embodiment Figure 21 is a diagram schematically illustrating a stacked memory 10 according to an eighth embodiment of the present invention. The stacked memory 10 according to the eighth embodiment of the present invention is a configuration in which the stacked memory 10 according to the first embodiment is a combination of the sixth and seventh embodiments. A first heat transfer portion 18b is sandwiched between a first memory portion 12 and a second memory portion 13, and a second heat transfer portion 18c is provided on at least one side of the first memory portion 12 and the second memory portion 13, either front, rear, left, or right. The first heat transfer portion 18b and the second heat transfer portion 18c constitute a heat transfer portion 18. The first heat transfer portion 18b and the second heat transfer portion 18c may be integral with each other. The second heat transfer section 18c may be provided on some or all of the left, right, front, and rear sides of the first memory section 12 and the second memory section 13, and may be functionally integrated with the first heat transfer section 18b to release heat from the memory controller 11 and diffuse the heat.

[0128] With this heat transfer section 18, heat that may be generated in the memory controller 11 is discharged to the outside of the stacked memory 10 by the first heat transfer section 18b and the second heat transfer section 18c. Preferably, the heat is unlikely to reach the second memory die 13a.

[0129] Since the eighth embodiment is a combination of the sixth embodiment and the seventh embodiment, the configurations of the heat transfer portions 18 of the sixth embodiment and the seventh embodiment may be combined.

[0130] Although the sixth, seventh and eighth embodiments have been described with respect to the first embodiment, they are also applicable to any of the other embodiments.

[0131] In the description of this specification and the claims, "a first memory unit and a second memory unit are repeatedly arranged" means that the order in the stacking direction is first memory unit, second memory unit, first memory unit, or the order in the opposite direction to the stacking direction is first memory unit, second memory unit, first memory unit.

[0132] The types of the first memory die 12a and the second memory die 13a are not limited to an MRAM die for the first memory die 12a and a DRAM die for the second memory die 13a, but may also include any of a resistive random access memory (ReRAM) die, a phase-change memory (PRAM) die, and a ferroelectric random access memory (FeRAM) die.

[0133] When the first memory die 12a is an MRAM, the second memory die 13a may be a DRAM die, a PRAM die, or an FeRAM die, because the MRAM, which is the first memory die 12a, is superior to the die selected as the second memory die 13a in terms of heat resistance.

[0134] When the second memory die 13a is a DRAM die, the first memory die 12a may be an MRAM or an ReRAM, because the die selected as the first memory die 12a is superior in heat resistance to the DRAM that is the second memory die.

[0135] When the second memory die 13a is a DRAM die, the first memory die 12a may be an MRAM, an FeRAM, or an ReRAM because the die selected as the first memory die 12a has a lower read power than the DRAM, which is the second memory die.

[0136] The first memory portion 12 includes a first memory die 12a but does not include a second memory die, and the second memory portion 13 includes a second memory die 13a but does not include the first memory die.

[0137] The first memory die 12a and the second memory die 13a refer to individual memory dies cut out from a semiconductor wafer after various processes such as exposure and etching of a circuit pattern. They are sometimes called chips instead of memory dies.

[0138] The memory controller 11 is also a control die configured to control data flowing in and out of the first memory unit 12 and the second memory unit 13. The memory controller 11 may further have a function to perform logical operation processing of data in the stacked memory 10.

[0139] The logic dies 23 and 33 are also called computation dies and perform logical operation processing of data in the stacked memory 10. The logic dies 23 and 33 may be a CPU, an ASIC, a GPU, an FPGA, an SoC, or a combination thereof. The logic dies may include a photoelectric conversion element such as a laser to optically exchange data and control signals with the outside of the integrated module.

[0140] In an AI system, in a neural network, a product-sum operation is performed between the output value of a neuron in the previous layer and its corresponding weighting coefficient, and the weighted sum obtained by the product-sum operation is passed through an activation function, with the output value being the final output value.

[0141] The first memory dies 12a of the first memory unit 12, the second memory dies 13a of the second memory unit 13, the memory controller 11 and the first memory unit 12, and the memory controller 11 and the second memory unit 13 may be close to or adjacent to each other, for example, if they are connected vertically by through-hole wiring.

[0142] In the stacked memory 10 according to the embodiment of the present invention, the memory controller 11 and the lower surface of the first memory unit 12 are shown in contact in the drawings, but in actual implementation, one or more intervening members, such as microbumps, underfill, connection layers, or other insulating layers, may be provided between them. Therefore, a minute gap of 10 μm or more and 100 μm or less is typically formed between the opposing surfaces of the memory controller 11 and the first memory unit 12, for example, between the upper surface of the memory controller 11 and the lower surface of the first memory unit 12. Furthermore, a distance of more than 100 μm may be ensured depending on design requirements, such as the placement of a thermal diffusion structure, such as the heat transfer unit 18, a cooling member, or mechanical stress relief.

[0143] A stacked memory 10 according to an embodiment of the present invention includes a memory controller 11, a first memory unit 12 including one or more first memory dies 12a, and a second memory unit 13 including one or more second memory dies 13a, arranged in this order, where the first memory unit 12 does not include the second memory die 13a, and the second memory unit 13 does not include the first memory die 12a, and the first memory die 12a is superior to the second memory die 13a in at least one of heat resistance, read power, and power consumption. In particular, it is preferable that the first memory die 12a be superior to the second memory die 13a in heat resistance.

[0144] The embodiments described in this specification and the embodiments shown in the drawings are merely examples for specifically explaining the present invention, and the present invention is not limited to these. The technical scope of the present invention includes a wide range of variations including various modifications, improvements, and substitutions that those skilled in the art may make based on the technical concept of the present invention.

[0145] 10: Stacked memory 11: Memory controller 11a: First memory controller 11b: Second memory controller 11c: Third memory controller 12: First memory section 12a: First memory die 13: Second memory section 13a: Second memory die 14: Third memory section 14a: Third memory die 15, 35: Through wiring 20, 30: Integrated module 21, 31: Substrate (e.g., package substrate) 22: Wiring connection substrate 22a: Wiring 23, 33: Logic die 24a: Solder ball 24b: Solder ball 25: Solder ball 26, 36: Solder ball 40: Neural network 41: Input layer 42: Intermediate layer 43: Output layer

Claims

1. A stacked memory comprising: a memory controller; a first memory unit comprising one or more first memory dies; and a second memory unit comprising one or more second memory dies, arranged in this order; wherein the first memory unit does not include the second memory die, and the second memory unit does not include the first memory die; and the first memory die is superior to the second memory die in at least one of heat resistance, read power, and power consumption.

2. The stacked memory according to claim 1, wherein the first memory section and the second memory section are provided repeatedly in this order.

3. The stacked memory of claim 2, wherein the number of first memory dies included in said first memory portion is equal to or greater than the number of second memory dies included in said second memory portion.

4. The stacked memory of claim 1, wherein the first memory die and the second memory die are connected by through-wiring.

5. The stacked memory of claim 1, wherein the first memory die is an MRAM die and the second memory die is a DRAM die.

6. The stacked memory according to any one of claims 1 to 5, for use in an integrated module having a bandwidth of a certain maximum value per stack formed by stacking the first memory section and the second memory section, the certain maximum value being 256 GB / s or more.

7. An integrated module comprising: a stacked memory according to any one of claims 1 to 5; and a logic die.

8. The integrated module of claim 7, wherein the first memory die is configured to store weighting coefficients that are input to the logic die and required for inference in the AI ​​model, and the second memory die is configured to store input data that is input to the logic die and required for inference in the AI ​​model.

9. The integrated module of claim 7, wherein the stacked memory is disposed vertically or horizontally with the logic die, and the stacked memory is wired to the logic die.

10. The integrated module according to claim 7, wherein each stack formed by stacking the first memory section and the second memory section has a bandwidth of a certain maximum value, the certain maximum value being 256 GB / s or more.

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