Semiconductor device

Abstract

This semiconductor device includes: a chip having a main surface; a first pillar region of a first conductivity type disposed in the chip and extending in a band shape along a first direction in plan view; and a second pillar region of a second conductivity type adjacent to the first pillar region in the chip and extending in a band shape along the first direction in plan view. The second pillar region includes a width-changing part where the width in a second direction crossing the first direction changes in plan view.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-114363 filed with the Japan Patent Office on July 17, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device having a superjunction structure. The semiconductor device includes an epitaxial layer. A p-type body region is formed in a surface portion of the epitaxial layer. An n-type potential extraction region is formed in a surface portion of the p-type body region.

[0004] In the epitaxial layer, a region below the p-type body region is － A p-type pillar region is formed on the epitaxial layer. A gate electrode is formed on the epitaxial layer. The gate electrode faces the p-type body region and the n-type potential extraction region with a gate insulating film sandwiched therebetween.

[0005] JP 2010-109296 A

[0006] [Summary] One embodiment of the present disclosure provides a semiconductor device including: a chip having a main surface; a first pillar region of a first conductivity type disposed within the chip and extending in a strip shape along a first direction in a planar view; and a second pillar region of a second conductivity type adjacent to the first pillar region within the chip and extending in a strip shape along the first direction in a planar view, wherein the second pillar region includes a width varying portion whose width varies in a second direction intersecting the first direction in a planar view.

[0007] One embodiment of the present disclosure provides a semiconductor device comprising: a SiC chip having a main surface, the SiC chip including an active region and a peripheral region outside the active region; a drift region of a first conductivity type formed in a surface layer portion of the main surface of the SiC chip; a superjunction structure including first pillar regions of the first conductivity type and second pillar regions of a second conductivity type arranged adjacent to each other and alternately repeated in a direction along the main surface within the drift region; a device structure formed in the active region between the superjunction structure and the main surface; the first pillar region having a first extension portion extending in a first direction from the active region toward the peripheral region in a planar view; the second pillar region having a second extension portion extending in the first direction from the active region toward the peripheral region in a planar view and adjacent to the first extension portion;

[0008] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a chip. FIG. 4 is a perspective view showing an example layout of a chip. FIG. 5 is a cross-sectional perspective view showing a main portion of a chip together with a basic form of a pillar region. FIG. 6 is an enlarged view of a region surrounded by dashed dotted line VI in FIG. 3 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6 . FIG. 9 is a cross-sectional perspective view showing a pillar region according to a first embodiment. FIG. 10 is a cross-sectional perspective view showing a pillar region according to a second embodiment. FIG. 11 is a cross-sectional perspective view showing a pillar region according to a third embodiment. FIG. 12 is a cross-sectional perspective view showing a pillar region according to a fourth embodiment. FIG. 13 is a cross-sectional perspective view showing a pillar region according to a fifth embodiment. FIG. 14 is a cross-sectional perspective view showing a pillar region according to a sixth embodiment. FIG. 15 is a cross-sectional perspective view showing a pillar region according to a seventh embodiment. FIG. 16 is a cross-sectional perspective view showing a pillar region according to an eighth embodiment. FIG. 17 is a cross-sectional perspective view showing a pillar region according to a ninth embodiment. FIG. 18 is a cross-sectional perspective view showing a pillar region according to a tenth embodiment. FIG. 19 is a cross-sectional perspective view showing a pillar region according to an eleventh embodiment. FIG. 20 is a plan view showing a main portion of an active region. FIG. 21 is a cross-sectional perspective view showing a gate structure according to a first embodiment. FIG. 22 is a cross-sectional view showing a main portion of a peripheral region. FIG. 23A is a cross-sectional view taken along line XXIIIA-XXIIIA shown in FIG. 3. FIG. 23B is a cross-sectional view taken along line XXIIIB-XXIIIB shown in FIG. 23A. FIG. 24 is a plan view showing a second embodiment of the second extension portion, corresponding to FIG. 6. FIG. 25 is a plan view showing a third embodiment of the second extension portion, corresponding to FIG. 6. FIG. 26 is a plan view showing a fourth embodiment of the second extension portion, corresponding to FIG. 6. Fig. 27 is a plan view showing an example layout of a chip according to a first modified example of the first embodiment, and is a view corresponding to Fig. 3. Fig. 28 is a plan view showing an example layout of a chip according to a second modified example of the first embodiment, and is a view corresponding to Fig. 3. Fig. 29 is a plan view showing a semiconductor device according to a second embodiment of the present disclosure. Fig. 30 is a cross-sectional view taken along line XXX-XXX shown in Fig. 29.FIG. 31 is a plan view showing an example of a chip layout. FIG. 32 is a plan view showing a main portion of an active region. FIG. 33 is a cross-sectional view showing a gate structure according to a first embodiment. FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV shown in FIG. 31. FIG. 35 is a cross-sectional perspective view showing a gate structure according to a second embodiment. FIG. 36 is a cross-sectional perspective view showing a gate structure according to a third embodiment. FIG. 37 is a cross-sectional perspective view showing a gate structure according to a fourth embodiment. FIG. 38 is a plan view showing a semiconductor device according to a third embodiment of the present disclosure. FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in FIG. 38. FIG. 40 is a plan view showing an example of a chip layout. FIG. 41 is a cross-sectional perspective view showing a diode structure according to the basic embodiment.

[0009] [Detailed Description] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are all schematic views and are not strictly illustrative, and the scale, ratio, angle, etc. are not necessarily the same. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2. Fig. 5 is a cross-sectional perspective view showing a main portion of the chip 2 together with the basic form of a second pillar region 12.

[0013] 1 to 5, semiconductor device 1A is a SiC semiconductor device in this embodiment. Semiconductor device 1A includes chip 2 including SiC single crystal. Chip 2 may also be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of another polytype.

[0014] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0015] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0016] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface (end face) 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface (end face) 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The second side surface 5B and the fourth side surface 5D extend in a first direction Y along the first main surface 3 and face a second direction X that intersects (specifically, is perpendicular to) the first direction Y. The first side surface 5A and the third side surface 5C extend in the second direction X and face the first direction Y.

[0017] In this embodiment, the first direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction X is the m-axis direction ([1-100] direction) of the SiC single crystal. Of course, the first direction Y may be the m-axis direction of the SiC single crystal, and the second direction X may be the a-axis direction of the SiC single crystal.

[0018] The XY plane including the first direction Y and the second direction X forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction Y and the second direction X may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0019] 5, the chip 2 (first main surface 3 and second main surface 4) has an off angle θoff inclined at a predetermined angle in a predetermined off direction Doff with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Doff by the off angle θoff. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θoff.

[0020] The off-direction Doff is preferably the a-axis direction of the SiC single crystal (i.e., the first direction Y). The off-angle θoff may be greater than 0° and less than or equal to 10°. The off-angle θoff may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0021] The off angle θ is preferably 5° or less. The off angle θ is particularly preferably 2° or more and 4.5° or less. The off angle θ is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θ is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0022] The chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 may also be referred to as a "base SiC layer," a "base region," or the like. The base layer 6 extends horizontally in a layered manner and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate). The base layer 6 has the off direction Doff and off angle θoff described above.

[0023] The base layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0024] The base layer 6 has a base thickness TB. The base thickness TB may be 5 μm or more and 300 μm or less. The base thickness TB may have a value belonging to any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less. The base thickness TB is preferably 50 μm or more and 250 μm or less.

[0025] The chip 2 includes a stacked layer 7 stacked on a base layer 6. The stacked layer 7 may be referred to as a "semiconductor layer," "SiC layer," "SiC stacked layer," "semiconductor stacked layer," or the like. In this embodiment, the stacked layer 7 is provided as a layer for forming a superjunction structure SJ. In this embodiment, the stacked layer 7 is formed of a single semiconductor layer, but may be formed of multiple semiconductor layers. When the stacked layer 7 is formed of multiple semiconductor layers, the number of layers is arbitrary and is adjusted appropriately depending on the electrical characteristics to be achieved. Examples of electrical characteristics include a breakdown voltage and a resistance value.

[0026] The stacked portion 7 extends in layers in the horizontal direction and forms part of the first to fourth side surfaces 5A to 5D of the chip 2. The stacked portion 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) grown from the base layer 6 as a starting point.

[0027] The laminate 7 has a lower end and an upper end. The lower end of the laminate 7 is the starting point of crystal growth, and the upper end of the laminate 7 is the end point of crystal growth. Because the laminate 7 is grown continuously from the base layer 6, the lower end of the laminate 7 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the laminate 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The laminate 7 has an off-direction Doff and an off-angle θoff that are approximately the same as the off-direction Doff and off-angle θoff of the base layer 6.

[0028] The entire stacked layer 7 may be referred to as the drift region 8. The drift region 8 is a region that serves as the base of impurity regions (such as the first pillar region 13, the second pillar region 12, the body region 32, the source region 33, and the contact region 34, which will be described later) that are selectively formed by implanting impurity ions into the stacked layer 7. By implanting n-type impurity ions or p-type impurity ions into the stacked layer 7 to a concentration that exceeds the impurity concentration of the drift region 8, various n-type or p-type impurity regions having characteristics according to the respective concentrations are formed.

[0029] Although the drift region 8 is replaced by various impurity regions in the target region of the stacked layer 7 by ion implantation, the n-type impurity ions added during epitaxial growth of the stacked layer 7 remain at the concentration at the time of growth. As a result, the drift region 8 provides an n-type background concentration within a range that does not impair the characteristics (electrical behavior) of the various impurity regions. On the other hand, even if only a small amount of n-type or p-type impurity ions are implanted into the stacked layer 7, the characteristics of the drift region 8 are maintained in the region, and the drift region 8 remains.

[0030] The n-type impurity concentration of the stacked layer 7 (drift region 8) is preferably lower than the n-type impurity concentration of the base layer 6. １５ cm －３ 1x10 or more １６ cm －３The n-type impurity concentration of the multilayer portion 7 may have the following peak value: The n-type impurity concentration of the multilayer portion 7 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the multilayer portion 7 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0031] The stacked layer 7 (drift region 8) has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the stacked layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The stacked layer 7 preferably contains a pentavalent element other than phosphorus.

[0032] The n-type impurity concentration of the stacked layer 7 (drift region 8) is preferably adjusted by at least nitrogen. When the stacked layer 7 contains two or more pentavalent elements, the stacked layer 7 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the stacked layer 7 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen. In this embodiment, the stacked layer 7 (drift region 8) does not contain phosphorus, but contains nitrogen as a pentavalent element.

[0033] The stacked portion 7 has an epitaxial thickness TE. The epitaxial thickness TE is preferably less than the base thickness TB. The epitaxial thickness TE is preferably 1 μm or more. The epitaxial thickness TE is preferably 5 μm or less. The epitaxial thickness TE may have a value belonging to any one of the following ranges: 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0034] The semiconductor device 1A includes an active region 10 set in a chip 2. The active region 10 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 10 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 10 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0035] The semiconductor device 1A includes a peripheral region 11 set outside the active region 10 in the chip 2. The peripheral region 11 is provided in a region between the periphery of the chip 2 and the active region 10 in a plan view. The peripheral region 11 extends in a band shape along the active region 10 in a plan view, and is set in a polygonal ring shape (a square ring shape in this embodiment) surrounding the active region 10.

[0036] The semiconductor device 1A includes a plurality of p-type second pillar regions 12 formed in the stacked layer 7 in the active region 10. The second pillar regions 12 may also be referred to as "pillar layers," "column layers (regions)," "p-type layers (regions)," "p-type zones," etc. The plurality of second pillar regions 12 are formed at intervals in the horizontal direction within the stacked layer 7, and define a plurality of n-type first pillar regions 13, each of which is made up of a part of the stacked layer 7.

[0037] The multiple second pillar regions 12 are formed by part of the stacked layer 7. The multiple second pillar regions 12 form multiple pn junctions having charge balance together with the multiple first pillar regions 13. As a result, the multiple second pillar regions 12 form a super junction structure SJ together with the multiple first pillar regions 13 within the stacked layer 7. The state of having charge balance means that, with respect to multiple adjacent second pillar regions 12, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the multiple first pillar regions 13.

[0038] The multiple second pillar regions 12 are arranged at intervals in the second direction X within the stacked unit 7, and are each formed in a strip shape extending in the first direction Y. That is, the multiple second pillar regions 12 are formed in a stripe shape extending in the first direction Y, and the multiple first pillar regions 13 are formed in a stripe shape extending in the first direction Y. The multiple second pillar regions 12 are also arranged at intervals in the m-axis direction of the SiC single crystal, and extend in the a-axis direction of the SiC single crystal. In other words, the extension direction of the multiple second pillar regions 12 coincides with the off-direction Doff of the stacked unit 7. The multiple first pillar regions 13 and the multiple second pillar regions 12 are alternately arranged in the second direction X, and are arranged in a stripe shape as a whole.

[0039] 5 , the plurality of second pillar regions 12 each have a second lower end 12a on the lower end side of the laminated portion 7 and a second upper end 12b on the upper end side of the laminated portion 7. The second lower end 12a is located in a region on the lower end side of the laminated portion 7 relative to the intermediate portion of the thickness range of the laminated portion 7, and the second upper end 12b is located in a region on the upper end side of the laminated portion 7 relative to the intermediate portion of the thickness range of the laminated portion 7.

[0040] The second lower end 12a may be formed at a distance from the lower end of the laminate 7 toward the upper end, and may face the base layer 6 across a part (lower end) of the laminate 7. The second lower end 12a may be substantially coincident with the lower end of the laminate 7 and connected to the base layer 6.

[0041] The distance between the lower end of laminated portion 7 and second lower end 12a may be 0 μm or more and 2 μm or less. The distance between the lower end of laminated portion 7 and second lower end 12a may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0042] The second lower end 12a may have an extension that crosses the boundary between the base layer 6 and the laminated portion 7 and is located within the base layer 6. In this case, the thickness of the extension of the second lower end 12a, based on the upper end of the base layer 6, may be greater than 0 μm and less than 2 μm. The thickness of the extension of the second lower end 12a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0043] The second upper end 12b may be formed at a distance from the upper end of the laminated portion 7 toward the lower end thereof, and may face the upper end of the laminated portion 7 across a part (upper end) of the laminated portion 7. The second upper end 12b may be substantially coincident with the upper end of the laminated portion 7.

[0044] The distance between the upper end of the laminated portion 7 and the second upper end 12b may be 0 μm or more and 1 μm or less. The distance between the upper end of the laminated portion 7 and the second upper end 12b may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0045] The plurality of second pillar regions 12 are 1×10 １６ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the second pillar region 12 may have the following peak value. The p-type impurity concentration of the second pillar region 12 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the second pillar region 12 is adjusted by a trivalent element that is heavier than carbon. In other words, the second pillar region 12 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the second pillar region 12 is adjusted by aluminum.

[0046] 3 , each of the multiple second pillar regions 12 includes one second body portion 121 and two second extension portions 122 formed on both end portions of the second body portion 121. One second body portion 121 is formed in a strip shape extending in the first direction Y in the active region 10. The two second extension portions 122 are each strip-shaped extending along the first direction Y in the peripheral region 11. That is, each second extension portion 122 extends along the first direction Y from the active region 10 toward the peripheral region 11 in a plan view.

[0047] 5 , the second main body portions 121 of the multiple second pillar regions 12 each have a second pillar width W2. The second pillar width W2 is the width in a direction perpendicular to the extension direction of the second pillar regions 12. The second pillar width W2 is constant throughout the second main body portion 121 in the first direction Y. The second pillar width W2 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the second pillar width W2 may be equal to or greater than the epitaxial thickness TE.

[0048] The second pillar width W2 may be 0.1 μm or more and 5 μm or less. The second pillar width W2 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The second pillar width W2 is preferably 0.5 μm or more and 1.5 μm or less.

[0049] The second body portions 121 of the second pillar regions 12 each have a second thickness T2. The second thickness T2 may also be referred to as the depth of the second pillar regions 12. The second thickness T2 may be less than the epitaxial thickness TE of the stack 7. The second thickness T2 may be greater than the epitaxial thickness TE. The second thickness T2 may be approximately equal to the epitaxial thickness TE.

[0050] The second thickness T2 is preferably 1 μm or more. The second thickness T2 is preferably 5 μm or less. The second thickness T2 may have a value belonging to any one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0051] It is preferable that the second pillar width W2 is less than the epitaxial thickness TE of the stacked portion 7, and that the second thickness T2 is greater than the second pillar width W2. In other words, it is preferable that the second body portions 121 of the multiple second pillar regions 12 each have a second aspect ratio T2 / W2 such that they extend in a vertically elongated columnar shape along the thickness direction of the stacked portion 7. The second aspect ratio T2 / W2 is the ratio of the second thickness T2 to the second pillar width W2. In this case, it is particularly preferable that the second thickness T2 is greater than the epitaxial thickness TE. For example, the second aspect ratio T2 / W2 may be greater than 1 and not greater than 100.

[0052] The second main body portions 121 of the multiple second pillar regions 12 are formed at intervals of a second pitch P2 in the second direction X. The second pitch P2 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the second pitch P2 may be equal to or greater than the epitaxial thickness TE.

[0053] The second pitch P2 may be 0.1 μm or more and 5 μm or less. The second pitch P2 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The second pitch P2 is preferably 0.5 μm or more and 1.5 μm or less.

[0054] The plurality of first pillar regions 13 each have a first lower end 13a at the lower end of the laminate 7 and a first upper end 13b at the upper end of the laminate 7. The first lower end 13a is located in a region on the lower end side of the laminate 7 relative to the intermediate part of the thickness range of the laminate 7, and the first upper end 13b is located in a region on the upper end side of the laminate 7 relative to the intermediate part of the thickness range of the laminate 7.

[0055] The first lower end 13a may be formed at a distance from the lower end of the laminate 7 toward the upper end, and may face the base layer 6 across a part (lower end) of the laminate 7. The first lower end 13a may be substantially coincident with the lower end of the laminate 7 and connected to the base layer 6.

[0056] The distance between the lower end of laminated portion 7 and first lower end 13a may be 0 μm or more and 2 μm or less. The distance between the lower end of laminated portion 7 and first lower end 13a may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0057] First lower end 13a may have an extension that crosses the boundary between base layer 6 and stacked portion 7 and is located within base layer 6. In this case, the thickness of the extension of first lower end 13a, based on the upper end of base layer 6, may be greater than 0 μm and less than 2 μm. The thickness of the extension of first lower end 13a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0058] The first upper end 13b may be formed at a distance from the upper end of the laminated portion 7 toward the lower end thereof, and may face the upper end of the laminated portion 7 across a part (upper end) of the laminated portion 7. The first upper end 13b may be substantially coincident with the upper end of the laminated portion 7.

[0059] The distance between the upper end of the laminated portion 7 and the first upper end 13b may be 0 μm or more and 1 μm or less. The distance between the upper end of the laminated portion 7 and the first upper end 13b may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0060] The plurality of first pillar regions 13 are 1×10 １６ cm －３ 1x10 or more １８ cm －３ The first pillar region 13 may have the following n-type impurity concentration as a peak value. The n-type impurity concentration is adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the first pillar region 13 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. In this embodiment, the n-type impurity concentration of the first pillar region 13 is adjusted by phosphorus.

[0061] 3 , each of the multiple first pillar regions 13 includes one first main body portion 131 and two first extension portions 132 formed at both end portions of the first main body portion 131. One first main body portion 131 is formed in a strip shape extending in the first direction Y in the active region 10. The two first extension portions 132 are each formed in a strip shape extending in the first direction Y in the peripheral region 11. That is, each first extension portion 132 extends along the first direction Y from the active region 10 toward the peripheral region 11 in a plan view. Each first extension portion 132 is sandwiched between the two first extension portions 132 in the second direction X. That is, the first extension portion 132 is adjacent to another first extension portion 132.

[0062] 5 , the first main body portions 131 of the multiple first pillar regions 13 each have a first pillar width W1. The first pillar width W1 is the width in a direction perpendicular to the extension direction of the first pillar regions 13. The first pillar width W1 is constant across the entire area of ​​the second main body portion 121 in the first direction Y. The first pillar width W1 may be the same as the second pillar width W2. Of course, the first pillar width W1 may be wider or narrower than the second pillar width W2. The first pillar width W1 is preferably less than the epitaxial thickness TE of the stack portion 7. Of course, the first pillar width W1 may be equal to or greater than the epitaxial thickness TE.

[0063] The first pillar width W1 may be 0.1 μm or more and 5 μm or less. The first pillar width W1 may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The first pillar width W1 is preferably 0.5 μm or more and 1.5 μm or less.

[0064] The first body portions 131 of the multiple first pillar regions 13 each have a first thickness T1. The first thickness T1 may also be referred to as the depth of the multiple first pillar regions 13. The first thickness T1 may be less than the epitaxial thickness TE of the stack 7. The first thickness T1 may also be greater than the epitaxial thickness TE. The first thickness T1 may also be approximately equal to the epitaxial thickness TE.

[0065] The first thickness T1 is preferably 1 μm or more and 5 μm or less. The first thickness T1 may have a value belonging to any one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0066] It is preferable that the first pillar width W1 is less than the epitaxial thickness TE of the stacked portion 7, and that the first thickness T1 is greater than the first pillar width W1. In other words, it is preferable that the multiple first pillar regions 13 each have a first aspect ratio T1 / W1 such that they extend in a vertically elongated columnar shape along the thickness direction of the stacked portion 7. The first aspect ratio T1 / W1 is the ratio of the first thickness T1 to the first pillar width W1. In this case, it is particularly preferable that the first thickness T1 be greater than the epitaxial thickness TE. For example, the first aspect ratio T1 / first pillar width W1 may be greater than 1 and not greater than 100.

[0067] The first body portions 131 of the multiple first pillar regions 13 are formed at intervals of a first pitch P1 in the second direction X. The first pitch P1 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the first pitch P1 may be equal to or greater than the epitaxial thickness TE.

[0068] The first pitch P1 may be 0.1 μm or more and 5 μm or less. The first pitch P1 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The first pitch P1 is preferably 0.5 μm or more and 1.5 μm or less.

[0069] In this embodiment, the drift region 8 in the active region 10 is wholly or partially replaced by the first pillar region 13 and the second pillar region 12. The drift region 8 may be formed (remain) outside the formation region of the first pillar region 13 and the second pillar region 12 in the active region 10. In order to clarify the basic form of the first pillar region 13 and the second pillar region 12, Figure 5 shows an embodiment in which the drift region 8 is not formed in the active region 10, but is formed only in the peripheral region 11. Although not shown in Figure 5, the drift region 8 may remain in the active region 10.

[0070] Note that the first pillar region 13 may be simply referred to as a drift region because it is an impurity region that maintains the conductivity type of the drift region 8. Considering the concentration difference between the first pillar region 13 and the drift region 8 (the concentration of the first pillar region 13 > the concentration of the drift region 8), the first pillar region 13 may be referred to as a "high-concentration drift region" and the drift region 8 may be referred to as a "low-concentration drift region." Furthermore, considering that the first pillar region 13 is formed in the drift region 8 after the formation of the drift region 8, the drift region 8 may be referred to as a "base drift region" and the first pillar region 13 may be referred to as a "second drift region."

[0071] Fig. 6 is an enlarged view of the area surrounded by the dashed line VI in Fig. 3. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 6.

[0072] One second extending portion 122 will be described below with reference to Figures 3 and 6 to 8. Figures 6 to 8 show a first embodiment of the second extending portion 122.

[0073] 6, the second extension portion 122 has a second inner end portion (inner end portion) 124 connected to the outer end portion (end portion) 123 of the second main body portion 121, and a second outer end portion (outer end portion) 125 disposed in the outer peripheral region 11. The length L2 of the second extension portion 122 in the first direction Y is not less than 5 μm and not more than 30 μm.

[0074] The length L2 may have a value belonging to any one of the ranges of 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, and 25 μm to 30 μm. The length L2 is preferably 10 μm to 20 μm.

[0075] The length L2 may be within a range of 0.03% to 1.5% of the length L1 ( FIG. 3 ) of the second pillar region 12. The length ratio (L2 / L1) (%) of the length L2 to the length L1 may have a value belonging to any one of the ranges of 0.03% to 0.1%, 0.1% to 0.2%, 0.2% to 0.3%, 0.3% to 0.4%, 0.4% to 0.5%, 0.5% to 1.0%, and 1.0% to 1.5%.

[0076] The length L2 may be in the range of 0.5% to 25% of the width of the outer peripheral region 11. The dimensional ratio (%) of the length L2 to the width dimension of the outer peripheral region 11 may be in any one of the ranges of 0.5% to 2.5%, 2.5% to 5%, 5% to 10%, 10% to 15%, 15% to 20%, and 20% to 25%.

[0077] The second inner end portion 124 is adjacent to one of the plurality of source contact portions (first contact portions) 50 described later in plan view. In FIG. 6, for clarity, the plurality of source contact portions 50 are indicated by dots (the same applies to FIGS. 24 to 26). The plurality of source contact portions 50 are strip-shaped and extend in a direction transverse to the superjunction structure SJ (i.e., the second direction X). In this embodiment, the plurality of source contact portions 50 are disposed at the boundary between the active region 10 and the peripheral region 11 (FIG. 1).

[0078] The second outer end 125 is disposed at a distance in the first direction Y from the side surface 5A, 5C (the first side surface 5A in the examples of FIGS. 3 and 6 ). The second outer end 125 has a plane that extends along the second direction X and the vertical direction Z. The second outer end 125 of two second extension portions 122 adjacent to each other in the second direction X are disposed at a distance from each other in the second direction X.

[0079] The second extending portion 122 has a width W20. The width W20 is the width in a direction perpendicular to the extension direction of the second pillar region 12 (i.e., the second direction X). The second extending portion 122 includes a width-varying portion 14 whose width W20 varies in the first direction Y. In this embodiment (a first embodiment example of the second extending portion 122), the width-varying portion 14 is a first tapered portion (tapered portion) 14A whose width W20 narrows in the first direction Y toward the side surfaces 5A, 5C ( FIG. 3 ; in the example of FIG. 6 , the first side surface 5A).

[0080] In this embodiment, the first tapered portion 14A is set over the entire area of ​​the second extending portion 122 in the first direction Y. In other words, the width W20 of the multiple first tapered portions 14A narrows from the multiple source contact portions 50 toward the second outer end portion 125.

[0081] The second extending portion 122 has two side portions 126 connecting the second inner end portion 124 and the second outer end portion 125. The two side portions 126 are inclined in a plan view so as to approach each other from the second inner end portion 124 toward the second outer end portion 125. The angle θ1 formed between each side portion 126 and the second outer end portion 125 is greater than 90.0° and not greater than 95.0°. The angle θ1 is the angle formed between each side portion 126 and a direction perpendicular to the extension direction of the second pillar region 12 (i.e., the second direction X).

[0082] The angle θ1 may have a value belonging to any one of the following ranges: greater than 90.0° and not greater than 91.0°; 91.0° or greater and not greater than 92.0°; 92.0° or greater and not greater than 93.0°; 93.0° or greater and not greater than 94.0°; and 94.0° or greater and not greater than 95.0°. The angle θ1 is preferably not less than 91.0° and not greater than 93.0°. The angle θ1 is even more preferably not less than 91.5° and not greater than 92.5°.

[0083] The two side portions 126 are not inclined relative to the vertical direction Z. In other words, the width of the second extending portion 122 does not change in the depth direction of the chip 2.

[0084] 6 to 8 , in the first tapered portion 14A (width-varying portion 14), the width W20 of the second extending portion 122 varies within a range between a first width W21, which is the maximum width, and a second width W22, which is the minimum width. The first width W21 is the width of the second extending portion 122 at the second inner end portion 124. The first width W21 is equal to the second pillar width W2 of the second main body portion 121 in the second pillar region 12.

[0085] The second width W22 is the width of the second extension portion 122 at the second outer end portion 125. In this embodiment, the width ratio (W22 / W21) (%) of the second width W22 to the first width W21 is equal to or greater than 20% and less than 100%.

[0086] The width ratio (W22 / W21) (%) of the second width W22 to the first width W21 may be a value belonging to any one of the following ranges: 20% to 40%, 40% to 60%, 60% to 65%, 65% to 70%, 70% to 75%, 75% to 80%, 80% to 85%, 85% to 90%, and 90% to less than 100%. The width ratio (W22 / W21) (%) is preferably 60% to 90%.

[0087] 7 and 8, the second extending portion 122 has the same thickness as the second thickness T2 of the second main body portion 121. The second extending portion 122 may be larger or smaller than the second thickness T2 of the second main body portion 121. The first extending portion 132 is defined by two adjacent second extending portions 122.

[0088] Below, one first extending portion 132 will be described.

[0089] 6 , the first extending portion 132 is sandwiched in the second direction X by two second extending portions 122. The first extending portion 132 has a first inner end portion 134 connected to the end portion 133 of the first main body portion 131 and a first outer end portion 135 disposed in the outer peripheral region 11. The length of the first extending portion 132 in the first direction Y is equal to the length L2 of the second extending portion 122 in the first direction Y.

[0090] The first inner end portion 134 is adjacent to a source contact portion 50 (described later) in a plan view. As described above, the source contact portions 50 are strip-shaped and extend in a direction crossing the superjunction structure SJ (i.e., the second direction X). The source contact portions 50 are also arranged at the boundary between the active region 10 and the peripheral region 11 ( FIG. 1 ).

[0091] The first outer end 135 is disposed at a distance from the side surfaces 5A and 5C in the first direction Y. The first outer end 135 is connected to the drift region 8 that surrounds the periphery of the superjunction structure SJ.

[0092] The first extending portion 132 has a width W10 in the second direction X. The width W10 of the first extending portion 132 changes in the first direction Y in accordance with the change in width of the width-changing portion 14 (first tapered portion 14A) of the second extending portion 122. Specifically, the width W10 of the first extending portion 132 increases in the first direction Y toward the side surfaces 5A and 5C of the chip 2 (FIG. 3; in the example of FIG. 6, the first side surface 5A).

[0093] The width W10 of the first extension portion 132 varies within a range between a minimum width W11 and a maximum width W12. The minimum width W11 is the width of the first extension portion 132 at the first inner end portion 134. The minimum width W11 is equal to the first pillar width W1 of the first main body portion 131 in the first pillar region 13.

[0094] The maximum width W12 is the width of the second extension portion 122 at the second outer end portion 125. In this embodiment, the width ratio (%) of the minimum width W11 to the maximum width W12 is 90% or more.

[0095] The width ratio (W11 / W12) (%) of the minimum width W11 to the maximum width W12 may be 20% or more and less than 100%. The width ratio (W22 / W21) (%) may have a value belonging to any one of the following ranges: 20% or more and 40% or less, 40% or more and 60% or less, 60% or more and 65% or less, 65% or more and 70% or less, 70% or more and 75% or less, 75% or more and 80% or less, 80% or more and 85% or less, 85% or more and 90% or less, and 90% or more and less than 100%. The width ratio (W11 / W12) (%) is preferably 60% or more and 90% or less.

[0096] The first extension portions 132 of the multiple first pillar regions 13 each have the same thickness as the first thickness T1 of the first main body portion 131. The first extension portions 132 may be larger or smaller than the first thickness T1 of the first main body portion 131.

[0097] As described above, the width W10 of the first extending portion 132 changes in the first direction Y in accordance with the change in width of the width varying portion 14 (first tapered portion 14A) of the second extending portion 122.

[0098] In order for the multiple second extension portions 122 to have charge balance with the multiple first extension portions 132, for the multiple adjacent second extension portions 122, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction must be connected within the multiple first extension portions 132.

[0099] Consider a case where each of the multiple second extension portions 122 has a constant width (constant width W2, similar to the first extension portion 132) across the entire area in the first direction Y. In this case, the multiple first extension portions 132 partitioned by the multiple second extension portions 122 also have a constant width across the entire area in the first direction Y. The spacing between the multiple second extension portions 122 (the width of the multiple first extension portions 132) and the impurity concentrations of the multiple second extension portions 122 are set to such spacing and concentrations that the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the multiple first pillar regions 13.

[0100] However, an error (variation) may occur in at least one of the spacing and impurity concentration of the multiple second extension portions 122. In this case, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction may not be connected across the entire area of ​​the multiple first extension portions 132 in the first direction Y. In this state, there is no charge balance across the entire area of ​​the second extension portions 122 in the first direction Y, which may result in a decrease in breakdown voltage.

[0101] From the perspective of preventing a decrease in breakdown voltage, this problem can be avoided by setting the width of the spacing between the multiple second extension portions 122 (the multiple first extension portions 132) extremely narrow. However, the spacing between the multiple second extension portions 122 depends on the second pillar width W2 of each of the multiple second pillar regions 12 in the active region 10. Narrowing the second pillar width W2 of each of the multiple second pillar regions 12 leads to a narrower current path. In other words, considering the current characteristics, it is not necessarily preferable to set the width of the spacing between the multiple second extension portions 122 (the multiple first extension portions 132) extremely narrow.

[0102] As described above, in this embodiment, the width W10 of the multiple first extension portions 132 sandwiched between the multiple second extension portions 122 also changes in the first direction Y. Therefore, even if there is an error (variation) in at least one of the dimensions and the impurity concentration of the second pillar region 12, charge balance can be ensured at any position in the first direction Y in the first extension portion 132.

[0103] Specifically, referring to Figures 7 and 8, when the dimensions and impurity concentrations of the multiple second extension portions 122 have no error (variation) from the intended dimensions and intended impurity concentrations, in the multiple first extension portions 132, the depletion layer S1 extending from one pn junction and the depletion layer S1 extending from the other pn junction are connected throughout the entire area in the first direction Y.

[0104] In contrast, if there is an error (variation) in at least one of the dimensions and impurity concentration of the second extension portion 122, the depletion layer S2 extending from one pn junction and the depletion layer S2 extending from the other pn junction may not be connected at the first outer end portion 135 of the multiple first extension portions 132 (Figure 8).

[0105] Even in this case, the depletion layer S2 extending from one pn junction and the depletion layer S2 extending from the other pn junction are connected at the first inner ends 134 of the first extensions 132 ( FIG. 7 ). That is, charge balance can be ensured at any position in the first direction Y on the first extensions 132.

[0106] Therefore, according to the semiconductor device 1A of this embodiment, it is possible to ensure at least the necessary breakdown voltage even if there are errors (variations) in the dimensions, impurity concentrations, etc. of the multiple second extension portions 122. In other words, it is possible to provide a semiconductor device 1A that has high robustness with respect to the breakdown voltage of the outer circumferential region 11.

[0107] Furthermore, according to this embodiment, the width-varying portion 14 is set in the second extending portion 122 arranged in the outer peripheral region 11. The requirement for withstand voltage for the outer peripheral region 11 is relatively strict. By setting the width-varying portion 14 in the second extending portion 122 arranged in the outer peripheral region 11, the robustness of the withstand voltage of the outer peripheral region 11 can be improved.

[0108] Furthermore, the second extension portion 122 and the first extension portion 132 disposed in the peripheral region 11 are not required to function as a current path. This allows for a high degree of freedom in the layout of the planar shape of the second extension portion 122. In other words, by providing the width-varying portion 14 in the second extension portion 122, the robustness of the withstand voltage of the peripheral region 11 can be increased without affecting the current characteristics of the chip 2.

[0109] In this embodiment, in the first tapered portion 14A, the width W20 of the second extending portion 122 narrows toward the side surfaces 5A and 5C. In other words, the width W10 of the multiple first extending portions 132 sandwiched between the multiple second pillar regions 12 widens toward the side surfaces 5A and 5C.

[0110] The depletion layers that extend from one pn junction and the other pn junction in the first extending portion 132 and connect to each other are unlikely to expand laterally from the connection position. Therefore, if the width W10 of the multiple first extending portions 132 narrows toward the side surfaces 5A and 5C, it would be difficult for the depletion layers to expand from the connection position toward the side surfaces 5A and 5C.

[0111] In contrast, in this embodiment, the width W10 of the multiple first extension portions 132 increases toward the side surfaces 5A and 5C. This allows the mutually connected depletion layers to expand toward the side surfaces 5A and 5C. This allows for a further improvement in the breakdown voltage in the peripheral region 11.

[0112] In this embodiment, the chip 2 includes SiC. In addition to the method described in this embodiment, a method of varying the width W20 of the second extension portion 122 in the depth direction of the chip 2 can also be considered as a method for improving the robustness of the outer peripheral region 11 with respect to the breakdown voltage. However, when the chip 2 includes SiC, forming an epitaxial layer in multiple stages (multi-epi) is usually not adopted due to manufacturing time and space constraints. Therefore, when the chip 2 includes SiC, the above method cannot be adopted.

[0113] In contrast, in this embodiment, the width W20 in the second direction X is changed in the width-changing portion 14. This ensures charge balance at any position in the first direction Y in the width-changing portion 14. Therefore, even if the chip 2 contains SiC, the robustness of the withstand voltage of the outer circumferential region 11 can be improved.

[0114] 8 to 19, first to eleventh embodiments of the second pillar region 12 will be described below. The second pillar regions 12 may have at least one of the features shown in the first to eleventh embodiments. The second pillar regions 12 may have a feature that combines a plurality (two or more) of the features shown in the first to eleventh embodiments.

[0115] 8 to 19 show the cross-sectional shape of the second main body portion 121 as the second pillar region 12. In the first to eleventh embodiments, the second extension portion 122 of the second pillar region 12 (FIGS. 6 to 8, etc.) may have the same cross-sectional shape as the second main body portion 121.

[0116] 9 is a cross-sectional perspective view showing the second pillar region 12 according to the first embodiment. Referring to Fig. 9, the second pillar region 12 has a thickness less than the epitaxial thickness TE of the stacked portion 7, and is formed in the stacked portion 7 (drift region 8) at a distance from the upper end of the stacked portion 7. Specifically, the second upper end 12b of the second pillar region 12 is formed at a distance from the upper end (first main surface 3) of the stacked portion 7 toward the lower end, and faces the first main surface 3 with a part (upper end) of the stacked portion 7 in between.

[0117] 10 is a cross-sectional perspective view showing a second pillar region 12 according to the second embodiment. Referring to Fig. 10, the second pillar region 12 has a thickness less than the epitaxial thickness TE of the stacked layer 7, and is formed in the stacked layer 7 (drift region 8) at a distance from the lower end of the stacked layer 7. Specifically, a second lower end 12a of the second pillar region 12 is formed at a distance from the lower end (base layer 6) of the stacked layer 7 toward the upper end, and faces the base layer 6 with a part (lower end) of the stacked layer 7 in between.

[0118] 11 is a cross-sectional perspective view showing a second pillar region 12 according to a third embodiment. Referring to FIG. 11 , the second pillar region 12 has a thickness less than the epitaxial thickness TE of the stacked portion 7 and is formed in the stacked portion 7 (drift region 8) at a distance from both the lower and upper ends of the stacked portion 7. Specifically, the second upper end 12b of the second pillar region 12 is formed at a distance from the upper end (first main surface 3) of the stacked portion 7 toward the lower end and faces the first main surface 3 across a portion (upper end) of the stacked portion 7. Meanwhile, the second lower end 12a of the second pillar region 12 is formed at a distance from the lower end (base layer 6) of the stacked portion 7 toward the upper end and faces the base layer 6 across a portion (lower end) of the stacked portion 7.

[0119] 12 is a cross-sectional perspective view showing a second pillar region 12 according to a fourth embodiment. Referring to Fig. 12, each of the multiple second pillar regions 12 has a stacked structure including a first region 18 and a second region 19 in the thickness direction of the stacked portion 7. In this embodiment, the first region 18 and the second region 19 are arranged at intervals from each other in the thickness direction of the stacked portion 7. The first region 18 and the second region 19 may have different p-type impurity concentrations.

[0120] A part of the stacked layer 7 (drift region 8) is interposed between the first region 18 and the second region 19. The part of the drift region 8 provides an n-type intermediate region 25 that physically separates the first region 18 and the second region 19. The intermediate region 25 may be located at the center of the stacked layer 7 in the thickness direction, or at the upper or lower end side relative to the center position.

[0121] 13 is a cross-sectional perspective view showing a second pillar region 12 according to a fifth embodiment. Referring to FIG. 13, each of the multiple second pillar regions 12 has a stacked structure including a first region 18 and a second region 19 in the thickness direction of the laminated unit 7. In this embodiment, the first region 18 and the second region 19 are connected to each other in the thickness direction of the laminated unit 7. A boundary 26 between the first region 18 and the second region 19 may be located in the center of the thickness direction of the laminated unit 7, or may be located on the upper or lower end side of the center position.

[0122] Fig. 14 is a cross-sectional perspective view showing a second pillar region 12 according to a sixth embodiment. Fig. 15 is a cross-sectional perspective view showing a second pillar region 12 according to a seventh embodiment. With reference to Figs. 14 and 15 , the second pillar region 12 having a second upper end 12b at a position spaced apart from the upper end of the laminated portion 7 may have a laminated structure including a first region 18 and a second region 19.

[0123] Fig. 16 is a cross-sectional perspective view showing a second pillar region 12 according to an eighth embodiment. Fig. 17 is a cross-sectional perspective view showing a second pillar region 12 according to a ninth embodiment. With reference to Figs. 16 and 17 , the second pillar region 12 having a second lower end 12a at a position spaced apart from the lower end of the laminated portion 7 may have a laminated structure including a first region 18 and a second region 19.

[0124] Fig. 18 is a cross-sectional perspective view showing a second pillar region 12 according to a tenth embodiment. Fig. 19 is a cross-sectional perspective view showing a second pillar region 12 according to an eleventh embodiment. With reference to Figs. 18 and 19 , the second pillar region 12 having a second upper end 12b and a second lower end 12a at positions spaced apart from the upper and lower ends of the laminated portion 7, respectively, may have a laminated structure including a first region 18 and a second region 19.

[0125] Below, examples of device structures formed in the active region 10 are shown. Fig. 20 is a plan view showing a main part of the active region 10. Fig. 21 is a cross-sectional perspective view showing a gate structure 35 according to a first example. Fig. 22 is a cross-sectional view showing a main part of the peripheral region 11. Fig. 23A is a cross-sectional view taken along line XXIIIA-XXIIIA shown in Fig. 3. Fig. 23B is a cross-sectional view taken along line XXIIIB-XXIIIB shown in Fig. 23A.

[0126] 21 illustrates the second pillar region 12 according to the third embodiment. Of course, a configuration in which any one or more of the second pillar regions 12 according to the basic embodiment and the first to eleventh embodiments is applied may also be applied to FIG.

[0127] 20 and 21 , in this embodiment, the semiconductor device 1A includes a metal insulator semiconductor (MIS) structure 31 as an example of a device structure formed in the active region 10. The MIS structure 31 may also be referred to as a "field effect transistor structure."

[0128] The semiconductor device 1A includes a plurality of p-type body regions 32 formed in the active region 10. In this embodiment, the plurality of body regions 32 are arranged at intervals in the second direction X and are each formed in a strip shape extending in the first direction Y. That is, the plurality of body regions 32 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. In other words, the extension direction of the plurality of body regions 32 coincides with the off-direction Doff of the SiC single crystal. Furthermore, the extension direction of the plurality of body regions 32 coincides with the extension direction of the plurality of second pillar regions 12.

[0129] The body regions 32 are formed in the surface layer portion of the first main surface 3 so as to overlap the second pillar regions 12 corresponding to them in the stacking direction. Specifically, the body regions 32 overlap the second pillar regions 12 in a one-to-one correspondence in the stacking direction.

[0130] When the multiple second pillar regions 12 are formed at intervals from the first main surface 3, the multiple body regions 32 are each formed in a region between the first main surface 3 and the second upper ends 12b (see FIG. 11) of the multiple second pillar regions 12. The multiple body regions 32 are preferably formed on the first main surface 3 side of the intermediate thickness range of the stacked unit 7, and are exposed from the first main surface 3. The multiple body regions 32 are preferably connected to the corresponding second pillar regions 12 (second upper ends 12b).

[0131] The plurality of body regions 32 are each formed wider than the second pillar region 12 directly below them, and are formed at intervals from the adjacent plurality of second pillar regions 12 toward the second pillar region 12 directly below them. The plurality of body regions 32 expose a portion of the first pillar region 13 from a region of the first main surface 3 between the adjacent plurality of second pillar regions 12.

[0132] The plurality of body regions 32 may be, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0133] The p-type impurity concentrations of the plurality of body regions 32 are preferably adjusted by at least one trivalent element. The trivalent element of the body region 32 may be the same as or different from the trivalent element of the second pillar region 12, etc. The trivalent element of the body region 32 may be at least one of boron, aluminum, gallium, and indium.

[0134] The semiconductor device 1A includes one or more n-type source regions 33 formed in the surface layer portions of the plurality of body regions 32 in the active region 10. In this embodiment, a plurality of (two in this embodiment) source regions 33 are formed at intervals in the surface layer portion of each body region 32. The plurality of source regions 33 have an n-type impurity concentration higher than the n-type impurity concentration of the first pillar region 13 and the drift region 8 of the stacked portion 7. The plurality of source regions 33 have an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more２１ cm －３ The n-type impurity concentration may have the following peak value:

[0135] The multiple source regions 33 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the multiple source regions 33 may be formed at intervals along the extension direction of the corresponding body region 32. The multiple source regions 33 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 32. The multiple source regions 33, together with the multiple first pillar regions 13, define a channel (current path) along the first main surface 3 at the periphery of the body region 32.

[0136] The semiconductor device 1A includes one or more p-type contact regions 34 formed in the surface layer portions of the plurality of body regions 32 in the active region 10. The contact regions 34 may also be referred to as "back gate regions." In this embodiment, one contact region 34 is formed in a region between the plurality of adjacent source regions 33 in the surface layer portion of each body region 32.

[0137] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second pillar regions 12. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of second pillar regions 12. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0138] The plurality of contact regions 34 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the plurality of contact regions 34 may also be formed at intervals along the extension direction of the corresponding body region 32. The plurality of contact regions 34 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the peripheral edge of the corresponding body region 32.

[0139] The semiconductor device 1A includes a plurality of planar electrode type gate structures 35 arranged on the first main surface 3 in the active region 10. The gate structures 35 may also be referred to as "planar gate structures." The plurality of gate structures 35 are arranged at intervals on the first main surface 3 so as to overlap at least one body region 32 (channel) in the stacking direction. A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control the inversion and non-inversion of the channel (current path) in the body region 32 in response to the gate potential.

[0140] In this embodiment, the multiple gate structures 35 are arranged at intervals in the second direction X and are each formed in a strip shape extending in the first direction Y. That is, the multiple gate structures 35 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. In other words, the extension direction of the multiple gate structures 35 coincides with the off-direction Doff of the SiC single crystal. Furthermore, the extension direction of the multiple gate structures 35 coincides with the extension direction of the multiple second pillar regions 12.

[0141] The plurality of gate structures 35 are arranged shifted from the plurality of second pillar regions 12 toward the plurality of first pillar regions 13, and overlap the plurality of first pillar regions 13 in a one-to-one correspondence in the stacking direction. In this embodiment, the plurality of gate structures 35 are each arranged to straddle two adjacent body regions 32, and each cover the plurality of source regions 33 located in one and the other body regions 32.

[0142] Each of the plurality of gate structures 35 has a stacked structure including a gate insulating film 36 disposed on the first main surface 3 and a gate electrode 37 disposed on the gate insulating film 36. The gate insulating film 36 may include a silicon oxide film. The gate electrode 37 may include conductive polysilicon.

[0143] Either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as to partially overlap the second pillar region 12 in the stacking direction. Of course, either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as not to partially overlap the second pillar region 12 in the stacking direction.

[0144] 23A and 23B , semiconductor device 1A includes a plurality of p-type outer body regions 51 formed in a surface layer portion of first main surface 3 in peripheral region 11. In this embodiment, the plurality of outer body regions 51 are arranged at intervals in second direction X and are each formed in a strip shape extending in first direction Y. The extension direction of the plurality of outer body regions 51 coincides with the extension direction of the plurality of second pillar regions 12 (second extension portions 122).

[0145] The outer body region 51 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 32. Of course, the p-type impurity concentration of the outer body region 51 may be lower than the p-type impurity concentration of the body region 32 or higher than the p-type impurity concentration of the body region 32.

[0146] The outer body regions 51 are formed on the surface layer portion of the first main surface 3 so as to overlap the second extension portions 122 of the second pillar regions 12 corresponding to them in the stacking direction. The outer body regions 51 overlap the second pillar regions 12 in a one-to-one correspondence in the stacking direction.

[0147] The outer body regions 51 extend from a position adjacent to the body region 32 closest to the outer circumferential region 11 toward the side surfaces 5A and 5C (first side surface 5A in FIG. 23A).

[0148] 23A , the outer body regions 51 have inner end portions 51 a and outer end portions 51 b. The inner end portions 51 a of the outer body regions 51 are aligned with the second inner end portions 124 of the second extension portions 122 in the first direction Y. The inner end portions 51 a of the outer body regions 51 are connected to the body region 32 closest to the outer circumferential region 11.

[0149] The outer end 51b of the outer body region 51 is formed at a distance from the periphery (side surfaces 5A and 5C) of the first main surface 3 toward the active region 10. The outer end 51b of the outer body region 51 is substantially aligned with the second outer end 125 of the second extension portion 122 in the first direction Y. As shown in FIG. 23A , the outer end 51b may slightly protrude beyond the second outer end 125 of the second extension portion 122 toward the side surfaces 5A and 5C (first side surface 5A in FIG. 23A ).

[0150] In a plan view, the outer body regions 51 overlap the second extension portions 122 of the second pillar regions 12, respectively. The outer body regions 51 do not face the first extension portions 132 of the first pillar regions 13 in the depth direction of the chip 2.

[0151] 23B , both side edges of each outer body region 51 in the second direction X are aligned with both side edges 126 of the corresponding second extension 122 in the second direction X. In this configuration, the width WB of one outer body region 51 is equal to the width W20 of the second extension 122 (width WB = width W20). The width WB of one outer body region 51 is narrower than the width WA ( FIG. 21 ) of one body region 32 (width WB < width WA).

[0152] 21 to 23B, the semiconductor device 1A includes an insulating layer 40 covering the first main surface 3. The insulating layer 40 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the insulating layer 40 has a stacked structure including a first insulating film 41 and a second insulating film 42 (see FIG. 22, etc.). The first insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 41 include a silicon oxide film made of an oxide of the chip 2 (stacked portion 7).

[0153] The first insulating film 41 selectively covers the first main surface 3 in the active region 10 and the peripheral region 11. The first insulating film 41 covers the region outside the gate insulating film 36 in the active region 10 and is connected to the gate insulating film 36. In this embodiment, the first insulating film 41 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the first insulating film 41 may be formed at a distance inward from the periphery of the first main surface 3, with the stacked portion 7 exposed from the periphery of the first main surface 3.

[0154] The second insulating film 42 is stacked on the first insulating film 41. The second insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating layer 40 preferably includes a silicon oxide film. The second insulating film 42 covers the first main surface 3 in the active region 10 and the peripheral region 11, sandwiching the first insulating film 41 therebetween.

[0155] The second insulating film 42 covers the multiple gate structures 35 in the active region 10. In this embodiment, the second insulating film 42 is continuous with the periphery of the first main surface 3. Of course, the second insulating film 42 may be formed at a distance inward from the periphery of the first main surface 3, and may expose the periphery of the first main surface 3 together with the first insulating film 41.

[0156] 21 , the semiconductor device 1A includes a plurality of contact openings formed in an insulating layer 40. The plurality of contact openings include a plurality of contact openings (not shown) exposing a plurality of gate structures 35 (gate electrodes 37) and a plurality of source contact openings 43 exposing a plurality of source regions 33.

[0157] The source contact openings 43 are formed in regions between adjacent gate structures 35, exposing the source regions 33 and the contact regions 34. In this embodiment, the source contact openings 43 are arranged in strips along the first direction Y at intervals in the second direction X. In other words, the source contact openings 43 extend in a direction crossing the superjunction structure SJ.

[0158] Specifically, the source contact openings 43 are arranged in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the first side surface 5A side (FIG. 1). The source contact openings 43 are arranged in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the third side surface 5C side (FIG. 1). In FIG. 1, for simplicity of illustration, the source contact openings 43 are depicted as a single opening (two in total).

[0159] 1 , semiconductor device 1A includes a gate pad 45 disposed on insulating layer 40. Gate pad 45 is an electrode to which a gate potential is applied from the outside. Gate pad 45 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. Gate pad 45 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the insulating layer 40 side.

[0160] In this embodiment, the gate pad 45 is disposed on a portion of the insulating layer 40 that covers the active region 10. The gate pad 45 may be disposed at a distance from the outer periphery region 11 toward the active region 10. In this embodiment, the gate pad 45 is disposed on the periphery of the active region 10 in plan view.

[0161] 1 shows an example in which the gate pad 45 is arranged in a region along the center of the second side surface 5B on the periphery of the active region 10. Of course, the gate pad 45 may also be arranged in a region along the center of any of the first to fourth side surfaces 5A to 5D. Of course, the gate pad 45 may also be arranged at any corner of the active region 10 in a plan view. Also, the gate pad 45 may be arranged in the center of the active region 10 in a plan view. In this embodiment, the gate pad 45 is formed in a quadrangular shape in a plan view.

[0162] The semiconductor device 1A includes at least one gate wiring 46 (multiple in this embodiment) extending from the gate pad 45 onto the insulating layer 40. The gate wiring 46 may also be referred to as a "wiring" or "wiring electrode." The multiple gate wirings 46 may have a layered structure including a Ti-based metal film and an Al-based metal film stacked in this order from the insulating layer 40 side. In this embodiment, the multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0163] The first gate wiring 46A is drawn out from the gate pad 45 toward the first side surface 5A and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, one end) of the multiple gate structures 35. The first gate wiring 46A penetrates the insulating layer 40 via multiple gate contact openings (not shown) and is electrically connected to one end of the multiple gate structures 35.

[0164] The second gate wiring 46B is drawn out from the gate pad 45 toward the third side surface 5C and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, the other end portions) of the multiple gate structures 35. The second gate wiring 46B penetrates the insulating layer 40 via the multiple source contact openings 43 and is electrically connected to the other end portions of the multiple gate structures 35.

[0165] 1 , semiconductor device 1A includes a source pad (first main surface electrode) 47 disposed on insulating layer 40 at a distance from gate pad 45 and gate wiring 46. Source pad 47 is an electrode to which a source potential is applied from the outside. Source pad 47 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. Source pad 47 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the insulating layer 40 side.

[0166] The source pad 47 is disposed on a portion of the insulating layer 40 that covers the active region 10. The source pad 47 may be disposed at an interval from the peripheral region 11 toward the active region 10. In this embodiment, the source pad 47 is formed in a polygonal shape having a recess that is recessed along the gate pad 45 in a plan view. Of course, the source pad 47 may also be formed in a quadrangular shape in a plan view.

[0167] The active region 10 includes at least a region covered by the source pad 47. More specifically, when the source pad 47 has a substantially rectangular (polygonal) shape with four sides along the periphery of the chip 2, the active region 10 is a region inside the four sides. The active region 10 is a region that does not face the gate wiring 46 in the vertical direction Z.

[0168] The source pad 47 is electrically connected to the body regions 32, the source regions 33, and the contact regions 34 via source contact portions (first contact portions) 50 that penetrate the insulating layer 40. The source contact portions 50 include source contact openings 43 and a wiring layer that penetrates the source contact openings 43. The wiring layer may include a portion of the source pad 47.

[0169] The plurality of source contact portions 50 are electrically connected to both the source pad 47 and the plurality of body regions 32. That is, the source pad 47 is electrically connected to the plurality of second pillar regions 12 via the plurality of body regions 32.

[0170] The multiple source contact portions 50 extend in a direction crossing the superjunction structure SJ. Specifically, the multiple source contact portions 50 are arranged in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the first side surface 5A side (FIG. 1). The multiple source contact portions 50 are arranged in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the third side surface 5C side (FIG. 1). In FIG. 1, for simplicity of illustration, the multiple source contact portions 50 are depicted as a single contact portion (two in total).

[0171] The plurality of source contact portions 50 may be arranged in a rectangular ring shape along the boundary between the active region 10 and the peripheral region 11 .

[0172] The source contact portion 50 may be a single contact portion extending in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the first side surface 5A side. The source contact portion 50 may be a single source contact portion extending in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the third side surface 5C side.

[0173] The source contact portion 50 may be a single source contact portion extending in a rectangular ring shape along the boundary between the active region 10 and the outer peripheral region 11 on the first side surface 5A side.

[0174] 2 , the semiconductor device 1A includes a drain pad 48 covering the second main surface 4. The drain pad 48 is an electrode to which a drain potential is applied from the outside. The drain pad 48 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 48 forms an ohmic contact with the base layer 6 exposed from the second main surface 4. In other words, the drain pad 48 is electrically connected to the stacked portion 7 (the drift region 8 and the plurality of first pillar regions 13) via the base layer 6.

[0175] The drain pad 48 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 48 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0176] The breakdown voltage that can be applied between source pad 47 and drain pad 48 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0177] As described above, according to the semiconductor device 1A, the width W20 of each of the plurality of second extending portions (predetermined sections) 122 varies in the first direction Y in the width varying portions 14. In this case, the width W10 of each of the plurality of first extending portions 132 sandwiched between the width varying portions 14 of the plurality of second extending portions 122 also varies in the first direction Y. Therefore, even if an error (variation) occurs in at least one of the spacing and impurity concentration of the plurality of second extending portions 122, charge balance can be ensured at any position in the first direction Y in the first extending portion 132, and at least the required withstand voltage can be ensured. In other words, a semiconductor device 1A having high robustness with respect to withstand voltage can be provided.

[0178] FIG. 24 is a plan view showing a second embodiment of the second extending portion 122, and corresponds to FIG.

[0179] 24 , the width-varying portion 14 of the second extending portion 122 includes a first tapered portion 14A and a constant width portion 54. The constant width portion 54 is a strip-shaped portion extending along the first direction Y. The constant width portion 54 has a constant width over the entire area in the first direction Y.

[0180] The constant width portion 54 connects the first tapered portion 14A and the outer end (end) 123 of the second main body portion (main body portion) 121 of the second pillar region 12. The width of the constant width portion 54 is approximately equal to the first width W21, which is the maximum width of the first tapered portion 14A (width-varying portion 14). In addition, the constant width portion 54 is approximately equal to the second pillar width W2 of the second main body portion 121 of the second pillar region 12.

[0181] According to the second embodiment of the second extending portion 122, the same effects as those of the first embodiment of the second extending portion 122 are achieved.

[0182] FIG. 25 is a plan view showing a third embodiment of the second extending portion 122, and corresponds to FIG.

[0183] 25 , in the third embodiment of the second extending portion 122, the width-changing portion 14 of the second extending portion 122 is a second tapered portion (tapered portion) 14B whose width W20 increases toward the side surfaces 5A and 5C ( FIG. 3 ; in the example of FIG. 6 , the first side surface 5A) in the first direction Y. The width W20 of the plurality of second tapered portions 14B increases from the plurality of source contact portions 50 toward the second outer end portion 125.

[0184] In a plan view, the two side portions 126 of the second extending portion 122 are inclined so as to move away from each other from the second inner end portion 124 toward the second outer end portion 125. The angle θ2 formed between each side portion 126 and the second outer end portion 125 (end face) is equal to or greater than 85° and less than 90°. The angle θ2 is the angle formed between each side portion 126 and a direction perpendicular to the extension direction of the second pillar region 12 (i.e., the second direction X).

[0185] The angle θ2 may have a value belonging to any one of the ranges of 85.0° to 86.0°, 86.0° to 87.0°, 87.0° to 88.0°, 88.0° to 89.0°, and 89.0° to less than 90.0°. The angle θ2 is preferably 87.0° to 89.0°. The angle θ2 is even more preferably 87.5° to 88.5°.

[0186] In the second tapered portion 14B (width-varying portion 14), the width W20 of the second extending portion 122 varies within a range between a first width W21, which is the minimum width, and a second width W22, which is the maximum width. The first width W21 is the width of the second extending portion 122 at the second inner end portion 124. The first width W21 is equal to the second pillar width W2 of the second main body portion 121 in the second pillar region 12.

[0187] The second width W22 is the width of the second extending portion 122 at the second outer end portion 125. In the third embodiment of the second extending portion 122, the width ratio (%) of the second width W22 to the first width W21 is greater than 100% and less than 110%. In other words, the second width W22 is 10% or less of the first width W21.

[0188] The width ratio (W22 / W21) (%) of the second width W22 to the first width W21 may have a value belonging to any one of the ranges of more than 100% to 101% or less, 101% to 102%, 102% to 103%, 103% to 104%, 104% to 105%, 105% to 106%, 106% to 107%, 107% to 108%, 108% to 109%, and 109% to less than 1100%.

[0189] According to the third embodiment of the second extending portion 122, the same effects as those of the first embodiment of the second extending portion 122 are achieved.

[0190] FIG. 26 is a plan view showing a fourth embodiment of the second extending portion 122, and corresponds to FIG.

[0191] Referring to Figure 26, in a fourth embodiment of the second extension portion 122, the width-changing portion 14 of the second extension portion 122 includes, on both sides in the second direction X, a protruding portion 14C from which the second extension portion 122 selectively protrudes, and a constricted portion 14D that is continuous with the protruding portion 14C in the first direction Y and from which the second extension portion 122 selectively constricts.

[0192] The second extension portion 122 includes two first side portions 127 facing each other in the second direction X, two second side portions 128 facing each other in the second direction X, and two third side portions 129 facing each other in the second direction X. The first side portions 127, the second side portions 128, and the third side portions 129 are arranged in this order from the side surfaces 5A and 5C ( FIG. 3 ; in the example of FIG. 6 , the first side surface 5A) toward the active region 10.

[0193] The two first side portions 127 connect both ends of the second outer end portion 125 in the second direction X to the two second side portions 128, respectively. The two second side portions 128 connect the two first side portions 127 to the two third side portions 129, respectively. The two third side portions 129 connect the two second side portions 128 to both ends of the second inner end portion 124 in the second direction X, respectively.

[0194] In a plan view, the two first side portions 127 of the second extending portion 122 are inclined so as to approach each other from the second inner end portion 124 toward the second outer end portion 125. The angle θ3 formed between each first side portion 127 and the second outer end portion 125 (end face) is greater than 90.0° and not greater than 95.0°. The angle θ3 is the angle formed between each first side portion 127 and a direction perpendicular to the extension direction of the second pillar region 12 (i.e., the second direction X).

[0195] The angle θ3 may have a value belonging to any one of the following ranges: greater than 90.0° and not greater than 91.0°, 91.0° or greater and not greater than 92.0°, 92.0° or greater and not greater than 93.0°, 93.0° or greater and not greater than 94.0°, and 94.0° or greater and not greater than 95.0°. The angle θ3 is preferably not less than 91.0° and not greater than 93.0°. The angle θ3 is even more preferably not less than 91.5° and not greater than 92.5°.

[0196] The two second side portions 128 of the second extending portion 122 are inclined in a plan view so as to move away from each other from the second inner end portion 124 toward the second outer end portion 125. The angle θ4 formed between each second side portion 128 and the second outer end portion 125 (end face) is equal to or greater than 85° and less than 90°. The angle θ4 is the angle formed between each second side portion 128 and a direction perpendicular to the extension direction of the second pillar region 12 (i.e., the second direction X).

[0197] The angle θ4 may have a value belonging to any one of the ranges of 85.0° to 86.0°, 86.0° to 87.0°, 87.0° to 88.0°, 88.0° to 89.0°, and 89.0° to less than 90.0°. The angle θ4 is preferably 87.0° to 89.0°. The angle θ4 is even more preferably 87.5° to 88.5°. The sum of the angle θ4 and the angle θ3 is preferably 180°.

[0198] The two third side portions 129 of the second extending portion 122 are inclined in a plan view so as to approach each other from the second inner end portion 124 toward the second outer end portion 125. The angle θ5 formed between each third side portion 129 and the second outer end portion 125 (end face) is greater than 90.0° and not greater than 95.0°. The angle θ5 is the angle formed between each third side portion 129 and a direction perpendicular to the extension direction of the second pillar region 12 (i.e., the second direction X).

[0199] The angle θ5 may have a value belonging to any one of the following ranges: greater than 90.0° and not greater than 91.0°; 91.0° or greater and not greater than 92.0°; 92.0° or greater and not greater than 93.0°; 93.0° or greater and not greater than 94.0°; and 94.0° or greater and not greater than 95.0°. The angle θ5 is preferably not less than 91.0° and not greater than 93.0°. The angle θ5 is even more preferably not less than 91.5° and not greater than 92.5°.

[0200] The angle θ5 is preferably equal to the angle θ3. The sum of the angle θ5 and the angle θ4 is preferably 180°.

[0201] None of the two first side portions 127, the two second side portions 128, and the two third side portions 129 are inclined with respect to the vertical direction Z. In other words, the width of the second extension portion 122 does not change in the depth direction of the chip 2.

[0202] In the fourth embodiment of the second extending portion 122, the protruding portion 14C is defined by the first side portion 127 and the outer portion of the second side portion 128. The constricted portion 14D is defined by the inner portion of the second side portion 128 and the third side portion 129.

[0203] In the protruding portion 14C and the constricted portion 14D (i.e., the width-changing portion 14), the maximum width W23 of the protruding portion 14C is wider than the minimum width W24 of the constricted portion 14D (W23 > W24). In the fourth embodiment of the second extending portion 122, the maximum width W23 of the protruding portion 14C is the same as the first width W21 of the second extending portion 122 at the second inner end portion 124 (W23 = W21). The maximum width W23 of the protruding portion 14C may be wider or narrower than the first width W21 of the second extending portion 122.

[0204] In the fourth embodiment of the second extending portion 122, the minimum width W24 of the constricted portion 14D is the same as the second width W22 of the second extending portion 122 at the second outer end 125 (W24 = W22). The minimum width W24 of the constricted portion 14D may be wider or narrower than the second width W22 of the second extending portion 122.

[0205] The width ratio (W24 / W23) (%) of the minimum width W24 of the constricted portion 14D to the maximum width W23 of the protruding portion 14C is 90% or more and less than 100%.

[0206] The width ratio (W24 / W23) (%) of the minimum width W24 of the constricted portion 14D to the maximum width W23 of the protrusion 14C may have a value belonging to any one of the ranges of 90% or more and 91% or less, 91% or more and 92% or less, 92% or more and 93% or less, 93% or more and 94% or less, 94% or more and 95% or less, 95% or more and 96% or less, 96% or more and 97% or less, 97% or more and 98% or less, 98% or more and 99% or less, and 99% or more and less than 100%.

[0207] The fourth embodiment of the second extending portion 122 provides the same advantageous effects as the first embodiment of the second extending portion 122 ( FIG. 6 ), as well as the following advantageous effects. Specifically, if the length L2 of the second extending portion 122 is long due to reasons such as a wide width of the outer peripheral region 11, attempting to address this with only the tapered portions (first tapered portion 14A, second tapered portion 14B, etc.) may result in the angles θ1 ( FIG. 6 ) and θ2 ( FIG. 25 ) becoming too close to 90°, potentially preventing the angles θ1 ( FIG. 6 ) and θ2 ( FIG. 25 ) from maintaining their optimal angle ranges. In this case, the withstand voltage of the outer peripheral region 11 may not be maintained high.

[0208] By including the protruding portion 14C and the constricted portion 14D in the width-varying portion 14, the angles θ3, θ4, and θ5 of the width-varying portion 14 can be maintained within an appropriate angle range even when the length L2 of the second extending portion 122 is long. This makes it possible to maintain a high pressure resistance in the outer circumferential region 11.

[0209] The number of each of the protruding portion 14C and the constricted portion 14D is not limited to one, and a plurality of each may be provided.

[0210] FIG. 27 is a plan view showing an example of the layout of the chip 2 according to the first modification of the first embodiment, and corresponds to FIG.

[0211] The chip 2 according to the first modified example shown in FIG. 27 includes at least one (preferably two or more and twenty or less) p-type field region 38 formed in the surface layer portion of the first main surface 3 in the peripheral region 11.

[0212] The number of field regions 38 is typically 4 to 8. The field regions 38 are formed in an electrically floating state and relieve the electric field within chip 2 at the periphery of first main surface 3. The number, width, depth, p-type impurity concentration, etc. of field regions 38 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0213] The multiple field regions 38 are formed at intervals in a region between the periphery of the chip 2 and the active region 10. The multiple field regions 38 are formed in strip shapes extending along the active region 10 in a plan view. Each of the multiple field regions 38 has a portion extending in a strip shape in the first direction Y and a portion extending in a strip shape in the second direction X. In this embodiment, the multiple field regions 38 are formed in an annular shape (specifically, a quadrangular annular shape) surrounding the multiple second pillar regions 12 in a plan view.

[0214] The multiple field regions 38 are formed in the stack 7 at intervals from the lower end of the stack 7 (drift region 8) toward the first main surface 3, and each form a p-n junction with the drift region 8. The multiple field regions 38 preferably have bottoms located on the first main surface 3 side of the intermediate portion of the thickness range of the stack 7. In this embodiment, the multiple field regions 38 are formed at intervals from the multiple second pillar regions 12 toward the periphery of the chip 2. Therefore, the multiple field regions 38 do not face the multiple second pillar regions 12 in the stacking direction.

[0215] The bottoms of the plurality of field regions 38 may be located closer to the first main surface 3 than the depth position of the second upper end 12b of the second pillar region 12. Of course, the bottoms of the plurality of field regions 38 may be located closer to the second lower end 12a of the second pillar region 12 than the depth position of the second upper end 12b of the second pillar region 12. In this case, the bottoms of the plurality of field regions 38 are preferably located closer to the first main surface 3 than the intermediate portion of the thickness range of the second pillar region 12.

[0216] The field regions 38 may have a thickness approximately equal to that of the body regions 32 (outer body region 51). In this case, the field regions 38 can be formed simultaneously with the body regions 32 (outer body region 51). Of course, the thickness of the field regions 38 may be greater than that of the body regions 32 (outer body region 51). Alternatively, the thickness of the field regions 38 may be smaller than that of the body regions 32 (outer body region 51).

[0217] The plurality of field regions 38 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0218] The p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 32 (outer body region 51). Of course, the p-type impurity concentrations of the plurality of field regions 38 may be higher than the p-type impurity concentrations of the plurality of body regions 32 (outer body regions 51). Furthermore, the p-type impurity concentrations of the plurality of field regions 38 may be lower than the p-type impurity concentrations of the plurality of body regions 32 (outer body regions 51).

[0219] The p-type impurity concentrations of the multiple field regions 38 are preferably adjusted by at least one trivalent element. The trivalent element in the field regions 38 may be the same as the trivalent element in the second pillar regions 12, etc., or may be a different species from the trivalent element in the second pillar regions 12, etc. The trivalent element in the field regions 38 may be at least one of boron, aluminum, gallium, and indium.

[0220] The plurality of field regions 38 preferably have a width different from the second pillar width W2 of the second pillar region 12. In other words, the electric field relaxation effect of the plurality of field regions 38 is preferably adjusted separately from the plurality of second pillar regions 12.

[0221] It is particularly preferable that the width of the multiple field regions 38 be larger than the second pillar width W2 of the second pillar region 12. Of course, the width of the multiple field regions 38 may be smaller than the second pillar width W2. Alternatively, the width of the multiple field regions 38 may be approximately equal to the second pillar width W2.

[0222] The field regions 38 are preferably formed at a pitch different from the second pitch P2 of the second pillar regions 12. It is particularly preferable that the pitch of the field regions 38 be larger than the second pitch P2. Of course, the pitch of the field regions 38 may be smaller than the second pitch P2. Alternatively, the pitch of the field regions 38 may be approximately equal to the second pitch P2.

[0223] FIG. 28 is a plan view showing an example of the layout of the chip 2 according to the second modification of the first embodiment, and corresponds to FIG.

[0224] The chip 2 according to the second modification shown in FIG. 28 includes a connection ring 55 that electrically connects the terminal ends of the second pillar regions 12 (the second outer ends 125 (FIG. 6) of the second extension portions 122).

[0225] The connection rings 55 are formed at intervals in the region between the periphery of the chip 2 and the active region 10. The connection rings 55 are formed in an annular shape (specifically, a rectangular annular shape) surrounding the plurality of second pillar regions 12 (second extension portions 122) and the plurality of outer body regions 51 (see also FIG. 23B ) in a plan view. The connection rings 55 are formed along the periphery of the chip 2 in a plan view. The connection rings 55 are formed along the boundary between the active region 10 and the outer periphery region 11 in a plan view.

[0226] The connecting ring 55 is adjacent to the end portions of the outer body regions 51. Specifically, the connecting ring 55 laterally contacts the end portions of the outer body regions 51. As described above, the outer body regions 51 overlap the second extension portions 122, respectively. This allows the outer body regions 51 and the second extension portions 122 to be electrically connected via the outer body regions 51.

[0227] Connection ring 55 is formed in stack 7 at a distance from the lower end of stack 7 (drift region 8) toward first main surface 3, and forms a pn junction with drift region 8. Connection ring 55 preferably has a bottom located on the first main surface 3 side of the intermediate portion of the thickness range of stack 7.

[0228] The connection ring 55 is formed in the stack 7 at a distance from the lower end of the stack 7 (drift region 8) toward the first main surface 3, and forms a p-n junction with the drift region 8. The connection ring 55 preferably has a bottom located on the first main surface 3 side of the intermediate portion of the thickness range of the stack 7. In this embodiment, the connection ring 55 is formed at a distance from the multiple second pillar regions 12 toward the peripheral edge of the chip 2. Therefore, the connection ring 55 does not face the multiple second pillar regions 12 in the stacking direction.

[0229] The bottom of the connection ring 55 may be located closer to the first main surface 3 than the depth position of the second upper end 12b of the second pillar region 12. Of course, the bottom of the connection ring 55 may be located closer to the second lower end 12a of the second pillar region 12 than the depth position of the second upper end 12b of the second pillar region 12. In this case, it is preferable that the bottom of the connection ring 55 is located closer to the first main surface 3 than the intermediate part of the thickness range of the second pillar region 12.

[0230] The connection ring 55 may have a thickness approximately equal to that of the plurality of body regions 32 (outer body region 51). In this case, the connection ring 55 can be formed simultaneously with the plurality of body regions 32 (outer body region 51). Of course, the thickness of the connection ring 55 may be greater than that of the plurality of body regions 32 (outer body region 51). Alternatively, the thickness of the connection ring 55 may be smaller than that of the plurality of body regions 32 (outer body region 51).

[0231] The connecting ring 55 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0232] The p-type impurity concentration of the connection ring 55 may be approximately equal to the p-type impurity concentration of the body region 32 (outer body region 51). Of course, the p-type impurity concentration of the connection ring 55 may also be higher than the p-type impurity concentrations of the plurality of body regions 32 (outer body regions 51). Alternatively, the p-type impurity concentration of the connection ring 55 may be lower than the p-type impurity concentrations of the plurality of body regions 32 (outer body regions 51).

[0233] The p-type impurity concentration of the connection ring 55 is preferably adjusted by at least one trivalent element. The trivalent element of the connection ring 55 may be the same as the trivalent element of the second pillar region 12, etc., or may be a different species from the trivalent element of the second pillar region 12, etc. The trivalent element of the connection ring 55 may be at least one of boron, aluminum, gallium, and indium.

[0234] Fig. 29 is a plan view showing a semiconductor device 1B according to a second embodiment of the present disclosure. Fig. 30 is a cross-sectional view taken along line XXX-XXX shown in Fig. 29. Fig. 31 is a plan view showing an example layout of a chip 2.

[0235] 29 to 31, semiconductor device 1B includes chip 2, base layer 6, stacked portion 7, active region 10 and peripheral region 11, similar to semiconductor device 1A.

[0236] The semiconductor device 1B includes a plurality of p-type second pillar regions 12 formed in the stacked portion 7 in the active region 10. The plurality of second pillar regions 12 are formed in the same layout as in the semiconductor device 1A.

[0237] 31 , each of the second pillar regions 12 includes one second main body portion 121 and two second extension portions 122 formed on both end portions of the second main body portion 121. The second extension portion 122 may have at least one of the features shown in the first to fourth embodiments. The second extension portion 122 may have a feature that combines multiple (two or more) features shown in the first to fourth embodiments.

[0238] The second pillar regions 12 may have at least one of the features shown in the basic form and the first to eleventh embodiments. The second pillar regions 12 may have a feature that combines two or more of the features shown in the basic form and the first to eleventh embodiments.

[0239] Furthermore, the chip 2 of the semiconductor device 1B may have at least one of the features shown in the first and second modified examples of the first embodiment.

[0240] Fig. 32 is a plan view showing a main part of the active region 10. Fig. 33 is a cross-sectional perspective view showing a gate structure 35 according to the first embodiment. With reference to Figs. 32 and 33, the semiconductor device 1B includes an MIS structure (device structure) 31 formed in the active region 10. The following components will be described as components of the semiconductor device 1B, but they are also components of the MIS structure 31.

[0241] The semiconductor device 1B includes a p-type body region 32 formed in a surface layer portion of the first main surface 3 .

[0242] The body region 32 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0243] The p-type impurity concentration of the body region 32 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 32 may be the same as or different from the trivalent element of the second pillar region 12, etc. The trivalent element of the body region 32 may be at least one of boron, aluminum, gallium, and indium.

[0244] The semiconductor device 1B includes a plurality of trench electrode type gate structures 35 formed on the first main surface 3 in the active region 10. The gate structures 35 may also be referred to as "trench gate structures." A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control inversion and non-inversion of a channel (current path) in the body region 32 in response to the gate potential.

[0245] In this embodiment, the multiple gate structures 35 are arranged in stripes extending in the extension direction of the multiple second pillar regions 12. Specifically, in this embodiment, the multiple gate structures 35 are arranged at intervals in the second direction X and are each formed in a band shape extending in the first direction Y.

[0246] That is, the multiple gate structures 35 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. In other words, the extending direction of the multiple gate structures 35 coincides with the off-direction Doff of the SiC single crystal. Furthermore, the extending direction of the multiple gate structures 35 coincides with the extending direction of the multiple second pillar regions 12.

[0247] In this embodiment, the multiple gate structures 35 are arranged shifted from the multiple second pillar regions 12 toward the multiple first pillar regions 13. Specifically, the multiple gate structures 35 penetrate the body region 32 at intervals from the multiple second pillar regions 12, and are arranged in a one-to-one correspondence within the multiple first pillar regions 13. In other words, the multiple gate structures 35 face the multiple second pillar regions 12 in the horizontal direction.

[0248] The multiple gate structures 35 are formed at intervals from the lower ends of the multiple first pillar regions 13 toward the first main surface 3, and face the multiple base layers 6 across parts of the multiple first pillar regions 13. The multiple gate structures 35 are preferably formed at intervals from intermediate portions of the thickness ranges of the multiple second pillar regions 12 toward the first main surface 3. Of course, the multiple gate structures 35 may also be formed at depth positions that cross the intermediate portions of the thickness ranges of the multiple second pillar regions 12.

[0249] Each gate structure 35 has a trench width WT in the second direction X and a trench depth DT in the vertical direction Z. The trench width WT is less than the second pitch P2. The trench depth DT is less than the second thickness T2 of the second pillar region 12.

[0250] The trench width WT may be 0.1 μm or more and 5 μm or less. The trench width WT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0251] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less.

[0252] Each gate structure 35 includes a trench 75, an insulating film 76, and a buried electrode 77. The trench 75 is formed in the first main surface 3 and defines the wall surface of the gate structure 35. The insulating film 76 covers the wall surface of the trench 75. The insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0253] In this embodiment, the insulating film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 76 includes a silicon oxide film made of an oxide of the chip 2. The buried electrode 77 is buried in the trench 75 with the insulating film 76 therebetween and faces the channel with the insulating film 76 therebetween. The buried electrode 77 may include p-type or n-type conductive polysilicon.

[0254] The semiconductor device 1B includes a plurality of source regions 33 formed on both sides of a plurality of gate structures 35 in a surface layer portion of the first main surface 3. The plurality of source regions 33 are formed in a surface layer portion of the body region 32. The plurality of source regions 33 have an n-type impurity concentration higher than the n-type impurity concentrations of the first pillar regions 13 and the drift region 8 of the stacked portion 7. The plurality of source regions 33 have an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0255] The multiple source regions 33 extend in a strip shape along the corresponding gate structures 35 in a plan view. The multiple source regions 33 are formed at intervals from the bottom of the body region 32 toward the first main surface 3, and face the first pillar regions 13 in the stacking direction, with part of the body region 32 sandwiched between them. The multiple source regions 33, together with the multiple first pillar regions 13 located directly below them, define channels (current paths) that extend along the wall surfaces of the corresponding gate structures 35.

[0256] The multiple source regions 33 may face the second pillar region 12 across a part of the body region 32 in the stacking direction. Of course, the multiple source regions 33 may be formed at intervals from the second pillar region 12 to the first pillar region 13 side (gate structure 35 side) so as not to face the second pillar region 12 in the stacking direction.

[0257] The semiconductor device 1B includes a plurality of contact regions 34 formed in regions between a plurality of gate structures 35 in a surface layer portion of the first main surface 3. The plurality of contact regions 34 are formed in a surface layer portion of the body region 32.

[0258] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second pillar regions 12. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of second pillar regions 12. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0259] The plurality of contact regions 34 are interposed in regions between the plurality of adjacent source regions 33, and extend in strip shapes along the plurality of gate structures 35. The plurality of contact regions 34 are formed at intervals from the bottom of the body region 32 toward the first main surface 3, and face the plurality of second pillar regions 12 with part of the body region 32 interposed therebetween in the stacking direction.

[0260] The multiple contact regions 34 may face the first pillar region 13 across a part of the body region 32 in the stacking direction. Of course, the multiple contact regions 34 may be formed at intervals from the first pillar region 13 toward the second pillar region 12 so as not to face the first pillar region 13 in the stacking direction.

[0261] The semiconductor device 1B includes the aforementioned insulating layer 40 covering the first main surface 3. The insulating layer 40 has a laminated structure including a first insulating film 41 and a second insulating film 42. In this embodiment, the first insulating film 41 selectively covers the first main surface 3. The first insulating film 41 is connected to the insulating film 76 in the active region 10, exposing the buried electrode 77.

[0262] In this embodiment, the first insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 41 may be formed at an interval inward from the periphery of the first main surface 3.

[0263] In this embodiment, the second insulating film 42 selectively covers the first main surface 3 with the first insulating film 41 sandwiched therebetween. The second insulating film 42 covers the plurality of gate structures 35 in the active region 10. In this embodiment, the second insulating film 42 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 42 may be formed at a distance inward from the periphery of the first main surface 3, and may expose the stacked portion 7 from the periphery of the first main surface 3 together with the first insulating film 41.

[0264] The semiconductor device 1B includes a plurality of contact openings formed in the insulating layer 40. The plurality of contact openings include a plurality of contact openings (not shown) exposing a plurality of gate structures 35 (gate electrodes 37) and a plurality of source contact openings 43 exposing a plurality of source regions 33.

[0265] The source contact openings 43 are formed in regions between adjacent gate structures 35, exposing the source regions 33 and the contact regions 34. In this embodiment, the source contact openings 43 are arranged in strips along the first direction Y at intervals in the second direction X. In other words, the source contact openings 43 extend in a direction crossing the superjunction structure SJ.

[0266] Specifically, the source contact openings 43 are arranged in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the first side surface 5A side (FIG. 29). The source contact openings 43 are arranged in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the third side surface 5C side (FIG. 29). In FIG. 29, for simplicity of illustration, the source contact openings 43 are depicted as a single opening (two in total).

[0267] Similar to the semiconductor device 1A, the semiconductor device 1B includes a gate pad 45, a plurality of gate wirings 46, a source pad 47, and a drain pad 48. The drain pad 48 is formed in the same form as in the first embodiment.

[0268] In this embodiment, the gate pad 45 is disposed on the active region 10 in a plan view. The gate pad 45 is disposed in a region close to the center of one side of the active region 10 in a plan view. Of course, the gate pad 45 may also be disposed in a corner of the active region 10 or in the center of the active region 10 in a plan view.

[0269] In this embodiment, the plurality of gate wirings 46 are arranged above the active region 10 in a plan view. The plurality of gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0270] The first gate wiring 46A is drawn out from the gate pad 45 toward the first side surface 5A and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, one end) of the multiple gate structures 35. The first gate wiring 46A penetrates the insulating layer 40 via the multiple source contact openings 43 and is electrically connected to one end of the multiple gate structures 35 (buried electrodes 77).

[0271] The second gate wiring 46B is drawn out from the gate pad 45 toward the third side surface 5C and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) some (specifically, the other ends) of the multiple gate structures 35. The second gate wiring 46B penetrates the insulating layer 40 via the multiple source contact openings 43 and is electrically connected to the other ends of the multiple gate structures 35 (buried electrodes 77).

[0272] In this embodiment, the source pad 47 is disposed above the active region 10 in a plan view. The source pad 47 is electrically connected to the body region 32, the source regions 33, and the contact regions 34 via a plurality of source contact portions (first contact portions) 50 that penetrate the insulating layer 40. The source contact portions 50 include a plurality of source contact openings 43 and a wiring layer that penetrates the source contact openings 43. The wiring layer may include a portion of the source pad 47.

[0273] The plurality of source contact portions 50 are electrically connected to both the source pad 47 and the plurality of body regions 32. That is, the source pad 47 is electrically connected to the plurality of second pillar regions 12 via the plurality of body regions 32.

[0274] The multiple source contact portions 50 extend in a direction transverse to the superjunction structure SJ. Specifically, the multiple source contact portions 50 are arranged in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the first side surface 5A side (FIG. 29). The multiple source contact portions 50 are arranged in a strip shape along the boundary between the active region 10 and the peripheral region 11 on the third side surface 5C side (FIG. 29). In FIG. 29, for simplicity of illustration, the multiple source contact portions 50 are depicted as a single contact portion (two in total).

[0275] Fig. 35 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment. The plurality of gate structures 35 according to the first embodiment described above were arranged shifted from the plurality of second pillar regions 12 toward the plurality of first pillar regions 13. In contrast, referring to Fig. 35, the plurality of gate structures 35 according to the second embodiment are arranged so as to overlap the plurality of second pillar regions 12 in the stacking direction. The plurality of gate structures 35 overlap the plurality of second pillar regions 12 in a one-to-one correspondence in the stacking direction.

[0276] The plurality of gate structures 35 each have a bottom wall connected to the corresponding second pillar region 12. Specifically, the plurality of gate structures 35 are formed wider than the corresponding second pillar region 12, and each have a bottom wall connected to the corresponding second pillar region 12 and a sidewall connected to the corresponding first pillar region 13.

[0277] That is, the buried electrodes 77 face the corresponding second pillar regions 12 across the insulating film 76 in the stacking direction, and face the corresponding first pillar regions 13 across the insulating film 76 in the horizontal direction. The aforementioned multiple source regions 33 and multiple contact regions 34 face the corresponding first pillar regions 13 across a part of the body region 32 in the stacking direction, respectively.

[0278] Fig. 36 is a cross-sectional perspective view showing a gate structure 35 according to the third embodiment. Referring to Fig. 36, the plurality of gate structures 35 according to the third embodiment each have a configuration that contributes to narrowing the pitch. The plurality of gate structures 35 according to the third embodiment are particularly effective in realizing a narrower pitch in the second pillar regions 12. Fig. 36 shows an example in which the gate structure 35 according to the first embodiment described above is replaced with the gate structure 35 according to the third embodiment, but the configuration of the gate structure 35 according to the third embodiment is also applicable to the configuration of the gate structure 35 according to the second embodiment.

[0279] Each of the multiple gate structures 35 includes a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80. The trench 75 has the same configuration as in the first embodiment. In this configuration, the insulating film 76 is formed at a distance from the first main surface 3 toward the bottom wall of the trench 75, and exposes a surface portion of the first main surface 3 at the opening end of the trench 75. The upper end of the insulating film 76 is preferably located closer to the first main surface 3 than the intermediate depth of the trench 75.

[0280] In this embodiment, the buried electrode 77 is buried in the trench 75 at a distance from the first main surface 3 toward the bottom wall of the trench 75, and defines an open recess that is recessed toward the bottom wall of the trench 75 at the open end of the trench 75. The buried electrode 77 exposes the surface portion of the first main surface 3 and the upper end of the insulating film 76 at the open end of the trench 75. The upper end of the buried electrode 77 is preferably located on the first main surface 3 side relative to the intermediate depth range of the trench 75.

[0281] The buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first main surface 3, and covers the insulating film 76 and the buried electrode 77 within the trench 75. The buried insulator 80 is buried in the trench 75 at a distance from the first main surface 3 toward the buried electrode 77, and exposes a surface portion of the first main surface 3 at the open end of the trench 75.

[0282] The upper end of the buried insulator 80 is preferably located closer to the first main surface 3 than the intermediate depth of the trench 75. The buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 80 preferably includes a silicon oxide film.

[0283] In this embodiment, the plurality of source regions 33 are formed in regions between adjacent gate structures 35 in the surface layer portion of the first main surface 3. The plurality of source regions 33 are arranged at intervals along the plurality of gate structures 35 so as to be connected to the plurality of gate structures 35 located on both sides.

[0284] Specifically, the plurality of source regions 33 arranged along one sidewall of the gate structure 35 face in one-to-one correspondence with the plurality of source regions 33 arranged along the other sidewall of the gate structure 35. In other words, the plurality of source regions 33 are arranged in a matrix in plan view.

[0285] Of course, the plurality of source regions 33 on one side may face the regions between the plurality of source regions 33 on the other side in a one-to-one correspondence. That is, the plurality of source regions 33 may be arranged in a staggered pattern in a plan view. The plurality of source regions 33 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 interposed therebetween.

[0286] In this embodiment, the aforementioned plurality of contact regions 34 are respectively formed in regions between the plurality of adjacent gate structures 35 in the surface layer portion of the first main surface 3. The plurality of contact regions 34 are arranged at intervals along the plurality of gate structures 35 so as to be connected to the plurality of gate structures 35 located on both sides.

[0287] Specifically, the plurality of contact regions 34 are arranged alternately with the plurality of source regions 33 along the plurality of gate structures 35. More specifically, the plurality of contact regions 34 arranged along one sidewall of the gate structure 35 face in one-to-one correspondence with the plurality of contact regions 34 arranged along the other sidewall of the gate structure 35. Furthermore, the plurality of source regions 33 are arranged in a matrix in plan view.

[0288] Of course, the multiple contact regions 34 on one side may face the regions between the multiple source regions 33 on the other side (i.e., the multiple source regions 33) in a one-to-one correspondence. That is, the multiple contact regions 34 may be arranged in a staggered pattern in a plan view. The multiple contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 sandwiched therebetween.

[0289] Although not specifically shown in the drawings, the insulating layer 40 has a laminated structure including a first insulating film 41 and a second insulating film 42. The first insulating film 41 selectively covers the first main surface 3, as in the first embodiment.

[0290] In this embodiment, the first insulating film 41 covers the peripheral edge of the active region 10 and exposes the plurality of gate structures 35 collectively in the inner portion of the active region 10. Specifically, the first insulating film 41 is connected to the insulating film 76 at both ends of the plurality of gate structures 35, exposing the buried electrodes 77. The first insulating film 41 also covers the outer periphery region 11 in the same manner as in the first embodiment.

[0291] As in the first embodiment, the second insulating film 42 selectively covers the first main surface 3 with the first insulating film 41 sandwiched therebetween. In this embodiment, the second insulating film 42 covers the peripheral portion of the active region 10 and collectively exposes the plurality of gate structures 35 in the inner portion of the active region 10. Specifically, the second insulating film 42 extends from above the first main surface 3 into the trench 75 at both ends of the plurality of gate structures 35 and is connected to the buried insulator 80 in the trench 75.

[0292] In this form, the insulating layer 40 includes a plurality of contact openings (not shown) that expose both ends (buried electrodes 77) of the plurality of gate structures 35, and a single source contact opening 43 that collectively exposes the inner portions (buried insulator 80) of the plurality of gate structures 35, a plurality of source regions 33, and a plurality of contact regions 34.

[0293] The gate pad 45, the gate wirings 46, and the drain pad 48 have the same configurations as those in the first embodiment. The source pad 47 is electrically connected to the body regions 32, the source regions 33, and the contact regions 34 via a single source contact portion (first contact portion) 50 that penetrates the insulating layer 40. The single source contact portion 50 includes a plurality of source contact openings 43 and a wiring layer that penetrates the source contact openings 43. This wiring layer may include a portion of the source pad 47. The single source contact portion 50 collectively covers the inner portions (buried insulator 80) of the gate structures 35, the source regions 33, and the contact regions 34 within the single source contact opening 43.

[0294] The source pad 47 is electrically insulated from the plurality of gate structures 35 (buried electrodes 77) by the buried insulator 80, and is electrically connected to the plurality of source regions 33 and the plurality of contact regions 34 at the first main surface 3. The source pad 47 has a buried portion buried in the trench 75. The buried portion of the source pad 47 faces the buried electrode 77 within the trench 75 with the buried insulator 80 sandwiched therebetween, and is electrically connected to the plurality of source regions 33 and the plurality of contact regions 34 at the open end of the trench 75.

[0295] 37 is a cross-sectional perspective view showing a gate structure 35 according to the fourth embodiment. Referring to Fig. 37, the plurality of gate structures 35 according to the fourth embodiment each have a configuration obtained by modifying the plurality of gate structures 35 according to the third embodiment. The configuration of the gate structure 35 according to the fourth embodiment is also applicable to the configurations of the gate structures 35 according to the first to third embodiments.

[0296] Each of the gate structures 35 includes a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80. The trench 75 has the same configuration as in the first embodiment. In this configuration, the insulating film 76 includes an upper insulating film 81 and a lower insulating film 82.

[0297] The upper insulating film 81 is formed as an insulating film for channel control, and covers the wall surface on the opening side of the trench 75 relative to the bottom of the body region 32. The upper insulating film 81 has a portion that covers the first pillar region 13 across the boundary between the first pillar region 13 and the body region 32. In this case, the coverage area of ​​the upper insulating film 81 with respect to the body region 32 is preferably larger than the coverage area of ​​the upper insulating film 81 with respect to the first pillar region 13.

[0298] The upper insulating film 81 may include a silicon oxide film. The upper insulating film 81 preferably includes a silicon oxide film made of an oxide of the chip 2. The upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value belonging to any one of the ranges of 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0299] The lower insulating film 82 covers the wall surface of the trench 75 on the bottom wall side of the bottom of the body region 32. The lower insulating film 82 covers the first pillar region 13. The coverage area of ​​the first pillar region 13 by the lower insulating film 82 is larger than the coverage area of ​​the body region 32 by the upper insulating film 81.

[0300] The lower insulating film 82 may include a silicon oxide film. The lower insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The lower insulating film 82 has a thickness greater than that of the upper insulating film 81. The thickness of the lower insulating film 82 is preferably 10 to 50 times the thickness of the upper insulating film 81.

[0301] In this embodiment, the buried electrode 77 has a multi-electrode structure (double electrode structure) including an upper electrode 83, a lower electrode 84, and an intermediate insulating film 85. The upper electrode 83 is buried in the opening side of the trench 75 with an insulating film 76 sandwiched therebetween. Specifically, the upper electrode 83 is buried in the opening side of the trench 75 with an upper insulating film 81 sandwiched therebetween, and faces the body region 32 with the upper insulating film 81 sandwiched therebetween.

[0302] The area of ​​the upper electrode 83 facing the body region 32 is larger than the area of ​​the upper electrode 83 facing the first pillar region 13. In this embodiment, the upper electrode 83 is embedded in the trench 75 at a distance from the first main surface 3 toward the bottom wall of the trench 75, and defines an open recess that is recessed toward the bottom wall of the trench 75 at the opening end of the trench 75. The upper electrode 83 exposes a surface portion of the first main surface 3 and an upper end of the upper insulating film 81 at the opening end of the trench 75.

[0303] A gate potential as a control potential is applied to the upper electrode 83. In response to the gate potential, the upper electrode 83 controls the inversion and non-inversion of a channel (current path) in the body region 32. The upper electrode 83 may include p-type or n-type conductive polysilicon.

[0304] The lower electrode 84 is embedded in the bottom wall side of the trench 75 with the insulating film 76 sandwiched therebetween. Specifically, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with the lower insulating film 82 sandwiched therebetween, and faces the first pillar region 13 with the lower insulating film 82 sandwiched therebetween. In other words, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with respect to the bottom of the body region 32. Although specific illustration is omitted, the lower electrode 84 is extended to the opening side of the trench 75 in parts of the trench 75 (both ends in this embodiment).

[0305] The facing area of ​​the lower electrode 84 with respect to the first pillar region 13 is larger than the facing area of ​​the upper electrode 83 with respect to the body region 32. The lower electrode 84 extends in a wall shape along the depth direction of the trench 75. The lower electrode 84 has an upper end that protrudes from the lower insulating film 82 toward the upper electrode 83 and engages with the lower end of the upper electrode 83. The upper end of the lower electrode 84 faces the upper insulating film 81 (body region 32) with the lower end of the upper electrode 83 sandwiched in the horizontal direction.

[0306] A gate potential or a source potential may be applied to the lower electrode 84. When a gate potential is applied to the lower electrode 84, the lower electrode 84 has the same potential as the upper electrode 83. Therefore, the voltage drop between the upper electrode 83 and the lower electrode 84 is suppressed. This suppresses electric field concentration on the gate structure 35.

[0307] On the other hand, when a source potential is applied to the lower electrode 84, the lower electrode 84 can function as a field electrode. Therefore, the parasitic capacitance between the lower electrode 84 and the first pillar region 13 is reduced. This suppresses a decrease in switching speed due to the parasitic capacitance. The lower electrode 84 may include p-type or n-type conductive polysilicon.

[0308] The intermediate insulating film 85 is interposed between the upper electrode 83 and the lower electrode 84, and electrically insulates the upper electrode 83 and the lower electrode 84 within the trench 75. The intermediate insulating film 85 is continuous with the upper insulating film 81 and the lower insulating film 82. The intermediate insulating film 85 has a thickness smaller than that of the lower insulating film 82. The thickness of the intermediate insulating film 85 is preferably greater than that of the upper insulating film 81. The intermediate insulating film 85 may include a silicon oxide film. The intermediate insulating film 85 preferably includes a silicon oxide film made of an oxide of the lower electrode 84.

[0309] The buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first main surface 3, and covers the upper insulating film 81 and the upper electrode 83 within the recess. The buried insulator 80 is buried in the trench 75 at a distance from the first main surface 3 toward the upper electrode 83, and exposes a surface portion of the first main surface 3 at the open end of the trench 75.

[0310] In this embodiment, the plurality of source regions 33 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the upper electrode 83 and the buried insulator 80 with the upper insulating film 81 interposed therebetween. In this embodiment, the plurality of contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the upper electrode 83 and the buried insulator 80 with the upper insulating film 81 interposed therebetween.

[0311] The insulating layer 40, the gate pad 45, the gate wirings 46, the source pad 47, and the drain pad 48 have the same configurations as those in the second embodiment. In this configuration, the gate wirings 46 penetrate the insulating layer 40 via the source contact openings 43 and are electrically connected to the upper electrodes 83. When a gate potential is applied to the lower electrode 84, the gate wirings 46 penetrate the insulating layer 40 via the source contact openings 43 and are electrically connected to the upper electrodes 83 and the lower electrodes 84.

[0312] When a source potential is applied to the lower electrode 84, the source pad 47 is electrically connected to the plurality of lower electrodes 84. In this case, the semiconductor device 1B may include a source wiring extending from the source pad 47 onto the insulating layer 40. In this case, the source wiring is formed in a line shape extending along the periphery of the active region 10 so as to intersect (specifically, orthogonally intersect) with a portion (one end or both ends) of the plurality of gate structures 35 in a region outside the plurality of gate wirings 46. The source wiring penetrates the insulating layer 40 via the plurality of source contact openings 43 and is electrically connected to the plurality of lower electrodes 84.

[0313] Fig. 38 is a plan view showing a semiconductor device 1C according to a third embodiment of the present disclosure. Fig. 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in Fig. 38. Fig. 40 is a plan view showing an example layout of a chip 2.

[0314] 38 to 40, semiconductor device 1C includes chip 2, base layer 6, stacked portion 7, active region 10, peripheral region 11, multiple second pillar regions 12, and multiple first pillar regions 13, similar to semiconductor device 1A.

[0315] The semiconductor device 1C includes at least one (preferably 2 to 20) p-type field region 38 formed in the surface layer portion of the first main surface 3 in the peripheral region 11 .

[0316] The number of field regions 38 is typically 4 to 8. The field regions 38 are formed in an electrically floating state and relieve the electric field within chip 2 at the periphery of first main surface 3. The number, width, depth, p-type impurity concentration, etc. of field regions 38 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0317] The multiple field regions 38 are formed at intervals in a region between the periphery of the chip 2 and the active region 10. The multiple field regions 38 are formed in strip shapes extending along the active region 10 in a plan view. Each of the multiple field regions 38 has a portion extending in a strip shape in the first direction Y and a portion extending in a strip shape in the second direction X. In this embodiment, the multiple field regions 38 are formed in an annular shape (specifically, a quadrangular annular shape) surrounding the multiple second pillar regions 12 in a plan view.

[0318] The multiple field regions 38 are formed in the stack 7 at intervals from the lower end of the stack 7 (drift region 8) toward the first main surface 3, and each form a p-n junction with the drift region 8. The multiple field regions 38 preferably have bottoms located on the first main surface 3 side of the intermediate portion of the thickness range of the stack 7. In this embodiment, the multiple field regions 38 are formed at intervals from the multiple second pillar regions 12 toward the periphery of the chip 2. Therefore, the multiple field regions 38 do not face the multiple second pillar regions 12 in the stacking direction.

[0319] The plurality of field regions 38 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0320] The p-type impurity concentrations of the multiple field regions 38 are preferably adjusted by at least one trivalent element. The trivalent element in the field regions 38 may be the same as the trivalent element in the second pillar regions 12, etc., or may be a different species from the trivalent element in the second pillar regions 12, etc. The trivalent element in the field regions 38 may be at least one of boron, aluminum, gallium, and indium.

[0321] 40 , each of the second pillar regions 12 includes one second main body portion 121 and two second extension portions 122 formed on both end portions of the second main body portion 121. The second extension portion 122 may have at least one of the features shown in the first to fourth embodiments. The second extension portion 122 may have a feature that combines multiple (two or more) features shown in the first to fourth embodiments.

[0322] The second pillar regions 12 may have at least one of the features shown in the basic form and the first to eleventh embodiments. The second pillar regions 12 may have a feature that combines two or more of the features shown in the basic form and the first to eleventh embodiments.

[0323] Furthermore, the chip 2 of the semiconductor device 1C may have the features shown in the second modification of the first embodiment.

[0324] The semiconductor device 1C includes an insulating layer 90 that selectively covers the first main surface 3. The insulating layer 90 may have a single-layer structure or a multilayer structure including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating layer 90 has a single-layer structure including a silicon oxide film.

[0325] The insulating layer 90 covers the plurality of field regions 38 in the outer peripheral region 11. In this embodiment, the insulating layer 90 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the insulating layer 90 may be formed at a distance inward from the periphery of the first main surface 3, with the laminated portion 7 exposed from the periphery of the first main surface 3.

[0326] The insulating layer 90 has a contact opening 91 that exposes the active region 10. In this form, the contact opening 91 has an opening wall positioned above the innermost field region 38, exposing the entire active region 10 and the inner edge of the innermost field region 38.

[0327] The semiconductor device 1C includes a first pad electrode (main surface electrode, Schottky electrode) 92 that covers the first main surface 3 in the active region 10. The first pad electrode 92 is formed as an anode pad. The first pad electrode 92 is disposed inward from the periphery of the chip 2 with a space therebetween. The first pad electrode 92 is formed in a polygonal shape (a quadrangular shape in this embodiment) that follows the periphery of the chip 2 in a plan view.

[0328] The first pad electrode 92 penetrates the contact opening 91 from above the insulating layer 90 and is electrically connected to the first main surface 3 and the innermost field region 38 within the contact opening 91. The first pad electrode 92 forms a Schottky junction with the first main surface 3 (first pillar region 13). As a result, an SBD structure (device structure) 93 (Schottky Barrier Diode structure) as a diode structure (device structure) is formed in the active region 10.

[0329] The semiconductor device 1C includes a second pad electrode 94 covering the second main surface 4. The second pad electrode 94 is formed as a cathode pad. The second pad electrode 94 forms ohmic contact with the base layer 6 exposed from the second main surface 4. In other words, the second pad electrode 94 is electrically connected to the first pillar region 13 via the base layer 6.

[0330] The second pad electrode 94 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The second pad electrode 94 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0331] The breakdown voltage that can be applied between the first pad electrode 92 and the second pad electrode 94 (between the first main surface 3 and the second main surface 4) may be 500 V to 3000 V or less. The breakdown voltage may have a value that belongs to any one of the following ranges: 500 V to 1000 V or less, 1000 V to 1500 V, 1500 V to 2000 V, 2000 V to 2500 V, and 2500 V to 3000 V.

[0332] A basic form of an SBD structure 93 will be shown below with reference to FIG. 41 . FIG. 41 is a cross-sectional perspective view showing an SBD structure 93 according to the basic form. Referring to FIG. 41 , when the plurality of second pillar regions 12 and the plurality of first pillar regions 13 are exposed from the first main surface 3, the first pad electrode 92 is mechanically and electrically connected to the plurality of second pillar regions 12 and the plurality of first pillar regions 13 at the first main surface 3. In this case, the first pad electrode 92 forms a JBS structure (Junction Barrier Controlled Schottky structure) with the plurality of second pillar regions 12 and forms a Schottky junction with the plurality of first pillar regions 13.

[0333] For example, in the above-described embodiments (including the exemplary embodiments and modifications), the width-varying portion 14 (first tapered portion 14A ( FIG. 6 , etc.), second tapered portion 14B ( FIG. 25 ), protruding portion 14C ( FIG. 26 ), and constricted portion 14D ( FIG. 26 )) has been described as being formed in the second extending portion 122 of the second pillar region 12 (i.e., the outer circumferential region 11).

[0334] However, the width-varying portion 14 (first tapered portion 14A, second tapered portion 14B, protruding portion 14C, and constricted portion 14D ( FIG. 26 )) may be formed in the second pillar region 12 formed in the active region 10. In this case, the width-varying portion 14 is formed in a predetermined section of the second pillar region 12 formed in the active region 10. This can improve the robustness of the breakdown voltage of the active region 10.

[0335] In addition, in each of the above-described embodiments, the base layer 6 and the stacked portion 7 each include a SiC single crystal. However, at least one of the base layer 6 and the stacked portion 7 or all of them may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0336] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３ The base layer 6 and the laminated portion 7 may be made of the same type of single crystal, or may be made of different types of single crystal.

[0337] At least one or all of the base layer 6 and the stacked portion 7 may contain a single crystal other than a wide bandgap semiconductor, or at least one or all of the base layer 6 and the stacked portion 7 may contain single crystal silicon.

[0338] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0339] In the above-described embodiments, examples have been shown in which the MIS structure 31 and the SBD structure 93 are individually formed on different chips 2. However, the MIS structure 31 and the SBD structure 93 may be formed on one chip 2. In this case, the SBD structure 93 may be electrically interposed between the source pad 47 (anode pad) and the drain pad 48 (cathode pad) as a freewheeling diode for the MIS structure 31.

[0340] In the above-described embodiments, an n-type base layer 6 has been described. However, a p-type base layer 6 may be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type base layer 6 may be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0341] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0342] [Supplementary Note 1-1] A semiconductor device (1A, 1B, 1C) comprising: a chip (2) having a main surface (3); a first pillar region (13) of a first conductivity type disposed within the chip (2) and extending in a strip shape along a first direction (Y) in a planar view; and a second pillar region (12) of a second conductivity type adjacent to the first pillar region (13) within the chip (2) and extending in a strip shape along the first direction (Y) in a planar view, wherein the second pillar region (12) includes a width varying portion (14) whose width (W20) varies in a second direction (X) intersecting the first direction (Y) in a planar view.

[0343] According to this configuration, the widths (W20) of the second pillar regions (12) change in the first direction (Y) in the width-varying portions (14). When one first pillar region (13) is sandwiched between two second pillar regions (12) in the second direction (X), the width (W10) of the first pillar region (13) also changes in the first direction (Y). Therefore, even if an error (variation) occurs in at least one of the spacing and impurity concentration between adjacent second pillar regions (12), charge balance can be ensured at any position in the first direction (Y) in the first pillar region (13), and at least the required breakdown voltage can be ensured. In other words, a semiconductor device (1A, 1B, 1C) having high robustness with respect to breakdown voltage can be provided.

[0344] [Appendix 1-2] The semiconductor device (1A, 1B, 1C) described in Appendix 1-1, wherein the width-changing portion (14) includes a tapered portion (14A) in which the width (W20) of the second pillar region (12) narrows toward an end face (5A, 5C) of the chip (2) in the first direction (Y).

[0345] According to this configuration, in the tapered portion (14A), the width (W20) of the second pillar region (12) narrows toward the end faces (5A, 5C) of the chip (2). In other words, the width (W10) of one first pillar region (13) sandwiched between two second pillar regions 12 adjacent in the second direction (X) widens toward the end faces (5A, 5C) of the chip (2). This allows the mutually connected depletion layers to expand toward the end faces (5A, 5C) of the chip (2). This further improves the breakdown voltage.

[0346] [Appendix 1-3] The semiconductor device (1A, 1B, 1C) described in Appendix 1-1, wherein the width-changing portion (14) includes a tapered portion (14B) in which the width (W2) of the second pillar region (12) increases toward an end face (5A, 5C) of the chip (2) in the first direction (Y).

[0347] [Appendix 1-4] The semiconductor device (1A, 1B, 1C) according to Appendix 1-1, wherein the width-changing portion (14) includes a protruding portion (14C) on both sides in the second direction (X) where the second pillar region (12) selectively protrudes, and a constricted portion (14D) that is continuous with the protruding portion (14C) in the first direction (Y) and where the second pillar region (12) selectively constricts.

[0348] [Appendix 1-5] The semiconductor device (1A, 1B, 1C) according to any one of Appendices 1-1 to 1-4, wherein the width-varying portion (14) has a first width (W21) and a second width (W22) different from the first width (W21) in a predetermined section (122) of the second pillar region (12) in the first direction (Y), and the width (W2) of the second pillar region (13) varies in a range between the first width (W21) and the second width (W22).

[0349] [Supplementary Note 1-6] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 1-5, wherein the second width (W22) has a size of ±10% or less of the first width (W21).

[0350] [Supplementary Note 1-7] The semiconductor device (1A, 1B, 1C) according to any one of Supplementary Note 1-1 to Supplementary Note 1-6, wherein the first pillar regions (13) and the second pillar regions (12) are alternately repeated in the second direction (X) and are arranged in a striped pattern overall, and the second pillar regions (12) have the width-varying portions (14) within a range of 0.03% to 1.5% of a length of the striped second pillar regions (12).

[0351] [Supplementary Note 1-8] The semiconductor device (1A, 1B, 1C) according to any one of Supplementary Note 1-1 to Supplementary Note 1-7, wherein the chip (2) includes SiC.

[0352] [Supplementary Note 1-9] The present invention relates to a SiC chip (2) having a main surface (3), the SiC chip (2) including an active region (10) and a peripheral region (11) outside the active region; a drift region (8) of a first conductivity type formed in a surface layer portion of the main surface (3) of the SiC chip; a superjunction structure (SJ) including first pillar regions (13) of the first conductivity type and second pillar regions (12) of a second conductivity type arranged adjacent to each other and alternately in a direction (X) along the main surface (3) in the drift region (8); and a device structure (31, 91) formed between the superjunction structure (SJ) and the main surface (3) in the active region (10), the first pillar region (13) having a first extension portion (132) extending from the active region (10) toward the peripheral region (11) in a first direction (Y) in a plan view; The semiconductor device (1A, 1B, 1C) is characterized in that the second pillar region (12) extends from the active region (10) toward the peripheral region (11) along the first direction (Y) in a planar view and has a second extension portion (122) adjacent to the first extension portion (132), and the second extension portion (122) includes a width-varying portion (14) whose width (W20) in a second direction (X) intersecting the first direction (Y) in a planar view changes.

[0353] According to this configuration, the widths (W20) of the multiple second extension portions (122) change in the first direction (Y) in the width-varying portions (14). In this case, the widths (W10) of the multiple first extension portions (132) sandwiched between the width-varying portions (14) of the multiple second extension portions (122) also change in the first direction (Y). Therefore, even if an error (variation) occurs in at least one of the spacing and impurity concentration of the multiple second extension portions (122), charge balance can be ensured at any position in the first direction (Y) in each of the multiple first extension portions (132). This ensures at least the required breakdown voltage even if an error (variation) occurs in the dimensions, impurity concentration, etc. of the multiple second extension portions (122). In other words, a semiconductor device (1A, 1B, 1C) having high robustness in terms of breakdown voltage can be provided.

[0354] [Appendix 1-10] The semiconductor device (1A, 1B, 1C) according to Appendix 1-9, wherein the second extension portion (122) has an outer end portion (125) disposed in the outer peripheral region (11), and the width-changing portion (14) includes a tapered portion (14A) in which the width (W20) of the second extension portion (122) narrows to be narrowest at the outer end portion (125) of the second extension portion (122) in the first direction (Y).

[0355] [Appendix 1-11] The semiconductor device (1A, 1B, 1C) according to Appendix 1-10, wherein the tapered portion (14A) has a pair of side portions (125) extending in the first direction (Y) from the outer end portion (125), and an angle (θ1) between the outer end portion (125) and the side portions (125) of the tapered portion (14A) is greater than or equal to 90° and less than or equal to 95°.

[0356] [Appendix 1-12] The semiconductor device (1A, 1B, 1C) according to Appendix 1-10 or Appendix 1-11, wherein the second pillar region (12) is disposed in the active region (10) and includes a main body portion (121) extending in a strip shape with a constant width (W2) along the first direction (Y), and a width (W20) of the tapered portion (14A) narrows from an end (123) of the main body portion (121) toward the outer end (125) of the tapered portion (14A).

[0357] [Appendix 1-13] The semiconductor device (1A, 1B, 1C) according to any one of Appendices 1-10 to 1-12, further including: an insulating layer (40, 90) covering the device structure (31, 93); and a first principal surface electrode (47, 92) disposed on the insulating layer (40, 90) and facing the device structure (31, 93) across the insulating layer (40, 90), wherein the tapered portion (14A) is disposed in a region outside the first principal surface electrode (47, 92).

[0358] [Appendix 1-14] The semiconductor device (1A, 1B) according to Appendix 1-13, further including a first contact portion (50) disposed in the insulating layer (40), extending in a direction transverse to the superjunction structure (SJ), and connecting the device structure (31) and the first principal surface electrode (47), wherein a width (W20) of the tapered portion (14A) narrows from the first contact portion (50) toward the outer end portion (125) of the tapered portion (14A).

[0359] [Appendix 1-15] The semiconductor device (1A, 1B) according to Appendix 1-9 further includes: an insulating layer (40) covering the device structure (31); a first main surface electrode (47) disposed on the insulating layer (40) and facing the device structure (31) across the insulating layer (40); and a first contact portion (50) disposed in the insulating layer (40), extending in a direction across the superjunction structure (SJ), and connecting the device structure (31) and the first main surface electrode (47), wherein the width-changing portion (14) includes a tapered portion (14A) that narrows from the first contact portion (50) toward an outer end (125) of the second extension portion (122) so as to be widest at the first contact portion (50) and narrowest at the outer end (125) of the second extension portion (122).

[0360] [Appendix 1-16] The semiconductor device (1A, 1B) according to any one of Appendices 1-9 to 1-15, wherein the device structure (31) includes a body region (32) of a second conductivity type formed in the drift region (8), and a source region (33) of a first conductivity type formed in a surface layer portion of the body region (32).

[0361] [Appendix 1-17] The semiconductor device (1A) according to Appendix 1-16, wherein the device structure (31) includes a planar gate structure having a gate electrode (37) disposed on the main surface (3) and facing the body region (32), and a gate insulating film (36) between the gate electrode (37) and the main surface (3).

[0362] [Supplementary Note 1-18] The semiconductor device (1B) according to Supplementary Note 1-16, wherein the device structure (31) includes a trench gate structure having a gate trench (75) that penetrates the source region (33) and the body region (32) to reach the drift region (8), a gate insulating film (36) disposed on the inner surface of the gate trench (75), and a gate electrode (37) embedded in the gate trench (75) via the gate insulating film (36).

[0363] [Appendix 1-19] The semiconductor device (1C) according to any one of Appendices 1-9 to 1-15, wherein the device structure (93) includes a Schottky electrode (92) that covers the plurality of first pillar regions (13) and the plurality of second pillar regions (12) and forms a Schottky junction with the plurality of first pillar regions (13).

[0364] 1A...semiconductor device, 1B...semiconductor device, 1C...semiconductor device, 2...chip, 3...first main surface (main surface), 4...second main surface, 5A...first side surface (end surface), 5B...second side surface, 5C...third side surface (end surface), 5D...fourth side surface, 6...base layer, 7...laminated portion, 8...drift region, 10...active region, 11...peripheral region, 12...second pillar region, 12a...second lower end, 12b...second upper end, 13...first pillar region, 13a...first lower end, 13b...first upper end, 14...width changing portion, 14A...first tapered portion (tapered portion), 14B...second tapered portion (tapered portion), 14C...protruding portion, 14D...constricted portion, 18...first region, 19...second region, 25...intermediate region, 26...boundary portion, 31...MIS structure (device structure), 32...body region, 33...source region, 34...contact region, 35...gate structure, 36...gate insulating film, 37...gate electrode, 38...field region, 40...insulating layer, 41...first insulating film, 42...second insulating film, 43...source contact opening, 45...gate pad, 46...gate wiring, 46A...first gate wiring, 46B...second gate wiring, 47...source pad (first main surface electrode), 48...drain pad, 50...source contact portion (first contact portion), 51 ...outer body region, 51a...inner end, 51b...outer end, 54...constant width portion, 55...connection ring, 75...trench, 76...insulating film, 77...buried electrode, 80...buried insulator, 81...upper insulating film, 82...lower insulating film, 83...upper electrode, 84...lower electrode, 85...intermediate insulating film, 90...insulating layer, 91...contact opening, 92...first pad electrode (main surface electrode, Schottky electrode), 93...SBD structure (device structure) 9,4...second pad electrode, 121...second main body portion (main body portion), 122...second extension portion (predetermined section), 124...second inner end (inner end), 125...second outer end (outer side end), 126...side portion, 127...first side portion, 128...second side portion, 129...third side portion, 131...first main body portion, 132...first extension portion, 133...end portion, 134...first inner end portion, 135...first outer end portion, DT...trench depth, S1...depletion layer, S2...depletion layer, SJ...super junction structure, T1...first thickness, T2...second thickness, TB...base thickness, TE...epi thickness, W1...first pillar width, W2...second pillar width, W10...width, W11...minimum width, W12...maximum width, W20...width, W21...first width, W22...second width, W23...maximum width, W24...minimum width, WT...trench width,X...second direction, Y...first direction, Z...vertical direction, θ1...angle, θ2...angle, θ3...angle, θ4...angle, θ5...angle,

Claims

1. A semiconductor device comprising: a chip having a main surface; a first pillar region of a first conductivity type disposed within the chip and extending in a strip shape along a first direction in a planar view; and a second pillar region of a second conductivity type adjacent to the first pillar region within the chip and extending in a strip shape along the first direction in a planar view, wherein the second pillar region includes a width varying portion whose width varies in a second direction intersecting the first direction in a planar view.

2. The semiconductor device according to claim 1, wherein the width-changing portion includes a tapered portion in which the width of the second pillar region narrows toward the end face of the chip in the first direction.

3. The semiconductor device according to claim 1, wherein the width-changing portion includes a tapered portion in which the width of the second pillar region increases toward the end face of the chip in the first direction.

4. The semiconductor device according to claim 1, wherein the width-changing portion includes a protruding portion where the second pillar region selectively protrudes on both sides in the second direction, and a constricted portion that is continuous with the protruding portion in the first direction and where the second pillar region selectively constricts.

5. A semiconductor device according to any one of claims 1 to 4, wherein the width varying portion has a first width and a second width different from the first width in a predetermined section of the second pillar region in the first direction, and the width of the second pillar region varies within a range between the first width and the second width.

6. The semiconductor device according to claim 5, wherein the second width has a size within ±10% of the first width.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first pillar regions and the second pillar regions are alternately arranged in the second direction in a striped pattern overall, and the second pillar regions have the width varying portions within a range of 0.03% to 1.5% of the length of the striped second pillar regions.

8. The semiconductor device according to any one of claims 1 to 7, wherein the chip comprises SiC.

9. A semiconductor device comprising: a SiC chip having a main surface, the SiC chip including an active region and a peripheral region outside the active region; a drift region of a first conductivity type formed in a surface layer portion of the main surface of the SiC chip; a superjunction structure including first pillar regions of the first conductivity type and second pillar regions of a second conductivity type arranged adjacent to each other and alternately repeated in a direction along the main surface within the drift region; and a device structure formed in the active region between the superjunction structure and the main surface; the first pillar region has a first extension portion extending in a first direction from the active region toward the peripheral region in a planar view; the second pillar region has a second extension portion extending in the first direction from the active region toward the peripheral region in a planar view and adjacent to the first extension portion; and the second extension portion includes a width varying portion whose width varies in a second direction intersecting the first direction in a planar view.

10. The semiconductor device described in claim 9, wherein the second extension portion has an outer end portion located in the outer peripheral region, and the width-changing portion includes a tapered portion in which the width of the second extension portion narrows so as to be narrowest at the outer end portion of the second extension portion in the first direction.

11. The semiconductor device according to claim 10, wherein the tapered portion has a pair of side portions extending in the first direction from the outer end portion, and the angle between the outer end portion of the tapered portion and the side portions is greater than or equal to 90° and less than or equal to 95°.

12. The semiconductor device described in claim 10 or 11, wherein the second pillar region is disposed in the active region and includes a main body portion extending in a strip shape with a constant width along the first direction, and the width of the tapered portion narrows from the end of the main body portion toward the outer end of the tapered portion.

13. A semiconductor device according to any one of claims 10 to 12, further comprising: an insulating layer covering said device structure; and a first main surface electrode disposed on said insulating layer and facing said device structure across said insulating layer, wherein said tapered portion is disposed in an area outside said first main surface electrode.

14. The semiconductor device according to claim 13, further comprising a first contact portion disposed in the insulating layer, extending in a direction transverse to the superjunction structure, and connecting the device structure and the first principal surface electrode, wherein the width of the tapered portion narrows from the first contact portion toward the outer end of the tapered portion.

15. The semiconductor device described in claim 9, further comprising: an insulating layer covering the device structure; a first main surface electrode disposed on the insulating layer and facing the device structure across the insulating layer; and a first contact portion disposed within the insulating layer, extending in a direction transverse to the superjunction structure, and connecting the device structure and the first main surface electrode, wherein the width-changing portion includes a tapered portion that narrows from the first contact portion toward the outer end so as to be widest at the first contact portion and narrowest at the outer end of the second extension portion.

16. The semiconductor device according to any one of claims 9 to 15, wherein the device structure includes a body region of a second conductivity type formed in the drift region, and a source region of a first conductivity type formed in a surface layer portion of the body region.

17. The semiconductor device according to claim 16, wherein the device structure includes a planar gate structure having a gate electrode disposed on the main surface and facing the body region, and a gate insulating film between the gate electrode and the main surface.

18. The semiconductor device according to claim 16, wherein the device structure includes a trench gate structure having a gate trench that penetrates the source region and the body region to reach the drift region, a gate insulating film disposed on the inner surface of the gate trench, and a gate electrode embedded in the gate trench via the gate insulating film.

19. The semiconductor device according to any one of claims 9 to 15, wherein the device structure includes a Schottky electrode that covers the plurality of first pillar regions and the plurality of second pillar regions and forms a Schottky junction with the plurality of first pillar regions.

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