Image display device and video wall having same

Abstract

The present disclosure relates to an image display device and a video wall having same. An image display device according to an embodiment of the present disclosure comprises: a plurality of light-emitting diodes; and a driving control unit that outputs a scan signal to the plurality of light-emitting diodes for each of a plurality of sub-frame periods, and outputs a data signal for displaying an image, wherein the driving control unit turns on or off the plurality of light-emitting diodes on the basis of a first clock signal, during some sub-frame periods among the plurality of sub-frame periods, and turns on or off the plurality of light-emitting diodes on the basis of a second clock signal, which is different from the first clock signal, during some other sub-frame periods among the plurality of sub-frame periods. Accordingly, it is possible to reduce power consumption while maintaining gradation expression.

Description

Video display device and video wall equipped with the same

[0001] The present disclosure relates to a video display device and a video wall having the same, and more specifically, to a video display device capable of reducing power consumption while maintaining gradation expressiveness and a video wall having the same.

[0002] A video display device is a device that has a display and displays images.

[0003] Meanwhile, various types of displays are used in video display devices, such as liquid crystal display panels and light-emitting diode panels.

[0004] Meanwhile, in the case of configuring a video display device based on a light-emitting diode panel, an active matrix driving method or a passive matrix driving method is used to drive the light-emitting diode panel.

[0005] When driving a display device based on a light-emitting diode panel based on a passive matrix driving method, a plurality of sub-frames are used to cause the light-emitting diode to emit light or not emit light.

[0006] Meanwhile, as the bit depth of the image signal increases, the gradation expressiveness increases, so a high-speed clock signal is required when driving a light-emitting diode, which ultimately increases the power consumption of the image display device.

[0007] Meanwhile, in order to reduce power consumption of a video display device, when the bit depth of the video signal is reduced and the frequency of the clock signal is reduced, there is a problem of reduced grayscale expressiveness.

[0008] The problem of the present disclosure is to provide a video display device capable of reducing power consumption while maintaining gradation expressiveness and a video wall having the same.

[0009] Another object of the present disclosure is to provide a video display device capable of reducing power consumption while maintaining bit depth and a video wall including the same.

[0010] According to one embodiment of the present disclosure for achieving the above-described problem, a video display device and a video wall including the same include a plurality of light-emitting diodes, and a driving control unit that outputs a scan signal to the plurality of light-emitting diodes for each of a plurality of sub-frame periods and outputs a data signal for displaying an image, wherein the driving control unit turns on or off the plurality of light-emitting diodes based on a first clock signal during some sub-frame periods among the plurality of sub-frame periods, and turns on or off the plurality of light-emitting diodes based on a second clock signal different from the first clock signal during some other sub-frame periods among the plurality of sub-frame periods.

[0011] Meanwhile, the driving control unit can control the frequency of the second clock signal to be lower than the frequency of the first clock signal.

[0012] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on a first clock signal during a first sub-frame period among the plurality of sub-frame periods, and can turn on or off the plurality of light-emitting diodes based on a second clock signal during a sub-frame period after the first sub-frame period among the plurality of sub-frame periods.

[0013] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on a first clock signal during a last sub-frame period among the plurality of sub-frame periods, and can turn on or off the plurality of light-emitting diodes based on a second clock signal during a sub-frame period prior to the last sub-frame period among the plurality of sub-frame periods.

[0014] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on the second clock signal during a first sub-frame period and a last sub-frame period among the plurality of sub-frame periods, and can turn on or off the plurality of light-emitting diodes based on the first clock signal during some sub-frame periods between the first sub-frame period and the last sub-frame period.

[0015] Meanwhile, the driving control unit can control the position of some sub-frame periods operating at the frequency of the first clock signal to be variable for each frame.

[0016] Meanwhile, the driving control unit can output a first scan signal corresponding to the first clock signal to a plurality of light-emitting diodes during some sub-frame period.

[0017] Meanwhile, the driving control unit can output a first scan signal corresponding to a first clock signal to a plurality of light-emitting diodes during some sub-frame periods among the plurality of sub-frame periods, and can output a second scan signal corresponding to a second clock signal to a plurality of light-emitting diodes during some other sub-frame periods among the plurality of sub-frame periods.

[0018] Meanwhile, the driving control unit can control the number of sub-frame periods that operate based on the first clock signal among the plurality of sub-frame periods to be plural.

[0019] Meanwhile, the driving control unit can control the positions of a plurality of sub-frame periods that operate based on the first clock signal to vary for each frame.

[0020] Meanwhile, the driving control unit may include a first counter that performs counting based on a first clock signal, a second counter that performs counting based on a second clock signal, and a multiplexer that outputs a first scan signal corresponding to the first clock signal or a second scan signal corresponding to the second clock signal based on the first counter or the second counter.

[0021] Meanwhile, the driving control unit can control the number of some sub-frame periods to be greater than the number of other sub-frame periods.

[0022] According to another embodiment of the present disclosure, a video display device and a video wall including the same include a plurality of light-emitting diodes, and a driving control unit that outputs a scan signal for each of a plurality of sub-frame periods to the plurality of light-emitting diodes and outputs a data signal for expressing a plurality of grayscales, wherein the driving control unit turns on or off the plurality of light-emitting diodes based on a first clock signal during some sub-frame periods among the plurality of sub-frame periods when the plurality of grayscales are a first set grayscale, and turns on or off the plurality of light-emitting diodes based on a second clock signal that is different from the first clock signal during some sub-frame periods among the plurality of sub-frame periods when the plurality of grayscales are a second set grayscale.

[0023] Meanwhile, the driving control unit can control the frequency of the second clock signal to be lower than the frequency of the first clock signal.

[0024] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on the second clock signal during some other sub-frame periods among the plurality of sub-frame periods, when the first set gradation is among the plurality of gradations.

[0025] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on the first clock signal during some other sub-frame periods among the plurality of sub-frame periods, when the second set gradation is among the plurality of gradations.

[0026] Meanwhile, the driving control unit can output a first scan signal corresponding to a first clock signal to a plurality of light-emitting diodes, and output a second scan signal corresponding to a second clock signal to a plurality of light-emitting diodes.

[0027] An image display device and a video wall having the same according to one embodiment of the present disclosure include a plurality of light-emitting diodes, and a driving control unit that outputs a scan signal to the plurality of light-emitting diodes for each of a plurality of sub-frame periods and outputs a data signal for image display, wherein the driving control unit turns on or off the plurality of light-emitting diodes based on a first clock signal during some sub-frame periods among the plurality of sub-frame periods, and turns on or off the plurality of light-emitting diodes based on a second clock signal different from the first clock signal during other sub-frame periods among the plurality of sub-frame periods. Accordingly, power consumption can be reduced while maintaining grayscale expressiveness. In particular, power consumption can be reduced while maintaining bit depth.

[0028] Meanwhile, the driving control unit can control the frequency of the second clock signal to be lower than the frequency of the first clock signal. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0029] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on a first clock signal during a first sub-frame period among the plurality of sub-frame periods, and can turn on or off the plurality of light-emitting diodes based on a second clock signal during a sub-frame period following the first sub-frame period among the plurality of sub-frame periods. Accordingly, it is possible to reduce power consumption while maintaining grayscale expressiveness.

[0030] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on a first clock signal during the last sub-frame period among the plurality of sub-frame periods, and can turn on or off the plurality of light-emitting diodes based on a second clock signal during the sub-frame period prior to the last sub-frame period among the plurality of sub-frame periods. Accordingly, it is possible to reduce power consumption while maintaining grayscale expressiveness.

[0031] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on the second clock signal during the first sub-frame period and the last sub-frame period among the plurality of sub-frame periods, and can turn on or off the plurality of light-emitting diodes based on the first clock signal during some sub-frame periods between the first sub-frame period and the last sub-frame period. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0032] Meanwhile, the drive control unit can control the position of some sub-frame periods operating at the frequency of the first clock signal to vary from frame to frame. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0033] Meanwhile, the driving control unit can output a first scan signal corresponding to the first clock signal to a plurality of light-emitting diodes during a certain sub-frame period. Accordingly, power consumption can be reduced while maintaining grayscale expressiveness.

[0034] Meanwhile, the driving control unit can output a first scan signal corresponding to a first clock signal to a plurality of light-emitting diodes during some sub-frame periods among the plurality of sub-frame periods, and can output a second scan signal corresponding to a second clock signal to a plurality of light-emitting diodes during some other sub-frame periods among the plurality of sub-frame periods. Accordingly, power consumption can be reduced while maintaining grayscale expressiveness.

[0035] Meanwhile, the driving control unit can control a plurality of sub-frame periods to operate based on the first clock signal among the plurality of sub-frame periods. Accordingly, power consumption can be reduced while maintaining grayscale expressiveness.

[0036] Meanwhile, the driving control unit can control the positions of multiple sub-frame periods operating based on the first clock signal to vary for each frame. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0037] Meanwhile, the driving control unit may include a first counter that performs counting based on a first clock signal, a second counter that performs counting based on a second clock signal, and a multiplexer that outputs a first scan signal corresponding to the first clock signal or a second scan signal corresponding to the second clock signal based on the first counter or the second counter. Accordingly, it is possible to reduce power consumption while maintaining grayscale expressiveness.

[0038] Meanwhile, the driving control unit can control the number of sub-frame periods to be greater than the number of other sub-frame periods. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0039] According to another embodiment of the present disclosure, a video display device and a video wall including the same include a plurality of light-emitting diodes, and a driving control unit that outputs a scan signal to the plurality of light-emitting diodes for each of a plurality of sub-frame periods and outputs a data signal for expressing a plurality of grayscales, wherein the driving control unit turns on or off the plurality of light-emitting diodes based on a first clock signal during some sub-frame periods among the plurality of sub-frame periods when the plurality of grayscales are a first set grayscale, and turns on or off the plurality of light-emitting diodes based on a second clock signal that is different from the first clock signal during some sub-frame periods among the plurality of sub-frame periods when the plurality of grayscales are a second set grayscale. Accordingly, power consumption can be reduced while maintaining grayscale expressiveness. In particular, power consumption can be reduced while maintaining a bit depth.

[0040] Meanwhile, the driving control unit can control the frequency of the second clock signal to be lower than the frequency of the first clock signal. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0041] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on the second clock signal during some other sub-frame periods among the plurality of sub-frame periods when the first set gradation is among the plurality of gradations. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0042] Meanwhile, the driving control unit can turn on or off the plurality of light-emitting diodes based on the first clock signal during some other sub-frame periods among the plurality of sub-frame periods when the second set gradation is among the plurality of gradations. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0043] Meanwhile, the driving control unit can output a first scan signal corresponding to a first clock signal to a plurality of light-emitting diodes, and a second scan signal corresponding to a second clock signal to a plurality of light-emitting diodes. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0044] FIG. 1 is a diagram illustrating a video wall according to one embodiment of the present disclosure.

[0045] Figure 2 is an example of an internal block diagram of the video wall of Figure 1.

[0046] Figure 3 is an example of an internal block diagram of the signal processing device of Figure 2.

[0047] Figure 4 is an internal block diagram of the display of Figure 2.

[0048] FIGS. 5A to 5C are drawings for reference in the description of the light-emitting panel of FIG. 4.

[0049] Fig. 6 is a drawing illustrating an example of the light-emitting panel of Fig. 4.

[0050] FIGS. 7A to 7D are drawings for reference in explaining the operation of a video display device related to the present disclosure.

[0051] FIG. 8 is a drawing illustrating an example of a light-emitting panel according to one embodiment of the present disclosure.

[0052] FIGS. 9A to 9D are drawings for reference in explaining the operation of a video display device related to the present disclosure.

[0053] FIG. 10 is a diagram showing the operation of a video display device according to one embodiment of the present disclosure.

[0054] Figures 11a to 23 are drawings referred to in the description of Figure 10.

[0055] FIG. 24 is a drawing showing the operation of a video display device according to another embodiment of the present disclosure.

[0056] Figures 25a and 25b are drawings referred to in the description of Figure 24.

[0057] Hereinafter, the present disclosure will be described in more detail with reference to the drawings.

[0058] The suffixes "module" and "part" used in the following description are given solely for the convenience of writing this specification and do not impart any particularly significant meaning or role to the components themselves. Therefore, the terms "module" and "part" may be used interchangeably.

[0059] FIG. 1 is a diagram illustrating a video wall according to one embodiment of the present disclosure.

[0060] Referring to the drawing, a video wall (10) according to one embodiment of the present disclosure may include a plurality of image display devices (100a to 100d).

[0061] A video wall (10) according to one embodiment of the present disclosure can receive images from a set-top box (not shown), a server (not shown), or an internal memory.

[0062] For example, the video wall (10) can receive a video signal from a set-top box (not shown) through an HDMI terminal.

[0063] As another example, the video wall (10) can receive a video signal from a server (not shown) through a network terminal.

[0064] Meanwhile, the video wall (10) can be installed inside or outside the building.

[0065] For example, a video wall (10) can be installed in public facilities such as vehicles, terminals, train stations, and airports to provide information such as advertisements, news, and notices. Furthermore, it can be placed around show windows in stores such as department stores, shopping malls, and large marts to advertise specific products.

[0066] As another example, the video wall (10) can be installed and placed on a wall inside a house.

[0067] Such a video wall (10) may be equipped with a plurality of displays (180a to 180d) that are arranged adjacently.

[0068] Meanwhile, the plurality of displays (180a to 180d) may be implemented using any one of various panels. For example, the plurality of displays (180a to 180d) may be any one of a liquid crystal display panel (LCD panel), an organic light-emitting diode (OLED) panel, an inorganic light-emitting panel (LED panel), etc.

[0069] In this disclosure, a plurality of displays (180a to 180d) are described with a focus on having inorganic light-emitting panels (LED panels).

[0070] Meanwhile, the inorganic light-emitting panel (LED panel) contains light-emitting diodes and has the advantages of excellent response speed and color reproduction.

[0071] Meanwhile, a plurality of displays (180a to 180d) may be provided with a plurality of panels (210a to 210d) and bezels (Ba to Bd) surrounding the panels (210a to 210d).

[0072] In the drawing, the video wall (10) is exemplified as having a plurality of video display devices (100a to 100d) each having a display (180a to 180d).

[0073] Alternatively, for displaying images on a video wall (10), a signal processing device (170 to 170d) provided in each of a plurality of image display devices (100a to 100d) may be used.

[0074] For example, an image distributed from a signal processing device (170) is input to a signal processing device (170 to 170d) provided in each of a plurality of image display devices (100a to 100d), and an image signal processed in each of the signal processing devices (170 to 170d) is input to each display (180a to 180d), and each display (180a to 180d) can display the corresponding image.

[0075] Accordingly, the viewer (50) can view the image displayed on the video wall (10), as shown in the drawing. In particular, the viewer can view the image displayed on multiple displays (180a to 180d).

[0076] As another example, the video wall (10) may include a single signal processing device that commonly controls multiple image display devices (100a to 100d). Accordingly, the common signal processing device can perform signal processing on the displayed image. Then, the image signal-processed image is input to each display (180a to 180d), and each display (180a to 180d) can display the corresponding image.

[0077] Meanwhile, when a plurality of displays (180a to 180d) are driven based on a passive matrix method, inorganic light-emitting panels including light-emitting diodes, the light-emitting diodes are made to emit light or not emit light by using a plurality of sub-frames.

[0078] Figure 2 is an example of an internal block diagram of the video wall of Figure 1.

[0079] Referring to the drawing, the video wall (10) may be equipped with first to fourth video display devices (100a to 100d).

[0080] In the drawing, for convenience, the second to fourth image display devices (100b to 100d) are illustrated as having second to fourth displays (180b to 180d) and second to fourth signal processing devices (170b to 170d), respectively; however, alternatively, they may be provided with an external device interface unit, a network interface unit, a memory, an image distribution unit, a power supply unit, an audio output unit, etc.

[0081] Meanwhile, the first image display device (100a) may be equipped with an external device interface unit (130), a network interface unit (135), a memory (140), a user input interface unit (150), a signal processing device (170), a signal processing device (170), a first display (180a), a power supply unit (190), an audio output unit (185), etc.

[0082] The external device interface unit (130) can transmit and receive data with a connected external device (not shown). To this end, the external device interface unit (130) may include an A / V input / output unit (not shown) or a data input / output unit (not shown).

[0083] For example, the external device interface unit (130) may include an HDMI terminal, an RGB terminal, a component terminal, a USB terminal, a micro SD terminal, etc.

[0084] The network interface unit (135) provides an interface for connecting the video display device (100) to a wired / wireless network, including the Internet. For example, the network interface unit (135) can transmit and receive content or data provided by the Internet, a content provider, or a network operator via a network.

[0085] The memory (140) may store a program for each signal processing and control within the signal processing device (170), and may also store a signal-processed image, voice, or data signal.

[0086] Additionally, the memory (140) may also perform a function for temporary storage of image, voice, or data signals input to the external device interface unit (130).

[0087] Meanwhile, multiple displays (180a to 180d) can be arranged adjacent to each other and can be equipped with various display panels such as LCD, OLED, PDP, etc., and can display a predetermined image through the display panels.

[0088] The user input interface unit (150) transmits a signal input by the user to the signal processing device (170) or transmits a signal from the signal processing device (170) to the user.

[0089] To this end, the user input interface unit (150) may be equipped with a local key including a power key, a touch panel for inputting user information, etc.

[0090] The signal processing device (170) can distribute an input image stored in a memory (140), an input image received from an external device through an external device interface unit (130), or a network interface unit (135) into a plurality of images for display on a plurality of displays (180a to 180d).

[0091] For example, the signal processing device (170) can crop an input image into multiple images and perform scaling.

[0092] In particular, the signal processing device (170) can perform cropping, scaling, etc., taking into account the resolution, size, etc. of the plurality of displays (180a to 180d).

[0093] Meanwhile, the signal processing device (170) may perform overall control operations of the video wall (10). Specifically, it may control the operations of each unit within the video wall (10).

[0094] Meanwhile, the signal processing device (170) can distribute the image and transmit the distributed image to a plurality of signal processing devices (170 to 170d).

[0095] Meanwhile, at least one signal processing device may be provided to control multiple displays (180a to 180d).

[0096] Meanwhile, in the drawing, a plurality of signal processing devices (170 to 170d) corresponding to the number of the plurality of displays (180a to 180d) are illustrated to control the plurality of displays (180a to 180d).

[0097] A plurality of signal processing devices (170 to 170d) can perform control operations for displaying images on a plurality of displays (180a to 180d).

[0098] A plurality of signal processing devices (170 to 170d) can perform signal processing on an input image and transmit the processed image signal to a plurality of displays (180a to 180d).

[0099] That is, each of the plurality of signal processing devices (170 to 170d) can control the plurality of displays (180a to 180d) to output a predetermined image. Specifically, R, G, and B signals corresponding to the video image to be displayed can be output to the plurality of displays (180a to 180d). Accordingly, the plurality of displays (180a to 180d) can display each image.

[0100] The power supply unit (190) can supply power required for the operation of each component by receiving external power or internal power.

[0101] The power supply unit (190) supplies power to the entire image display device (100). In particular, it can supply power to a plurality of signal processing devices (170 to 170d) that can be implemented in the form of a system on chip (SOC), a plurality of displays (180a to 180d) for image display, and an audio output unit (185) for audio output.

[0102] The temperature sensing unit (not shown) can sense the temperature of the video wall (10).

[0103] The temperature detected by the temperature detection unit (not shown) can be input to at least one of the plurality of signal processing devices (170 to 170d), and at least one of the plurality of signal processing devices (170 to 170d) can control the operation of the fan driving unit (not shown) to reduce internal heat based on the detected temperature.

[0104] Meanwhile, an image display device (100A) according to an embodiment of the present disclosure may include an image receiving unit (105), a memory (140), a user input interface unit (150), a sensor unit (not shown), a signal processing unit (170), a display (180), and an audio output unit (185).

[0105] The video receiving unit (105) may include a tuner unit (110), a demodulation unit (120), a network interface unit (130), and an external device interface unit (130).

[0106] Meanwhile, unlike the drawing, the video receiving unit (105) may include only a tuner unit (110), a demodulator unit (120), and an external device interface unit (130). That is, it may not include a network interface unit (130).

[0107] The tuner unit (110) selects an RF broadcast signal corresponding to a channel selected by the user or all pre-stored channels among RF (Radio Frequency) broadcast signals received through an antenna (not shown). In addition, it converts the selected RF broadcast signal into an intermediate frequency signal or a baseband video or audio signal.

[0108] For example, if the selected RF broadcast signal is a digital broadcast signal, it is converted into a digital IF signal (DIF), and if it is an analog broadcast signal, it is converted into an analog baseband video or audio signal (CVBS / SIF). That is, the tuner unit (110) can process a digital broadcast signal or an analog broadcast signal. The analog baseband video or audio signal (CVBS / SIF) output from the tuner unit (110) can be directly input to the signal processing device (170).

[0109] Meanwhile, the tuner unit (110) may be equipped with multiple tuners to receive broadcast signals of multiple channels. Alternatively, a single tuner that simultaneously receives broadcast signals of multiple channels is also possible.

[0110] The demodulation unit (120) receives the digital IF signal (DIF) converted from the tuner unit (110) and performs a demodulation operation.

[0111] The demodulator (120) can output a stream signal (TS) after performing demodulation and channel decoding. At this time, the stream signal may be a signal in which a video signal, an audio signal, or a data signal is multiplexed.

[0112] The stream signal output from the demodulator (120) can be input to the signal processing device (170). The signal processing device (170) performs demultiplexing, image / audio signal processing, etc., and then outputs an image to the display (180) and outputs an audio to the audio output device (185).

[0113] The external device interface unit (130) can transmit or receive data to or from a connected external device (not shown), for example, a set-top box (50). To this end, the external device interface unit (130) may include an A / V input / output unit (not shown).

[0114] The external device interface unit (130) can be connected to external devices such as a DVD (Digital Versatile Disk), Blu-ray, game device, camera, camcorder, computer (laptop), set-top box, etc., via wired / wireless connection, and can also perform input / output operations with the external devices.

[0115] The A / V input / output unit can receive video and audio signals from an external device. Meanwhile, the wireless communication unit (not shown) can perform short-range wireless communication with other electronic devices.

[0116] Through this wireless communication unit (not shown), the external device interface unit (130) can exchange data with an adjacent mobile terminal (600). In particular, the external device interface unit (130) can receive device information, running application information, application images, etc. from the mobile terminal (600) in mirroring mode.

[0117] The network interface unit (135) provides an interface for connecting the video display device (100) to a wired / wireless network, including the Internet. For example, the network interface unit (135) can receive content or data provided by the Internet, a content provider, or a network operator via a network.

[0118] Meanwhile, the network interface unit (135) may include a wireless communication unit (not shown).

[0119] The memory (140) may store a program for each signal processing and control within the signal processing device (170), and may also store a signal-processed image, voice, or data signal.

[0120] In addition, the memory (140) may also perform a function for temporary storage of video, audio, or data signals input to the external device interface unit (130). In addition, the memory (140) may store information about a specific broadcast channel through a channel memory function such as a channel map.

[0121] Although the memory (140) of FIG. 2 illustrates an embodiment in which the memory (140) is provided separately from the signal processing device (170), the scope of the present disclosure is not limited thereto. The memory (140) may be included within the signal processing device (170).

[0122] The user input interface unit (150) transmits a signal input by the user to the signal processing device (170) or transmits a signal from the signal processing device (170) to the user.

[0123] For example, a user input signal such as power on / off, channel selection, screen setting, etc. may be transmitted / received from a remote control device (200), a user input signal input from a local key (not shown) such as a power key, a channel key, a volume key, a setting value, etc. may be transmitted to a signal processing device (170), a user input signal input from a sensor unit (not shown) that senses a user's gesture may be transmitted to the signal processing device (170), or a signal from the signal processing device (170) may be transmitted to a sensor unit (not shown).

[0124] The signal processing device (170) can demultiplex an input stream or process demultiplexed signals through a tuner unit (110), a demodulator unit (120), a network interface unit (135), or an external device interface unit (130) to generate and output a signal for video or audio output.

[0125] For example, the signal processing device (170) can receive a broadcast signal or an HDMI signal received from the image receiving unit (105), perform signal processing based on the received broadcast signal or HDMI signal, and output a signal-processed image signal.

[0126] An image signal processed by a signal processing device (170) may be input to a display (180) and displayed as an image corresponding to the image signal. In addition, an image signal processed by a signal processing device (170) may be input to an external output device through an external device interface unit (130).

[0127] The voice signal processed in the signal processing device (170) can be output as sound to the audio output unit (185). In addition, the voice signal processed in the signal processing device (170) can be input to an external output device through the external device interface unit (130).

[0128] Although not illustrated in FIG. 2, the signal processing device (170) may include a demultiplexing unit, an image processing unit, etc. That is, the signal processing device (170) may perform various signal processing operations and, accordingly, may be implemented in the form of a system on chip (SOC). This will be described later with reference to FIG. 3.

[0129] In addition, the signal processing device (170) can control the overall operation within the video display device (100). For example, the signal processing device (170) can control the tuner unit (110) to select (tune) an RF broadcast corresponding to a channel selected by a user or a pre-stored channel.

[0130] In addition, the signal processing device (170) can control the image display device (100) by a user command or internal program input through the user input interface unit (150).

[0131] Meanwhile, the signal processing device (170) can control the display (180) to display an image. At this time, the image displayed on the display (180) may be a still image or a moving image, and may be a 2D image or a 3D image.

[0132] Meanwhile, the signal processing device (170) can cause a predetermined object to be displayed within an image displayed on the display (180). For example, the object can be at least one of a connected web screen (newspaper, magazine, etc.), an EPG (Electronic Program Guide), various menus, widgets, icons, still images, videos, and text.

[0133] Meanwhile, the signal processing device (170) can recognize the user's location based on an image captured from a camera (not shown). For example, the distance (z-axis coordinate) between the user and the image display device (100) can be determined. In addition, the x-axis coordinate and y-axis coordinate within the display (180) corresponding to the user's location can be determined.

[0134] The display (180) generates a driving signal by converting a video signal, data signal, OSD signal, control signal, etc. processed by the signal processing device (170) or a video signal, data signal, control signal, etc. received from the external device interface unit (130).

[0135] Meanwhile, the display (180) is configured as a touch screen and can be used as an input device in addition to an output device.

[0136] The audio output unit (185) receives a signal processed by the signal processing device (170) and outputs it as voice.

[0137] A camera unit (not shown) photographs a user. The camera unit (not shown) may be implemented with a single camera, but is not limited thereto, and may also be implemented with multiple cameras. Image information captured by the camera unit (not shown) may be input to a signal processing device (170).

[0138] The signal processing device (170) can detect the user's gesture based on an image captured from a shooting unit (not shown) or a signal detected from a sensor unit (not shown), or a combination thereof.

[0139] The power supply unit (190) supplies power to the entire image display device (100). In particular, the power supply unit (190) can supply power to a signal processing device (170) that can be implemented in the form of a system on chip (SOC), a display (180) for image display, and an audio output unit (185) for audio output.

[0140] Specifically, the power supply unit (190) may be equipped with a converter that converts AC power into DC power and a dc / dc converter that converts the level of the DC power.

[0141] The remote control device (200) transmits user input to the user input interface unit (150). To this end, the remote control device (200) may use Bluetooth, RF (Radio Frequency) communication, IR (Infrared) communication, UWB (Ultra Wideband), ZigBee, etc. In addition, the remote control device (200) may receive video, audio, or data signals output from the user input interface unit (150) and display or output the same as audio on the remote control device (200).

[0142] Meanwhile, the above-described video display device (100) may be a digital broadcast receiver capable of receiving fixed or mobile digital broadcasts.

[0143] Meanwhile, the block diagram of the image display device (100) illustrated in FIG. 3 is a block diagram for one embodiment of the present disclosure. Each component of the block diagram may be integrated, added, or omitted depending on the specifications of the image display device (100) actually implemented. That is, two or more components may be combined into one component, or one component may be subdivided into two or more components, as needed. In addition, the functions performed by each block are intended to explain the embodiment of the present disclosure, and the specific operations or devices thereof do not limit the scope of the present disclosure.

[0144] Figure 3 is an example of an internal block diagram of the signal processing device of Figure 2.

[0145] Referring to the drawings, a signal processing device (170) according to an embodiment of the present disclosure may include a demultiplexing unit (310), an image processing unit (320), a processor (330), and an audio processing unit (370). In addition, a data processing unit (not shown) may be further included.

[0146] The demultiplexer (310) demultiplexes the input stream. For example, when MPEG-2 TS is input, it can be demultiplexed to separate it into video, audio, and data signals, respectively. Here, the stream signal input to the demultiplexer (310) may be a stream signal output from the tuner (110), the demodulator (120), or the external device interface (130).

[0147] The image processing unit (320) can perform signal processing on an input image. For example, the image processing unit (320) can perform image processing on an image signal demultiplexed from the demultiplexing unit (310).

[0148] To this end, the image processing unit (320) may include an image decoder (325), a scaler (335), an image quality processing unit (635), an image encoder (not shown), an OSD processing unit (340), a frame image rate conversion unit (350), and a formatter (360).

[0149] The video decoder (325) decodes the demultiplexed video signal, and the scaler (335) scales the resolution of the decoded video signal so that it can be output on the display (180).

[0150] The video decoder (325) can be equipped with decoders of various standards. For example, it can be equipped with an MPEG-2, H.264 decoder, a 3D video decoder for color images and depth images, a decoder for multi-view images, etc.

[0151] The scaler (335) can scale an input video signal that has been decoded by a video decoder (325), etc.

[0152] For example, the scaler (335) can upscale when the size or resolution of the input image signal is small, and downscale when the size or resolution of the input image signal is large.

[0153] The image quality processing unit (635) can perform image quality processing on an input image signal for which image decoding has been completed in the image decoder (325), etc.

[0154] For example, the image quality processing unit (635) may perform noise removal processing of an input image signal, expand the resolution of the gradation of an input image signal, perform image resolution enhancement, perform signal processing based on high dynamic range (HDR), vary the frame image rate, or perform image quality processing corresponding to panel characteristics, particularly a light-emitting panel.

[0155] The OSD processing unit (340) generates an OSD signal based on user input or on its own. For example, based on a user input signal, a signal for displaying various information in the form of graphics or text on the screen of the display (180) may be generated. The generated OSD signal may include various data such as the user interface screen of the image display device (100), various menu screens, widgets, and icons. In addition, the generated OSD signal may include a 2D object or a 3D object.

[0156] In addition, the OSD processing unit (340) can generate a pointer that can be displayed on the display based on a pointing signal input from the remote control device (200). In particular, such a pointer can be generated by the pointing control unit, and the OSD processing unit (240) can include such a pointing control unit (not shown). Of course, the pointing control unit (not shown) can also be provided separately rather than being included within the OSD processing unit (240).

[0157] The frame rate converter (FRC) (350) can convert the frame rate of an input video. Meanwhile, the frame rate converter (350) can also output the video as is without a separate frame rate conversion.

[0158] Meanwhile, the formatter (360) can change the format of an input video signal into a video signal for display on a display and output it.

[0159] In particular, the formatter (360) can change the format of the video signal to correspond to the display panel.

[0160] The processor (330) can control the overall operation within the image display device (100) or the signal processing device (170).

[0161] For example, the processor (330) can control the tuner (110) to select (tuning) an RF broadcast corresponding to a channel selected by the user or a pre-stored channel.

[0162] In addition, the processor (330) can control the image display device (100) by a user command or internal program input through the user input interface unit (150).

[0163] Additionally, the processor (330) can perform data transmission control with the network interface unit (135) or the external device interface unit (130).

[0164] Additionally, the processor (330) can control the operation of the demultiplexing unit (310), the image processing unit (320), etc., within the signal processing device (170).

[0165] Meanwhile, the audio processing unit (370) within the signal processing device (170) can perform audio processing of the demultiplexed audio signal. For this purpose, the audio processing unit (370) can be equipped with various decoders.

[0166] Additionally, the audio processing unit (370) within the signal processing device (170) can process bass, treble, volume control, etc.

[0167] A data processing unit (not shown) within a signal processing device (170) can perform data processing on a demultiplexed data signal. For example, if the demultiplexed data signal is an encoded data signal, it can be decoded. The encoded data signal may be electronic program guide information (EPG) information that includes broadcast information such as the start time and end time of a broadcast program broadcast on each channel.

[0168] Meanwhile, the block diagram of the signal processing device (170) illustrated in FIG. 4 is a block diagram for one embodiment of the present disclosure. Each component of the block diagram may be integrated, added, or omitted depending on the specifications of the signal processing device (170) actually implemented.

[0169] In particular, the frame image rate conversion unit (350) and the formatter (360) may be provided separately from the image processing unit (320).

[0170] Figure 4 is an internal block diagram of the display of Figure 2.

[0171] Referring to the drawing, a display (180) based on a light-emitting panel may include a light-emitting panel (210), a first interface unit (230), a second interface unit (231), a timing controller (232), a scan driver unit (234), a data driver unit (236), a memory (240), a power supply unit (290), etc.

[0172] The display (180) receives a video signal (Vd), a first DC power source (V1), and a second DC power source (V2), and can display a predetermined image based on the video signal (Vd).

[0173] Meanwhile, the first interface unit (230) within the display (180) can receive a video signal (Vd) and a first DC power source (V1) from the signal processing device (170).

[0174] Here, the first DC power supply (V1) can be used for the operation of the power supply (290) and the timing controller (232) within the display (180).

[0175] Next, the second interface unit (231) can receive a second DC power supply (V2) from an external power supply unit (190). Meanwhile, the second DC power supply (V2) can be input to a data drive unit (236) within the display (180).

[0176] The timing controller (232) can output a data drive signal (Sda) and a scan drive signal (Sga) based on a video signal (Vd).

[0177] For example, when the first interface unit (230) converts an input image signal (Vd) and outputs a converted image signal (va1), the timing controller (232) can output a data drive signal (Sda) and a scan drive signal (Sga) based on the converted image signal (va1).

[0178] The timing controller (232) can receive, in addition to the video signal (Vd) from the signal processing device (170), a control signal, a vertical synchronization signal (Vsync), etc.

[0179] In addition, the timing controller (232) can output a scan drive signal (Sga) for the operation of the scan drive unit (234) and a data drive signal (Sda) for the operation of the data drive unit (236) based on a control signal, a vertical synchronization signal (Vsync), etc., in addition to a video signal (Vd).

[0180] The data driving signal (Sda) at this time may be a data driving signal for driving RGB subpixels when the panel (210) has RGB subpixels.

[0181] Meanwhile, the timing controller (232) can further output a control signal (Cs) to the scan driver (234).

[0182] The scan driving unit (234) and the data driving unit (236) supply scan signals and data signals to the light-emitting panel (210) through the scan line (GL) and the data line (DL), respectively, in accordance with the scan driving signal (Sga) and the data driving signal (Sda) from the timing controller (232). Accordingly, the light-emitting panel (210) displays a predetermined image.

[0183] Meanwhile, the light-emitting panel (210) may include a light-emitting layer, and in order to display an image, a plurality of scan lines (GL) and data lines (DL) may be arranged in a matrix form to cross each pixel corresponding to the light-emitting layer.

[0184] Meanwhile, the data driving unit (236) can output a data signal to the light-emitting panel (210) based on the second direct current power supply (V2) from the second interface unit (231).

[0185] The power supply unit (290) can supply various power sources to the scan driving unit (234), the data driving unit (236), the timing controller (232), etc.

[0186] Meanwhile, the timing controller (232), scan driver (234), and data driver (236) in the drawing can be implemented as a single integrated circuit (IC).

[0187] Accordingly, the timing controller (232), scan driver (234), and data driver (236) may be named a drive control unit (285).

[0188] Meanwhile, the drive control unit (285) may include a buffer (238) that stores frame data.

[0189] In particular, the timing controller (232) in the driving control unit (285) can output a gate signal and a data signal for image display based on frame data stored in the buffer (238).

[0190] FIGS. 5A to 5C are drawings for reference in the description of the light-emitting panel of FIG. 4.

[0191] First, FIG. 5a is a drawing showing pixels within a light-emitting panel (210).

[0192] Referring to the drawing, the light-emitting panel (210) may have a plurality of scan lines (Scan 1 to Scan n) and a plurality of data lines (R1, G1, B1 to Rm, Gm, Bm) intersecting therewith.

[0193] Meanwhile, a pixel (subpixel) is defined in the intersection area of ​​the scan line and the data line within the light-emitting panel (210). In the drawing, a pixel (Pixel) having RGB subpixels (SR1, SG1, SB1) is illustrated.

[0194] Meanwhile, red light-emitting diodes, green light-emitting diodes, and blue light-emitting diodes are placed in each of the RGB subpixels (SR1, SG1, SB1).

[0195] FIG. 5b illustrates the circuit of one subpixel within a pixel of the light-emitting panel of FIG. 5a.

[0196] Referring to the drawing, the light-emitting sub-pixel circuit (CRTm) may be of a passive type and may only include a light-emitting diode (LED) without a separate switching element.

[0197] As shown in the drawing, the anode of the light emitting diode (LED) is connected to a data line, so that a data signal (Vdata) can be input, and the cathode of the light emitting diode (LED) is connected to a scan line, so that a scan signal (Vscan) can be input.

[0198] Meanwhile, light-emitting diodes can emit light or not, based on multiple sub-frames based on a passive matrix method.

[0199] Figure 5c is a diagram showing examples of scan signals and data signals.

[0200] Referring to the drawing, the scan signal (Vscan) applied to each of the red light-emitting diode, green light-emitting diode, and blue light-emitting diode maintains the LVb level and then drops to the LVa level at the scan timing.

[0201] At this time, the width of the scan signal (Vscan) can be set to Wa.

[0202] Meanwhile, red light-emitting diodes may have higher luminous efficiency than green light-emitting diodes and blue light-emitting diodes due to their device characteristics.

[0203] In response to this, the driving control unit (285) can control the level of the data signal supplied to the red light-emitting diode to be lower than the level of the data signal supplied to the green light-emitting diode or the blue light-emitting diode.

[0204] Figure 5c (b) illustrates a data signal (Vdata) that maintains the level of LVd and then rises to the level of LVc in response to the scan timing of the scan signal (Vscan).

[0205] (c) of Fig. 5c illustrates a data signal (Vdatam) that maintains the level of LVd and then rises to the LVe level, which is higher than the LVc level, in response to the scan timing of the scan signal (Vscan).

[0206] A data signal (Vdata) of LVc level can be applied to a red light-emitting diode, and a data signal (Vdatam) of LVe level higher than the LVc level is preferably applied to a green light-emitting diode or a blue light-emitting diode.

[0207] Accordingly, it is possible to output a data signal corresponding to the light-emitting diode, and further perform uniform color implementation.

[0208] Meanwhile, the data signal (Vdata) of (b) of Fig. 5c or the data signal (Vdatam) of (c) of Fig. 5c is a data signal based on pulse width variation, and the brightness of the light-emitting diode is varied by variation of the duty corresponding to the pulse width.

[0209] Fig. 6 is a drawing illustrating an example of the light-emitting panel of Fig. 4.

[0210] Referring to the drawing, the light-emitting panel (210) may have a plurality of data lines and a plurality of scan lines.

[0211] In Fig. 6, as an example of a light-emitting panel (210), for convenience of explanation, four data lines (Data 1 to Data 4) and four scan lines (Scan 1 to Scan 4) are illustrated.

[0212] FIGS. 7A to 7D are drawings for reference in explaining the operation of a video display device related to the present disclosure.

[0213] FIG. 7a illustrates an example of a data signal applied corresponding to a case where the frame grayscale is the first grayscale during a plurality of sub-frame periods within a frame period.

[0214] Referring to the drawing, a plurality of sub-frame periods (Subframe 1 to 3) may be provided within a frame period (Frame 1).

[0215] For convenience of explanation, the drawing illustrates three subframe periods (Subframe 1 to 3) within a frame period (Frame 1), but various variations are possible.

[0216] (a) of FIG. 7a illustrates that data signals (Vdata 1 to 4) are applied to each of the four data lines illustrated in FIG. 6 during the first subframe (Subframe 1) period among multiple subframe periods (Subframe 1 to 3).

[0217] In the drawing, during the first subframe (Subframe 1) period, data signals (Vdata 1 to 4) each having four pulses or voltages (Vx) on four data lines are illustrated.

[0218] At this time, the pulse width of the data signal (Vdata 1~4) can be Wx.

[0219] Figure 7a (b) illustrates that during the first subframe (Subframe 1), scan signals (Vscan 1 to 4) are sequentially applied to each of the four scan lines.

[0220] Accordingly, during the first subframe (Subframe 1) period, 16 light-emitting diodes emit light, as shown in (c) of Fig. 7a.

[0221] Figure 7a (a) illustrates that during the second subframe (Subframe 2) period, data signals (Vdata 1 to 4) are applied to each of the four data lines illustrated in Figure 6.

[0222] In the drawing, during the second subframe (Subframe 2) period, data signals (Vdata 1 to 4) each having one pulse or voltage (Vx) on four data lines are illustrated.

[0223] Figure 7a (b) illustrates that during the second subframe (Subframe 2) period, scan signals (Vscan 1 to 4) are sequentially applied to each of the four scan lines.

[0224] Accordingly, during the second subframe (Subframe 2) period, four light-emitting diodes in the diagonal direction emit light, as shown in (c) of Fig. 7a.

[0225] Figure 7a (a) illustrates that during the third subframe (Subframe 3) period, data signals (Vdata 1 to 4) are applied to each of the four data lines illustrated in Figure 6.

[0226] In the drawing, during the third subframe (Subframe 3) period, data signals (Vdata 1 to 4) each having one pulse or voltage (Vx) on four data lines are illustrated.

[0227] Figure 7a (b) illustrates that during the third subframe (Subframe 3), scan signals (Vscan 1 to 4) are sequentially applied to each of the four scan lines.

[0228] Accordingly, during the third subframe (Subframe 3), four light-emitting diodes in the diagonal direction emit light, as shown in (c) of Fig. 7a.

[0229] FIG. 7b illustrates an example of a data signal applied in response to a case where the frame grayscale is a second grayscale lower than the first grayscale during a plurality of sub-frame periods within a frame period.

[0230] (a) of FIG. 7b illustrates that data signals (Vdata 1 to 4) are applied to each of the four data lines illustrated in FIG. 6 during the first subframe (Subframe 1) period among multiple subframe periods (Subframe 1 to 3).

[0231] In the drawing, during the first subframe (Subframe 1) period, data signals (Vdata 1 to 4) each having four pulses or voltages (Vx) on four data lines are illustrated.

[0232] At this time, the pulse width of the data signal (Vdata 1~4) can be Wx.

[0233] (b) of Fig. 7b illustrates that scan signals (Vscan 1 to 4) are sequentially applied to each of four scan lines during a period of multiple subframes (Subframe 1 to 3).

[0234] Accordingly, during the first subframe (Subframe 1) period, 16 light-emitting diodes emit light, as shown in (c) of Fig. 7b.

[0235] Meanwhile, (a) of FIG. 7b illustrates that during the second subframe (Subframe 2) period among multiple subframe periods (Subframe 1 to 3), data signals (Vdata 1 to 4) each having one pulse or voltage (Vx) are applied to the four data lines illustrated in FIG. 6, and during the third subframe (Subframe 3) period, no pulse or voltage (Vx) is applied.

[0236] Accordingly, during the second subframe (Subframe 2) period, four light-emitting diodes in the diagonal direction, as shown in (c) of Fig. 7b, emit light, and during the third subframe (Subframe 3) period, all 16 light-emitting diodes are turned off and do not emit light.

[0237] FIG. 7c illustrates an example of a data signal applied in response to a case where the frame grayscale is a third grayscale lower than the second grayscale during a plurality of sub-frame periods within a frame period.

[0238] (a) of FIG. 7c illustrates that during the first subframe (Subframe 1) period among multiple subframes (Subframes 1 to 3), data signals (Vdata 1 to 4) each having one pulse or voltage (Vx) are applied to the four data lines illustrated in FIG. 6, and during the second subframe (Subframe 2) period and the third subframe (Subframe 3) period, no pulse or voltage (Vx) is applied.

[0239] Figure 7c (b) illustrates that scan signals (Vscan 1 to 4) are sequentially applied to each of four scan lines during a period of multiple subframes (Subframe 1 to 3).

[0240] Accordingly, during the first subframe (Subframe 1) period, four light-emitting diodes in the diagonal direction, as shown in (c) of Fig. 7c, emit light, and during the second subframe (Subframe 2) period and the third subframe (Subframe 3) period, all 16 light-emitting diodes are turned off and do not emit light.

[0241] FIG. 8 is a drawing illustrating an example of a light-emitting panel according to one embodiment of the present disclosure.

[0242] Referring to the drawing, a light emitting panel (210) according to one embodiment of the present disclosure has a plurality of driving control units (285a to 285h).

[0243] In the drawing, the driving control units (285a to 285h) arranged in n*4 are exemplified, but this is not limited to this and various modifications are possible.

[0244] Meanwhile, each driving control unit (285a to 285h) outputs a scan signal to a plurality of light-emitting diodes for each of a plurality of sub-frame periods and outputs a data signal for image display.

[0245] For example, each drive control unit (285a to 285h) can output a data signal based on pulse width modulation (PWM) based on a constant current source.

[0246] FIGS. 9A to 9D are drawings for reference in explaining the operation of a video display device related to the present disclosure.

[0247] FIG. 9a illustrates a clock signal (GCLKx) and a scan signal (SCx) and a data signal (DTx) based on the clock signal (GCLKx) in connection with the present disclosure.

[0248] The data signal (DTx) may be a pulse width modulation (PWM)-based data signal based on a constant current source.

[0249] FIG. 9b illustrates multiple subframes related to the present disclosure.

[0250] Referring to the drawing, four scan signals (scan0 to scan3) can be applied during each of four subframes (SF1 to SF4).

[0251] The four scan signals (scan0 to scan3) at this time may be scan signals based on the clock signal (GCLKx) of Fig. 9a.

[0252] Meanwhile, a data signal based on pulse width variation can be applied in response to four scan signals (scan0 to scan3).

[0253] Figure 9c illustrates a tone allocation method related to the present disclosure.

[0254] Referring to the drawing, 1 to 25 grayscale levels can be allocated using four sub-frame periods (SF1 to SF4).

[0255] For example, for the expression of 1 tone, a data signal of a first pulse width can be applied to the light-emitting diode during the first sub-frame period (SF1).

[0256] As another example, for the expression of two tones, a data signal of a first pulse width can be applied to the light-emitting diode during the first sub-frame period (SF1) and the third sub-frame period (SF3).

[0257] As another example, for the expression of 5 gradations, during the first sub-frame period (SF1), a data signal having a second pulse width that is twice the first pulse width may be applied to the light-emitting diode, and during the second to fourth sub-frame periods (SF2 to SF4), a data signal having the first pulse width may be applied to the light-emitting diode.

[0258] As another example, for the expression of 25 gray levels, during the first sub-frame period (SF1), a data signal having a pulse width that is 7 times the first pulse width may be applied to the light-emitting diode, and during the second to fourth sub-frame periods (SF2 to SF4), a data signal having a pulse width that is 6 times the first pulse width may be applied to the light-emitting diode.

[0259] Figure 9d illustrates the current change of a light-emitting diode corresponding to the frequency change of a clock signal.

[0260] Referring to the drawing, as the frequency of the clock signal increases, the current of the light-emitting diode increases, which ultimately increases the power consumption of the video display device.

[0261] Referring to FIGS. 9a to 9d, as the bit depth of the data signal increases, the grayscale expressiveness increases, so when driving multiple light-emitting diodes, a high-speed clock signal (GCLKx) is required.

[0262] For example, as the frequency of the clock signal (GCLKx) increases, the power consumption of the video display device increases.

[0263] Meanwhile, in order to reduce power consumption of a video display device, when the bit depth of the data signal is reduced and the frequency of the clock signal (GCLKx) is reduced, there is a problem of reduced grayscale expressiveness. Therefore, the present disclosure proposes a method for reducing power consumption while maintaining grayscale expressiveness.

[0264] FIG. 10 is a diagram showing the operation of a video display device according to one embodiment of the present disclosure.

[0265] Referring to the drawing, the driving control unit (285) determines whether a sub-frame period is one of a plurality of sub-frame periods (S1010), and if so, turns on or off a plurality of light-emitting diodes based on the first clock signal (S1015).

[0266] Next, the driving control unit (285), in step 1010 (S1010), determines whether some of the sub-frame periods are not sub-frame periods among the plurality of sub-frame periods (S1020), and if so, turns on or off the plurality of light-emitting diodes based on a second clock signal that is different from the first clock signal during some of the other sub-frame periods among the plurality of sub-frame periods (S1025).

[0267] Accordingly, power consumption can be reduced while maintaining gradation expressivity. In particular, power consumption can be reduced while maintaining bit depth.

[0268] Meanwhile, the driving control unit (285) can control the frequency of the second clock signal to be lower than the frequency of the first clock signal. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0269] That is, the driving control unit (285) according to one embodiment of the present disclosure performs grayscale allocation using the frequencies of multiple clock signals, rather than the frequency of the fixed clock signal of FIGS. 9A to 9C . Accordingly, power consumption can be reduced while maintaining grayscale expressiveness. In particular, power consumption can be reduced while maintaining bit depth.

[0270] Figures 11a to 23 are drawings referred to in the description of Figure 10.

[0271] First, FIG. 11A is an example of a plurality of subframes according to an embodiment of the present disclosure.

[0272] Referring to the drawings, a driving control unit (285) according to one embodiment of the present disclosure can turn on or off a plurality of light-emitting diodes based on a first clock signal during a first sub-frame period (SF1) among a plurality of sub-frame periods (SF1 to SF5), and can turn on or off a plurality of light-emitting diodes based on a second clock signal during a sub-frame period (SF2 to SF5) after the first sub-frame period (SF1) among a plurality of sub-frame periods (SF1 to SF5).

[0273] Specifically, the driving control unit (285) can turn on or off a plurality of light-emitting diodes based on a first clock signal during a first sub-frame period (SF1) among a plurality of sub-frame periods (SF1 to SF5), and can turn on or off a plurality of light-emitting diodes based on a second clock signal during a second to fifth sub-frame periods (SF2 to SF5) among a plurality of sub-frame periods (SF1 to SF5).

[0274] At this time, it is desirable for the frequency of the first clock signal to be higher than that of the second clock signal. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0275] FIG. 11b illustrates a scan signal and a data signal based on the first clock signal of FIG. 11a, and a scan signal and a data signal based on the second clock signal.

[0276] Referring to the drawing, the driving control unit (285) can output a scan signal (SCa) and a data signal (DTa) based on a first clock signal (GCLKa), a scan signal (SCb) and a data signal (DTb) based on a second clock signal (GCLKb).

[0277] For example, the driving control unit (285) can output a first scan signal (SCa) and a first data signal (DTa) based on a pulse width variable based on a first clock signal (GCLKa) during a first sub-frame period (SF1) among a plurality of sub-frame periods (SF1 to SF5).

[0278] As another example, the driving control unit (285) can output a second scan signal (SCb) and a second data signal (DTb) based on a pulse width variable based on a second clock signal (GCLKb) during the second to fifth sub-frame periods (SF2 to SF5) among a plurality of sub-frame periods (SF1 to SF5).

[0279] Figure 11c illustrates an example of tone allocation based on Figures 11a to 11b.

[0280] Referring to the drawing, the driving control unit (285) can allocate 1 to 26 grayscale levels using five sub-frame periods (SF1 to SF5).

[0281] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0282] As another example, for the expression of two tones, the driving control unit (285) can apply a second data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the second sub-frame period (SF2).

[0283] Meanwhile, since the frequency of the first clock signal (clk) is twice the frequency of the second clock signal (1 / 2*clk), it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0284] That is, the meaning of 1 tone in SF2 to SF5 in the drawing can correspond to 1*2 tone.

[0285] As another example, for the expression of 5 gradations, the driving control unit (285) may apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1), and apply a second data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the second sub-frame period (SF2) and the fourth sub-frame period (SF4).

[0286] Figure 11d illustrates another example of tone assignment based on Figures 11a to 11b.

[0287] Referring to the drawing, the driving control unit (285) can allocate 1 to 26 grayscale levels using five sub-frame periods (SF1 to SF5).

[0288] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the fifth sub-frame period (SF5), which is the last sub-frame.

[0289] As another example, for the expression of two tones, the driving control unit (285) can apply a second data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the first sub-frame period (SF1).

[0290] Meanwhile, since the frequency of the first clock signal (clk) is twice the frequency of the second clock signal (1 / 2*clk), it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0291] That is, the meaning of 1 tone in SF1 to SF4 in the drawing can correspond to 1*2 tone.

[0292] As another example, for the expression of 5 gradations, the driving control unit (285) may apply a second data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the first sub-frame period (SF1) and the third sub-frame period (SF3), and may apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the fifth sub-frame period (SF5).

[0293]

[0294] Figures 12a to 12c are drawings illustrating various types of sub-frames.

[0295] Figure 12a illustrates placing a subframe with a higher clock signal frequency as the last subframe.

[0296] Referring to the drawing, the driving control unit (285) can turn on or off a plurality of light-emitting diodes based on a first clock signal during the last sub-frame period (SF5) among a plurality of sub-frame periods (SF1 to SF5), and can turn on or off a plurality of light-emitting diodes based on a second clock signal during a sub-frame period (SF1 to SF4) prior to the last sub-frame period (SF5) among a plurality of sub-frame periods (SF1 to SF5).

[0297] At this time, the frequency of the first clock signal used in the last sub-frame period (SF5) may be higher than the frequency of the second clock signal used in the first to fourth sub-frame periods (SF1 to SF4). Accordingly, power consumption can be reduced while maintaining grayscale expressiveness.

[0298] Figure 12b illustrates placing a subframe with a higher clock signal frequency as the first subframe.

[0299] Referring to the drawing, the driving control unit (285) can turn on or off a plurality of light-emitting diodes based on a first clock signal during a first sub-frame period (SF1) among a plurality of sub-frame periods (SF1 to SF5), and can turn on or off a plurality of light-emitting diodes based on a second clock signal during a sub-frame period (SF2 to SF5) after the first sub-frame period (SF1) among a plurality of sub-frame periods (SF1 to SF5).

[0300] At this time, the frequency of the first clock signal used in the first sub-frame period (SF1) may be higher than the frequency of the second clock signal used in the second to fifth sub-frame periods (SF2 to SF5). Accordingly, power consumption can be reduced while maintaining grayscale expressiveness.

[0301] Figure 12c illustrates placing a subframe with a higher clock signal frequency between the first subframe and the last subframe.

[0302] Referring to the drawing, the driving control unit (285) can turn on or off a plurality of light-emitting diodes based on a second clock signal during a first sub-frame period (SF1) and a last sub-frame period (SF5) among a plurality of sub-frame periods (SF1 to SF5), and can turn on or off a plurality of light-emitting diodes based on a first clock signal during a part of a sub-frame period (SF3) between the first sub-frame period (SF1) and the last sub-frame period (SF5). Accordingly, power consumption can be reduced while maintaining grayscale expressiveness.

[0303] Referring to FIGS. 12A to 12C, the driving control unit (285) can control the position of some sub-frame periods operating at the frequency of the first clock signal to vary from frame to frame. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0304] Referring to FIGS. 12A to 12C, the driving control unit (285) can output a first scan signal corresponding to the first clock signal to a plurality of light-emitting diodes during some sub-frame periods operating at the frequency of the first clock signal.

[0305] Meanwhile, the driving control unit (285) can output a second scan signal corresponding to the second clock signal to a plurality of light-emitting diodes during some other sub-frame period operating at the frequency of the second clock signal.

[0306] At this time, it is preferable that the pulse width of the second scan signal be larger than the pulse width of the first clock signal.

[0307] That is, the driving control unit (285) can output a first scan signal corresponding to a first clock signal to a plurality of light-emitting diodes during some sub-frame periods among the plurality of sub-frame periods (SF1 to SF5), and can output a second scan signal corresponding to a second clock signal to a plurality of light-emitting diodes during some other sub-frame periods among the plurality of sub-frame periods (SF1 to SF5). Accordingly, it is possible to reduce power consumption while maintaining grayscale expressiveness.

[0308] Meanwhile, FIGS. 12a to 12c illustrate that among multiple sub-frame periods (SF1 to SF5), only one sub-frame period operates based on the first clock signal, but variations thereof are possible.

[0309] For example, unlike FIGS. 12A to 12C , the driving control unit (285) can control the number of sub-frame periods (SF1 to SF5) to be plural, operating based on the first clock signal among the plurality of sub-frame periods. Accordingly, power consumption can be reduced while maintaining grayscale expressiveness.

[0310] Meanwhile, the driving control unit (285) can control the number of some sub-frame periods operating based on the second clock signal to be greater than the number of some sub-frame periods operating based on the first clock signal. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0311] Meanwhile, the driving control unit (285) can control the positions of multiple sub-frame periods (SF1 to SF5) operating based on the first clock signal to vary for each frame. Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0312] Figure 12d illustrates that the position of the first clock signal with a higher frequency varies for each scan line.

[0313] Referring to the drawing, the driving control unit (285) can vary the position of the first clock signal with a higher frequency for each scan line during the sub-frame period.

[0314] For example, the driving control unit (285) can apply a first scan signal based on a first clock signal in a first sub-frame period (SF1) in a first scan line (Scan0), and can apply a second scan signal based on a second clock signal in the second to fourth sub-frame periods (SF2 to SF4). Accordingly, power consumption can be reduced while maintaining grayscale expressiveness.

[0315] As another example, the driving control unit (285) may apply a first scan signal based on a first clock signal in a second sub-frame period (SF2) in a second scan line (Scan1), and apply a second scan signal based on a second clock signal in the first and third to fourth sub-frame periods (SF1, SF to SF4). Accordingly, power consumption can be reduced while maintaining gradation expressiveness.

[0316] Figure 13 is an example of an internal circuit diagram of a drive control unit.

[0317] Referring to the drawing, a driving control unit (285m) according to an embodiment of the present disclosure includes a timing generator (1220) that outputs a scan signal or a data signal, and a data processor (1230) that performs data processing.

[0318] Meanwhile, the driving control unit (285m) according to the embodiment of the present disclosure may further include a command shift register (1204) that receives and outputs a command signal, an image data shift register (1202) that receives and outputs an image data signal, a frame memory (1208, 1209) that stores a plurality of outputs from the image data shift register (1202), and a multiplexer (1211) that multiplexes a plurality of outputs from the frame memory (1208, 1209).

[0319] A signal output from a multiplexer ((1211)) is input to a data processor (1230), and a signal output from the data processor (1230) can be input to a timing generator (1220).

[0320] Meanwhile, the driving control unit (285m) according to the embodiment of the present disclosure may further include an oscillator (1212) that outputs an oscillation signal and a phase-locked loop (PLL) (1215) that receives a clock signal and an oscillation signal from the outside.

[0321] Meanwhile, the scan signal output from the driving control unit (285m) is output to the scan switching element (SWC((1248), and can be output to the red switching element (SWR) for the red light-emitting diode, the green switching element (SWG) for the green light-emitting diode, and the blue switching element (SWB) for the blue light-emitting diode, which output the data signal output from the driving control unit (285m).

[0322] Meanwhile, a current source (1240) may be connected to each of the data switching elements (1245) including a red switching element (SWR), a green switching element (SWG), and a blue switching element (SWB).

[0323] Figure 14 illustrates a plurality of light emitting diodes.

[0324] Referring to the drawing, scan switching elements (SWC1 to SWCn) can be connected to cathodes of a plurality of light-emitting diodes, and data switching elements (SWD1 to SWDn) can be connected to anodes of a plurality of light-emitting diodes.

[0325] Meanwhile, the scan driving unit (234) of FIG. 4 may be equipped with a plurality of scan switching elements (SWC1 to SWCn), and the data driving unit (236) of FIG. 4 may be equipped with a plurality of data switching elements (SWD1 to SWDn).

[0326] FIG. 15 illustrates an example of an internal block diagram of a timing generator (1220) and a data processor (1230) of FIG. 13.

[0327] Referring to the drawing, the data processor (1230) can divide the data bits (1231) of the input image data signal into an LSB bit, an MSB bit, and an additional bit for the first clock signal.

[0328] Meanwhile, the data processor (1230) may be equipped with a lockup table (1232), a comparator (1234) that compares data from the lockup table with an LSB bit among data bits (1231), an adder (1236) that adds the result data of the comparator (1234) and an MSB bit among data bits (1231), and a register (1229) that stores the output of the adder (1236).

[0329] Meanwhile, the timing generator (1220) within the driving control unit (285) may include a first counter (1221) that performs counting based on a first clock signal (GCLK), a second counter (1221b) that performs counting based on a second clock signal (GCLK / 2 or GCLK / 4), and a multiplexer (1224) that outputs a first scan signal corresponding to the first clock signal or a second scan signal corresponding to the second clock signal based on the first counter or the second counter. Accordingly, it is possible to reduce power consumption while maintaining grayscale expressiveness.

[0330] Meanwhile, the timing generator (1220) within the driving control unit (285) may further include a first comparator (1222) that compares an additional bit among the data bits (1231) with the output data of the first counter (1221), and a second comparator (1222b) that compares data from the register (1229) with the output data of the second counter (1221b).

[0331] Meanwhile, the timing generator (1220) within the driving control unit (285) may further include a subframe controller (1227) for subframe control, a line controller (1226) for scan line control, and a sequence controller (1225) for sequence control.

[0332] Meanwhile, the multiplexer (1224) can output a data signal based on data from the sequence controller (1225), data from the first comparator (1222), and data from the second comparator (1222b).

[0333] Figures 16a to 16c are drawings referred to in the description of Figure 15.

[0334] Figure 16a illustrates an example of grayscale allocation based on a first clock signal (clk) and a second clock signal (clk / 2).

[0335] Referring to the drawing, the driving control unit (285) can allocate 1 to 26 grayscale levels using five sub-frame periods (SF1 to SF5).

[0336] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0337] As another example, for the expression of two tones, the driving control unit (285) can apply a second data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the second sub-frame period (SF2).

[0338] Meanwhile, since the frequency of the first clock signal (clk) is twice the frequency of the second clock signal (1 / 2*clk), it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0339] That is, the meaning of 1 tone in SF2 to SF5 in the drawing can correspond to 1*2 tone.

[0340] As another example, for the expression of 5 gradations, the driving control unit (285) may apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1), and apply a second data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the second sub-frame period (SF2) and the fourth sub-frame period (SF4).

[0341] Meanwhile, for the expression of 10 gray levels, the driving control unit (285) can apply a third data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the second sub-frame period (SF2), and can apply a second data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the third sub-frame period (SF3) and the fourth sub-frame period (SF4).

[0342] At this time, it is preferable that the pulse width of the third data signal be twice the pulse width of the second data signal.

[0343] Figure 16b illustrates an example of grayscale allocation based on a first clock signal (clk) and a second clock signal (clk / 4).

[0344] Referring to the drawing, the driving control unit (285) can allocate 1 to 26 grayscale levels using five sub-frame periods (SF1 to SF5).

[0345] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0346] As another example, for the expression of two tones, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0347] Meanwhile, it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0348] As another example, for the expression of 5 gradations, the driving control unit (285) may apply a first data signal based on a first clock signal (clk) to the light-emitting diode during a first sub-frame period (SF1), and apply a third data signal based on a second clock signal (1 / 4*clk) to the light-emitting diode during a second sub-frame period (SF2).

[0349] Meanwhile, since the frequency of the first clock signal (clk) is four times the frequency of the second clock signal (1 / 4*clk), it is preferable that the pulse width of the third data signal be four times the pulse width of the first data signal.

[0350] That is, the meaning of 1 tone in SF2 to SF5 in the drawing can correspond to 1*4 tone.

[0351] Meanwhile, for the expression of 20 gray levels, the driving control unit (285) can apply a fourth data signal based on the second clock signal (1 / 4*clk) to the light-emitting diode during the second sub-frame period (SF2), and can apply a third data signal based on the second clock signal (1 / 4*clk) to the light-emitting diode during the third sub-frame period (SF3) and the fourth sub-frame period (SF4).

[0352] At this time, it is preferable that the pulse width of the fourth data signal be twice the pulse width of the third data signal.

[0353] Figure 16c illustrates another example of grayscale allocation based on the first clock signal (clk) and the second clock signal (clk / 2).

[0354] Referring to the drawing, the driving control unit (285) can allocate 1 to 26 grayscale levels using five sub-frame periods (SF1 to SF5).

[0355] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0356] As another example, for the expression of two tones, the driving control unit (285) can apply a second data signal based on the first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0357] Meanwhile, it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0358] As another example, for the expression of 4 gradations, the driving control unit (285) can apply a third data signal based on the second clock signal (1 / 2*clk) to the light-emitting diode during the second sub-frame period (SF2) and the fourth sub-frame period (SF4).

[0359] Meanwhile, since the frequency of the first clock signal (clk) is twice the frequency of the second clock signal (1 / 2*clk), it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0360] That is, the meaning of 1 tone in SF2 to SF5 in the drawing can correspond to 1*2 tone.

[0361] Meanwhile, for the expression of 12 gradations, the driving control unit (285) can apply a fourth data signal based on the second clock signal (1 / 2*clk) to the light-emitting diode during the second sub-frame period (SF2) and the fourth sub-frame period (SF4).

[0362] At this time, it is preferable that the pulse width of the fourth data signal be twice the pulse width of the third data signal.

[0363] Figure 17a illustrates another example of an internal block diagram of the data processor of Figure 13.

[0364] Referring to the drawing, the internal configuration of the timing generator (1220) may be the same as the internal configuration of the timing generator (1220) of FIG. 15.

[0365] Meanwhile, the data processor (1230b) may be equipped with a quotient operator (1615) that performs a quotient operation on data (1612) obtained by dividing input image data (1611) by Q and then multiplying it by P, a remainder operator (1617) that performs a remainder operation, a lockup table (1232), a comparator (1234) that compares data from the lockup table with data from the remainder operator (1617), a summer (1236) that adds the result data of the comparator (1234) and the result data of the quotient operator (1615), and a register (1229) that stores the output of the summer (1236).

[0366] Meanwhile, the first comparator (1222) within the timing generator (1220) can compare the output data of the first counter (1221) with data (1612) among the remaining data (1613) after dividing the image data (1611) by Q.

[0367] FIG. 17b is a diagram referenced in the description of the operation of the phase locked loop (PLL) (1215) of FIG. 13.

[0368] Referring to the drawing, a phase locked loop (PLL) (1215) outputs a first clock signal (GCLk) based on a reference clock signal (Ref_clk) from the outside.

[0369] Meanwhile, the multiplier (1603) multiplies the first clock signal (GCLk) and P, and the divider (1605) divides the result of the multiplier (1603) by Q.

[0370] The multiplexer (1607) outputs a first clock signal (GCLk) or a second clock signal (GCLk*P / Q) based on the result data of the divider (1605) and the output data of the phase-locked loop (PLL) (1215).

[0371] Figures 18a to 18c are drawings referenced in the description of Figure 17b.

[0372] Fig. 18a illustrates an example of grayscale allocation based on a first clock signal (GCLk) or a second clock signal (GCLk*P / Q).

[0373] Referring to the drawing, when P is 1 and Q is 2, the driving control unit (285) can perform grayscale allocation based on the first clock signal (clk) and the second clock signal (clk / 2).

[0374] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0375] As another example, for the expression of two tones, the driving control unit (285) can apply a second data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the second sub-frame period (SF2).

[0376] Meanwhile, since the frequency of the first clock signal (clk) is twice the frequency of the second clock signal (1 / 2*clk), it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0377] That is, the meaning of 1 tone in SF2 to SF5 in the drawing can correspond to 1*2 tone.

[0378] Figure 18b illustrates an example of grayscale allocation based on the first clock signal (GCLk) or the second clock signal (GCLk*P / Q).

[0379] Referring to the drawing, when P is 1 and Q is 4, the driving control unit (285) can perform grayscale allocation based on the first clock signal (clk) and the second clock signal (clk / 4).

[0380] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0381] As another example, for the expression of two tones, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0382] Meanwhile, it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0383] As another example, for the expression of 5 gradations, the driving control unit (285) may apply a first data signal based on a first clock signal (clk) to the light-emitting diode during a first sub-frame period (SF1), and apply a third data signal based on a second clock signal (1 / 4*clk) to the light-emitting diode during a second sub-frame period (SF2).

[0384] Meanwhile, since the frequency of the first clock signal (clk) is four times the frequency of the second clock signal (1 / 4*clk), it is preferable that the pulse width of the third data signal be four times the pulse width of the first data signal.

[0385] That is, the meaning of 1 tone in SF2 to SF5 in the drawing can correspond to 1*4 tone.

[0386] Figure 18c illustrates an example of grayscale allocation based on the first clock signal (GCLk) or the second clock signal (GCLk*P / Q).

[0387] Referring to the drawing, when P is 2 and Q is 4, the driving control unit (285) can perform grayscale allocation based on the first clock signal (clk) and the second clock signal (clk / 2).

[0388] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0389] As another example, for the expression of two tones, the driving control unit (285) can apply a second data signal based on a second clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0390] Meanwhile, it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0391] As another example, for the expression of 4 gradations, the driving control unit (285) can apply a third data signal based on the second clock signal (clk / 2) to the light-emitting diode during the second sub-frame period (SF2) and the fourth sub-frame period (SF4).

[0392] Meanwhile, since the frequency of the first clock signal (clk) is twice the frequency of the second clock signal (1 / 2*clk), it is preferable that the pulse width of the third data signal be twice the pulse width of the first data signal.

[0393] That is, the meaning of 1 tone in SF2 to SF5 in the drawing can correspond to 1*2 tone.

[0394] Figure 19 illustrates another example of an internal block diagram of the data processor of Figure 13.

[0395] Referring to the drawing, the internal configuration of the timing generator (1220) may be the same as the internal configuration of the timing generator (1220) of FIG. 15.

[0396] Meanwhile, the data processor (1230c) may be equipped with a quotient operator (1615) that performs a quotient operation on data (1612) obtained by dividing input image data (1611) by Q and then multiplying it by P, a remainder operator (1617) that performs a remainder operation, a lockup table (1232), a comparator (1234) that compares data from the lockup table with data from the remainder operator (1617), a summer (1236) that adds the result data of the comparator (1234) and the result data of the quotient operator (1615), and a register (1229) that stores the output of the summer (1236).

[0397] Meanwhile, the data processor (1230c) may further include a second quotient operator (1615b) that performs a quotient operation, a second remainder operator (1617b) that performs a remainder operation, a second lockup table (1232b), a second comparator (1234b) that compares data from the second lockup table with data from the second remainder operator (1617b), a second adder (1236b) that adds the result data of the second comparator (1234b) and the result data of the second quotient operator (1615b), and a register (1229b) that stores the output of the second adder (1236b).

[0398] Figures 20a to 20d are drawings referred to in the description of Figure 19.

[0399] Figure 20a illustrates that the number of sub-frames corresponding to the first clock signal is plural.

[0400] Referring to the drawing, the driving control unit (285) can control the number of sub-frame periods (SF1 to SF6) to be plural, operating based on the first clock signal.

[0401] For example, during the first sub-frame period (SF1) and the fourth sub-frame period (SF4) among the plurality of sub-frame periods (SF1 to SF6), it may operate based on the first clock signal, and during the remaining sub-frame periods (SF2, SF3, SF4, SF5) among the plurality of sub-frame periods (SF1 to SF6), it may operate based on the second clock signal. Accordingly, it is possible to reduce power consumption while maintaining grayscale expressiveness.

[0402] FIG. 20b illustrates operation based on a first clock signal in multiple sub-frame periods among scan lines.

[0403] Referring to the drawing, the driving control unit (285) can apply a first scan signal based on a first clock signal in the first sub-frame period (SF1) and the third sub-frame period (SF3) in the first scan line (Scan0), and can apply a second scan signal based on a second clock signal in the second sub-frame period (SF2) and the fourth sub-frame period (SF4). Accordingly, it is possible to reduce power consumption while maintaining grayscale expressiveness.

[0404] Figure 21 illustrates another example of an internal block diagram of the data processor of Figure 13.

[0405] Referring to the drawing, the internal configuration of the timing generator (1220) may be the same as the internal configuration of the timing generator (1220) of FIG. 15.

[0406] Meanwhile, the data processor (1230d) may be equipped with a quotient operator (1615) that performs a quotient operation on data (1612) obtained by dividing input image data (1611) by Q and then multiplying it by P, a remainder operator (1617) that performs a remainder operation, a lockup table (1232), a comparator (1234) that compares data from the lockup table with data from the remainder operator (1617), a summer (1236) that adds the result data of the comparator (1234) and the result data of the quotient operator (1615), and a register (1229) that stores the output of the summer (1236).

[0407] Meanwhile, the data processor (1230d) may further include an operator (2005) that performs a multiplication or division operation based on data from a register (1229), and an adder (2003) that adds the remaining data (1613) after dividing the data of the operator (2005) and the image data (1611) by Q.

[0408] Figure 22 illustrates another example of an internal block diagram of the data processor of Figure 13.

[0409] Referring to the drawing, the internal configuration of the timing generator (1220) may be the same as the internal configuration of the timing generator (1220) of FIG. 15.

[0410] Meanwhile, the data processor (1230e) may include a lockup table (1232), a comparator (1234) that compares data from the lockup table with an LSB bit among data bits (1231), an adder (1236) that adds the result data of the comparator (1234) and an MSB bit among data bits (1231), and a register (2103) that stores the output of the adder (1236), and a first quotient operator (2105) and a second quotient operator (2107) that perform quotient operations based on the output data of the register (2103).

[0411] Figure 23 is a drawing referenced in the description of Figure 22.

[0412] Referring to the drawing, the driving control unit (285) can perform grayscale allocation based on the first clock signal (clk) and the second clock signal (clk / 2).

[0413] Meanwhile, the driving control unit (285) can allocate 1 to 13 grayscale levels using four sub-frame periods (SF1 to SF4).

[0414] In particular, the driving control unit (285) can perform grayscale allocation based on the first clock signal (clk) during the first sub-frame period (SF1) and the third sub-frame period (SF3) among the four sub-frames (SF1 to SF4), and can perform grayscale allocation based on the second clock signal (clk / 2) during the second sub-frame period (SF2) and the fourth sub-frame period (SF4).

[0415] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0416] As another example, for the expression of two tones, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1) and the third sub-frame period (SF3).

[0417] As another example, for the expression of three gradations, the driving control unit (285) may apply a second data signal based on a second clock signal (1 / 2*clk) to the light-emitting diode during the second sub-frame period (SF2), and may apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the third sub-frame period (SF3).

[0418] Meanwhile, it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0419] FIG. 24 is a drawing showing the operation of a video display device according to another embodiment of the present disclosure.

[0420] Referring to the drawing, the driving control unit (285) determines whether the first set gradation is among the plurality of gradations (S2310), and if so, turns on or off the plurality of light-emitting diodes based on the first clock signal during some sub-frame periods among the plurality of sub-frame periods (SF1 to SF5) (S2315).

[0421] Next, in step 2310 (S2310), the driving control unit (285) determines whether it is a second set gradation if it is not a first set gradation among the plurality of gradations (S2320), and if so, turns on or off a plurality of light-emitting diodes based on a second clock signal that is different from the first clock signal during some sub-frame periods among the plurality of sub-frame periods (SF1 to SF5) (S2325).

[0422] For example, the driving control unit (285) can turn on or off the plurality of light-emitting diodes based on a first clock signal during a first sub-frame period (SF1) among the plurality of sub-frame periods (SF1 to SF5) when the first set gradation is among the plurality of gradations, and can turn on or off the plurality of light-emitting diodes based on a second clock signal during a first sub-frame period (SF1) among the plurality of sub-frame periods (SF1 to SF5) when the second set gradation is among the plurality of gradations.

[0423] Accordingly, power consumption can be reduced while maintaining gradation expressivity. In particular, power consumption can be reduced while maintaining bit depth.

[0424] Figures 25a and 25b are drawings referred to in the description of Figure 24.

[0425] Fig. 25a is an example of gradation allocation according to Fig. 24.

[0426] Referring to the drawing, the driving control unit (285) can perform grayscale allocation based on the first clock signal (clk) and the second clock signal (clk / 2).

[0427] Meanwhile, the driving control unit (285) can allocate 1 to 26 grayscale levels using four sub-frame periods (SF1 to SF4).

[0428] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0429] As another example, for the expression of two tones, the driving control unit (285) can apply a second data signal based on a second clock signal (clk / 2) to the light-emitting diode during the first sub-frame period (SF1).

[0430] Meanwhile, it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0431] As another example, for the expression of three grayscale levels, the driving control unit (285) may apply a second data signal based on a second clock signal (clk / 2) to the light-emitting diode during the first sub-frame period (SF1), and may apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the third sub-frame period (SF3). Accordingly, power consumption may be reduced while maintaining grayscale expressiveness.

[0432] Fig. 25b is another example of tone allocation according to Fig. 24.

[0433] Referring to the drawing, the driving control unit (285) can perform grayscale allocation based on the first clock signal (clk) and the second clock signal (clk / 4).

[0434] Meanwhile, the driving control unit (285) can allocate 1 to 26 grayscale levels using four sub-frame periods (SF1 to SF4).

[0435] For example, to express 1 tone, the driving control unit (285) can apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0436] As another example, for the expression of two tones, the driving control unit (285) can apply a second data signal based on the first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0437] Meanwhile, it is preferable that the pulse width of the second data signal be twice the pulse width of the first data signal.

[0438] As another example, for the expression of three tones, the driving control unit (285) can apply a third data signal based on the first clock signal (clk) to the light-emitting diode during the first sub-frame period (SF1).

[0439] Meanwhile, it is preferable that the pulse width of the third data signal be twice the pulse width of the first data signal.

[0440] As another example, for the expression of 4 gradations, the driving control unit (285) can apply a fourth data signal based on a second clock signal (clk / 4) to the light-emitting diode during the first sub-frame period (SF1).

[0441] Meanwhile, it is preferable that the pulse width of the fourth data signal be four times the pulse width of the first data signal.

[0442] As another example, for the expression of 5 grayscale levels, the driving control unit (285) may apply a fourth data signal based on a second clock signal (clk / 4) to the light-emitting diode during the first sub-frame period (SF1), and may apply a first data signal based on a first clock signal (clk) to the light-emitting diode during the third sub-frame period (SF3). Accordingly, power consumption may be reduced while maintaining grayscale expressiveness.

[0443] Although the preferred embodiments of the present disclosure have been illustrated and described above, the present disclosure is not limited to the specific embodiments described above, and various modifications may be made by a person skilled in the art to which the present invention pertains without departing from the gist of the present disclosure as claimed in the claims, and such modifications should not be understood individually from the technical idea or prospect of the present disclosure.

Claims

Multiple light emitting diodes; A driving control unit that outputs a scan signal for each of a plurality of sub-frame periods to the plurality of light-emitting diodes and outputs a data signal for image display; The above driving control unit, During some sub-frame periods among the plurality of sub-frame periods, the plurality of light-emitting diodes are turned on or off based on a first clock signal, An image display device that turns on or off the plurality of light-emitting diodes based on a second clock signal that is different from the first clock signal during another sub-frame period among the plurality of sub-frame periods. In the first paragraph, The above driving control unit, A video display device that controls the frequency of the second clock signal to be lower than the frequency of the first clock signal. In the first paragraph, The above driving control unit, During a first sub-frame period among the plurality of sub-frame periods, the plurality of light-emitting diodes are turned on or off based on the first clock signal, An image display device that turns on or off the plurality of light-emitting diodes based on the second clock signal during a sub-frame period after the first sub-frame period among the plurality of sub-frame periods. In the first paragraph, The above driving control unit, During the last sub-frame period among the plurality of sub-frame periods, turning on or off the plurality of light-emitting diodes based on the first clock signal, An image display device that turns on or off the plurality of light-emitting diodes based on the second clock signal during a sub-frame period prior to the last sub-frame period among the plurality of sub-frame periods. In the first paragraph, The above driving control unit, During the first sub-frame period and the last sub-frame period among the plurality of sub-frame periods, the plurality of light-emitting diodes are turned on or off based on the second clock signal, An image display device that turns on or off the plurality of light-emitting diodes based on the first clock signal during a portion of the sub-frame period between the first sub-frame period and the last sub-frame period. In the first paragraph, The above driving control unit, A video display device in which the position of the sub-frame period operating at the frequency of the first clock signal is controlled to vary from frame to frame. In paragraph 6, The above driving control unit, An image display device that outputs a first scan signal corresponding to the first clock signal to the plurality of light-emitting diodes during the above-described sub-frame period. In the first paragraph, The above driving control unit, During some sub-frame periods among the plurality of sub-frame periods, a first scan signal corresponding to the first clock signal is output to the plurality of light-emitting diodes, An image display device that outputs a second scan signal corresponding to the second clock signal to the plurality of light-emitting diodes during some other sub-frame periods among the plurality of sub-frame periods. In the first paragraph, The above driving control unit, A video display device that controls a plurality of sub-frame periods to operate based on the first clock signal among the plurality of sub-frame periods. In paragraph 9, The above driving control unit, A video display device that controls the positions of a plurality of sub-frame periods that operate based on the first clock signal so that they vary from frame to frame. In the first paragraph, The above driving control unit, A first counter that performs counting based on the first clock signal; A second counter that performs counting based on the second clock signal; An image display device comprising a multiplexer that outputs a first scan signal corresponding to the first clock signal or a second scan signal corresponding to the second clock signal based on the first counter or the second counter. Multiple light emitting diodes; A driving control unit that outputs a scan signal for each of a plurality of sub-frame periods to the plurality of light-emitting diodes and outputs a data signal for expressing a plurality of gray levels; The above driving control unit, When the first set grayscale is among the plurality of grayscales, during some sub-frame periods among the plurality of sub-frame periods, the plurality of light-emitting diodes are turned on or off based on the first clock signal, An image display device that turns on or off the plurality of light-emitting diodes based on a second clock signal that is different from the first clock signal during some of the sub-frame periods among the plurality of sub-frame periods, when the second set gradation is among the plurality of gradations. In Article 12, The above driving control unit, A video display device that controls the frequency of the second clock signal to be lower than the frequency of the first clock signal. In Article 12, The above driving control unit, An image display device that turns on or off the plurality of light-emitting diodes based on the second clock signal during some other sub-frame periods among the plurality of sub-frame periods when the plurality of gradations are the first set gradations. In Article 12, The above driving control unit, An image display device that turns on or off the plurality of light-emitting diodes based on the first clock signal during some other sub-frame periods among the plurality of sub-frame periods when the second set gradation is among the plurality of gradations. In Article 12, The above driving control unit, Outputting a first scan signal corresponding to the first clock signal to the plurality of light-emitting diodes, An image display device that outputs a second scan signal corresponding to the second clock signal to the plurality of light-emitting diodes. Includes multiple video display devices; The above video display device, A video wall comprising a video display device according to any one of claims 1 to 16.

Images