Micro light-emitting diode and manufacturing method therefor

Abstract

A micro light-emitting diode is disclosed. The micro light-emitting diode comprises: a semiconductor unit including a n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer between the n-type and p-type semiconductor layers; a first chip electrode electrically connected to the n-type semiconductor layer; a second chip electrode electrically connected to the p-type semiconductor layer; a lens which is provided on a light-emitting surface of the semiconductor unit and focuses light emitted from the light-emitting surface of the semiconductor unit; and a reflective layer which is provided on a side surface of the semiconductor unit and reflects light emitted from the light-emitting layer toward the light-emitting surface.

Description

Micro light-emitting diode and method for manufacturing the same

[0001] The present disclosure relates to a micro light emitting diode and a method for manufacturing the same.

[0002] Recently, light-emitting diode (LED) technology based on compound semiconductors such as GaN, GaAs, and GaP has been developing rapidly. Along with this technological advancement in LEDs, interest in LED display devices utilizing panel configuration technology that directly mounts (transfers) LEDs that emit light in the R (red), G (green), and B (blue) wavelength bands onto a circuit board has grown. In particular, miniaturization of LEDs is essential for outputting high-definition images from LED display devices, and thus, significant development infrastructure is being invested to perfect micro light-emitting diodes with an ultra-small size of 100 micrometers or less.

[0003] A micro light emitting diode according to one or more embodiments of the present disclosure may include a semiconductor portion including an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer between the n-type semiconductor layer and the p-type semiconductor layer; a first chip electrode electrically connected to the n-type semiconductor layer; a second chip electrode electrically connected to the p-type semiconductor layer; a lens provided on a light emitting surface of the semiconductor portion and focusing light emitted from the light emitting surface of the semiconductor portion; and a reflective layer provided on a side surface of the semiconductor portion and reflecting light emitted from the light emitting layer toward the light emitting surface.

[0004] The above lens may be configured such that the central portion of the lens is convex.

[0005] The size of the above semiconductor portion may be 30㎛ or less.

[0006] The thickness of the semiconductor portion may be 8 µm to 10 µm.

[0007] The thickness of the above lens may be 1㎛ to 4㎛.

[0008] The radius of curvature of the above lens may be 30 μm to 100 μm.

[0009] The above lens may include one of SiO2, Al2O3, TiO2, and ITO (indium tin oxide).

[0010] The side surface of the semiconductor portion may be configured to be inclined so as to form an acute angle with the light-emitting surface of the semiconductor portion.

[0011] The above reflective layer may be configured to extend to the lower surface of the semiconductor portion opposite the light-emitting surface of the semiconductor portion.

[0012] The above reflective layer may be configured to be concave from the upper part to the lower part of the semiconductor portion.

[0013] The above reflective layer may include a distributed bragg reflector (DBR).

[0014] A method for manufacturing a micro light emitting diode according to one or more embodiments of the present disclosure may include: forming a semiconductor portion including an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer between the n-type semiconductor layer and the p-type semiconductor layer on a substrate; forming a reflective layer on a side surface and a lower surface of the semiconductor portion; forming a first chip electrode in contact with the n-type semiconductor and a second chip electrode in contact with the p-type semiconductor on a lower surface of the semiconductor portion; separating the substrate from a light emitting surface included in the n-type semiconductor layer of the semiconductor portion; and forming a convex lens on the light emitting surface of the semiconductor portion.

[0015] FIG. 1 is a front view illustrating a display module according to one or more embodiments of the present disclosure.

[0016] FIG. 2 is an enlarged view of a portion of a display module according to one or more embodiments of the present disclosure.

[0017] Figure 3 is a cross-sectional view taken along line AA shown in Figure 2.

[0018] FIG. 4 is a cross-sectional view illustrating a micro light emitting diode according to one or more embodiments of the present disclosure.

[0019] FIG. 5 is a flowchart illustrating a manufacturing process of a micro light-emitting diode according to one or more embodiments of the present disclosure.

[0020] FIGS. 6 to 21 are drawings illustrating a manufacturing process of a micro light emitting diode according to one or more embodiments of the present disclosure.

[0021] FIG. 22 is a cross-sectional view illustrating a micro light emitting diode according to one or more embodiments of the present disclosure.

[0022] FIG. 23 is a cross-sectional view illustrating a micro light emitting diode according to one or more embodiments of the present disclosure.

[0023] FIG. 24 is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0024] One or more embodiments according to the present disclosure may have various modifications and multiple embodiments, and specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the scope to specific embodiments, but should be understood to include various modifications, equivalents, and / or alternatives of one or more embodiments according to the present disclosure. In connection with the description of the drawings, similar reference numerals may be used for similar components.

[0025] In describing the present disclosure, detailed descriptions of related known functions or configurations will be omitted if they are deemed to unnecessarily obscure the gist of the present disclosure. Furthermore, one or more embodiments according to the present disclosure may be modified in various different forms, and the scope of the technical concepts of the present disclosure is not limited to the following embodiments. Rather, these embodiments are provided to further faithfully and completely convey the technical concepts of the present disclosure to those skilled in the art.

[0026] The terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the scope of the rights. Singular expressions include plural expressions unless the context clearly dictates otherwise.

[0027] In this disclosure, expressions such as “has,” “can have,” “includes,” or “may include” indicate the presence of a corresponding feature (e.g., a component such as a number, function, operation, or part), and do not exclude the presence of additional features.

[0028] In this disclosure, expressions such as “A or B,” “at least one of A and / or B,” or “one or more of A or / and B” can include all possible combinations of the listed items. For example, “A or B,” “at least one of A and B,” or “at least one of A or B” can all refer to cases where ① at least one A is included, ② at least one B is included, or ③ both at least one A and at least one B are included.

[0029] The expressions “first,” “second,” “first,” or “second,” etc., used in this disclosure can describe various components, regardless of order and / or importance, and are only used to distinguish one component from another, but do not limit the components.

[0030] The expression "configured to" as used in the present disclosure may be used interchangeably with, for example, "suitable for," "having the capacity to," "designed to," "adapted to," "made to," or "capable of." The term "configured to" may not necessarily mean only "specifically designed to" in terms of hardware.

[0031] In the present disclosure, a "module" or "part" performs at least one function or operation and may be implemented in hardware or software, or a combination of hardware and software. Furthermore, multiple "modules" or multiple "parts" may be integrated into at least one module and implemented as at least one processor, excluding any "modules" or "parts" that require specific hardware implementation.

[0032] Meanwhile, the various elements and areas in the drawings are schematically drawn. Therefore, the technical concepts of the present disclosure are not limited by the relative sizes or spacings drawn in the attached drawings.

[0033] Hereinafter, one or more embodiments according to the present disclosure will be described in detail with reference to the attached drawings so that a person having ordinary skill in the art to which the present disclosure pertains can easily practice the present disclosure.

[0034] FIG. 1 is a front view showing a display module (30) according to one or more embodiments of the present disclosure.

[0035] Referring to FIG. 1, the display module (30) may include a substrate (50) and a plurality of micro light emitting diodes (61, 62, 63) arranged on the substrate (50). The plurality of micro light emitting diodes (61, 62, 63) may be arranged in a grid pattern at a constant pitch on the upper surface of the substrate (50). The size (width X length X height) of each of the plurality of micro light emitting diodes (61, 62, 63) may be, for example, 30 ㎛ X 30 ㎛ X 10 ㎛ or less. Here, the width X length may be the area of ​​the light emitting surface (61c, 62c, 63c) of each of the plurality of micro light emitting diodes (61, 62, 63).

[0036] In the present disclosure, the horizontal and vertical lengths of the plurality of micro light emitting diodes (61, 62, 63) are exemplified as being the same, but are not limited thereto. The horizontal and vertical lengths of the plurality of micro light emitting diodes (61, 62, 63) may not be the same. For example, the horizontal X vertical length of the plurality of micro light emitting diodes (61, 62, 63) may be 30 μm X 10 μm or 10 μm X 30 μm.

[0037] In addition, when the horizontal and vertical lengths of a plurality of micro light-emitting diodes (61, 62, 63) are 30㎛ X 30㎛ or less, it is difficult to form the height of a plurality of micro light-emitting diodes (61, 62, 63) to exceed 10㎛ due to technical limitations.

[0038] FIG. 2 is an enlarged view illustrating a portion of a display module according to one or more embodiments of the present disclosure. FIG. 3 is a cross-sectional view taken along line AA shown in FIG. 2.

[0039] Referring to FIGS. 2 and 3, the plurality of micro light emitting diodes (61, 62, 63) may include a first micro light emitting diode (61) that emits red light, a second micro light emitting diode (61) that emits green light, and a third micro light emitting diode (61) that emits blue light. In this case, the first micro light emitting diode (61), the second micro light emitting diode (62), and the third micro light emitting diode (63) may form one pixel. Each of the plurality of micro light emitting diodes (61, 62, 63) may be referred to as a sub-pixel. The substrate (50) may have a plurality of pixel areas provided in a roughly grid shape on the front surface of the substrate (50). One pixel may be provided in each pixel area.

[0040] Thin film transistor circuits (TFT circuits) may be provided on the front surface of the substrate (50). A power supply circuit for supplying power to the TFT circuit, a data drive driver, a gate drive driver, and a timing controller for controlling each drive driver may be arranged on the back surface of the substrate (50).

[0041] The TFT circuit may include a plurality of TFTs for driving the first, second, and third micro light emitting diodes (81, 82, 83). The TFT circuit may be formed on the front surface of the substrate (50), but is not limited thereto, and may be manufactured in the form of a separate film and laminated on the front surface of the substrate (50). A plurality of substrate pads (51a, 51b, 52a, 52b, 53a, 53b) arranged in the TFT circuit may be electrically connected to the TFTs included in the TFT circuit. The TFT is not limited to a specific structure or type. For example, the TFT may be implemented as an LTPS TFT (Low-temperature polycrystalline silicon TFT), an oxide TFT, a Si TFT (poly silicon, a-silicon), an organic TFT, a graphene TFT, etc. The TFT circuit may include only a P-type (or N-type) MOSFET (metal oxide semiconductor field effect transistor) in a CMOS (complementary metal oxide semiconductor) process using a Si wafer.

[0042] The first chip electrodes (61a, 62a, 63a) and the second chip electrodes (61b, 62b, 63b) of the first, second, and third micro light emitting diodes (61, 62, 63) can be electrically and physically connected to the first substrate pads (51a, 52a, 53a) and the second substrate pads (52b, 53a, 53b) of the substrate (50) by a conductive adhesive member (55). For example, the conductive adhesive member (55) can be an anisotropic conductive film or an anisotropic conductive paste.

[0043] Each of the first, second, and third micro light emitting diodes (61, 62, 63) may include a light emitting surface (61c, 62c, 63c) from which light is emitted. The first, second, and third micro light emitting diodes (61, 62, 63) may be formed in a flip chip form in which a first chip electrode (61a, 62a, 63a) and a second chip electrode (61b, 62b, 63b) are provided on opposite sides of the light emitting surfaces (61c, 62c, 63c).

[0044] The first, second, and third micro light-emitting diodes (61, 62, 63) differ in that they emit light of different colors, but their structures, including an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer, are substantially the same. Hereinafter, the structure of the first micro light-emitting diode (61) will be described in detail. For convenience of explanation, the 'first micro light-emitting diode (61)' will be referred to as a 'micro light-emitting diode (61)'.

[0045] FIG. 4 is a cross-sectional view illustrating a micro light emitting diode according to one or more embodiments of the present disclosure.

[0046] Referring to FIG. 4, the micro light-emitting diode (61) may include a semiconductor portion (S), a reflective layer (61-4), a lens (61-5), and a first chip electrode (61a) and a second chip electrode (61b).

[0047] The semiconductor portion (S) may include an n-type semiconductor layer (61-1), a p-type semiconductor layer (61-2), and a light-emitting layer (61-3). Each of the n-type semiconductor layer (61-1) and the p-type semiconductor layer (61-2) may be implemented with a compound semiconductor of group III-V, group II-VI, etc. For example, each of the n-type semiconductor layer (61-1) and the p-type semiconductor layer (61-2) may be implemented with a nitride semiconductor. Each of the n-type semiconductor layer (61-1) and the p-type semiconductor layer (61-2) may be an n-GaN semiconductor layer and a p-GaN semiconductor layer, respectively. However, each of the n-type semiconductor layer (61-1) and the p-type semiconductor layer (61-2) is not limited thereto, and may be formed of various materials according to various characteristics required for the micro light-emitting diode.

[0048] The n-type semiconductor layer (61-1) is a semiconductor in which free electrons are used as carriers for transferring charges, and can be made by doping with an n-type dopant such as Si, Ge, Sn, or Te. The p-type semiconductor layer (61-2) is a semiconductor in which holes are used as carriers for transferring charges, and can be made by doping with a p-type dopant such as Mg, Zn, Ca, or Ba.

[0049] The n-type semiconductor layer (61-1) may include a light-emitting surface (61c) on the opposite side of the light-emitting surface (61c) that serves as a passage through which light generated from the light-emitting layer (61-3) is emitted to the outside of the micro light-emitting diode (61). The light-emitting surface (61c) may be approximately flat and formed approximately parallel to the light-emitting layer (61-3). In the present disclosure, the terms “upper surface of the semiconductor portion (S),” “light-emitting surface of the semiconductor portion (S),” and “light-emitting surface of the micro light-emitting diode (61)” all refer to the same light-emitting surface (61c).

[0050] The n-type semiconductor layer (61-1) can be electrically connected to the first chip electrode (61a). The first chip electrode (61a) can be made of any one of Al, Ti, Cr, Ni, Pd, Ag, Ge, and Au, or an alloy thereof. Electrically conductive oxides such as ITO (indium tin oxide) and ZnO can be used for ohmic contacts between the first chip electrode (61a) and the n-type semiconductor layer (61-1).

[0051] The p-type semiconductor layer (61-2) can be electrically connected to the second chip electrode (61b). The second chip electrode (61b) can be made of any one of Al, Ti, Cr, Ni, Pd, Ag, Ge, and Au, or an alloy thereof. Electrically conductive oxides such as ITO (indium tin oxide) and ZnO can be used for ohmic contacts between the second chip electrode (61b) and the p-type semiconductor layer (61-2).

[0052] The n-type semiconductor layer (61-1), the p-type semiconductor layer (61-2), and the light-emitting layer (61-3) may be composed of various semiconductors having a band gap corresponding to a specific region within the spectrum. For example, the first micro light-emitting diode (61) having an optical wavelength of 600-750 nm (red) may include one or more layers based on an AlInGaP-based semiconductor. The second micro light-emitting diode (62) and the third micro light-emitting diode (63), each having an optical wavelength of 500-570 nm (green) and an optical wavelength of 450-490 nm (blue), may include one or more layers based on an AlInGaN-based semiconductor.

[0053] The light-emitting layer (61-3) may be positioned between the n-type semiconductor layer (61-1) and the p-type semiconductor layer (61-2). The light-emitting layer (61-3) is a layer where electrons, which are carriers of the n-type semiconductor layer (61-1), and holes, which are carriers of the p-type semiconductor layer (61-2), meet. When electrons and holes meet in the light-emitting layer (61-3), a potential barrier is formed as the electrons and holes recombine. In this case, when the electrons and holes transition to a lower energy level by overcoming the potential barrier according to the voltage applied to the micro light-emitting diode (61), light of a corresponding wavelength (e.g., red light) is emitted.

[0054] The light-emitting layer (61-3) may include a multi-quantum well structure, but the present disclosure is not limited thereto. For example, the light-emitting layer (61-3) may include one of a single quantum well structure or a quantum dot structure. When the light-emitting layer (61-3) includes a multi-quantum well structure, the well layer / barrier layer of the light-emitting layer (61-3) may be formed in a structure such as InGaN / GaN, InGaN / InGaN, or GaAs / AlGaAs, but is not limited thereto. The number of quantum wells included in the light-emitting layer (61-3) is also not limited to a specific number.

[0055] The reflective layer (61-4) may include a first reflective layer (61-4a) covering the side surface of the semiconductor portion (S) and a second reflective layer (61-4b) covering the lower surface of the semiconductor portion (S). For example, the first reflective layer (61-4a) and the second reflective layer (61-4b) may be formed collectively on the side surface and the lower surface of the semiconductor portion (S) by a deposition process.

[0056] The side surface of the semiconductor portion (S) may be configured to be inclined from the upper surface (e.g., the light-emitting surface (61c)) of the semiconductor portion (S) toward the lower surface of the semiconductor portion (S). For example, the side surface of the semiconductor portion (S) may form an acute angle with the upper surface of the semiconductor portion (S). Since the reflective layer (61-4) covers the side surface and the lower surface of the semiconductor portion (S), it may form a concave shape below the light-emitting layer (61-3). In this case, the reflective layer (61-4) may have a three-dimensional shape that gradually narrows from the upper surface to the lower surface of the semiconductor portion (S).

[0057] The reflective layer (61-4) can reflect light emitted from the light-emitting layer (61-3) of the semiconductor portion (S). In this case, the reflective layer (61-4) reflects the light emitted from the light-emitting layer (61-3) of the semiconductor portion (S) so that it is focused onto the light-emitting surface (61-3) based on its concave shape.

[0058] The reflection layer (61-4) may be composed of a distributed Bragg reflector (DBR) that has insulating properties and is capable of reflecting light. The DBR may be composed of Bragg reflectors in which two thin films with a large difference in refractive index (e.g., a thin film composed of TiO2, a high-refractive index dielectric, and a thin film composed of SiO2, a low-refractive index dielectric) are alternately and repeatedly deposited to a predetermined thickness. The material forming the thin film of the DBR may also be SiN.

[0059] The reflective layer (61-4) may include a third reflective layer (61-4c) extending to the second reflective layer (61-4b). The third reflective layer (61-4c) may electrically isolate the second contact electrode (61b) from the p-type semiconductor layer (61-2) and the light-emitting layer (61-3).

[0060] A lens (61-5) may be provided on the light-emitting surface (61c). The lens (61-5) may protrude convexly toward the upper side of the light-emitting surface (61c). The lens (61-5) may focus light emitted from the light-emitting surface (61c) toward the outer side of the micro light-emitting diode (61) toward approximately the center of the light-emitting surface (61c), thereby improving the light efficiency of the micro light-emitting diode (61).

[0061] The lens (61-5) may be made of a transparent material. For example, the lens (61-5) may be made of SiO2, Al2O3, TiO2, or ITO (indium tin oxide). The lens (61-5) may be formed on the light-emitting surface (61c) through photolithography.

[0062] Referring to FIG. 4, the thickness (t2) of the lens (61-5) may be smaller than the thickness (t2) of the semiconductor portion (S). The thickness (t1) of the semiconductor portion (S) may be about 8 µm to 10 µm. The thickness of the lens (61-5) may be about 1 µm to 4 µm. For example, if the thickness (t1) of the semiconductor portion (S) is about 8.5 µm, the thickness (t2) of the lens (61-5) may be about 4 µm or less. The lens (61-5) is formed by depositing a transparent material on the light-emitting surface (61c). In this case, it is difficult due to technical limitations to deposit the transparent material in excess of about 4 µm on the light-emitting surface (61c) (e.g., the area of ​​the light-emitting surface is 30 µm X 30 µm or less in width X length).

[0063] The radius of curvature of the lens (61-5) may be inversely proportional to the thickness (t2) of the lens (61-5). The radius of curvature of the lens may be about 5 µm to 100 µm. For example, when the lower length of the lens (61-5) (e.g., the length along the X-axis in FIG. 4) is 30 µm, and when the thickness (t2) of the lens (61-5) is about 4 µm, about 2.3 µm, or about 1.1314 µm, the radius of curvature of the lens (61-5) may be about 30 µm, about 50 µm, or about 100 µm for each thickness (s2), respectively.

[0064] Hereinafter, the manufacturing process of a micro light emitting diode (61) will be described in detail with reference to the drawings. FIG. 5 is a flowchart illustrating a manufacturing process of a micro light emitting diode according to one or more embodiments of the present disclosure. FIGS. 6 to 21 are drawings illustrating a manufacturing process of a micro light emitting diode according to one or more embodiments of the present disclosure.

[0065] Referring to Fig. 6, an epitaxial layer (60) is formed on a substrate (1) through an epitaxy process. The substrate (1) may be a sapphire substrate. In order to form a mesa (60b, see Fig. 8) on the epitaxial layer (60), a photoresist is applied on the epitaxial layer (60) to form a first photoresist layer (3).

[0066] Referring to Fig. 7, an opening (3a) is formed in the first photoresist layer (3) through an exposure process using a dry etching process. A portion (60a) of the upper surface of the epitaxial layer (60) can be exposed by the opening (3a) of the first photoresist layer (3).

[0067] Referring to Fig. 8, a mesa (60b) is formed on a portion (60a) of the upper surface of the epitaxial layer (60) through a dry etching process. The first photoresist layer (3) formed on the epitaxial layer (60) is removed.

[0068] Referring to Fig. 9, in order to form a first mask pattern (5a, see Fig. 10) on the epitaxial layer (60), a photoresist is applied on the epitaxial layer (60) to form a second photoresist layer (5). In this case, the mesa (60b) is filled with the photoresist.

[0069] Referring to Fig. 10, the second photoresist layer (5) is exposed to light to form a first mask pattern (5a) so as to have an island shape corresponding to the point where the LED is formed (element 501 of Fig. 5).

[0070] After the exposure process, the first mask pattern (5a) may be contracted by surface tension through a reflow process. In this case, the upper surface of the first mask pattern (5a) may be formed into an approximately hemispherical shape depending on the viscosity, thickness, and temperature of the second photoresist layer (5). For example, the viscosity of the second photoresist layer (5) may be 10 mPa·s to 50 mPa·s, and the thickness of the second photoresist layer (5) may be 1 μm to 15 μm. The curing temperature (or bake temperature) may be 100°C to 200°C.

[0071] Forming the upper surface of the first mask pattern (5a) into a hemispherical shape is not limited to the reflow process. For example, after the exposure process, the upper surface of the first mask pattern (5a) can be formed into a hemispherical shape through an anisotropic etching process.

[0072] Alternatively, after the exposure process, a reflow process and an anisotropic etching process may be sequentially performed to form the upper surface of the first mask pattern (5a) into a hemispherical shape.

[0073] Referring to FIG. 11, a dry etching process is performed to form the shape of a semiconductor portion (S) by removing a portion of the epitaxial layer (60) not covered by the first mask pattern (5a). In this case, the dry etching process is performed as an anisotropic etching process to form the side surface of the semiconductor portion (S) at an angle (component 502 of FIG. 5).

[0074] The anisotropic etching process may be composed of a primary etching process and a secondary etching process. For example, the primary etching process may etch the first mask pattern (5a) and the epitaxial layer (60) at different etch rates. For example, the etching rate of the epitaxial layer (60) may be set higher than the etching rate of the first mask pattern (5a). Accordingly, the etching of the first mask pattern (5a) may be minimized, thereby substantially maintaining the shape. Alternatively, the epitaxial layer (60) may be formed with an edge surface (60-1) having directionality, as shown in FIG. 12.

[0075] The secondary etching process is a process of forming the upper region of the epitaxial layer (60) that continues to the edge surface (60-1) of the epitaxial layer (60) to have a gentle slope. In this case, the etching rate of the first mask pattern (5a) can be set higher than the etching rate of the epitaxial layer (60).

[0076] Referring to Fig. 13, the epitaxial layer (60) can be formed as a semiconductor portion (S) with inclined side surfaces through an anisotropic etching process. The semiconductor portion (S) can include an n-type semiconductor layer (61-1), a p-type semiconductor layer (61-2), and a light-emitting layer (61-3) (component 503 of Fig. 5).

[0077] Referring to Fig. 14, a reflective layer (61-4), a first chip electrode (61a), and a second chip electrode (61b) are formed on a semiconductor portion (S) through a FAB process. For example, a dielectric material is deposited on the side and bottom surfaces of the semiconductor portion (S) to form a reflective layer (61-4) (component 504 of Fig. 5).

[0078] Meanwhile, before forming a reflective layer (61-4) on the semiconductor portion (S), a contact electrode may be formed on the lower surface of the semiconductor portion (S) corresponding to the second chip electrode (61b) to increase the contact area between the p-type semiconductor layer (61-2) and the second chip electrode (61b). The contact electrode may be made of ITO.

[0079] A conductive material is deposited on the reflective layer (61-4) corresponding to the lower surface of the semiconductor portion (S) to form a first chip electrode (61a) in contact with the n-type semiconductor layer (61-1) and a second chip electrode (61b) in contact with the p-type semiconductor layer (61-2) (component 505 in Fig. 5). The first chip electrode (61a) is isolated from the p-type semiconductor layer (61-2) and the light-emitting layer (61-3) by the reflective layer (61-4).

[0080] Referring to Fig. 15, a carrier substrate (6) is attached to the lower portion of the semiconductor portion (S). The carrier substrate (6) may be provided with an adhesive layer (7) on one surface to which the semiconductor portion (S) can be adhered.

[0081] The carrier substrate (6) may be a substrate that serves to transfer the micro light-emitting diode to another carrier substrate or a target substrate (e.g., a substrate (50) including a TFT circuit and included in a display module (10)). In the present disclosure, the carrier substrate (6) may be used as a jig for forming a lens (61-5) on the light-emitting surface (61c).

[0082] Referring to Fig. 16, the substrate (1) is separated from the light-emitting surface (61c) of the semiconductor portion (S) through a laser lift-off (LLO) process (component 506 of Fig. 5).

[0083] Referring to Fig. 17, as a pretreatment process for forming a lens (61-5), a transparent layer (8) is formed using a transparent material (e.g., SiO2, Al2O3, TiO2, or ITO) through a deposition process on the light-emitting surface (61c) of the semiconductor portion (S). The transparent layer (8) can cover a portion of the side surface of the semiconductor portion (S) adjacent to the light-emitting surface (61c) of the semiconductor portion (S), and the adhesive layer (7).

[0084] The thickness of the transparent layer (8) can be formed similarly to the thickness of the lens (61-5) (t2, see Fig. 4). In this case, the thickness of the transparent layer (8) can be smaller than the thickness of the semiconductor portion (S) (t1, see Fig. 4).

[0085] Referring to Fig. 18, in order to form a second mask pattern (9a, see Fig. 18) on the light-emitting surface (61c), a photoresist is applied on the transparent layer (8) to form a third photoresist layer (9).

[0086] Referring to Fig. 19, a second mask pattern (9a) is formed to have an island shape corresponding to the point where the LED is formed by exposing the third photoresist layer (9) (component 507 of Fig. 5).

[0087] The second mask pattern (9a) may undergo a reflow process and / or anisotropic etching process, similar to the first mask pattern (5a).

[0088] For example, after the exposure process, the second mask pattern (9a) may be contracted by surface tension through a reflow process. In this case, the upper surface of the second mask pattern (9a) may be formed into an approximately hemispherical shape depending on the viscosity, thickness, and temperature of the third photoresist layer (9). For example, the viscosity of the third photoresist layer (9) may be 10 mPa·s to 50 mPa·s, and the thickness of the third photoresist layer (9) may be 1 μm to 15 μm. The curing temperature (or bake temperature) may be 100°C to 200°C.

[0089] After the exposure process, the second mask pattern (9a) can be formed into a shape having a predetermined curvature on the upper surface of the second mask pattern (9a) through an anisotropic etching process.

[0090] Alternatively, after the exposure process, a reflow process and anisotropic etching process may be sequentially performed to form a predetermined curvature on the upper surface of the second mask pattern (9a).

[0091] Referring to Fig. 20, a dry etching process is performed to remove a portion of the transparent layer (8) not covered by the second mask pattern (9a) to form a shape of a lens (61-5) convex with a predetermined curvature in the upward direction.

[0092] The dry etching process for forming the lens (61-5) is similar to the anisotropic etching process for forming the semiconductor portion (S).

[0093] For example, the anisotropic etching process for forming a lens (61-5) may be composed of a first etching process and a second etching process. The first etching process may etch the second mask pattern (9a) and the transparent layer (8) at different etch rates. For example, the etching rate of the transparent layer (8) may be set higher than the etching rate of the second mask pattern (9a). Accordingly, the etching of the second mask pattern (9a) may be minimized, so that the shape may be generally maintained. Alternatively, the transparent layer (8) may be formed with an edge surface (8-1) having directionality, as shown in FIG. 21.

[0094] The secondary etching process is a process of forming the upper region of the transparent layer (8) that continues to the edge surface (8-1) of the transparent layer (8) to have a predetermined curvature. In this case, the etching rate of the second mask pattern (9a) can be set higher than the etching rate of the transparent layer (8).

[0095] A method for manufacturing a micro light emitting diode (61) according to one or more embodiments of the present disclosure first forms a semiconductor portion (S), a first chip electrode (61a), and a second chip electrode (61b) of the micro light emitting diode (61), and then does not form a light collection structure, i.e., a reflective layer (61-4) and a lens (61-5), of the micro light emitting diode (61) using a separate process and equipment. That is, since the light collection structure can be formed together in the process of manufacturing the micro light emitting diode (61), manufacturing efficiency can be improved.

[0096] A plurality of micro light emitting diodes arranged on a carrier substrate (6) can be transferred to another carrier substrate through a first transfer process and then transferred to a substrate (50) applied to a display module (30) through a second transfer process.

[0097] FIG. 22 is a cross-sectional view showing a micro light emitting diode (161) according to one or more embodiments of the present disclosure.

[0098] Referring to FIG. 22, the micro light emitting diode (161) is substantially identical in most of its configuration to the micro light emitting diode (61) illustrated in FIG. 4, and differs from the micro light emitting diode (61) in that the side surface of the semiconductor portion (S') is formed without a step.

[0099] The side surface of the semiconductor portion (S'') may be a continuous plane without a step from the upper surface of the semiconductor portion (S') to the lower surface of the semiconductor portion (S'). The first reflective layer (161-4a) of the reflective layer (161-4) may cover the side surface of the semiconductor portion (S') formed as a plane. The second reflective layer (161-4b) of the reflective layer (161-4) may extend to the first reflective layer (161-4a) and cover the lower surface of the semiconductor portion (S').

[0100] In FIG. 22, the unexplained symbol 161-1 is an n-type semiconductor layer, 161-2 is a p-type semiconductor layer, 161-3 is a light-emitting layer, S' is a semiconductor portion, 161a is a first chip electrode, and 161b is a second chip electrode.

[0101] FIG. 23 is a cross-sectional view showing a micro light emitting diode (261) according to one or more embodiments of the present disclosure.

[0102] Referring to FIG. 23, the micro light emitting diode (261) is substantially the same in most of its configuration as the micro light emitting diode (61) illustrated in FIG. 4, and differs from the light emitting surface (61c) of the micro light emitting diode (61) in that the light emitting surface (261c) has a rough structure. The light emitting surface (261c) may have a rough structure through a sputtering process included in the process of forming the micro light emitting diode (261). The light emitting surface (261c) having the rough structure can diffusely reflect light emitted from the light emitting layer (261c). The light diffusely reflected from the light emitting surface (261c) can be focused toward the center of the light emitting surface (261c) by the lens (261-5) and emitted to the outside of the micro light emitting diode (261).

[0103] In FIG. 23, the unexplained symbol 261-1 is an n-type semiconductor layer, 261-2 is a p-type semiconductor layer, S'' is a semiconductor portion, 261-4 is a reflective layer, 261a is a first chip electrode, and 261b is a second chip electrode.

[0104] FIG. 24 is a block diagram illustrating a display device (10) according to one or more embodiments of the present disclosure.

[0105] Referring to FIG. 24, a display device (10) may include a display module (30) and a processor (40). The display module (30) may include a substrate (50) and a display driver integrated circuit (IC) (70) for controlling the driving of a plurality of micro light emitting diodes provided on the substrate (50).

[0106] The processor (40) may be implemented as a digital signal processor (DSP), a microprocessor, a graphics processing unit (GPU), an artificial intelligence (AI) processor, a neural processing unit (NPU), or a time controller (TCON) that processes a digital image signal. The processor (40) is not limited thereto, and may include one or more of a central processing unit (CPU), a micro controller unit (MCU), a micro processing unit (MPU), a controller, an application processor (AP), a communication processor (CP), or an ARM processor, or may be defined by the relevant terminology. The processor (40) may be implemented as a system on chip (SoC) or large scale integration (LSI) having a built-in processing algorithm, or may be implemented in the form of an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA).

[0107] The processor (40) can control hardware or software components connected to the processor (40) by running an operating system or application program, and can perform various data processing and operations. In addition, the processor (40) can load commands or data received from at least one of the other components into volatile memory and process them, and store various data in non-volatile memory.

[0108] The display driver IC (70) may include an interface module (71), a memory (72) (e.g., a buffer memory), an image processing module (73), or a mapping module (74). The display driver IC (70) may receive, for example, image information including image data or an image control signal corresponding to a command for controlling image data, from a corresponding component of the display device (10) through the interface module (71). For example, according to one embodiment, the image information may be received from a processor (40) (e.g., a main processor (e.g., an application processor) or an auxiliary processor (e.g., a graphics processing unit) that operates independently of the function of the main processor).

[0109] The display driver IC (70) can communicate with the sensor module and the interface module (71). In addition, the display driver IC (70) can store at least a portion of the received image information in the memory (72), for example, in units of frames. The image processing module (73) can, for example, perform preprocessing or postprocessing (e.g., resolution, brightness, or size adjustment) on at least a portion of the image data based on the characteristics of the image data or the characteristics of the substrate (50). The mapping module (74) can generate a voltage value or a current value corresponding to the image data preprocessed or postprocessed through the image processing module (73). According to one embodiment, the generation of the voltage value or current value may be performed at least in part based on, for example, properties of the pixels of the substrate (50), for example, the arrangement of the pixels (RGB stripe or pentile structure), or the size of each of the sub-pixels. At least some of the pixels of the substrate (50) may be driven at least in part based on, for example, the voltage value or current value, so that visual information (e.g., text, an image, or an icon) corresponding to the image data may be displayed through the substrate (50).

[0110] The display driver IC (70) can transmit a driving signal (e.g., a driver driving signal, a gate driving signal, etc.) to the display based on image information received from the processor (40).

[0111] The display driver IC (70) can display an image based on an image signal received from the processor (40). For example, the display driver IC (70) can display an image by generating a driving signal for a plurality of sub-pixels based on the image signal received from the processor (40) and controlling the light emission of the plurality of sub-pixels based on the driving signal.

[0112] According to one or more embodiments, the display module (30) may further include a touch circuit. The touch circuit may include a touch sensor and a touch sensor IC for controlling the same. The touch sensor IC may control the touch sensor to detect, for example, a touch input or a hovering input with respect to a designated location of the substrate (50). For example, the touch sensor IC may detect the touch input or the hovering input by measuring a change in a signal (e.g., voltage, light quantity, resistance, or charge quantity) with respect to the designated location of the substrate (50). The touch sensor IC may provide information (e.g., location, area, pressure, or time) regarding the detected touch input or hovering input to the processor (40). According to one embodiment, at least a portion of the touch circuit (e.g., the touch sensor IC) may be included as a part of the display driver IC (70), the substrate (50), or another component (e.g., a coprocessor) disposed externally to the display module (30).

[0113] According to one or more embodiments, the pixel driving method of the display module (30) may be an AM (active matrix) driving method or a PM (passive matrix) driving method.

[0114] According to one or more embodiments, the display device (10) may include a display module (30). The display module (30) may display various images. Here, the images may include still images and / or moving images. The display module (30) may display various images, such as broadcast content, multimedia content, etc. In addition, the display module (30) may also display a user interface and icons.

[0115] According to one or more embodiments, the display device (10) may include a plurality of display modules (30) and a support substrate to which the plurality of display modules (30) are each electrically connected. The display device (10) may be implemented as a large format display (LFD) in which a plurality of display modules (30) are arranged in a grid pattern on the support substrate.

[0116] A micro light emitting diode (61) according to one or more embodiments of the present disclosure may have a light collection structure, i.e., a concave reflective layer (61-4) provided on the lower portion of the micro light emitting diode (61) and a convex lens (61-5) provided on the upper portion of the micro light emitting diode (61). Accordingly, the efficiency of light emitted from the light emitting surface (61c) of the micro light emitting diode (61) manufactured in an ultra-small size (e.g., 30 μm or less) can be improved.

[0117] Although the preferred embodiments of the present disclosure have been illustrated and described above, the present disclosure is not limited to the specific embodiments described above, and various modifications may be made by a person having ordinary skill in the art to which the present disclosure pertains without departing from the gist of the present disclosure as claimed in the claims, and such modifications should not be understood individually from the technical idea or prospect of the present disclosure.

Claims

1. In micro light emitting diodes, A semiconductor part including an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer between the n-type semiconductor layer and the p-type semiconductor layer; A first pixel electrode electrically connected to the n-type semiconductor layer; A second pixel electrode electrically connected to the p-type semiconductor layer; A lens provided on the light-emitting surface of the semiconductor portion and focusing light emitted from the light-emitting surface of the semiconductor portion; and A reflective layer provided on the side of the semiconductor portion and reflecting light emitted from the light-emitting layer toward the light-emitting surface; Micro light emitting diodes.

2. In paragraph 1, The above lens, The central portion of the above lens is convexly configured, Micro light emitting diodes.

3. In paragraph 2, The size of the above semiconductor part is Less than 30㎛, Micro light emitting diodes.

4. In paragraph 3, The thickness of the above semiconductor part is 8㎛ to 10㎛, Micro light emitting diodes.

5. In paragraph 3, The thickness of the above lens is 1㎛ to 4㎛, Micro light emitting diodes.

6. In paragraph 5, The radius of curvature of the above lens is 30㎛ to 100㎛, Micro light emitting diodes.

7. In paragraph 1, The above lens, Containing one of SiO2, Al2O3, TiO2 and ITO (indium tin oxide), Micro light emitting diodes.

8. In paragraph 1, The side of the above semiconductor part is, It is configured to be inclined so as to form an acute angle with the light-emitting surface of the semiconductor portion. Micro light emitting diodes.

9. In paragraph 8, The above reflective layer is, configured to extend to the lower surface of the semiconductor portion opposite to the light-emitting surface of the semiconductor portion; Micro light emitting diodes.

10. In paragraph 9, The above reflective layer is, The semiconductor portion is concavely formed from the top to the bottom, Micro light emitting diodes.

11. In paragraph 9, The above reflective layer is, including a distributed bragg reflector (DBR), Micro light emitting diodes.

12. In a method for manufacturing a micro light-emitting diode, A step of forming a semiconductor part including an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer between the n-type semiconductor layer and the p-type semiconductor layer on a substrate; A step of forming a reflective layer on the side and bottom surfaces of the semiconductor portion; A step of forming a first chip electrode in contact with the n-type semiconductor and a second chip electrode in contact with the p-type semiconductor on the lower surface of the semiconductor portion; A step of separating the substrate from the light-emitting surface included in the n-type semiconductor layer of the semiconductor portion; and A step of forming a convex lens on the light-emitting surface of the semiconductor portion; The step of forming the semiconductor portion is: A step of applying a first photoresist layer on the epitaxial layer of the above substrate: A step of forming the first photoresist layer as a first mask pattern; and A step of forming a slope on the side surface of the semiconductor portion; including; Method for manufacturing micro light emitting diodes.

13. In paragraph 12, The step of forming the first photoresist layer as a first mask pattern is: A step of forming a plurality of islands by exposing the first photoresist layer; and A step of performing a reflow process to shrink the plurality of islands by surface tension so that the upper surface of each island is formed into a hemispherical shape; including; Method for manufacturing micro light emitting diodes.

14. In paragraph 12, The step of forming a slope on the side of the semiconductor portion is as follows: A first etching process for etching the epitaxial layer and the first mask pattern by setting the etching rate of the epitaxial layer to be greater than the etching rate of the first mask pattern; and A second etching process for etching the epitaxial layer and removing the first mask pattern by setting the etching rate of the first mask pattern to be greater than the etching rate of the epitaxial layer; Method for manufacturing micro light emitting diodes.

15. In paragraph 12, The step of forming the above lens is: A step of forming a transparent layer covering the semiconductor portion on the substrate; A step of applying a second photoresist layer covering the transparent layer on the substrate: A step of forming the second photoresist layer as a second mask pattern; and a step of forming a curvature in the upper region of the transparent layer; Method for manufacturing micro light emitting diodes.

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