Pixel, display device comprising same, and electronic device comprising display device

Abstract

A display device of the present invention comprises: a light-emitting element connected between a first power line to which a first power is provided and a first node; and a pixel driving circuit connected to the light-emitting element. The pixel driving circuit includes a driving transistor and a plurality of switching transistors, wherein the driving transistor is an N-type transistor, and at least one of the plurality of switching transistors is a P-type transistor.

Description

Pixels, display devices including the same, and electronic devices including the display devices

[0001] The present invention relates to a pixel capable of reducing power consumption, a display device including the same, and an electronic device including the same.

[0002] Emissive displays are a type of display that generates light from each pixel without a backlight. These emissive displays have a high contrast ratio, fast response speed, wide viewing angle, and low power consumption.

[0003] Emissive display devices include pixels connected to data lines and scan lines. Pixels typically include a light-emitting element and a pixel circuit for controlling the amount of current flowing to the light-emitting element. The pixel circuit controls the amount of current flowing to the light-emitting element in response to a data signal. At this time, light of a predetermined brightness is generated in response to the amount of current flowing through the light-emitting element.

[0004] However, pixel circuits may require large voltage swings to turn off the transistors. These large voltage swings increase power consumption, as power consumption increases as the square of the voltage difference. They also require high-voltage operation from peripheral circuits, such as gate drivers and voltage generators. This can lead to increased circuit complexity, larger non-display areas, reduced power efficiency, and potential long-term reliability issues. Furthermore, as light-emitting elements degrade over time, variations in pixel current can occur, resulting in brightness drift or image retention.

[0005] An object of the present invention is to provide a pixel capable of reducing power consumption and improving display reliability, a display device including the pixel, and an electronic device including the display device.

[0006] A display device according to an embodiment of the present invention may include a pixel including a light-emitting element connected between a first power line to which a first power is provided and a first node, and a pixel driving circuit connected to the light-emitting element. The pixel driving circuit may include a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node, a second transistor including a first electrode electrically connected to a data line to which a data signal is provided, a second electrode electrically connected to the third node, and a gate electrode that receives a scan signal, and a third transistor including a first electrode electrically connected to a first initialization voltage line to which a first initialization voltage is provided, a second electrode electrically connected to the first node, and a gate electrode that receives a compensation scan signal. The first transistor may be an N-type transistor, the second transistor may be an N-type transistor or a P-type transistor, the third transistor may be a P-type transistor, and a high level of the compensation scan signal may be 10 V or less.

[0007] The pixel driving circuit may further include a fourth transistor including a first electrode electrically connected to a reference voltage line to which a reference voltage is provided, a second electrode electrically connected to the third node, and a gate electrode receiving an initialization scan signal. The fourth transistor may be an N-type transistor or a P-type transistor.

[0008] During the initialization period, the initialization scan signal may be at an active level, and the compensation scan signal and the scan signal may be at an inactive level; during the compensation period, the compensation scan signal and the initialization scan signal may be at an active level, and the scan signal may be at an inactive level.

[0009] The pixel driving circuit may further include a first capacitor connected between the second node and the third node, and a second capacitor connected between the second node and a second power line to which a second power source having a lower voltage level than the first power source is provided.

[0010] The pixel driving circuit may further include a fifth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode receiving a first emission signal. The fifth transistor may be a P-type transistor.

[0011] The pixel driving circuit may further include a sixth transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a second power line to which a second power source having a lower voltage level than the first power source is provided, and a gate electrode receiving a second light emission signal. The sixth transistor may be an N-type transistor or a P-type transistor.

[0012] The high level of the first light-emitting signal may be 10 V or less.

[0013] During the initialization period, the second light-emitting signal may be at an active level and the first light-emitting signal may be at a non-active level, and during the compensation period, the first light-emitting signal may be at an active level and the second light-emitting signal may be at a non-active level.

[0014] The voltage value of the first power supply may be 8.4 V or less.

[0015] The voltage value of each of the first power supply and the first initialization voltage may be about 8.4 V, the voltage value of the second power supply may be about 0 V, and the high level of each of the compensation scan signal and the first light emission signal may be about 8.4 V.

[0016] The voltage value of each of the first power supply and the first initialization voltage may be about 7 V, and the voltage value of the second power supply may be about 0 V. The high level of each of the compensation scan signal and the first light emission signal may be about 7 V.

[0017] The pixel driving circuit further includes a fifth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode that receives a light emission signal, and a sixth transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a second power line to which a second power source having a lower voltage level than the first power source is provided, and a gate electrode that receives the light emission signal, wherein each of the fifth and sixth transistors may be a P-type transistor.

[0018] The pixel driving circuit further includes a seventh transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a second initialization voltage line to which a second initialization voltage having a lower voltage level than the first initialization voltage is provided, and a gate electrode receiving an input scan signal, wherein the seventh transistor may be an N-type transistor.

[0019] During the initialization period, the input scan signal may be at an active level, and during the compensation period, the input scan signal may be at an inactive level.

[0020] The pixel driving circuit further includes an eighth transistor including a first electrode electrically connected to the first initialization voltage line, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode receiving the compensation scan signal, wherein the eighth transistor may be a P-type transistor.

[0021] The voltage value of the first power supply may be about 8.4 V, the voltage value of the second power supply may be about 0 V, and the high level of the light emission signal may be 10 V or less. The voltage value of the first initialization voltage may be about 8.4 V, and the high level of the compensation scan signal may be 10 V or less.

[0022] The light-emitting element includes an anode, a cathode disposed on the anode, and at least a light-emitting layer, and includes an intermediate layer disposed between the anode and the cathode, wherein the anode is electrically connected to the first power line, and the cathode can be electrically connected to the first node.

[0023] The display device further includes a pixel defining film having an opening defined therein that exposes at least a portion of the anode, a connection electrode disposed on the pixel defining film and electrically connected to the first node and the cathode, and a separator disposed on the pixel defining film, wherein in a contact area adjacent to the separator, a lower surface of the cathode can contact an upper surface of the connection electrode.

[0024] According to one embodiment of the present invention, a display device may include a first electrode, an intermediate layer disposed on the first electrode and including at least a light-emitting layer, and a second electrode disposed on the intermediate layer, a light-emitting element connected between a first power line to which a first power is supplied and a first node, a driving transistor, and a plurality of switching transistors, and a pixel driving circuit connected to the light-emitting element, a pixel defining layer defining an opening exposing at least a portion of the first electrode, a connection electrode disposed on the pixel defining layer and electrically connected to the pixel driving circuit and the second electrode, and a separator disposed on the pixel defining layer. In a contact region adjacent to the separator, a lower surface of the second electrode may be in contact with an upper surface of the connection electrode, the driving transistor may be an N-type transistor, and at least one of the plurality of switching transistors may be a P-type transistor.

[0025] According to one embodiment of the present invention, there is provided a display device for displaying an electronic device image, and a processor for controlling driving of the display device. The display device may include a pixel including a light-emitting element connected between a first power line to which a first power is provided and a first node, and a pixel driving circuit connected to the light-emitting element. The pixel driving circuit may include a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node, a second transistor including a first electrode electrically connected to a data line to which a data signal is provided, a second electrode electrically connected to the third node, and a gate electrode for receiving a scan signal, and a third transistor including a first electrode electrically connected to a first initialization voltage line to which a first initialization voltage is provided, a second electrode electrically connected to the first node, and a gate electrode for receiving a compensation scan signal. The first transistor is an N-type transistor, the second transistor is an N-type transistor or a P-type transistor, the third transistor is a P-type transistor, and the high level of the compensation scan signal may be 10 V or less.

[0026] According to the present invention, the cathode of the light-emitting element can be electrically connected to the drain of the driving transistor. The driving transistor in the pixel driving circuit can be an N-type transistor, and at least one of the switching transistors can be a P-type transistor. Through this, the maximum voltage value required to turn on and off the transistors in the pixel driving circuit can be lowered. Accordingly, the voltage difference between the maximum voltage value and the minimum voltage value can be reduced, and a pixel with reduced power consumption and a display device including the same can be provided.

[0027] FIG. 1 is a block diagram of a display device according to one embodiment of the present invention.

[0028] Figure 2 is a circuit diagram of a pixel according to one embodiment of the present invention.

[0029] FIG. 3 is a timing diagram for explaining the operation of the pixel of FIG. 2 according to one embodiment of the present invention.

[0030] Figure 4 is a circuit diagram of a pixel according to one embodiment of the present invention.

[0031] FIG. 5 is a timing diagram for explaining the operation of the pixel of FIG. 4 according to one embodiment of the present invention.

[0032] Figure 6 is a circuit diagram of a pixel according to one embodiment of the present invention.

[0033] FIG. 7 is a timing diagram for explaining the operation of the pixel of FIG. 6 according to one embodiment of the present invention.

[0034] Figure 8 is a circuit diagram of a pixel according to one embodiment of the present invention.

[0035] FIG. 9 is a timing diagram for explaining the operation of the pixel of FIG. 8 according to one embodiment of the present invention.

[0036] Fig. 10 is a circuit diagram of a pixel according to one embodiment of the present invention.

[0037] FIG. 11 is a timing diagram for explaining the operation of the pixel of FIG. 10 according to one embodiment of the present invention.

[0038] FIG. 12a is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0039] FIG. 12b is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0040] FIG. 13a is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0041] FIG. 13b is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0042] FIG. 13c is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0043] FIG. 13d is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0044] Figure 14 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0045] FIG. 15 is an enlarged cross-sectional view of a portion of a display panel according to one embodiment of the present invention.

[0046] Fig. 16 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0047] Figure 17 is a block diagram of an electronic device according to one embodiment of the present invention.

[0048] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0049] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" encompasses any combination of one or more of the associated components.

[0050] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0051] Additionally, terms such as "below," "below," "above," and "above" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0052] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0053] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0054] The present invention relates to a pixel driver circuit for a display device designed to reduce power consumption. The pixel driver circuit may employ a hybrid configuration using NMOS transistors as the driver transistors and PMOS transistors as switching transistors, such as compensation transistors and emission control transistors. This NMOS / PMOS hybrid configuration allows pixels to operate with lower gate high voltages and significantly reduces the voltage swing between logic levels required for pixel operation. Since power consumption is proportional to the square of this voltage swing, this configuration substantially reduces power consumption. Furthermore, by configuring the driver transistor as an NMOS and connecting the cathode of the light-emitting element to the drain of the driver transistor, a stable source voltage can be maintained regardless of light-emitting element deterioration. This maintains a constant gate-source voltage (Vgs) of the driver transistor, enabling the pixel to output a stable current for an extended period of time. Consequently, the display becomes less susceptible to brightness fluctuations, image retention, and uneven degradation, and has a longer lifespan and improved long-term image quality. In some embodiments, pixel wiring can be further simplified by reusing existing power lines for source initialization, reducing the need for separate initialization voltage lines, reducing non-display area, and improving circuit reliability.

[0055] FIG. 1 is a block diagram of a display device (DD) according to one embodiment of the present invention.

[0056] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a driving controller (100) (e.g., a controller circuit), a data driving circuit (200), and a voltage generator (300).

[0057] A display panel (DP) according to an embodiment of the present invention may be an emissive display panel, and is not particularly limited thereto. For example, the display panel (DP) may be an organic light-emitting display panel, a quantum dot light-emitting display panel, a micro LED display panel, or a nano LED display panel. The emissive layer of the organic light-emitting display panel may include an organic light-emitting material. The emissive layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. The emissive layer of the micro LED display panel may include micro LEDs. The emissive layer of the nano LED display panel may include nano LEDs.

[0058] The drive controller (100) can receive an image signal (RGB) and a control signal (CTRL). The drive controller (100) can generate an image data signal (DATA) by converting the data format of the image signal (RGB) to match the interface specifications with the data drive circuit (200). The drive controller (100) can output a scan control signal (SCS), a data control signal (DCS), and an emission drive control signal (ECS).

[0059] The data driving circuit (200) can receive a data control signal (DCS) and an image data signal (DATA) from the driving controller (100). The data driving circuit (200) can convert the image data signal (DATA) into data signals (Vdata, see FIG. 2) and output the data signals (Vdata, see FIG. 2) to a plurality of data lines (DL1 to DLm), respectively. The data signals (Vdata, see FIG. 2) can be analog voltages corresponding to grayscale values ​​of the image data signal (DATA).

[0060] In one embodiment of the present invention, the data driving circuit (200) can output data signals (Vdata, see FIG. 2) corresponding to the image data signal (DATA) to the data lines (DL1 to DLm) during a frame section (e.g., driving section) of one frame.

[0061] The voltage generator (300) can generate voltages required for the operation of the display panel (DP). In one embodiment of the present invention, the voltage generator (300) can generate a first power supply (ELVDD), a second power supply (ELVSS), a reference voltage (Vref), and an initialization voltage (Vcint).

[0062] The display panel (DP) may include scan lines (GCL1 to GCLn, GWL1 to GWLn, GRL1 to GRLn), emission control lines (EML11 to EML1n, EML21 to EML2n), data lines (DL1 to DLm), and pixels (PX). The display panel (DP) may further include a scan driving circuit (SD) and an emission driving circuit (EDC).

[0063] A scan driving circuit (SD) may be arranged on a first side of a display panel (DP). Scan lines (GCL1 to GCLn, GWL1 to GWLn, GRL1 to GRLn) may extend in a first direction (DR1) from the scan driving circuit (SD).

[0064] The emission driving circuit (EDC) may be arranged on the second side of the display panel (DP). The emission control lines (EML11 to EML1n, EML21 to EML2n) ​​may extend from the emission driving circuit (EDC) in a direction opposite to the first direction (DR1).

[0065] Each of the scan lines (GCL1 to GCLn, GWL1 to GWLn, GRL1 to GRLn) and the emission control lines (EML11 to EML1n, EML21 to EML2n) ​​can be arranged spaced apart from each other in the second direction (DR2).

[0066] The scan lines (GCL1 to GCLn, GWL1 to GWLn, GRL1 to GRLn) may include compensation scan lines (GCL1 to GCLn), write scan lines (GWL1 to GWLn), and initialization scan lines (GRL1 to GRLn).

[0067] The light emission control lines (EML11 to EML1n, EML21 to EML2n) ​​may include first light emission control lines (EML11 to EML1n) and second light emission control lines (EML21 to EML2n).

[0068] The data lines (DL1 to DLm) may extend from the data driving circuit (200) in a direction opposite to the second direction (DR2). Each of the data lines (DL1 to DLm) may be arranged spaced apart from each other in the first direction (DR1).

[0069] In the example illustrated in FIG. 1, the scan driving circuit (SD) and the light emitting driving circuit (EDC) are arranged facing each other with pixels (PX) interposed therebetween, but the present invention is not limited thereto. For example, the scan driving circuit (SD) and the light emitting driving circuit (EDC) may be arranged adjacent to each other on either the first side or the second side of the display panel (DP). In one embodiment, the scan driving circuit (SD) and the light emitting driving circuit (EDC) may be configured as a single circuit.

[0070] A plurality of pixels (PX) can be electrically connected to scan lines (GCL1 to GCLn, GWL1 to GWLn, GRL1 to GRLn), emission control lines (EML11 to EML1n, EML21 to EML2n), and data lines (DL1 to DLm), respectively. Each of the plurality of pixels (PX) can be electrically connected to four scan lines and two emission control lines.

[0071] Each of the plurality of pixels (PX) may include a light-emitting element (LD, see FIG. 2) and a pixel circuit unit that controls light emission of the light-emitting element (LD, see FIG. 2).

[0072] Each light-emitting element (LD, see FIG. 2) of a plurality of pixels (PX) can generate different color light. For example, the pixels may include red pixels that generate red color light, green pixels that generate green color light, and blue pixels that generate blue color light. The light-emitting elements of the red pixels, the light-emitting elements of the green pixels, and the light-emitting elements of the blue pixels may include light-emitting layers of different materials.

[0073] The pixel circuit unit may include at least one transistor and at least one capacitor, as described below. The scan driving circuit (SD) and the emission driving circuit (EDC) may include transistors formed through the same process as the transistors of the pixel circuit unit.

[0074] Each of the plurality of pixels (PX) can receive a first power supply (ELVDD), a second power supply (ELVSS), a reference voltage (Vref), and an initialization voltage (Vcint) from a voltage generator (300).

[0075] The scan driving circuit (SD) can receive a scan control signal (SCS) from the driving controller (100). The scan driving circuit (SD) can output scan signals to scan lines (GCL1 to GCLn, GWL1 to GWLn, GRL1 to GRLn) in response to the scan control signal (SCS).

[0076] The light emitting drive circuit (EDC) can output light emitting signals to light emitting control lines (EML11 to EML1n, EML21 to EML2n) ​​in response to a light emitting drive control signal (ECS) from the drive controller (100).

[0077] A drive controller (100) according to one embodiment of the present invention can determine a drive frequency and control a data drive circuit (200), a scan drive circuit (SD), and an emission drive circuit (EDC) according to the determined drive frequency.

[0078] Fig. 2 is a circuit diagram of a pixel (PXij) according to one embodiment of the present invention. Each of the plurality of pixels (PX) illustrated in Fig. 1 may have the same circuit configuration as the equivalent circuit diagram of the pixel (PXij) illustrated in Fig. 2.

[0079] Referring to FIG. 2, a pixel (PXij) can be connected to a j-th data line (DLj) among data lines (DL1 to DLm), an i-th compensation scan line (GCLi) among compensation scan lines (GCL1 to GCLn), an i-th write scan line (GWLi) among write scan lines (GWL1 to GWLn), an i-th initialization scan line (GRLi) among initialization scan lines (GRL1 to GRLn), an i-th first emission control line (EML1i) among first emission control lines (EML11 to EML1n), and an i-th second emission control line (EML2i) among second emission control lines (EML21 to EML2n). Here, i and j are natural numbers.

[0080] A pixel (PXij) may include a light-emitting element (LD) and a pixel driving circuit (PCij). The light-emitting element (LD) may be a light-emitting diode, and for example, the light-emitting element (LD) may be an organic light-emitting diode including an organic light-emitting layer. The pixel driving circuit (PCij) may be connected to the light-emitting element (LD) to control the amount of current flowing to the light-emitting element (LD), and the light-emitting element (LD) may generate light having a predetermined brightness according to the amount of current provided.

[0081] The pixel driver circuit (PCij) may include first to sixth transistors (T1, T2, T3, T4, T5, T6) and capacitors (Cst, Chold).

[0082] A pixel (PXij) according to one embodiment of the present invention may be referred to as having a 6T2C structure.

[0083] In the present invention, the first transistor (T1) is an N-type transistor. At least one of the second to sixth transistors (T2, T3, T4, T5, T6) is a P-type transistor. The remaining transistors (T2, T3, T4, T5, T6) except for at least one of the second to sixth transistors (T2, T3, T4, T5, T6) may be N-type transistors. The first transistor (T1) may have an oxide semiconductor as a semiconductor layer. At least one of the second to sixth transistors (T2, T3, T4, T5, T6) may have a silicon semiconductor as a semiconductor layer, and the remaining transistors (T2, T3, T4, T5, T6) may have an oxide semiconductor as a semiconductor layer. For example, the silicon semiconductor may include amorphous silicon, low-temperature polycrystalline silicon (LTPS), crystalline silicon, etc. However, this is exemplary, and the semiconductor layer of each transistor according to an embodiment is not limited.

[0084] Scan lines (GCLi, GWLi, GRLi) can transmit scan signals (GC, GW, GR), respectively, and emission control lines (EML1i, EML2i) can transmit emission signals (EM1, EM2). Data lines (DLj) can transmit data signals (Vdata). The data signals (Vdata) can have voltage levels corresponding to image signals (RGB, see Fig. 1) input to a display device (DD, see Fig. 1).

[0085] The first power line (PL1) can provide the first power (ELVDD). The second power line (PL2) can provide the second power (ELVSS). The second power (ELVSS) can have a lower voltage level than the first power (ELVDD). The reference voltage line (VL1) can provide the reference voltage (Vref). The first initialization voltage line (VL2) can provide the first initialization voltage (Vcint).

[0086] A light emitting element (LD) may be connected between a first power line (PL1) to which a first power source (ELVDD) is provided and a first node (N1). The light emitting element (LD) may include an anode (AE) and a cathode (CE). The anode (AE) may be directly connected to the first power line (PL1). The cathode (CE) may be electrically connected to a second power line (PL2) via a fifth transistor (T5), a first transistor (T1), and a sixth transistor (T6).

[0087] When the light-emitting element (LD) is an organic light-emitting element, the light-emitting element (LD) may further include an organic layer disposed between the anode (AE) and the cathode (CE). The cathode (CE) of the light-emitting element (LD) may be connected to the pixel driving circuit (PCij) via the first node (N1). The light-emitting element (LD) may emit light in response to the amount of driving current (Id) flowing in the first transistor (T1) of the pixel driving circuit (PCij).

[0088] The first transistor (T1) may include a first electrode electrically connected to the first node (N1) via the fifth transistor (T5), a second electrode electrically connected to the second node (N2), and a gate electrode electrically connected to the third node (N3). The first transistor (T1) may be referred to as a driving transistor. In one embodiment of the present invention, the first transistor (T1) may further include a back gate electrode. The back gate electrode of the first transistor (T1) may be connected to the second electrode of the first transistor (T1). Meanwhile, the embodiment is not limited thereto, and the back gate electrode of the first transistor (T1) may be omitted.

[0089] According to the present invention, the first transistor (T1) is an N-type transistor. The cathode (CE) of the light-emitting element (LD) may be connected to the drain (or first electrode) of the first transistor (T1). In this case, even if the light-emitting element (LD) deteriorates, the voltage at the source (or second electrode) terminal of the first transistor (T1) may not shift. That is, even if the light-emitting element (LD) deteriorates, the gate-source voltage (referred to as Vgs) of the first transistor (T1) may not change. Therefore, even if the usage time of the pixel (PX) increases, the range of change in the amount of current flowing through the first transistor (T1) is reduced, so that the afterimage defect (or long-term afterimage defect) of the display panel (DP, see FIG. 1) is reduced, and the lifespan of the display panel (DP, see FIG. 1) can be improved. Therefore, a pixel (PXij) with improved display quality and a display device (DD, see FIG. 1) including the same can be provided.

[0090] A second transistor (T2) may include a first electrode electrically connected to a data line (DLj) to which a data signal (Vdata) is provided, a second electrode electrically connected to a third node (N3), and a gate electrode receiving a scan signal (GW). The gate electrode of the second transistor (T2) may be connected to a write scan line (GWLi).

[0091] A third transistor (T3) may include a first electrode electrically connected to a first initialization voltage line (VL2), a second electrode electrically connected to a first node (N1), and a gate electrode receiving a compensation scan signal (GC). The gate electrode of the third transistor (T3) may be connected to a compensation scan line (GCLi).

[0092] The fourth transistor (T4) may include a first electrode electrically connected to a reference voltage line (VL1) to which a reference voltage (Vref) is provided, a second electrode electrically connected to a third node (N3), and a gate electrode receiving an initialization scan signal (GR). The gate electrode of the fourth transistor (T4) may be connected to an initialization scan line (GRLi).

[0093] The fifth transistor (T5) may include a first electrode electrically connected to the first node (N1), a second electrode electrically connected to the first electrode of the first transistor (T1), and a gate electrode receiving a first emission signal (EM1). The gate electrode of the fifth transistor (T5) may be connected to a first emission control line (EML1i). In this specification, the fifth transistor (T5) may be referred to as a first emission control transistor.

[0094] The sixth transistor (T6) may include a first electrode electrically connected to a second node (N2), a second electrode electrically connected to a second power line (PL2) to which a second power source (ELVSS) is provided, and a gate electrode receiving a second light emission signal (EM2). The gate electrode of the sixth transistor (T6) may be connected to a second light emission control line (EML2i). In the present specification, the sixth transistor (T6) may be referred to as a second light emission control transistor.

[0095] According to one embodiment of the present invention, each of the second to sixth transistors (T2, T3, T4, T5, T6) may be a P-type transistor. That is, all of the second to sixth transistors (T2, T3, T4, T5, T6) corresponding to the switching transistors, except for the driving transistor, may be provided as P-type transistors. In particular, when the third transistor (T3) electrically connected to the first initialization voltage line (VL2) to which the first initialization voltage (Vcint) is provided and the fifth transistor (T5) electrically connected to the first power line (PL1) to which the first power (ELVDD) is provided are provided as P-type transistors, the gate high voltages of each of the third and fifth transistors (T3, T5) may be set lower than when they are provided as N-type transistors. That is, the high levels of each of the compensation scan signal (GC) and the first emission signal (EM1) may be set lower. The high level of the compensation scan signal (GC) may be 10 V or lower. The high level of the first emission signal (EM1) may be 10 V or lower. Accordingly, a pixel (PXij) with improved power consumption and a display device (DD, see FIG. 1) including the pixel may be provided. A detailed description thereof will be provided later.

[0096] A first capacitor (Cst) may be connected between a second node (N2) and a third node (N3). A second capacitor (Chold) may be connected between a second node (N2) and a second power line (PL2).

[0097] FIG. 3 is a timing diagram for explaining the operation of the pixel (PXij) of FIG. 2 according to one embodiment of the present invention.

[0098] Referring to FIGS. 2 and 3, the display panel (DP, see FIG. 1) can display an image by operating in units of frame periods (FP). One frame period (FP) can include first to fourth periods (t1, t2, t3, t4). The first to third periods (t1, t2, t3) can be referred to as non-emitting periods, and the fourth period (t4) can be referred to as an emitting period.

[0099] In the first period (t1), the initialization scan signal (GR) and the second emission signal (EM2) may be at an active level. The active level of each of the initialization scan signal (GR) and the second emission signal (EM2) may be a low level.

[0100] In the first period (t1), the compensation scan signal (GC), the first emission signal (EM1), and the scan signal (GW) may be at inactive levels. The inactive levels of each of the compensation scan signal (GC), the first emission signal (EM1), and the scan signal (GW) may be at a high level.

[0101] The fourth transistor (T4) can be turned on in response to an initialization scan signal (GR). A reference voltage (Vref) can be provided to the third node (N3) through the fourth transistor (T4).

[0102] During the first period (t1), the gate electrode of the first transistor (T1) can be initialized to the reference voltage (Vref). That is, the voltage of the third node (N3) can change from the data signal (Vdata) of the previous frame period to the reference voltage (Vref).

[0103] The sixth transistor (T6) can be turned on in response to the second emission signal (EM2). A second power source (ELVSS) can be provided to the second node (N2) through the sixth transistor (T6).

[0104] During the first period (t1), the source of the first transistor (T1) can be initialized with the second power supply (ELVSS). The pixel (PXij) can initialize the source of the first transistor (T1) through the second power supply (ELVSS) without using a separate initialization voltage.

[0105] According to the present invention, a separate power line for supplying an initialization voltage to a second node (N2) may be omitted from a voltage generator (300, see FIG. 1). Accordingly, the area of ​​a non-display area (NDA, see FIG. 12a) may be reduced. In addition, the number of power lines included in a pixel (PXij) may be reduced. When the number of power lines is reduced, the spacing or space between wires included in a pixel (PXij) may be increased. Accordingly, signal interference between wires is reduced, thereby providing a pixel (PXij) and a display device (DD, see FIG. 1) with improved display quality.

[0106] The first interval (t1) may be referred to as an initialization interval.

[0107] In the second period (t2), the compensation scan signal (GC), the initialization scan signal (GR), and the first emission signal (EM1) may be at an active level. The active level of each of the compensation scan signal (GC), the initialization scan signal (GR), and the first emission signal (EM1) may be a low level.

[0108] In the second period (t2), the second emission signal (EM2) and the scan signal (GW) may be at inactive levels. The inactive levels of each of the second emission signal (EM2) and the scan signal (GW) may be at a high level.

[0109] The fourth transistor (T4) can be turned on in response to an initialization scan signal (GR). A reference voltage (Vref) can be provided to the third node (N3) through the fourth transistor (T4).

[0110] The third transistor (T3) can be turned on in response to a compensation scan signal (GC). The fifth transistor (T5) can be turned on in response to a first emission signal (EM1). The first transistor (T1) can be turned on in response to a reference voltage (Vref) provided to the gate electrode.

[0111] As the third transistor (T3) and the fifth transistor (T5) are turned on, the first transistor (T1) can operate as a source follower. A voltage (Vref-Vth) lower than the threshold voltage (referred to as Vth) of the first transistor (T1) than the reference voltage (Vref) can be provided to the second node (N2) corresponding to the source of the first transistor (T1). That is, a voltage of Vref-Vth can be provided to the source of the first transistor (T1).

[0112] A second capacitor (Chold) may be connected to a second node (N2). One electrode of the second capacitor (Chold) may be connected to a second power line (PL2) supplied with a second power source (ELVSS), and the other electrode of the second capacitor (Chold) may be connected to a second node (N2). The second capacitor (Chold) may store a charge corresponding to a voltage difference ((Vref-Vth)-ELVSS) between the second power source (ELVSS) and the second node (N2). The second capacitor (Chold) may be referred to as a hold capacitor. The second capacitor (Chold) may have a higher storage capacity compared to the first capacitor (Cst). The second capacitor (Chold) may minimize a voltage change of the second node (N2) in response to a voltage change of the third node (N3).

[0113] The second period (t2) may be referred to as a compensation period.

[0114] In the third period (t3), the scan signal (GW) may be at an active level. The active level of the scan signal (GW) may be a low level.

[0115] In the third period (t3), the compensation scan signal (GC), the initialization scan signal (GR), the first emission signal (EM1), and the second emission signal (EM2) may be at inactive levels. The inactive levels of each of the compensation scan signal (GC), the initialization scan signal (GR), the first emission signal (EM1), and the second emission signal (EM2) may be at a high level.

[0116] The second transistor (T2) can be turned on in response to a scan signal (GW). A data signal (Vdata) provided through a data line (DLj) can be provided to a third node (N3).

[0117] A first capacitor (Cst) may be placed between a second node (N2) and a third node (N3). The first capacitor (Cst) may store a voltage corresponding to a voltage difference between the second node (N2) and the third node (N3). A voltage level of one end of the first capacitor (Cst), that is, the third node (N3), may change to a voltage level of a data signal (Vdata). At this time, a voltage level of the other end of the first capacitor (Cst), that is, the second node (N2), may be a voltage level of Vref-Vth. The first capacitor (Cst) may store a charge corresponding to a voltage difference (Vdata-(Vref-Vth)) between the third node (N3) and the second node (N2). The first capacitor (Cst) may be referred to as a storage capacitor.

[0118] The third period (t3) may be referred to as a write period.

[0119] In the fourth section (t4), the first light emission signal (EM1) and the second light emission signal (EM2) may be at an active level. The active level of each of the first light emission signal (EM1) and the second light emission signal (EM2) may be a low level.

[0120] In the fourth period (t4), the compensation scan signal (GC), the initialization scan signal (GR), and the scan signal (GW) may be at inactive levels. The inactive levels of each of the compensation scan signal (GC), the initialization scan signal (GR), and the scan signal (GW) may be at a high level.

[0121] The fifth transistor (T5) can be turned on in response to the first light-emitting signal (EM1). The sixth transistor (T6) can be turned on in response to the second light-emitting signal (EM2).

[0122] As the fifth transistor (T5) and the sixth transistor (T6) are turned on, a current path can be formed from the first power line (PL1) to the light-emitting element (LD), the fifth transistor (T5), the first transistor (T1), the sixth transistor (T6), and the second power line (PL2). That is, the driving current (Id) can flow to the second power source (ELVSS) via the first power line (PL1), the light-emitting element (LD), the fifth transistor (T5), the first transistor (T1), the sixth transistor (T6), and the second power line (PL2).

[0123] The voltage value of the second power supply (ELVSS) may be less than the value obtained by subtracting the threshold voltage (Vth) of the first transistor (T1) from the reference voltage (Vref).

[0124] Unlike the present invention, when the second power supply (ELVSS) is greater than the value obtained by subtracting the threshold voltage (Vth) of the first transistor (T1) from the reference voltage (Vref), an unintended current may be generated. However, according to the present invention, the second power supply (ELVSS) can be set to a value smaller than the value obtained by subtracting the threshold voltage (Vth) of the first transistor (T1) from the reference voltage (Vref), so that the current path can be reliably formed and the light emitting element (LD) can easily emit light. Accordingly, a pixel (PXij) with improved display quality and a display device (DD, see FIG. 1) including the pixel (PXij) can be provided.

[0125] Data signals output from a data driving circuit (200, see Fig. 1) of a display panel (DP, see Fig. 1) are written, and accordingly, a light-emitting element (LD) can emit light. The driving current (Id) can be expressed by the following mathematical formulas.

[0126] [Mathematical Formula 1]

[0127]

[0128] [Equation 2]

[0129]

[0130] [Equation 3]

[0131]

[0132] [Equation 4]

[0133]

[0134] In the above mathematical equations, μ may represent the electric field mobility, Cox may represent the capacitance of the gate insulating film, W / L may represent the width and length of the first transistor (T1), and Vgs may represent the gate-source voltage of the first transistor (T1). μ and Cox may be constants. Mathematical equation 4 may be a summary of Mathematical equation 3, which reflects Mathematical equation 2 in Mathematical equation 1.

[0135] The threshold voltage (Vth) of the first transistor (T1) included in each of the pixels (PX, see FIG. 1) may differ depending on the characteristics of the first transistor (T1). However, according to the present invention, the threshold voltage (Vth) of the first transistor (T1) may not affect the driving current (Id) flowing through the light-emitting element (LD) during the first to fourth periods (t1, t2, t3, t4). Referring to mathematical expression 4, the driving current (Id) flowing in the light-emitting element (LD) in the fourth period (t4) may not be affected by the threshold voltage (Vth) of the first transistor (T1). The driving current (Id) flowing in the light-emitting element (LD) may be proportional to the square of the difference between the data signal (Vdata) and the reference voltage (Vref) regardless of the characteristics of the first transistor (T1). Accordingly, the brightness of the image output from the display panel (DP, see Fig. 1) can be maintained uniformly. Accordingly, a display device (DD, see Fig. 1) including pixels (PXij) and pixels (PXij) with improved display quality can be provided.

[0136] In addition, the voltage level of the second power supply (ELVSS) in the second power line (PL2) may change due to a voltage drop (referred to as IR Drop). However, according to the present invention, the second power supply (ELVSS) may not affect the driving current (Id) flowing through the light-emitting element (LD) during the first to fourth periods (t1, t2, t3, t4). Referring to mathematical expression 4, the driving current (Id) flowing in the light-emitting element (LD) in the fourth period (t4) may not be affected by the second power supply (ELVSS). The driving current (Id) may be proportional to the square of the difference between the data signal (Vdata) and the reference voltage (Vref) regardless of the voltage value of the second power supply (ELVSS). Accordingly, the brightness of the image output from the display panel (DP, see FIG. 1) may be maintained uniformly. Accordingly, a display device (DD, see Fig. 1) including pixels (PXij) and pixels (PXij) with improved display quality can be provided.

[0137] In addition, according to the present invention, the first transistor (T1) is an N-type transistor, and the cathode (CE) of the light-emitting element (LD) may be electrically connected to the drain of the first transistor (T1). In this case, even if the light-emitting element (LD) deteriorates, the voltage of the source terminal of the first transistor (T1), which affects the driving current (Id), may not change or shift. That is, even if the light-emitting element (LD) deteriorates, the gate-source voltage (Vgs) of the first transistor (T1) may not change. Accordingly, even if the usage time increases, the range of change in the amount of current flowing to the first transistor (T1) is reduced, so that the afterimage defect (or long-term afterimage defect) of the display panel (DP, see FIG. 1) is reduced, and the lifespan of the display panel (DP, see FIG. 1) can be improved. Accordingly, a display device (DD, see FIG. 1) including pixels (PXij) and pixels (PXij) with improved display quality can be provided.

[0138] The fourth section (t4) may be referred to as the luminous section.

[0139] In one embodiment of the present invention, the voltage value of the first power supply (ELVDD) may be about 8.4 V, and the voltage value of the second power supply (ELVSS) may be about 0 V. The voltage value of the reference voltage (Vref) may be about 2.7 V. The voltage value of the first initialization voltage (Vcint) may be the same as the voltage value of the first power supply (ELVDD). The voltage value of the first initialization voltage (Vcint) may be about 8.4 V. The voltage value of the data signal (Vdata) may be about 2 V to about 7 V. The threshold voltage (Vth) of the N-type transistor may be about 0 V, the threshold voltage (Vth) of the P-type transistor may be about -2 V, and a margin value for Vth may be set to about 2 V.

[0140] The low level or activation level of each of the compensation scan signal (GC) and the first emission signal (EM1) may be about 4.4 V, and the high level or deactivation level may be about 8.4 V. The turn-on voltage for turning on the third transistor (T3) and the fifth transistor (T5) may be about 4.4 V, and the turn-off voltage for turning off the third transistor (T3) and the fifth transistor (T5) may be about 8.4 V.

[0141] The low level or activation level of the scan signal (GW) may be -2 V, and the high level or deactivation level may be 7 V. The turn-on voltage for turning on the second transistor (T2) may be about -2 V, and the turn-off voltage for turning off the second transistor (T2) may be about 7 V.

[0142] The low level or activation level of the initialization scan signal (GR) may be -1.3 V, and the high level or deactivation level may be 2.7 V. The turn-on voltage for turning on the fourth transistor (T4) may be about -1.3 V, and the turn-off voltage for turning off the fourth transistor (T4) may be about 2.7 V.

[0143] The low level or activation level of the second light emitting signal (EM2) may be -3 V, and the high level or deactivation level may be 1 V. The turn-on voltage for turning on the sixth transistor (T6) may be about -3 V, and the turn-off voltage for turning off the sixth transistor (T6) may be about 1 V.

[0144] The maximum voltage value (or the maximum voltage value of the gate high voltage of the transistors) required to turn on and off the transistors in the pixel driver circuit (PCij) may be about 8.4 V, and the minimum voltage value (or the minimum voltage value of the gate low voltage of the transistors) may be about -3 V. In the present embodiment, the maximum voltage value may be determined by the high level, that is, the deactivation level, of each of the compensation scan signal (GC) and the first emission signal (EM1), and the minimum voltage value may be determined by the low level, that is, the activation level of the second emission signal (EM2). The voltage difference between the maximum voltage value and the minimum voltage value may be about 11.4 V.

[0145] In contrast to the present invention, when the second to sixth transistors (T2, T3, T4, T5, and T6) are all provided as N-type, the active level of each of the compensation scan signal (GC), the initialization scan signal (GR), the first emission signal (EM1), the second emission signal (EM2), and the scan signal (GW) may be a high level, and the inactive level may be a low level. In addition, the turn-on voltage for turning on each of the second to sixth transistors (T2, T3, T4, T5, and T6) may correspond to the high level of the corresponding signal. In this case, the low level or inactive level of each of the compensation scan signal (GC) and the first emission signal (EM1) may be 6.4 V, and the high level or active level may be 10.4 V. The low level or inactive level of the scan signal (GW) may be 0 V, and the high level or active level may be 9 V. The low level or deactivation level of the initialization scan signal (GR) may be 0.7 V, and the high level or activation level may be 4.7 V. The low level or deactivation level of the second emission signal (EM2) may be -2 V, and the high level or activation level may be 3 V. In this case, the maximum voltage value required to turn on and off the transistors in the pixel driving circuit (PCij) may be about 10.4 V, and the minimum voltage value may be about -2 V. The voltage difference between the maximum voltage value and the minimum voltage value may be about 12.4 V.

[0146] That is, when each of the third transistor (T3) and the fifth transistor (T5) is provided as an N-type, the turn-on voltage for turning on each of the third transistor (T3) and the fifth transistor (T5) can be set higher than 8.4 V. That is, the activation level, which is a high level of the compensation scan signal (GC) and the first light emission signal (EM1), can be set higher than 8.4 V, and the maximum voltage value required for turning on and off the transistors in the pixel driving circuit (PCij) can also be increased.

[0147] Meanwhile, when the sixth transistor (T6) is provided as an N-type, the turn-off voltage for turning off the sixth transistor (T6) can be set higher than -2 V. That is, the deactivation level, which is the low level of the second light emission signal (EM2), can be set higher than -2 V, and the minimum voltage value required for turning on and off the transistors in the pixel driving circuit (PCij) can also be increased. However, since the degree to which the low level of the second light emission signal (EM2) increases is small compared to the degree to which the high level of the compensation scan signal (GC) increases, when the third, fifth, and sixth transistors (T3, T5, T6) are provided as an N-type, the voltage difference between the maximum voltage value and the minimum voltage value can increase compared to when they are provided as a P-type.

[0148] Therefore, according to the present embodiment, by providing the second to sixth transistors (T2, T3, T4, T5, T6) as P-type, the voltage difference between the maximum voltage value and the minimum voltage value can be reduced. Since the power consumption is proportional to the square of the voltage difference between the maximum voltage value and the minimum voltage value, a pixel (PXij) with reduced power consumption and a display device (DD, see FIG. 1) including the same can be provided.

[0149] Additionally, according to one embodiment of the present invention, the first power supply (ELVDD) can be driven even if the voltage value has a voltage value lower than 8.4 V. That is, the voltage value of the first power supply (ELVDD) can be lower than 8.4 V. For example, when the voltage value of the second power supply (ELVSS) is about 0 V, the voltage value of the reference voltage (Vref) is about 2.7 V, and the voltage value of the data signal (Vdata) is about 2 V to about 7 V, the voltage value of the first power supply (ELVDD) can be set to about 7 V. The voltage value of the first initialization voltage (Vcint) can be the same as the voltage value of the first power supply (ELVDD), and the voltage value of the first initialization voltage (Vcint) can also be set to about 7 V. In this case, the low level or activation level of each of the compensation scan signal (GC) and the first emission signal (EM1) may be about 3 V, and the high level or deactivation level may be about 7 V. Accordingly, the maximum voltage value required to turn on and off the transistors in the pixel driving circuit (PCij) may be reduced to about 7 V, and the voltage difference between the maximum voltage value and the minimum voltage value may be reduced to about 10 V. Since the power consumption is proportional to the square of the voltage difference between the maximum voltage value and the minimum voltage value, a pixel (PXij) with further reduced power consumption and a display device (DD, see FIG. 1) including the same may be provided.

[0150] Meanwhile, the high level and low level voltage values ​​of each signal may vary depending on the settings of the first and second power supplies (ELVDD, ELVSS), the reference voltage (Vref), and the first initialization voltage (Vcint), and may also vary depending on the settings of the threshold voltage (Vth) value of each transistor and the margin value for the threshold voltage (Vth) of each transistor.

[0151] Fig. 4 is a circuit diagram of a pixel (PXaij) according to an embodiment of the present invention. Fig. 5 is a timing diagram for explaining the operation of the pixel (PXaij) of Fig. 4 according to an embodiment of the present invention.

[0152] Referring to FIG. 4, a pixel (PXaij) may include a light-emitting element (LD) and a pixel driving circuit (PCaij). The pixel driving circuit (PCaij) may include first to sixth transistors (T1, T2, T3, T4a, T5, T6a) and capacitors (Cst, Chold).

[0153] The first transistor (T1) is an N-type transistor. According to one embodiment of the present invention, each of the second, third, and fifth transistors (T2, T3, T5) may be a P-type transistor, and each of the fourth and sixth transistors (T4a, T6a) may be an N-type transistor. That is, some of the switching transistors may be provided as P-type transistors, and the rest may be provided as N-type transistors.

[0154] Referring to FIGS. 4 and 5, any one frame section (FPa) may include first to fourth sections (t1, t2, t3, t4).

[0155] In the case of the scan signal (GW) provided to the gate electrode of the second transistor (T2), the active level may be a low level and the inactive level may be a high level. In the case of the compensation scan signal (GC) provided to the gate electrode of the third transistor (T3), the active level may be a low level and the inactive level may be a high level. In the case of the first emission signal (EM1) provided to the gate electrode of the fifth transistor (T5), the active level may be a low level and the inactive level may be a high level.

[0156] For the initialization scan signal (GRa) provided to the gate electrode of the fourth transistor (T4a), the active level may be a high level and the inactive level may be a low level. For the second emission signal (EM2a) provided to the gate electrode of the sixth transistor (T6a), the active level may be a high level and the inactive level may be a low level.

[0157] In the first period (t1), the initialization scan signal (GRa) and the second emission signal (EM2a) may be at active levels, and the compensation scan signal (GC), the first emission signal (EM1), and the scan signal (GW) may be at inactive levels. The active levels of each of the initialization scan signal (GRa) and the second emission signal (EM2a) may be at a high level. The inactive levels of each of the compensation scan signal (GC), the first emission signal (EM1), and the scan signal (GW) may be at a high level.

[0158] In the second period (t2), the compensation scan signal (GC), the initialization scan signal (GRa), and the first emission signal (EM1) may be at active levels, and the second emission signal (EM2a) and the scan signal (GW) may be at inactive levels. The active levels of each of the compensation scan signal (GC) and the first emission signal (EM1) may be at a low level, and the active level of the initialization scan signal (GRa) may be at a high level. The inactive level of the scan signal (GW) may be at a high level, and the inactive level of the second emission signal (EM2a) may be at a low level.

[0159] In the third period (t3), the scan signal (GW) may be at an active level, and the compensation scan signal (GC), the initialization scan signal (GRa), the first emission signal (EM1), and the second emission signal (EM2a) may be at inactive levels. The active level of the scan signal (GW) may be a low level. The inactive levels of each of the compensation scan signal (GC) and the first emission signal (EM1) may be a high level, and the inactive levels of each of the initialization scan signal (GRa) and the second emission signal (EM2a) may be a low level.

[0160] In the fourth period (t4), the first light emission signal (EM1) and the second light emission signal (EM2a) may be at active levels, and the compensation scan signal (GC), the initialization scan signal (GRa), and the scan signal (GW) may be at inactive levels. The active level of the first light emission signal (EM1) may be a low level, and the active level of the second light emission signal (EM2a) may be a high level. The inactive levels of each of the compensation scan signal (GC) and the scan signal (GW) may be a high level, and the inactive level of the initialization scan signal (GRa) may be a low level.

[0161] In one embodiment of the present invention, the voltage value of the first power supply (ELVDD) may be about 7 V, and the voltage value of the second power supply (ELVSS) may be about 0 V. The voltage value of the reference voltage (Vref) may be about 2.7 V. The voltage value of the first initialization voltage (Vcint) may be the same as the voltage value of the first power supply (ELVDD). The voltage value of the first initialization voltage (Vcint) may be about 7 V. The voltage value of the data signal (Vdata) may be about 2 V to about 7 V.

[0162] The low level or activation level of each of the compensation scan signal (GC) and the first emission signal (EM1) may be about 3 V, and the high level or deactivation level may be about 7 V. The turn-on voltage for turning on the third transistor (T3) and the fifth transistor (T5) may be about 3 V, and the turn-off voltage for turning off the third transistor (T3) and the fifth transistor (T5) may be about 7 V.

[0163] The low level or activation level of the scan signal (GW) may be -2 V, and the high level or deactivation level may be 7 V. The turn-on voltage for turning on the second transistor (T2) may be about -2 V, and the turn-off voltage for turning off the second transistor (T2) may be about 7 V.

[0164] The low level or deactivation level of the initialization scan signal (GRa) may be 0.7 V, and the high level or activation level may be 4.7 V. The turn-on voltage for turning on the fourth transistor (T4a) may be about 4.7 V, and the turn-off voltage for turning off the fourth transistor (T4a) may be about 0.7 V.

[0165] The low level or deactivation level of the second light emitting signal (EM2a) may be -2 V, and the high level or activation level may be 3 V. The turn-on voltage for turning on the sixth transistor (T6a) may be about 3 V, and the turn-off voltage for turning off the sixth transistor (T6a) may be about -2 V.

[0166] The maximum voltage value required to turn on and off the transistors in the pixel driver circuit (PCaij) may be about 7 V, and the minimum voltage value may be about -2 V. The maximum voltage value may be determined by the high level, that is, the deactivation level, of each of the compensation scan signal (GC) and the first emission signal (EM1), and the minimum voltage value may be determined by the low level, that is, the deactivation level, of the second emission signal (EM2a). The voltage difference between the maximum voltage value and the minimum voltage value may be about 9 V. When the first, fourth, and sixth transistors (T1, T4a, T6a) are provided as N-type and the second, third, and fifth transistors (T2, T3, T5) are provided as P-type, the voltage value of the first power supply (ELVDD) can be lowered compared to when all of the first to sixth transistors (T1, T2, T3, T4, T5, T6) are provided as N-type, and the maximum voltage value can be lowered without changing the minimum voltage value. Accordingly, the voltage difference between the maximum voltage value and the minimum voltage value can be further reduced, and a pixel (PXaij) with further reduced power consumption and a display device (DD, see FIG. 1) including the pixel can be provided.

[0167] Fig. 6 is a circuit diagram of a pixel (PXbij) according to one embodiment of the present invention. Fig. 7 is a timing diagram for explaining the operation of the pixel (PXbij) of Fig. 6 according to one embodiment of the present invention.

[0168] Referring to FIG. 6, a pixel (PXbij) may include a light-emitting element (LD) and a pixel driving circuit (PCbij). The pixel driving circuit (PCbij) may include first to sixth transistors (T1, T2a, T3, T4a, T5, T6a) and capacitors (Cst, Chold).

[0169] The first transistor (T1) is an N-type transistor. According to one embodiment of the present invention, each of the third and fifth transistors (T3, T5) may be a P-type transistor, and each of the second, fourth, and sixth transistors (T2a, T4a, T6a) may be an N-type transistor. That is, some of the switching transistors may be provided as P-type transistors, and the rest may be provided as N-type transistors.

[0170] For the compensation scan signal (GC) provided to the gate electrode of the third transistor (T3), the active level may be a low level and the inactive level may be a high level. For the first emission signal (EM1) provided to the gate electrode of the fifth transistor (T5), the active level may be a low level and the inactive level may be a high level.

[0171] In the case of the scan signal (GWa) provided to the gate electrode of the second transistor (T2a), the active level may be a high level and the inactive level may be a low level. In the case of the initialization scan signal (GRa) provided to the gate electrode of the fourth transistor (T4a), the active level may be a high level and the inactive level may be a low level. In the case of the second emission signal (EM2a) provided to the gate electrode of the sixth transistor (T6a), the active level may be a high level and the inactive level may be a low level.

[0172] In the first period (t1), the initialization scan signal (GRa) and the second emission signal (EM2a) may be at active levels, and the compensation scan signal (GC), the first emission signal (EM1), and the scan signal (GWa) may be at inactive levels. The active levels of each of the initialization scan signal (GRa) and the second emission signal (EM2a) may be at a high level. The inactive levels of each of the compensation scan signal (GC) and the first emission signal (EM1) may be at a high level, and the inactive level of the scan signal (GWa) may be at a low level.

[0173] In the second period (t2), the compensation scan signal (GC), the initialization scan signal (GRa), and the first emission signal (EM1) may be at active levels, and the second emission signal (EM2a) and the scan signal (GWa) may be at inactive levels. The active levels of each of the compensation scan signal (GC) and the first emission signal (EM1) may be at a low level, and the active level of the initialization scan signal (GRa) may be at a high level. The inactive levels of the scan signal (GWa) and the second emission signal (EM2a) may be at a low level.

[0174] In the third period (t3), the scan signal (GWa) may be at an active level, and the compensation scan signal (GC), the initialization scan signal (GRa), the first emission signal (EM1), and the second emission signal (EM2a) may be at inactive levels. The active level of the scan signal (GWa) may be a high level. The inactive levels of each of the compensation scan signal (GC) and the first emission signal (EM1) may be a high level, and the inactive levels of each of the initialization scan signal (GRa) and the second emission signal (EM2a) may be a low level.

[0175] In the fourth period (t4), the first light emission signal (EM1) and the second light emission signal (EM2a) may be at active levels, and the compensation scan signal (GC), the initialization scan signal (GRa), and the scan signal (GWa) may be at inactive levels. The active level of the first light emission signal (EM1) may be a low level, and the active level of the second light emission signal (EM2a) may be a high level. The inactive level of the compensation scan signal (GC) may be a high level, and the inactive levels of each of the initialization scan signal (GRa) and the scan signal (GWa) may be a low level.

[0176] In one embodiment of the present invention, the voltage value of the first power supply (ELVDD) may be about 7 V, and the voltage value of the second power supply (ELVSS) may be about 0 V. The voltage value of the reference voltage (Vref) may be about 2.7 V. The voltage value of the first initialization voltage (Vcint) may be the same as the voltage value of the first power supply (ELVDD). The voltage value of the first initialization voltage (Vcint) may be about 7 V. The voltage value of the data signal (Vdata) may be about 2 V to about 7 V. The Vth of the N-type transistor may be about 0 V, the Vth of the P-type transistor may be about -2 V, and the margin value for Vth may be set to about 2 V.

[0177] The low level or activation level of each of the compensation scan signal (GC) and the first emission signal (EM1) may be about 3 V, and the high level or deactivation level may be about 7 V. The turn-on voltage for turning on the third transistor (T3) and the fifth transistor (T5) may be about 3 V, and the turn-off voltage for turning off the third transistor (T3) and the fifth transistor (T5) may be about 7 V.

[0178] The low level or deactivation level of the scan signal (GWa) may be 0 V, and the high level or activation level may be 9 V. The turn-on voltage for turning on the second transistor (T2a) may be about 9 V, and the turn-off voltage for turning off the second transistor (T2a) may be about 0 V.

[0179] The low level or deactivation level of the initialization scan signal (GRa) may be 0.7 V, and the high level or activation level may be 4.7 V. The turn-on voltage for turning on the fourth transistor (T4a) may be about 4.7 V, and the turn-off voltage for turning off the fourth transistor (T4a) may be about 0.7 V.

[0180] The low level or deactivation level of the second light emitting signal (EM2a) may be -2 V, and the high level or activation level may be 3 V. The turn-on voltage for turning on the sixth transistor (T6a) may be about 3 V, and the turn-off voltage for turning off the sixth transistor (T6a) may be about -2 V.

[0181] The maximum voltage required to turn on and off the transistors in the pixel driver circuit (PCbij) may be about 9 V, and the minimum voltage may be about -2 V. The maximum voltage may be determined by the active level, which is a high level of the scan signal (GWa), and the minimum voltage may be determined by the inactive level, which is a low level of the second emission signal (EM2a). The voltage difference between the maximum voltage and the minimum voltage may be about 11 V. When the first, second, fourth, and sixth transistors (T1, T2, T4a, T6a) are provided as N-type and the third and fifth transistors (T2, T3, T5) are provided as P-type, the voltage value of the first power supply (ELVDD) can be lowered compared to when all of the first to sixth transistors (T1, T2, T3, T4, T5, T6) are provided as N-type, and the maximum voltage value can be lowered without changing the minimum voltage value. Accordingly, the voltage difference between the maximum voltage value and the minimum voltage value can be further reduced, and a pixel (PXbij) with further reduced power consumption and a display device (DD, see FIG. 1) including the same can be provided.

[0182] Fig. 8 is a circuit diagram of a pixel (PX-1ij) according to an embodiment of the present invention. Fig. 9 is a timing diagram for explaining the operation of the pixel (PX-1ij) of Fig. 8 according to an embodiment of the present invention.

[0183] Referring to FIG. 8, a pixel (PX-1ij) may include a light-emitting element (LD) and a pixel driving circuit (PC-1ij). The pixel driving circuit (PC-1ij) may include first to eighth transistors (T1, T2, T3, T4, T5-1, T6-1, T7, T8) and capacitors (Cst, Chold). That is, compared to the embodiment described above with reference to FIG. 2, the pixel driving circuit (PC-1ij) may further include a seventh transistor (T7) and an eighth transistor (T8). In the present specification, the eighth transistor (T8) may be referred to as a first initialization transistor, and the seventh transistor (T7) may be referred to as a second initialization transistor.

[0184] A pixel (PX-1ij) according to one embodiment of the present invention may be referred to as having an 8T2C structure.

[0185] The first transistor (T1) is an N-type transistor. In one embodiment of the present invention, at least one of the second to eighth transistors (T2, T3, T4, T5-1, T6-1, T7, T8) may be a P-type transistor. The remaining transistors (T2, T3, T4, T5-1, T6-1, T7, T8) excluding at least one of the second to eighth transistors (T2, T3, T4, T5-1, T6-1, T7, T8) may be N-type transistors. At least one of the second to sixth transistors (T2, T3, T4, T5-1, T6-1, T7, T8) may have a silicon semiconductor as a semiconductor layer, and the remaining transistors (T2, T3, T4, T5-1, T6-1, T7, T8) may have an oxide semiconductor as a semiconductor layer. For example, the silicon semiconductor may include amorphous silicon, low-temperature polycrystalline silicon (LTPS), crystalline silicon, etc. However, this is an example and the semiconductor layer of each transistor according to one embodiment is not limited.

[0186] According to one embodiment of the present invention, each of the second to sixth transistors (T2, T3, T4, T5-1, T6-1) and the eighth transistor (T8) may be a P-type transistor, and the seventh transistor (T7) may be an N-type transistor.

[0187] Each of the gate electrode of the fifth transistor (T5-1) and the gate electrode of the sixth transistor (T6-1) can be connected to an emission scan line (EMLi) that receives an emission signal (EM). That is, the gate electrode of the fifth transistor (T5-1) and the gate electrode of the sixth transistor (T6-1) can receive the same signal.

[0188] The seventh transistor (T7) may include a first electrode electrically connected to a second node (N2), a second electrode electrically connected to a second initialization voltage line (VL3) to which a second initialization voltage (Vint) is provided, and a gate electrode receiving an input scan signal (GI). The gate electrode of the seventh transistor (T7) may be connected to an input scan line (GILi).

[0189] The eighth transistor (T8) may include a first electrode connected to a first initialization voltage line (VL2) receiving a first initialization voltage (Vcint), a second electrode connected to the first electrode of the first transistor (T1), and a gate electrode receiving a compensation scan signal (GC). The gate electrode of the eighth transistor (T8) may be connected to a compensation scan line (GCLi).

[0190] For the emission signal (EM) provided to the gate electrode of each of the fifth and sixth transistors (T5-1, T6-1), the active level may be a low level and the inactive level may be a high level. For the input scan signal (GI) provided to the gate electrode of the seventh transistor (T7), the active level may be a high level and the inactive level may be a low level.

[0191] According to one embodiment of the present invention, the third and eighth transistors (T3, T8) electrically connected to the first initialization voltage line (VL2) to which the first initialization voltage (Vcint) is provided and the fifth transistor (T5) electrically connected to the first power line (PL1) to which the first power (ELVDD) is provided are provided as P-type transistors, so that the gate high voltages of each of the third, fifth, and eighth transistors (T3, T5, T8) can be set low. That is, the high levels of each of the compensation scan signal (GC) and the emission signal (EM) can be set low. The high level of the compensation scan signal (GC) can be 10 V or less. The high level of the emission signal (EM) can be 10 V or less. Accordingly, a pixel (PX-1ij) with improved power consumption and a display device (DD, see FIG. 1) including the same can be provided.

[0192] Referring to FIGS. 8 and 9, the display panel (DP, see FIG. 1) can display an image by operating in units of frame periods (FP-1). One frame period (FP-1) can include first to fourth periods (t1-1, t2-1, t3-1, t4-1). The first to third periods (t1-1, t2-1, t3-1) can be referred to as non-emitting periods, and the fourth period (t4-1) can be referred to as an emitting period.

[0193] In the first period (t1-1), the initialization scan signal (GR) and the input scan signal (GI) may be at active levels. The active level of the initialization scan signal (GR) may be a low level. The active level of the input scan signal (GI) may be a high level.

[0194] In the first period (t1-1), the compensation scan signal (GC), the emission signal (EM), and the scan signal (GW) may be at inactive levels. The inactive levels of each of the compensation scan signal (GC), the emission signal (EM), and the scan signal (GW) may be at a high level.

[0195] The fourth transistor (T4) can be turned on in response to an initialization scan signal (GR). A reference voltage (Vref) can be provided to the third node (N3) through the fourth transistor (T4).

[0196] During the first period (t1-1), the gate electrode of the first transistor (T1) can be initialized to the reference voltage (Vref). That is, the voltage of the third node (N3) can change from the data signal (Vdata) of the previous frame to the reference voltage (Vref).

[0197] The seventh transistor (T7) can be turned on in response to an input scan signal (GI). A second initialization voltage (Vint) can be provided to the second node (N2) through the seventh transistor (T7).

[0198] According to the present invention, the second initialization voltage (Vint) provided from the voltage generator (300, see FIG. 1) may not cause a voltage drop (IR drop). The second initialization voltage (Vint) may have a more stable voltage value than the second power supply (ELVSS). Accordingly, a pixel (PX-1ij) and a display device (DD, see FIG. 1) with improved reliability can be provided.

[0199] The voltage value of the second initialization voltage (Vint) may be less than the value obtained by subtracting the threshold voltage (Vth) of the first transistor (T1) from the reference voltage (Vref). For example, the voltage value of the second initialization voltage (Vint) may be equal to or lower than the voltage value of the second power supply (ELVSS).

[0200] The first interval (t1-1) may be referred to as an initialization interval.

[0201] In the second period (t2-1), the compensation scan signal (GC) and the initialization scan signal (GR) may be at an active level. The active level of each of the compensation scan signal (GC) and the initialization scan signal (GR) may be a low level.

[0202] In the second period (t2-1), the emission signal (EM), the input scan signal (GI), and the scan signal (GW) may be at inactive levels. The inactive levels of each of the emission signal (EM) and the scan signal (GW) may be at a high level. The inactive level of the input scan signal (GI) may be at a low level.

[0203] The fourth transistor (T4) can be turned on in response to an initialization scan signal (GR). A reference voltage (Vref) can be provided to the third node (N3) through the fourth transistor (T4).

[0204] The third transistor (T3) can be turned on in response to a compensation scan signal (GC). The eighth transistor (T8) can be turned on in response to an input scan signal (GI). The first transistor (T1) can be turned on in response to a reference voltage (Vref) provided to the gate electrode.

[0205] As the eighth transistor (T8) is turned on, the first transistor (T1) can operate as a source follower. A voltage (Vref-Vth) lower than the threshold voltage (referred to as Vth) of the first transistor (T1) than the reference voltage (Vref) can be provided to the second node (N2) corresponding to the source of the first transistor (T1). That is, a voltage of Vref-Vth can be provided to the source of the first transistor (T1).

[0206] A second capacitor (Chold) may be connected to a second node (N2). One electrode of the second capacitor (Chold) may be connected to a second power line (PL2) supplied with a second power source (ELVSS), and the other electrode of the second capacitor (Chold) may be connected to a second node (N2). The second capacitor (Chold) may store a charge corresponding to a voltage difference ((Vref-Vth)-ELVSS) between the second power source (ELVSS) and the second node (N2). The second capacitor (Chold) may be referred to as a hold capacitor. The second capacitor (Chold) may have a higher storage capacity compared to the first capacitor (Cst). The second capacitor (Chold) may minimize a voltage change of the second node (N2) in response to a voltage change of the third node (N3).

[0207] The second interval (t2-1) may be referred to as the compensation interval.

[0208] In the third period (t3-1), the scan signal (GW) may be at an active level. The active level of the scan signal (GW) may be a low level.

[0209] In the third period (t3-1), the compensation scan signal (GC), the initialization scan signal (GR), the emission signal (EM), and the input scan signal (GI) may be at inactive levels. The inactive levels of each of the compensation scan signal (GC), the initialization scan signal (GR), and the emission signal (EM) may be at a high level. The inactive level of the input scan signal (GI) may be at a low level.

[0210] The second transistor (T2) can be turned on in response to a scan signal (GW). The data signal (Vdata) provided through the data line (DLj) can be provided to the third node (N3). The voltage level of the other end of the first capacitor (Cst), i.e., the second node (N2), can be a voltage level of Vref-Vth. The first capacitor (Cst) can store a charge corresponding to the voltage difference (Vdata-(Vref-Vth)) between the third node (N3) and the second node (N2).

[0211] The third section (t3-1) may be referred to as a write section.

[0212] In the fourth section (t4-1), the light emission signal (EM) may be at an active level. The active level of the light emission signal (EM) may be a low level.

[0213] In the fourth period (t4-1), the compensation scan signal (GC), the initialization scan signal (GR), the input scan signal (GI), and the scan signal (GW) may be at inactive levels. The inactive levels of each of the compensation scan signal (GC), the initialization scan signal (GR), and the scan signal (GW) may be at a high level. The inactive level of the input scan signal (GI) may be at a low level.

[0214] The fifth transistor (T5) and the sixth transistor (T6) can be turned on in response to the light emitting signal (EM). A driving current (Id) can flow to the second power supply (ELVSS) via the first power supply line (PL1), the light emitting element (LD), the fifth transistor (T5), the first transistor (T1), the sixth transistor (T6), and the second power supply line (PL2). The voltage value of the second power supply (ELVSS) can be lower than a value obtained by subtracting the threshold voltage (Vth) of the first transistor (T1) from the reference voltage (Vref).

[0215] According to the present invention, the threshold voltage (Vth) of the first transistor (T1) may not affect the driving current (Id) flowing through the light-emitting element (LD) through the first to fourth steps (t1-1, t2-1, t3-1, t4-1). Accordingly, the brightness of the image output from the display panel (DP, see Fig. 1) may be maintained uniformly. Accordingly, a pixel (PX-1ij) and a display device (DD, see Fig. 1) with improved display quality may be provided.

[0216] According to the present invention, the second power supply (ELVSS) may not affect the driving current (Id) flowing through the light emitting element (LD) through the first to fourth steps (t1-1, t2-1, t3-1, t4-1). Accordingly, the brightness of the image output from the display panel (DP, see Fig. 1) may be maintained uniformly. Accordingly, a pixel (PX-1ij) and a display device (DD, see Fig. 1) with improved display quality may be provided.

[0217] The fourth section (t4-1) may be referred to as the luminous section.

[0218] In one embodiment of the present invention, the voltage value of the first power supply (ELVDD) may be about 8.4 V, and the voltage value of the second power supply (ELVSS) may be about 0 V. The voltage value of the reference voltage (Vref) may be about 2.7 V. The voltage value of the first initialization voltage (Vcint) may be the same as the voltage value of the first power supply (ELVDD). The voltage value of the first initialization voltage (Vcint) may be about 8.4 V. The voltage value of the second initialization voltage (Vint) may be about -3 V.

[0219] The maximum voltage required to turn on and off the transistors in the pixel driver circuit (PC-1ij) may be about 10 V, and the minimum voltage may be about -6 V. The voltage difference between the maximum voltage and the minimum voltage may be about 16 V. The maximum voltage may be determined by the deactivation level, which is a high level of each of the compensation scan signal (GC) and the emission signal (EM). The minimum voltage may be determined by the deactivation level, which is a low level of the seventh transistor (T7).

[0220] In contrast to the present invention, when all of the first to eighth transistors (T1, T2, T3, T4, T5-1, T6-1, T7, and T8) are provided as N-type, the active level of each of the compensation scan signal (GC), the initialization scan signal (GR), the emission signal (EM), the input scan signal (GI), and the scan signal (GW) may be a high level, and the inactive level may be a low level. In addition, the turn-on voltage for turning on each of the second to eighth transistors (T2, T3, T4, T5-1, T6-1, T7, and T8) may correspond to the high level of the corresponding signal. In this case, the maximum voltage value required for turning on and off the transistors in the pixel driving circuit (PC-1ij) may be about 15 V, and the minimum voltage value may be about -6 V. The voltage difference between the maximum voltage value and the minimum voltage value may be about 18 V. The maximum voltage value can be determined by the activation level, which is a high level of each of the compensation scan signal (GC) and the emission signal (EM). The minimum voltage value can be determined by the deactivation level, which is a low level of the seventh transistor (T7).

[0221] That is, according to one embodiment of the present invention, by providing the third, fifth, and eighth transistors (T3, T5-1, T8) as P-type, the gate high voltage can be lowered compared to the case where the third, fifth, and eighth transistors (T3, T5-1, T8) are provided as N-type. That is, the high level of each of the compensation scan signal (GC) and the emission signal (EM) can be lowered, and the minimum voltage value required to turn on and off the transistors in the pixel driving circuit (PC-1ij) can be lowered. Through this, the voltage difference between the maximum voltage value and the minimum voltage value can be reduced, and a pixel (PX-1ij) with reduced power consumption and a display device (DD, see FIG. 1) including the same can be provided.

[0222] Meanwhile, when the second to sixth transistors (T2, T3, T4, T5-1, T6-1) and the eighth transistor (T8) are provided as P-type, the gate low voltage may also be lowered compared to when the second to sixth transistors (T2, T3, T4, T5-1, T6-1) and the eighth transistor (T8) are provided as N-type. However, when the second to sixth transistors (T2, T3, T4, T5-1, T6-1) and the eighth transistor (T8) are provided as P-type, the degree to which the gate low voltage is lowered may be less compared to the degree to which the gate high voltage is lowered. Accordingly, the voltage difference between the gate high voltage and the gate low voltage of the second to sixth transistors (T2, T3, T4, T5-1, T6-1) and the eighth transistor (T8) can be reduced, and the power consumption for the second to sixth transistors (T2, T3, T4, T5-1, T6-1) and the eighth transistor (T8) can be reduced.

[0223] Additionally, according to one embodiment of the present invention, when the second, third, fifth to eighth transistors (T3, T5-1, T6-1, T8) are provided as a P-type compared to when they are provided as an N-type, the first power supply (ELVDD) can be driven even if it has a relatively low voltage value. In one embodiment, the voltage value of the first power supply (ELVDD) can be lower than 8.4 V. Accordingly, the high level voltage values ​​of each of the compensation scan signal (GC) and the emission signal (EM) can also be set low, and the maximum voltage value required to turn on and off the transistors in the pixel driving circuit (PC-1ij) can also be set low. Through this, a pixel (PX-1ij) with further reduced power consumption and a display device (DD, see FIG. 1) including the same can be provided.

[0224] Fig. 10 is a circuit diagram of a pixel (PX-1aij) according to an embodiment of the present invention. Fig. 11 is a timing diagram for explaining the operation of the pixel (PX-1aij) of Fig. 10 according to an embodiment of the present invention.

[0225] Referring to FIG. 10, a pixel (PX-1aij) may include a light emitting element (LD) and a pixel driving circuit (PC-1aij). The pixel driving circuit (PC-1aij) may include first to eighth transistors (T1, T2a, T3, T4a, T5-1, T6-1, T7, T8) and capacitors (Cst, Chold).

[0226] The first transistor (T1) is an N-type transistor. According to one embodiment of the present invention, each of the third, fifth, sixth, and eighth transistors (T3, T5-1, T6-1, T8) may be a P-type transistor, and each of the second, fourth, and seventh transistors (T2a, T4a, T7) may be an N-type transistor.

[0227] Referring to FIGS. 10 and 11, any one frame section (FP-1a) may include first to fourth sections (t1-1, t2-1, t3-1, t4-1).

[0228] For the compensation scan signal (GC) provided to the gate electrodes of each of the third transistor (T3) and the eighth transistor (T8), the active level may be a low level and the inactive level may be a high level. For the emission signal (EM) provided to the gate electrodes of each of the fifth transistor (T5-1) and the sixth transistor (T6-1), the active level may be a low level and the inactive level may be a high level.

[0229] In the case of the scan signal (GWa) provided to the gate electrode of the second transistor (T2a), the active level may be a high level and the inactive level may be a low level. In the case of the initialization scan signal (GRa) provided to the gate electrode of the fourth transistor (T4a), the active level may be a high level and the inactive level may be a low level. In the case of the input scan signal (GI) provided to the gate electrode of the seventh transistor (T7), the active level may be a high level and the inactive level may be a low level.

[0230] In the first period (t1-1), the initialization scan signal (GRa) and the input scan signal (GI) may be at active levels, and the compensation scan signal (GC), the emission signal (EM), and the scan signal (GWa) may be at inactive levels. The active levels of each of the initialization scan signal (GRa) and the input scan signal (GI) may be at a high level. The inactive levels of each of the compensation scan signal (GC) and the emission signal (EM) may be at a high level, and the inactive level of the scan signal (GWa) may be at a low level.

[0231] In the second period (t2-1), the compensation scan signal (GC) and the initialization scan signal (GRa) may be at active levels, and the light emission signal (EM), the input scan signal (GI), and the scan signal (GWa) may be at inactive levels. The active level of the compensation scan signal (GC) may be a low level, and the active level of the initialization scan signal (GRa) may be a high level. The inactive level of the light emission signal (EM) may be a high level, and the inactive levels of each of the input scan signal (GI) and the scan signal (GWa) may be a low level.

[0232] In the third period (t3-1), the scan signal (GWa) may be at an active level, and the compensation scan signal (GC), the initialization scan signal (GRa), the emission signal (EM), and the input scan signal (GI) may be at inactive levels. The active level of the scan signal (GWa) may be a high level. The inactive levels of each of the compensation scan signal (GC) and the emission signal (EM) may be a high level, and the inactive levels of each of the initialization scan signal (GRa) and the input scan signal (GI) may be a low level.

[0233] In the fourth period (t4-1), the emission signal (EM) may be at an active level, and the compensation scan signal (GC), the initialization scan signal (GRa), the input scan signal (GI), and the scan signal (GWa) may be at inactive levels. The active level of the emission signal (EM) may be a low level. The inactive level of the compensation scan signal (GC) may be a high level, and the inactive levels of each of the initialization scan signal (GRa), the input scan signal (GI), and the scan signal (GWa) may be a low level.

[0234] According to the present embodiment, by providing the third, fifth, and eighth transistors (T3, T5-1, T8) as P-type, the turn-on voltage for turning on each of the third, fifth, and eighth transistors (T3, T5-1, T8) can be lowered, thereby reducing the voltage difference between the maximum voltage value and the minimum voltage value. Additionally, according to one embodiment of the present invention, since the first power supply (ELVDD) can be driven even if it has a relatively low voltage value, the first power supply (ELVDD) can be set low. Through this, the turn-on voltage for turning on each of the third, fifth, and eighth transistors (T3, T5-1, T8) can be further lowered. Therefore, a pixel (PX-1aij) with reduced power consumption and a display device (DD, see FIG. 1) including the same can be provided.

[0235] FIGS. 12A and 12B are schematic plan views illustrating a display panel according to one embodiment of the present invention. Some components are omitted in each of FIGS. 12A and 12B. The present invention will now be described with reference to FIGS. 12A and 12B.

[0236] Referring to FIG. 12A, a display panel (DP) of one embodiment may be divided into a display area (DA) and a peripheral area (or non-display area, NDA). The display area (DA) may include a plurality of light-emitting units (EP).

[0237] The light-emitting portions (EP) may be regions that are each illuminated by pixels (PX, see FIG. 1). Specifically, each of the light-emitting portions (EP) may correspond to a light-emitting aperture (OP-PDL, see FIG. 14) described below. The light-emitting aperture (OP-PDL) may be referred to as an aperture or an opening.

[0238] The peripheral area (NDA) may be positioned adjacent to the display area (DA). In the present embodiment, the peripheral area (NDA) is illustrated as a shape surrounding the edge of the display area (DA). However, this is merely an example, and the peripheral area (NDA) may be positioned on one side of the display area (DA), or may be omitted, and is not limited to any one embodiment.

[0239] In the present embodiment, a scan driver (SDC) and a data driver (DDC) may be mounted on a display panel (DP). In one embodiment, the scan driver (SDC) may be disposed in a display area (DA), and the data driver (DDC) may be disposed in a peripheral area (NDA). The scan driver (SDC) may overlap at least some of a plurality of light-emitting units (EP) disposed in the display area (DA) on a plane. Since the scan driver (SDC) is disposed in the display area (DA), the area of ​​the peripheral area (NDA) may be reduced compared to a conventional display panel in which the scan driver is disposed in the peripheral area, and a display device with a thin bezel may be easily implemented.

[0240] Meanwhile, unlike the one illustrated in FIG. 12A, the scan driver (SDC) may be provided in two distinct parts. The two scan drivers (SDC) may be positioned spaced apart from each other on the left and right with the center of the display area (DA) interposed therebetween. Alternatively, the scan drivers (SDC) may be provided in a greater number, such as two or more, and are not limited to any one embodiment.

[0241] Meanwhile, Fig. 12a illustrates an example of a display panel, and a data driver (DDC) may be arranged in a display area (DA). In this case, some of the light-emitting units (EP) arranged in the display area (DA) may overlap with the data driver (DDC) on a plane.

[0242] In one embodiment, the data driver (DDC) may be provided in the form of a separate driver chip independent from the display panel (DP) and connected to the display panel (DP). However, this is merely an example, and the data driver (DDC) may be formed in the same process as the scan driver (SDC) to form the display panel (DP), and is not limited to any one embodiment.

[0243] As illustrated in FIG. 12B, the display panel (DP) may have a form in which a length corresponding to the first direction (DR1) is longer than a length corresponding to the second direction (DR2). A plurality of pixels (PX11 to PXnm) arranged in n rows and m columns are exemplarily illustrated in the display area (DA). In the present embodiment, the display panel (DP) may include a plurality of scan drivers (SDC1, SDC2). The scan drivers (SDC1, SDC2) are exemplarily illustrated as including a first scan driver (SDC1) and a second scan driver (SDC2) that are spaced apart from each other in the first direction (DR1).

[0244] The first scan driver (SDC1) may be connected to some of the scan lines (GL1 to GLn), and the second scan driver (SDC2) may be connected to other some of the scan lines (GL1 to GLn). For example, the first scan driver (SDC1) may be connected to odd-numbered scan lines among the scan lines (GL1 to GLn), and the second scan driver (SDC2) may be connected to even-numbered scan lines among the scan lines (GL1 to GLn).

[0245] For ease of explanation, pads (PD) of data lines (DL1 to DLm) are illustrated in Fig. 12b. The pads (PD) may be defined at the ends of the data lines (DL1 to DLm). The data lines (DL1 to DLm) may be connected to a data driver (DDC, see Fig. 12a) through the pads (PD).

[0246] According to the present invention, the pads (PD) may be arranged in a divided manner at positions spaced apart from each other with the display area (DA) in the peripheral area (NDA). For example, some of the pads (PD) may be arranged on the upper side, that is, on the side adjacent to the first scan line (GL1) among the scan lines (GL1 to GLn), and other of the pads (PD) may be arranged on the lower side, that is, on the side adjacent to the last scan line (GLn) among the scan lines (GL1 to GLn). In the present embodiment, the pads (PD) connected to odd-numbered data lines among the data lines (DL1 to DLm) may be arranged on the upper side, and the pads (PD) connected to even-numbered data lines among the data lines (DL1 to DLm) may be arranged on the lower side.

[0247] Although not shown, the display panel (DP) may include a plurality of upper data drivers connected to pads (PD) arranged on the upper side and / or a plurality of lower data drivers connected to pads (PD) arranged on the lower side. However, this is described by way of example, and the display panel (DP) may include one upper data driver connected to pads (PD) arranged on the upper side and / or one lower data driver connected to pads (PD) arranged on the lower side. The pads (PD) according to one embodiment of the present invention may be arranged on only one side of the display panel (DP) and connected to a single data driver, and are not limited to any one embodiment.

[0248] In addition, as described above in FIG. 12a, the display panel (DP) in FIG. 12b may also have a scan driver and / or a data driver disposed in the display area (DA), and accordingly, some of the light emitting units disposed in the display area (DA) may overlap with the scan driver and / or the data driver on a plane.

[0249] FIGS. 13A to 13D are enlarged plan views of a portion of a display panel according to one embodiment of the present invention.

[0250] In Fig. 13a, light emitting units (UT11, UT12, UT21, UT22) of two rows and two columns are exemplarily illustrated. Referring to Fig. 13a, the light emitting units of the first row (Rk) include light emitting units constituting the first row, first column light emitting unit (UT11) and the first row, second column light emitting unit (UT12), and the light emitting units of the second row (Rk+1) include light emitting units constituting the second row, first column light emitting unit (UT21) and the second row, second column light emitting unit (UT22).

[0251] Each of the light-emitting parts (EP1, EP2, EP3) may correspond to a light-emitting opening (OP-PDL, see FIG. 14) described below. That is, each of the light-emitting parts (EP1, EP2, EP3) may be an area where light is emitted by the light-emitting element described above. The light-emitting parts (EP1, EP2, EP3) may correspond to a unit that constitutes an image displayed on a display panel (DP, see FIG. 1). More specifically, each of the light-emitting parts (EP1, EP2, EP3) may correspond to an area defined by the light-emitting opening (OP-PDL) described below, particularly, an area defined by a lower surface of the light-emitting opening (OP-PDL).

[0252] The light emitting units (EP1, EP2, EP3) may include a first light emitting unit (EP1), a second light emitting unit (EP2), and a third light emitting unit (EP3). The first light emitting unit (EP1), the second light emitting unit (EP2), and the third light emitting unit (EP3) may emit lights of different colors. For example, the first light emitting unit (EP1) may emit red light, the second light emitting unit (EP2) may emit green light, and the third light emitting unit (EP3) may emit blue light, but the color combination is not limited thereto. In addition, at least two of each of the first to third light emitting units (EP1, EP2, EP3) may emit light of the same color. For example, all of the first to third light emitting units (EP1, EP2, EP3) may emit blue light, or all of them may emit white light.

[0253] Among the first to third light-emitting units (EP1, EP2, EP3), the third light-emitting unit (EP3) that displays light emitted by the third light-emitting element may include two sub-light-emitting units (EP31, EP32) spaced apart from each other in the second direction (DR2). However, this is merely an example, and the third light-emitting unit (EP3) may be provided as a single pattern having an integral shape like the first and second light-emitting units (EP1, EP2), or at least one of the first and second light-emitting units (EP1, EP2) may include spaced apart sub-light-emitting units, and is not limited to any one embodiment.

[0254] The first row (Rk) light emitting units may include first to third light emitting units (EP1, EP2, EP3) constituting the first row, first column light emitting unit (UT11) and first to third light emitting units (EP1, EP2, EP3a) constituting the first row, second column light emitting unit (UT12), and the second row (Rk+1) light emitting units may include first to third light emitting units (EP1, EP2, EP3a) constituting the second row, first column light emitting unit (UT21) and first to third light emitting units (EP1, EP2, EP3) constituting the second row, second column light emitting unit (UT22).

[0255] In one embodiment of the present invention, the shapes of the light emitting parts constituting the first row, first column light emitting unit (UT11) and the shapes of the light emitting parts constituting the second row, second column light emitting unit (UT22) may be substantially the same. In addition, the shapes of the light emitting parts constituting the first row, second column light emitting unit (UT12) and the shapes of the light emitting parts constituting the second row, first column light emitting unit (UT21) may be substantially the same. The shapes of the light emitting parts constituting the first row, first column light emitting unit (UT11) may be different from the shapes of the light emitting parts constituting the first row, second column light emitting unit (UT12). For example, some of the light emitting parts of the first row (Rk) and some of the light emitting parts of the second row (Rk+1) may have symmetrical shapes.

[0256] In one embodiment of the present invention, the third light-emitting unit (EP3a) of the second row, first column light-emitting unit (UT21) and the third light-emitting unit (EP3) of the first row, first column light-emitting unit (UT11) may have a shape and arrangement that are line-symmetrical with respect to an axis parallel to the first direction (DR1), and the third light-emitting unit (EP3) of the second row, second column light-emitting unit (UT22) and the third light-emitting unit (EP3a) of the first row, second column light-emitting unit (UT12) may have a shape and arrangement that are line-symmetrical with respect to an axis parallel to the first direction (DR1). However, this is exemplary and is not limited thereto.

[0257] Fig. 13b illustrates light emitting units arranged in a row. For ease of explanation, Fig. 13b illustrates a plurality of second electrodes (EL2_1, EL2_2, EL2_3), a plurality of pixel drivers (PDC1, PDC2, PDC3), first to third connection electrodes (CNE1, CNE2, CNE3), and a separator (SPR). Fig. 13c illustrates a separator (SPR), a plurality of light emitting units (EP1, EP2, EP3) arranged within an area partitioned by the separator (SPR), and a plurality of connection electrodes (CNE1, CNE2, CNE3) among the components of the display panel. As an example of the present invention, the separator (SPR) may be a structural element (e.g., an insulator) that spatially defines and separates light emitting units between pixels or adjacent pixels. A separator (SPR) can be used as a bank or pixel definition layer formed between light-emitting portions to prevent mixing of materials during deposition and to guide the formation of an organic light-emitting layer to maintain uniform alignment of electrodes.

[0258] Referring to FIGS. 13b and 13c, the second electrodes (EL2_1, EL2_2, EL2_3) can be electrically disconnected by being separated from each other by a separator (SPR). In the present embodiment, one light emitting unit (UT11) can include three light emitting parts (EP1, EP2, EP3). Accordingly, the light emitting unit (UT11) can include three second electrodes (EL2_1, EL2_2, EL2_3, hereinafter referred to as first to third cathodes), three pixel driving parts (PDC1, PDC2, PDC3), and three connection electrodes (CNE1, CNE2, CNE3). However, this is merely an example, and the number and arrangement of the light emitting parts included in the light emitting unit (UT11) can be designed in various ways and are not limited to any one embodiment.

[0259] Each of the first to third pixel driving units (PDC1, PDC2, PDC3) is electrically connected to each of the first to third light-emitting elements (LD1, LD2, LD3) including the first to third light-emitting units (EP1, EP2, EP3). In this specification, “connected” includes not only cases where they are connected by direct physical contact but also cases where they are electrically connected.

[0260] In addition, as in FIG. 13b, each area where the first to third pixel driving units (PDC1, PDC2, PDC3) are defined on a plane may correspond to a unit in which transistor and capacitor elements constituting a circuit (PDC, see FIG. 14) for driving a light-emitting element of a pixel are repeatedly arranged. According to the present invention, each of the first to third pixel driving units (PDC1, PDC2, PDC3) may have a structure of any one of the pixel driving circuits (PCij, PCaij, PCbij, PC-1ij, PC-1aij) described above with reference to FIGS. 2 to 11.

[0261] The first to third pixel driving units (PDC1, PDC2, PDC3) can be sequentially arranged along the first direction (DR1). Meanwhile, the arrangement positions of the first to third pixel driving units (PDC1, PDC2, PDC3) can be designed independently regardless of the positions or shapes of the first to third light-emitting units (EP1, EP2, EP3).

[0262] For example, the first to third pixel driving units (PDC1, PDC2, PDC3) may be arranged in a region defined by the separator (SPR), that is, in a position different from the positions where the first to third cathodes (EL2_1, EL2_2, EL2_3) are arranged, or may be designed to have a shape and area different from the shapes of the first to third cathodes (EL2_1, EL2_2, EL2_3). Alternatively, the first to third pixel driving units (PDC1, PDC2, PDC3) may be arranged to overlap the positions where the first to third light-emitting units (EP1, EP2, EP3) exist, and may be designed to have a shape having an area similar to the first to third cathodes (EL2_1, EL2_2, EL2_3) in a region defined by the separator (SPR).

[0263] In this embodiment, each of the first to third pixel driving units (PDC1, PDC2, PDC3) is illustrated as a rectangular shape, each of the first to third light emitting units (EP1, EP2, EP3) is arranged in a smaller area and a different shape, and the first to third cathodes (EL2_1, EL2_2, EL2_3) are arranged in a position overlapping the first to third light emitting units (EP1, EP2, EP3), but are illustrated as an irregular shape.

[0264] Accordingly, as illustrated in FIG. 13b, the first pixel driver (PDC1) may be positioned at a position partially overlapping the first light-emitting unit (EP1), the second light-emitting unit (EP2), and other adjacent light-emitting units. The second pixel driver (PDC2) may be positioned at a position overlapping the first light-emitting unit (EP1), the second light-emitting unit (EP2), and the third cathode (EL2_3). The third pixel driver (PDC3) may be positioned at a position overlapping the third light-emitting unit (EP3). However, this is merely an example, and the positions of the first to third pixel drivers (PDC1, PDC2, PDC3) may be designed in various shapes and arrangements independently from the first to third light-emitting units (EP1, EP2, EP3) and are not limited to any one embodiment.

[0265] The light emitting unit (UT11) may include first to third connection electrodes (CNE1, CNE2, CNE3). The first connection electrode (CNE1) may electrically connect a first light emitting element (LD1) forming a first light emitting portion (EP1) (or a first light emitting portion (EP1) is defined) and a first pixel driver (PDC1), the second connection electrode (CNE2) may electrically connect a second light emitting element (LD2) forming a second light emitting portion (EP2) and a second pixel driver (PDC2), and the third connection electrode (CNE3) may electrically connect a third light emitting element (LD3) forming a third light emitting portion (EP3) and a third pixel driver (PDC3).

[0266] Specifically, the first to third connection electrodes (CNE1, CNE2, CNE3) can electrically connect the first to third cathodes (EL2_1, EL2_2, EL2_3) and the first to third pixel drivers (PDC1, PDC2, PDC3) in a one-to-one correspondence, respectively.

[0267] Each of the first to third connection electrodes (CNE1, CNE2, CNE3) may be disposed on a pixel defining layer (PDL, see FIG. 14) to be described later. Each of the first to third connection electrodes (CNE1, CNE2, CNE3) may have a ring shape or a square shape surrounding the corresponding first to third light-emitting parts (EP1, EP2, EP3). In one embodiment of the present invention, it is illustrated as an example that each of the first to third connection electrodes (CNE1, CNE2, CNE3) has a closed-loop shape (e.g., a ring, a square, a polygon, or an irregular shape), but the present invention is not limited thereto. For example, at least some of the first to third connection electrodes (CNE1, CNE2, CNE3) may have an open-loop shape in which a portion is disconnected.

[0268] Since the first to third connection electrodes (CNE1, CNE2, CNE3) have an open loop shape, the degree of freedom of the positions at which the first to third connection electrodes (CNE1, CNE2, CNE3) and the first to third pixel drivers (PDC1, PDC2, PDC3) are connected can be improved. For example, the first connection electrode (CNE1) can be connected to the first pixel driver (PDC1) through the first connection portion (CE1), the second connection electrode (CNE2) can be connected to the second pixel driver (PDC2) through the second connection portion (CE2), and the third connection electrode (CNE3) can be connected to the third pixel driver (PDC3) through the connection wire (CN3). That is, connection wires additionally connected to the first and second connection electrodes (CNE1, CNE2) can be omitted.

[0269] A single connecting wire (CN3) can electrically connect a third light-emitting element (LD3) constituting a third pixel driver (PDC3) and a third light-emitting element (EP3). Specifically, the connecting wire (CN3) can correspond to a node where a light-emitting element (LD, see FIG. 2) is connected to a pixel driver (or pixel driver circuit (PCij, see FIG. 2)).

[0270] The connecting wire (CN3) may include a third connection portion (CE3) and a driving connection portion (CD3). The third connection portion (CE3) may be provided on one side of the connecting wire (CN3), and the driving connection portion (CD3) may be provided on the other side of the connecting wire (CN3).

[0271] The driving connection part (CD3) may be a portion of the connection line (CN3) that is connected to the pixel driver (PDC3). In the present embodiment, the driving connection part (CD3) may be connected to one electrode of a transistor constituting the pixel driver (PDC3). Specifically, the driving connection part (CD3) may be connected to the drain of the fifth transistor (T5) illustrated in FIG. 2 or the drain of the fifth transistor (T5-1) illustrated in FIG. 8. Accordingly, the position of the driving connection part (CD3) may correspond to the position of the transistor physically connected to the connection line (CN3) among the pixel drivers. The third connection part (CE3) may be a portion of the connection line (CN3) that is connected to the third light-emitting element (LD3). In the present embodiment, the third connection part (CE3) may be connected to the third connection electrode (CNE3).

[0272] The first connection electrode (CNE1) may include a first edge (EG11) surrounding at least a portion of the first light-emitting portion (EP1) and a second edge (EG12) surrounding the first edge (EG11). The second connection electrode (CNE2) may include a first edge (EG21) surrounding at least a portion of the second light-emitting portion (EP2) and a second edge (EG22) surrounding the first edge (EG21). The third connection electrode (CNE3) may include a first edge (EG31) surrounding at least a portion of the third light-emitting portion (EP3) and a second edge (EG32) surrounding the first edge (EG31).

[0273] The first to third connecting electrodes (CNE1, CNE2, CNE3) may be arranged to be spaced apart from each other. For example, gaps (GP1, GP2, GP3) between a plurality of adjacent connecting electrodes among the first to third connecting electrodes (CNE1, CNE2, CNE3) may overlap with the separator (SPR). For example, first edges (EG11, EG21, EG31) of the first to third connecting electrodes (CNE1, CNE2, CNE3) may not be covered by the separator (SPR), and second edges (EG12, EG22, EG32) of the first to third connecting electrodes (CNE1, CNE2, CNE3) may overlap with the separator (SPR). Alternatively, the second edges (EG12, EG22, EG32) of the first to third connecting electrodes (CNE1, CNE2, CNE3) may be covered by a separator (SPR).

[0274] In one embodiment of the present invention, the first to third connecting portions (CE1, CE2, CE3) may be arranged at positions that do not overlap with the first to third light-emitting portions (EP1, EP2, EP3) on a plane. For example, a light-emitting opening (OP-PDL, see FIG. 14) and through holes (OP-P, see FIG. 14) spaced apart from the light-emitting opening (OP-PDL) may be defined in the pixel defining layer (PDL).

[0275] The through holes (OP-P) may include a first through hole (OP-P1), a second through hole (OP-P2), and a third through hole (OP-P3). The first to third connecting portions (CE1, CE2, CE3) may be arranged to correspond to the first to third through holes (OP-P1, OP-P2, OP-P3), respectively. The light-emitting opening (OP-PDL) may include a first light-emitting opening (OP-PDL1), a second light-emitting opening (OP-PDL2), and a third light-emitting opening (OP-PDL3). The first to third light-emitting portions (EP1, EP2, EP3) may be defined to correspond to the first to third light-emitting openings (OP-PDL1, OP-PDL2, OP-PDL3), respectively. Accordingly, the first to third connecting portions (CE1, CE2, CE3) can be positioned at a position spaced apart from the first to third light-emitting portions (EP1, EP2, EP3).

[0276] The first to third connection electrodes (CNE1, CNE2, CNE3) may be arranged on a pixel defining layer (PDL, see FIG. 14). When viewed in a plan view, the first connection electrode (CNE1) may surround the first light-emitting opening (OP-PDL1), the second connection electrode (CNE2) may surround the second light-emitting opening (OP-PDL2), and the third connection electrode (CNE3) may surround the third light-emitting openings (OP-PDL3).

[0277] According to one embodiment of the present invention, the driving connection portion (CD3), which is a position where the connection wiring (CN3) connects to the transistor (TR, see FIG. 14) of the third pixel driver (PDC3), may be defined at a position that does not overlap with the third connection portion (CE3) on a plane and may be disposed at a position that overlaps with the third light-emitting portion (EP3). For example, the driving connection portion (CD3), which is a position where the connection wiring (CN3) connects to the transistor (TR, see FIG. 14) of the third pixel driver (PDC3), may be defined at a position that overlaps with the third light-emitting portion (EP3) on a plane and may be disposed at a distance from the third connection portion (CE3). For example, the connection wiring (CN3) may correspond to the connection wiring (CN-ad) illustrated in FIG. 16, the driving connection portion (CD3) may correspond to a portion in contact with the intermediate connection electrode (CN) illustrated in FIG. 16, and the third connection portion (CE3) may correspond to a portion in contact with the connection electrode (CNEa) illustrated in FIG. 16. By connecting the third cathode (EL2_3) and the pixel driver (PDC3) through the connection wiring (CN3), restrictions on the position or shape of the third light-emitting portion (EP3) in the design of the pixel driver (PDC3) may be reduced, thereby improving the degree of freedom in design.

[0278] The first to third cathodes (EL2_1, EL2_2, EL2_3) can be connected to the first to third connection electrodes (CNE1, CNE2, CNE3). For example, the lower surfaces of the first to third cathodes (EL2_1, EL2_2, EL2_3) can be connected (or in contact) with the upper surfaces of the first to third connection electrodes (CNE1, CNE2, CNE3), respectively. Accordingly, the contact reliability (or connection stability) of the first to third cathodes (EL2_1, EL2_2, EL2_3) and the first to third connection electrodes (CNE1, CNE2, CNE3) can be further improved.

[0279] Additionally, the connection regions where the first to third cathodes (EL2_1, EL2_2, EL2_3) and the first to third connection electrodes (CNE1, CNE2, CNE3) are connected may surround at least a portion of each of the first to third light-emitting openings (OP-PDL1, OP-PDL2, OP-PDL3). The first to third cathodes (EL2_1, EL2_2, EL2_R) and the first to third connection electrodes (CNE1, CNE2, CNE3) may be connected in a region adjacent to the separator (SPR), and each of the contact regions may be defined adjacent to the separator (SPR). That is, the first to third cathodes (EL2_1, EL2_2, EL2_R) and the first to third connection electrodes (CNE1, CNE2, CNE3) are not connected at a specific point, but can be connected over a relatively wide area, for example, an area similar to the shape of each of the first to third connection electrodes (CNE1, CNE2, CNE3). That is, the area of ​​the connection contact is increased, so that the connection can proceed stably.

[0280] Figure 13d illustrates a separator (SPR), light-emitting parts (EP1, EP2, EP3), and a first electrode (EL1).

[0281] Referring to FIG. 13d, the first electrode (EL1, hereinafter referred to as anode) of the light-emitting element (LD, see FIG. 14) according to one embodiment of the present invention may be commonly provided to the first to third light-emitting portions (EP1, EP2, EP3). That is, the anode (EL1) may be formed as a single layer integral with the entire display area (DA), and thus the anode (EL1) layer may be arranged to overlap the separator (SPR). Alternatively, the anodes (EL1) of each of the light-emitting elements (LD) may be formed as independent conductive patterns spaced apart from each other and electrically connected to each other through other conductive layers, and thus the anode (EL1) patterns may be arranged to not overlap the separator (SPR).

[0282] As described above, a first power source (ELVDD, see Fig. 1) may be applied to the anode (EL1) and a common voltage may be provided to all light-emitting units. The anode (EL1) may be connected to a first power source line (PL1, see Fig. 2) that provides the first power source (ELVDD) in the peripheral area (NDA), or may be connected to a first power source line (PL1, see Fig. 2) in the display area (DA), and is not limited to any one embodiment.

[0283] According to the present embodiment, a plurality of openings may be defined in the anode (EL1), and the openings may penetrate the anode (EL1) layer. The openings in the anode (EL1) layer may be positioned so as not to overlap with the light-emitting portions (EP, see FIG. 12a), and may generally be defined so as to overlap with the separator (SPR). For example, the opening of the anode (EL1) may be defined so as to overlap with the separator (SPR) and to be spaced apart from the light-emitting portions (EP, see FIG. 12a). The openings may facilitate the discharge of gas generated from an organic layer disposed under the anode (EL1), for example, a sixth insulating layer (60, see FIG. 14) described below. Accordingly, the gas of the organic layer disposed under the light-emitting element may be sufficiently discharged during the display panel manufacturing process, and the gas emitted from the organic layer after manufacturing may be reduced, thereby reducing the rate at which the light-emitting element deteriorates.

[0284] Fig. 14 is a cross-sectional view of a display panel according to one embodiment of the present invention. Fig. 15 is an enlarged cross-sectional view of a portion of a display panel according to one embodiment of the present invention. Fig. 14 is a cross-sectional view showing a portion corresponding to line I-I' of Fig. 13a. Fig. 15 is an enlarged cross-sectional view of area AA' of Fig. 14.

[0285] Referring to FIGS. 14 and 15, a display panel (DP) of one embodiment may include a base layer (BS), a driving element layer (DDL), a light emitting element layer (LDL), an encapsulation layer (ECL), and a sensing layer (ISL). However, this is only an example, and in one embodiment of the present invention, the sensing layer (ISL) may be omitted from the display panel (DP).

[0286] A driving device layer (DDL) may include a plurality of insulating layers (10, 20, 30, 40, 50, 60) disposed on a base layer (BS), and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers (10, 20, 30, 40, 50, 60). The conductive patterns and semiconductor patterns may be disposed between the insulating layers (10, 20, 30, 40, 50, 60) to form a pixel driver (PDC). For easy explanation, FIG. 14 illustrates a cross-section of one area among the areas where one light-emitting unit is disposed.

[0287] The base layer (BS) may be a member that provides a base surface on which a pixel driver (PDC) is arranged. The base layer (BS) may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. The base layer (BS) may be a glass substrate, a metal substrate, a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer (BS) may be an inorganic layer, an organic layer, or a composite material layer.

[0288] The base layer (BS) may have a multilayer structure. The base layer (BS) may include a first polymer resin layer, a silicon oxide (SiOx) layer disposed on the first polymer resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0289] The polymer resin layer may include a polyimide-based resin. In addition, the polymer resin layer may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. Meanwhile, in the present specification, the "~~-based" resin means one that includes a "~~" functional group.

[0290] The insulating layers, conductive layers, and semiconductor layers disposed on the base layer (BS) can each be formed by methods such as coating and deposition. Thereafter, the insulating layer, semiconductor layer, and conductive layer can be selectively patterned through multiple photolithography processes to form holes in the insulating layer, or semiconductor patterns, conductive patterns, and signal lines.

[0291] The driving device layer (DDL) may include first to sixth insulating layers (10, 20, 30, 40, 50, 60) sequentially stacked on the base layer (BS) and a pixel driver (PDC). Fig. 14 illustrates one transistor (TR) and two capacitors (C1, C2) of the pixel driver (PDC).

[0292] The transistor (TR) corresponds to a transistor connected to the light-emitting element (LD) via the intermediate connection electrode (CN) and the connection electrode (CNE), i.e., a connection transistor connected to a node corresponding to the cathode of the light-emitting element (LD) (for example, the first node N1, see FIG. 2)), and specifically, may correspond to the fifth transistor (T5) of FIGS. 2, 4, and 6 or the fifth transistor (T5-1) of FIGS. 8 and 10. Meanwhile, although not shown, other transistors constituting the pixel driver (PDC) may have the same structure as the transistor (TR, hereinafter referred to as the connection transistor) illustrated in FIG. 14. However, this is merely an example, and other transistors constituting the pixel driver (PDC) may have a different structure from the connection transistor (TR) and are not limited to any one embodiment.

[0293] A first insulating layer (10) may be disposed on the base layer (BS). The first insulating layer (10) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer (10) is illustrated as a single-layer silicon oxide layer. Meanwhile, the insulating layers described below may be inorganic layers and / or organic layers, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-described materials, but is not limited thereto.

[0294] Meanwhile, the first insulating layer (10) may cover the lower conductive layer (BCL). That is, the display panel (DP) may further include a lower conductive layer (BCL) arranged to overlap the connection transistor (TR). The lower conductive layer (BCL) may block the electric potential caused by the polarization phenomenon of the base layer (BS) from affecting the connection transistor (TR). In addition, the lower conductive layer (BCL) may block light incident on the connection transistor (TR) from below. At least one of an inorganic barrier layer and a buffer layer may be further arranged between the lower conductive layer (BCL) and the base layer (BS).

[0295] The bottom conductive layer (BCL) may include a reflective metal. For example, the bottom conductive layer (BCL) may include titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu).

[0296] In the present embodiment, the lower conductive layer (BCL) may be connected to the source of the connection transistor (TR, or transistor) through the source electrode pattern (W1). In this case, the lower conductive layer (BCL) may be synchronized with the source of the transistor (TR). However, this is merely an example, and the lower conductive layer (BCL) may be connected to the gate of the transistor (TR) and may be synchronized with the gate. Alternatively, the lower conductive layer (BCL) may be connected to another electrode and independently receive a constant voltage or pulse signal. Alternatively, the lower conductive layer (BCL) may be provided in a form isolated from other conductive patterns. The lower conductive layer (BCL) according to one embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0297] A connection transistor (TR) may be disposed on a first insulating layer (10). The connection transistor (TR) may include a semiconductor pattern (SP) and a gate electrode (GE). The semiconductor pattern (SP) may be disposed on the first insulating layer (10). The semiconductor pattern (SP) may include an oxide semiconductor. For example, the oxide semiconductor may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, the present invention is not limited thereto, and the semiconductor pattern (SP) may include amorphous silicon, low-temperature crystalline silicon, or polycrystalline silicon.

[0298] A semiconductor pattern (SP) may include a source region (SR), a drain region (DR), and a channel region (CR), which are distinguished according to the degree of conductivity. The channel region (CR) may be a portion that overlaps with a gate electrode (GE) on a plane. The source region (SR) and the drain region (DR) may be portions spaced apart from each other with the channel region (CR) therebetween. When the semiconductor pattern (SP) is an oxide semiconductor, each of the source region (SR) and the drain region (DR) may be a reduced region. Accordingly, the source region (SR) and the drain region (DR) have a relatively high reduced metal content compared to the channel region (CR). Alternatively, when the semiconductor pattern (SP) is polycrystalline silicon, each of the source region (SR) and the drain region (DR) may be a highly doped region.

[0299] The source region (SR) and the drain region (DR) may have relatively higher conductivity than the channel region (CR). The source region (SR) may correspond to the source electrode of the connection transistor (TR), and the drain region (DR) may correspond to the drain electrode of the connection transistor (TR). As illustrated in FIG. 5, separate source electrode patterns (W1) and drain electrode patterns (W2) may be further provided, each connected to the source region (SR) and the drain region (DR). Specifically, the separate source electrode patterns (W1) and drain electrode patterns (W2) may be formed integrally with one of the lines constituting the pixel driver (or pixel driver circuit), and are not limited to any one embodiment.

[0300] The second insulating layer (20) overlaps a plurality of pixels in common and can cover the semiconductor pattern (SP). The second insulating layer (20) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The second insulating layer (20) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the second insulating layer (20) may be a single-layer silicon oxide layer.

[0301] The gate electrode (GE) may be disposed on the second insulating layer (20). The gate electrode (GE) may correspond to the gate of the connection transistor (TR). In addition, the gate electrode (GE) may be disposed on the upper side of the semiconductor pattern (SP). However, this is merely an example, and the gate electrode (GE) may also be disposed on the lower side of the semiconductor pattern (SP), and is not limited to any one embodiment.

[0302] The gate electrode (GE) may include, but is not particularly limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or an alloy thereof.

[0303] A third insulating layer (30) may be disposed on the gate electrode (GE). The third insulating layer (30) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The third insulating layer (30) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0304] Among the plurality of challenge patterns (W1, W2, CPE1, CPE2, CPE3), the first capacitor electrode (CPE1) and the second capacitor electrode (CPE2) constitute the first capacitor (C1). The first capacitor electrode (CPE1) and the second capacitor electrode (CPE2) may be spaced apart from each other with the first insulating layer (10) and the second insulating layer (20) therebetween.

[0305] In one embodiment of the present invention, the first capacitor electrode (CPE1) and the lower conductive layer (BCL) may have an integral shape. For example, the first capacitor electrode (CPE1) and the lower conductive layer (BCL) may be formed as a single continuous physical structure rather than as separate layers or components. In addition, the second capacitor electrode (CPE2) and the gate electrode (GE) may have an integral shape. For example, the second capacitor electrode (CPE2) and the gate electrode (GE) may be formed as a single continuous physical structure rather than as separate layers or components.

[0306] A third capacitor electrode (CPE3) may be placed on the third insulating layer (30). The third capacitor electrode (CPE3) may be spaced apart from the second capacitor electrode (CPE2) with the third insulating layer (30) interposed therebetween and may overlap on a plane. The third capacitor electrode (CPE3) may form a second capacitor (C2) with the second capacitor electrode (CPE2).

[0307] A fourth insulating layer (40) may be disposed on the third insulating layer (30) and / or the third capacitor electrode (CPE3). The fourth insulating layer (40) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The fourth insulating layer (40) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0308] A source electrode pattern (W1) and a drain electrode pattern (W2) may be disposed on a fourth insulating layer (40). The source electrode pattern (W1) may be connected to a source region (SR) of a connection transistor (TR) through a first contact hole (CNT1), and the source electrode pattern (W1) and the source region (SR) of the semiconductor pattern (SP) may function as a source of the connection transistor (TR). The drain electrode pattern (W2) may be connected to a drain region (DR) of the connection transistor (TR) through a second contact hole (CNT2), and the drain electrode pattern (W2) and the drain region (DR) of the semiconductor pattern (SP) may function as a drain of the connection transistor (TR). A fifth insulating layer (50) may be disposed on the source electrode pattern (W1) and the drain electrode pattern (W2).

[0309] An intermediate connection electrode (CN) may be disposed on the fifth insulating layer (50). The intermediate connection electrode (CN) may electrically connect the pixel driver (PDC) and the light-emitting element (LD). That is, the intermediate connection electrode (CN) may electrically connect the connection transistor (TR) and the light-emitting element. The intermediate connection electrode (CN) may be a connection node connecting the pixel driver (PDC) and the light-emitting element (LD). That is, the intermediate connection electrode (CN) may correspond to the first node (N1, see FIG. 2).

[0310] A sixth insulating layer (60) may be disposed on the intermediate connecting electrode (CN). The sixth insulating layer (60) may be disposed on the fifth insulating layer (50) to cover at least a portion of the intermediate connecting electrode (CN). Each of the fifth insulating layer (50) and the sixth insulating layer (60) may be an organic layer. For example, each of the fifth insulating layer (50) and the sixth insulating layer (60) may include a general-purpose polymer such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), or PS (Polystyrene), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, and blends thereof.

[0311] The sixth insulating layer (60) may be provided with a through hole (OP-60) that exposes at least a portion of the intermediate connection electrode (CN). The intermediate connection electrode (CN) may be connected to the connection electrode (CNE) through a portion exposed from the sixth insulating layer (60), and may be electrically connected to the light emitting element (LD). That is, the intermediate connection electrode (CN) may electrically connect the connection transistor (TR) and the light emitting element (LD) together with the connection electrode (CNE). In the present specification, the region where the intermediate connection electrode (CN) and the connection electrode (CNE) are connected may be referred to as a connection region (CNA). The connection region (CNA) may be defined by the through hole (OP-60). In one embodiment of the present invention, the sixth insulating layer (60) may be omitted from the display panel (DP) or may be provided in multiple portions in the display panel (DP), and is not limited to any one embodiment. When the sixth insulating layer (60) is omitted, the intermediate connection electrode (CN) may also be omitted.

[0312] The intermediate connecting electrode (CN) may include a first layer (L1), a second layer (L2), and a third layer (L3) sequentially stacked along a third direction (DR3). The second layer (L2) may include a different material from the first layer (L1). Furthermore, the second layer (L2) may include a different material from the third layer (L3). The second layer (L2) may have a relatively thicker thickness than the first layer (L1). Furthermore, the second layer (L2) may have a relatively thicker thickness than the third layer (L3). The second layer (L2) may include a highly conductive material. In one embodiment, the second layer (L2) may include aluminum (Al).

[0313] A light-emitting device layer (LDL) may be disposed on a driving device layer (DDL). The light-emitting device layer (LDL) may include a pixel defining layer (PDL), a light-emitting device (LD), and a separator (SPR).

[0314] The pixel defining layer (PDL) may be an organic layer. For example, the pixel defining layer (PDL) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), or PS (Polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0315] In one embodiment, the pixel defining layer (PDL) may have a light-absorbing property and may have, for example, a black color. That is, the pixel defining layer (PDL) may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining layer (PDL) may correspond to a light-shielding pattern having light-shielding properties.

[0316] An opening (OP-PDL, hereinafter referred to as an emission opening) exposing at least a portion of a first electrode (EL1) to be described later may be defined in a pixel defining layer (PDL). A plurality of emission openings (OP-PDL) may be provided and arranged to correspond to each of the emission elements. All components of the emission element (LD) may be arranged to overlap in the emission opening (OP-PDL), and may be an area where light emitted by the emission element (LD) is substantially displayed. Accordingly, the shape of the first emission portion (EP1, see FIG. 13a) may substantially correspond to the shape of the emission opening (OP-PDL) on a plane. An area corresponding to the first emission portion (EP1), that is, an area defined by the emission opening (OP-PDL), may be referred to as an emission area (EA).

[0317] A connection electrode (CNE) may be arranged on a pixel defining layer (PDL). The connection electrode (CNE) may electrically connect a pixel driver (PDC) and a light emitting element (LD). That is, the pixel driver (PDC) may be electrically connected to the light emitting element (LD) via the intermediate connection electrode (CN) and the connection electrode (CNE). The connection electrode (CNE) may correspond to the first connection electrode (CNE1) illustrated in FIG. 13a. The second connection electrode (CNE2, see FIG. 13a) and the third connection electrode (CNE3, see FIG. 13a) may also have structures similar to the connection electrode (CNE).

[0318] The connecting electrode (CNE) may include a first edge (EG1c) adjacent to the light-emitting aperture (OP-PDL) and a second edge (EG2c) surrounding the first edge (EG1c). The second electrode (EL2) of the light-emitting element (LD) may be in contact with the connecting electrode (CNE) in an area adjacent to the second edge (EG2c).

[0319] The connecting electrode (CNE) may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, the material constituting the connecting electrode (CNE) is not limited to the above examples. For example, the connecting electrode (CNE) may also include a metallic material.

[0320] A pixel defining layer (PDL) may define a light-emitting aperture (OP-PDL) and a spaced-apart through hole (OP-P). A plurality of through holes (OP-P) may be provided and arranged to correspond to each light-emitting element. The size of the through hole (OP-P) defined in the pixel defining layer (PDL) may be larger than the size of the through hole (OP-60) defined in the sixth insulating layer (60). A connection electrode (CNE) may be arranged within the through hole (OP-P) and the through hole (OP-60) and may be connected to an intermediate connection electrode (CN).

[0321] The light emitting element (LD) may include a first electrode (EL1), an intermediate layer (IML), and a second electrode (EL2).

[0322] The first electrode (EL1) may be a semi-transparent, transparent, or reflective electrode. According to one embodiment of the present invention, the first electrode (EL1) may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode (EL1) may include a stacked structure of ITO / Ag / ITO.

[0323] In the present embodiment, the first electrode (EL1) may be an anode of the light emitting element (LD). That is, the first electrode (EL1) may be connected to a first power line (PL1, see FIG. 2) and may be supplied with a first power source (ELVDD, see FIG. 2). The first electrode (EL1) may be connected to the first power line (PL1) within a display area (DA, see FIG. 12a or 12b) or may be connected to the first power line (PL1) in a peripheral area (NDA). In the latter case, the first power line (PL1) may be arranged in the peripheral area (NDA, see FIG. 12a or 12b) and the first electrode (EL1) may have a shape extending to the peripheral area (NDA).

[0324] In the cross-sectional view of FIG. 14, the first electrode (EL1) is illustrated as overlapping the light-emitting opening (OP-PDL) and not overlapping the separator (SPR). However, as described above in FIG. 13d, the first electrodes (EL1) of the light-emitting elements may have a single shape and a mesh or lattice shape in which openings are defined in some areas. That is, as long as the same first power supply voltage (VDD) can be applied to the first electrodes (EL1) of each of the plurality of light-emitting elements, the shape of the first electrodes (EL1) may be provided in various ways and is not limited to any one embodiment.

[0325] An intermediate layer (IML) may be disposed between a first electrode (EL1) and a second electrode (EL2). The intermediate layer (IML) may include a light-emitting layer (EML) and a functional layer (FNL). The light-emitting element (LD) may include an intermediate layer (IML) of various structures and is not limited to any one embodiment. For example, the functional layer (FNL) may be provided as a plurality of layers or as two or more layers spaced apart with the light-emitting layer (EML) interposed therebetween.

[0326] Referring to FIGS. 14 and 15, the functional layer (FNL) may be disposed between the first electrode (EL1) and the second electrode (EL2). The functional layer (FNL) may include a first intermediate functional layer (FNLa) disposed between the first electrode (EL1) and the light-emitting layer (EML), and a second intermediate functional layer (FNLb) disposed between the second electrode (EL2) and the light-emitting layer (EML). In the present embodiment, the light-emitting layer (EML) is illustrated as being inserted into the functional layer (FNL). That is, it can be understood that the light-emitting layer (EML) is disposed between the first intermediate functional layer (FNLa) and the second intermediate functional layer (FNLb).

[0327] The functional layer (FNL) can control the movement of charges between the first electrode (EL1) and the second electrode (EL2). For example, the first intermediate functional layer (FNLa) can include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer (FNLb) can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0328] The light-emitting layer (EML) may include an organic light-emitting material. In addition, the light-emitting layer (EML) may include an inorganic light-emitting material, or may be provided as a mixed layer of an organic light-emitting material and an inorganic light-emitting material. In the present embodiment, the light-emitting layers (EML) included in each adjacent light-emitting portion (EP, see FIG. 12a) may include light-emitting materials that display different colors. For example, the light-emitting layer (EML) included in each light-emitting portion (EP) may provide light of any one of blue, red, and green. However, the present invention is not limited thereto, and the light-emitting layers (EML) disposed in all light-emitting portions (EP) may include light-emitting materials that display the same color. In this case, the light-emitting layers (EML) may provide blue light or white light.

[0329] The second electrode (EL2) may be disposed on the intermediate layer (IML). As described above, the second electrode (EL2) may be electrically connected to the pixel driver (PDC) by being connected to the connection electrode (CNE). That is, the second electrode (EL2) may be electrically connected to the connection transistor (TR) through the connection electrode (CNE).

[0330] The separator (SPR) may be disposed on a pixel defining layer (PDL). Additionally, the separator (SPR) may be disposed on a connection electrode (CNE) disposed on the pixel defining layer (PDL) and a gap (GP) between the connection electrode (CNE) and an adjacent connection electrode.

[0331] In one embodiment, the second electrode (EL2) and the functional layer (FNL) may be formed by commonly depositing on a plurality of pixels through an open mask. At this time, the second electrode (EL2) and the functional layer (FNL) may be divided by a separator (SPR). For example, the separator (SPR) may separate the second electrode (EL2) from the functional layer (FNL). As described above, the separator (SPR) may have a closed-line shape for each light-emitting portion, and accordingly, the second electrode (EL2) and the functional layer (FNL) may have a divided shape for each light-emitting portion. That is, the second electrode (EL2) and the intermediate layer (IML) may be electrically independent for each adjacent pixel. For example, the second electrode (EL2) and the functional layer (FNL) may be divided into separate regions corresponding to each light-emitting portion, and may not be formed as a continuous layer across the plurality of light-emitting portions.

[0332] In one embodiment, the separator (SPR) may have a reverse taper shape. That is, the separator (SPR) may have a shape whose width increases as it gets farther from the upper surface of the pixel defining layer (PDL). The side surface (TP) of the separator (SPR) may have a shape with an obtuse taper angle inclined from the upper surface of the pixel defining layer (PDL). However, this is merely an example, and if the separator (SPR) can electrically disconnect the second electrode (EL2) for each pixel, the taper angle of the separator (SPR) may be set in various ways, and for example, may have a dual structure with different taper angles. In addition, the separator (SPR) may have a structure such as a tip portion and is not limited to any one embodiment.

[0333] As illustrated in FIGS. 14 and 15, the separator (SPR) may have a double reverse taper shape. The side surface (TP) of the separator (SPR) may include a first side surface (TP1) and a second side surface (TP2) having different taper angles. The taper angle formed by the first side surface (TP1) of the separator (SPR) with respect to the upper surface of the pixel defining layer (PDL) and the taper angle formed by the second side surface (TP2) with respect to the upper surface of the pixel defining layer (PDL) may be different from each other. Each of the taper angles may be an obtuse angle. For example, as illustrated in FIG. 15, the taper angle formed by the first side surface (TP1) with respect to the upper surface of the pixel defining layer (PDL) may be smaller than the taper angle formed by the second side surface (TP2) with respect to the upper surface of the pixel defining layer (PDL). However, this is merely an example, and the taper angles can be set in various ways as long as the separator (SPR) can electrically disconnect the second electrode (EL2) for each pixel. In addition, the separator (SPR) may have a structure similar to a tip portion and is not limited to any one embodiment.

[0334] The separator (SPR) may include an insulating material, and in particular, an organic insulating material. The separator (SPR) may also include an inorganic insulating material, may be composed of multiple layers of organic and inorganic insulating materials, and may include a conductive material, depending on the embodiment. That is, as long as the second electrode (EL2) can be electrically isolated for each pixel, the separator (SPR) is not particularly limited in terms of the type of material.

[0335] A dummy layer (UP) may be disposed on the separator (SPR). The dummy layer (UP) may include a first dummy layer (UP1) disposed on the separator (SPR) and a second dummy layer (UP2) disposed on the first dummy layer (UP1). The first dummy layer (UP1) may be formed by the same process as the intermediate layer (IML) and may include the same material. The first dummy layer (UP1) may include a 1-1 dummy layer (UP1a) and a 1-2 dummy layer (UP1b). The 1-1 dummy layer (UP1a) may be formed by the same process as the first intermediate functional layer (FNLa) and may include the same material. The 1-2 dummy layer (UP1b) may be formed by the same process as the second intermediate functional layer (FNLb) and may include the same material. The second dummy layer (UP2) may be formed by the same process as the second electrode (EL2) and may include the same material. That is, the first dummy layer (UP1) and the second dummy layer (UP2) may be formed simultaneously during the process of forming the functional layer (FNL) and the second electrode (EL2). As illustrated in FIG. 15, the dummy layer (UP) may be formed not only on the upper surface of the separator (SPR) but also on a portion of the side surface (TP). In another embodiment, the dummy layer (UP) may be omitted from the display panel (DP). The dummy layer (UP) may be in non-contact with the connection electrode (CNE) and the second electrode (EL2). The second dummy layer (UP2) included in the dummy layer (UP) may be in non-contact with the connection electrode (CNE) and the second electrode (EL2).

[0336] The second electrode (EL2) is in contact with the connection electrode (CNE) through a contact area (CA). The contact area (CA) is provided adjacent to the separator (SPR). In the contact area (CA), the upper surface (CNE-us) of the connection electrode (CNE) is in contact with the lower surface (EL2-bs) of the second electrode (EL2). Meanwhile, since the separator (SPR) has a reverse taper shape and the contact area (CA) is provided adjacent to the separator (SPR), at least a part of the contact area (CA) where the second electrode (EL2) and the connection electrode (CNE) are in contact can be disposed below the side surface (TP) of the separator (SPR).

[0337] In one embodiment, at least a portion of the connecting electrode (CNE) may be disposed under the separator (SPR). The separator (SPR) may be disposed over a gap (GP) between the connecting electrode (CNE) and an adjacent connecting electrode adjacent to the connecting electrode (CNE), and a second edge (EG2c) of the second electrode (EL2) may be covered by the separator (SPR).

[0338] A display panel (DP) of one embodiment may include an intermediate area (MA) disposed between an emission area (EA) in which a light-emitting element (LD) is disposed and a contact area (CA). The intermediate area (MA) may be an area in which at least a portion of an intermediate layer (IML) is disposed. In the intermediate area (MA), a functional layer (FNL) included in the intermediate layer (IML) may be disposed between a connection electrode (CNE) and a second electrode (EL2). That is, in the intermediate area (MA), the connection electrode (CNE) and the second electrode (EL2) may be spaced apart from each other with the functional layer (FNL) therebetween.

[0339] The intermediate region (MA) may be adjacent to the contact region (CA). The functional layer (FNL) disposed in the intermediate region (MA) may include the first intermediate functional layer (FNLa) and the second intermediate functional layer (FNLb) described above. The first intermediate functional layer (FNLa) may be disposed between the first electrode (EL1) and the emission layer (EML) in the emission region (EA), and the second intermediate functional layer (FNLb) may be disposed between the second electrode (EL2) and the emission layer (EML) in the emission region (EA).

[0340] In the display panel (DP) of one embodiment, the functional layer (FNL) and the second electrode (EL2) may be formed through different deposition process methods. The second electrode (EL2) may be formed by a deposition method that can deposit a deposition material at a lower incident angle than the deposition method for forming the functional layer (FNL). The functional layer (FNL) may be formed, for example, by a thermal evaporation method, and the second electrode (EL2) may be covered by a sputtering method. Accordingly, in the process of forming the functional layer (FNL), the material for forming the functional layer (FNL) may not penetrate below the side surface (TP) of the separator (SPR), thereby exposing a part of the connection electrode (CNE), and the second electrode (EL2) may be formed closer to the separator (SPR) than the functional layer (FNL), so that the second electrode (EL2) may contact the upper surface (CNE-us) of the exposed connection electrode (CNE). That is, a contact area (CA) where the second electrode (EL2) and the connection electrode (CNE) come into contact can be formed through differences in the deposition process methods in the functional layer (FNL) and second electrode (EL2) formation processes.

[0341] Meanwhile, as illustrated in FIG. 14, a connection area (CNA) where a connection electrode (CNE) is connected to an intermediate connection electrode (CN) may be disposed between the light-emitting area (EA) and the contact area (CA). The connection area (CNA) may overlap the intermediate area (MA). At least a portion of the intermediate layer (IML) may be disposed to overlap the connection area (CNA). In the display panel (DP) of one embodiment, the functional layer (FNL) included in the intermediate layer (IML) may be disposed to overlap the connection area (CNA).

[0342] According to one embodiment of the present invention, the connecting electrode (CNE) has a shape that surrounds at least a portion of the light-emitting area (EA) where the light-emitting element (LD) is arranged. Therefore, the degree of freedom of the position at which the connecting electrode (CNE) and the light-emitting element (LD) are connected and the degree of freedom of the position at which the connecting electrode (CNE) and the pixel driver (PDC) are connected can be improved. In addition, the upper surface (CNE-us) of the connecting electrode (CNE) can be in contact with the lower surface (EL2-bs) of the second electrode (EL2) of the light-emitting element (LD) through the contact area (CA) defined adjacent to the separator (SPR). Accordingly, the contact reliability of the connecting electrode (CNE) and the second electrode (EL2) can be improved, and since the lower surface of the connecting electrode (CNE) and the upper surface of the intermediate connecting electrode (CN) are in contact, the contact reliability can be improved. According to one embodiment, the display panel (DP) has a structure in which the sizes of through holes (OP-P, OP-60) for connecting a connection electrode (CNE) and an intermediate connection electrode (CN) can be reduced or minimized, thereby easily increasing the area or resolution of a light-emitting portion of the display panel (DP).

[0343] Referring again to FIG. 14, an encapsulation layer (ECL) may be disposed on the light emitting element layer (LDL). The encapsulation layer (ECL) may cover the light emitting element (LD) and the separator (SPR). The encapsulation layer (ECL) may include a first inorganic layer (IL1), an organic layer (OL), and a second inorganic layer (IL2) that are sequentially laminated. However, the present invention is not limited thereto, and the encapsulation layer (ECL) may additionally include a plurality of inorganic layers and organic layers. In addition, the encapsulation layer (ECL) may be a glass substrate.

[0344] The first and second inorganic layers (IL1, IL2) protect the light emitting element (LD) from moisture and oxygen outside the display panel (DP), and the organic layer (OL) can protect the light emitting element (LD) from foreign substances such as particles remaining during the formation of the first inorganic layer (IL1). The first and second inorganic layers (IL1, IL2) may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer (OL) may include an acrylic-based organic layer, and the type of material is not limited to any one.

[0345] The sensing layer (ISL) can sense an external input. In the present embodiment, the sensing layer (ISL) can be formed on the encapsulation layer (ECL) through a continuous process. At this time, the sensing layer (ISL) can be expressed as being directly disposed on the encapsulation layer (ECL). Directly disposed may mean that no other components are disposed between the sensing layer (ISL) and the encapsulation layer (ECL). In other words, a separate adhesive member may not be disposed between the sensing layer (ISL) and the encapsulation layer (ECL). However, this is merely an example, and in the display panel (DP) according to an embodiment of the present invention, the sensing layer (ISL) may be formed separately and then coupled to the display panel (DP) through an adhesive member, and is not limited to any one embodiment.

[0346] The sensing layer (ISL) may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer (MTL1) and a second sensing conductive layer (MTL2), and the plurality of insulating layers may include first to third sensing insulating layers (71, 72, 73). However, this is merely an example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0347] Each of the first to third sensing insulating layers (71, 72, 73) may have a single-layer structure or a multi-layer structure laminated along the third direction (DR3). The first to third sensing insulating layers (71, 72, 73) may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulating layers (71, 72, 73) may include an organic film. The organic film may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0348] The first sensing conductive layer (MTL1) may be disposed between the first sensing insulating layer (71) and the second sensing insulating layer (72), and the second sensing conductive layer (MTL2) may be disposed between the second sensing insulating layer (72) and the third sensing insulating layer (73). A portion of the second sensing conductive layer (MTL2) may be connected to the first sensing conductive layer (MTL1) through a contact hole (CNT) formed in the second sensing insulating layer (72). Each of the first sensing conductive layer (MTL1) and the second sensing conductive layer (MTL2) may have a single-layer structure or a multi-layer structure stacked along the third direction (DR3).

[0349] The sensing conductive layer of the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, or the like.

[0350] The multilayered sensing conductive layer may include metal layers. The metal layers may have a three-layer structure of, for example, titanium (Ti) / aluminum (Al) / titanium (Ti). Alternatively, the multilayered sensing conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0351] The first sensing conductive layer (MTL1) and the second sensing conductive layer (MTL2) can form a sensor configured to detect an external input in the sensing layer (ISL). The sensor can be driven by a capacitive method, and can be driven by either a mutual capacitive method or a self-capacitive method. However, this is described as an example, and the sensor can also be driven by a resistive method, an ultrasonic method, or an infrared method in addition to a capacitive method, and is not limited to any one embodiment.

[0352] Each of the first sensing conductive layer (MTL1) and the second sensing conductive layer (MTL2) may include a transparent conductive oxide or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer (MTL1) and the second sensing conductive layer (MTL2) may have various materials and various shapes as long as the visibility of the image displayed by the display panel (DP) is not reduced, and are not limited to any one embodiment.

[0353] Fig. 16 is a cross-sectional view of a display panel according to one embodiment of the present invention. In describing Fig. 16, identical / similar reference numerals are used for configurations identical / similar to those described in Figs. 14 and 15, and duplicate descriptions are omitted, with a focus on differences.

[0354] Referring to FIG. 16, the display panel (DP-1) may further include a connection wire (CN-ad) disposed between the sixth insulating layer (60) and the pixel defining layer (PDL). The connection wire (CN-ad) may be connected to the intermediate connection electrode (CN) through a through hole (OP-60) that exposes at least a portion of the intermediate connection electrode (CN).

[0355] In one embodiment of the present invention, the connection wiring (CN-ad) may be disposed on the same layer as the first electrode (EL1). For example, the connection wiring (CN-ad) may have the same material and the same layer structure as the first electrode (EL1). In addition, the connection wiring (CN-ad) may be formed by the same process as the first electrode (EL1). However, this is merely an example and is not limited thereto. For example, the connection wiring (CN-ad) may include a different material from the first electrode (EL1) and may be formed by a different process.

[0356] A through hole (OP-Pa) may be defined in a pixel defining layer (PDL). The through hole (OP-Pa) and the through hole (OP-60) may not overlap each other, but this is not particularly limited. For example, the through hole (OP-Pa) and the through hole (OP-60) may overlap each other. A connection electrode (CNE) may be arranged within the through hole (OP-Pa). The connection electrode (CNEa) may be connected to a portion of the connection wiring (CN-ad) exposed by the through hole (OP-Pa).

[0357] According to the present invention, the cathode of the light-emitting element can be electrically connected to the drain of the driving transistor. The driving transistor in the pixel driving circuit can be an N-type transistor, and at least one of the switching transistors can be a P-type transistor. Through this, the maximum voltage value required to turn on and off the transistors in the pixel driving circuit can be lowered. Accordingly, the voltage difference between the maximum voltage value and the minimum voltage value can be reduced, and a pixel with reduced power consumption and a display device including the same can be provided.

[0358] Figure 17 is a block diagram of an electronic device according to one embodiment of the present invention.

[0359] Referring to FIG. 17, the electronic device (601) outputs various information through the display module (640) within the operating system. When the processor (610) executes an application stored in the memory (620), the display module (640) provides application information to the user through the display panel (641).

[0360] The processor (610) obtains external input through the input module (630) or the sensor module (661) and executes an application corresponding to the external input. For example, when a user selects a camera icon displayed on the display panel (641), the processor (610) obtains the user input through the input sensor (661-2) and activates the camera module (671). The processor (610) transmits image data corresponding to the captured image obtained through the camera module (671) to the display module (640). The display module (640) can display an image corresponding to the captured image through the display panel (641).

[0361] As another example, when personal information authentication is performed in the display module (640), the fingerprint sensor (661-1) acquires the input fingerprint information as input data. The processor (610) compares the input data acquired through the fingerprint sensor (661-1) with the authentication data stored in the memory (620) and executes an application based on the comparison result. The display module (640) can display the information executed according to the application's logic through the display panel (641).

[0362] As another example, when a music streaming icon displayed on the display module (640) is selected, the processor (610) obtains user input through the input sensor (661-2) and activates the music streaming application stored in the memory (620). When a music execution command is input from the music streaming application, the processor (610) activates the audio output module (663) to provide the user with audio information corresponding to the music execution command.

[0363] Above, the operation of the electronic device (601) has been briefly described. Below, the configuration of the electronic device (601) will be described in detail. Some of the configurations of the electronic device (601) described below may be integrated and provided as a single configuration, or one configuration may be provided by being separated into two or more configurations.

[0364] Referring to FIG. 17, an electronic device (601) may communicate with an external electronic device (602) via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device (601) may include a processor (610), a memory (620), an input module (630), a display module (640), a power module (650), a built-in module (660), and an external module (670). According to one embodiment, the electronic device (601) may omit at least one of the above-described components, or may have one or more other components added. According to one embodiment, some of the above-described components (e.g., a sensor module (661), an antenna module (662), or an audio output module (663)) may be integrated into another component (e.g., a display module (640)).

[0365] The processor (610) may execute software to control at least one other component (e.g., a hardware or software component) of the electronic device (601) connected to the processor (610) and perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operations, the processor (610) may store commands or data received from other components (e.g., an input module (630), a sensor module (661), or a communication module (673)) in a volatile memory (621), process the commands or data stored in the volatile memory (621), and store the resulting data in a non-volatile memory (622).

[0366] The processor (610) may include a main processor (611) and a secondary processor (612). The main processor (611) may include one or more of a central processing unit (CPU: central processing unit) 611-1 or an application processor (AP: application processor). The main processor (611) may further include one or more of a graphic processing unit (GPU: graphic processing unit) 611-2, a communication processor (CP: communication processor), and an image signal processor (ISP: image signal processor). The main processor (611) may further include a neural network processing unit (NPU: neural processing unit) 611-3. The neural network processing unit is a processor specialized in processing artificial intelligence models, and the artificial intelligence models can be generated through machine learning. The artificial intelligence models may include a plurality of artificial neural network layers. The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), deep Q-networks, or a combination of two or more of the above, but is not limited to the examples described above. In addition to or as an alternative to the hardware structure, the artificial intelligence model may include a software structure. At least two of the processing units and processors described above may be implemented as a single integrated configuration (e.g., a single chip), or each may be implemented as an independent configuration (e.g., multiple chips).

[0367] The auxiliary processor (612) may include a drive controller (612-1). The drive controller (612-1) may include an interface conversion circuit and a timing control circuit. The drive controller (612-1) receives a video signal from the main processor (611), converts the data format of the video signal to match the interface specifications with the display module (640), and outputs the video data. The drive controller (612-1) may output various control signals necessary for driving the display module (640). Since the configuration of the drive controller (612-1) is substantially similar to the drive controller (100) illustrated in FIG. 1, a detailed description thereof will be omitted.

[0368] The auxiliary processor (612) may further include a data conversion circuit (612-2), a gamma correction circuit (612-3), a rendering circuit (612-4), etc. The data conversion circuit (612-2) may receive image data from the driving controller (612-1) and compensate for the image data so that the image is displayed at a desired brightness according to the characteristics of the electronic device (601) or the user's settings, or may convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit (612-3) may convert the image data or the gamma reference voltage so that the image displayed on the electronic device (601) has a desired gamma characteristic. The rendering circuit (612-4) may receive image data from the driving controller (612-1) and render the image data in consideration of the pixel layout of the display panel (641) applied to the electronic device (601). At least one of the data conversion circuit (612-2), the gamma correction circuit (612-3), and the rendering circuit (612-4) may be integrated into another component (e.g., the main processor (611) or the controller (612-1)). At least one of the data conversion circuit (612-2), the gamma correction circuit (612-3), and the rendering circuit (612-4) may also be integrated into the data driver (643) described below.

[0369] The memory (620) can store various data used by at least one component of the electronic device (601) (e.g., the processor (610) or the sensor module (661)) and input data or output data for commands related thereto. The memory (620) can include at least one of a volatile memory (621) and a non-volatile memory (622).

[0370] The input module (630) can receive commands or data to be used in components of the electronic device (601) (e.g., a processor (610), a sensor module (661), or an audio output module (663)) from an external source of the electronic device (601) (e.g., a user or an external electronic device (602)).

[0371] The input module (630) may include a first input module (631) for inputting a command or data from a user and a second input module (632) for inputting a command or data from an external electronic device (602). The first input module (631) may include a microphone, a mouse, a keyboard, a key (e.g., a button), or a pen (e.g., a passive pen or an active pen). The second input module (632) may support a designated protocol that can be connected to the external electronic device (602) by wire or wirelessly. According to one embodiment, the second input module (632) may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface. The second input module (632) may include a connector that can be physically connected to the external electronic device (602), for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0372] The display module (640) visually provides information to the user. The display module (640) may include a display panel (641), a scan driver (642), and a data driver (643). The display module (640) may further include a window, a chassis, and a bracket for protecting the display panel (641). The display module (640) may further include a light emitting driver and a voltage generator. The voltage generator may output various voltages required to drive the display panel (641) (for example, first and second driving voltages (ELVDD, ELVSS), see FIG. 2). The configuration of the display panel (641), the scan driver (642), the data driver (643), and the voltage generator is substantially similar to the display panel (DP), the scan driving circuit (SD), the light emitting driving circuit (EDC), the data driving circuit (200), and the voltage generator (300) illustrated in FIG. 1, and thus a detailed description thereof will be omitted.

[0373] The power module (650) supplies power to components of the electronic device (601). The power module (650) may include a battery that charges a power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power module (650) may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and those described below. The power module (650) may include a wireless power transmitting / receiving element electrically connected to the battery. The wireless power transmitting / receiving element may include a plurality of coil-shaped antenna radiators.

[0374] The electronic device (601) may further include a built-in module (660) and an external module (670). The built-in module (660) may include a sensor module (661), an antenna module (662), and an audio output module (663). The external module (670) may include a camera module (671), a light module (672), and a communication module (673).

[0375] The sensor module (661) can detect input by the user's body or input by a pen among the first input modules (631), and generate an electric signal or data value corresponding to the input. The sensor module (661) can include at least one of a fingerprint sensor (661-1), an input sensor (661-2), and a digitizer (661-3).

[0376] The fingerprint sensor (661-1) can generate a data value corresponding to the user's fingerprint. The fingerprint sensor (661-1) can include either an optical or capacitive fingerprint sensor.

[0377] The input sensor (661-2) can generate data values ​​corresponding to coordinate information of input by the user's body or input by the pen. The input sensor (661-2) generates a data value based on the amount of change in electrostatic capacity due to the input. The input sensor (661-2) can detect input by a passive pen or transmit and receive data with an active pen.

[0378] The input sensor (661-2) can also measure bio-signals such as blood pressure, moisture, or body fat. For example, when a user touches a part of his or her body to the sensor layer or sensing panel and remains motionless for a certain period of time, the input sensor (661-2) can detect the bio-signal based on the change in the electric field caused by the part of his or her body and output the information desired by the user to the display module (640).

[0379] The digitizer (661-3) can generate data values ​​corresponding to coordinate information input by the pen. The digitizer (661-3) generates the electromagnetic change amount due to the input as a data value. The digitizer (661-3) can detect input by a passive pen or transmit and receive data with an active pen.

[0380] At least one of the fingerprint sensor (661-1), the input sensor (661-2), and the digitizer (661-3) may be implemented as a sensor layer formed on the display panel (641) through a continuous process. The fingerprint sensor (661-1), the input sensor (661-2), and the digitizer (661-3) may be disposed on the upper side of the display panel (641), and any one of the fingerprint sensor (661-1), the input sensor (661-2), and the digitizer (661-3), for example, the digitizer (661-3), may be disposed on the lower side of the display panel (641).

[0381] At least two of the fingerprint sensor (661-1), the input sensor (661-2), and the digitizer (661-3) may be formed to be integrated into a single sensing panel through the same process. When integrated into a single sensing panel, the sensing panel may be arranged between the display panel (641) and a window arranged on the upper side of the display panel (641). According to one embodiment, the sensing panel may be arranged on the window, and the position of the sensing panel is not particularly limited.

[0382] At least one of the fingerprint sensor (661-1), the input sensor (661-2), and the digitizer (661-3) can be built into the display panel (641). That is, at least one of the fingerprint sensor (661-1), the input sensor (661-2), and the digitizer (661-3) can be formed simultaneously through a process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel (641).

[0383] In addition, the sensor module (661) can generate an electrical signal or data value corresponding to an internal or external state of the electronic device (601). The sensor module (661) may further include, for example, a gesture sensor, a gyro sensor, a pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0384] The antenna module (662) may include one or more antennas for transmitting or receiving signals or power to or from the outside. According to one embodiment, the communication module (673) may transmit or receive signals to or from an external electronic device via an antenna suitable for a communication method. The antenna pattern of the antenna module (662) may be integrated into one component of the display module (640) (e.g., the display panel (641)) or the input sensor (661-2).

[0385] The audio output module (663) is a device for outputting audio signals to the outside of the electronic device (601), and may include, for example, a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for phone reception. According to one embodiment, the receiver may be formed integrally with or separately from the speaker. The audio output pattern of the audio output module (663) may also be integrated into the display module (640).

[0386] The camera module (671) can capture still images and videos. According to one embodiment, the camera module (671) may include one or more lenses, image sensors, or image signal processors. The camera module (671) may further include an infrared camera capable of measuring the presence of a user, the user's location, the user's line of sight, etc.

[0387] The light module (672) can provide light. The light module (672) can include a light emitting diode or a xenon lamp. The light module (672) can operate in conjunction with the camera module (671) or can operate independently.

[0388] The communication module (673) can support the establishment of a wired or wireless communication channel between the electronic device (601) and the external electronic device (602), and the performance of communication through the established communication channel. The communication module (673) can include any one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module, and a wired communication module such as a local area network (LAN) communication module or a power line communication module. The communication module (673) can communicate with the external electronic device (602) through a short-range communication network such as Bluetooth, WiFi direct, or IrDA (infrared data association), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or WAN). The various types of communication modules (673) described above can be implemented as one chip or can be implemented as separate chips.

[0389] The input module (630), sensor module (661), camera module (671), etc. can be used to control the operation of the display module (640) in conjunction with the processor (610).

[0390] The processor (610) outputs a command or data to the display module (640), the audio output module (663), the camera module (671), or the light module (672) based on the input data received from the input module (630). For example, the processor (610) may generate image data corresponding to input data applied through a mouse or an active pen, and output the image data to the display module (640), or generate command data corresponding to the input data and output the image data to the camera module (671) or the light module (672). When no input data is received from the input module (630) for a certain period of time, the processor (610) may switch the operation mode of the electronic device (601) to a low-power mode or a sleep mode to reduce power consumption of the electronic device (601).

[0391] The processor (610) outputs a command or data to the display module (640), the audio output module (663), the camera module (671), or the light module (672) based on the sensing data received from the sensor module (661). For example, the processor (610) may compare the authentication data authorized by the fingerprint sensor (661-1) with the authentication data stored in the memory (620), and then execute an application based on the comparison result. The processor (610) may execute a command or output corresponding image data to the display module (640) based on the sensing data detected by the input sensor (661-2) or the digitizer (661-3). When the sensor module (661) includes a temperature sensor, the processor (610) may receive temperature data on the temperature measured from the sensor module (661) and further perform brightness correction, etc. on the image data based on the temperature data.

[0392] The processor (610) can receive measurement data regarding the presence or absence of a user, the user's location, the user's line of sight, etc. from the camera module (671). The processor (610) can further perform brightness correction, etc. on the image data based on the measurement data. For example, the processor (610) that determines the presence or absence of a user through input from the camera module (671) can output the image data with brightness corrected through the data conversion circuit (612-2) or the gamma correction circuit (612-3) to the display module (640).

[0393] Some of the above components may be interconnected with each other through a communication method between peripheral devices, such as a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface), or UPI (ultra path interconnect) link, to exchange signals (e.g., commands or data) with each other. The processor (610) may communicate with the display module (640) through a mutually agreed upon interface, and may use, for example, any one of the above-described communication methods, and is not limited to the above-described communication methods.

[0394] The electronic device (601) according to various embodiments disclosed in this document may be a device of various forms. The electronic device (601) may include, for example, at least one of a portable communication device (e.g., a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device. The electronic device (601) according to the embodiments of this document is not limited to the aforementioned devices.

[0395] While the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0396] Recently, the demand for low-power displays has been increasing. The present invention can reduce the maximum voltage required to turn on and off transistors by combining N-type and P-type transistors in a pixel driving circuit. Therefore, the voltage difference between the maximum and minimum voltages can be reduced, and pixels with reduced power consumption and a display device including the same can be provided, and thus the present invention has high industrial applicability.

Claims

1. A pixel including a light-emitting element connected between a first power line to which a first power source is provided and a first node, and a pixel driving circuit connected to the light-emitting element, The above pixel driving circuit, A first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the second node, and a gate electrode electrically connected to the third node; A second transistor including a first electrode electrically connected to a data line to which a data signal is provided, a second electrode electrically connected to the third node, and a gate electrode receiving a scan signal; and A third transistor comprising a first electrode electrically connected to a first initialization voltage line to which a first initialization voltage is provided, a second electrode electrically connected to the first node, and a gate electrode receiving a compensation scan signal, The above first transistor is an N-type transistor, The above second transistor is an N-type transistor or a P-type transistor, The display device wherein the third transistor is a P-type transistor.

2. In paragraph 1, The pixel driving circuit further includes a fourth transistor including a first electrode electrically connected to a reference voltage line to which a reference voltage is provided, a second electrode electrically connected to the third node, and a gate electrode receiving an initialization scan signal, A display device in which the fourth transistor is an N-type transistor or a P-type transistor.

3. In paragraph 2, During the initialization period, the initialization scan signal is at an active level, and the compensation scan signal and the scan signal are at an inactive level. A display device in which the compensation scan signal and the initialization scan signal are at active levels during the compensation period, and the scan signal is at an inactive level.

4. In paragraph 1, The above pixel driving circuit, a first capacitor connected between the second node and the third node; and A display device further comprising a second capacitor connected between the second node and a second power line through which a second power source having a lower voltage level than the first power source is provided.

5. In paragraph 1, The pixel driving circuit further includes a fifth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode receiving a first light emission signal. The display device in which the above fifth transistor is a P-type transistor.

6. In paragraph 5, The pixel driving circuit further includes a sixth transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a second power line to which a second power source having a lower voltage level than the first power source is provided, and a gate electrode that receives a second light emission signal. The display device wherein the above sixth transistor is an N-type transistor or a P-type transistor.

7. In paragraph 6, A display device in which the high level of the first light-emitting signal and the high level of the compensation scan signal are 10 V or less.

8. In paragraph 6, During the initialization period, the second light emitting signal is at an active level and the first light emitting signal is at a non-active level; A display device wherein the first light emitting signal is at an active level and the second light emitting signal is at a non-active level during the compensation period.

9. In paragraph 6, A display device in which the voltage value of the first power supply is 8.4 V or less.

10. In paragraph 9, A display device in which the voltage value of each of the first power supply and the first initialization voltage is about 8.4 V, the voltage value of the second power supply is about 0 V, and the high level of each of the compensation scan signal and the first light emission signal is about 8.4 V.

11. In paragraph 9, The voltage value of each of the first power supply and the first initialization voltage is about 7 V, and the voltage value of the second power supply is about 0 V. A display device in which the high level of each of the compensation scan signal and the first light emission signal is approximately 7 V.

12. In paragraph 1, The above pixel driving circuit, A fifth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode that receives a light emission signal; and A sixth transistor further includes a first electrode electrically connected to the second node, a second electrode electrically connected to a second power line to which a second power source having a lower voltage level than the first power source is provided, and a gate electrode that receives the light-emitting signal. A display device wherein each of the fifth and sixth transistors is a P-type transistor.

13. In paragraph 12, The pixel driving circuit further includes a seventh transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a second initialization voltage line to which a second initialization voltage having a lower voltage level than the first initialization voltage is provided, and a gate electrode that receives an input scan signal. The display device in which the above seventh transistor is an N-type transistor.

14. In paragraph 13, During the initialization period, the above input scan signal is at an active level, A display device in which the input scan signal is at an inactive level during the compensation period.

15. In paragraph 13, The pixel driving circuit further includes an eighth transistor including a first electrode electrically connected to the first initialization voltage line, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode receiving the compensation scan signal, The above eighth transistor is a display device that is a P-type transistor.

16. In paragraph 12, The voltage value of the first power source is about 8.4 V, the voltage value of the second power source is about 0 V, and the high level of the light-emitting signal is 10 V or less. A display device in which the voltage value of the first initialization voltage is approximately 8.4 V and the high level of the compensation scan signal is 10 V or less.

17. In paragraph 1, The light emitting element comprises an anode, a cathode disposed on the anode, and at least a light emitting layer, and an intermediate layer disposed between the anode and the cathode, A display device wherein the anode is electrically connected to the first power line and the cathode is electrically connected to the first node.

18. In paragraph 17, A pixel defining film having an opening defined therein exposing at least a portion of the anode; A connecting electrode disposed on the pixel definition film and electrically connected to the first node and the cathode; and Further comprising a separator disposed on the pixel defining film, A display device in which the lower surface of the cathode is in contact with the upper surface of the connecting electrode in the contact area adjacent to the separator.

19. A light emitting element comprising a first electrode, an intermediate layer disposed on the first electrode and including at least a light emitting layer, and a second electrode disposed on the intermediate layer, and connected between a first power line to which a first power source is provided and a first node; A pixel driving circuit comprising a driving transistor and a plurality of switching transistors and connected to the light emitting element; A pixel defining film having an opening defined therein that exposes at least a portion of the first electrode; A connecting electrode disposed on the pixel defining film and electrically connected to the pixel driving circuit and the second electrode; and A separator is disposed on the pixel defining film, In the contact area adjacent to the separator, the lower surface of the second electrode contacts the upper surface of the connecting electrode, The above driving transistor is an N-type transistor, A display device wherein at least one of the plurality of switching transistors is a P-type transistor.

20. A display device that displays images; and including a processor that controls the operation of the display device; The above display device, A pixel including a light-emitting element connected between a first power line and a first node to which a first power source is provided, and a pixel driving circuit connected to the light-emitting element, The above pixel driving circuit, A first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the second node, and a gate electrode electrically connected to the third node; A second transistor including a first electrode electrically connected to a data line to which a data signal is provided, a second electrode electrically connected to the third node, and a gate electrode receiving a scan signal; and A third transistor comprising a first electrode electrically connected to a first initialization voltage line to which a first initialization voltage is provided, a second electrode electrically connected to the first node, and a gate electrode receiving a compensation scan signal, The above first transistor is an N-type transistor, The above second transistor is an N-type transistor or a P-type transistor, An electronic device wherein the third transistor is a P-type transistor.

Images