Three-dimensional random access memory having structure including OTS or selection transistor

Abstract

The present invention proposes: a three-dimensional random access memory having a structure including two selection transistors respectively disposed at upper and lower ends of a string in order to prevent a deviation in a memory cell applied disturbance voltage from occurring in an unselected string; and an operating method thereof. The three-dimensional random access memory comprises: gate electrodes stacked and spaced apart from each other in the vertical direction while extending in the horizontal direction; and vertical structures passing through the gate electrodes and extending in the vertical direction, wherein each of the vertical structures may include a data storage pattern, a vertical conductive pattern, and at least one ovonic threshold switch (OTS) positioned at at least one end of an upper end or a lower end of each of the vertical structures.

Description

A three-dimensional random access memory having a structure including an OTS or selection transistor

[0001] The examples below are for three-dimensional random access memory.

[0002] Semiconductor devices such as DRAM (Dynamic Random Access Memory) have a MOS transistor including a source and a drain, a capacitor electrically connected to the source of the MOS transistor, and wiring such as a bit line electrically connected to the drain of the MOS transistor.

[0003] These DRAMs began to be implemented in a three-dimensional structure, moving away from the two-dimensional structure, in line with the trend toward high integration to secure storage space.

[0004] A 3D DRAM is implemented to support and operate random access based on a semiconductor structure including interlayer insulating layers and gate electrodes that are alternately stacked in the vertical direction, and a memory cell string that extends vertically through the semiconductor structure, and a vertical conductive pattern that functions as a gate electrode and a vertical electrode within the memory cell string.

[0005] However, since the existing 3D DRAM only includes a bit line selection transistor (BL ST) provided at the top of the memory cell string, it has a problem in that a deviation in the memory cell applied disturbance voltage occurs within an unselected string that does not include the target memory cell that is the target of the memory operation.

[0006] Accordingly, a technique for preventing deviation of memory cell input disturbance voltage within an unselected string needs to be proposed.

[0007] Furthermore, a technique needs to be proposed to reduce the complexity of the manufacturing process of a component having the function of string selection.

[0008] The embodiments propose a three-dimensional random access memory having a structure including two selection transistors respectively arranged at the top and bottom of a string, and an operating method thereof, to prevent variations in memory cell input disturbance voltages from occurring within an unselected string.

[0009] The embodiments propose a three-dimensional random access memory having a structure including at least one OTS (Ovonic Threshold Switch) positioned at at least one end of the top or bottom of each of the vertical structures to reduce the complexity of the manufacturing process of the component having the function of string selection.

[0010] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0011] According to an embodiment, a three-dimensional random access memory may include gate electrodes that are formed to extend horizontally and are vertically spaced apart from each other and are stacked; and vertical structures that extend vertically through the gate electrodes, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) positioned at at least one end of an upper or lower end of each of the vertical structures.

[0012] According to one aspect, the at least one OTS may be characterized in that, instead of being positioned corresponding to the gate electrodes, it is positioned corresponding to at least one end of the top or bottom of each of the vertical structures.

[0013] According to another aspect, the at least one OTS may be selectively turned on or off by a voltage applied to a bit line connected to an upper portion of each of the vertical structures or a source line connected to a lower portion of each of the vertical structures during a memory operation, thereby allowing each of the vertical structures to be selected.

[0014] According to another aspect, any one of the vertical structures including a target memory cell that is a target of a memory operation among the vertical structures may be characterized in that the one or more vertical structures are selected in response to at least one OTS being turned on during the memory operation.

[0015] According to another aspect, at least one vertical structure among the vertical structures that does not include a target memory cell that is a target of a memory operation may be characterized in that it is not selected in response to at least one OTS being turned off in the at least one vertical structure during the memory operation.

[0016] According to another aspect, the at least one OTS may be characterized in that it is located at at least one of the upper or lower portions of the data storage pattern and the vertical conductive pattern in each of the vertical structures.

[0017] According to an embodiment, a method of operating a three-dimensional random access memory including gate electrodes formed to extend horizontally and spaced apart vertically and stacked; and vertical structures formed to extend vertically through the gate electrodes, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) positioned at at least one end of an upper or lower end of each of the vertical structures, may include the steps of: selectively turning on or turning off the at least one OTS included in each of the vertical structures by a voltage applied to a bit line connected to an upper portion of each of the vertical structures or a source line connected to a lower portion of each of the vertical structures; and selecting one of the vertical structures including a target memory cell among the vertical structures and performing a memory operation on the target memory cell as the at least one OTS is selectively turned on or off.

[0018] According to one aspect, the performing step may be characterized by including a step of not selecting the at least one vertical structure that does not include the target memory cell in response to the at least one OTS being turned off in the at least one vertical structure that does not include the target memory cell, and selecting the at least one vertical structure that includes the target memory cell in response to the at least one OTS being turned on in the at least one vertical structure that includes the target memory cell.

[0019] According to an embodiment, a method for manufacturing a three-dimensional random access memory may include a step of extending vertical structures penetrating a semiconductor structure including gate electrodes that are vertically spaced apart and stacked while being formed to extend in a horizontal direction, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) positioned at at least one end of an upper or lower end of each of the vertical structures.

[0020] According to an embodiment, a method for manufacturing a three-dimensional random access memory may include: forming vertical structures extending through a semiconductor structure including sacrificial layers that are vertically spaced apart and stacked while extending in a horizontal direction, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) positioned at at least one end of an upper or lower end of each of the vertical structures; and removing the sacrificial layers to form gate electrodes in spaces where the sacrificial layers are removed.

[0021] According to one aspect, the step of extending and forming the vertical structures may include a step of forming the at least one OTS with a semiconductor material that is selectively turned on or off by a voltage applied to a bit line connected to an upper portion of each of the vertical structures or a source line connected to a lower portion of each of the vertical structures during a memory operation.

[0022] According to an embodiment, a three-dimensional random access memory may include gate electrodes that are formed to extend horizontally and are vertically spaced apart from each other and are stacked; and vertical structures that extend vertically through the gate electrodes, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and two select transistors disposed above and below the vertical conductive pattern, respectively.

[0023] According to one aspect, the two selection transistors included in each of the vertical structures may be selectively turned on or off during memory operation to selectively connect each of the vertical structures to a bit line or a source.

[0024] According to another aspect, a selected vertical structure among the vertical structures, wherein the selected vertical structure includes a target memory cell that is a target of a memory operation, may be characterized in that, in response to a bit line selection transistor among the two selection transistors in the selected vertical structure being turned on and a source selection transistor being turned off during the memory operation, the selected vertical structure is connected to the bit line.

[0025] According to another aspect, an unselected vertical structure among the vertical structures, which does not include a target memory cell that is a target of a memory operation, may be characterized in that, in response to the bit line selection transistor among the two selection transistors in the unselected vertical structure being turned off and the source selection transistor being turned on during the memory operation, the unselected vertical structure is connected to the source.

[0026] According to another aspect, a three-dimensional random access memory characterized in that each of the two selection transistors is formed of a semiconductor material that selectively forms a channel so as to be selectively turned on or off during memory operation.

[0027] According to another aspect, each of the two selection transistors may be characterized by having a structure including a buried pattern therein.

[0028] According to another aspect, the two selection transistors may be characterized in that they are provided surrounded by two dielectric patterns arranged on the upper and lower sides of the data storage pattern so as to correspond to the two selection transistors, respectively.

[0029] According to an embodiment, a memory operation method of a three-dimensional random access memory including gate electrodes formed to extend horizontally and spaced apart vertically and stacked; and vertical structures formed to extend vertically through the gate electrodes, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and two select transistors respectively disposed on an upper and a lower portion of the vertical conductive pattern, may include a step of selectively turning on or off the two select transistors included in each of the vertical structures to selectively connect each of the vertical structures to a bit line or a source; and a step of performing a memory operation on a target memory cell in response to each of the vertical structures being selectively connected to the bit line and the source.

[0030] According to one aspect, the connecting step may be characterized by including a step of connecting the selected vertical structure to the bit line in response to a bit line select transistor among the two select transistors being turned on and a source select transistor being turned off in the selected vertical structure, the selected vertical structure including a target memory cell to be the target of the memory operation.

[0031] According to another aspect, the connecting step may be characterized by including a step of connecting an unselected vertical structure among the vertical structures, wherein the unselected vertical structure does not include a target memory cell that is a target of a memory operation, to the source in response to a bit line select transistor among the two select transistors being turned off and a source select transistor being turned on.

[0032] According to an embodiment, a method for manufacturing a three-dimensional random access memory may include: preparing a semiconductor structure including gate electrodes that are formed to extend in a horizontal direction and are vertically spaced apart and stacked; extending vertical holes penetrating the semiconductor structure in the vertical direction; and extending vertical structures penetrating the gate electrodes in the vertical direction within each of the vertical holes, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and two select transistors disposed above and below the vertical conductive pattern, respectively.

[0033] According to another embodiment, a method for manufacturing a three-dimensional random access memory may include preparing a semiconductor structure including sacrificial layers that are vertically spaced apart and stacked while extending in a horizontal direction; forming vertical holes extending through the semiconductor structure in the vertical direction; forming vertical structures extending through the sacrificial layers in each of the vertical holes in the vertical direction, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and two select transistors disposed above and below the vertical conductive pattern, respectively; and removing the sacrificial layers to form gate electrodes in spaces where the sacrificial layers are removed.

[0034] According to one aspect, the step of extending and forming the vertical structures may include a step of forming the two selection transistors with a semiconductor material that selectively forms a channel so as to be selectively turned on or off during memory operation.

[0035] The embodiments propose a three-dimensional random access memory having a structure including two selection transistors respectively arranged at the top and bottom of a string and an operating method thereof, thereby achieving a technical effect of preventing a deviation in a memory cell applied disturbance voltage from occurring within an unselected string.

[0036] The embodiments can achieve a technical effect of reducing the complexity of the manufacturing process of a component having a string selection function by proposing a three-dimensional random access memory having a structure including at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures.

[0037] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0038] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to embodiments.

[0039] FIG. 2 is a plan view illustrating a three-dimensional random access memory according to embodiments.

[0040] FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2.

[0041] FIG. 4 is a cross-sectional view illustrating a three-dimensional random access memory according to another embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2.

[0042] FIG. 5 is a flow chart illustrating an operating method of a three-dimensional random access memory according to embodiments.

[0043] Figures 6 and 7 are flow charts illustrating a method for manufacturing a three-dimensional random access memory according to embodiments.

[0044] FIGS. 8A to 8G are drawings for explaining a method for manufacturing a three-dimensional random access memory according to one embodiment.

[0045] FIGS. 9A to 9G are drawings for explaining a method for manufacturing a three-dimensional random access memory according to another embodiment.

[0046] FIG. 10 is a simplified circuit diagram illustrating a three-dimensional random access memory according to embodiments.

[0047] FIG. 11 is a plan view illustrating a three-dimensional random access memory according to embodiments.

[0048] Fig. 12 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of Fig. 11.

[0049] FIGS. 13 to 16 are cross-sectional views illustrating a three-dimensional random access memory according to another embodiment, corresponding to a cross-section taken along line A-A' of FIG. 11.

[0050] FIGS. 17 and 18 are drawings for explaining an operating method of a three-dimensional random access memory according to embodiments.

[0051] FIG. 19 is a flow chart illustrating an operating method of a three-dimensional random access memory according to embodiments.

[0052] FIGS. 20 to 21 are flowcharts illustrating a method for manufacturing a three-dimensional random access memory according to embodiments.

[0053] FIG. 22 is a perspective view schematically illustrating an electronic system including a three-dimensional random access memory according to embodiments.

[0054] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0055] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0056] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0057] Hereinafter, with reference to FIGS. 1 to 9g and 22, a three-dimensional random access memory having a structure including at least one OTS (Ovonic Threshold Switch) positioned at at least one end of the upper or lower end of each of the vertical structures will be described in detail, and with reference to FIGS. 10 to 21 and 22, a three-dimensional random access memory having a structure including two selection transistors positioned at the upper and lower ends of a string, respectively, and an operating method thereof will be described in detail.

[0058] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to embodiments.

[0059] Referring to FIG. 1, a three-dimensional random access memory according to one embodiment may include a plurality of bit lines (BL1, BL2), a common source (CS; hereinafter, referred to as a source), and a plurality of vertical electrodes (VE; hereinafter, referred to as a vertical conductive pattern) connecting the bit lines. Each of the plurality of vertical electrodes (VE) may constitute a plurality of memory cell strings (CSTR; hereinafter, referred to as cell strings).

[0060] The bit lines (BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0061] Each of the bit lines (BL1, BL2) may have a plurality of cell strings (CSTR) connected in parallel. Each of the cell strings (CSTR) includes a vertical electrode (VE), and thus, a plurality of bit lines (BL1, BL2) and a plurality of vertical electrodes (VE) may be connected in parallel.

[0062] Cell strings (CSTR) may be commonly connected to a source (CS) provided between bit lines (BL1, BL2) and a common source (CS).

[0063] At this time, the source (CS) may be implemented in a plate shape so as to be shared by the cell strings (CSTR) constituting the array, but is not limited thereto and may be implemented in a line shape so as to be shared only by the cell strings (CSTR) included in the same row or column. When the source (CS) is implemented in a line shape, a plurality of sources (CS) may be provided, and the plurality of sources (CS) may be two-dimensionally arranged while extending in the first direction (D1) and spaced apart from each other along the second direction (D2). The plurality of sources (CS) may be electrically applied with the same voltage, but is not limited thereto and each of the plurality of sources (CS) may be electrically independently controlled so as to be applied with different voltages.

[0064] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may include memory cell transistors (MCT) arranged corresponding to word lines (WL1, WL2, WL3, ..., WLn) and at least one OTS (OTS1-U, OTS1-L, OTS2-U, OTS2-L, OTS3-U, OTS3-L, OTS4-U, OTS4-L) positioned at at least one end of the upper or lower end of each of the cell strings (CSTR). Each of the memory cell transistors (MCT) may include a data storage element.

[0065] More specifically, one cell string (CSTR) may be composed of an OTS (OTS1-U, OTS2-U, OTS3-U, OTS4-U) positioned at the top of the string closest to the bit lines (BL1, BL2), a plurality of memory cell transistors (MCT) having different distances from the bit lines (BL1, BL2), and an OTS (OTS1-L, OTS2-L, OTS3-L, OTS4-L) positioned at the bottom of the string closest to the source (CS). That is, the memory cell transistors (MCT) may be connected in series while being arranged along the third direction (D3).

[0066] However, without being limited or restricted thereto, in one cell string (CSTR), the OTS (OTS1-L, OTS2-L, OTS3-L, OTS4-L) located at the bottom of the string closest to the source (CS) may be omitted.

[0067] Here, the OTS (OTS1-U, OTS2-U, OTS3-U, OTS4-U) located at the top of the string closest to the bit lines (BL1, BL2) can be controlled to be selectively turned on or off by a voltage applied to each of the bit lines (BL1, BL2).

[0068] Similarly, the OTSs (OTS1-L, OTS2-L, OTS3-L, OTS4-L) located at the bottom of the string closest to the source (CS) can be controlled to be selectively turned on or off by a voltage applied to each of the sources (CS).

[0069] Memory cell transistors (MCT) can be controlled by word lines (WL1, WL2, WL3, ..., WLn). For this purpose, gate electrodes (EL) of the memory cell transistors (MCT) can be commonly connected to one of the word lines (WL1, WL2, WL3, ..., WLn) to be in an equipotential state.

[0070] The word lines (WL1, WL2, WL3, ..., WLn) can be implemented in the form of plates so as to be shared by the cell strings (CSTR) constituting the array.

[0071] FIG. 2 is a plan view illustrating a three-dimensional random access memory according to embodiments, and FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2. FIG. 4 is a cross-sectional view illustrating a three-dimensional random access memory according to another embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2.

[0072] Referring to the drawings, the laminated structure (ST) can be formed to extend in the first direction (D1) and the second direction (D2). In the drawings, the laminated structure (ST) is illustrated as one, but is not limited thereto, and a plurality of laminated structures (ST) may be provided and arranged two-dimensionally while being spaced apart from each other along one direction (the first direction (D1) or the second direction (D2)).

[0073] The stacked structure (ST) may include gate electrodes (EL) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)). The stacked structure (ST) may have a substantially flat upper surface. Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0074] Although omitted in the drawing, the stacked structure (ST) may exist in a state of being arranged on the substrate (SUB) before the formation of the source (CS). That is, the stacked structure (ST) is manufactured by alternately stacking gate electrodes (EL) and interlayer insulating layers (ILD) on the substrate (SUB), and then the substrate (SUB) is removed during the formation of the source (CS), so that it may not include the substrate (SUB) as a result. However, the stacked structure (ST) is not limited thereto, and may have a structure that includes the substrate (SUB) as the source (CS) is formed through a process such as implanting impurities into the substrate (SUB).

[0075] The substrate (SUB) may be a semiconductor substrate, such as a substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0076] Referring again to FIG. 1, each of the gate electrodes (EL) may be one of the word lines (WL1, WL2, WL3, ..., WLn) sequentially stacked on the substrate (SUB), and may be a component used as a conductor in a three-dimensional random access memory.

[0077] Each of the gate electrodes (EL) may be formed in a plate shape extending in the first direction (D1) and also extending in the second direction (D2), and may be shared by an array of vertical structures (VS; cell strings in FIG. 1), and may have a substantially identical thickness in the third direction (D3). Hereinafter, the thickness refers to the thickness in the third direction (D3).

[0078] Each of these gate electrodes (EL) can be formed of a conductive material. For example, each of the gate electrodes (EL) can be formed of at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). In addition to the described metal materials, each of the gate electrodes (EL) can include at least one of all metal materials that can be formed by ALD.

[0079] Although not shown, one of the upper and lower ends of each of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL) of the stacked structures (ST) may have a length in the first direction (D1) that decreases from the bottom to the top in the vertical direction. For example, the gate electrode positioned at the uppermost position among the gate electrodes (EL) may have the shortest length in the first direction (D1), and the gate electrode positioned at the lowermost position among the gate electrodes (EL) may have the longest length in the first direction (D1).

[0080] However, without being limited or restricted thereto, the end of the laminated structure (ST) may have a step structure along the second direction (D2).

[0081] Although each of the interlayer insulating layers (ILDs) is illustrated as having the same thickness, it is not limited thereto and may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between gate electrodes (EL). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0082] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, an air gap may be interposed between the gate electrodes (EL) while the gate electrodes (EL) are stacked while being spaced apart from each other in the vertical direction (e.g., the third direction (D3)).

[0083] A plurality of vertical holes (H) penetrating a portion of the stacked structures (ST) may be provided. Vertical structures (VS) may be provided within the vertical holes (H). The vertical structures (VS) may be formed as a plurality of cell strings (CSTR) as illustrated in FIG. 1 and may extend in a third direction (D3) while being connected to bit lines (BL1, BL2) and a source (CS).

[0084] The vertical structures (VS) may be connected to the bit lines (BL1, BL2) by indirectly contacting the upper surfaces of each of the vertical structures (VS) with the lower surfaces of the bit lines (BL1, BL2) through another structure (e.g., a bit line plug (BLPG)). However, without being limited thereto, the vertical structures (VS) may be connected to the bit lines (BL1, BL2) by directly contacting the upper surfaces of each of the vertical structures (VS) with the lower surfaces of the bit lines (BL1, BL2).

[0085] The vertical structures (VS) may be connected to the source (CS) by having the lower surface of each of the vertical structures (VS) directly contact the upper surface of the source (CS). However, without limitation or restriction thereto, the vertical structures (VS) may also be connected to the source (CS) by having the lower surface of each of the vertical structures (VS) indirectly contact the upper surface of the source (CS) through another structure.

[0086] The rows of vertical structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL) are formed in a plate shape, the vertical structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL). For example, as illustrated in FIG. 2, eight vertical structures (VS) may form four columns and four rows and penetrate one of the stacked structures (ST). However, the number of vertical structures (VS) forming the array is not limited thereto.

[0087] As vertical structures (VS) are formed in a plate shape to form an array of multiple columns and rows on a horizontal plane of gate electrodes (EL), the three-dimensional random access memory can have a structure in which the integration of memory cell strings is improved.

[0088] At this time, the vertical structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on the horizontal plane and to be misaligned with each other. For example, the vertical structures (VS) included in the first column may be arranged in the first and third rows, and the vertical structures (VS) included in the second column may be arranged in the second and fourth rows, such that the vertical structures (VS) included in the pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string may be further improved compared to the case where the vertical structures (VS) included in the pair of adjacent columns are arranged side by side in the same row on the horizontal plane.

[0089] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical structures (VS) is depicted as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0090] These vertical structures (VS) may correspond to the cell strings (CSTR) illustrated in FIG. 1.

[0091] To this end, each of the vertical structures (VS) may include a data storage pattern (DSP), a vertical conductive pattern (VE), and at least one OTS. In each of the vertical structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with the top and bottom ends open, and the vertical conductive pattern (VE) may have a shape that fills a space inside the data storage pattern (DSP) from the top and bottom ends to a predetermined depth and height while being surrounded on the outside by the data storage pattern (DSP), and at least one OTS may be located at at least one end of the top or bottom of each of the vertical structures (VS). That is, instead of being located at a position corresponding to the gate electrodes, the at least one OTS may be located at a position corresponding to at least one end of the top or bottom of each of the vertical structures (VS). Precisely, at least one OTS may be located at at least one portion of the top or bottom of the data storage pattern (DSP) and the vertical conductive pattern (VE) in each of the vertical structures (VS).

[0092] For example, referring to FIG. 3, which illustrates a structure in which a vertical structure (VS) includes one OTS, the OTS may be positioned on top of a data storage pattern (DSP) and a vertical conductive pattern (VE) in the vertical structure (VS), and may be arranged on the top of the vertical structure (VS).

[0093] For another example, referring to FIG. 4 which illustrates a structure in which two OTSs (OTS-U, OTS-L) are included in a vertical structure (VS), the upper OTS-U among the OTSs (OTS-U, OTS-L) may be positioned above the data storage pattern (DSP) and the vertical conductive pattern (VE) in the vertical structure (VS) and may be arranged at the top of the vertical structure (VS), and the lower OTS-L among the OTSs (OTS-U, OTS-L) may be positioned below the data storage pattern (DSP) and the vertical conductive pattern (VE) in the vertical structure (VS) and may be arranged at the bottom of the vertical structure (VS).

[0094] In this way, since at least one OTS is located at at least one end of the top or bottom of the vertical structure (VS) rather than at a position corresponding to the gate electrode (EL), the complexity of the manufacturing process can be reduced.

[0095] The data storage pattern (DSP) surrounds the outer sidewall of the vertical conductive pattern (VE) and can be in contact with the outer sidewalls of the gate electrodes (EL). Accordingly, regions of the data storage pattern (DSP) corresponding to the gate electrodes (EL) can constitute memory cells in which a memory operation (a write operation including a program operation and an erase operation, and a read operation) is performed by a voltage applied through the gate electrodes (EL) and a voltage applied to the vertical conductive pattern (VE). Hereinafter, the application of voltage to the vertical conductive pattern (VE) means that the vertical structure (VS) including the corresponding vertical conductive pattern (VE) is selected by at least one OTS, and thus the corresponding vertical conductive pattern (VE) is selectively connected to the bit line (BL), so that the voltage is transmitted to the corresponding vertical conductive pattern (VE).

[0096] The memory cells correspond to the memory cell transistors (MCT) illustrated in Fig. 1. To this end, the data storage pattern (DSP) may be a polarization-generating dielectric pattern, which is a data storage element that generates a polarization phenomenon by a voltage applied through gate electrodes (EL) and a voltage applied to a vertical conductive pattern (VE), thereby representing a data value as a change in voltage, current, or resistance corresponding to the polarization state of charges.

[0097] For example, as a data storage pattern (DSP), at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx or InOx can be used.

[0098] As another example, antiferroelectric materials can be used as data storage patterns (DSPs), and ZrO is an antiferroelectric material. x , Zr a X b O x (X may include Hf, Si, Al, Ge or one of the elements in group 2 of the periodic table) may be used.

[0099] However, without being limited or restricted thereto, the data storage pattern (DSP) may be a data storage element that represents a data value by trapping a charge by an applied voltage.

[0100] Additionally, although the drawing illustrates that the data storage pattern (DSP) is formed to extend in a vertical direction (e.g., a third direction (D3)), it is not limited thereto and may have a structure in which the data storage pattern (DSP) is segmented into multiple pieces and spaced apart only in areas corresponding to the gate electrodes (EL) on the outer wall of the vertical conductive pattern (VE).

[0101] The vertical conductive pattern (VE) is a component used as a conductor rather than a channel in a 3D random access memory, and, like the gate electrodes (EL), can be formed of at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0102] These vertical conductive patterns (VE) can be selectively connected to a bit line (BL) or a source (CS) through at least one OTS located at at least one of the upper or lower portions included in each of the vertical structures (VS). Hereinafter, the fact that the bit line (BL) or the source (CS) is selectively connected to the vertical conductive pattern (VE) does not mean that the bit line (BL) or the source (CS) is physically in contact with and connected to the vertical conductive pattern (VE), but that the vertical conductive pattern (VE) is electrically connected to the bit line (BL) or the source (CS) so as to receive a voltage applied to the bit line (BL) or the source (CS).

[0103] To this end, at least one OTS can serve as a selector that is selectively turned on or off by a voltage applied to a bit line (BL) or a source line (CS) during a memory operation so that each of the vertical structures (VS) is selected (a selector that is selectively turned on or off and selectively connects the vertical structures (VS) (more precisely, the vertical conductive pattern (VE) of each of the vertical structures (VS)) to the bit line (BL) or the source (CS).

[0104] That is, at least one OTS can be selectively turned on or off to select any one of the vertical structures (VS) that includes a target memory cell to be the target of the memory operation.

[0105] For example, any one of the vertical structures (VS) containing a target memory cell can be selected in response to at least one OTS being turned on in any one of the vertical structures during a memory operation.

[0106] As another example, at least one vertical structure among the vertical structures (VS) that does not contain a target memory cell may not be selected in response to at least one OTS being turned off in the at least one vertical structure during a memory operation.

[0107] At least one OTS may be formed of a semiconductor material (e.g., polycrystalline silicon, an oxide semiconductor material, a doped semiconductor material, a phase change material, etc.) that is selectively turned on or off by a voltage applied to a bit line (BL) or a source line (CS) during a memory operation to serve as the described selector.

[0108] At least two bit lines (BL1, BL2) are positioned at the same height on the upper portion of the vertical structures (VS). The vertical structures (VS) arranged in the same row in the array may further include bit line plugs (BLPG) arranged at positions offset from the centers of each of the vertical structures (VS) so as to be connected to different bit lines (BL1, BL2), respectively. That is, the vertical structures (VS) arranged in the same row in the array may be connected to different bit lines (BL1, BL2), respectively, through the bit line plugs (BLPG) arranged at positions offset from the centers of each of the vertical structures (VS).

[0109] A separation trench (BLSLT; not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). Insulating spacers (not shown) may be formed in the separation trench (BLSLT), thereby isolating the adjacent stacked structures (ST) from each other. For example, the insulating spacers may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant. The separation trench (BLSLT) may serve to isolate the gate electrode (EL-BLSL) as described above.

[0110] A capping insulating film (CAP) may be provided on the stacked structures (ST) and the vertical structures (VS). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0111] Bit lines (BL) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit lines (BL) may be formed by extending along a second direction (D2) with a conductive material while being spaced apart from each other along a first direction (D2). The conductive material forming the bit lines (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL).

[0112] As described, a three-dimensional random access memory can perform a memory operation by selecting a vertical structure (VS) containing a target memory cell through at least one OTS. This will be described with reference to FIG. 5.

[0113] FIG. 5 is a flow chart illustrating an operating method of a three-dimensional random access memory according to embodiments.

[0114] Hereinafter, the operating method described is assumed to be performed by a three-dimensional random access memory having a structure described with reference to FIGS. 1 to 4, and may mean a memory operation including at least one of a program operation, a read operation, or an erase operation for a target memory cell.

[0115] In step (S510), the three-dimensional random access memory can selectively turn on or turn off at least one OTS included in each of the vertical structures (VS) by a voltage applied to a bit line (BL) connected to the upper portion of each of the vertical structures (VS) or a source line (CS) connected to the lower portion of each of the vertical structures (VS).

[0116] Accordingly, in step (S520), the three-dimensional random access memory can perform a memory operation on the target memory cell by selecting one of the vertical structures (VS) including the target memory cell as at least one OTS is selectively turned on or off.

[0117] More specifically, the three-dimensional random access memory can select any one vertical structure including the target memory cell in response to at least one OTS being turned on in any one vertical structure including the target memory cell, without selecting any one vertical structure not including the target memory cell in response to at least one OTS being turned off in any one vertical structure not including the target memory cell.

[0118] Figures 6 and 7 are flowcharts illustrating a method for manufacturing a three-dimensional random access memory according to embodiments. More specifically, Figure 6 is a flowchart illustrating a manufacturing method based on a gate-first process, and Figure 7 is a flowchart illustrating a manufacturing method based on a gate replacement process.

[0119] The manufacturing method described below is for manufacturing a three-dimensional random access memory having the structure described above with reference to FIGS. 1 to 4, and is assumed to be performed by an automated and mechanized manufacturing system.

[0120] Referring to FIG. 6, in step S610, the manufacturing system can form vertical structures (VS) extending in the horizontal direction and vertically penetrating a semiconductor structure (SEMI-STR) including stacked gate electrodes (EL) spaced apart from each other in the vertical direction.

[0121] Here, each of the vertical structures (VS) includes a data storage pattern (DSP), a vertical conductive pattern (VE), and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures (VS), and as step (S610) is performed, a three-dimensional random access memory having a structure including at least one OTS can be manufactured.

[0122] Referring to FIG. 7, in step S710, the manufacturing system can form vertical structures (VS) extending in the horizontal direction and vertically penetrating a semiconductor structure (SEMI-STR) including stacked sacrificial layers (SAC) spaced apart from each other in the vertical direction.

[0123] Next, in step (S720), the manufacturing system can remove the sacrificial layers (SAC) to form gate electrodes (EL) in the spaces where the sacrificial layers (SAC) are removed.

[0124] Each of the vertical structures (VS) includes a data storage pattern (DSP), a vertical conductive pattern (VE), and at least one OTS (Ovonic Threshold Switch) positioned at at least one end of the top or bottom of each of the vertical structures (VS), and as the steps (S710 to S720) are performed, a three-dimensional random access memory having a structure including at least one OTS can be manufactured.

[0125] At this time, in both the gate first process-based manufacturing method and the gate replacement process-based manufacturing method, the manufacturing system can form at least one OTS with a semiconductor material that is selectively turned on or turned off by a voltage applied to a bit line (BL) connected to the upper portion of each of the vertical structures (VS) or a source line (CS) connected to the lower portion of each of the vertical structures (VS) during memory operation.

[0126] Accordingly, when at least one OTS is selectively turned on or off during a memory operation, a vertical structure (VS) including a target memory cell can be selected to enable a memory operation.

[0127] Below, the detailed process for manufacturing a 3D random access memory using a gate-first process-based manufacturing method is described with reference to drawings. In the case of a gate replacement process-based manufacturing method, only the step of removing sacrificial layers (SAC) to form gate electrodes (EL) is added to the gate-first process-based manufacturing method, and therefore a detailed description thereof will be omitted.

[0128] FIGS. 8A to 8G are drawings for explaining a method for manufacturing a three-dimensional random access memory according to one embodiment.

[0129] First, the manufacturing system can prepare a semiconductor structure (SEMI-STR) including gate electrodes (EL) that are vertically spaced and stacked while extending horizontally on a source line (CS) and a lower OTS (OTS-L) as shown in FIGS. 8a and 8b in the first step. Interlayer insulating layers (ILD) can be interposed between the gate electrodes (EL) in the semiconductor structure (SEMI-STR).

[0130] Next, the manufacturing system can extend vertical holes (H) penetrating vertically on the semiconductor structure (SEMI-STR) as shown in FIG. 8c in the second step.

[0131] Next, the manufacturing system can extend and form a data storage pattern (DSP) and a vertical conductive pattern (VE) within each of the vertical holes (H) as illustrated in FIG. 8d in the third step.

[0132] Next, the manufacturing system can etch the upper region corresponding to the data storage pattern (DSP) and the vertical conductive pattern (VE) on the semiconductor structure (SEMI-STR) as shown in FIG. 8e in the fourth step.

[0133] Thereafter, the manufacturing system can form an upper OTS (OTS-U) in the etched upper region as illustrated in FIG. 8f in the fifth step and form a bit line (BL) thereon. Although the formation of the bit line (BL) has been simplified and illustrated and described as a structure in which the bit line (BL) directly contacts the upper OTS (OTS-U), the case including the bit line plug (BLPG) as illustrated in FIG. 3 can also be described as forming the bit line plug (BLPG) so as to contact the upper OTS (OTS-U) and forming the bit line (BL) thereon.

[0134] In addition, the described manufacturing method is not limited or restricted thereto, and the fourth and fifth steps may be performed differently or omitted. For example, as the fourth step described above is omitted, the manufacturing system may sequentially form an upper OTS and a bit line (BL) in an area corresponding to a data storage pattern (DSP) and a vertical conductive pattern (VE) on a semiconductor structure (SEMI-STR) in the fifth step, as illustrated in FIG. 8g.

[0135] Although a method for manufacturing a three-dimensional random access memory having a structure in which each of the vertical structures (VS) includes two OTSs (lower OTS, upper OTS) has been described, a three-dimensional random access memory having a structure in which each of the vertical structures (VS) includes one OTS (upper OTS; OTS-U) can also be manufactured similarly.

[0136] For example, instead of preparing a semiconductor structure (SEMI-STR) on a source line (CS) and at least one OTS (lower OTS; OTS-L) in the first step, by preparing a semiconductor structure (SEMI-STR) on the source line (CS) (while performing the remaining steps in the same manner), a three-dimensional random access memory having a structure in which each of the vertical structures (VS) includes one OTS (upper OTS; OTS-U) can be manufactured.

[0137] FIGS. 9A to 9G are drawings for explaining a method for manufacturing a three-dimensional random access memory according to another embodiment.

[0138] First, the manufacturing system can prepare a semiconductor structure (SEMI-STR) by turning over the vertical structures (VS) formed therein, which includes gate electrodes (EL) that are horizontally extended and vertically spaced apart and stacked as shown in FIGS. 9a and 9b in the first step. Interlayer insulating layers (ILD) can be interposed between the gate electrodes (EL) in the semiconductor structure (SEMI-STR).

[0139] At this time, each of the vertical structures (VS) may include a data storage pattern (DSP), a vertical conductive pattern (VE), and an upper OTS (OTS-U), and a bit line (BL) may be formed on the upper portion of the upper OTS (OTS-U).

[0140] Although it is simplified and illustrated and described as a state in which a bit line (BL) is in direct contact with the upper portion of an upper OTS (OTS-U) in a semiconductor structure (SEMI-STR), the case in which a bit line plug (BLPG) is included as illustrated in FIG. 3 can also be described as a structure in which a bit line plug (BLPG) is positioned to contact the upper OTS (OTS-U) and a bit line (BL) is positioned above it.

[0141] Next, the manufacturing system can etch areas corresponding to the data storage pattern (DSP) and the vertical conductive pattern (VE) on the flipped semiconductor structure (SEMI-STR) as shown in FIG. 9c in a second step.

[0142] Next, the manufacturing system can form a lower OTS (OTS-L) in the etched area as shown in FIG. 9d in the third step.

[0143] Afterwards, the manufacturing system can form a source line (CS) on the lower OTS (OTS-L) as illustrated in FIG. 9e in the fourth step.

[0144] In addition, the described manufacturing method is not limited or restricted thereto, and the second, third, and fourth steps may be performed differently or omitted. For example, as the second step described above is omitted, the manufacturing system may form a lower OTS (OTS-L) directly in an area corresponding to a data storage pattern (DSP) and a vertical conductive pattern (VE) on a semiconductor structure (SEMI-STR) as illustrated in FIG. 9f in the third step, and form a source line (CS) on the lower OTS (OTS-L) as illustrated in FIG. 9g in the fourth step.

[0145] Although a method for manufacturing a three-dimensional random access memory having a structure in which each of the vertical structures (VS) includes two OTSs (lower OTS, upper OTS) has been described, a three-dimensional random access memory having a structure in which each of the vertical structures (VS) includes one OTS (upper OTS; OTS-U) can be manufactured by forming a source line (CS) in an area corresponding to a data storage pattern (DSP) and a vertical conductive pattern (VE) on an inverted semiconductor structure (SEMI-STR) after only the first step is performed.

[0146] FIG. 10 is a simplified circuit diagram illustrating a three-dimensional random access memory according to embodiments.

[0147] Referring to FIG. 10, a three-dimensional random access memory according to one embodiment may include a plurality of bit lines (BL1, BL2), a common source (CS; hereinafter, “source”), and a plurality of vertical electrodes (VE; hereinafter, “vertical conductive patterns”) connecting the bit lines. Each of the plurality of vertical electrodes (VE) may constitute a plurality of memory cell strings (CSTR; hereinafter, “cell strings”).

[0148] The bit lines (BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0149] Each of the bit lines (BL1, BL2) may have a plurality of cell strings (CSTR) connected in parallel. Each of the cell strings (CSTR) includes a vertical electrode (VE), and thus, a plurality of bit lines (BL1, BL2) and a plurality of vertical electrodes (VE) may be connected in parallel.

[0150] Cell strings (CSTR) may be commonly connected to a source (CS) provided between bit lines (BL1, BL2) and a common source (CS).

[0151] At this time, the source (CS) may be implemented in a plate shape so as to be shared by the cell strings (CSTR) constituting the array, but is not limited thereto and may be implemented in a line shape so as to be shared only by the cell strings (CSTR) included in the same row or column. When the source (CS) is implemented in a line shape, a plurality of sources (CS) may be provided, and the plurality of sources (CS) may be two-dimensionally arranged while extending in the first direction (D1) and spaced apart from each other along the second direction (D2). The plurality of sources (CS) may be electrically applied with the same voltage, but is not limited thereto and each of the plurality of sources (CS) may be electrically independently controlled so as to be applied with different voltages.

[0152] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may include memory cell transistors (MCT) arranged corresponding to word lines (WL1, WL2, WL3, ..., WLn), bit line select transistors (BLST1, BLST2) arranged corresponding to bit line select lines (BLSL1, BLSL2), and source select transistors (CSST1, CSST2) arranged corresponding to source select lines (CSSL1, CSSL2). Each of the memory cell transistors (MCT) may include a data storage element.

[0153] More specifically, one cell string (CSTR) may be composed of one bit line select transistor (BLST1, BLST2) positioned at the top of the string closest to the bit lines (BL1, BL2), a plurality of memory cell transistors (MCT) having different distances from the bit lines (BL1, BL2), and one source select transistor (CSST1, CSST2) positioned at the bottom of the string closest to the source (CS). That is, the memory cell transistors (MCT) may be connected in series while being arranged along the third direction (D3).

[0154] The bit line select transistors (BLST1, BLST2) can be controlled by the bit line select lines (BLSL1, BLSL2), the memory cell transistors (MCT) can be controlled by the word lines (WL1, WL2, WL3, ..., WLn), and the source select transistors (CSST1, CSST2) can be controlled by the source select lines (CSSL1, CSSL2).

[0155] Here, the gate electrodes (EL-BLSL) of the bit line select transistors (BLST1, BLST2) may be connected to the bit line select lines (BLSL1, BLSL2) and may be in an equipotential state, the gate electrodes (EL-WL) of the memory cell transistors (MCT) may be commonly connected to one of the word lines (WL1, WL2, WL3, ..., WLn) and may be in an equipotential state, and the gate electrodes (EL-CSSL) of the source select transistors (CSST1, CSST2) may be connected to the source select lines (CSSL1, CSSL2) and may be in an equipotential state.

[0156] Although the bit line select transistors (BLST1, BLST2) and the source select transistors (CSST1, CSST2) are described as being formed as a single layer, they are not limited thereto and may be formed as multiple layers along the vertical direction (e.g., the third direction (D3)). Accordingly, the bit line select lines (BLSL1, BLSL2) and the source select lines (CSSL1, CSSL2) may also be formed as multiple layers along the vertical direction (e.g., the third direction (D3)).

[0157] The bit line selection lines (BLSL1, BLSL2) can be implemented in the form of lines so that they are shared only by the cell strings (CSTR) included in the same row or column. Here, the bit line selection lines (BLSL1, BLSL2) can be arranged two-dimensionally so as to extend in a direction orthogonal to the bit lines (BL1, BL2) on a plane (e.g., a first direction (D1)) and to be spaced apart from the bit lines (BL1, BL2) on a plane (e.g., a second direction (D2)).

[0158] The word lines (WL1, WL2, WL3, ..., WLn) can be implemented in the form of plates so as to be shared by the cell strings (CSTR) constituting the array.

[0159] The source selection lines (CSSL1, CSSL2) can be implemented in the form of lines so that they are shared only by cell strings (CSTR) included in the same row or column. Here, the source selection lines (CSSL1, CSSL2) can be arranged two-dimensionally, extending in a direction orthogonal to the bit lines (BL1, BL2) on the plane (e.g., a first direction (D1)) and spaced apart from the bit lines (BL1, BL2) on the plane (e.g., a second direction (D2)).

[0160] FIG. 11 is a plan view illustrating a three-dimensional random access memory according to embodiments, FIG. 12 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, FIGS. 13 to 16 are cross-sectional views illustrating a three-dimensional random access memory according to another embodiment, corresponding to a cross-section taken along line A-A' of FIG. 11, and FIGS. 17 to 18 are drawings for explaining an operating method of a three-dimensional random access memory according to embodiments.

[0161] Referring to the drawings, the laminated structure (ST) can be formed to extend in the first direction (D1) and the second direction (D2). In the drawings, the laminated structure (ST) is illustrated as one, but is not limited thereto, and a plurality of laminated structures (ST) may be provided and arranged two-dimensionally while being spaced apart from each other along one direction (the first direction (D1) or the second direction (D2)).

[0162] The stacked structure (ST) may include gate electrodes (EL: EL-BLSL, EL-WL, EL-CSSL) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)). The stacked structure (ST) may have a substantially flat upper surface. Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0163] Although omitted in the drawing, the stacked structure (ST) may exist in a state of being arranged on the substrate (SUB) before the formation of the source (CS). That is, the stacked structure (ST) is manufactured by alternately stacking gate electrodes (EL: EL-BLSL, EL-WL, EL-CSSL) and interlayer insulating layers (ILD) on the substrate (SUB), and then the substrate (SUB) is removed during the formation of the source (CS), so that the stacked structure (ST) may not include the substrate (SUB). However, the stacked structure (ST) is not limited thereto, and may have a structure that includes the substrate (SUB) as the source (CS) is formed through a process such as implanting impurities into the substrate (SUB).

[0164] The substrate (SUB) may be a semiconductor substrate, such as a substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0165] Referring again to FIG. 10, the gate electrode (EL-BLSL) may be a bit line select line (BLSL1, BLSL2), the gate electrode (EL-CSSL) may be a source select line (CSSL1, CSSL2), and each of the gate electrodes (EL-WL) may be one of the word lines (WL1, WL2, WL3, ..., WLn) sequentially stacked on the substrate (SUB), and may be a component used as a conductor in a three-dimensional random access memory.

[0166] Each of the gate electrodes (EL-WL) may be formed in a plate shape extending in the first direction (D1) and also extending in the second direction (D2), and may be shared by an array of vertical structures (VS; cell strings in FIG. 1), and may have a substantially identical thickness in the third direction (D3). Hereinafter, the thickness refers to the thickness in the third direction (D3).

[0167] Similarly, the gate electrode (EL-CSSL) may be formed in a plate shape extending in the first direction (D1) and also extending in the second direction (D2) and may be shared by an array of vertical structures (VS).

[0168] The gate electrode (EL-BLSL) may be formed in a line shape so as to extend in the first direction (D1) and be shared by vertical structures (VS) included in the same row or column. The formation of the gate electrode (EL-BLSL) in a line shape may be achieved by a separation trench (BLSLT) that separates the gate electrode (EL-BLSL), as illustrated in FIG. 11.

[0169] Each of these gate electrodes (EL: EL-BLSL, EL-WL, EL-CSSL) can be formed of a conductive material. For example, each of the gate electrodes (EL: EL-BLSL, EL-WL, EL-CSSL) can be formed of at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL: EL-BLSL, EL-WL, EL-CSSL) can include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0170] Although not shown, one of the upper and lower ends of each of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL: EL-BLSL, EL-WL, EL-CSSL) of the stacked structures (ST) may have a length in the first direction (D1) that decreases from the bottom to the top in the vertical direction. For example, the gate electrode positioned at the top among the gate electrodes (EL: EL-BLSL, EL-WL, EL-CSSL) may have the shortest length in the first direction (D1), and the gate electrode positioned at the bottom among the gate electrodes (EL: EL-BLSL, EL-WL, EL-CSSL) may have the longest length in the first direction (D1).

[0171] However, without being limited or restricted thereto, the end of the laminated structure (ST) may have a step structure along the second direction (D2).

[0172] Although each of the interlayer insulating layers (ILDs) is illustrated as having the same thickness, it is not limited thereto and may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between gate electrodes (EL). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0173] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, an air gap may be interposed between the gate electrodes (EL) while the gate electrodes (EL) are stacked while being spaced apart from each other in the vertical direction (e.g., the third direction (D3)).

[0174] A plurality of vertical holes (H) penetrating a portion of the stacked structures (ST) may be provided. Vertical structures (VS) may be provided within the vertical holes (H). The vertical structures (VS) may be formed as a plurality of cell strings (CSTR) as illustrated in FIG. 10, and may extend in a third direction (D3) while being connected to bit lines (BL1, BL2) and a source (CS).

[0175] The vertical structures (VS) may be connected to the bit lines (BL1, BL2) by indirectly contacting the upper surfaces of each of the vertical structures (VS) with the lower surfaces of the bit lines (BL1, BL2) through another structure (e.g., a bit line plug (BLPG)). However, without being limited thereto, the vertical structures (VS) may be connected to the bit lines (BL1, BL2) by directly contacting the upper surfaces of each of the vertical structures (VS) with the lower surfaces of the bit lines (BL1, BL2).

[0176] The vertical structures (VS) may be connected to the source (CS) by having the lower surface of each of the vertical structures (VS) directly contact the upper surface of the source (CS). However, without limitation or restriction thereto, the vertical structures (VS) may also be connected to the source (CS) by having the lower surface of each of the vertical structures (VS) indirectly contact the upper surface of the source (CS) through another structure.

[0177] The rows of vertical structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL) are formed in a plate shape, the vertical structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL). For example, as illustrated in FIG. 11, eight vertical structures (VS) may form four columns and four rows and penetrate one of the stacked structures (ST). However, the number of vertical structures (VS) forming the array is not limited or restricted thereto.

[0178] As vertical structures (VS) are formed in a plate shape to form an array of multiple columns and rows on a horizontal plane of gate electrodes (EL), the three-dimensional random access memory can have a structure in which the integration of memory cell strings is improved.

[0179] At this time, the vertical structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on the horizontal plane and to be misaligned with each other. For example, the vertical structures (VS) included in the first column may be arranged in the first and third rows, and the vertical structures (VS) included in the second column may be arranged in the second and fourth rows, such that the vertical structures (VS) included in the pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string may be further improved compared to the case where the vertical structures (VS) included in the pair of adjacent columns are arranged side by side in the same row on the horizontal plane.

[0180] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical structures (VS) is depicted as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0181] These vertical structures (VS) may correspond to the cell strings (CSTR) illustrated in FIG. 10.

[0182] To this end, each of the vertical structures (VS) may include a data storage pattern (DSP), a vertical conductive pattern (VE), and two selection transistors (BLST, CSST). In each of the vertical structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with the top and bottom ends open, and the vertical conductive pattern (VE) may have a shape that fills a space from the top to a certain depth and a certain height from the bottom of the inner space of the data storage pattern (DSP) while being surrounded on the outside by the data storage pattern (DSP), and each of the two selection transistors (BLST, CSST) may have a shape that fills a space from the top to a certain depth and a space from the bottom to a certain height from the bottom of the inner space of the data storage pattern (DSP) while being surrounded on the outside by the data storage pattern (DSP). That is, the two selection transistors (BLST, CSST) can be arranged on the upper and lower sides of the vertical conductive pattern (VE) by being located at the uppermost and lowermost sides (the uppermost and lowermost sides of the vertical structure (VS)) of the inner space of the data storage pattern (DSP), respectively.

[0183] The data storage pattern (DSP) surrounds the outer sidewall of the vertical conductive pattern (VE) and can be in contact with the sidewalls of the gate electrodes (EL) toward the outside. Accordingly, regions corresponding to the gate electrodes (EL-WL) among the data storage pattern (DSP) can constitute memory cells in which a memory operation (a write operation including a program operation and an erase operation, and a read operation) is performed by a voltage applied through the gate electrodes (EL-WL) and a voltage applied to the vertical conductive pattern (VE). Hereinafter, applying a voltage to the vertical conductive pattern (VE) means that a voltage is applied to a bit line (BL) and a source (CS) selectively connected to the vertical conductive pattern (VE) and transmitted to the vertical conductive pattern (VE).

[0184] The memory cells correspond to the memory cell transistors (MCT) illustrated in Fig. 10. To this end, the data storage pattern (DSP) may be a polarization-generating dielectric pattern, which is a data storage element that generates a polarization phenomenon by a voltage applied through gate electrodes (EL-WL) and a voltage applied to a vertical conductive pattern (VE), thereby representing a data value as a change in voltage, current, or resistance corresponding to the polarization state of charges.

[0185] For example, as a data storage pattern (DSP), at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx or InOx can be used.

[0186] As another example, antiferroelectric materials can be used as data storage patterns (DSPs), and ZrO is an antiferroelectric material. x , Zr a X b O x (X may include Hf, Si, Al, Ge or one of the elements in group 2 of the periodic table) may be used.

[0187] Although the drawing shows the data storage pattern (DSP) as extending in a vertical direction (e.g., a third direction (D3)), it is not limited thereto and may have a structure of multiple segments spaced apart only in areas corresponding to the gate electrodes (EL-WL) on the outer wall of the vertical conductive pattern (VE).

[0188] The vertical conductive pattern (VE) is a component used as a conductor rather than a channel in a 3D random access memory, and, like the gate electrodes (EL), can be formed of at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0189] These vertical conductive patterns (VE) can be selectively connected to a bit line (BL) or a source (CS) through selection transistors (BLST, CSST) located at the upper and lower portions of each of the vertical structures (VS). Hereinafter, the fact that the bit line (BL) or the source (CS) is selectively connected to the vertical conductive pattern (VE) does not mean that the bit line (BL) or the source (CS) is physically in contact with and connected to the vertical conductive pattern (VE), but that the vertical conductive pattern (VE) is electrically connected to the bit line (BL) or the source (CS) so as to receive a voltage applied to the bit line (BL) or the source (CS).

[0190] To this end, selection transistors (BLST, CSST) are selectively turned on or off depending on the voltage applied through the corresponding gate electrodes (EL-BLSL, EL-CSSL) during memory operation, and can serve as selectors that selectively connect the vertical structures (VS) (more precisely, the vertical conductive pattern (VE) of each of the vertical structures (VS)) to the bit line (BL) or the source (CS).

[0191] For example, a selected vertical structure (Sel VS; the selected vertical structure includes a target memory cell that is a target of a memory operation) among the vertical structures (VS) can be connected to a bit line (BL) in response to a bit line select transistor (BLST) being turned on and a source select transistor (CSST) being turned off in the selected vertical structure (Sel VS) during a memory operation.

[0192] As another example, among the vertical structures (VS), an unselected vertical structure (Unsel VS; an unselected vertical structure does not include a target memory cell that is a target of a memory operation) can be connected to a source (CS) in response to a bit line select transistor (BLST) being turned off and a source select transistor (CSST) being turned on in the unselected vertical structure (Unsel VS) during a memory operation (at this time, since the source (CS) is grounded, the unselected vertical structure (Unsel VS) is actually connected to the ground).

[0193] At this time, the turn-on of the bit line select transistor (BLST) can be achieved by applying a turn-on voltage to the bit line select line (BLSL), and the turn-off of the bit line select transistor (BLST) can be achieved by applying a turn-off voltage to the bit line select line (BLSL).

[0194] Similarly, the turn-on of the source select transistor (CSST) can be achieved by applying a turn-on voltage to the source select line (CSSL), and the turn-off of the source select transistor (CSST) can be achieved by applying a turn-off voltage to the source select line (CSSL).

[0195] In this way, the selection transistors (BLST, CSST) are selectively turned on or off and can be formed of a semiconductor material (e.g., polycrystalline silicon, an oxide semiconductor material, a doped semiconductor material, etc.) that selectively forms a channel according to a voltage applied through the corresponding gate electrodes (EL-BLSL, EL-CSSL) during memory operation, in order to serve as a selector that selectively connects the vertical structures (VS) (more precisely, the vertical conductive pattern (VE) of each of the vertical structures (VS)) to the bit line (BL) or the source (CS).

[0196] In addition, the two selection transistors (BLST, CSST) may have a structure including a buried pattern (VFP) therein, as illustrated in FIG. 13. For example, a buried pattern (VFP) may be formed inside each of the two selection transistors (BLST, CSST) with a material that facilitates the diffusion of charges or holes (e.g., an intrinsic semiconductor material or a polycrystalline semiconductor material having excellent charge / hole mobility) to facilitate the formation of a channel by each of the two selection transistors (BLST, CSST). However, the function of the buried pattern (VFP) and the material forming the buried pattern (VFP) are not limited to or restricted to the described examples.

[0197] At this time, the two selection transistors (BLST, CSST) are not limited or restricted to the described structure, and may be implemented in a structure in which they are arranged above and below the data storage pattern (DSP) without being surrounded by the data storage pattern (DSP) as illustrated in FIG. 14. In this case as well, each of the two selection transistors (BLST, CSST) may include a buried pattern (VFP) as illustrated in FIG. 15.

[0198] The two selection transistors (BLST, CSST) are not limited or restricted to the structure described above, and may have a structure further including two dielectric patterns (DP) arranged on the upper and lower sides of the data storage pattern (DSP) to correspond to the two selection transistors (BLST, CSST), respectively, as illustrated in FIG. 16.

[0199] These two dielectric patterns (DP) play a role in resolving the problem that polarization may occur in the portions of the data storage pattern (DSP) corresponding to the two selection transistors (BLST, CSST) when the data storage pattern (DSP) is structured to extend to the regions corresponding to the two selection transistors (BLST, CSST) while the two selection transistors (BLST, CSST) are controlled by the selection lines (BLSL, CSSL).

[0200] That is, each of the two selection transistors (BLST, CSST) is surrounded by two dielectric patterns (DP) arranged on the upper and lower sides of the data storage pattern (DSP) so as to correspond to the two selection transistors (BLST, CSST), respectively, thereby solving the problem of polarization occurring in the portions of the data storage pattern (DSP) corresponding to the two selection transistors (BLST, CSST).

[0201] Although not depicted in a separate drawing, in the structure of vertical structures (VS) that also include a dielectric pattern (DP), each of the two selection transistors (BLST, CSST) can be implemented to include a buried pattern (VFP) therein.

[0202] At this time, at least two bit lines (BL1, BL2) are positioned at the same height on the upper portion of the vertical structures (VS), and the vertical structures (VS) arranged in the same row in the array may further include bit line plugs (BLPG) arranged at positions shifted from the centers of each of the vertical structures (VS) so as to be connected to different bit lines (BL1, BL2), respectively. That is, the vertical structures (VS) arranged in the same row in the array can be connected to different bit lines (BL1, BL2), respectively, through the bit line plugs (BLPG) arranged at positions shifted from the centers of each of the vertical structures (VS).

[0203] A separation trench (BLSLT) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). Insulating spacers (not shown) may be formed in the separation trench (BLSLT) to isolate the adjacent stacked structures (ST) from each other. For example, the insulating spacers may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant. The separation trench (BLSLT) may serve to isolate the gate electrode (EL-BLSL) as described above.

[0204] A capping insulating film (CAP) may be provided on the stacked structures (ST) and the vertical structures (VS). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0205] Bit lines (BL) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit lines (BL) may be formed by extending along a second direction (D2) with a conductive material while being spaced apart from each other along a first direction (D2). The conductive material forming the bit lines (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL).

[0206] As described, the three-dimensional random access memory can perform memory operations in response to a voltage applied between gate electrodes (EL) and vertical conductive patterns (VE) that are selectively connected to bit lines (BL) and sources (CS).

[0207] In particular, the three-dimensional random access memory can perform a memory operation by randomly accessing a target memory cell by selectively connecting the vertical conductive pattern (VE) of each of the vertical structures (VS) to a bit line (BL) or a source (VS) by selectively turning on or off selection transistors (BLST, CSST). Here, the fact that the bit line (BL) or the source (CS) is selectively connected to the vertical conductive pattern (VE) does not mean that the bit line (BL) or the source (CS) is physically in contact with and connected to the vertical conductive pattern (VE), but rather that the vertical conductive pattern (VE) is electrically connected to the bit line (BL) or the source (CS) so as to receive a voltage applied to the bit line (BL) or the source (CS).

[0208] For example, since the memory operation of a conventional 3D DRAM is performed through the application of voltages as illustrated in FIG. 17 and the turning on or off of one selection transistor (ST), voltages as shown in Table 1 below are applied to the memory cells. Hereinafter, the Sel memory cell of Sel VS refers to a target memory cell that is a target of the memory operation, and the voltage applied to the Sel memory cell of Sel VS represents a voltage for the memory operation. On the other hand, the Unsel memory cell of Sel VS, the Sel memory cell of Unsel VS, and the Unsel memory cell of Unsel VS refer to memory cells that are not target memory cells, and the voltages applied to the Unsel memory cell, the Sel memory cell of Unsel VS, and the Unsel memory cell of Unsel VS are voltages that interfere with the memory operation for the target memory cell, and are named "memory cell application interference voltages."

[0209] In addition, the target memory cell (Sel memory cell) of the unselected vertical structure (Unsel VS) hereinafter refers to a memory cell that is not a target of a memory operation and shares the same gate electrode (Sel EL) as the target memory cell (Sel memory cell; memory cell that is a target of a memory operation) of the selected vertical structure (Sel VS).

[0210] Table 1

[0211]

[0212] Here, in the unselected vertical structure (Unsel VS), the vertical conductive pattern (VE) is floated by the turned-off selection transistor (ST), and the floating vertical conductive pattern (VE) is applied to each of the unselected gate electrodes (Unsel WL) by a pass voltage ( ) by strong capacitive coupling, resulting in a pass voltage ( ) can be formed. Therefore, as shown in Table 1 above, in the Sel memory cell (830) of Unsel VS, A deviation in the memory cell applied disturbance voltage may occur within the unselected string (Unsel VS), such as when 0V is applied to the Unsel memory cell (840) of the Unsel VS. This , deviations in the memory cell input disturbance voltage such as 0V can cause memory performance degradation.

[0213] For another example, since the operation of the three-dimensional flash memory described with reference to FIGS. 10 to 16 is performed through the application voltages as shown in FIG. 18 and the turning on or off of two selection transistors (BLST, CSST), voltages as shown in Table 2 below are applied to the memory cells.

[0214] Table 2

[0215]

[0216] For a more specific example, a selected vertical structure (Sel VS) among the vertical structures (VS) is connected to a bit line (BL) in response to a bit line select transistor (BLST) being turned on and a source select transistor (CSST) being turned off in the selected vertical structure (Sel VS) during a memory operation. Accordingly, in the target memory cell (910) in the selected vertical structure (Sel VS), A voltage such as , is applied, and in the selected vertical structure (Sel VS), the unselected memory cell (920) A voltage such as can be applied.

[0217] On the other hand, among the vertical structures (VS), the unselected vertical structure (Unsel VS) is connected to the source (CS) in response to the bit line select transistor (BLST) being turned off and the source select transistor (CSST) being turned on in the unselected vertical structure (Unsel VS) during memory operation (at this time, since the source (CS) is grounded, the unselected vertical structure (Unsel VS) is actually connected to the ground). Therefore, in the target memory cell (930) in the unselected vertical structure (Unsel VS), A voltage such as , is applied, and in the unselected vertical structure (Unsel VS), the unselected memory cell (940) A voltage such as can be applied.

[0218] In this way, the input disturbance voltage of each memory cell within the unselected string (Unsel VS) does not have deviation. , memory performance can be improved by making it uniform.

[0219] FIG. 19 is a flow chart illustrating an operating method of a three-dimensional random access memory according to embodiments.

[0220] Hereinafter, the operating method described is assumed to be performed by a three-dimensional random access memory having a structure described with reference to FIGS. 10 to 16 and 18, and may mean a memory operation including any one of a program operation, a read operation, or an erase operation for a target memory cell.

[0221] In step (S1910), the three-dimensional random access memory can selectively turn on or off two selection transistors (BLST, CSST) included in each of the vertical structures (VS) according to a voltage applied through gate electrodes (EL-BLSL, EL-CSSL) corresponding to two of the selection transistors (BLST, CSST) among the gate electrodes (EL), thereby selectively connecting the vertical conductive pattern (VE) of each of the vertical structures (VS) to a bit line (BL) or a source (CS).

[0222] Here, selectively connecting the vertical conductive pattern (VE) to the bit line (BL) or the source (CS) does not mean physically contacting and connecting the vertical conductive pattern (VE) with the bit line (BL) or the source (CS) (the vertical conductive pattern (VE) is already physically contacting and connected with the bit line (BL) or the source (CS) during the manufacturing process), but rather means electrically connecting the vertical conductive pattern (VE) with the bit line (BL) or the source (CS) so that the vertical conductive pattern (VE) receives a voltage applied to the bit line (BL) or the source (CS).

[0223] For example, a three-dimensional random access memory can connect a vertical conductive pattern (VE) of a selected vertical structure (Sel VS) to a bit line (BL) in response to a bit line select transistor (BLST) being turned on and a source select transistor (CSST) being turned off in a selected vertical structure (Sel VS; the selected vertical structure includes a target memory cell that is a target of a memory operation) among two select transistors (BLST, CSST).

[0224] As another example, a three-dimensional random access memory can connect a vertical conductive pattern (VE) of an unselected vertical structure (Unsel VS; an unselected vertical structure does not include a target memory cell that is a target of a memory operation) among two select transistors (BLST, CSST) in response to a bit line select transistor (BLST) being turned off and a source select transistor (CSST) being turned on. Since the source (CS) is grounded during a memory operation, the unselected vertical structure (Unsel VS) can be connected to the ground in practice.

[0225] At this time, the turn-on of the bit line select transistor (BLST) can be achieved by applying a turn-on voltage to the bit line select line (BLSL), and the turn-off of the bit line select transistor (BLST) can be achieved by applying a turn-off voltage to the bit line select line (BLSL).

[0226] Similarly, the turn-on of the source select transistor (CSST) can be achieved by applying a turn-on voltage to the source select line (CSSL), and the turn-off of the source select transistor (CSST) can be achieved by applying a turn-off voltage to the source select line (CSSL).

[0227] Accordingly, in step (S1920), the three-dimensional random access memory can perform a memory operation on a target memory cell in response to each of the vertical structures (VS) being selectively connected to a bit line (BL) and a source (CS).

[0228] Figures 20 and 21 are flowcharts illustrating a manufacturing method of a three-dimensional random access memory according to embodiments. More specifically, Figure 20 is a flowchart illustrating a manufacturing method based on a gate first process, and Figure 21 is a flowchart illustrating a manufacturing method based on a gate replacement process.

[0229] The manufacturing method described below is for manufacturing a three-dimensional random access memory having the structure described above with reference to FIGS. 10 to 16 and FIG. 18, and is assumed to be performed by an automated and mechanized manufacturing system.

[0230] Referring to FIG. 20, in step S2010, the manufacturing system can prepare a semiconductor structure including gate electrodes (EL) that are horizontally extended, vertically spaced, and stacked. Interlayer insulating layers (ILDs) can be interposed between the gate electrodes (EL) in the semiconductor structure.

[0231] In step (S2020), the manufacturing system can extend vertical holes (H) that penetrate the semiconductor structure in a vertical direction.

[0232] In step (S2030), the manufacturing system can extend vertical structures (VS) that vertically penetrate gate electrodes (EL) within each of the vertical holes (H), each of the vertical structures (VS) including a data storage pattern (DSP), a vertical conductive pattern (VE), and two select transistors (BLST, CSST) respectively disposed on the upper and lower portions of the vertical conductive pattern (VE).

[0233] At this time, in step (S2030), the manufacturing system can form two selection transistors (BLST, CSST) with a semiconductor material that selectively forms a channel so as to be selectively turned on or off during memory operation.

[0234] Although not depicted as a separate step, the manufacturing system can horizontally extend bit lines (BL) on the upper portions of the vertical structures (VS) after step (S2030). In this process, the manufacturing system can connect the vertical conductive pattern (VE) included in each of the vertical structures (VS) to each of the bit lines (BL) through the bit line plug (BLPG). Here, connecting the vertical conductive pattern (VE) to each of the bit lines (BL) through the bit line plug (BLPG) means physically contacting and connecting the vertical conductive pattern (VE) and each of the bit lines (BL) in an indirect manner through the bit line plug (BLPG).

[0235] Additionally, the manufacturing system can form a source (CS) extending horizontally below the vertical structures (VS) after step (S2030). During this process, the manufacturing system can connect a vertical conductive pattern (VE) included in each of the vertical structures (VS) to the source (CS). Here, connecting the vertical conductive pattern (VE) to each of the bit lines (BL) means physically contacting and connecting the vertical conductive pattern (VE) and the source (CS).

[0236] The manufacturing method described above is a gate-first process. However, the manufacturing system may also utilize a gate replacement process in addition to the gate-first process. A detailed description of this will be provided below.

[0237] Referring to FIG. 21, in step S2110, the manufacturing system can prepare a semiconductor structure including sacrificial layers that are horizontally extended and vertically spaced apart and stacked. Interlayer insulating layers (ILDs) can be interposed between the sacrificial layers in the semiconductor structure.

[0238] In step (S2120), the manufacturing system can extend vertical holes (H) that penetrate the semiconductor structure in a vertical direction.

[0239] In step (S2130), the manufacturing system can extend vertical structures (VS) that vertically penetrate the sacrificial layers within each of the vertical holes (H), each of the vertical structures (VS) including a data storage pattern (DSP), a vertical conductive pattern (VE), and two select transistors (BLST, CSST) respectively disposed on the upper and lower portions of the vertical conductive pattern (VE).

[0240] At this time, in step (S2130), the manufacturing system can form two selection transistors (BLST, CSST) with a semiconductor material that selectively forms a channel so as to be selectively turned on or off during memory operation.

[0241] In step (S2140), the manufacturing system can remove the sacrificial layers to form gate electrodes (EL) in the spaces where the sacrificial layers are removed.

[0242] Although not depicted as a separate step, the manufacturing system can horizontally extend bit lines (BL) on the upper portions of the vertical structures (VS) after step (S2140). In this process, the manufacturing system can connect the vertical conductive pattern (VE) included in each of the vertical structures (VS) to each of the bit lines (BL) through the bit line plug (BLPG). Here, connecting the vertical conductive pattern (VE) to each of the bit lines (BL) through the bit line plug (BLPG) means physically contacting and connecting the vertical conductive pattern (VE) and each of the bit lines (BL) in an indirect manner through the bit line plug (BLPG).

[0243] Additionally, the manufacturing system can form a source (CS) extending horizontally below the vertical structures (VS) after step (S2140). During this process, the manufacturing system can connect a vertical conductive pattern (VE) included in each of the vertical structures (VS) to the source (CS). Here, connecting the vertical conductive pattern (VE) to each of the bit lines (BL) means physically contacting and connecting the vertical conductive pattern (VE) and the source (CS).

[0244] FIG. 22 is a perspective view schematically illustrating an electronic system including a three-dimensional random access memory according to embodiments.

[0245] Referring to FIG. 22, an electronic system (2200) including a three-dimensional random access memory according to embodiments may include a main substrate (2201), a controller (2202) mounted on the main substrate (2201), one or more semiconductor packages (2203), and a DRAM (2204).

[0246] The semiconductor package (2203) and DRAM (2204) can be interconnected with the controller (2202) by wiring patterns (2205) provided on the main substrate (2201).

[0247] The main board (2201) may include a connector (2206) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2206) may vary depending on the communication interface between the electronic system (2200) and the external host.

[0248] The electronic system (2200) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (2200) may operate by power supplied from an external host, for example, through a connector (2206). The electronic system (2200) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2202) and a semiconductor package (2203).

[0249] The controller (2202) can write data to the semiconductor package (2203) or read data from the semiconductor package (2203), and can improve the operating speed of the electronic system (2200).

[0250] The DRAM (2204) may be a buffer memory to mitigate the speed difference between the semiconductor package (2203), which is a data storage space, and an external host. The DRAM (2204) included in the electronic system (2200) may also function as a type of cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package (2203). When the electronic system (2200) includes the DRAM (2204), the controller (2202) may further include a DRAM controller for controlling the DRAM (2204) in addition to the NAND controller for controlling the semiconductor package (2203).

[0251] A semiconductor package (2203) may include first and second semiconductor packages (2203a, 2203b) that are spaced apart from each other. The first and second semiconductor packages (2203a, 2203b) may each be a semiconductor package including a plurality of semiconductor chips (2220). Each of the first and second semiconductor packages (2203a, 2203b) may include a package substrate (2210), semiconductor chips (2220) on the package substrate (2210), adhesive layers (2230) disposed on a lower surface of each of the semiconductor chips (2220), connection structures (2240) that electrically connect the semiconductor chips (2220) and the package substrate (2210), and a molding layer (2250) that covers the semiconductor chips (2220) and the connection structures (2240) on the package substrate (2210).

[0252] The package substrate (2210) may be a printed circuit board including package upper pads (2211). Each of the semiconductor chips (2220) may include input / output pads (2221). Each of the semiconductor chips (2220) may include the three-dimensional random access memory described above with reference to FIGS. 1 to 4 or FIGS. 10 to 16. More specifically, each of the semiconductor chips (2220) may include gate stack structures (2222) and memory structures (2223). The gate stack structures (2222) may correspond to the stack structures (ST) described above, and the memory structures (2223) may correspond to the vertical structures (VS) described above.

[0253] The connection structures (2240) may be, for example, bonding wires that electrically connect the input / output pads (2221) and the package upper pads (2211). Accordingly, in each of the first and second semiconductor packages (2203a, 2203b), the semiconductor chips (2220) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (2211) of the package substrate (2210). According to embodiments, in each of the first and second semiconductor packages (2203a, 2203b), the semiconductor chips (2220) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (2240).

[0254] Unlike the illustration, the controller (2202) and the semiconductor chips (2220) may be included in a single package. The controller (2202) and the semiconductor chips (2220) may be mounted on a separate interposer substrate different from the main substrate (2201), and the controller (2202) and the semiconductor chips (2220) may be connected to each other by wiring provided on the interposer substrate.

[0255] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0256] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. [Broadly rights a three-dimensional random access memory having a structure including at least one OTS located at at least one end of the upper or lower end of a string] Gate electrodes that are formed horizontally and are spaced apart vertically and stacked; and Vertical structures extending in the vertical direction and penetrating the gate electrodes, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) positioned at at least one end of the top or bottom of each of the vertical structures. A three-dimensional random access memory containing .

2. [Configuration in which at least one OTS is located at the end regardless of the position of the gate electrode] In the first paragraph, At least one OTS above, A three-dimensional random access memory characterized in that, instead of being positioned corresponding to the gate electrodes, the gate electrodes are positioned corresponding to at least one end of the upper or lower end of each of the vertical structures.

3. [A configuration in which at least one OTS is selectively turned on / off by a voltage applied to BL or SL so that each string is selected] In the second paragraph, At least one OTS above, A three-dimensional random access memory characterized in that each of the vertical structures is selectively turned on or off by a voltage applied to a bit line connected to the upper portion of each of the vertical structures or a source line connected to the lower portion of each of the vertical structures during memory operation, thereby selecting each of the vertical structures.

4. [Detailed composition of claim 3: Select the selected vertical structure] In the third paragraph, Among the above vertical structures, any one of the vertical structures including a target memory cell that is the target of the memory operation, A three-dimensional random access memory characterized in that the OTS is selected in response to the at least one OTS being turned on in the vertical structure during the memory operation.

5. [Detailed composition of claim 3: Unselected vertical structure] In the third paragraph, At least one vertical structure among the above vertical structures that does not include a target memory cell that is the target of a memory operation, A three-dimensional random access memory characterized in that the at least one OTS in the at least one vertical structure is not selected in response to being turned off during the memory operation.

6. [Detailed location of at least one OTS] In the first paragraph, At least one OTS above, A three-dimensional random access memory characterized in that each of the above vertical structures is located at least one of the upper or lower portions of the data storage pattern and the vertical conductive pattern.

7. [Memory operation method of a three-dimensional random access memory having the structure of claim 1: Selectively connecting a vertical channel structure to a bit line or source] A memory operation method of a three-dimensional random access memory, comprising: gate electrodes formed to extend horizontally and spaced apart vertically and stacked; and vertical structures formed to extend vertically through the gate electrodes, each of the vertical structures including a data storage pattern, a vertical conductive pattern, and two selection transistors respectively disposed above and below the vertical conductive pattern; A step of selectively turning on or off the two selection transistors included in each of the vertical structures to selectively connect each of the vertical structures to a bit line or a source; and A step of performing a memory operation on a target memory cell in response to each of the above vertical structures being selectively connected to the bit line and the source. A memory operation method of a three-dimensional random access memory including .

8. [Bit line connection configuration] In paragraph 7, The above connecting step is, A step of connecting the selected vertical structure to the bit line in response to a bit line select transistor among the two select transistors being turned on and a source select transistor being turned off in a selected vertical structure among the above vertical structures, the selected vertical structure including a target memory cell to be the target of a memory operation. A memory operation method of a three-dimensional random access memory, characterized in that it includes.

9. [Configure Source Connection] In paragraph 7, The above connecting step is, A step of connecting the unselected vertical structure to the source in response to a bit line select transistor among the two select transistors being turned off and a source select transistor being turned on in an unselected vertical structure among the above vertical structures, the unselected vertical structure not including a target memory cell that is a target of a memory operation. A memory operation method of a three-dimensional random access memory, characterized in that it includes.

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