Epitaxial digit line growth in vertical three-dimensional (3D) memory

Abstract

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source / drain regions and a second source / drain regions separated by channel regions. Gates at the channel regions formed fully around every surface of the channel region as gate-all-around (GAA) structures separated from channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes connected to the second source / drain regions and digit lines connected to the first source / drain regions.

Description

EPITAXIAL DIGIT LINE GROWTH IN VERTICAL THREE- DIMENSIONAL (3D) MEMORYTECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices, and more particularly, to epitaxial digit line growth in vertical three-dimensional (3D) memory.BACKGROUND

[0002] Memory' is often implemented in electronic systems, such as computers, cell phones, hand-held devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and may include random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), and synchronous dynamic random-access memory (SDRAM). Non-volatile memory may provide persistent data by retaining stored data when not powered and may include NAND flash memory', NOR flash memory', nitride read only memory (NROM), phase-change memory (e.g., phase-change random access memory ), resistive memory' (e.g., resistive randomaccess memory), cross-point memory’, ferroelectric random-access memory (FeRAM), or the like.

[0003] As design rules shrink, less semiconductor space is available to fabricate memory', including DRAM arrays. A respective memory' cell for DRAM may include an access device, e.g.. transistor, having a first and a second source / drain regions separated by epitaxially grown channel regions. A gate may oppose the channel region and be separated therefrom by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of the DRAM cell. A DRAM cell can include a storage node, such as a capacitor cell, connected by the access device to a digit line. The access device can be activated (e.g., to select the cell) by an access line connected to the access transistor. The capacitor can store a charge corresponding to a data value of a respective cell (e.g., a logic “1” or “0”).BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A is a schematic illustration of a horizontal access device in a vertical three-dimensional (3D) memory in accordance a number of embodiments of the present disclosure.

[0005] Figure IB is a perspective view illustrating a portion of a horizontal access device in vertical three-dimensional (3D) memory in accordance with a number of embodiments of the present disclosure.

[0006] Figure 2 illustrates a portion of a horizontal access device in vertical three-dimensional (3D) memory in accordance with a number of embodiments of the present disclosure.

[0007] Figure 3 illustrates a portion of a vertical 3D memory array in accordance with a number of embodiments of the present disclosure.

[0008] Figure 4 is a cross-sectional view, at one stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory in accordance with a number of embodiments of the present disclosure.

[0009] Figures 5A to 5B illustrate an example method, at one stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memoiy, in accordance with a number of embodiments of the present disclosure.

[0010] Figures 6A to 6D illustrate an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memoiy, in accordance with a number of embodiments of the present disclosure.

[0011] Figures 7A to 7B illustrate an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, in accordance with a number of embodiments of the present disclosure.

[0012] Figures 8A to 8B illustrate an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, in accordance with a number of embodiments of the present disclosure.

[0013] Figures 9A to 9C illustrate an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in verticalthree-dimensional (3D) memory, in accordance with a number of embodiments of the present disclosure.

[0014] Figures 10A to 10C illustrate an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, in accordance with a number of embodiments of the present disclosure.

[0015] Figures 11 A to 1 IB illustrate an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memoty, in accordance with a number of embodiments of the present disclosure.

[0016] Figure 12 illustrates an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, in accordance with a number of embodiments of the present disclosure.

[0017] Figures 13A to 13B illustrate an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, in accordance with a number of embodiments of the present disclosure.

[0018] Figures 14A to 14B illustrate an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, in accordance with a number of embodiments of the present disclosure.

[0019] Figures 15A to 15B illustrate an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, in accordance with a number of embodiments of the present disclosure.

[0020] Figures 16A to 16E illustrate an example method, at a stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, in accordance with a number of embodiments of the present disclosure.

[0021] Figure 17 is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure.DETAILED DESCRIPTION

[0022] Embodiments of the present disclosure describe epitaxial digit line growth in vertical three-dimensional (3D) memory'. A vertically oriented digit line is formed with horizontally oriented access devices and access lines in an array of vertically stacked memory cells. The horizontal access devices are integrated with horizontally oriented access lines having a first source / drain regions and a second source / drain regions separated by channel regions and integrated with vertically oriented digit lines. In vertically stacked memory array structures, such as transistor structures, poly crystalline silicon (also referred to as polysilicon) can be leaky, allowing current to leak through the poly crystalline structure, making the transistor less effective. Single crystal silicon is not very leaky. However, single crystal silicon cannot grow on amorphous dielectric materials, such as oxides or nitndes. which are the common materials upon which transistors are formed.

[0023] However, as disclosed in the embodiments of the present disclosure, it is possible to use a silicon wafer for a transistor that can be utilized as a substrate during the high temperature processes required for single crystal silicon formation. In such embodiments, a layer of silicon germanium can be grown on the silicon substrate. Single crystal silicon can, then, be grown on the silicon germanium.

[0024] This may be accomplished, for example, by providing a thin single crystal silicon germanium layer, as a seed layer, and then forming the single crystal silicon germanium layer thickness. Once the desired layer thickness is formed, a silicon layer can be formed into the surface of the silicon germanium layer. As with the silicon germanium layer, this may be accomplished, for example, by providing a thin single crystal silicon layer, as a seed layer, and then forming the thin single crystal silicon layer thickness into a thicker single crystal silicon layer.

[0025] Depending on the silicon germanium concentration, if silicon is x quantity and germanium is y quantity and, if y is smaller than x. then silicon / silicon germanium has a small lattice mismatch with respect to the lattice of single crystal silicon. This allows silicon to be formed on top of silicon germanium with a single cry stal structure. If a thin layer of single crystal siliconis applied to the surface of the silicon germanium, then the whole silicon layer acts as a seed for the growth of the single crystal silicon layer. Such layering can be done in alternating iterations (e.g., SiGe / Si / SiGe / Si, etc.) to create a superlattice structure in the form of a vertical stack such as shown in Figure 4.

[0026] For example, a seed layer of silicon germanium can be formed that is 100 Angstroms in thickness (height) and can be grown to, for example 1000 Angstroms. A thin silicon seed layer can be formed on the surface of the silicon germanium layer that is, for example, 50 Angstroms and can be grown to a thickness of, for example, 300 Angstroms. These thicknesses are merely provided as examples and should not be regarded as limiting unless recited explicitly in a particular claim.

[0027] The transistor devices of the present disclosure will have better performance with regard to I-on, better I-off, drivability, and / or leakage current because there is no grain boundary and therefore current cannot leak through the grain boundary which is where leakage often occurs in polysilicon. In some embodiments, devices can have, for example, three orders of magnitude lower I- off (leakage).

[0028] Advantages to the structure and process described herein can include a lower off-current (loff) for the access devices, as compared to silicon based (Si-based) access devices (e.g., transistors), better DRAM refresh requirement, and / or reduced gate / drain induced leakage (GTDL) for the access devices. Combined with a gate all around (GAA) structure at the channel region of the semiconductor material, provides better electrostatic control on the channel, better subthreshold slope and a more cost-effective process.

[0029] During formation of the 3D memory array, one step in the semiconductor fabrication process can include forming digit lines. In the process described herein, the digit lines can be vertically oriented in the 3D memory array. The digit lines can be formed in a vertical opening in the 3D memory array to conductively interconnect memory cells along vertical columns.

[0030] In some examples, the vertical columns are high aspect ratio spaces. Therefore, epitaxially growing the vertically oriented digit lines within the vertical column can ensure that the digit lines extend the full depth of thevertical columns and continuously touch every Si channel in the vertical columns.

[0031] However, epitaxial growth of Si material can occur both vertically as well as horizontally. Accordingly, a risk of horizontal merging of Si material during epitaxial growth of the vertical digit line is present. If such horizontal merging occurs, laterally adjacent vertically oriented digit lines may be electrically shorted together.

[0032] Epitaxial digit line grow th in vertical 3D memory according to the disclosure can allow for epitaxial growth of vertical digit lines without horizontal merging occurring. Various mechanisms for preventing horizontal merging of epitaxially grown adjacent vertical digit lines can be utilized in order to prevent laterally adjacent vertically oriented digit lines from being electrically shorted together, as is described herein.

[0033] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the drawing and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, reference numeral 103 may reference element “03"’ in Figure 1, and a similar element may be referenced as 203 in Figure 2. Multiple analogous elements within one figure may be referenced with a reference numeral followed by a hyphen and another numeral or a letter. For example, 302-1 may reference element 302-1 in Figure 3 and 302-2 may reference element 302-2, which may be analogous to element 302-1. Such analogous elements may be generally referenced without the hyphen and extra numeral or letter. For example, elements 302-1 and 302-2 or other analogous elements may be generally referenced as 302.

[0034] Figure 1 A is a schematic illustration of a horizontal access device in a vertical three-dimensional (3D) memory in accordance a number of embodiments of the present disclosure. Figure 1 A illustrates a circuit diagram showing a cell array of a 3D semiconductor memory device according to embodiments of the present disclosure. Figure 1 A illustrates that a cell array may have a plurality of sub cell arrays 101-1, 101-2, . . ., 101-N. The sub cell arrays 101-1, 101-2, . . ., 101-N may be arranged along a second direction (D2) 105. Each of the sub cell arrays, e.g., sub cell array 101-2, may include aplurality of access lines 107-1, 107-2, . . ., 107-Q (which also may be referred to as word lines). Also, each of the sub cell arrays, e.g., sub cell array 101-2, may include a plurality of digit lines 103-1, 103-2, . . ., 103-Q (which also may be referred to as bit lines, data lines, or sense lines). In Figure 1 A, the access lines 107-1, 107-2, . . ., 107-Q are illustrated extending in a first direction (DI) 109 and the digit lines 103-1, 103-2, . . ., 103-Q are illustrated extending in a third direction (D3) 111. According to embodiments, the first direction (DI) 109 and the second direction (D2) 105 may be considered in a horizontal (“X-Y”) plane. The third direction (D3) 111 may be considered in a vertical (“Z”) plane. Hence, according to embodiments described herein, the digit lines 103-1, 103-2, . . ., 103-Q are extending in a vertical direction, e.g., third direction (D3) 111.

[0035] A memory cell, e.g., memory cell 110, may include an access device, e.g., access transistor, and a storage node located at an intersection of each access line 107-1, 107-2, . . ., 107-Q and each digit line 103-1, 103-2, . . ., 103-Q. Memory cells may be written to. or read from, using the access lines 107-1, 107-2, . . ., 107-Q and digit lines 103-1, 103-2, . . ., 103-Q. The access lines 107-1, 107-2, . . ., 107-Q may conductively interconnect memory cells along horizontal rows of each sub cell array 101-, 101-2, . . ., 101-N, and the digit lines 103-1, 103-2, . . ., 103-Q may conductively interconnect memory cells along vertical columns of each sub cell array 101-. 101-2, . . .. 101-N. One memory7cell, e.g. 1 10, may be located between one access line, e.g., 107-2, and one digit line, e.g., 103-2. Each memory' cell may be uniquely addressed through a combination of an access line 107-1, 107-2, . . ., 107-Q and a digit line 103-1, 103-2, . . ., 103-Q.

[0036] The access lines 107-1, 107-2, . . ., 107-Q may be or include conducting patterns (e.g., metal lines) disposed on and spaced apart from a substrate. The access lines 107-1, 107-2, . . ., 107-Q may extend in a first direction (DI) 109. The access lines 107-1, 107-2, . . ., 107-Q in one sub cell array, e.g., 101-2. may be spaced apart from each other in a vertical direction, e.g., in a third direction (D3) 111.

[0037] The digit lines 103-1, 103-2, . . ., 103-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction with respect to the substrate, e.g., in a third direction (D3) 111. The digit lines in onesub cell array, e.g., 101-2, may be spaced apart from each other in the first direction (DI) 109.

[0038] A gate of a memory cell, e.g., memory cell 110, may be connected to an access line, e.g., 107-2, and a first conductive node, e.g., first source / drain region, of an access device, e.g., transistor, of the memory7cell 110 may be connected to a digit line, e.g., 103-2. Each of the memory cells, e.g., memory cell 110. may be connected to a storage node, e.g., capacitor. A second conductive node, e.g., second source / drain region, of the access device, e.g., transistor, of the memory7cell 110 may be connected to the storage node, e.g., capacitor. While first and second source / drain region references are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain region referred to as the "‘first” and / or “second” source / drain regions have some unique meaning. It is intended only that one of the source / drain regions is connected to a digit line, e.g., 103-2, and the other may be connected to a storage node.

[0039] Figure IB is a perspective view illustrating a portion of a horizontal access device in vertical three dimensional (3D) memory, e.g., a portion of a sub cell array 101-2 show n in Figure 1 A as a vertically oriented stack of memory cells in an array, in accordance with a number of embodiments of the present disclosure.

[0040] As shown in Figure 1 B, a substrate 100 may have formed thereon one of the plurality7of sub cell arrays, e.g., 101-2, described in connection with Figure 1A. For example, the substrate 100 may be or include a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. Embodiments, how ever, are not limited to these examples.

[0041] As shown in the example embodiment of Figure IB, the substrate 100 may have fabricated thereon a vertically oriented stack of memory7cells, e.g.. memory cell 110 in Figure 1A, extending in a vertical direction, e.g., third direction (D3) 111. According to some embodiments the vertically oriented stack of memory cells may be fabricated such that each memory7cell, e.g., memory7cell 110 in Figure 1A, is formed on plurality7of vertical levels, e.g., a first level (LI), a second level (L2), and a third level (L3). The repeating, vertical levels, LI, L2, and L3, may be arranged, e.g., “stacked”, a vertical direction, e.g., third direction (D3) 111 shown in Figure 1 A, and may beseparated from the substrate 100 by an insulator material. Each of the repeating, vertical levels, LI, L2, and L3 may include a plurality of discrete components, e.g., regions, to the horizontally oriented access devices 130, e.g., transistors, and storage nodes, e.g., capacitors, including access line 107-1, 107-2, . . ., 107- Q connections and digit line 103-1, 103-2, . . ., 103-Q connections. The plurality of discrete components to the horizontally oriented access devices 130, e.g.. transistors, may be formed in a plurality of iterations of vertically, repeating layers within each level, as described in more detail below, and may extend horizontally in the second direction (D2) 105, analogous to second direction (D2) 105 shown in Figure 1A.

[0042] The plurality of discrete components to the laterally oriented access devices 130, e.g., transistors, may include a first source / drain region 121 and a second source / drain region 123 separated by a channel region 125, extending laterally in the second direction (D2) 105, and formed in a body of the access devices. In some embodiments, the channel region 125 may include silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first and the second source / drain regions, 121 and 123, can include an n-type dopant region formed in a p-type doped body to the access device to form an n-type conductivity transistor. In some embodiments, the first and the second source / drain regions, 121 and 123, may include a p-type dopant formed within an n-type doped body to the access device to form a p-type conductivity' transistor. By way of example, and not by way of limitation, the n-type dopant may include phosphorous (P) atoms and the p-type dopant may include atoms of boron (B) formed in an oppositely doped body region of poly silicon semiconductor material. Embodiments, however, are not limited to these examples.

[0043] The storage node 127, e.g., capacitor, may be connected to one respective end of the access device. As shown in Figure IB, the storage node 127, e.g., capacitor, may be connected to the second source / drain region 123 of the access device. The storage node may be or include memory elements capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistance body which includes a phase change material, etc. Embodiments, however, are not limited to these examples. In some embodiments, the storagenode associated with each access device of a unit cell, e.g., memory cell 110 in Figure 1A, may similarly extend in the second direction (D2) 105. analogous to second direction (D2) 105 shown in Figure 1A.

[0044] As shown in Figure IB a plurality of horizontally oriented access lines 107-1, 107-2, . . ., 107-Q extend in the first direction (DI) 109, analogous to the first direction (DI) 109 in Figure 1A. The plurality of horizontally oriented access lines 107-1. 107-2. . . .. 107-Q may be analogous to the access lines 107-1, 107-2, . . ., 107-Q shown in Figure 1A. The plurality of horizontally oriented access lines 107-1, 107-2, . . ., 107-Q may be arranged, e.g., “stacked”, along the third direction (D3) 111. The plurality of horizontally oriented access lines 107-1. 107-2, . . .. 107-Q may include a conductive material. For example, the conductive material may include one or more of a doped semiconductor, e.g., doped silicon, doped germanium, etc., a conductive metal nitride, e.g., titanium nitride, tantalum nitride, etc., a metal, e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru). cobalt (Co), molybdenum (Mo), etc., and / or a metalsemiconductor compound, e.g., tungsten silicide, cobalt silicide, titanium silicide, etc. Embodiments, however, are not limited to these examples.

[0045] Among each of the vertical levels, (LI), (L2), and (L3), the horizontally oriented memory cells, e.g., memory cell 110 in Figure 1A, may be spaced apart from one another horizontally in the first direction (DI) 109. However, the plurality of discrete components to the horizontally oriented access devices 130, e.g., first source / drain region 121 and second source / drain region 123 separated by a channel region 125, extending laterally in the second direction (D2) 105, and the plurality of horizontally oriented access lines 107-1. 107-2, . . ., 107-Q extending laterally in the first direction (DI) 109, may be formed within different vertical layers within each level. For example, the plurality of horizontally oriented access lines 107-1, 107-2, . . ., 107-Q, extending in the first direction (DI) 109, may be formed on a top surface opposing and electrically connected to the channel regions 125, separated therefrom by a gate dielectric, and orthogonal to horizontally oriented access devices 130, e.g., transistors, extending in laterally in the second direction (D2) 105. In some embodiments, the plurality of horizontally oriented access lines 107-1, 107-2. . . ., 107-Q. extending in the first direction (DI) 109 are formed in a higher vertical layer, farther from the substrate 100, within a level, e.g., withinlevel (LI), than a layer in which the discrete components, e.g.. first source / drain region 121 and second source / drain region 123 separated by a channel region 125, of the horizontally oriented access device are formed.

[0046] As show n in the example embodiment of Figure IB, the digit lines, 103-1, 103-2, . . ., 103-Q, extend in a vertical direction with respect to the substrate 100. e.g., in a third direction (D3) 111. Further, as shown in Figure IB, the digit lines, 103-1. 103-2, . . .. 103-Q, in one sub cell array, e.g., sub cell array 101-2 in Figure 1 A, may be spaced apart from each other in the first direction (DI) 109. The digit lines, 103-1, 103-2, . . ., 103-Q, may be provided, extending vertically relative to the substrate 100 in the third direction (D3) 111 in vertical alignment with source / drain regions to serve as first source / drain regions 121 or, as shown, be vertically adjacent first source / drain regions 121 for each of the horizontally oriented access devices 130, e.g., transistors, extending laterally in the second direction (D2) 105, but adjacent to each other on a level, e.g., first level (LI), in the first direction (DI) 109. Each of the digit lines, 103-1, 103-2, . . ., 103-Q, may vertically extend, in the third direction (D3), on sidewalls, adjacent first source / drain regions 121, of respective ones of the plurality of horizontally oriented access devices 130, e.g., transistors, that are vertically stacked. In some embodiments, the plurality of vertically oriented digit lines 103-1, 103-2. . . ., 103-Q. extending in the third direction (D3) 111, may be connected to side surfaces of the first source / drain regions 121 directly and / or through additional contacts including metal silicides.

[0047] For example, a first one of the vertically extending digit lines, e.g.. 103-1, may be adjacent a sidewall of a first source / drain region 121 to a first one of the horizontally oriented access devices 130, e.g., transistors, in the first level (LI), a sidewall of a first source / drain region 121 of a first one of the horizontally oriented access devices 130, e.g., transistors, in the second level (L2), and a sidewall of a first source / drain region 121 a first one of the horizontally oriented access devices 130. e.g., transistors, in the third level (L3), etc. Similarly, a second one of the vertically extending digit lines, e.g., 103-2, may be adjacent a sidewall to a first source / drain region 121 of a second one of the horizontally oriented access devices 130, e.g., transistors, in the first level (LI), spaced apart from the first one of horizontally oriented access devices 130, e.g., transistors, in the first level (LI) in the first direction (DI) 109. And thesecond one of the vertically extending digit lines, e.g., 103-2, may be adjacent a sidewall of a first source / drain region 121 of a second one of the laterally oriented access devices 130, e.g., transistors, in the second level (L2), and a sidewall of a first source / drain region 121 of a second one of the horizontally oriented access devices 130, e.g., transistors, in the third level (L3), etc. Embodiments are not limited to a particular number of levels.

[0048] The vertically extending digit lines. 103-1, 103-2, . . ., 103-Q, may include a conductive material, such as, for example, one of a doped semiconductor material, a conductive metal nitride, metal, and / or a metalsemiconductor compound. The digit lines, 103-1, 103-2, . . ., 103-Q, may correspond to digit lines (DL) described in connection with Figure 1A.

[0049] As shown in the example embodiment of Figure IB, a conductive body contact may be formed extending in the first direction (DI) 109 along an end surface of the horizontally oriented access devices, e.g., transistors, in each level (LI), (L2), and (L3) above the substrate 100. The body contact may be connected to a body e.g., body region, of the horizontally oriented access devices, e.g., transistors, in each memon cell, e.g., memory cell 110 in Figure 1 A. The body contact may include a conductive material such as, for example, one of a doped semiconductor material, a conductive metal nitride, metal, and / or a metal-semiconductor compound.

[0050] Although not shown in Figure I B, an insulating material may fill other spaces in the vertically stacked array of memory cells. For example, the insulating material may include one or more of a silicon oxide material, a silicon nitride material, and / or a silicon oxynitride material, etc. Embodiments, however, are not limited to these examples.

[0051] Figure 2 illustrates a portion of a horizontal access device in vertical three-dimensional (3D) memory in accordance with a number of embodiments of the present disclosure. Figure 2 illustrates in more detail a unit cell, e.g., memory cell 110 in Figure 1. of the vertically stacked array of memory cells, e.g., within a sub cell array 101-2 in Figure 1, according to some embodiments of the present disclosure. As show n in Figure 2, the first and the second source / drain regions, 221 and 223, may be impurity' doped regions to the laterally oriented access devices 230. e.g., transistors. The first and the second source / drain regions may be separated by a channel region 225 formed in a bodyof semiconductor material, e.g., body region of the horizontally oriented access devices 230, e.g., transistors. The first and the second source / drain regions. 221 and 223, may be formed from an n-type or p-type dopant doped in the body region. However, embodiments are not so limited.

[0052] For example, for an n-type conductivity transistor construction the body region of the laterally oriented access devices 230, e.g., transistors, may be formed of a low doped p-type (p-) semiconductor material. In one embodiment, the body region and the channel region 225 separating the first and the second source / drain regions, 221 and 223, may include a low doped, p-type (e.g., low dopant concentration (p-)) polysilicon (Si) material consisting of boron (B) atoms as an impurity dopant to the poly crystalline silicon. The first and the second source / drain regions, 221 and 223, may also comprise a metal, and / or metal composite materials containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), a highly doped degenerate semiconductor material, and / or at least one of indium oxide (In2O3), or indium tin oxide (In2- xSnxO3), formed using an atomic layer deposition process, etc. Embodiments, however, are not limited to these examples. As used herein, a degenerate semiconductor material is intended to mean a semiconductor material, such as poly silicon, containing a high level of doping with significant interaction between dopants, e.g., phosphorus (P). boron (B), etc. Non-degenerate semiconductors, by contrast, contain moderate levels of doping, where the dopant atoms are well separated from each other in the semiconductor host lattice with negligible interaction.

[0053] In this example, the first and the second source / drain regions, 221 and 223, may include a high dopant concentration, n-type conductivity impurity (e.g., high dopant (n+)) doped in the first and the second source / drain regions, 221 and 223. In some embodiments, the high dopant, n-type conductivity first and second drain regions 221 and 223 may include a high concentration of phosphorus (P) atoms deposited therein. Embodiments, however, are not limited to this example. In other embodiments, the horizontally oriented access devices 230, e.g., transistors, may be of a p-type conductivity construction in which case the impurity, e.g., dopant, conductivity types would be reversed.

[0054] As shown in Figure 2. the first and the second source / drain regions, 221 and 223, may be impurity doped regions to the laterally orientedaccess devices 230, e.g., transistors. The first and the second source / drain regions may be separated by a channel region 225 formed in a body of semiconductor material, e.g., body region, of the horizontally oriented access devices 230, e.g., transistors. The first and the second source / drain regions, 221 and 223, may be formed from an n-type or p-type dopant doped in the body region. However, embodiments are not so limited.

[0055] The first source / drain region 221 may occupy an upper portion in the body of the laterally oriented access devices 230, e.g., transistors. For example, the first source / drain region 221 may have a bottom surface within the body of the horizontally oriented access device 230 which is located higher, vertically in the third direction (D3) 211. than a bottom surface of the body of the laterally, horizontally oriented access device 230. As such, the laterally, horizontally oriented access device 230 may have a body portion which is below the first source / drain region 221 and is in electrical contact with the body contact. Further, as shown in the example embodiment of Figure 2, an access line, e.g., 207, analogous to the access lines 107-1, 107-2, . . ., 107-Q shown in Figure 1, may disposed on a top surface opposing and connected to a channel region 225, separated therefrom by a gate dielectric 204. The gate dielectric 204 may be, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., or a combination thereof. Embodiments are not so limited. For example, in high-k dielectric material examples the gate dielectric material 304 may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobite, etc.

[0056] As shown in the example embodiment of Figure 2, a digit line, e.g.. 203-1, analogous to the digit lines 103-1, 103-2, . . ., 103-Q in Figure 1, may be vertically extending in the third direction (D3) 211 adjacent a sidewall of the first source / drain region 221 in the body to the horizontally oriented access devices 230, e.g., transistors horizontally conducting between the first and the second source / drain regions 221 and 223 along the second direction (D2) 205. In this embodiment, the vertically oriented digit line 203-1 is formed symmetrically, in vertical alignment, in electrical contact with the firstsource / drain region 221. The digit line 203-1 may be formed in contact with an insulator material such that there is no body contact within channel region 225.

[0057] As show n in the example embodiment of Figure 2, the digit line 203-1 may be formed symmetrically within the first source / drain region 221 such that the first source / drain region 221 surrounds the digit line 203-1 all around. The first source / drain region 221 may occupy an upper portion in the body of the laterally oriented access devices 230, e.g.. transistors. For example, the first source / drain region 221 may have a bottom surface within the body of the horizontally oriented access device 230 which is located higher, vertically in the third direction (D3) 211, than a bottom surface of the body of the laterally, horizontally oriented access device 230. As such, the laterally, horizontally oriented access device 230 may have a body portion which is below the first source / drain region 321 and is in contact with the body contact. An insulator material may fill the body contact such that the first source / drain region 221 may not be in electrical contact with channel region 225. Further, as shown in the example embodiment of Figure 2, an access line, e.g., 207, analogous to the access lines 107-1, 107-2, . . ., 107-Q shown in Figure 1, may disposed all around and connected to a channel region 225, separated therefrom by a gate dielectric 204.

[0058] Although the digit line 203-1 is described above as being formed symmetrically within the first source / drain region 221 such that the first source / drain region 221 surrounds the digit line 203-1 all around, embodiments are not so limited. For instance, in some examples, the digit line 203-1 can be formed asymmetrically. In this embodiment, the vertically oriented digit line is formed asymmetrically adjacent in electrical contact with the first source / drain regions 221. The digit line may be formed asymmetrically to reserve room for a body contact in the channel region 225.

[0059] Figure 3 is a perspective view of a memory device in accordance with a number of embodiments of the present disclosure. Figure 3 includes first conductive material 377, an Si material 332, a photolithographic mask material (e.g., mask material) 335, an interlayer dielectric (ILD) fill material 367, a second conductive material 370, a metal material 372, a first dielectric material 339, a second dielectric material 333, a second interlayer dielectric material 342, and a plurality of storage nodes (e.g., capacitors) 374.

[0060] Figure 3 illustrates a portion of a vertical 3D memory array that is formed in accordance with the process described in Figures 4-16, as is further described herein. The 3D memory array can include an array of vertically stacked memory cells having a plurality of levels. Each level of the plurality of levels can include horizontally oriented access devices and storage nodes.

[0061] Each storage node can include horizontally oriented access devices having first source / drain regions and second source / drain regions separated by channel regions, and gates on a gate dielectric material. The array can further comprise horizontally oriented access lines forming the gates to the horizontally oriented access devices. The horizontally oriented access lines can be gate all around (GAA) structures. The storage nodes can further include horizontally oriented storage nodes electrically connected to the second source / drain regions of the horizontally oriented access devices.

[0062] The horizontal access devices of the vertical 3D memory array can include the second dielectric material 333, the first dielectric material 377, a first dielectric material 339, and ILD fill material 367. The access devices can be connected to the plurality of storage nodes 374. In some embodiments, the plurality of storage nodes 374 can be double-sided capacitors. The access devices can be used to transfer current between the metal material 372 and the plurality of storage nodes 374.

[0063] Further included in the vertical 3D memory array can be epitaxially formed vertical digit lines 392 connected to the first source / drain regions of the horizontally oriented access devices. Devices and methods of forming the epitaxially grown vertical digit lines are further described herein.

[0064] Figure 4 is a cross-sectional view, at one stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, such as illustrated in Figures 1-3, and in accordance with a number of embodiments of the present disclosure.

[0065] In the example embodiment shown in the example of Figure 4. the method comprises forming alternating layers of a silicon germanium (SiGe) material , 430-1, 430-2, . . ., 430-N (collectively referred to as silicon germanium (SiGe) 430), and a silicon (Si) material, 432-1, 432-2, . . ., 432-N (collectively- referred to as epitaxially grown, single crystalline silicon (Si) material 432). in repeating iterations to form a vertical stack 402 on a working surface of asemiconductor substrate 400. In one embodiment, the silicon germanium (SiGe) 430 can be deposited on a dielectric 431 to have a thickness, e.g., vertical height in the third direction (D3), in a range of five (5) nm to thirty (30) nm. In one embodiment, the silicon 432 can be deposited to have a thickness (t2), e.g., vertical height, in a range of thirty (30) nanometers (nm) to sixty (60) nm. Embodiments, however, are not limited to these examples. As shown in Figure 4. a vertical direction 411 is illustrated as a third direction (D3). e.g., z-direction in an x-y-z coordinate system, analogous to the third direction (D3), among first, second, and third directions, shown in Figures 1-2.

[0066] In some embodiments, the silicon germanium (SiGe), 430-1, 430- 2, . . .. 430-N. may be a mix of silicon and germanium. By way of example, and not by way of limitation, the silicon germanium (SiGe) 430 may be grown on a dielectric 431 by way of epitaxial growth. Embodiments are not limited to these examples. In some embodiments, the single crystalline silicon (Si) material, 432-1, 432-2, . . ., 432-N. may comprise a silicon (Si) material in a polycrystalline and / or amorphous state. The single crystalline silicon (Si) material, 432-1, 432-2, . . ., 432-N, may be a low doped, p-type (p-) epitaxially grown, single cry stalline silicon (Si) material. The silicon material, 432-1, 432- 2, . . .. 432-N. may also be formed by epitaxially growth on the silicon germanium (SiGe) 430. After the epitaxially grown silicon germanium (SiGe) 430 has been formed, the seed is turned to pure silicon. Embodiments, however, are not limited to these examples.

[0067] The repeating iterations of alternating silicon germanium (SiGe), 430-1, 430-2, . . ., 430-N layers and epitaxially grown, single crystalline silicon (Si) material, 432-1, 432-2, . . ., 432-N layers may be deposited according to a semiconductor fabrication process such as chemical vapor deposition (CVD) in a semiconductor fabrication apparatus. Embodiments, however, are not limited to this example and other suitable semiconductor fabrication techniques may be used to deposit the alternating layers of epitaxially grown silicon germanium (SiGe) and epitaxially grown, single crystalline silicon (Si) material, in repeating iterations to form the vertical stack 402.

[0068] The layers may occur in repeating iterations vertically. In the example of Figure 4, N+l tiers, numbered 1. 2, 3, N. and N+l of the repeating iterations are shown. For example, the stack may include: a first silicongermanium (SiGe) 430-1, a first Si material 432-1, a second SiGe material 430-2, a second Si material 432-2, a third SiGe material 430-3. and a Si material 432-3, in further repeating iterations. Embodiments, however, are not limited to this example and more or fewer repeating iterations may be included.

[0069] Figure 5A illustrate an example method, at one stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, such as illustrated in Figures 1-3, and in accordance with a number of embodiments of the present disclosure.

[0070] Figure 5A illustrates a top-down view' of a semiconductor structure, at a particular point in time, in a semiconductor fabrication process, according to one or more embodiments. In the example embodiment shown in the example of Figure 5 A, the method comprises using an etchant process to form a plurality of vertical openings 515 (e.g., a plurality of second vertical openings), having a first horizontal direction (DI) 509 and a second horizontal direction (D2) 505, through the vertical stack to the substrate. In one example, as shown in Figure 5 A, the plurality of vertical openings 515 are extending predominantly in the second horizontal direction (D2) 505 and may form elongated vertical columns 513-1, 513-2, . . ., 513-M (collectively and / or independently referred to as 513), with sidew alls 514 in the vertical stack. The plurality of first vertical openings 500 may be formed using photolithographic techniques to pattern a photolithographic mask 535, e.g., to form a hard mask (HM), on the vertical stack prior to etching the plurality of first vertical openings 515. Similar semiconductor process techniques may be used at other points of the semiconductor fabrication process described herein.

[0071] Figure 5B is a cross sectional view, taken along cut-line A-A’ in Figure 5A, showing another view' of the semiconductor structure at a particular time in the semiconductor fabrication process. The cross-sectional view' shown in Figure 5B shows the repeating iterations of alternating layers of silicon germanium (SiGe) 530 and silicon (Si) material 532 on a semiconductor substrate 500 to form the vertical stack, e.g. 402 as shown in Figure 4.

[0072] As show n in Figure 5B, a plurality of vertical openings may be formed through the layers within the vertically stacked memory cells to expose vertical sidewalls in the vertical stack and form elongated vertical columns 513 and then filled with a first dielectric material 539. The vertical openings may beformed through the repeating iterations of the silicon germanium (SiGe) 530 and the silicon (Si) material 532.

[0073] The vertical openings may be formed to expose vertical sidewalls in the vertical stack. The vertical openings may extend in a second horizontal direction (D2) 505 to form the elongated vertical columns with first vertical sidewalls in the vertical stack and then filled with the dielectric material 539.

[0074] As shown in Figure 5B. a first dielectric material 539, such as an oxide or other suitable spin on dielectric (SOD), may be deposited in the vertical openings, using a process such as CVD, to fill the vertical openings. First dielectric material 539 may also be formed from a silicon nitride (Si3N4) material. In another example, the first dielectric material 539 may include silicon oxy-nitride (SiOxNy), and / or combinations thereof. Embodiments are not limited to these examples. The plurality of first vertical openings may be formed using photolithographic techniques to pattern a photolithographic mask 535, e.g., to form a hard mask (HM), on the vertical stack prior to etching the plurality of first vertical openings. In one embodiment, hard mask 535 may be deposited over silicon germanium (SiGe) 530. Similar semiconductor process techniques may be used at other points of the semiconductor fabrication process described herein.

[0075] Figure 6A illustrates an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory in accordance with a number of embodiments of the present disclosure. Figure 6A illustrates a top-down view of a semiconductor structure, at a particular point in time, in a semiconductor fabrication process, according to one or more embodiments.

[0076] In the example embodiment of Figure 6A, the method comprises using a photolithographic process to pattern a photolithographic mask 635. A first conductive material 677 may be deposited above the vertical openings 631. The first conductive material 677 may be deposited in continuous second horizontal openings to form horizontally oriented access lines at the channel regions of the silicon (Si) material 632. Such a process is further described herein.

[0077] For example, the semiconductor fabrication process can include using an etchant process to form a plurality’ of spaced, vertical openings 631through the vertical stack by patterning and selectively removing the first dielectric material 639 in the plurality of vertical openings 615 to expose second vertical sidewalls adjacent a first region of the silicon germanium (SiGe). Multiple vertical openings 631 may be formed through the layers of materials. In one example, as shown in Figure 6 A, the spaced, vertical openings 631 are extending predominantly in the first horizontal direction (D2) 609 and may form short vertical squares in the plurality of vertical openings 615 adjacent the vertical stack. The vertical openings 631 may be formed using photolithographic techniques to pattern first dielectric material 639 to form an opening within the vertical stack prior to etching the plurality of vertical openings 615.

[0078] The semiconductor fabrication process can further include doping a first source / drain region of the Si material 632. That is, the first Si material 632-1, the second Si material 632-2, the third Si material 632-3, and in further repeating iterations, can be doped. For example, a source / drain region may be formed by gas phase doping a dopant into a side surface portion of the Si material 632. In some embodiments, the source / drain region may be a first source / drain region that will connect to a digit line connection. In one example, gas phase doping may be used to achieve a highly isotropic (e.g., non-directi onal doping), to form the first source / drain regions for the horizontally oriented access devices. In another example, thermal annealing with doping gas, such as phosphorous (P) may be used with a high energy' plasma assist to break the bonding. Embodiments, however, are not so limited and other suitable semiconductor fabrication techniques may be utilized.

[0079] The openings 615 may be filled with a dielectric material 639. In one example, a spin on dielectric process may be used to fill the openings 615. In one embodiment, the dielectric material 639 may be an oxide material. However, embodiments are not so limited.

[0080] Figure 6B illustrates a cross sectional view, taken along cut-line A-A’ in Figure 6A, showing another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in Figure 6B shows the repeating iterations of alternating layers of the silicon germanium (SiGe) 630 and the silicon (Si) material 632, on a semiconductor substrate 600.

[0081] As mentioned in Figure 6A, the semiconductor fabrication process can include forming vertical openings 615 (e.g., illustrated in Figure 6A) through the layers within the vertically stacked memory cells to expose vertical sidewalls in the vertical stack 402 as show n in Figure 4. The vertical openings 615 can extend predominantly in a first horizontal direction. The dielectric material 639, such as an oxide or other suitable spin on dielectric (SOD), may be deposited in the first vertical openings, using a process such as CVD, to fill the first vertical openings. A photolithographic mask 635, e.g., hard mask, may be deposited over the vertical stack using CVD and planarized using chemical mechanical planarization (CMP). Similar semiconductor process techniques may be used at other points of the semiconductor fabrication process described herein.

[0082] The semiconductor fabrication process can further include selectively etching the silicon germanium (SiGe) 630 isotropically to form a plurality’ of first horizontal openings in the first region separating layers of the Si material 632. An etchant may be flowed into the second vertical opening 631 to selectively etch a portion of the epitaxially grown silicon germanium (SiGe) 630 within the stack. As such, the etchant may target the first silicon germanium (SiGe) 630-1, the second silicon germanium (SiGe) 630-2, and the third silicon germanium (SiGe) 630-3 within the stack. The selective etchant process may etch the silicon germanium (SiGe) 630 to form the plurality of first horizontal openings 673. As a result of the etchant process, the vertical thickness (e.g., D3) of the layers of the Si material 632 occurs.

[0083] The selective etchant process may comprise a selective etch chemistry of phosphoric acid (H3PO4) or hydrogen fluoride (HF) and / or dissolving the silicon germanium (SiGe) 630 using a selective solvent, among other possible etch chemistries or solvents. Alternatively, or in addition, a selective etch to remove the silicon germanium (SiGe) 630 may consist of one or more etch chemistries selected from an aqueous etch chemistry, a semi-aqueous etch chemistry, a vapor etch chemistry, or a plasma etch chemistries, among other possible selective etch chemistries. For example, a dry etch chemistry of oxygen (02) or 02 and sulfur dioxide (SO2) may be utilized. As another example, a dry etch chemistries of 02 or of 02 and nitrogen (N2) may be used to selectively etch the silicon germanium (SiGe) 630.

[0084] The silicon germanium (SiGe) 630 has now been selectively etched isotropically to form a plurality of first horizontal openings 673 in the first region separating layers of the Si material 632. A second dielectric material 633 may be conformally deposited all around first horizontal opening 673. The second dielectric material 633 may be deposited fully around exposed surfaces in the plurality of first horizontal openings 673. The second dielectric material 633 may serve as a liner around the plurality of first horizonal openings 673. The second dielectric material 633 may be flowed into the vertical opening 631 to cover exposed surfaces of the silicon (Si) material where the silicon germanium (SiGe) was removed to form the plurality' of first horizontal openings 673 within the stack.

[0085] In one embodiment, the second dielectric material 633 may comprise a nitride material. In another embodiment, second dielectric material 633 may comprise a silicon nitride (Si3N4) material (also referred to herein as ”SiN"). In another embodiment the second dielectric material 633 may include silicon dioxide (SiO2) material. In another embodiment the second dielectric material 633 may comprise a silicon oxy -carbide (SiOxCy) material, and / or combinations thereof. Embodiments are not limited to these examples.

[0086] In one embodiment, the second dielectric material 633 may be conformally deposited all around exposed surfaces in the plurality of first horizontal openings 673 to have a thickness (tl) of approximately 100 to 300 angstroms (A). Embodiments, however, are not limited to these examples.

[0087] The semiconductor fabrication process can further include depositing the first dielectric material 639 to full the plurality of first horizontal openings 673. For example, a first dielectric material 639, such as an oxide or other suitable spin on dielectric (SOD), is deposited into the plurality of first horizontal openings 673, on the exposed surfaces of the second dielectric material 633, to fill the first horizontal opening 673. The first dielectric material 639 may entirely fill the plurality of first horizontal openings 673. The first dielectric material 639 may be flowed into the vertical openings 631 to fill the vertical openings 631 and to fill the plurality7of first horizontal openings 673 within the stack. As such, the first dielectric material 639 may fill the first horizontal openings 673 within the first silicon germanium (SiGe) 630-1, thesecond silicon germanium (SiGe) 630-2, and the third silicon germanium (SiGe) 630-3 within the stack.

[0088] The semiconductor fabrication process can further include selectively etching the second dielectric material 633 from the plurality of first horizontal openings a second length (L2) from the vertical openings 670. An etchant may be flowed into the vertical opening 631 to selectively etch a portion of the second dielectric material 630 within the stack. As such, the etchant may target the second dielectric material 630 within the stack. The selective etchant process may etch the second dielectric material 630 the second length L2. Any selective etch chemistry described herein or otherwise may be utilized for such a selective etchant process.

[0089] The semiconductor fabrication process can further include forming a gate dielectric material on exposed surfaces of the reduced vertical thickness of the Si material 632. For example, a gate dielectric material 642 maybe formed on exposed surfaces of the Si material 632 to form horizontal access devices. In some embodiments the gate dielectnc material may be an oxide material 642. The gate dielectric material 642 may be conformally deposited fully around every7surface of the Si material 632 to form gate all around (GAA) gate structures, at the channels of the access device regions. The gates at the channel regions provide a subthreshold voltage (sub-Vt) slope in a range of approximately 45 to 100 millivolts per decade (mV / dec).

[0090] The gate dielectric material 642 may be deposited on exposed surfaces of the Si material 632 using an atomic layer deposition. In some embodiments the gate dielectric material may be an oxide material. For example, an oxide material may be deposited over the exposed surfaces of the epitaxially grown, single crystalline silicon (Si) material 632 to prevent oxidization of the Si material 632. The oxide material deposition may prevent shorts by protecting the Si material 632 from interactions with the first dielectric material 639. The oxide material may be selectively deposited on exposed surfaces of the Si material 632 using atomic layer deposition. A thermal oxidation process may be used to densify the ALD deposited oxide material. The thermal oxidation process involves forming oxide material from a hybrid oxide material. The hybrid oxide material may combine a low temperature oxide material and a high temperature oxide material.

[0091] In the semiconductor fabrication process, a first conductive material 677 may be deposited on the gate dielectric material 642. The first conductive material 677 may be deposited around the Si material 632 such that the first conductive material 677 may have a top portion above the Si material 632 and a bottom portion below the Si material 632 to form gate all around (GAA) gate structures, at the channels of the access device regions. The first conductive material 677 may be conformally deposited into vertical openings 670 and fill the continuous second horizontal openings 643 up to the un etched portions of the oxide material 642, the first dielectric material 639, and the second dielectric material 633. The first conductive material 677 may be conformally deposited using a chemical vapor deposition (CVD) process, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition process.

[0092] In some embodiments, the first conductive material 677 may comprise one or more of a doped semiconductor (e.g., doped silicon, doped germanium, etc., a conductive metal nitride, e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.), and / or some other combination thereof. The first conductive material 677 entwined with the gate dielectric material may form horizontally oriented access lines at a channel region of the epitaxially grown, single crystalline silicon (Si) material (which also may be referred to a word lines).

[0093] The first conductive material 677 can be recessed to the channel regions. For example, the first conductive material 677, formed on the gate dielectric material 642, may be recessed and etched away from the third vertical opening 670. In some embodiments, the first conductive material 677 may be etched using an atomic layer etching (ALE) process. In some embodiments, the first conductive material 677 may be etched using an isotropic etch process. The first conductive material 677 may be selectively etched leaving the oxide material 642 covering the Si material 632 and the first dielectric material 639 intact. The first conductive material 677 may be selectively etched in the second direction, in the continuous second horizontal openings, a third distance (DIST 3) in a range of twenty (20) to fifty (50) nanometers (nm) back from the thirdvertical opening 670. The first conductive material 677 may be selectively- etched around the Si material 632 back into the continuous second horizontal openings extending in the first horizontal direction.

[0094] Figure 6C illustrates a cross sectional view, taken along cut-line C-C’ in Figure 6A, showing another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in Figure 6C is illustrated extending in the second horizontal direction (D2) 605, left and right in the plane of the drawing sheet, along an axis of the repeating iterations of alternating layers of continuous second horizontal openings 643 and Si material 632.

[0095] In Figure 6C, first dielectric material 639 is shown spaced along a second horizontal direction (D2) 605, extending into and out from the plane of the drawings sheet, for a three-dimensional array of vertically oriented memory cells. At the left end of the drawing sheet is shown the repeating iterations of alternating layers of the first dielectric material 639. The first conductive material 677 may be conformally deposited into third vertical openings 670. The first conductive material 677 is formed on the gate dielectric material. At the right hand of the draw ing sheet, the first dielectric material 639 may be seen, separating access device and storage node regions in the first direction (DI).

[0096] Figure 6D illustrates a cross sectional view, taken along cut-line D-D’ in Figure 6A, show ing another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in Figure 6D is illustrated, right to left in the plane of the drawing sheet, extending in the first direction (DI) 609 along an axis of the repeating iterations of alternating layers of first dielectric material 639 and Si material 632 w rapped with a gate dielectric material 642. The gate dielectric material 642 may be conformally deposited fully around every surface of the Si material 632, to form gate all around (GAA) gate structures, at the channels of the access device regions. The first conductive material 677 may fill the spaces adjacent the bridged Si material 632. The Si material 632 may be surrounded by first conductive material 677 formed on the gate dielectric material 642. The first conductive material 677 may be conformally deposited fully around every surface of the Si material 632,to form gate all around (GAA) gate structures, at the channels of the access device regions.

[0097] Figure 7A illustrates an example method, at another stage of a semiconductor fabrication process, for forming epitaxial silicon within horizontal access devices in vertical three-dimensional (3D) memory, such as illustrated in Figures 1-3, and in accordance with a number of embodiments of the present disclosure. Figure 7A illustrates a top-down view of a semiconductor structure, at a particular point in time, in a semiconductor fabrication process, according to one or more embodiments. In the example embodiment of Figure 7A, the method comprises using a photolithographic process to pattern the photolithographic mask 735. The first conductive material 777 may have been deposited above the vertical openings 731 and is now recessed.

[0098] Figure 7B illustrates a cross sectional view, taken along cut-line B-B’ in Figure 7A, showing another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view- shown in Figure 7B is illustrated extending in the second horizontal direction (D2) 705, left and right along the plane of the drawing sheet, along an axis of the repeating iterations of alternating layers of the SiGe material 730 and the Si material 732.

[0099] A first conductive material 777 was deposited on the gate dielectric material and formed around the Si material 732, recessed back, to form gate all around (GAA) structure at channel regions of the Si material 732. The first conductive material 777. formed on the gate dielectric material 742, may be recessed and etched away from the vertical opening 770.

[0100] In some embodiments, the first conductive material 777 may7be etched using an atomic layer etching (ALE) process. In some embodiments, the first conductive material 777 may be etched using an isotropic etch process. The first conductive material 777 may be selectively etched leaving the oxide material 742 covering the Si material 732 and the first dielectric material 739 intact. The first conductive material 777 may be selectively etched in the second direction, in the continuous second horizontal openings, a third distance (DIST 3) in a range of twenty (20) to fifty (50) nanometers (nm) back from the third vertical opening 770. The first conductive material 777 may be selectivelyetched around the epitaxially grown, single crystalline silicon (Si) material 732 back into the continuous second horizontal openings extending in the first horizontal direction.

[0101] Figure 8A illustrates an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, such as illustrated in Figures 1-3, and in accordance with a number of embodiments of the present disclosure. Figure 8A illustrates a top down view of a semiconductor structure, at a particular point in time, in a semiconductor fabrication process, according to one or more embodiments. In the example embodiment of Figure 8 A, the method comprises using a photolithographic process to pattern the photolithographic mask 835. The method in Figures 8A-8B illustrates an interlayer dielectric (ILD) fill material 867 may be deposited in the vertical openings 831 to fill the vertical openings 831.

[0102] Figure 8B illustrates a cross sectional view, taken along cut-line B-B’ in Figure 8A, showing another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in Figure 8B is illustrated extending in the second horizontal direction (D2) 805, left and right along the plane of the drawing sheet, along an axis of the repeating iterations of alternating layers of the SiGe material 830 and the Si material 832.

[0103] An inter-layer dielectric (ILD) fill material 867 may be deposited into vertical openings 870 and filling the continuous second horizontal openings up to the unetched portions of the oxide material 842, the first dielectric material 839, and the first conductive material 877. The ILD fill material 867 may be conformally deposited using a chemical vapor deposition (CVD) process, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition process.

[0104] Figure 9A illustrates an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory', such as illustrated in Figures 1-3, and in accordance with a number of embodiments of the present disclosure. As illustrated in Figure 9A, a vertical opening 951 can be formed in a storage node region 950 through the vertical stack and extending predominantly in the firsthorizontal direction (DI) 909. The vertical opening 951 can be formed from one or more etchant processes to expose sidewalls in the repeating iterations of alternating layers of alternating silicon germanium (SiGe), 430-1, 430-2, . . ., 430-N layers and epitaxially grown, single crystalline silicon (Si) material, 432- 1, 432-2, . . ., 432-N layers, shown in Figure 4 in the vertical stack in order to form storage nodes.

[0105] Figure 9B is a cross sectional view, taken along cut-line B-B?in Figure 9A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. In Figure 9B, the one or more etchant processes can be utilized to form the storage node region 950. The storage node region 950 can include storage nodes (e.g.. horizontally oriented capacitor cells) having the first electrodes 961, e.g., bottom electrodes to be connected to source / drain regions of horizontal access devices, and second electrodes 956, e.g., top electrodes to be connected to a common electrode plane such as a ground plane. The storage nodes are shown formed in a third horizontal opening 979, extending in second direction (D2) 905, left and right in the plane of the drawing sheet, a third distance from the vertical opening formed in the vertical stack and along an axis of orientation of the horizontal access devices and horizontal storage nodes of the arrays of vertically stacked memory cells of the three-dimensional (3D) memory. In Figure 9B, a neighboring, horizontal access line 977 is illustrated adjacent the second dielectric material 933, with a portion of the first conductive material 977 located above the Si material 932, and a portion of the first conductive material 977 located below the Si material 932 extending in a direction inward and outward from the plane and orientation of the drawing sheet.

[0106] Additionally, as illustrated in Figure 9B, the ILD material 967 can be removed from the vertical opening 970 and up to a vertical sidewall of the vertical opening 970, resulting in a vertical stack in the vertical opening 970 of alternating ILD material 967. dielectric material 939, ILD material 967. gate dielectric material 942, Si material 932, dielectric material 942, ILD fill material 967, etc.

[0107] Figure 9C is a cross sectional view, taken along cut-line A-A’ in Figure 9A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. The cross-sectional view shownin Figure 9C is away from the plurality of separate, horizontal access lines 977, and shows repeating iterations of alternating layers of second electrodes 956 separated by horizontally oriented capacitor cells having first electrodes 961, e.g., bottom cell contact electrodes, cell dielectric material 963, and top, common node electrodes, on a semiconductor substrate 900 to form the vertical stack. In the example embodiment of Figure 9C, the first electrodes 961, e.g., bottom electrodes to be connected to source / drain regions of horizontal access devices, and second electrodes 956 are illustrated separated by a cell dielectric material 963 extending into and out of the plane of the drawing sheet in second direction (D2) and along an axis of orientation of the horizontal access devices and horizontal storage nodes of the arrays of vertically stacked memory cells of the 3D memory. In Figure 9C, the first dielectric material 939 is shown separating the space between neighboring horizontally oriented access devices and horizontally oriented storage nodes.

[0108] Figure 10A illustrates an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, such as illustrated in Figures 1-3, and in accordance with a number of embodiments of the present disclosure. As illustrated in Figure 10A, the semiconductor fabrication process can include patterning a plurality of vertical columns adjacent to the first source / drain regions, as is further described herein.

[0109] The semiconductor fabrication process can include filling the vertical opening 1070 with carbon material 1082. For example, carbon material1082 can be deposited into the vertical opening 1070 and fill the vertical opening 1070 up to the top of the stack.

[0110] A mask 1083 can be formed on the vertical stack. For example, photolithographic techniques can be utilized to pattern a photolithographic mask1083 (e.g., to form a hard mask) on the vertical stack. The photolithographic mask 1083 can extend predominantly in the direction 1005 (D2) to span the vertical opening 1070, as well as in the direction 1009 (DI). The photolithographic mask 1083 can be patterned on the vertical stack above the carbon material 1082 filling the vertical opening 1070 such that the layers of first dielectric material 1039 are located in the spaces between the patterned photolithographic masks 1083. The photolithographic mask 1083 can be utilizedto patern vertical openings in the carbon material 1082, as is further described herein.

[0111] Figure 1 OB is a cross sectional view, taken along cut-line A-A’ in Figure 10A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 10B, the carbon material 1082 can be deposited in the vertical opening 1070. The carbon material 1082 can fill the vertical opening 1070 up to the top of the stack.

[0112] Figure 10C illustrates a cross-sectional view, taken along cut-line B-B’ in Figure 10A, showing another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in Figure 10C is illustrated extending in the second horizontal direction (D2) 1005, left and right along the plane of the drawing sheet, along an axis of the repeating iterations capacitor cells. In the cross-sectional view of Figure 10C, the carbon material 1082 is located in the vertical opening 1070, with the paterned photolithographic masks 1083 located on the top of the stack.

[0113] Figure 11A illustrates an example method, at another stage of a semiconductor fabrication process, for epitaxial digit line growth in vertical three-dimensional (3D) memory, such as illustrated in Figures 1-3, and in accordance with a number of embodiments of the present disclosure. Figure 11 A is a cross-sectional view, taken along cut-line A-A’ in Figure 10A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. At this point, the semiconductor fabrication process can include paterning vertical openings in the carbon material 1182.

[0114] Figure 1 IB is a cross-sectional view, taken along cut-line B-B’ in Figure 10A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 1 IB, the semiconductor fabrication process can include patterning vertical openings 1184 in the carbon material 1182. The vertical openings 1184 can be paterned through the carbon material 1182 the height of the vertical stack, to remove the carbon material 1182 at these locations. For example, an etchant process may be utilized to form the vertical openings 1184 through the carbon material 1182. The etchant process may be a selective etchant process using any kind ofselective etch chemistry described herein or otherwise may be utilized for such an etchant process.

[0115] Figure 12 is a cross-sectional view, taken along cut-line B-B’ in Figure 10A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 12, the mask (e.g., mask 1183) can be removed from the top of the vertical stack. The vertical openings (e.g., vertical openings 1184) in the carbon material 1282 can be filled with the second dielectric material 1239. In one example embodiment, the second dielectric material 1239 may be a nitride material 1239, such as silicon nitride (S iaNa). Embodiments, however, are not limited to this example. According to embodiments, a second dielectric material 1239 is chosen that is selectively etchable relative to the carbon material 1282. As illustrated in Figure 12, the second dielectric material 1239 can be deposited in the vertical openings in the carbon material 1282. The second dielectric material 1239 can fill the vertical openings above the top of the stack. Such a fill can form alternating vertical columns of carbon material 1282 and the second dielectric material 1239.

[0116] Figure 13A is a cross-sectional view, taken along cut-line B-B’ in Figure 10A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 13 A, patterning the plurality of spaced vertical columns further includes exhuming the vertical columns of carbon material (e.g., carbon material 1282) from the vertical opening 1070. For example, a timed selective etch, exhume process may be utilized to exhume the carbon material, forming vertical openings 1386 and leaving columns of the second dielectric material 1339 remaining. Such a process can expose the Si material 1332 of the first source / drain regions in the vertical openings 1386 located in the vertical opening 1070.

[0117] The vertical columns of the first dielectric material 1339 can serve to direct, e.g.. restrict, epitaxial growth of Si material from the first source / drain regions (e.g., from the exposed Si material 1332 in the vertical openings 1386). For example, the vertical columns of the first dielectric material 1339 can prevent epitaxial growth of Si material from the Si material 1332 horizontally, in the first direction 1309 (e.g., the DI direction), which canprevent short circuiting of adjacent vertical digit lines during epitaxial growth, as is further described herein.

[0118] Figure 13B is a cross-sectional view, taken along cut-line A-A’ in Figure 10A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 13B, carbon material has been exhumed from the vertical opening 1370. Although not illustrated in Figure 13B. vertical columns of the first dielectric material 1339 can be located in the vertical opening 1370. Ends, e.g., tips, of Si material 1332 (e.g., exposed first source / drain regions) can be exposed in the vertical opening 1370 for epitaxial growth of Si material to allow7for epitaxial digit line growth, as is further described herein.

[0119] Figure 14A is a cross-sectional view, taken along cut-line A-A’ in Figure 10A, showing another view7of the semiconductor structure at a particular time in the semiconductor fabrication process. The semiconductor fabrication process can include epitaxially growing Si material 1490 at the first source / drain regions (e.g., at the tips of the exposed Si material 1432) in the vertical openings 1484 between the columns of the second dielectric material 1439. Epitaxially growing Si material 1490 can be percreated by flowing silane gas at appropriate temperature and pressure under vacuum conditions to seed and nucleate Si on the ends, e.g.. tips, of the exposed Si material 1432.

[0120] Figure 14B is a cross-sectional view, taken along cut-line B-B’ in Figure 10A, showing another view7of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 14B. epitaxially grown Silicon material 1490 can be grown from the first source / drain regions in the vertical openings 1484. The spaced vertical columns of the first dielectric material 1439 can prevent substantial horizontal growth (e.g., in direction 1409, DI) as the epitaxial growth of the Si material 1490 occurs. The columns of the first dielectric material 1439 can accordingly prevent merging in the horizontal direction (e.g.. direction 1409. DI) of the epitaxially grown Si material 1490, which can prevent short-circuiting between vertically oriented digit lines in the 3D memory array.

[0121] Figure 15A is a cross-sectional view7, taken along cut-line A-A’ in Figure 10A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. In Figure 15 A, the epitaxiallygrown Si material 1590 can be grown to a point at which it merges in the vertical direction (e.g., direction 1511, D3) to form a continuous, vertically oriented digit line.

[0122] Figure 15B is a cross-sectional view, taken along cut-line B-B’ in Figure 10A, showing another view of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 15B, the epitaxially grown Si material 1590 from each of the first source / drain regions (e.g., from the exposed Si material 1532) at each level of the stack has merged to form continuous, vertically oriented digit lines 1592 comprised of epitaxially grown Si material 1590.

[0123] In some examples, the semiconductor fabrication process can further include exhuming the columns of the second dielectric material. For example, a timed selective etch, exhume process may be utilized to exhume the second dielectric material, leaving the continuous, vertically oriented digit lines 1592 remaining in the vertical opening 1570.

[0124] At this point in the semiconductor fabrication process, the continuous, vertically oriented digit lines 1592 are still Si material. For example, the vertically oriented digit lines 1592 are still epitaxially grown Si material. As such, the semiconductor fabrication process can further include converting the continuous, vertically oriented digit lines 1592 from the Si material to a conductive material having a different characteristic from the Si material.

[0125] The epitaxially grown Si material of the vertically oriented digit lines 1592 can be converted to conductive material (e.g.. tungsten material). For instance, a tungsten hexafluoride (WF6) material can be selectively reacted with the remaining Si material. For example, the tungsten hexafluoride material can be flowed into the third vertical opening 1570 to expose the digit line 1592 to the tungsten hexafluoride material, such that the (e.g., exposed) vertically oriented digit lines 1592 are soaked with the tungsten hexafluoride, causing the tungsten material to grow. This reaction can be expressed chemically as:with the change in enthalpy for the reaction being -1908 KJ / mole. The tungsten hexafluoride may target all iterations of the vertically oriented digit lines 1592 in the stack.

[0126] The tungsten hexafluoride material, however, may react only with the epitaxially grown Si material. For instance, the tungsten hexafluoride material may not react with dielectric material, source / drain region, or oxide material. Hence, the conversion process may be selective to the epitaxially grown Si material of the continuous, vertically oriented digit lines 1592. For instance, the dielectric material, source / drain region, and oxide material may be left intact during the conversion process, and the source / drain region may remain nearly untouched by the conversion process.

[0127] As such, the epitaxially grown Si material can be converted into a conductive material to function as a vertically oriented digit line. The vertically oriented digit line formation as described above can be utilized in vertical openings having high aspect ratios, such as 5: 1 vertical / horizontal aspect ratio specifications, or even higher.

[0128] Figure 16A-1 is a cross-sectional view, taken along cut-line B-B’ in Figure 9A, showing a view of the semiconductor structure at a particular time in the semiconductor fabrication process. Figures 16A et. Seq. illustrate another, alternative embodiment for epitaxial digit line growth in vertical 3D memory to preclude horizontal growth and short circuiting between adjacent, vertical digit lines. As illustrated in Figure 16A-1, a first source / drain region has been formed in the Si material 1632. surrounded by ILD dielectric material 1667. along with the dielectric material 1 39 separating the vertical spaces between horizontally neighboring access devices and separating the horizontal spaces between vertically neighboring access devices (e.g., top and bottom access devices as oriented in Figure 16A-1. In such examples, the first dielectric material 1639 can be a nitride cap, or Si(C)N.

[0129] Figure 16A-2 is another cross-sectional view, taken along cut-line A-A’ in Figure 9A, showing a view' of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 16A-2, the first source / drain region in the Si material 1632 is protruding forth in the second horizontal direction (D2) 1605. The ILD dielectric material 1667, along with the dielectric material 1639 separating the vertical spaces betw een horizontally neighboring access devices and separating the horizontal spaces between vertically neighboring access devices (e.g., top and bottom accessdevices as oriented in Figure 16A-1) has been selectively recessed according to a timed, selective etch process so that the Si material 1632 protrudes forth.

[0130] Thus, at this point, the semiconductor fabrication process can include forming a plurality of spaced vertical columns openings, vertically between the first source / drain regions and forming a plurality of spaced horizontal row openings between the plurality of vertical columns and between the first source / drain regions.

[0131] Next, as shown in Figure 16B, for example, the first dielectric material 1639 can be extended, e.g., regrown or formed, using a technique such as timed, atomic selective deposition (ASD). Embodiments, however, are not limited to this example, and the first dielectric material 1639 can be conformally deposited using a chemical vapor deposition (CVD) process, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), area selective deposition (ASD), or any other suitable deposition process to form the plurality of spaced vertical columns and spaced horizontal rows made of the first dielectric material 1639, as is further described in Figures 16B-1 and 16B-2.

[0132] The first dielectric material 1639 can be an oxide material. For example, oxide material can be selectively deposited in a timed manner to form the plurality of spaced vertical columns and spaced horizontal rows, the plurality of spaced vertical columns and spaced horizontal rows being of the first dielectric material 1639. However, embodiments of the disclosure are not limited to an oxide material. For example, the first dielectric material 1639 deposited to form the plurality of spaced vertical columns and spaced horizontal rows can be a nitride, silicon-nitride, silicon dioxide, silicon oxy-carbide, and / or any other suitable dielectric material.

[0133] Figure 16B-1 is a cross-sectional view, taken along cut-line B-B’ in Figure 9A, showing a view' of the semiconductor structure at another particular time in the semiconductor fabrication process. As illustrated in Figure 16B-1, the dielectric material 1639 separating the vertical spaces between horizontally neighboring access devices and separating the horizontal spaces between vertically neighboring access devices (e.g., top and bottom access devices as oriented in Figure 16A-1) has been deposited. The deposited dielectric material 1639 can accordingly form a plurality of spaced columns of dielectric material 1694-1, 1694-2, as well as spaced horizontal rows 1696 ofdielectric material 1639. The spaced horizontal rows 1696 can be located between each of the spaced vertical columns 1694-1, 1694-2, and can be patterned vertically in a third direction (e.g., upwards and downw ards, as oriented in Figure 16B-1). The spaced vertical columns 1694-1, 1694-2 can be patterned horizontally in a first direction (e.g., direction DI / 909, as illustrated in Figure 9C).

[0134] Figure 16B-2 is another cross-sectional view, taken along cut-line A-A’ in Figure 9A, showing a view of the semiconductor structure at another particular time in the semiconductor fabrication process. As illustrated in Figure 16B-2, the dielectric material 1639 separating the vertical spaces betw een horizontally neighboring access devices and separating the horizontal spaces between vertically neighboring access devices (e.g., top and bottom access devices as oriented in Figure 16A-1) has been deposited.

[0135] As mentioned in Figure 16B-1, the spaced horizontal row s of dielectric material 1696 can be formed and, according to embodiments, may- have a vertical thickness (Vt) that is less than a horizontal width (Hw) of the deposited vertical columns 1694-1 and 1694-2 of dielectric material 1639. As illustrated in Figure 16B-2, the spaced horizontal row s 1696 of the first dielectric material 1639 can extend outwards in a direction D2 (e.g., direction D2 / 905 as illustrated in Figure 9B). The spaced horizontal rows 1696 of dielectric material 1696 can extend in the direction D2 further than the Si material 1 32.

[0136] Additionally, in the orientation of Figure 16B-2, the spaced vertical columns 1694-1, 1694-2 of dielectric material 1639 can also extend in the direction D2. Accordingly, the deposition of the first dielectric material 1639 can form a continuous barrier surface around each of the first source / drain regions (e.g., each portion of Silicon material 1632 and ILD fill material 1667). As a first step of epitaxial growth of Si material from the first source / drain regions occurs, the continuous barrier surface can prevent vertical and horizontal merging of the epitaxially growing Si material from occurring, as is further described herein.

[0137] Figure 16C-1 is a cross-sectional view, taken along cut-line B-B’ in Figure 9A, showing a view- of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 16C-1, deposited dielectric material 1639 can accordingly form a plurality of spacedcolumns 1694-1, 1694-2 of dielectric material 1639, as well as spaced horizontal rows 1696 of dielectric material 1639 forming a continuous barrier surface of dielectric material 1639 around each of the first source / drain regions.

[0138] Figure 16C-2 is another cross-sectional view, taken along cut-line A-A’ in Figure 9A, showing a view of the semiconductor structure at another particular time in the semiconductor fabrication process. The semiconductor fabrication process can include epitaxially growing Si material from the first source / drain regions between the spaced vertical columns 1694-1 and 1694-2 of dielectric material 1639 and the horizontal rows 1696 of dielectric material 1639. For example, Si material can be selectively epitaxially grown a first amount at the first source / drain regions (e.g., from the Si material 1632) between the spaced vertical columns 1694 and the spaced horizontal rows 1696 to form Silicon nodules 1697 of Si material 1632. According to embodiments, the Si material is selectively epitaxially grown a first amount at the first source / drain regions by flowing a silane gas to the exposed Si first source / drain regions in a timed manner at appropriate concentrations, pressures and temperatures to realize a particular growth rate such that epitaxially grown Si 1697, e.g., silicon nodules, is formed, e.g., grown, within the continuous barrier surface around each of the first source / drain regions.

[0139] The spaced horizontal rows 1696 of dielectric material 1639 can prevent vertical merging of the Silicon nodules 1697 of Si material 1632 and the spaced vertical columns 1694 of dielectric material 1639 prevent horizontal merging of the Silicon nodules 1697 of Si material 1632 at this point in the semiconductor fabrication process. The Silicon nodules 1697 are not intended to horizontally merge, as horizontal merger would form horizontal short circuits in the 3D memory array. While ultimately the Silicon nodules 1697 are intended to vertically merge, the continuous barrier surface created by the spaced vertical columns 1694 and spaced horizontal rows 1696 of dielectric material 1639 can prevent both vertical and horizontal merging of the epitaxially grown Silicon nodules 1697 at this point in the semiconductor fabrication process.

[0140] Figure 16D-1 is a cross-sectional view, taken along cut-line B-B’ in Figure 9A, showing a view- of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 16D-1, deposited dielectric material 1639 formed a plurality of spaced rows 1696 andcolumns 1694-1, 1694-2 of dielectric material 1639, and Silicon nodules 1697 of Si material 1632 have been epitaxially grown a first amount. According to embodiments, and as shown in the cross-sectional view of Figure 16, the horizontal rows 1696 and columns 1694-1 and 1694-2 of dielectric material 1639 can be selectively recessed in a timed manner to form recessed rows, e.g., 1698 of dielectric material 1639.

[0141] Figure 16D-2 is another cross-sectional view, taken along cut-line A-A’ in Figure 9A, showing a view of the semiconductor structure at another particular time in the semiconductor fabrication process. The semiconductor fabrication process can include recessing the spaced horizontal rows 1696 and columns 1694-1, 1694-2 of dielectric material 1639 to form recessed rows and columns 1698 of dielectric material 1639. The spaced horizontal rows 1696 and columns 1694-1, 1694-2 of dielectric material 1639 may be recessed using a selective etchant process, as previously described herein.

[0142] As illustrated in Figure 16D-2, the recessed rows and columns 1698 can allow for expansion, growth space between the Si nodules 1697. The space provided by the recessed rows and columns 1698 can allow for further vertical epitaxial growth of the Silicon nodules 1697, as is further described herein.

[0143] Figure 16E-1 is a cross-sectional view, taken along cut-line B-B’ in Figure 9A, showing a view of the semiconductor structure at a particular time in the semiconductor fabrication process. As illustrated in Figure 16E-1, the Silicon nodules 1697 of Si material 1632 have been epitaxially grown a second amount, allowing for vertical merging to form a vertically oriented digit line 1692 of Si material 1632 located between the vertical columns 1694-1, 1694-2 of dielectric material 1639.

[0144] Figure 16E-2 is another cross-sectional view, taken along cut-line A-A’ in Figure 9A, showing a view of the semiconductor structure at another particular time in the semiconductor fabrication process. The semiconductor fabrication process can include further epitaxially growing each of the Silicon nodules 1697 of Si material 1632 a second amount. The presence of the vertical columns 1694-1, 1694-2 of dielectric material 1639 prevents horizontal epitaxial growth and can prevent horizontal merging (e.g., in the second direction) of the Silicon nodules 1697 of Si material 1632. However, the recessed row andcolumns 1698 can allow for continued epitaxial grow th of the Silicon nodules 1697 until the Silicon nodules 1697 vertically merge in the third direction to form the continuous, vertically oriented digit line 1692.

[0145] At this point in the semiconductor fabrication process, the continuous, vertically oriented digit lines 1692 are still epitaxially grown Si material 1632. For example, the vertically oriented digit lines 1692 can be single crystalline and / or poly crystalline, doped, epitaxially grown Si material. As such, the semiconductor fabrication process can further include converting the continuous, vertically oriented digit lines 1692 from the epitaxially grown Si material to a conductive material having a different characteristic from the Si material.

[0146] The epitaxially grown Si material of the vertically oriented digit lines 1692 can be converted to conductive material (e.g., tungsten material). For instance, a tungsten hexafluoride (WF6) material can be selectively reacted with the remaining Si material. For example, the tungsten hexafluoride material can be flowed into the third vertical opening to expose the digit line 1692 to the tungsten hexafluoride material, such that the (e.g., exposed) vertically oriented digit lines 1692 are soaked with the tungsten hexafluoride, causing the tungsten material to grow. This reaction can be expressed chemically as:with the change in enthalpy for the reaction being -1908 KJ / mole. The tungsten hexafluoride may target all iterations of the vertically oriented digit lines 1692 in the stack.

[0147] The tungsten hexafluoride material, however, may react only with the epitaxially grown Si material. For instance, the tungsten hexafluoride material may not react with dielectric material, source / drain region, or oxide material. Hence, the conversion process may be selective to the epitaxially grown Si material of the continuous, vertically oriented digit lines 1692. For instance, the dielectric material, source / drain region, and oxide material may be left intact during the conversion process, and the source / drain region may remain nearly untouched by the conversion process.

[0148] As such, the epitaxially grown Si material can be converted into a conductive material to function as a vertically oriented digit line. The vertically oriented digit line formation as described above can be utilized in verticalopenings having high aspect ratios, such as 5: 1 vertical / horizontal aspect ratio specifications, or even higher.

[0149] Figure 17 is a block diagram of an apparatus in the form of a computing system 1700 including a memory device 1703 in accordance with a number of embodiments of the present disclosure. As used herein, a memory device 1703, a memory array 1710, and / or a host 1702, for example, might also be separately considered an “apparatus.” According to embodiments, the memon device 1703 may comprise at least one memory array 1710 with a memon cell formed having a digit line and body contact, according to the embodiments described herein.

[0150] In this example, system 1700 includes a host 1702 connected to memory device 1703 via an interface 1704. The computing system 1700 can be a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, a memory card reader, or an Intemet-of-Things (loT) enabled device, among various other types of systems. Host 1702 can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing memory 1703. The system 1700 can include separate integrated circuits, or both the host 1702 and the memory device 1703 can be on the same integrated circuit. For example, the host 1702 may be a system controller of a memory system comprising multiple memory devices 1703, with the system controller 1702 providing access to the respective memory' devices 2403 by another processing resource such as a central processing unit (CPU).

[0151] In the example shown in Figure 17. the host 1702 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded thereto (e.g., from memory device 1703 via controller 1702). The OS and / or various applications can be loaded from the memory device 1703 by providing access commands from the host 1702 to the memory device 1703 to access the data comprising the OS and / or the various applications. The host 1702 can also access data utilized by the OS and / or various applications by providing access commands to the memory' device 1703 to retrieve said data utilized in the execution of the OS and / or the various applications.

[0152] For clarity, the system 1700 has been simplified to focus on features w ith particular relevance to the present disclosure. The memory array 1710 can be a DRAM array comprising at least one memory cell having a digit line and body contact formed according to the techniques described herein. For example, the memory array 1710 can be an unshielded DL 4F2 array such as a 3D-DRAM memory’ array. The array 1710 can comprise memory cells arranged in rows connected by word lines (which may be referred to herein as access lines or select lines) and columns connected by digit lines (which may be referred to herein as sense lines or data lines). Although a single array 1710 is shown in Figure 17, embodiments are not so limited. For instance, memory device 1703 may include a number of arrays 1710 (e.g.. a number of banks of DRAM cells).

[0153] The memory' device 1703 includes address circuitry 1706 to latch address signals provided over an interface 1704. The interface can include, for example, a physical interface employing a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). Such protocol may be custom or proprietary, or the interface 1704 may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, or the like. Address signals are received and decoded by a row decoder 1708 and a column decoder 1712 to access the memory array 1710. Data can be read from memory array 1710 by sensing voltage and / or current changes on the sense lines using sensing circuitry 171 1. The sensing circuitry' 1711 can comprise, for example, sense amplifiers that can read and latch a page (e.g., row) of data from the memory array 1710. The I / O circuitry 1707 can be used for bi-directional data communication with the host 1702 over the interface 1704. The read / write circuitry 1713 is used to write data to the memory' array 1710 or read data from the memory' array 1710. As an example, the circuitry 1713 can comprise various drivers, latch circuitry, etc.

[0154] Control circuitry’ 1705 decodes signals provided by the host 1702. The signals can be commands provided by the host 1702. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory' array 1710, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry 1705 is responsible for executing instructions from the host 1702. The control circuitry 1705 can comprise a state machine, asequencer, and / or some other type of control circuitry, which may be implemented in the form of hardware, firmware, or software, or any combination of the three. In some examples, the host 1702 can be a controller external to the memory device 1703. For example, the host 1702 can be a memory7controller which is connected to a processing resource of a computing device.

[0155] The term semiconductor can refer to, for example, a material, a wafer, or a substrate, and includes any base semiconductor structure.“Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film-transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a base semiconductor structure, as well as other semiconductor structures. Furthermore, when reference is made to a semiconductor in the preceding description, previous process steps may have been utilized to form regions / j unctions in the base semiconductor structure, and the term semiconductor can include the underlying materials containing such regions / junctions.

[0156] The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar (e.g., the same) elements or components between different figures may be identified by the use of similar digits. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and / or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the embodiments of the present disclosure and should not be taken in a limiting sense.

[0157] As used herein, “a number of’ or a “quantity of’ something can refer to one or more of such things. For example, a number of or a quantity of memory cells can refer to one or more memon cells. A “plurality” of something intends two or more. As used herein, multiple acts being performed concurrently refers to acts overlapping, at least in part, over a particular time period. As used herein, the term “connected” may include electrically connected, directly- connected, and / or directly connected with no intervening elements (e.g., by direct physical contact), indirectly connected and / or connected with interveningelements, or wirelessly connected. The term connected may further include two or more elements that co-operate or interact with each other (e.g., as in a cause and effect relationship). An element connected between two elements can be between the two elements and connected to each of the two elements.

[0158] It should be recognized the term vertical accounts for variations from "‘exactly” vertical due to routine manufacturing, measuring, and / or assembly variations and that one of ordinary skill in the art would know what is meant by the term “perpendicular.” For example, the vertical can correspond to the z-direction. As used herein, when a particular element is “adjacent to” an other element, the particular element can cover the other element, can be over the other element or lateral to the other element and / or can be in direct physical contact the other element. Lateral to may refer to the horizontal direction (e.g., the y-direction or the x-direction) that may be perpendicular to the z-direction, for example.

[0159] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claims

What is claimed is:

1. A method for forming arrays of vertically stacked memory cells, comprising: forming a vertical stack having alternating layers of silicon germanium (SiGe) material and silicon (Si) material from a substrate, the vertical stack having vertically stacked memory cells comprising respective horizontally oriented access devices and horizontally oriented storage nodes, wherein the horizontally oriented access device comprise respective gates, channel regions, first source / drain regions, and second source / drain regions; forming a plurality of first vertical opening through the vertical stack and extending predominantly in a first horizontal direction; forming a plurality of spaced vertical columns adjacent to the first source / drain regions; and epitaxially growing Si material from the first source / drain regions vertically between the plurality spaced vertical columns to form continuous, vertically oriented digit lines in the first vertical openings.

2. The method of claim 1, wherein: forming the plurality of spaced vertical columns includes depositing a first dielectric material to form the plurality of spaced vertical columns; and wherein the method further includes depositing the first dielectric material to form a plurality of spaced horizontal rows between the plurality of spaced vertical columns and between each of the first source / drain regions in a third direction.

3. The method of claim 2, wherein the method includes depositing the first dielectric material via area selective deposition (ASD).

4. The method of claim 2, wherein: the method includes selectively epitaxially growing the Si material a first amount at the first source / drain regions between the plurality' of spaced vertical columns and the spaced horizontal rows to form Si nodules between the pluralityof spaced vertical columns having the spaced horizontal rows located therebetween; the spaced horizontal rows preventing vertical merging of the Si nodules; and the spaced vertical columns preventing horizontal merging of the Si nodules grown to the first amount.

5. The method of claim 4, wherein the method includes recessing the spaced horizontal rows to allow for vertical epitaxial growth of the Si nodules in the third direction.

6. The method of claim 5, wherein the method includes further epitaxially growing each of the Si nodules a second amount until the Si nodules vertically merge in the third direction to form the continuous, vertically oriented digit lines.

7. The method of any one of claims 1-6, wherein the method further includes forming the vertical stack having a plurality7of levels where the horizontally oriented storage nodes are located at each level of the plurality of levels to form the arrays of vertically stacked memory cells.

8. The method of any one of claims 1-6, wherein the method includes converting the continuous, vertically oriented digit lines from the Si material to a conductive material having a different characteristic from the Si material.

9. The method of any one of claims 1-6, wherein forming the horizontally oriented access devices and the horizontally oriented storage nodes at each level of the vertical stack comprises; forming a plurality of second vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack, the second vertical openings extending predominantly in the second horizontal direction to form elongated vertical columns with first vertical sidewalls in the stack, separating memory cells on each level;doping the first source / drain region of the Si layers at the second vertical opening; filling the plurality of second vertical openings with a first dielectric material; forming a third vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose second vertical sidewalls in the stack; selectively etching the silicon germanium (SiGe) layers and reducing a vertical thickness of the Si layers to form a plurality of first horizontal openings a first length (LI) from the third vertical opening; conformally depositing a second dielectric material on exposed surfaces in the plurality of first horizontal openings; depositing the first dielectric material to fill the plurality of first horizontal openings; selectively etching the second dielectric material from the plurality of first horizontal openings a second length (L2) from the second vertical opening; forming a gate dielectric material on exposed surfaces of the reduced vertical thickness of the Si layers; depositing a first conductive material on the Si layers to form gate all around (GAA) structures at the channel regions of the access devices; recessing the first conductive material to the channel regions; and capping the first horizontal openings with the second dielectric material.

10. The method of any one of claims 1-6, wherein the method includes recessing the second dielectric material to expose the first source / drain regions.

11. A method for forming array s of vertically stacked memory cells, comprising: forming a vertical stack having alternating layers of silicon germanium (SiGe) material and silicon (Si) material from a substrate, the vertical stack having vertically stacked memory cells comprising respective horizontally oriented access devices and respective horizontally oriented storage nodes, wherein the horizontally oriented access devices comprise respective gates, channel regions, first source / drain regions, and second source / drain regions;forming first vertical openings through the vertical stack and extending predominantly in a first horizontal direction; patterning a plurality of spaced vertical columns adjacent to the first source / drain regions; and epitaxially growing Si material from the first source / drain regions vertically between the plurality spaced vertical columns to form continuous vertically oriented digit lines in the first vertical openings.

12. The method of claim 11, wherein patterning the plurality of spaced vertical columns includes: filling the first vertical openings with carbon material; and patterning vertical openings in the carbon material.

13. The method of claim 12, wherein the method further includes: filling the vertical openings in the carbon material a dielectric material to form alternating vertical columns of carbon material and the second dielectric material; and patterning the plurality7of spaced vertical columns further includes exhuming the vertical columns of carbon material to expose the first source / drain regions, wherein the vertical columns of the second dielectric material remain.

14. The method of claim 13, wherein the method includes epitaxially growing the Si material at the first source / drain regions in the first vertical openings between the columns of the second dielectric material until the epitaxially grown Si material merges to form the continuous vertically oriented digit lines.

15. The method of claim 14, wherein the method includes exhuming the columns of the second dielectric material such that the continuous vertically oriented digit lines remain.

16. The method of any one of claims 15, wherein the method includes converting the continuous vertically oriented digit lines from the Si material to a conductive material having a different characteristic from the Si material.

17. The method of any one of claims 15, wherein forming the horizontally oriented access devices and horizontally oriented storage nodes at each level of the vertical stack comprises: forming a plurality of second vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack, the second vertical openings extending predominantly in the second horizontal direction to form elongated vertical columns with first vertical sidewalls in the stack, separating memory cells on each level; doping the first source / drain region of the Si layers at the second vertical opening; filling the plurality of second vertical openings with a first dielectric material; forming a third vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose second vertical sidewalls in the stack; selectively etching the silicon germanium (SiGe) layers and reducing a vertical thickness of the Si layers to form a plurality of first horizontal openings a first length (LI) from the third vertical opening; conformally depositing a second dielectric material on exposed surfaces in the plurality of first horizontal openings; depositing the first dielectric material to fill the plurality of first horizontal openings; selectively etching the second dielectric material from the plurality of first horizontal openings a second length (L2) from the second vertical opening; forming a gate dielectric material on exposed surfaces of the reduced vertical thickness of the Si layers; depositing a first conductive material on the Si layers to form gate all around (GAA) structures at the channel regions of the access devices; recessing the first conductive material to the channel regions;capping the first horizontal openings with the second dielectric material: and recessing the second dielectric material to expose the first source / drain regions.

18. A memory device, comprising: a plurality vertically stacked memory cells having respective horizontally oriented access devices and horizontally oriented storage nodes, wherein: the horizontally oriented access devices include respective channel regions, first source / drain regions, second source / drain regions, and gates on a gate dielectric material; and the horizontally oriented storage nodes are formed horizontally on the second source / drain regions of the horizontally oriented access devices; and a vertical digit line that is epitaxially formed from the first source / drain regions of the horizontally oriented access devices.

19. The memory device of claim 18, further comprising horizontally oriented access lines forming the respective gates of the horizontally oriented access devices.

20. The memory device of claim 19, wherein the horizontally oriented access lines are gate all around (GAA) structures.

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