Chip, networking system, and electronic device

Abstract

Embodiments of the present application provide a chip, a networking system, and an electronic device. The chip is applied to a target node comprised in a networking system; the networking system comprises multiple connected nodes; the multiple nodes include a master node and at least one child node; and the target node is any node among the multiple nodes. The chip comprises: a storage unit, a control unit, and an execution unit. The storage unit is used for storing an instruction to be executed issued by the master node in the networking system; the control unit is used for reading said instruction from the storage unit, parsing said instruction to obtain an instruction type of said instruction, and sending the instruction type of said instruction to the execution unit; and the execution unit is used for executing said instruction on the basis of the instruction type of said instruction. Applying the chip provided by the present application can improve the execution efficiency of instructions to be executed issued by a central controller in the master node.

Description

Chip, networking system and electronic device TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronic communication, and particularly relate to a chip, a networking system and an electronic device. BACKGROUND

[0002] Nowadays, the devices and functions on vehicles tend to be diversified, and there are multiple data transmissions in vehicles to meet different application scenarios of vehicle systems. The mainstream scheme of vehicle data transmission at present is based on Ethernet and Controller Area Network (CAN) bus transmission. However, with the development of intelligence, the CAN bus cannot meet the requirements of transmission rate and time delay, and the current vehicle Ethernet adopts traditional communication based on switches. Although it is mature and reliable, it needs more switches to connect multiple Electronic Control Units (ECUs) in the vehicle, which is obviously high in cost and complex to implement, cannot support more flexible node interconnection scenarios and complex communication structure applications, and has large transmission time delay.

[0003] In order to solve the above problems, at present, by using a networking system, a link transmission method is adopted to transmit data from multiple nodes. The micro control units in the multiple nodes can execute tasks issued by the master device, thereby supporting more flexible node interconnection scenarios and complex communication structure applications.

[0004] However, when the micro control units in the nodes process the tasks issued by the master node, the programs stored in the micro control units need to be programmed for the tasks issued by the master device, and the master device also needs to be reported before and after execution, resulting in a long time for task response.

[0005] SUMMARY

[0006] Therefore, embodiments of the present application provide a chip, a networking system and an electronic device to at least partially solve the above problems.

[0007] According to a first aspect of the embodiments of the present application, a chip is provided, which is applied to a target node in a networking system, the networking system including a plurality of connected nodes, the plurality of nodes including a master node and at least one slave node, the target node being any one of the plurality of nodes, and the chip including a storage unit, a control unit and an execution unit; the storage unit is configured to store a to-be-executed instruction issued by the master node; the control unit is configured to read the to-be-executed instruction from the storage unit, analyze the to-be-executed instruction, obtain an instruction type of the to-be-executed instruction, and send the instruction type of the to-be-executed instruction to the execution unit; and the execution unit is configured to execute the to-be-executed instruction according to the instruction type of the to-be-executed instruction.

[0008] In a possible implementation, the control unit is configured to read the to-be-executed instruction from the storage unit according to a count value of an instruction counter, the instruction counter increasing the count value by a period, and the count value of the instruction counter in each period being positively correlated with a length of the to-be-executed instruction.

[0009] In a possible implementation, the chip further includes a temporary storage unit, and the temporary storage unit is configured to store source operands and destination operands in the process of executing the to-be-executed instruction by the execution unit.

[0010] In a possible implementation, the temporary storage unit includes a plurality of registers, or the storage unit includes the temporary storage unit.

[0011] In a possible implementation, the execution unit includes an operation subunit and a read-write subunit; the operation subunit is configured to perform logical operation according to the instruction type of the to-be-executed instruction; and the read-write subunit is configured to read and write the temporary storage unit and / or a peripheral device connected to the target node according to a logical operation result of the operation subunit after receiving the logical operation result.

[0012] In a possible implementation, the control unit is configured to determine the instruction type of the to-be-executed instruction according to a value of an instruction type field in the to-be-executed instruction, and the instruction type includes at least one of an interrupt instruction, a memory access instruction, a conditional jump instruction and a calculation instruction.

[0013] In a possible implementation, the interrupt instruction includes an interrupt state read instruction and an interrupt state write instruction; the control unit is configured to send a first address in the to-be-executed instruction to the operator unit, so that the operator unit writes a state bit into the first address in the temporary storage unit when the to-be-executed instruction is the interrupt state read instruction, and send a second address in the to-be-executed instruction to the temporary storage unit, so that the temporary storage unit sends a source operand stored in the second address to the operator unit, and the operator unit updates a state bit to the source operand stored in the second address in the temporary storage unit when the to-be-executed instruction is the interrupt state write instruction.

[0014] In a possible implementation, the memory instruction includes a memory read instruction and a memory write instruction; the control unit is configured to send a third address, a first base address and a first offset in the to-be-executed instruction to the operator unit, and send a read request to the read-write subunit when the to-be-executed instruction is the memory read instruction, the operator unit determines a first peripheral address according to the first base address and the first offset, and sends the first peripheral address and the third address to the read-write subunit, the read-write subunit reads first data from a corresponding peripheral according to the read request and the first peripheral address, and writes the first data into the third address in the temporary storage unit; the control unit is configured to send a fourth address in the to-be-executed instruction to the temporary storage unit, and send a second base address and a second offset in the to-be-executed instruction to the operator unit, and send a write request to the read-write subunit when the to-be-executed instruction is the memory write instruction, the temporary storage unit sends second data stored in the fourth address to the operator unit, the operator unit determines a second peripheral address according to the second base address and the second offset, and sends the second data and the second peripheral address to the read-write subunit, and the read-write subunit writes the second data into a peripheral corresponding to the second peripheral address according to the write request.

[0015] In a possible implementation, the control unit is configured to send a fifth address in the conditional jump instruction to the temporary storage unit, and send an immediate number in the conditional jump instruction to the operator unit when the to-be-executed instruction is the conditional jump instruction, the temporary storage unit sends third data stored in the fifth address to the operator unit, the operator unit judges whether the third data meets a condition, and determines a first target count value of the instruction counter according to the immediate number if the third data meets the condition, and sends the first target count value to the control unit, and the control unit reads a to-be-executed instruction corresponding to the first target count value from the temporary storage unit according to the first target count value.

[0016] In a possible implementation, the computing instruction includes a shift instruction and a numerical computing instruction; when the to-be-executed instruction is the shift instruction, the control unit sends a sixth address in the to-be-executed instruction to the temporary storage unit and sends an immediate number in the to-be-executed instruction to the operation subunit, the temporary storage unit sends fourth data stored in the sixth address to the operation subunit, the operation subunit performs arithmetic or logical shift on the fourth data by using the immediate number, obtains fifth data, and sends the fifth data and the sixth address to the read-write subunit, the read-write subunit writes the fifth data into the sixth address of the temporary storage unit, or the control unit sends a seventh address and an eighth address in the to-be-executed instruction to the temporary storage unit, the temporary storage unit sends sixth data stored in the seventh address and a shift numerical value stored in the eighth address to the operation subunit, the operation subunit performs arithmetic or logical shift on the sixth data by using the shift numerical value, obtains seventh data, and sends the seventh data and the seventh address to the read-write subunit, and the read-write subunit writes the seventh data into the seventh address of the temporary storage unit; when the to-be-executed instruction is the numerical computing instruction, the control unit sends a ninth address in the to-be-executed instruction to the temporary storage unit and sends an immediate number in the to-be-executed instruction to the operation subunit, the temporary storage unit sends eighth data stored in the ninth address to the operation subunit, the operation subunit performs arithmetic operation on the eighth data and the immediate number, obtains ninth data, and sends the ninth data and the ninth address to the read-write subunit, the read-write subunit writes the ninth data into the ninth address of the temporary storage unit, or the control unit sends a tenth address and an eleventh address in the to-be-executed instruction to the temporary storage unit, the temporary storage unit sends tenth data stored in the tenth address and eleventh data stored in the eleventh address to the operation subunit, the operation subunit performs logical operation on the tenth data and the eleventh data, obtains twelfth data, and sends the twelfth data and the tenth address to the read-write subunit, the read-write subunit writes the twelfth data into the tenth address of the temporary storage unit, or the control unit sends a thirteenth address in the to-be-executed instruction to the temporary storage unit and sends a twelfth address in the to-be-executed instruction to the operation subunit, the temporary storage unit sends thirteenth data stored in the thirteenth address to the operation subunit, the operation subunit sends the thirteenth data and the twelfth address to the read-write subunit, and the read-write subunit writes the thirteenth data into the twelfth address of the temporary storage unit.

[0017] In a possible implementation, the control unit is configured to read an unconditional jump instruction and an unconditional jump and link instruction from the storage unit; when the unconditional jump instruction is read, the control unit reads, according to an immediate number in the unconditional jump instruction, a to-be-executed instruction corresponding to a second target count value of the instruction counter indicated by the immediate number from the storage unit, or reads, according to a first jump value stored in a fourteenth address in the unconditional jump instruction, a to-be-executed instruction corresponding to a third target count value of the instruction counter indicated by the first jump value from the storage unit; when the unconditional jump and link instruction is read, the control unit sends a count value of an instruction counter corresponding to the unconditional jump and link instruction to the read-write subunit, the read-write subunit writes the count value of the instruction counter into the temporary storage unit, the control unit reads, according to an immediate number in the unconditional jump and link instruction, a to-be-executed instruction corresponding to a fourth target count value of the instruction counter indicated by the immediate number from the storage unit, or reads, according to a second jump value stored in a fifteenth address in the unconditional jump instruction, a to-be-executed instruction corresponding to a fifth target count value of the instruction counter indicated by the second jump value from the storage unit.

[0018] In a possible implementation, the control unit includes a reading subunit and an analysis subunit; the reading subunit is configured to read the to-be-executed instruction from the storage unit and send the to-be-executed instruction to the analysis subunit; and the analysis subunit is configured to analyze the to-be-executed instruction, obtain an instruction type of the to-be-executed instruction, and send the instruction type of the to-be-executed instruction to the execution unit.

[0019] According to a second aspect of the embodiment of the present application, a networking system is provided, including: a plurality of connected nodes, the plurality of nodes including a master node and at least one slave node, and a target node in the plurality of nodes including the chip according to the first aspect of the embodiment of the present application, the target node being any one of the plurality of nodes.

[0020] According to a third aspect of the embodiment of the present application, an electronic device is provided, including the chip according to the first aspect of the embodiment of the present application.

[0021] According to the chip provided in the embodiment of the present application, the chip is arranged in the target node, the chip comprises a storage unit, a control unit and an execution unit, the storage unit can store the to-be-executed instruction issued by the master node, the control unit can analyze the to-be-executed instruction to determine the instruction type, and thus the to-be-executed instruction can be executed by the execution unit according to the instruction type to complete the task issued by the master control. Since the chip is arranged in the target node and can execute the task issued by the master control, the MCU arranged in the node in the prior art can be replaced in the target node, that is, the sub-node does not need to additionally arrange the MCU, and the sub-node can be directly remotely controlled by the master control through the networking link connected between the nodes, or some response tasks can be processed in real time by the sub-node itself. Since the to-be-executed instruction issued by the master node is directly received by the storage unit, the instruction conversion of the task issued by the master control through the program stored in the non-volatile memory is not needed, and thus the efficiency of determining the to-be-executed instruction can be improved. Since the to-be-executed instruction can be executed by the chip, the master control in the master node does not need to be reported through the link, the time delay of data transmission and processing is reduced, and the efficiency of processing the to-be-executed instruction can be improved, so that the efficiency of processing the task issued by the master control through the chip is high. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0023] Fig. 1 is a schematic diagram of a networking system provided in an embodiment of the present application;

[0024] Fig. 2 is a schematic diagram of another networking system provided in an embodiment of the present application;

[0025] Fig. 3 is a schematic diagram of a chip provided in an embodiment of the present application;

[0026] Fig. 4 is a schematic diagram of a chip comprising a temporary storage unit provided in an embodiment of the present application;

[0027] Fig. 5 is a schematic diagram of a chip comprising an operation sub-unit and a read-write sub-unit provided in an embodiment of the present application;

[0028] Fig. 6 is a schematic diagram of another chip comprising an operation sub-unit and a read-write sub-unit provided in an embodiment of the present application;

[0029] Fig. 7 is a schematic diagram of a to-be-executed instruction with an instruction type of an interrupt instruction provided in an embodiment of the present application;

[0030] FIG. 8 is a schematic diagram of an instruction to be executed according to an embodiment of the present application, where the instruction type is a memory access instruction;

[0031] FIG. 9 is a schematic diagram of an instruction to be executed according to an embodiment of the present application, where the instruction type is a conditional jump instruction;

[0032] FIG. 10 is a schematic diagram of an instruction to be executed according to an embodiment of the present application, where the instruction type is a shift instruction;

[0033] FIG. 11 is a schematic diagram of an instruction to be executed according to an embodiment of the present application, where the instruction type is a numerical computation instruction;

[0034] FIG. 12 is a schematic diagram of another instruction to be executed according to an embodiment of the present application;

[0035] FIG. 13 is a schematic diagram of an unconditional jump instruction and an unconditional jump and link instruction according to an embodiment of the present application;

[0036] FIG. 14 is a schematic diagram of a chip including a reading subunit and a parsing subunit according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the personnel in the art better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and in detail below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art should belong to the scope of protection of the embodiments of the present application.

[0038] As described above, the devices and functions on vehicles tend to be diversified, and various data transmission exists in vehicles to meet different application scenarios of vehicle systems. At present, the mainstream scheme of vehicle data transmission is based on Ethernet and Controller Area Network (CAN) bus transmission. However, with the development of intelligence, the CAN bus cannot meet the requirements of transmission rate and time delay, and the current vehicle Ethernet adopts traditional communication based on switches. Although it is mature and reliable, it needs more switches to connect multiple Electronic Control Units (ECUs) in the vehicle, which is obviously high in cost and complex in implementation, cannot support more flexible node interconnection scenarios and complex communication structure applications, and has large transmission time delay. In order to solve the above problems, at present, a networking system is used to adopt a link transmission method to transmit data through a link composed of multiple nodes. The micro control units in the multiple nodes can execute tasks issued by a master device, thereby supporting more flexible node interconnection scenarios and complex communication structure applications. However, when processing the tasks issued by the master node, the micro control units in the multiple nodes need to program the tasks issued by the master device through the programs stored in the micro control units, and report to the master device before and after execution, which results in long task response time. In addition, the multiple nodes contain micro control units, which results in high cost of the overall system. The micro control unit is, for example, a Microcontroller Unit (MCU).

[0039] In the embodiments of the present application, a chip is provided, which is arranged in a target node. The chip includes a storage unit, a control unit and an execution unit. The storage unit can store to-be-executed instructions issued by a master node. The control unit can analyze and determine the type of the to-be-executed instructions, so that the execution unit can execute the to-be-executed instructions according to the type of the instructions to complete the tasks issued by the master control. Since the chip is arranged in the target node and can execute the tasks issued by the master control, the MCU arranged in the node in the prior art can be replaced in the target node, that is, the sub-node does not need to additionally arrange an MCU, and the master control of the master node can remotely control the sub-node through the networking link connected between the nodes, or the sub-node can process some response tasks in real time. Since the to-be-executed instructions issued by the master node are directly received through the storage unit, the tasks issued by the master control do not need to be converted by the programs stored in the non-volatile memory, so that the efficiency of determining the to-be-executed instructions can be improved. Since the chip can execute the to-be-executed instructions, the master control in the master node does not need to be reported through the link, the time delay of data transmission and processing is reduced, and the efficiency of processing the to-be-executed instructions is improved, so that the efficiency of processing the tasks issued by the master control through the chip is high.

[0040] The chip provided by the present application will be described below through embodiments.

[0041] For the convenience of explaining the chip provided by the embodiments of the present application, first, a networking system is described. FIG. 1 is a schematic diagram of a networking system provided by an embodiment of the present application, and FIG. 2 is a schematic diagram of another networking system provided by an embodiment of the present application. As shown in FIG. 1 and FIG. 2, the networking system includes a plurality of connected nodes, which can include a master node and at least one slave node. The master node and each slave node are connected in turn to form a link. The master node can implement data sending to each slave node through data packets transmitted in turn in the link, and can also implement data collection from each slave node through data packets transmitted in turn in the link. The slave node can receive data packets transmitted in turn in the link and process the data packets according to the data packets.

[0042] Compared with the slave node, the master node further includes a control center, for example, an MCU or a central processing unit (CPU), so as to implement functions such as issuing instructions to the slave node and controlling the slave node. Therefore, the master node is usually a master device, and the slave node is usually a slave device.

[0043] The slave node or the master node can be connected to at least one external device. The master node and one slave node or a plurality of slave nodes can be connected through a physical transmission medium, for example, a shielded twisted pair, an unshielded twisted pair, a coaxial cable, etc.

[0044] Optionally, the external device connected by the sub-node or the master node described above includes a Local Interconnect Network (LIN) bus external device, a Pulse Width Modulation (PWM) drive device, an Inter-Integrated Circuit (I2C) external device, a Serial Peripheral Interface (SPI) bus external device, a Quad Serial Peripheral Interface (QSPI) bus external device, a General-purpose input / output (GPIO) external device, an Ethernet external device, a Controller Area Network (CAN) external device, a Media Independent Interface (MII) and various extensions and derivatives of the Media Independent Interface, a Universal Asynchronous Receiver / Transmitter (UART) external device, a Single Edge Nibble Transmission (SENT) bus external device, an external device of Peripheral Sensor Interface 5 (PSI5) protocol, an Inter-IC Sound (I2S) external device, a Time-Division Multiplexing (TDM) external device, an Analog Microphone (AMIC) external device, a Digital Microphone (DMIC) external device, and an Analog-to-digital converter (ADC) external device. The embodiments of the present application do not limit the specific type of the external device.

[0045] It should be understood that one topology example of the networking system is shown in FIG. 1, the chip 100 provided in the present application can be included in the master node, the MCU or CPU in the master node and the chip 100 provided in the present application jointly constitute the control center in the master node, and the chip 100 in the present application can be included in the sub-node, and the MCU does not need to be set. It should be understood that FIG. 1 only shows the scheme of one master node and one sub-node, but the topology of the networking system is not limited thereto. For example, as shown in FIG. 2, (a) of FIG. 2 shows a scheme in which the master node and multiple sub-nodes constitute a ring chain, and (b) of FIG. 2 shows a scheme in which the master node and multiple sub-nodes constitute a daisy chain. In addition, the networking system can also include other topology structure. The specific structure of the networking system is not limited in the embodiments of the present application.

[0046] FIG. 3 is a schematic diagram of a chip provided in an embodiment of the present application. As shown in FIG. 3, the chip 100 includes a storage unit 101, a control unit 102 and an execution unit 103. The storage unit 101 can store the to-be-executed instruction issued by the master node in the networking system. The control unit 102 can read the to-be-executed instruction from the storage unit 101, analyze the to-be-executed instruction, obtain the instruction type of the to-be-executed instruction, and send the instruction type of the to-be-executed instruction to the execution unit 103. The execution unit 103 can execute the to-be-executed instruction according to the instruction type of the to-be-executed instruction.

[0047] The chip 100 shown in FIG. 3 can be applied to the target node in the networking system. The target node can be any node in the networking system, for example, the master node and / or the sub-node in the networking system shown in FIG. 1 and FIG. 2. It should be understood that any node in the networking system can be provided with the chip 100, and the specific number of the chip 100 can be set as required.

[0048] The chip 100 comprises a storage unit 101, a control unit 102 and an execution unit 103. The storage unit 101 can store a to-be-executed instruction issued by a master node in a networking system. The to-be-executed instruction is binary data encoded according to a preset encoding rule. The to-be-executed instruction is generated by a central controller in the master node and is issued and directly or indirectly transmitted to the chip 100 in a target node. In an example, the to-be-executed instruction can be directly sent by the master node to the target node through an I2C or SPI bus, for example, the structure shown in FIG. 1, the target node is the sub-node A, and the to-be-executed instruction can be directly sent by the master node to the sub-node A. In another example, the to-be-executed instruction can be issued by the master node and forwarded to the target node through other nodes, for example, the structure shown in FIG. 1, the target node is the sub-node E, and the to-be-executed instruction can be sent by the master node to the sub-node G, then sent by the sub-node G to the sub-node F, and then sent by the sub-node F to the sub-node E. The storage unit 101 can be a memory with storage function, for example, a static random access memory (SRAM), a random access memory (RAM) and the like.

[0049] The control unit 102 in the chip 100 can read the to-be-executed instruction stored in the storage unit 101. In an example, the control unit 102 can read the to-be-executed instruction stored in the storage unit 101 periodically, for example, reading the to-be-executed instruction once every 10 ms. After the control unit 102 reads the to-be-executed instruction in the storage unit 101, the control unit 102 analyzes the to-be-executed instruction, determines the instruction type of the to-be-executed instruction, and the instruction type can represent the instruction operation logic of the to-be-executed instruction, for example, reading and writing a register, reading and writing a memory, numerical operation and the like. After the control unit 102 analyzes the instruction type, the control unit 102 sends the instruction type to the execution unit 103. It should be understood that the analysis result of the control unit 102 on the to-be-executed instruction at least includes the instruction type, and can also include related data for executing the corresponding type, which is not limited again.

[0050] The execution unit 103 can execute the to-be-executed instruction according to the instruction type analyzed by the analysis unit, for example, the execution unit 103 can execute the reading and writing register operation, the reading and writing peripheral device 200 memory operation and the like according to the instruction type.

[0051] Optionally, the chip 100 can further comprise a transceiver unit. The transceiver unit can receive instructions or data sent by a neighboring node (for example, a master node or a sub-node) of the target node, and then store the instructions or data to the storage unit 101, or the transceiver unit can send the data obtained after the execution of the execution unit 103 (or some data needed to be reported) to the neighboring node (for example, a master node or a sub-node) to realize the transmission of data.

[0052] In the embodiment of the present application, the target node is provided with a chip 100, the chip 100 includes a storage unit 101, a control unit 102 and an execution unit 103, the storage unit 101 can store the to-be-executed instruction issued by the central control of the master node, the control unit 102 can analyze and determine the instruction type of the to-be-executed instruction, and thus the to-be-executed instruction can be executed by the execution unit 103 according to the instruction type to complete the task issued by the central control. Since the target node is provided with the chip 100 and the chip 100 can execute the task issued by the central control, the MCU provided in the node in the prior art can be replaced in the target node, that is, the sub-node does not need to additionally provide the MCU, and the sub-node can be directly remotely controlled by the central control of the master node through the networking link connected between the nodes, or some response tasks can be processed in real time by the sub-node itself. Since the to-be-executed instruction issued by the master node is directly received by the storage unit 101, the task demand issued by the master control device needs to be converted by the program stored in the non-volatile memory, and thus the efficiency of determining the to-be-executed instruction can be improved. Since the to-be-executed instruction can be executed by the chip 100, the central control in the master node does not need to be reported through the link, the time delay of data transmission and processing is reduced, and the efficiency of processing the to-be-executed instruction can be improved, so that the efficiency of processing the task issued by the central control by the chip 100 is high.

[0053] In a possible implementation, the control unit 102 can read the to-be-executed instruction from the storage unit 101 according to the count value of the instruction counter. The instruction counter increases the count value by period. The count value increment of the instruction counter in each period is positively correlated with the length of the to-be-executed instruction.

[0054] The control unit 102 can be provided with an instruction counter. In an example, the instruction counter can be a register. The count value of the instruction counter increases by period, that is, a certain count value increment is added in each period, and the count value increment is positively correlated with the length of the to-be-executed instruction. For example, the count value increment can be linearly related to the length of the to-be-executed instruction. In an example, the count value increment can be equal to the ratio of the length of the to-be-executed instruction to 8. For example, if the length of the to-be-executed instruction is 16 bytes, the count value increment can be 2, that is, 16 / 8. If the length of the to-be-executed instruction is 32 bytes, the count value increment can be 4, that is, 32 / 8. It should be understood that 8 bytes is 1 byte, and 8 bytes is used as a unit to determine the byte number of the to-be-executed instruction as the count value increment.

[0055] The following is described in detail with an example. When the count value of the instruction counter is 2, the control unit 102 reads the data of the first byte and the second byte from the storage unit 101. After one cycle, the count value of the instruction counter becomes 4, and the control unit 102 reads the data of the third byte and the fourth byte from the storage unit 101. It should be understood that the above is described only as an example, and should not cause any limitation to the embodiments of the present application.

[0056] In the embodiments of the present application, the control unit 102 can read the to-be-executed instruction from the storage unit 101 according to the count value of the instruction counter. Thus, the control unit 102 can read the to-be-executed instruction issued by the master node and stored in the storage unit 101 in cycles. Since the control unit 102 reads the to-be-executed instruction according to the count value of the instruction counter which is incremented in cycles, the control unit 102 can prevent missing reading part of the instruction when reading the to-be-executed instruction. The to-be-executed instruction issued by the master node can be received and processed by the chip 100, and the practicability of the chip 100 is improved.

[0057] In a possible implementation, the chip 100 further includes a temporary storage unit 104. The temporary storage unit 104 can store the source operand and the destination operand in the process of executing the to-be-executed instruction by the execution unit 103.

[0058] The chip 100 further includes the temporary storage unit 104. The temporary storage unit 104 can store the source operand required by the execution unit 103 in the process of executing the to-be-executed instruction and the generated destination operand. It should be understood that the source operand generally refers to the data to be processed. When the execution unit 103 executes the to-be-executed instruction, the source operand provides the data operated by the execution unit 103. The destination operand is the result after the instruction execution, which can be obtained by logically operating the source operand by the execution unit 103.

[0059] In the embodiments of the present application, the chip 100 further includes the temporary storage unit 104. Thus, the data required to be read by the execution unit 103 in the process of executing the to-be-executed instruction, i.e., the source operand, and the data generated after the execution unit 103 executes the to-be-executed instruction, i.e., the destination operand, can be stored in the temporary storage unit 104. Thus, the execution unit 103 can execute the to-be-executed instruction and store the execution result, and it is ensured that the chip 100 can normally execute the to-be-executed instruction issued by the master node.

[0060] In a possible implementation, the temporary storage unit 104 includes a plurality of registers, or the storage unit 101 includes the temporary storage unit 104.

[0061] The temporary storage unit 104 can be the storage unit 101 in FIG. 3, that is, the source operand and the destination operand are stored through the storage unit 101 in FIG. 3. FIG. 4 is a schematic diagram of a chip including a temporary storage unit according to an embodiment of the present application. As shown in FIG. 4, the temporary storage unit 104 can be a plurality of registers provided in the chip 100, for example, the register 1 to the register n in FIG. 4. In an example, the registers can include a state register and an operand register. The state register can be used to store the state of the chip 100 and the state of the peripheral device 200, and the like. The operand register can be used to store the source operand and the destination operand, and the like.

[0062] In the embodiment of the present application, the storage unit 101 includes the temporary storage unit 104, so that part of the memory can be used as the temporary storage unit 104, and the additional registers of the peripheral device 200 can not be needed, thereby reducing the cost. The temporary storage unit 104 can also be a plurality of registers, so that compared with the above-mentioned scheme that the storage unit 101 includes the temporary storage unit 104, since the read-write speed of the registers is greater than the read-write speed of the storage unit 101, the data read-write efficiency can be improved, and the time delay of data transmission and processing is reduced.

[0063] FIG. 5 is a schematic diagram of a chip including an operation subunit and a read-write subunit according to an embodiment of the present application. As shown in FIG. 5, the execution unit 103 includes the operation subunit 1031 and the read-write subunit 1032. The operation subunit 1031 can perform logical operation according to the type of the instruction to be executed. The read-write subunit 1032 can perform read-write operation on the temporary storage unit 104 and / or the peripheral device 200 connected to the target node according to the logical operation result of the operation subunit 1031.

[0064] The execution unit 103 includes the operation subunit 1031. The operation subunit 1031 can perform logical operation according to the type of the instruction to be executed, for example, arithmetic operation, logical shift, arithmetic shift, and the like. In an example, the operation subunit 1031 can perform logical operation according to the source operand, the immediate number, and the like in the instruction to be executed, to obtain the destination operand. In an example, the operation subunit 1031 can be an arithmetic and logic unit (ALU) which is a combination logic circuit capable of realizing a plurality of arithmetic operations and logical operations.

[0065] The execution unit 103 further includes a read-write subunit 1032, which can read and write the temporary storage unit 104 after receiving the logical operation result of the operation subunit 1031, for example, can write the logical operation result into the temporary storage unit 104, or read out the data in the temporary storage unit 104 and write it into the peripheral device 200, the read-write subunit 1032 can also read and write the peripheral device 200, for example, write the logical operation result output by the operation subunit 1031 into the memory or register of the peripheral device 200, or read data from the peripheral device 200 according to the logical operation result of the operation subunit 1031 and write it into the temporary storage unit 104. In an example, the read-write subunit 1032 can be a load store unit (LSU), through which the temporary storage unit 104 and / or the peripheral device 200 connected to the target node can be read and written.

[0066] In an example, FIG. 6 is a schematic diagram of another chip including an operation subunit and a read-write subunit provided in an embodiment of the present application, as shown in FIG. 6, the operation subunit 1031 can include an IRQ_STATUS status register 10311, the IRQ_STATUS status register 10311 is connected to the interrupt of the peripheral device 200 of the target node, so that the interrupt state of the peripheral device 200 can be queried or modified, for example, the interrupt state of the peripheral device 200 is modified, or the interrupt state of the peripheral device 200 is written into the temporary storage unit 104, and the like.

[0067] In the embodiment of the present application, the execution unit 103 includes the operation subunit 1031 and the read-write subunit 1032, through the operation subunit 1031, logical operation can be performed according to the instruction type, through the read-write subunit 1032, the peripheral device 200 and / or the temporary storage subunit can be read and written, thereby the execution of the to-be-executed instruction can be implemented, and the related functions of the execution unit 103 can be implemented. Since the to-be-executed instruction is executed by the chip 100, the master control in the main node does not need to be reported through the link, the efficiency of processing the to-be-executed instruction can be improved, so that the efficiency of the chip 100 processing the task issued by the master control is high, and the time delay of data transmission and processing is reduced.

[0068] In a possible implementation, the control unit 102 can determine the instruction type of the to-be-executed instruction according to the value of the instruction type field in the to-be-executed instruction, and the instruction type includes at least one of an interrupt instruction, a memory access instruction, a conditional jump instruction, and a calculation instruction.

[0069] The to-be-executed instruction includes an instruction type field, when the control unit 102 parses the to-be-executed instruction, the instruction type of the to-be-executed instruction can be determined according to the instruction type field in the to-be-executed instruction, for example, an interrupt instruction, a memory access instruction, a conditional jump instruction, and a calculation instruction.

[0070] In an example, the result of the parsing of the to-be-executed instruction is 16 bytes of data, wherein the first byte and the second byte can indicate a large category of instruction types, such as: interrupt instructions, memory access instructions, conditional jump instructions, and calculation instructions, and the 14th byte, the 15th byte, and the 16th byte can indicate a specific operation corresponding to the large category of instruction types indicated by the first byte and the second byte, such as: addition and subtraction logical operations in calculation instructions, read instructions, and write instructions of interrupt instructions, and the like.

[0071] In the embodiments of the present application, the control unit 102 can determine the instruction type of the to-be-executed instruction according to the value of the instruction type field in the to-be-executed instruction, thereby realizing the parsing of the execution type of the to-be-executed instruction, and thereby the operation unit can process the to-be-executed instruction according to the instruction type.

[0072] In a possible implementation, the interrupt instruction includes an interrupt state read instruction and an interrupt state write instruction. The control unit 102 can send the first address in the to-be-executed instruction to the operation sub-unit 1031 when the to-be-executed instruction is the interrupt state read instruction, so that the operation sub-unit 1031 writes the state bit into the first address in the temporary storage unit 104, and send the second address in the to-be-executed instruction to the temporary storage unit 104 when the to-be-executed instruction is the interrupt state write instruction, so that the temporary storage unit 104 sends the source operand stored in the second address to the operation sub-unit 1031, and the operation sub-unit 1031 updates the state bit to the source operand stored in the second address in the temporary storage unit 104.

[0073] The interrupt instruction includes an interrupt state read instruction and an interrupt state write instruction. The interrupt state read instruction is to read the interrupt state of the peripheral 200, for example, to read the interrupt state of the peripheral 200 stored in the IRQ_STATUS state register 10311. The interrupt state write instruction is to update the interrupt state bit, for example, to update the interrupt state of the peripheral 200 stored in the IRQ_STATUS state register 10311.

[0074] The following is a specific example to illustrate how to execute the interrupt instruction.

[0075] In an example, FIG. 7 is a schematic diagram of an instruction to be executed of the type of interrupt instruction according to an embodiment of the present application. As shown in FIG. 7, the instruction to be executed can be a 16 byte instruction, and two instructions to be executed are shown in FIG. 7. In the first instruction to be executed, op=11 indicates that the instruction is an interrupt instruction, and funct3=000 indicates that the instruction to be executed is an interrupt status read instruction. In the second instruction to be executed, op=11 indicates that the instruction is an interrupt instruction, and funct3=001 indicates that the instruction to be executed is an interrupt status write instruction. For the first instruction to be executed, the control unit 102 parses that the instruction to be executed is an interrupt status read instruction, and rd1 in the first instruction to be executed is a first address. The control unit 102 sends the parsed first address rd1 to the operator unit 1031, and the operator unit 1031 writes the read interrupt status bit to the first address rd1 in the temporary storage unit 104, for example, writes the interrupt status of the peripheral 200 stored in the IRQ_STATUS status register to the first address rd1 in the temporary storage unit 104. For the second instruction to be executed, rs1 in the second instruction to be executed is a second address. The control unit 102 sends the parsed second address rs1 to the temporary storage unit 104, and the temporary storage unit 104 sends the source operand stored in the second address rs1 to the operator unit 1031. The operator unit 1031 can update the interrupt status bit to the source operand stored in the second address rs1, for example, modifies the IRQ_STATUS status register to the data 0 stored in the second address rs1.

[0076] It should be noted that, since the instruction to be executed of the type of interrupt instruction only needs to include the instruction type field and the first address or the second address, and the instruction to be executed is a 16 byte instruction, as shown in FIG. 7, the interrupt instruction is padded with 0 as redundant bits except the instruction type field and the first address or the second address.

[0077] In the embodiment of the present application, when the control unit 102 parses that the instruction to be executed is an interrupt instruction, if the instruction to be executed is an interrupt status read instruction, the operator unit 1031 writes the interrupt status bit to the temporary storage unit 104, and if the instruction to be executed is an interrupt status write instruction, the operator unit 1031 updates the interrupt status bit to the source operand stored in the second address in the temporary storage unit 104. Thus, the query and modification of the interrupt status of the peripheral 200 stored in the operator unit 1031 are realized. Since the interrupt status bit does not need to be reported to the master control in the query and modification, the master control in the master node does not need to be reported through the link, and thus the processing speed of the interrupt instruction is faster, the processing efficiency of the instruction to be executed is improved, and the time delay of data transmission and processing is reduced.

[0078] In a possible implementation, the memory access instruction includes a memory read instruction and a memory write instruction. When the to-be-executed instruction is the memory read instruction, the control unit 102 sends the third address in the to-be-executed instruction, the first base address, and the first offset to the operation subunit 1031, and sends a read request to the read-write subunit 1032. The operation subunit 1031 determines the first peripheral address according to the first base address and the first offset, and sends the first peripheral address and the third address to the read-write subunit 1032. The read-write subunit 1032 reads the first data from the corresponding peripheral 200 according to the read request and the first peripheral address, and writes the first data to the third address in the temporary storage unit 104.

[0079] When the to-be-executed instruction is the memory write instruction, the control unit 102 sends the fourth address in the to-be-executed instruction to the temporary storage unit 104, and sends the second base address and the second offset in the to-be-executed instruction to the operation subunit 1031, and sends a write request to the read-write subunit 1032. The temporary storage unit 104 sends the second data stored in the fourth address to the operation subunit 1031. The operation subunit 1031 determines the second peripheral address according to the second base address and the second offset, and sends the second data and the second peripheral address to the read-write subunit 1032. The read-write subunit 1032 writes the second data to the peripheral 200 corresponding to the second peripheral address according to the write request.

[0080] The memory access instruction can include a memory read instruction and a memory write instruction. Executing the memory read instruction can read the memory or the register of the peripheral 200, and write the read data to the temporary storage unit 104. Executing the memory write instruction can write the data of the temporary storage unit 104 to the memory or the register of the peripheral 200.

[0081] The following is a specific example of how to execute the memory access instruction.

[0082] Figure 8 is a schematic diagram of an instruction to be executed provided by an embodiment of the present application, as shown in Figure 8, the instruction to be executed can be a 16 byte instruction, two instructions to be executed are shown in Figure 8, op = 00 in the first instruction to be executed indicates that the instruction is a memory access instruction, funct3 = 010 indicates that the instruction to be executed is a memory access read instruction, op = 00 in the second instruction to be executed indicates that the instruction is a memory access instruction, funct3 = 110 indicates that the instruction to be executed is a memory access write instruction, for the first instruction to be executed, the control unit 102 parses that the instruction to be executed is a memory access read instruction, rs'1 in the first instruction to be executed is the first base address in the peripheral device 200, rd2 is the third address, the control unit 102 sends the parsed first base address rs'1 and the first offset (the immediate number imm in the first instruction to be executed in Figure 8) to the operator unit 1031, the operator unit 1031 determines the first peripheral device address in the peripheral device 200 based on the first base address rs' and the first offset, and sends the first peripheral device address and the third address rd2 to the read-write unit 1032, the read-write unit 1032 reads the first data from the first peripheral device address, and writes the first data into the third address rd2 in the temporary storage unit, completing the memory access read instruction.

[0083] For the second instruction to be executed, the control unit 102 parses that the instruction to be executed is a memory access write instruction, rs'2 in the second instruction to be executed is the second base address in the peripheral device 200, rs2 is the fourth address, the control unit 102 sends the parsed fourth address rs2 to the temporary storage unit 104, the temporary storage unit 104 sends the second data stored in the fourth address rs2 to the operator unit 1031, the control unit 102 sends the parsed second base address rs'2 and the second offset (the immediate number imm in the second instruction to be executed in Figure 8) to the operator unit 1031, the operator unit 1031 determines the second peripheral device address in the peripheral device 200 based on the second base address rs' and the second offset, and sends the second peripheral device address and the second data to the read-write unit 1032, the read-write unit 1032 writes the second data into the second peripheral device address in the peripheral device 200, completing the memory access write instruction.

[0084] In the embodiment of the present application, the access instruction includes an access read instruction and an access write instruction, the control unit 102 can send the base address and the offset in the to-be-executed instruction to the operation subunit 1031, so that the operation subunit 1031 can determine the peripheral device address in the peripheral device 200 according to the base address and the offset, so as to perform read and write operations on the peripheral device 200 according to the peripheral device address, thereby achieving the writing of data in the peripheral device 200 into the temporary storage unit 104 or the writing of data in the temporary storage unit 104 into the peripheral device 200. Since the read and write operations on the peripheral device 200 do not need to be reported to the central controller in the host node, it is not necessary to report to the central controller in the host node through the link, so the processing speed of the access instruction is faster, the processing efficiency of the to-be-executed instruction is improved, and the time delay of data transmission and processing is reduced.

[0085] In a possible implementation, when the to-be-executed instruction is a conditional jump instruction, the control unit 102 sends the fifth address in the conditional jump instruction to the temporary storage unit 104 and sends the immediate number in the conditional jump instruction to the operation subunit 1031. The temporary storage unit 104 sends the third data stored in the fifth address to the operation subunit 1031. The operation subunit 1031 judges whether the third data meets the condition. If the condition is met, the operation subunit 1031 determines the first target count value of the instruction counter according to the immediate number and sends the first target count value to the control unit 102. The control unit 102 reads the to-be-executed instruction corresponding to the first target count value from the temporary storage unit 104 according to the first target count value.

[0086] The to-be-executed instruction can include a conditional jump instruction. The conditional jump instruction can jump to execute other to-be-executed instructions when the condition is met.

[0087] The following is a specific example to illustrate how to execute the conditional jump instruction.

[0088] Figure 9 is a schematic diagram of an instruction to be executed of the conditional jump instruction type according to an embodiment of the present application. As shown in Figure 9, the instruction to be executed can be a 16 byte instruction. Three instructions to be executed are shown in Figure 9. op = 01 in each instruction to be executed indicates that the instruction is a jump instruction. funct3 = 010, funct3 = 110, and funct3 = 111 indicate different conditions, for example, greater than 0, less than 0, equal to 0, not equal to 0, and the like. rs3 is the fifth address. The control unit 102 sends the fifth address rs3 to the temporary storage unit 104 according to the analysis that the instruction to be executed is a conditional jump instruction. The temporary storage unit 104 sends the third data stored in the fifth address rs3 to the operator unit 1031 after receiving the fifth address rs3. The control unit 102 sends the immediate number imm to the operator unit 1031. The operator unit 1031 determines whether the third data satisfies the condition, for example, whether the third data is greater than 0 or less than 0. When the third data satisfies the condition, the operator unit 1031 determines the first target count value of the instruction counter according to the immediate number. The control unit 102 can read the instruction to be executed corresponding to the first target count value from the storage unit 101 according to the first target count value, and parse the instruction to be executed, so that the first target count value corresponding to the instruction to be executed is executed by the execution unit 103, thereby realizing conditional jump. It should be noted that when the immediate number is positive, it is a backward jump. When the immediate number is negative, it is a forward jump. It should be understood that when the jump condition is not satisfied, no jump is performed.

[0089] In the embodiment of the present application, when the instruction to be executed is a conditional jump instruction, the temporary storage unit 104 sends the third data in the fifth address to the operator unit 1031 according to the fifth address in the instruction to be executed parsed by the control unit 102. The operator unit 1031 determines whether the third data satisfies the jump condition. If yes, the first target count value is determined according to the immediate number in the conditional jump instruction, so that the control unit 102 can read the instruction to be executed corresponding to the first target count value from the storage unit 101, thereby realizing instruction jump. Since the conditional jump instruction does not need to be reported to the central control in the master node when it is executed, it does not need to be reported to the central control of the master node through the link, so the processing speed of the conditional jump instruction is faster, the processing efficiency of the instruction to be executed is improved, and the time delay of data transmission and processing is reduced.

[0090] In a possible implementation, when the to-be-executed instruction is a shift instruction, the control unit 102 sends the sixth address in the to-be-executed instruction to the temporary storage unit 104 and sends the immediate number in the to-be-executed instruction to the operation subunit 1031, the temporary storage unit 104 sends the fourth data stored in the sixth address to the operation subunit 1031, the operation subunit 1031 performs an arithmetic shift or a logical shift on the fourth data by using the immediate number to obtain fifth data, and sends the fifth data and the sixth address to the read-write subunit 1032, and the read-write subunit 1032 writes the fifth data into the sixth address of the temporary storage unit 104, or the control unit 102 sends the seventh address and the eighth address in the to-be-executed instruction to the temporary storage unit 104, the temporary storage unit 104 sends the sixth data stored in the seventh address and the shift value stored in the eighth address to the operation subunit 1031, the operation subunit 1031 performs an arithmetic shift or a logical shift on the sixth data by using the shift value to obtain seventh data, and sends the seventh data and the seventh address to the read-write subunit 1032, and the read-write subunit 1032 writes the seventh data into the seventh address of the temporary storage unit 104.

[0091] When the to-be-executed instruction is a numerical calculation instruction, the control unit 102 sends the ninth address in the to-be-executed instruction to the temporary storage unit 104 and sends the immediate number in the to-be-executed instruction to the operation subunit 1031, the temporary storage unit 104 sends the eighth data stored in the ninth address to the operation subunit 1031, the operation subunit 1031 performs an arithmetic operation on the eighth data and the immediate number to obtain ninth data, and sends the ninth data and the ninth address to the read-write subunit 1032, and the read-write subunit 1032 writes the ninth data into the ninth address of the temporary storage unit 104, or the control unit 102 sends the tenth address and the eleventh address in the to-be-executed instruction to the temporary storage unit 104, the temporary storage unit 104 sends the tenth data stored in the tenth address and the eleventh data stored in the eleventh address to the operation subunit 1031, the operation subunit 1031 performs a logical operation on the tenth data and the eleventh data to obtain twelfth data, and sends the twelfth data and the tenth address to the read-write subunit 1032, and the read-write subunit 1032 writes the twelfth data into the tenth address of the temporary storage unit 104, or the control unit 102 sends the thirteenth address in the to-be-executed instruction to the temporary storage unit 104 and sends the twelfth address in the to-be-executed instruction to the operation subunit 1031, the temporary storage unit 104 sends the thirteenth data stored in the thirteenth address to the operation subunit 1031, the operation subunit 1031 sends the thirteenth data and the twelfth address to the read-write subunit 1032, and the read-write subunit 1032 writes the thirteenth data into the twelfth address of the temporary storage unit 104.

[0092] The to-be-executed instruction can be a shift instruction and a numerical calculation instruction. When the to-be-executed instruction is the shift instruction, the execution unit 103 performs shift on the data according to the analysis result of the control unit 102, for example, arithmetic left shift, arithmetic right shift, logical left shift or logical right shift, etc. When the to-be-executed instruction is the numerical calculation instruction, the execution unit 103 performs logical calculation on the data according to the analysis result of the control unit 102, for example, addition operation, subtraction operation, etc.

[0093] The following will be specifically illustrated by examples how to execute the calculation instruction.

[0094] FIG. 10 is a schematic diagram of a to-be-executed instruction of which the instruction type is a shift instruction according to an embodiment of the present application. As shown in FIG. 10, the to-be-executed instruction can be a 16 byte instruction. Two to-be-executed instructions are shown in FIG. 10. op=10 in each to-be-executed instruction indicates that the instruction is a calculation instruction. funct3=000 in the first to-be-executed instruction indicates that the calculation instruction is a shift instruction. According to the different funct3, the shift instruction can be divided into arithmetic left shift, arithmetic right shift, logical left shift or logical right shift. rs4 is the sixth address. The control unit 102 analyzes that the to-be-executed instruction is a shift instruction. The control unit 102 sends the analyzed sixth address rs4 to the temporary storage unit 104. After receiving the sixth address rs4, the temporary storage unit 104 sends the fourth data stored in the sixth address rs4 to the operation subunit 1031. The control unit 102 sends the immediate number imm to the operation subunit 1031. The operation subunit 1031 performs arithmetic shift or logical shift on the fourth data according to the immediate number to determine the fifth data. It should be understood that the control unit 102 determines the shift mode according to funct3 in the to-be-executed instruction. The operation subunit performs shift according to the shift mode. For example, if funct3 in the to-be-executed instruction indicates arithmetic left shift, the operation subunit performs arithmetic left shift on the fourth data. If funct3 in the to-be-executed instruction indicates logical right shift, the operation subunit performs logical right shift on the fourth data. For example, the fourth data is 0011011110. If funct3 indicates logical right shift and the immediate number indicates shift by 2 bits, the fifth data is 0000110111. If funct3 indicates logical left shift and the immediate number indicates shift by 2 bits, the fifth data is 1101111000. It should be understood that the arithmetic left shift is the same as the logical shift. When performing arithmetic right shift, the sign value 0 or 1 needs to be supplemented in the empty shift. The operation subunit sends the fifth data and the sixth address rs4 to the read-write subunit 1032. The read-write subunit 1032 can store the fifth data in the sixth address rs4 of the temporary storage unit 104, thereby realizing the shift instruction.

[0095] The second instruction in FIG. 10 is also a shift instruction, op = 10 indicates that the instruction is a calculation instruction, funct3 = 010 indicates that the calculation instruction is a shift instruction, and different shift instructions according to funct3 can be divided into arithmetic left shift, arithmetic right shift, logical left shift or logical right shift, rs5 is the seventh address, rs6 is the eighth address, the control unit 102 parses that the to-be-executed instruction is a shift instruction, the control unit 102 sends the parsed seventh address rs5 and the eighth address rs6 to the temporary storage unit 104, after the temporary storage unit 104 receives the seventh address rs5 and the eighth address rs6, the temporary storage unit 104 sends the sixth data stored in the seventh address rs5 and the shift value stored in the eighth address rs6 to the operation sub-unit 1031, the operation sub-unit 1031 performs arithmetic shift or logical shift on the sixth data according to the shift value, and determines the seventh data, it should be understood that the shift method of the sixth data according to the shift value is the same as the shift method in the above scheme, the difference is only that the shift item number is confirmed by the immediate number or the shift item number is determined by the value stored in the eighth address rs6, and the specific shift method can be seen in the above example, which will not be described here. The operation sub-unit sends the seventh data and the seventh address rs5 to the read-write sub-unit 1032, and the read-write sub-unit 1032 can store the seventh data in the seventh address rs5 of the temporary storage unit 104, thereby realizing the shift instruction.

[0096] FIG. 11 is a schematic diagram of a to-be-executed instruction of an instruction type of a numerical calculation instruction according to an embodiment of the present application. As shown in FIG. 11, the first to-be-executed instruction op = 10 indicates that the instruction is a calculation instruction, funct3 = 100 indicates that the calculation instruction is a numerical calculation instruction according to an immediate number, rs7 is the ninth address, the control unit 102 parses that the to-be-executed instruction is a numerical calculation instruction, the control unit 102 sends the parsed ninth address rs7 to the temporary storage unit 104, the temporary storage unit 104 sends the eighth data stored in the ninth address rs7 to the operation sub-unit 1031, the control unit 102 sends the immediate number imm to the operation sub-unit 1031, the operation sub-unit 1031 performs arithmetic operation on the eighth data and the immediate number imm, for example: addition operation, subtraction operation, etc., to obtain the ninth data, and the operation sub-unit sends the ninth data and the ninth address rs7 to the read-write sub-unit 1032, and the read-write sub-unit 1032 can store the ninth data in the ninth address rs7, thereby realizing the numerical calculation instruction.

[0097] The op=10 in the second to-be-executed instruction in FIG. 11 indicates that the instruction is a calculation instruction, the funct3=110 indicates that the calculation instruction is a numerical calculation instruction, the rs8 is the tenth address, and the rs9 is the eleventh address. The control unit 102 parses that the to-be-executed instruction is a numerical calculation instruction based on stored values. The control unit 102 sends the parsed tenth address rs8 and the eleventh address rs9 to the temporary storage unit 104. The temporary storage unit 104 sends the tenth data stored in the tenth address rs8 and the eleventh data stored in the eleventh address rs9 to the operation subunit 1031. The operation subunit 1031 performs an arithmetic operation, for example, addition, subtraction, or the like, on the tenth data and the eleventh data to obtain the twelfth data. The operation subunit 1031 sends the twelfth data and the tenth address rs8 to the read-write subunit 1032. The read-write subunit 1032 can store the twelfth data in the tenth address rs8 of the temporary storage unit 104, thereby implementing the numerical calculation instruction.

[0098] The op=10 in the third to-be-executed instruction in FIG. 11 indicates that the instruction is a calculation instruction, the funct3=111 indicates that the calculation instruction is an assignment calculation instruction, the rs 10 The rs13 is the thirteenth address, the rd3 is the twelfth address, the control unit 102 parses that the to-be-executed instruction is an assignment calculation instruction, and the control unit 102 sends the parsed thirteenth address rs 10 To the temporary storage unit 104. The temporary storage unit 104 sends the thirteenth data stored in the thirteenth address rs 10 To the operation subunit 1031. The operation subunit 1031 sends the twelfth address rd3 and the thirteenth data to the read-write subunit 1032. The read-write subunit 1032 writes the thirteenth data into the twelfth address rd3 of the temporary storage unit 104, thereby completing the assignment calculation instruction.

[0099] It should be understood that FIG. 12 is a schematic diagram of another to-be-executed instruction provided in the embodiment of the present application. FIG. 12 shows a schematic diagram in which a plurality of calculation instructions are null instructions. When the to-be-executed instruction is the instruction shown in FIG. 12, the execution unit 103 does not execute the instruction. For example, the control unit 102 can directly discard the instruction after parsing.

[0100] In the embodiment of the present application, when the to-be-executed instruction is a calculation instruction, the operation subunit performs a logical operation according to the parsing result of the to-be-executed instruction by the control unit 102, thereby implementing the execution of the calculation instruction. Since the calculation instruction does not need to be reported to the central controller in the master node when processing the calculation instruction, the calculation instruction does not need to be reported to the central controller in the master node through the link, and thus the processing speed of the calculation instruction is faster, the processing efficiency of the to-be-executed instruction is improved, and the time delay of data transmission and processing is reduced.

[0101] In a possible implementation, the control unit 102 can read the unconditional jump instruction and the unconditional jump and link instruction from the storage unit 101.

[0102] When the unconditional jump instruction is read, the control unit 102 reads, according to the immediate number in the unconditional jump instruction, the to-be-executed instruction corresponding to the second target count value of the instruction counter indicated by the immediate number from the storage unit 101, or the control unit 102 reads, according to the first jump value stored in the fourteenth address in the unconditional jump instruction, the to-be-executed instruction corresponding to the third target count value of the instruction counter indicated by the first jump value from the storage unit 101.

[0103] When the unconditional jump and link instruction is read, the control unit 102 sends the count value of the instruction counter corresponding to the unconditional jump and link instruction to the read-write subunit 1032, and the read-write subunit 1032 writes the count value of the instruction counter to the temporary storage unit 104, the control unit 102 reads, according to the immediate number in the unconditional jump and link instruction, the to-be-executed instruction corresponding to the fourth target count value of the instruction counter indicated by the immediate number from the storage unit 101, or the control unit 102 reads, according to the second jump value stored in the fifteenth address in the unconditional jump instruction, the to-be-executed instruction corresponding to the fifth target count value of the instruction counter indicated by the second jump value from the storage unit 101.

[0104] The storage unit 101 can also store the unconditional jump instruction and the unconditional jump and link instruction. When processing the unconditional jump instruction, the control unit 102 can directly jump to the to-be-executed instruction indicated by the immediate number or the stored value in the temporary storage unit 104 according to the unconditional jump instruction, and when processing the unconditional jump and link instruction, the control unit 102 can directly jump to the to-be-executed instruction indicated by the immediate number or the stored value in the temporary storage unit 104 according to the unconditional jump and link instruction, and save the count value corresponding to the currently processed unconditional jump and link instruction to the associated storage position in the temporary storage unit 104.

[0105] The following is a specific example of how to execute the unconditional jump instruction and the unconditional jump and link instruction.

[0106] Figure 13 is a schematic diagram of unconditional jump instructions and unconditional jump and link instructions provided in an embodiment of the present application. As shown in Figure 13, op = 01 in each instruction indicates that the instruction is a jump instruction. funct3 = 001 in the first instruction indicates that the instruction is an unconditional jump instruction. The control unit 102 parses the instruction to be executed as an unconditional jump instruction. The control unit 102 reads the first target count value corresponding to the instruction to be executed from the storage unit 101 according to the first target count value indicated by the immediate number imm. funct3 = 100 in the second instruction indicates that the instruction is an unconditional jump register instruction. The control unit 102 parses the instruction to be executed as an unconditional jump register instruction. The control unit 102 reads the first jump value stored in the fourteenth address rs 11 from the storage unit 101 according to the third target count value of the instruction counter indicated by the first jump value, and reads the instruction to be executed corresponding to the third target count value from the storage unit 101. 11

[0107] funct3 = 101 in the third instruction indicates that the instruction is an unconditional jump and link instruction. The control unit 102 parses the instruction to be executed as an unconditional jump and link instruction. After the control unit 102 stores the count value of the instruction counter corresponding to the currently processed unconditional jump and link instruction to the temporary storage unit 104, the control unit 102 reads the instruction to be executed corresponding to the fourth target count value of the instruction counter from the storage unit 101 according to the fourth target count value indicated by the immediate number imm. funct3 = 111 in the fourth instruction indicates that the instruction is an unconditional jump register and link instruction. After the control unit 102 parses the instruction to be executed as an unconditional jump register and link instruction, the control unit 102 stores the count value of the instruction counter corresponding to the currently processed unconditional jump register and link instruction to the temporary storage unit 104. The control unit 102 reads the second jump value stored in the fifteenth address rs 12 from the storage unit 101 according to the fifth target count value of the instruction counter indicated by the second jump value, and reads the instruction to be executed corresponding to the fifth target count value from the storage unit 101. 12

[0108] In an embodiment of the present application, the control unit 102 can read the unconditional jump instruction and the unconditional jump and link instruction from the storage unit 101. Thus, the control unit 102 can jump to the instruction to be executed indicated by the unconditional jump instruction, and implement unconditional jump. Since the control unit 102 does not need to report to the master node in the control center when processing the unconditional jump instruction, the control unit 102 does not need to report to the master node in the control center through the link. Therefore, the processing speed of the unconditional jump instruction is faster, the processing efficiency of the instruction to be executed is improved, and the time delay of data transmission and processing is reduced.​​

[0109] It should be understood that the values of the parameters such as op and funct3 in the above embodiments are only illustrative, and the specific values of the parameters such as op and funct3 are not limited in the embodiments of the present application.

[0110] FIG. 14 is a schematic diagram of a chip including a reading subunit and an analysis subunit according to an embodiment of the present application. As shown in FIG. 14, the control unit 102 includes a reading subunit 1021 and an analysis subunit 1022. The reading subunit 1021 is configured to read an instruction to be executed from the storage unit 101 and send the instruction to be executed to the analysis subunit 1022. The analysis subunit 1022 is configured to analyze the instruction to be executed and obtain the instruction type of the instruction to be executed, and send the instruction type of the instruction to be executed to the execution unit 103.

[0111] In an example, the reading subunit 1021 can read the instruction to be executed from the storage unit 101 according to the count value of the instruction counter. It should be noted that the reading subunit 1021 and the analysis subunit 1022 can cooperate with each other to implement the operation of the control unit 102 in any of the above embodiments.

[0112] The present application also provides a computer software. The software can be used to compile the analysis subunit 1022 by writing assembly code, so as to implement the functions required to be executed by the analysis subunit 1022. The assembly code needs to be translated by one layer, and this work is implemented by a simple assembler. The specific functions of the assembler are as follows: 1, support for embedded macro, 2, support for assembly LABEL (function name), 3, support for function stack, 4, support for comments, and 5, support for assembly code to binary file.

[0113] In the embodiments of the present application, the control unit 102 includes the reading subunit 1021 and the analysis subunit 1022. Thus, the reading subunit 1021 can be used to read the instruction to be executed stored in the storage unit 101, and the analysis subunit 1022 can be used to analyze the instruction to be executed. Thus, the execution subunit can execute the instruction to be executed.

[0114] It should be noted that the chip 100 in any of the above embodiments can achieve the following advantages by using the structure shown in any of the above embodiments: 1, simple structure, small logical resource occupation, 2, strong scalability, large remaining amount of instruction set encoding space, only the instructions need to be defined, and the corresponding logic circuit can be implemented, 3, compared with the state machine circuit of the current function node, it has stronger flexibility (the analysis subunit 1022 can be compiled by software).

[0115] The embodiment of the present application further provides a networking system, comprising: a plurality of connected nodes, the plurality of nodes comprising a master node and at least one slave node, and a target node in the plurality of nodes comprising the chip 100 in any of the above embodiments, the target node being any one of the plurality of nodes.

[0116] In an example, as shown in FIG. 1 and FIG. 2, the plurality of nodes can comprise a master node and a slave node, and the target node can be the master node or the slave node, which will not be described herein.

[0117] The embodiment of the present application further provides an electronic device comprising the chip 100 in any of the above embodiments.

[0118] It should be understood that each of the embodiments in the specification is described in a progressive manner, and the same or similar parts of each embodiment can be referred to each other, and each embodiment mainly describes the difference from other embodiments. Especially, for the method embodiment, since it is basically similar to the method described in the device and system embodiment, the description is relatively simple, and the relevant parts can refer to the description of other embodiments.

[0119] It should be understood that the above describes specific embodiments of the specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in an order different from the embodiments and still achieve the desired result. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired result. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

[0120] It should be understood that the elements described herein in singular form or only one shown in the drawings do not represent the number of the elements limited to one. In addition, the modules or elements described or shown herein as separate can be combined into a single module or element, and the modules or elements described or shown herein as single can be split into multiple modules or elements.

[0121] It should also be understood that the terms and expressions used herein are only used for description, and one or more embodiments of the specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean that any illustration and description (or part thereof) is excluded, and it should be recognized that various modifications can exist and should be included in the scope of the claims. Other modifications, changes and replacements can also exist. Accordingly, the claims should be considered to cover all these equivalents.

Claims

1. A chip applied to a target node included in a networking system, characterized by, The networking system comprises a plurality of connected nodes including a master node and at least one slave node, the target node being any one of the plurality of nodes, and the chip comprises a storage unit, a control unit and an execution unit; The storage unit is configured to store a to-be-executed instruction issued by the master node; The control unit is configured to read the to-be-executed instruction from the storage unit, analyze the to-be-executed instruction, obtain an instruction type of the to-be-executed instruction, and send the instruction type of the to-be-executed instruction to the execution unit; The execution unit is configured to execute the to-be-executed instruction according to the instruction type of the to-be-executed instruction.

2. The chip of claim 1, wherein The control unit is configured to read the to-be-executed instruction from the storage unit according to a count value of an instruction counter, the instruction counter increasing the count value by a period, and the count value increment of the instruction counter in each period being positively correlated with a length of the to-be-executed instruction.

3. The chip of claim 2, wherein, The chip further comprises a temporary storage unit; The temporary storage unit is configured to store a source operand and a destination operand in a process in which the execution unit executes the to-be-executed instruction.

4. The chip of claim 3, wherein The temporary storage unit comprises a plurality of registers, or the storage unit comprises the temporary storage unit.

5. The chip of claim 3, wherein, The execution unit comprises an operation subunit and a read-write subunit; The operation subunit is configured to perform a logical operation according to the instruction type of the to-be-executed instruction; The read-write subunit is configured to read and write the temporary storage unit and / or a peripheral device connected to the target node according to a logical operation result of the operation subunit after receiving the logical operation result.

6. The chip of claim 5, wherein The control unit is configured to determine the instruction type of the to-be-executed instruction according to a value of an instruction type field in the to-be-executed instruction, the instruction type comprising at least one of an interrupt instruction, a memory access instruction, a conditional jump instruction and a calculation instruction.

7. The chip of claim 6, wherein The interrupt instruction comprises an interrupt state read instruction and an interrupt state write instruction; The control unit is configured to send a first address in the to-be-executed instruction to the operation subunit to make the operation subunit write a state bit to the first address in the temporary storage unit when the to-be-executed instruction is the interrupt state read instruction, and send a second address in the to-be-executed instruction to the temporary storage unit to make the temporary storage unit send a source operand stored in the second address to the operation subunit to make the operation subunit update the state bit to the source operand stored in the second address in the temporary storage unit when the to-be-executed instruction is the interrupt state write instruction.

8. The chip of claim 6, wherein, The memory access instruction comprises a memory access read instruction and a memory access write instruction; When the to-be-executed instruction is the memory read instruction, the control unit sends a third address in the to-be-executed instruction, a first base address and a first offset to the operation subunit, and sends a read request to the read-write subunit, the operation subunit determines a first peripheral address according to the first base address and the first offset, and sends the first peripheral address and the third address to the read-write subunit, the read-write subunit reads first data from a corresponding peripheral according to the read request and the first peripheral address, and writes the first data into the third address in the temporary storage unit; When the to-be-executed instruction is the memory write instruction, the control unit sends a fourth address in the to-be-executed instruction to the temporary storage unit, and sends a second base address and a second offset in the to-be-executed instruction to the operation subunit, and sends a write request to the read-write subunit, the temporary storage unit sends second data stored in the fourth address to the operation subunit, the operation subunit determines a second peripheral address according to the second base address and the second offset, and sends the second data and the second peripheral address to the read-write subunit, and the read-write subunit writes the second data into a peripheral corresponding to the second peripheral address according to the write request.

9. The chip of claim 6, wherein When the to-be-executed instruction is the conditional jump instruction, the control unit sends a fifth address in the conditional jump instruction to the temporary storage unit, and sends an immediate number in the conditional jump instruction to the operation subunit, the temporary storage unit sends third data stored in the fifth address to the operation subunit, the operation subunit determines whether the third data satisfies a condition, and if the third data satisfies the condition, determines a first target count value of the instruction counter according to the immediate number, and sends the first target count value to the control unit, and the control unit reads a to-be-executed instruction corresponding to the first target count value from the temporary storage unit according to the first target count value.

10. The chip of claim 6, wherein, The calculation instruction includes a shift instruction and a numerical calculation instruction. When the to-be-executed instruction is the shift instruction, the control unit sends a sixth address in the to-be-executed instruction to the temporary storage unit and sends an immediate number in the to-be-executed instruction to the operation subunit, the temporary storage unit sends fourth data stored in the sixth address to the operation subunit, the operation subunit performs arithmetic shift or logical shift on the fourth data by the immediate number to obtain fifth data, and sends the fifth data and the sixth address to the read-write subunit, the read-write subunit writes the fifth data into the sixth address of the temporary storage unit, or the control unit sends a seventh address and an eighth address in the to-be-executed instruction to the temporary storage unit, the temporary storage unit sends sixth data stored in the seventh address and a shift value stored in the eighth address to the operation subunit, the operation subunit performs arithmetic shift or logical shift on the sixth data by the shift value to obtain seventh data, and sends the seventh data and the seventh address to the read-write subunit, the read-write subunit writes the seventh data into the seventh address of the temporary storage unit; When the to-be-executed instruction is the value calculation instruction, the control unit sends a ninth address in the to-be-executed instruction to the temporary storage unit and sends an immediate number in the to-be-executed instruction to the operation subunit, the temporary storage unit sends eighth data stored in the ninth address to the operation subunit, the operation subunit performs arithmetic operation on the eighth data and the immediate number to obtain ninth data, and sends the ninth data and the ninth address to the read-write subunit, the read-write subunit writes the ninth data into the ninth address of the temporary storage unit, or the control unit sends a tenth address and an eleventh address in the to-be-executed instruction to the temporary storage unit, the temporary storage unit sends tenth data stored in the tenth address and eleventh data stored in the eleventh address to the operation subunit, the operation subunit performs logical operation on the tenth data and the eleventh data to obtain twelfth data, and sends the twelfth data and the tenth address to the read-write subunit, the read-write subunit writes the twelfth data into the tenth address of the temporary storage unit, or the control unit sends a thirteenth address in the to-be-executed instruction to the temporary storage unit and sends a twelfth address in the to-be-executed instruction to the operation subunit, the temporary storage unit sends thirteenth data stored in the thirteenth address to the operation subunit, the operation subunit sends the thirteenth data and the twelfth address to the read-write subunit, and the read-write subunit writes the thirteenth data into the twelfth address of the temporary storage unit.

11. The chip of claim 3, wherein The control unit is configured to read an unconditional jump instruction and an unconditional jump and link instruction from the storage unit. When the unconditional jump instruction is read, the control unit reads, according to an immediate number in the unconditional jump instruction, a to-be-executed instruction corresponding to a second target count value of the instruction counter indicated by the immediate number from the storage unit, or reads, according to a first jump value stored in a fourteenth address in the unconditional jump instruction, a to-be-executed instruction corresponding to a third target count value of the instruction counter indicated by the first jump value from the storage unit. When the unconditional jump and link instruction is read, the control unit sends a count value of an instruction counter corresponding to the unconditional jump and link instruction to a read-write subunit, the read-write subunit writes the count value of the instruction counter into a temporary storage unit, the control unit reads, according to an immediate number in the unconditional jump and link instruction, a to-be-executed instruction corresponding to a fourth target count value of the instruction counter indicated by the immediate number from the storage unit, or reads, according to a second jump value stored in a fifteenth address in the unconditional jump instruction, a to-be-executed instruction corresponding to a fifth target count value of the instruction counter indicated by the second jump value from the storage unit.

12. The chip according to any one of claims 1 to 11, characterized in that The control unit comprises a reading subunit and an analysis subunit. The reading subunit is configured to read the to-be-executed instruction from the storage unit and send the to-be-executed instruction to the analysis subunit. The analysis subunit is configured to analyze the to-be-executed instruction, obtain an instruction type of the to-be-executed instruction, and send the instruction type of the to-be-executed instruction to the execution unit.

13. A networking system, comprising: The chip comprises: A plurality of connected nodes, the plurality of nodes comprising a master node and at least one slave node, and a target node in the plurality of nodes comprising the chip of any one of claims 1-12, the target node being any one of the plurality of nodes.

14. An electronic device, comprising: The chip comprises: The chip of any one of claims 1-12.

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