Micro-display panel and manufacturing method therefor, and micro-display device

Abstract

A micro-display panel and a manufacturing method therefor, and a micro-display device. The micro-display panel comprises: a silicon-based backplane, which comprises a plurality of driving circuits; a reflection layer, which is located on one side of the silicon-based backplane; a light-transmitting bonding layer, which is located on the side of the reflection layer away from the silicon-based backplane; and a light-emitting device layer, which is located on the side of the light-transmitting bonding layer away from the silicon-based backplane, wherein the light-emitting device layer comprises a plurality of micro light-emitting devices, which are electrically connected to the driving circuits.

Description

Micro display panel, manufacturing method thereof and micro display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a micro display panel, a manufacturing method thereof and a micro display device. BACKGROUND

[0002] Micro display based on light emitting diode is one of the hotspots in the field of virtual reality (VR) and augmented reality (AR) research.

[0003] The micro display panel includes a silicon-based backplane and a display array, and the silicon-based backplane and the display array are usually electrically connected by a bonding metal. The bonding metal not only electrically connects the silicon-based backplane and the display array, but also reflects light emitted by the display array to improve the light efficiency of the micro display panel.

[0004] Please refer to FIG. 1 for a curve diagram of the film thickness and reflectivity of the bonding metal. As shown in FIG. 1, when the film thickness of the bonding metal is from 0 nm to 60 nm, the average reflectivity is about 50%, which results in a relatively low light efficiency of the micro display panel.

[0005] SUMMARY

[0006] The embodiments of the present application provide a micro display panel, a manufacturing method thereof and a micro display device to solve the problem of low light efficiency of the micro display panel in the prior art.

[0007] In a first aspect, to solve the above technical problem, the embodiments of the present application provide a micro display panel, comprising:

[0008] A silicon-based backplane, comprising a plurality of driving circuits;

[0009] A reflective layer located on one side of the silicon-based backplane;

[0010] A light-transmitting bonding layer located on the side of the reflective layer away from the silicon-based backplane;

[0011] A light emitting device layer located on the side of the light-transmitting bonding layer away from the silicon-based backplane; the light emitting device layer comprises a plurality of micro light emitting devices, and the micro light emitting devices are electrically connected with the driving circuits.

[0012] In a possible implementation, the reflective layer comprises a plurality of first insulating layers and a plurality of first conductive structures;

[0013] The plurality of first insulating layers have a plurality of first through holes penetrating through the thickness direction, and the first conductive structures are filled in the first through holes; the driving circuits are electrically connected with the corresponding micro light emitting devices through at least one first conductive structure.

[0014] In a possible implementation, the first through hole is located in the orthographic projection of the silicon-based backboard within the orthographic projection of the corresponding micro light emitting device on the silicon-based backboard.

[0015] In a possible implementation, in the direction in which the silicon-based backboard is directed to the light-transmitting bonding layer, the multilayer first insulating layer is arranged alternately with a first insulating layer having a first refractive index and a first insulating layer having a second refractive index; the first refractive index is greater than the second refractive index; and the thickness of each first insulating layer is 1 / 4 wavelength.

[0016] In a possible implementation, the silicon-based backboard further comprises:

[0017] A plurality of first connection holes are located on the side of the silicon-based backboard close to the reflective layer, the first connection hole overlaps with the corresponding first through hole; and the driving circuit is electrically connected to the first conductive structure through the first connection hole.

[0018] In a possible implementation, the light-transmitting bonding layer is a transparent conductive layer.

[0019] The transparent conductive layer comprises a plurality of transparent conductive blocks corresponding to the plurality of micro light emitting devices one by one, and the transparent conductive block coincides with the corresponding micro light emitting device.

[0020] In a possible implementation, the light-transmitting bonding layer comprises a second insulating layer and a plurality of second conductive structures; and the second insulating layer is light-transmitting.

[0021] The second insulating layer comprises a plurality of second through holes penetrating in the thickness direction, and the second conductive structure is filled in the second through hole.

[0022] The driving circuit is electrically connected to the corresponding micro light emitting device through the first conductive structure and the second conductive structure.

[0023] In a possible implementation, the second insulating layer comprises:

[0024] A first sub-insulating layer is located on the side of the light emitting device layer close to the silicon-based backboard; the first sub-insulating layer has a first sub-through hole penetrating in the thickness direction.

[0025] A second sub-insulating layer is located between the first sub-insulating layer and the reflective layer; the second sub-insulating layer has a second sub-through hole penetrating in the thickness direction, and the second through hole comprises at least the first sub-through hole and the second sub-through hole.

[0026] The second conductive structure includes a first sub-conductive structure and a second sub-conductive structure, the first sub-conductive structure is filled in the first sub-via hole, and the second sub-conductive structure is filled in the second sub-via hole.

[0027] In a possible implementation, the first sub-insulating layer includes:

[0028] A plurality of sub-insulating blocks correspond to the plurality of micro light emitting devices one by one, and the sub-insulating blocks coincide with the corresponding micro light emitting devices; two adjacent sub-insulating blocks and the second sub-insulating block form a groove.

[0029] In a possible implementation, the light emitting device layer includes a P-type gallium nitride layer, a multi-quantum well layer, and an N-type gallium nitride layer; the P-type gallium nitride layer is located on a side of the reflective layer away from the silicon-based backboard, the multi-quantum well layer is located between the P-type gallium nitride layer and the N-type gallium nitride layer;

[0030] The silicon-based backboard further includes a plurality of second connection holes located on a side of the silicon-based backboard close to the reflective layer, and the plurality of second connection holes correspond to the plurality of micro light emitting devices one by one;

[0031] The pattern of the P-type gallium nitride layer and the pattern of the multi-quantum well layer in the same micro light emitting device correspond to the pattern of the N-type gallium nitride layer, and the pattern of the N-type gallium nitride layer overlaps; wherein the pattern area of the N-type gallium nitride layer is greater than the pattern area of the multi-quantum well layer;

[0032] The micro display panel further includes a plurality of third conductive structures corresponding to the plurality of micro light emitting devices one by one, and the second connection hole and the third conductive structure corresponding to the same micro light emitting device overlap and are electrically connected;

[0033] The third conductive structure is located in the projection of the P-type gallium nitride layer and the multi-quantum well layer on the silicon-based backboard.

[0034] The second conductive structure is located in the projection of the P-type gallium nitride layer and the multi-quantum well layer on the silicon-based backboard.

[0035] In a possible implementation, the silicon-based backboard further includes a second connection hole located on a side of the silicon-based backboard close to the reflective layer and not overlapping with the plurality of micro light emitting devices.

[0036] The micro display panel further includes:

[0037] A second transparent conductive layer is located on a side of the light emitting device layer away from the silicon-based backboard.

[0038] a grid-shaped common electrode is located on the side of the second transparent conductive layer away from the silicon-based backboard, the common electrode does not overlap the light-emitting device layer and overlaps the second connecting hole;

[0039] In the thickness direction, the edge of the common electrode extends to the second connecting hole of the silicon-based backboard.

[0040] In a possible implementation, the light-emitting device layer includes a P-type gallium nitride layer, a multiple quantum well layer, and an N-type gallium nitride layer; the P-type gallium nitride layer is located on the side of the reflective layer away from the silicon-based backboard, and the multiple quantum well layer is located between the P-type gallium nitride layer and the N-type gallium nitride layer;

[0041] The silicon-based backboard further includes a second connecting hole located on the side of the silicon-based backboard close to the reflective layer;

[0042] The micro display panel further includes:

[0043] a grid-shaped common electrode is located between the N-type gallium nitride layer and the multiple quantum well layer, the P-type gallium nitride layer and the multiple quantum well layer are patterned, and the N-type gallium nitride layer is not patterned; the common electrode overlaps the second connecting hole and does not overlap the P-type gallium nitride layer and the multiple quantum well layer;

[0044] In the thickness direction, the edge of the common electrode extends to the second connecting hole of the silicon-based backboard.

[0045] In a possible implementation, in the thickness direction, one part of the common electrode is inlaid in the N-type gallium nitride layer, and the other part is inlaid in the gap between the multiple quantum well layers corresponding to the adjacent two micro light-emitting devices.

[0046] In a possible implementation, there is a gap between the adjacent two micro light-emitting devices;

[0047] The micro display panel further includes:

[0048] a filling layer filled in the gap and around the plurality of micro light-emitting devices, the filling layer being light-absorbing or light-reflecting.

[0049] In a second aspect, an embodiment of the present application provides a manufacturing method of a micro display panel, including:

[0050] forming a first wafer substrate, the first wafer substrate including a substrate base plate and a light-emitting device layer or a light-emitting device epitaxial layer and a first sub-bonding layer sequentially stacked on one side of the substrate base plate; the light-emitting device layer includes a plurality of micro light-emitting devices, and the light-emitting device layer is the light-emitting device epitaxial layer after patterning;

[0051] forming a second wafer substrate, the second wafer substrate comprising a silicon-based backplane, a reflective layer and a second sub-bonding layer stacked together; the silicon-based backplane comprising a plurality of driving circuits corresponding to the plurality of micro light emitting devices one by one, the driving circuits being electrically connected to the micro light emitting devices; wherein the first sub-bonding layer and the second sub-bonding layer are transparent to light;

[0052] bonding the first wafer substrate and the second wafer substrate through the first sub-bonding layer and the second sub-bonding layer to obtain a transparent bonding layer; removing the substrate wafer; wherein the light emitting device epitaxial layer is patterned before bonding or after removing the substrate wafer.

[0053] In a possible implementation, a first wafer substrate is formed, comprising:

[0054] providing a substrate wafer;

[0055] forming the light emitting device epitaxial layer on one side of the substrate wafer;

[0056] forming the first sub-bonding layer on the side of the light emitting device epitaxial layer away from the substrate wafer.

[0057] In a possible implementation, the first sub-bonding layer is formed on the side of the light emitting device epitaxial layer away from the substrate wafer, comprising:

[0058] growing a first sub-transparent conductive layer on the side of the light emitting device epitaxial layer away from the substrate wafer;

[0059] taking the first sub-transparent conductive layer as the first sub-bonding layer.

[0060] In a possible implementation, after growing the first sub-transparent conductive layer, further comprising:

[0061] patterning the light emitting device epitaxial layer and the first sub-transparent conductive layer to obtain a plurality of first sub-transparent conductive blocks and the plurality of micro light emitting devices;

[0062] taking the plurality of first sub-transparent conductive blocks as the first sub-bonding layer.

[0063] In a possible implementation, the first sub-bonding layer is formed on the side of the light emitting device epitaxial layer away from the substrate wafer, comprising:

[0064] growing a first sub-insulating layer on the side of the light emitting device epitaxial layer away from the substrate wafer;

[0065] forming a plurality of first sub-vias penetrating through the thickness direction in the first sub-insulating layer;

[0066] filling conductive material in the first sub-via hole to obtain a first sub-conductive structure;

[0067] The first sub-insulating layer with the first sub-conductive structure is used as the first sub-bonding layer.

[0068] A possible implementation, forming a second wafer substrate, comprises:

[0069] providing the silicon-based backplane;

[0070] forming the reflective layer on a side of the silicon-based backplane close to the first wafer substrate;

[0071] forming a plurality of first via holes penetrating through the thickness direction on the reflective layer; and filling conductive material in the first via holes to obtain a first conductive structure; the first via holes are located within the orthographic projection of the corresponding micro light emitting device on the silicon-based backplane;

[0072] forming the second sub-bonding layer on a side of the reflective layer away from the silicon-based backplane.

[0073] A possible implementation, forming the second sub-bonding layer on a side of the reflective layer away from the silicon-based backplane, comprises:

[0074] growing a second sub-transparent conductive layer on a side of the reflective layer away from the silicon-based backplane;

[0075] using the second sub-transparent conductive layer as the second sub-bonding layer.

[0076] A possible implementation, after growing the second sub-transparent conductive layer, further comprises:

[0077] patterning the second sub-transparent conductive layer to obtain a plurality of second sub-transparent conductive blocks corresponding one-to-one to the plurality of micro light emitting devices;

[0078] using the plurality of second sub-transparent conductive blocks as the second sub-bonding layer.

[0079] A possible implementation, forming the second sub-bonding layer on a side of the reflective layer away from the silicon-based backplane, comprises:

[0080] growing a second sub-insulating layer on a side of the reflective layer away from the silicon-based backplane;

[0081] forming a plurality of second sub-via holes penetrating through the thickness direction on the second sub-insulating layer;

[0082] filling conductive material in the second sub-via hole to obtain a second sub-conductive structure;

[0083] The second sub-insulating layer with the second sub-conductive structure is used as the second sub-bonding layer.

[0084] In a third aspect, an embodiment of the present application provides a micro display device, comprising the micro display panel as shown in the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0085] FIG. 1 is a structural schematic diagram of a micro display panel in the related art;

[0086] FIG. 2 is a flow schematic diagram of forming a micro display panel in the related art;

[0087] FIG. 3 is a diagram of the relationship between the film thickness and reflectivity of a metal bonding layer;

[0088] FIG. 4 is a structural schematic diagram of a micro display panel provided by an embodiment of the present application;

[0089] FIG. 5 is a structural schematic diagram of another micro display panel provided by an embodiment of the present application;

[0090] FIG. 6 is a structural schematic diagram of another micro display panel provided by an embodiment of the present application;

[0091] FIG. 7 is a structural schematic diagram of another micro display panel provided by an embodiment of the present application;

[0092] FIG. 8 is a structural schematic diagram of another micro display panel provided by an embodiment of the present application;

[0093] FIG. 9 and FIG. 10 are structural schematic diagrams of another micro display panel provided by an embodiment of the present application;

[0094] FIG. 11 is a structural schematic diagram of another micro display panel provided by an embodiment of the present application;

[0095] FIG. 12 is a structural schematic diagram of another micro display panel provided by an embodiment of the present application;

[0096] FIG. 13 is a structural schematic diagram of another micro display panel provided by an embodiment of the present application;

[0097] FIG. 14 is a structural schematic diagram of another micro display panel provided by an embodiment of the present application;

[0098] FIG. 15 is a structural schematic diagram of another micro display panel provided by an embodiment of the present application;

[0099] FIG. 16 is a flow diagram of a manufacturing method of a micro display panel provided by an embodiment of the present application;

[0100] FIG. 17 is a schematic diagram of forming a micro display panel provided by an embodiment of the present application;

[0101] FIG. 18 is a schematic view of forming a micro display panel according to an embodiment of the present application;

[0102] FIG. 19 is a schematic view of forming a first wafer substrate according to an embodiment of the present application;

[0103] FIG. 20 is a schematic view of forming a first sub-bonding layer according to an embodiment of the present application;

[0104] FIG. 21 is a schematic view of forming a second wafer substrate according to an embodiment of the present application;

[0105] FIG. 22 is a schematic view of forming a second sub-bonding layer according to an embodiment of the present application.

[0106] FIG. 18 is a schematic view of forming a micro display panel according to an embodiment of the present application; DETAILED DESCRIPTION

[0107] The present application provides a micro display panel, a manufacturing method thereof and a micro display device, which solve the problem of low light efficiency of the micro display panel in the prior art.

[0108] It should be understood that the specific structures and functional details disclosed in the embodiments of the present application are merely representative, and are for the purpose of describing the exemplary embodiments of the present application. However, the present application can be embodied in many alternative forms, and should not be interpreted as being limited to the embodiments set forth herein.

[0109] In the description of the present application, it needs to be understood that the terms "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified and limited, the term "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0110] In the description of the present application, it needs to be understood that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0111] The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular form "a", "an" used herein is also intended to include the plural. It should also be understood that the terms "include" and / or "contain" herein specify the existence of the stated features, integers, steps, operations, units and / or components, and do not exclude the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0112] The term "and / or" in the embodiments of the present application is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, the character " / " herein generally represents that the front and rear associated objects have an "or" relationship.

[0113] In order to make the above objectives, characteristics and advantages of the present application more apparent, comprehensible and easier to be understood, the present application will be further described below in conjunction with the accompanying drawings and embodiments. However, the example embodiments can be implemented in various forms, and should not be understood as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so as to make the present application more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The same reference signs in the drawings represent the same or similar structures, and thus repeated description thereof will be omitted. The words expressing position and direction described in the present application are described by taking the drawings as an example, but changes can also be made as needed, and the changes made are all included in the protection scope of the present application. The drawings of the present application are only used to illustrate the relative positional relationship and do not represent the true proportion.

[0114] It should be noted that specific details are set forth in the following description in order to provide a thorough understanding of the present application. However, the present application can be practiced in a variety of ways beyond those described herein, and it should be understood that it is not intended to limit the present application to the specific embodiments described herein. Therefore, the present application is not limited to the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment for implementing the present application, and is intended to illustrate the general principles of the present application, but is not intended to limit the scope of the present application. The protection scope of the present application is defined by the appended claims.

[0115] Please refer to FIG. 1 for a structural schematic diagram of a micro display panel in the related art.

[0116] The micro display panel comprises:

[0117] A silicon-based backplane 1' comprising a plurality of driving circuits (not shown);

[0118] A light-emitting diode (LED) layer 2' located on one side of the silicon-based backplane 1'; the LED layer 2' comprises a plurality of LEDs 21', each LED 21' being electrically connected with a driving circuit, and the driving circuit being used to drive the electrically connected LED 21' to emit light;

[0119] A metal bonding layer 3' located between the silicon-based backplane 1' and the LED layer 2', and the metal bonding layer 3' being used to bond the silicon-based backplane 1' and the LED layer 2'; the metal bonding layer 3' comprises metal blocks with the same pattern as the LEDs 21', and is also used to electrically connect the driving circuit and the corresponding LED 21', and reflect the light emitted by the LED 21'.

[0120] The LED layer 2' comprises:

[0121] An indium tin oxide (ITO) layer 22' located on the side of the metal bonding layer 3' away from the silicon-based backplane 1'; the indium tin oxide (ITO) layer 22' can be used as an anode of the LED 21'.

[0122] a P-type gallium nitride (P-GaN) layer 23' on a side of the ITO layer 22' away from the silicon-based backplane 1';

[0123] a multiple quantum well (MQW) layer 24' on a side of the P-GaN layer 23' away from the silicon-based backplane 1';

[0124] an N-type gallium nitride (N-GaN) layer 25' on a side of the MQW layer 24' away from the silicon-based backplane 1'.

[0125] Please refer to FIG. 2 for a flowchart of forming a micro display panel in the related art.

[0126] S10: providing a first wafer substrate 01' and a second wafer substrate 02'; wherein the first wafer substrate 01' comprises a substrate 011' and a buffer layer 012', an LED epitaxial layer 013', and a first sub-metal bonding layer 014' on a side of the substrate 011'; the second wafer substrate 02' comprises a silicon-based backplane 1' and a second sub-metal bonding layer 021' on a side of the silicon-based backplane 1'; the LED epitaxial layer 013' is consistent with the film layer structure of the LED layer 2' described above;

[0127] S11: bonding the first wafer substrate 01' and the second wafer substrate 02' through the first sub-metal bonding layer 014' and the second sub-metal bonding layer 021', and removing the substrate 011' and the buffer layer 012'; wherein the first sub-metal bonding layer 014' and the second sub-metal bonding layer 021' form a metal bonding layer 3' after bonding;

[0128] S12: patterning the LED epitaxial layer 013' and the metal bonding layer 3' to obtain the LED layer 2'; forming a common cathode 4' on a side of the LED layer 2' away from the silicon-based backplane 1'.

[0129] As can be seen from the structure of the micro display panel, the light emitted downward by the LED 21' is reflected by the metal bonding layer 3' and emitted upward, and therefore the reflectivity of the metal bonding layer is a key factor determining the light efficiency of the micro display panel. However, in addition to the function of reflection, the metal bonding layer 3' also needs to consider multiple functions such as an adhesive layer, a protective layer, a bonding layer, etc., and therefore the selection range is limited. In order to allow the metal bonding layer 3' to consider the above-mentioned multiple functions, the currently available materials for the metal bonding layer 3' are limited, and most of them are chromium (Cr) / silver (Pt) / gold (Au), etc. Please refer to FIG. 3 for a diagram of the film layer thickness of the metal bonding layer and the reflectivity. As can be seen from FIG. 3, when the thickness of the metal bonding layer is from 0 nm to 60 nm, the average reflectivity is only about 50%, which leads to a low light efficiency of the micro display panel.

[0130] To solve the above problems, the embodiment of the present application provides a micro display panel, a manufacturing method thereof and a display device, which are specifically described below with reference to the drawings.

[0131] Please refer to Fig. 4 for a structural schematic diagram of a micro display panel provided by the embodiment of the present application, which comprises:

[0132] The silicon-based backboard 1 comprises a plurality of driving circuits (not shown); the silicon-based backboard 1 is integrated with the driving circuits for driving LEDs on a semiconductor substrate by using a CMOS process, and the driving circuits in the silicon-based backboard 1 are extremely high in precision and electrical performance and highly mature in technology, but the cost of the backboard per unit area is also extremely high, and it is extremely difficult to be large-sized. Therefore, the silicon-based backboard 1 can meet the requirements of micro-sized display such as AR.

[0133] The reflective layer 2 is located on one side of the silicon-based backboard 1; wherein the reflectivity of the reflective layer 2 is greater than that of metal, and the metal here generally refers to the metal material used in the metal bonding layer 3' in Fig. 1;

[0134] The light-transmitting bonding layer 3 is located on the side of the reflective layer 2 away from the silicon-based backboard 1; the light-transmitting bonding layer 3 is light-transmitting;

[0135] The light-emitting device layer 4 is located on the side of the light-transmitting bonding layer 3 away from the silicon-based backboard 1; the light-emitting device layer 4 comprises a plurality of micro light-emitting devices 4a, and the micro light-emitting devices 4a are electrically connected with the driving circuits. The micro light-emitting devices 4a can be silicon-based diodes, such as silicon-based organic diodes, silicon-based inorganic diodes, etc. When the micro light-emitting devices 4a are silicon-based inorganic diodes, the light-emitting device layer 4 comprises a P-type gallium nitride layer 41, a multi-quantum well layer 42 and an N-type gallium nitride layer 43.

[0136] By specially providing the reflective layer 2 in the micro display panel to reflect the light emitted by the micro light-emitting devices 4a, the reflective performance required by the reflective layer 2 can be considered more, and the bonding performance does not need to be considered as in the metal bonding layer 3' in Fig. 1, so that the light efficiency of the micro display panel can be improved.

[0137] The reflective layer 2 can be a distributed Bragg reflector, and the reflectivity of the distributed Bragg reflector can generally reach more than 99%, so by providing the reflective layer 2 between the silicon-based backboard 1 and the light-transmitting bonding layer 3 and making the light-transmitting bonding layer 3 light-transmitting, the light emitted by the light-emitting devices 4a towards the silicon-based backboard 1 can be almost reflected to the side away from the silicon-based backboard 1 by the reflective layer 2, so that the light efficiency of the light-emitting devices 4a can be improved, and the light efficiency of the micro display panel can be further improved.

[0138] Please refer to Fig. 5 for a structural schematic diagram of another micro display panel provided by the embodiment of the present application. The reflective layer 2 comprises a plurality of first insulating layers 21 and a plurality of first conductive structures 22;

[0139] The multi-layer first insulating layer 21 has a plurality of first through holes H1 penetrating through the thickness direction, and the first conductive structure 22 is filled in the first through hole H1, and the driving circuit (not shown) is electrically connected to the corresponding micro light emitting device 4a through at least one first conductive structure 22.

[0140] The material of the first insulating layer 21 and the second insulating layer 32 can be zirconium dioxide (ZrO2), titanium dioxide (TiO2), silicon dioxide (SiO2), etc. The material of the first conductive structure 22 can be a metal with low resistivity (resistivity less than or equal to a preset value), such as copper (Cu) and gold (Au).

[0141] One driving circuit can correspond to one first conductive structure 22, or correspond to a plurality of first conductive structures 22; when the driving circuit corresponds to one first conductive structure 22, the driving circuit is electrically connected to the corresponding micro light emitting device 4a through the first conductive structure 22; when the driving circuit corresponds to a plurality of first conductive structures 22, the driving circuit is electrically connected to the corresponding micro light emitting device 4a through the plurality of first conductive structures 22.

[0142] By providing a plurality of first through holes H1 penetrating through the thickness direction on the multi-layer first insulating layer 21, and filling the first conductive structure 22 in the first through hole H1, it is convenient to establish the electrical connection relationship between the driving circuit and the corresponding light emitting device 4a through the first conductive structure 22.

[0143] Please continue to refer to FIG. 5, the orthographic projection of the first through hole H1 on the silicon-based backboard 1 is located within the orthographic projection of the corresponding micro light emitting device 4a on the silicon-based backboard 1.

[0144] By setting the orthographic projection of the first through hole H1 on the silicon-based backboard 1 within the orthographic projection of the corresponding micro light emitting device 4a on the silicon-based backboard 1, the electrical connection path between the driving circuit and the corresponding light emitting device 4a can be made shortest, thereby reducing power consumption.

[0145] Please continue to refer to FIG. 5, in the direction of the silicon-based backboard 1 pointing to the light-transmitting bonding layer 3, the multi-layer first insulating layer 21 is arranged alternately with the first insulating layer 21 having a first refractive index a and the first insulating layer 21 having a second refractive index b; wherein the first refractive index a is greater than the second refractive index b; the thickness d of each layer of the first insulating layer 21 is 1 / 4 wavelength.

[0146] For example, in the direction of the silicon-based backboard 1 pointing to the light-transmitting bonding layer 3, the multi-layer TiO2 with a first refractive index of 2.55 and the multi-layer SiO2 with a second refractive index of 1.57 are arranged alternately to form a reflection layer 2 with a distributed Bragg structure.

[0147] The first insulating layer 21 with the first refractive index a and the first insulating layer 21 with the second refractive index b are one repeating period, the reflective layer 2 can be provided with 10-14 periods, the total thickness of the reflective layer 2 is in the range of 8-14 um, so that the reflectivity of the reflective layer 2 can reach 99%.

[0148] It should be noted that the thickness of the first insulating layer 21 is drawn thicker in Figure 5 for easy observation, but this does not represent the relationship between the thickness of the first insulating layer 21 and the thickness of other film layers in the figure.

[0149] Please continue to refer to Figure 5, the silicon-based backboard 1 further comprises:

[0150] A plurality of first connecting holes H' are located on the side of the silicon-based backboard 1 close to the reflective layer 2, the first connecting hole H' overlaps with the corresponding first through hole H1; the driving circuit (not shown) is electrically connected to the first conductive structure 22 through the first connecting hole H'.

[0151] The first connecting hole H' can be a metal connecting hole such as a tungsten hole, or other conductive connecting hole, which is not limited here.

[0152] The light-transmitting bonding layer 3 is a transparent conductive layer; the transparent conductive layer can be an ITO layer, an indium zinc oxide IZO layer, etc., which is not limited in detail.

[0153] The transparent conductive layer includes a plurality of transparent conductive blocks 31 corresponding to the plurality of micro light emitting devices 4a, and the transparent conductive block 31 overlaps with the corresponding micro light emitting device 4a.

[0154] By setting the light-transmitting bonding layer 3 as a transparent conductive layer, the light emitted by the light emitting device 4a can pass through the light-transmitting bonding layer 3 to the reflective layer 2 and be reflected out by the reflective layer 2, and the transparent conductive block 31 constituting the transparent conductive layer can be electrically connected to the first conductive structure 22 as an anode of the light emitting device 4a; at the same time, it can also serve as a bonding layer for bonding the light emitting device layer 4 and the silicon-based backboard 1, so that the light emitting device layer 4 and the silicon-based backboard 1 can be stably connected in structure and electrically connected in electrical property.

[0155] Please refer to Figure 6 for another structure of a micro display panel provided by the embodiment of the present application, the light-transmitting bonding layer 3 includes a second insulating layer 32 and a plurality of second conductive structures 33; the second insulating layer 32 is light-transmitting;

[0156] The second insulating layer 32 includes a plurality of second through holes H2 penetrating in the thickness direction, and the second conductive structure 33 is filled in the second through hole H2;

[0157] The driving circuit is electrically connected to the corresponding micro light emitting device 4a through the first conductive structure 22 and the second conductive structure 33.

[0158] The first via hole H1 can overlap with the second via hole H2, so that the first conductive structure 22 overlaps with the second conductive structure 33. The first conductive structure 22 overlaps with the second conductive structure 33, so that the second conductive structure 33 can be directly stacked on the first conductive structure 22, and there is no need to additionally set a wire connecting the first conductive structure 22 and the second conductive structure 33.

[0159] The material of the second insulating layer 32 can be SiO2 or other transparent insulating materials, which are not limited in particular. The second conductive structure 33 can be a metal with low resistivity, such as gold, copper, etc., or other conductive materials.

[0160] The thickness of the second insulating layer 32 ranges from 0.1 to 0.5 um.

[0161] When the light-transmitting bonding layer 3 includes the second insulating layer 32 and the plurality of second conductive structures 33, the value range of the repetition period of the reflective layer 2 can be 10 to 14, and the value range of the total thickness of the reflective layer 2 can be 2 to 10 um, so that the reflectivity of the reflective layer 2 can reach 99%.

[0162] Please refer to FIG. 7 for a structural schematic diagram of another micro display panel provided by an embodiment of the present application. The second insulating layer 32 includes:

[0163] The first sub-insulating layer 321 is located on the side of the light-emitting device layer 4 close to the silicon-based backboard 1. The first sub-insulating layer 321 has a first sub-via hole H21 penetrating in the thickness direction.

[0164] The second sub-insulating layer 322 is located between the first sub-insulating layer 321 and the reflective layer 2. The second sub-insulating layer 322 has a second sub-via hole H22 penetrating in the thickness direction. The second via hole H2 includes at least the first sub-via hole H21 and the second sub-via hole H22. The first sub-insulating layer 321 and the second sub-insulating layer 322 adopt the same material.

[0165] The second conductive structure 33 includes the first sub-conductive structure 331 and the second sub-conductive structure 332. The first sub-conductive structure 331 is filled in the first sub-via hole H21, and the second sub-conductive structure 332 is filled in the second sub-via hole H22. The first sub-conductive structure 331 and the second sub-conductive structure 332 that overlap with each other constitute a second conductive structure 33. The first sub-conductive structure 331 and the second sub-conductive structure 332 adopt the same material.

[0166] Ideally, when the micro display panel is manufactured, the wafer on which the light-emitting device layer 4 is located is completely aligned with the wafer on which the silicon-based backboard 1 is located when bonding. In this case, the second conductive structure 33 in the micro display panel obtained has no obvious layering error, as shown in FIG. 6.

[0167] In actual production, due to the alignment error between the wafer on which the light emitting device layer 4 is located and the wafer on which the silicon-based backboard 1 is located when being bonded, the second conductive structure 33 in the micro display panel obtained has obvious layering error, and the first sub-conductive structure 331 and the second sub-conductive structure 332 constituting the second conductive structure 33 can be clearly distinguished, as shown in FIG. 7.

[0168] By setting the second insulating layer 32 as the first sub-insulating layer 321 and the second sub-insulating layer 322, the first sub-insulating layer 321 and the second sub-insulating layer 322 can be used as sub-bonding layers of the wafer on which the light emitting device layer 4 is located and the wafer on which the silicon-based backboard 1 is located to bond the two; and by setting the first sub-via hole H21 and the second sub-via hole H22 in the first sub-insulating layer 321 and the second sub-insulating layer 322 to overlap each other, and filling the first sub-conductive structure 331 and the second sub-conductive structure 332 in the first sub-via hole H21 and the second sub-via hole H22 respectively, the corresponding first conductive structure 22 and the micro light emitting device 4a can be electrically connected through the overlapping first sub-conductive structure 331 and the second sub-conductive structure 332.

[0169] Please refer to FIG. 8 for a structural schematic diagram of another micro display panel provided by an embodiment of the present application. The first sub-insulating layer 321 includes:

[0170] A plurality of sub-insulating blocks 3211 correspond one-to-one to a plurality of micro light emitting devices 4a, and the sub-insulating block 3211 coincides with the corresponding micro light emitting device 4a; the adjacent two sub-insulating blocks 3211 and the second sub-insulating layer 322 form a groove K'. Each sub-insulating block 3211 includes a first sub-via hole H21 penetrating through the thickness direction, and the first sub-conductive structure 331 is filled in the first sub-via hole H21.

[0171] By setting the first sub-insulating layer 321 to include a plurality of sub-insulating blocks 3211, the light emitting device layer 4 and the first sub-insulating layer 321 can be patterned first when the wafer on which the light emitting device layer 4 is located is made, and then the plurality of sub-insulating blocks 3211 obtained are bonded with the second sub-insulating layer 322. Since the first sub-insulating layer 321 and the light emitting device layer 4 in FIG. 8 are patterned at the same time when being made, the gap K between the adjacent two micro light emitting devices 4a coincides with the groove K'. FIGS. 6 and 7 are first bonding the first sub-insulating layer 321 with the second sub-insulating layer 322, and then patterning the light emitting device layer 4.

[0172] By setting the light-transmitting bonding layer 3 as the second insulating layer 32 with a plurality of second through holes H2, and filling the second conductive structure 33 in the second through holes H2, the first conductive structure 22 and the corresponding light emitting device 4a can be electrically connected by the second conductive structure 33, so that the driving circuit is electrically connected to the corresponding light emitting device 4a through the first conductive structure 22 and the second conductive structure 33; meanwhile, the second insulating layer 32 can be reliably connected to the reflective layer 2 and the light emitting device layer 4, which facilitates the bonding of the light emitting device layer 4 and the silicon-based backboard 1 with the reflective layer 2 by hybrid bonding technology. Compared with ITO bonding technology, the hybrid bonding technology is more mature, requires lower temperature and shorter time.

[0173] Please refer to FIG. 9 and FIG. 10 for another structure of the micro display panel provided by the embodiment of the present application. The gap K is between the two adjacent micro light emitting devices 4a; the micro display panel further comprises a filling layer 5 filled in the gap K and around the plurality of micro light emitting devices 4a, and the filling layer absorbs light or reflects light.

[0174] In FIG. 10, the transparent conductive block 31 included in the transparent bonding layer 3 comprises a first sub-transparent conductive block 311 and a second sub-transparent conductive block 312. The film layer where the first sub-transparent conductive block 311 is located belongs to the same wafer as the light emitting device layer 4 when manufactured, and they are obtained by patterning at the same time before bonding. The film layer where the second sub-transparent conductive block 312 is located belongs to another wafer as the film layer where the silicon-based backboard 1 is located when manufactured, and the second sub-transparent conductive block 312 is obtained by patterning before bonding. Since there may be an alignment error between the two wafers during bonding, the first sub-transparent conductive block 311 and the second sub-transparent conductive block 312 may have a layering error, but this does not affect the conductivity of the transparent conductive block 31.

[0175] By filling the light-absorbing filling layer 5 in the gap K between the two adjacent micro light emitting devices 4a and around the plurality of micro light emitting devices 4a, the contrast of the micro display panel can be improved; by filling the light-reflecting filling layer 5 in the gap K between the two adjacent micro light emitting devices 4a and around the plurality of micro light emitting devices 4a, the light efficiency of the micro display panel can be further improved.

[0176] Please refer to FIG. 11 for another structure of the micro display panel provided by the embodiment of the present application. The light emitting device layer 4 comprises a P-type gallium nitride layer 41, a multi-quantum well layer 42 and an N-type gallium nitride layer 43; the P-type gallium nitride layer 41 is located on the side of the reflective layer 3 away from the silicon-based backboard 1, and the multi-quantum well layer 42 is located between the P-type gallium nitride layer 41 and the N-type gallium nitride layer 43.

[0177] The silicon-based backboard 1 further comprises a plurality of second connecting holes H" on the side of the silicon-based backboard 1 close to the reflecting layer 3, the plurality of second connecting holes H" correspond to the plurality of micro light emitting devices 4a one by one; the second connecting hole H" can be a metal connecting hole such as a tungsten hole or other conductive connecting hole, which is not limited herein.

[0178] The pattern of the P-type gallium nitride layer 41 and the pattern of the multiple quantum well layer 42 in the same micro light emitting device 4a correspond to the pattern of the N-type gallium nitride layer 43 which is overlapped; wherein the pattern area of the N-type gallium nitride layer 43 is greater than the pattern area of the multiple quantum well layer 42; the pattern of the P-type gallium nitride layer 41 and the pattern of the multiple quantum well layer 42 are coincident;

[0179] The micro display panel further comprises a plurality of third conductive structures 34 corresponding to the plurality of micro light emitting devices 4a one by one, the second connecting hole H" corresponding to the same micro light emitting device 4a is overlapped and electrically connected with the third conductive structure 34; the light-transmitting bonding layer 3 comprises a plurality of third through holes H3 penetrating through the thickness direction, the third conductive structure 34 is filled in the third through hole H3, the reflecting layer 2 comprises a plurality of fourth through holes H4 penetrating through the thickness direction, the fourth conductive structure 23 is filled in the fourth through hole H4, the third through hole H3 corresponding to the same micro light emitting device 4a is at least overlapped with the fourth through hole H4, the third conductive structure 34 is electrically connected with the second connecting hole H" and the micro light emitting device 4a through the corresponding fourth conductive structure 23.

[0180] The third conductive structure 34 is in the orthographic projection of the silicon-based backboard 1, and is located in the orthographic projection of the pattern of the N-type gallium nitride layer 43 in the silicon-based backboard 1, and is not overlapped with the pattern of the P-type gallium nitride layer 43 and the pattern of the multiple quantum well layer 42;

[0181] The second conductive structure 33 is in the orthographic projection of the silicon-based backboard 1, and is located in the orthographic projection of the pattern of the P-type gallium nitride layer 41 and the pattern of the multiple quantum well layer 42 in the silicon-based backboard 1.

[0182] Fig. 11 shows that the transparent bonding layer 3 in the micro display panel is composed of the second insulating layer 32 and the second conductive structure 33 and the third conductive structure 34, and in order to facilitate the observation of the micro display panel, the bonding is shown without alignment error, when there is alignment error, the second conductive structure 33 and the third conductive structure 34 exist the misregistration phenomenon, which can be referred to the foregoing description of the related embodiments, and will not be repeated here.

[0183] Please refer to Fig. 12 for another structure schematic diagram of the micro display panel provided by the embodiment of the present application, the light-transmitting bonding layer 3 in the micro display panel is composed of a plurality of transparent conductive blocks 31 and a plurality of third conductive structures 34, and in order to facilitate the observation of the micro display panel, the bonding is shown without alignment error, when there is alignment error, the third conductive structure 34 exists the misregistration phenomenon, which will not be repeated here.

[0184] By overlapping the pattern of the P-type gallium nitride layer 41 and the pattern of the multi-quantum well layer 42 of the micro light emitting device 4a with the pattern of the N-type gallium nitride layer 43, the area of the pattern of the N-type gallium nitride layer 43 is greater than the area of the pattern of the multi-quantum well layer 42, and the third conductive structure 34 is located within the projection of the pattern of the N-type gallium nitride layer 43 on the silicon-based backboard 1, and does not overlap with the pattern of the P-type gallium nitride layer 41 and the pattern of the multi-quantum well layer 42, and the second conductive structure 33 is located within the projection of the pattern of the P-type gallium nitride layer 41 and the pattern of the multi-quantum well layer 42 on the silicon-based backboard 1, so that the second conductive structure 33 and the third conductive structure 34 can be used as the anode and the cathode of the micro light emitting device 4a, respectively, thereby facilitating independent control of the micro light emitting device 4a by the silicon-based backboard 1.

[0185] Please refer to FIG. 13 for another structure of the micro display panel provided by the embodiment of the present application. The silicon-based backboard 1 further comprises a second connecting hole H” located on the side of the silicon-based backboard 1 close to the reflecting layer 3.

[0186] The micro display panel further comprises:

[0187] The current spreading layer 6 is located on the side of the light emitting device layer 4 away from the silicon-based backboard 1. The current spreading layer 6 can be made of transparent conductive material, such as ITO, IZO

[0188] The grid-shaped common electrode 7 is located on the side of the current spreading layer 6 away from the silicon-based backboard 1, and does not overlap with the light emitting device layer 4 and overlaps with the second connecting hole H”. By arranging the current spreading layer 6 between the grid-shaped common electrode 7 and the light emitting device layer 4, the contact area between the micro light emitting device 4a and the current spreading layer 6 can be increased, and the current can be spread to the entire micro light emitting device 4a, thereby improving the uniformity of the current in the micro light emitting device 4a. The common electrode 7 can be made of metal material, which can improve the conductivity. By arranging the common electrode 7 in a grid shape and without overlapping with the light emitting device 4a (i.e. the light emitting device layer 4), the common electrode 7 can reduce the shielding of the light emitted by the micro light emitting device 4a, thereby improving the light efficiency of the micro display panel.

[0189] In the thickness direction, the edge of the common electrode 7 extends to the second connecting hole H” of the silicon-based backboard 1.

[0190] The silicon-based backboard 1 can comprise one second connecting hole H”, or can comprise a plurality of second connecting holes H”. The second connecting hole H” is located outside the projection of the light emitting device layer 4 on the silicon-based backboard.

[0191] By arranging the current spreading layer 6 on the side of the light emitting device layer 4 away from the silicon-based backboard 1, and arranging the grid-shaped common electrode 7 on the side of the current spreading layer 6 away from the silicon-based backboard 1, the common electrode 7 is not overlapped with the light emitting device layer 4 and is overlapped with the second connecting hole H'', the common electrode 7 is electrically connected with the second connecting hole H'' through the third conductive structure 34, and the plurality of micro light emitting devices 4a are connected in parallel, so that the silicon-based backboard 1 can independently control the plurality of micro light emitting devices 4a, and the number of the second connecting holes H'' contained in the silicon-based backboard 1 can be saved, and the alignment difficulty in manufacturing the micro display panel can be reduced.

[0192] Please refer to FIG. 14 for another structure schematic diagram of a micro display panel provided by the embodiment of the present application, the light emitting device layer 4 includes a P-type gallium nitride layer 41, a multi-quantum well layer 42 and an N-type gallium nitride layer 43; the P-type gallium nitride layer 41 is located on the side of the reflecting layer 3 away from the silicon-based backboard 1, and the multi-quantum well layer 42 is located between the P-type gallium nitride layer 41 and the N-type gallium nitride layer 43.

[0193] The silicon-based backboard 1 further includes a second connecting hole H'' located on the side of the silicon-based backboard 1 close to the reflecting layer 2.

[0194] The micro display panel further includes:

[0195] The grid-shaped common electrode 7 is located between the N-type gallium nitride layer 43 and the multi-quantum well layer 43, the P-type gallium nitride layer 41 and the multi-quantum well layer 42 are patterned, and the N-type gallium nitride layer 43 is not patterned; the common electrode 7 is overlapped with the second connecting hole H'' and is not overlapped with the P-type gallium nitride layer 41 and the multi-quantum well layer 42.

[0196] In the thickness direction, the edge of the common electrode 7 extends to the second connecting hole H'' of the silicon-based backboard 1.

[0197] In the embodiment provided by the present application, by arranging the grid-shaped common electrode 7 between the unpatterned N-type gallium nitride layer 43 and the multi-quantum well layer 43, the shielding of the light emitted by the micro light emitting device 4a by the common electrode 7 can be reduced, the required film layers of the micro display panel can be reduced, and the micro display panel can be thinned.

[0198] Please continue to refer to FIG. 14, in the thickness direction, one part of the common electrode 7 is embedded in the N-type gallium nitride layer 43, and the other part is embedded in the gap between the multi-quantum well layers 42 corresponding to the adjacent two micro light emitting devices 4a, so that the flatness of the N-type gallium nitride layer 43 can be improved.

[0199] Please refer to FIG. 15 for another structure schematic diagram of a micro display panel provided by the embodiment of the present application, the micro display panel further includes:

[0200] The cover plate 8 is located on the side of the common electrode 7 away from the silicon-based backboard 1.

[0201] Referring to FIG. 16, a flowchart of a manufacturing method of a micro display panel according to an embodiment of the present application is shown. The manufacturing method comprises the following steps:

[0202] S21: forming a first wafer substrate, the first wafer substrate comprising a substrate, a light emitting device layer or a light emitting device epitaxial layer and a first sub-bonding layer, which are sequentially stacked on one side of the substrate; the light emitting device layer comprising a plurality of micro light emitting devices, the light emitting device layer being a patterned light emitting device epitaxial layer;

[0203] S22: forming a second wafer substrate, the second wafer substrate comprising a silicon-based backplane, a reflective layer and a second sub-bonding layer, which are sequentially stacked; the silicon-based backplane comprising a plurality of driving circuits corresponding to the plurality of micro light emitting devices, the driving circuits being electrically connected to the micro light emitting devices; wherein the first sub-bonding layer and the second sub-bonding layer are transparent;

[0204] S23: bonding the first wafer substrate and the second wafer substrate through the first sub-bonding layer and the second sub-bonding layer to obtain a transparent bonding layer; removing the substrate; wherein the light emitting device epitaxial layer is patterned before the bonding or after the substrate is removed.

[0205] The steps S21 and S22 can be performed simultaneously or not simultaneously, and the order of forming the first wafer substrate and the second wafer substrate can be interchanged.

[0206] Referring to FIG. 17, a schematic diagram of forming a micro display panel according to an embodiment of the present application is shown.

[0207] S31: forming a first wafer substrate 01 and a second wafer substrate 02;

[0208] The first wafer substrate 01 comprises a substrate 011, a light emitting device layer 4 and a first sub-bonding layer 013, which are sequentially stacked on one side of the substrate 011; the light emitting device layer 4 comprising a plurality of micro light emitting devices 4a; the substrate 011 can be a sapphire substrate or a silicon-based substrate.

[0209] The second wafer substrate 02 comprises a silicon-based backplane 1, a reflective layer 2 and a second sub-bonding layer 021, which are sequentially stacked; the reflectivity of the reflective layer 2 being greater than that of a metal. The first sub-bonding layer 013 and the second sub-bonding layer 021 form a transparent bonding layer 3 after bonding, and the first sub-bonding layer 013 and the second sub-bonding layer 021 have the same structure as the transparent bonding layer 3, which will not be described here.

[0210] S32: bonding the first wafer substrate 01 and the second wafer substrate 02 through the first sub-bonding layer 013 and the second sub-bonding layer 021;

[0211] S33: removing the substrate base plate 011 to obtain the micro display panel.

[0212] Please refer to Fig. 18 for another schematic diagram of forming the micro display panel according to an embodiment of the present application.

[0213] S41: forming the first wafer base plate 01 and the second wafer base plate 02;

[0214] The first wafer base plate 01 comprises a substrate base plate 011, and a light emitting device epitaxial layer 012 and a first sub-bonding layer 013 which are sequentially arranged on one side of the substrate base plate 011; the light emitting device epitaxial layer 012 is patterned to obtain a plurality of micro light emitting devices 4a; the substrate base plate 011 can be a sapphire base plate or a silicon-based substrate base plate.

[0215] The second wafer base plate 02 comprises a silicon-based back plate 1, a reflective layer 2 and a second sub-bonding layer 021 which are sequentially arranged.

[0216] S42: bonding the first wafer base plate 01 and the second wafer base plate 02 through the first sub-bonding layer 013 and the second sub-bonding layer 021; the first sub-bonding layer 013 and the second sub-bonding layer 021 are bonded to form a light-transmitting bonding layer 3, and the first sub-bonding layer 013 and the second sub-bonding layer 021 have the same structure as the light-transmitting bonding layer 3, which will not be described herein again.

[0217] S43: patterning the light emitting device epitaxial layer 012 and the light-transmitting bonding layer 3, and removing the substrate base plate 011 to obtain the micro display panel.

[0218] In the embodiments provided by the present application, the first wafer base plate 01 and the second wafer base plate 02 are formed respectively, the first sub-bonding layer 013 in the first wafer base plate 01 and the second sub-bonding layer 021 in the second wafer base plate 02 are light-transmitting, and the reflective layer 2 having a reflectivity greater than that of metal is arranged between the silicon-based back plate 1 in the second wafer base plate 01 and the second sub-bonding layer 021, so that the light emitted by the light emitting device 4a is reflected by the reflective layer 2 to the silicon-based back plate 1, thereby improving the light efficiency of the micro display panel.

[0219] Please refer to Fig. 19 for a schematic diagram of forming the first wafer base plate according to an embodiment of the present application.

[0220] S51: providing a substrate base plate 011;

[0221] S52: forming a light emitting device epitaxial layer 012 on one side of the substrate base plate 011;

[0222] S53: forming a first sub-bonding layer 013 on the side of the light emitting device epitaxial layer 012 away from the substrate base plate 011;

[0223] S54: patterning the first sub-bonding layer 013 and the light emitting device epitaxial layer 012 to obtain a plurality of micro light emitting devices 4a and the patterned first sub-bonding layer 013.

[0224] The first sub-bonding layer 013 can be formed on the side of the light emitting device epitaxial layer 012 away from the substrate substrate 011 in the following ways.

[0225] Firstly, a first sub-transparent conductive layer is grown on the side of the light emitting device epitaxial layer 012 away from the substrate substrate 011; the first sub-transparent conductive layer is used as the first sub-bonding layer 013. That is, the first sub-bonding layer 013 is directly grown on the side of the light emitting device epitaxial layer 012 away from the substrate substrate 011 (S51-S53 are performed). The material of the first sub-transparent conductive layer can be ITO or IZO, etc.

[0226] This way is suitable for the way shown in FIG. 18 to pattern the light emitting device epitaxial layer 012 after removing the substrate substrate 011, and then the first wafer substrate 01 is formed.

[0227] Secondly, a first sub-transparent conductive layer is grown on the side of the light emitting device epitaxial layer 012 away from the substrate substrate 011; the light emitting device epitaxial layer 012 and the first sub-transparent conductive layer are patterned to obtain a plurality of first sub-transparent conductive blocks and a plurality of micro light emitting devices 4a; the plurality of first sub-transparent conductive blocks are used as the first sub-bonding layer 013. That is, the first sub-bonding layer 013 is grown on the side of the light emitting device epitaxial layer 012 away from the substrate substrate 011, and then the first sub-bonding layer 013 is patterned (S51-S54 are performed).

[0228] The second scheme is suitable for the way shown in FIG. 17 to pattern the light emitting device epitaxial layer 012 before bonding.

[0229] Thirdly, please refer to FIG. 20 for a schematic diagram of forming a first sub-bonding layer provided by an embodiment of the present application.

[0230] S53': a first sub-insulating layer 321 is grown on the side of the light emitting device epitaxial layer 012 away from the substrate substrate 011; the first sub-insulating layer 321 is a transparent insulating layer, such as SiO2.

[0231] S54': a plurality of first sub-vias H21 penetrating the thickness direction are formed in the first sub-insulating layer 321;

[0232] S55': a conductive material is filled in the first sub-via H21 to obtain a first sub-conductive structure 331; the first sub-insulating layer 321 with the first sub-conductive structure 331 is used as the first sub-bonding layer 013. The material of the first sub-conductive structure 331 can be metal, such as copper, gold, etc., or other conductive materials.

[0233] S56’: patterning the first sub-bonding layer 013 and the light emitting device epitaxial layer 012 to obtain a plurality of light emitting devices and the patterned first sub-bonding layer 013. The first sub-via hole H21 is in the orthographic projection of the substrate substrate 011 within the orthographic projection of the corresponding light emitting device in the substrate substrate 011.

[0234] The first wafer substrate 01 can be formed in a third way. The light emitting device epitaxial layer 012 can be patterned before bonding in the manner shown in FIG. 17, and then S53’-S56’ are performed after S52 and S52 are performed. The light emitting device epitaxial layer 012 can also be patterned after the substrate substrate 011 is removed in the manner shown in FIG. 18, and then S53’-S55’ are performed after S52 and S52 are performed.

[0235] Please refer to FIG. 21 for a schematic diagram of forming a second wafer substrate according to an embodiment of the present application.

[0236] S61: providing a silicon-based backplane 1;

[0237] The silicon-based backplane 1 has a plurality of first connection holes H’ on one side, and the driving circuit (not shown) in the silicon-based backplane 1 is electrically connected to at least one first connection hole H’;

[0238] S62: forming a reflective layer 2 on the side of the silicon-based backplane 1 close to the first wafer substrate 01;

[0239] The reflective layer 2 is formed on the side of the silicon-based backplane 1 having a plurality of first connection holes H’;

[0240] S63: forming a plurality of first through holes H1 penetrating the thickness direction on the reflective layer 2 corresponding to the positions of the first connection holes H’; and filling the first through holes H1 with conductive material to obtain a first conductive structure 22; the first through holes H1 are located within the orthographic projection of the corresponding micro light emitting device on the silicon-based backplane;

[0241] The first through holes H1 overlap the first connection holes H’.

[0242] S64: forming a second sub-bonding layer 021 on the side of the reflective layer 2 away from the silicon-based backplane 1.

[0243] S65: patterning the second sub-bonding layer 021 to obtain a patterned second sub-bonding layer 021.

[0244] The second sub-bonding layer 021 can be formed on the side of the reflective layer 2 away from the silicon-based backplane 1 in the following ways:

[0245] The first mode: a second sub-transparent conductive layer is grown on the side of the reflective layer 2 away from the silicon-based backboard 1; the second sub-transparent conductive layer is used as the second sub-bonding layer 021. The material of the second sub-transparent conductive layer can be ITO or IZO, etc. That is, the second sub-bonding layer 021 is directly grown on the side of the reflective layer 2 away from the silicon-based backboard 1.

[0246] In this mode, the second wafer substrate 02 needs to be formed by performing S61-S64. The first mode is suitable for forming the micro display panel in the mode shown in FIG. 18.

[0247] The second mode: a second sub-transparent conductive layer is grown on the side of the reflective layer 2 away from the silicon-based backboard 1; the second sub-transparent conductive layer is patterned to obtain a plurality of second sub-transparent conductive blocks corresponding to the plurality of micro light emitting devices 4a one by one; the plurality of second sub-transparent conductive blocks are used as the second sub-bonding layer 021. After the first sub-bonding layer 013 and the second sub-bonding layer 021 are bonded, the first sub-transparent conductive block and the corresponding second sub-transparent conductive block constitute a transparent conductive block. That is, after the second sub-bonding layer 021 is grown on the side of the reflective layer away from the silicon-based backboard 1, the second sub-bonding layer 021 is patterned. In this mode, the second wafer substrate 02 needs to be formed by performing S61-S65.

[0248] The second mode is suitable for forming the micro display panel in the mode shown in FIG. 17.

[0249] The third mode, please refer to FIG. 22 for a schematic diagram of forming a second sub-bonding layer provided by an embodiment of the present application.

[0250] S64': a second sub-insulating layer 322 is grown on the side of the reflective layer 2 away from the silicon-based backboard 1; the second sub-insulating layer 322 is a transparent insulating layer, such as SiO2.

[0251] S65': a plurality of second sub-vias H22 penetrating the thickness direction are formed in the second sub-insulating layer 322;

[0252] S66': the second sub-vias H22 are filled with conductive materials to obtain a second sub-conductive structure 332; the second sub-insulating layer 322 with the second sub-conductive structure 332 is used as the second sub-bonding layer 021.

[0253] After the first sub-bonding layer 013 and the second sub-bonding layer 021 are bonded, the first sub-insulating layer 321 and the second sub-insulating layer 322 jointly constitute the second insulating layer 32, and the first sub-conductive structure 331 and the corresponding second sub-conductive structure jointly constitute the second conductive structure 33.

[0254] When the second wafer substrate 02 is formed in the third mode, after S61-S63 are performed, S64'-S66' are performed.

[0255] The third mode is suitable for manufacturing the micro display panel in the mode shown in FIG. 17.

[0256] Based on the same inventive concept, the embodiment of the present application provides a micro display device comprising the micro display panel as shown above.

[0257] The micro display device can be a liquid crystal display device, an electroluminescent display device, etc., and can be used in AR, VR display products.

[0258] Although preferred embodiments of the present application have been described, those skilled in the art who have the benefit of the present disclosure can make additional alterations and modifications of the embodiments without departing from the spirit and scope of the present application. Therefore, it is intended that the appended claims be construed to include all such alterations and modifications as falling within the scope of the present application.

[0259] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the spirit and scope of the present application. Thus, it is intended that the present application embrace all such modifications and changes as fall within the scope of the appended claims and their equivalents.

Claims

1. A microdisplay panel, wherein, The application relates to a light-emitting device, comprising: a silicon-based backplane comprising a plurality of driving circuits; a reflective layer located on one side of the silicon-based backplane; wherein the reflectivity of the reflective layer is greater than that of metal; a light-transmitting bonding layer located on the side of the reflective layer away from the silicon-based backplane; a light-emitting device layer located on the side of the light-transmitting bonding layer away from the silicon-based backplane; the light-emitting device layer comprises a plurality of micro light-emitting devices, and the micro light-emitting devices are electrically connected with the driving circuits.

2. The microdisplay panel of claim 1, wherein, The reflective layer comprises a plurality of first insulating layers and a plurality of first conductive structures; The plurality of first insulating layers have a plurality of first through holes penetrating through the thickness direction, and the first conductive structures are filled in the first through holes; the driving circuits are electrically connected with the corresponding micro light-emitting devices through at least one first conductive structure.

3. The microdisplay panel of claim 2, wherein, The first through holes are located in the projection of the corresponding micro light-emitting devices on the silicon-based backplane.

4. The microdisplay panel of claim 2 or 3, wherein, In the direction of the silicon-based backplane pointing to the light-transmitting bonding layer, the plurality of first insulating layers are arranged alternately in a first insulating layer with a first refractive index and a first insulating layer with a second refractive index; wherein the first refractive index is greater than the second refractive index; the thickness of each first insulating layer is 1 / 4 wavelength.

5. The microdisplay panel of any of claims 2-4, wherein, The silicon-based backplane further comprises: a plurality of first connecting holes located on the side of the silicon-based backplane close to the reflective layer, the first connecting holes overlap with the corresponding first through holes; the driving circuits are electrically connected with the first conductive structures through the first connecting holes.

6. The microdisplay panel of any of claims 1-5, wherein, The light-transmitting bonding layer is a transparent conductive layer; The transparent conductive layer comprises a plurality of transparent conductive blocks corresponding to the plurality of micro light-emitting devices one by one, and the transparent conductive blocks coincide with the corresponding micro light-emitting devices.

7. The microdisplay panel of claim 4, wherein, The light-transmitting bonding layer comprises a second insulating layer and a plurality of second conductive structures; the second insulating layer is light-transmitting; The second insulating layer comprises a plurality of second through holes penetrating through the thickness direction, and the second conductive structures are filled in the second through holes; The driving circuits are electrically connected with the corresponding micro light-emitting devices through the first conductive structures and the second conductive structures.

8. The microdisplay panel of claim 7, wherein, The second insulating layer comprises: a first sub-insulating layer located on the side of the light-emitting device layer close to the silicon-based backplane; the first sub-insulating layer has first sub-through holes penetrating through the thickness direction; a second sub-insulating layer located between the first sub-insulating layer and the reflective layer; the second sub-insulating layer has second sub-through holes penetrating through the thickness direction, and the second through holes comprise at least the first sub-through holes and the second sub-through holes; The second conductive structures comprise first sub-conductive structures and second sub-conductive structures, the first sub-conductive structures are filled in the first sub-through holes, and the second sub-conductive structures are filled in the second sub-through holes.

9. The microdisplay panel of claim 8, wherein, The first sub-insulating layer comprises: a plurality of sub-insulating blocks corresponding to the plurality of micro light-emitting devices one by one, and the sub-insulating blocks coincide with the corresponding micro light-emitting devices; adjacent two sub-insulating blocks and the second sub-insulating block form a groove.

10. The microdisplay panel of any of claims 7-9, wherein, The light-emitting device layer comprises a P-type gallium nitride layer, a multi-quantum well layer and an N-type gallium nitride layer; the P-type gallium nitride layer is located on the side of the reflective layer away from the silicon-based backboard, and the multi-quantum well layer is located between the P-type gallium nitride layer and the N-type gallium nitride layer; The silicon-based backboard further comprises a plurality of second connecting holes located on the side of the silicon-based backboard close to the reflective layer; The plurality of second connecting holes correspond one-to-one to the plurality of micro light-emitting devices; The pattern of the N-type gallium nitride layer in the same micro light-emitting device corresponds to the pattern of the P-type gallium nitride layer and the pattern of the multi-quantum well layer and is overlapped; wherein the area of the pattern of the N-type gallium nitride layer is greater than the area of the pattern of the multi-quantum well layer; The micro display panel further comprises a plurality of third conductive structures corresponding one-to-one to the plurality of micro light-emitting devices, and the second connecting hole corresponding to the same micro light-emitting device is overlapped and electrically connected with the third conductive structure; The third conductive structure is located in the projection of the N-type gallium nitride layer on the silicon-based backboard and does not overlap with the pattern of the P-type gallium nitride layer and the pattern of the multi-quantum well layer; The second conductive structure is located in the projection of the P-type gallium nitride layer and the multi-quantum well layer on the silicon-based backboard.

11. The microdisplay panel of any of claims 1-9, wherein, The silicon-based backboard further comprises a second connecting hole located on the side of the silicon-based backboard close to the reflective layer and not overlapped with the plurality of micro light-emitting devices; The micro display panel further comprises: A second transparent conductive layer located on the side of the light-emitting device layer away from the silicon-based backboard; A grid-shaped common electrode located on the side of the second transparent conductive layer away from the silicon-based backboard, the common electrode being not overlapped with the light-emitting device layer and overlapped with the second connecting hole; In the thickness direction, the edge of the common electrode extends to the second connecting hole.

12. The microdisplay panel of any of claims 1-9, wherein, The light-emitting device layer comprises a P-type gallium nitride layer, a multi-quantum well layer and an N-type gallium nitride layer; the P-type gallium nitride layer is located on the side of the reflective layer away from the silicon-based backboard, and the multi-quantum well layer is located between the P-type gallium nitride layer and the N-type gallium nitride layer; The silicon-based backboard further comprises a second connecting hole located on the side of the silicon-based backboard close to the reflective layer; The micro display panel further comprises: A grid-shaped common electrode located between the N-type gallium nitride layer and the multi-quantum well layer, the P-type gallium nitride layer and the multi-quantum well layer being patterned, and the N-type gallium nitride layer not being patterned; the common electrode is overlapped with the second connecting hole and not overlapped with the P-type gallium nitride layer and the multi-quantum well layer; In the thickness direction, the edge of the common electrode extends to the second connecting hole. In the thickness direction, one part of the common electrode is inlaid in the N-type gallium nitride layer, and the other part is inlaid in the gap between the multi-quantum well layers corresponding to the adjacent two micro light-emitting devices.

13. The microdisplay panel of claim 12, wherein, There is a gap between the adjacent two micro light-emitting devices; 14. The microdisplay panel of any of claims 1-13, wherein, The micro display panel further comprises: A filling layer filled in the gap and around the plurality of micro light-emitting devices; the filling layer absorbs light or reflects light. ​ 15. A method of fabricating a microdisplay panel, wherein, The method comprises the following steps: forming a first wafer substrate, the first wafer substrate comprising a substrate wafer and a light-emitting device layer or a light-emitting device epitaxial layer and a first sub-bonding layer which are sequentially stacked on one side of the substrate wafer; the light-emitting device layer comprises a plurality of micro light-emitting devices, and the light-emitting device layer is a patterned light-emitting device epitaxial layer; forming a second wafer substrate, the second wafer substrate comprising a silicon-based backboard, a reflective layer and a second sub-bonding layer which are sequentially stacked; the silicon-based backboard comprises a plurality of driving circuits corresponding to the plurality of micro light-emitting devices one by one, and the driving circuits are electrically connected to the micro light-emitting devices; wherein the reflectivity of the reflective layer is greater than the reflectivity of metal, and the first sub-bonding layer and the second sub-bonding layer are light-transmissive; bonding the first wafer substrate and the second wafer substrate through the first sub-bonding layer and the second sub-bonding layer to obtain a light-transmissive bonding layer; and removing the substrate wafer; wherein the light-emitting device epitaxial layer is patterned before bonding or after removing the substrate wafer. forming a first wafer substrate, comprising:

16. The production method according to claim 15, wherein providing a substrate wafer; forming the light-emitting device epitaxial layer on one side of the substrate wafer; forming the first sub-bonding layer on the side of the light-emitting device epitaxial layer away from the substrate wafer. forming the first sub-bonding layer on the side of the light-emitting device epitaxial layer away from the substrate wafer, comprising:

17. The production method according to claim 16, wherein growing a first sub-transparent conductive layer on the side of the light-emitting device epitaxial layer away from the substrate wafer; taking the first sub-transparent conductive layer as the first sub-bonding layer. After growing the first sub-transparent conductive layer, further comprising:

18. The production method according to claim 17, wherein patterning the light-emitting device epitaxial layer and the first sub-transparent conductive layer to obtain a plurality of first sub-transparent conductive blocks and the plurality of micro light-emitting devices; taking the plurality of first sub-transparent conductive blocks as the first sub-bonding layer. forming the first sub-bonding layer on the side of the light-emitting device epitaxial layer away from the substrate wafer, comprising:

19. The production method as claimed in claim 16, wherein, growing a first sub-insulating layer on the side of the light-emitting device epitaxial layer away from the substrate wafer; forming a plurality of first sub-vias penetrating through the thickness direction in the first sub-insulating layer; filling a conductive material in the first sub-via to obtain a first sub-conductive structure; taking the first sub-insulating layer with the first sub-conductive structure as the first sub-bonding layer. forming a second wafer substrate, comprising:

20. The method of manufacturing of claim 15, wherein, providing the silicon-based backboard; forming the reflective layer on the side of the silicon-based backboard close to the first wafer substrate; forming a plurality of first vias penetrating through the thickness direction on the reflective layer; and filling a conductive material in the first vias to obtain a first conductive structure; the first vias are located in the orthographic projection of the corresponding micro light-emitting device on the silicon-based backboard; forming the second sub-bonding layer on the side of the reflective layer away from the silicon-based backboard. forming the second sub-bonding layer on the side of the reflective layer away from the silicon-based backboard, comprising:

21. The production method according to claim 20, wherein growing a second sub-transparent conductive layer on the side of the reflective layer away from the silicon-based backboard; taking the second sub-transparent conductive layer as the second sub-bonding layer. After growing the second sub-transparent conductive layer, further comprising:

22. The method of manufacturing as defined in claim 21, wherein, ​ The second sub-transparent conductive layer is patterned to obtain a plurality of second sub-transparent conductive blocks corresponding to the plurality of micro light emitting devices one by one; The plurality of second sub-transparent conductive blocks are used as the second sub-bonding layer.

23. The production method according to claim 20, wherein On the side of the reflective layer away from the silicon-based backboard, the second sub-bonding layer is formed, comprising: On the side of the reflective layer away from the silicon-based backboard, a second sub-insulating layer is grown; A plurality of second sub-vias penetrating the thickness direction are formed in the second sub-insulating layer; A second sub-conductive structure is obtained by filling a conductive material in the second sub-via; The second sub-insulating layer with the second sub-conductive structure is used as the second sub-bonding layer.

24. A microdisplay device, wherein, The micro display panel comprises the micro display panel according to any one of claims 1-14.

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