Semiconductor device and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of electronics. Provided in the embodiments are a semiconductor device, a manufacturing method therefor, and an electronic device, which are used for reducing the likelihood of short circuit between a gate structure and a source / drain in semiconductor devices. The semiconductor device comprises a substrate, and a source, a drain, a plurality of channel layers, a gate structure, and an inner spacer, which are provided on the same side of the substrate. The plurality of channel layers are located between the source and the drain, the plurality of channel layers being distributed at intervals in the thickness direction of the substrate. The gate structure surrounds each channel layer. The inner spacer comprises a plurality of first sub-inner spacers, the plurality of first sub-inner spacers being respectively provided between adjacent channel layers and located on two sides of the gate structure. Each first sub-inner spacer has an uneven first surface that is separately attached to the channel layers on both sides. By means of the simple structural arrangement, the semiconductor device can reduce the probability of short circuit between the gate structure and the source / drain, thereby effectively improving the reliability of the semiconductor device.

Description

Semiconductor device and preparation method therefor, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410990954.5, filed on July 22, 2024, and entitled "Semiconductor device and preparation method therefor, and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, and in particular to a semiconductor device and a preparation method therefor, and an electronic device. BACKGROUND

[0003] With the advancement of Moore's law, semiconductor devices have evolved from metal-oxide-semiconductor field-effect transistors (MOSFETs) to fin field effect transistors (Fin FETs). That is, semiconductor devices have undergone a transition from a planar structure to a three-dimensional structure, improving device performance while reducing the impact of short channel effects.

[0004] However, as the physical size of semiconductor devices continues to decrease, Fin FETs also face problems such as increased electrostatic coupling and parasitic capacitance, and increased off-state leakage.

[0005] Currently, a new type of semiconductor device, namely a nanowire (NW) / nanosheet (NS) gate all around field-effect transistor (GAA FET), has been introduced in the field. The GAA FET can effectively replace the key devices of Fin FETs below 5 nm, and can significantly suppress short channel effects and improve the current driving performance of the device.

[0006] The current GAA FET requires an inner sidewall between the source / drain and the gate structure. However, the inner sidewall is formed by depositing a dielectric material and etching the dielectric material in two steps, and the topography of the finally formed inner sidewall is difficult to accurately control. It is easy to cause the inner sidewall to be etched through, resulting in a short circuit between the gate structure and the source / drain, which affects the performance of the GAA FET. SUMMARY

[0007] The embodiments of the present application provide a semiconductor device and a preparation method therefor, and an electronic device, which are used to adjust the topography of the inner sidewall to reduce the probability of short circuit between the gate structure and the source / drain, and improve the performance of the semiconductor device.

[0008] To achieve the above objectives, this application adopts the following technical solution:

[0009] A first aspect of this application provides a semiconductor device. The semiconductor device includes a substrate, and a source, a drain, a plurality of channel layers, a gate structure, and inner sidewalls disposed on the same side of the substrate. The plurality of channel layers are located between the source and the drain, with one end of each channel layer connected to the source and the other end connected to the drain. The plurality of channel layers are spaced apart along the thickness direction of the substrate. A gate structure surrounds each channel layer. The inner sidewalls include a plurality of first sub-inner sidewalls, which are respectively disposed between adjacent channel layers and on both sides of the gate structure, for isolating the source, drain, and gate structure. Each first sub-inner sidewall has an uneven first surface that respectively conforms to the channel layers on both sides.

[0010] The semiconductor device provided in this application embodiment increases the difficulty of the etching gas used in the channel release process traveling along the interface between the first sub-inner wall and the channel layer to the source or drain by making the first surface of the first sub-inner wall uneven. This improves the problem of gaps forming between the first sub-inner wall and the channel layer due to the etching gas traveling along the interface between the first sub-inner wall and the channel layer. This helps reduce the probability of short circuits between the gate structure and the source or drain, and improves the electrical performance of the semiconductor device.

[0011] In one possible implementation, the first surface includes a first protrusion projecting toward the channel layer thereto, and the surface of the channel layer that is in contact with the first surface has a first targeted recess that is in contact with the first protrusion.

[0012] This design allows the first protrusion to engage with the first target recess, increasing the contact area between the first surface of the first sub-inner wall and the channel layer. This reduces the likelihood of gaps forming between the first sub-inner wall and the channel layer. Furthermore, the presence of the first protrusion directly alters the morphology of the first surface of the first sub-inner wall, making the surface near the channel layer uneven, further reducing the probability of etching gas forming gaps between the first sub-inner wall and the channel layer.

[0013] In one possible implementation, along the thickness direction of the substrate, the first protrusion protrudes from the first surface near the edge of the gate structure.

[0014] With this configuration, the first protrusion is closer to the interior of the adjacent channel layer than the edge of the gate structure on the first surface, so as to increase the contact area between the sub-inner wall and the channel layer and reduce the probability of gaps forming between the sub-inner wall and the channel layer.

[0015] In one possible implementation, the first surface has a recess away from the channel layer it is attached to, the recess being located on the side of the first protrusion away from the gate structure; the surface of the channel layer that is attached to the first surface has a first target protrusion that is attached to the recess.

[0016] This configuration utilizes the first protrusion and depression to alter the extension direction of the first surface of the sub-inner wall, further increasing the unevenness of the surface of the sub-inner wall near the channel layer. This further increases the difficulty of forming the gap connecting the gate structure with the source and drain. Consequently, the probability of short circuits between the gate structure and the source and drain is further reduced, improving the electrical performance of the semiconductor device.

[0017] In one possible implementation, the recess and the first protrusion are continuously disposed on the first surface.

[0018] This configuration, with both a first protrusion and a depression on the first surface, increases the surface unevenness of the first sub-inner wall near the channel layer, making it more difficult to form the gap connecting the gate structure to the source and drain. This further reduces the probability of short circuits between the gate structure and the source and drain, thereby improving the electrical performance of the semiconductor device.

[0019] In one possible implementation, along the thickness direction of the substrate, the first surface protrudes from the recess away from the edge of the gate structure.

[0020] This configuration allows the edge of the first surface furthest from the gate structure to further alter the extension direction of the sub-inner sidewall near the channel layer, increasing the unevenness of the sub-inner sidewall near the channel layer. This further increases the difficulty of forming the gap connecting the gate structure with the source and drain. Consequently, the probability of short circuits between the gate structure and the source and drain is further reduced, thereby improving the electrical performance of the semiconductor device.

[0021] In one possible implementation, along the length of the gate structure, the edge of the surface of the channel layer that contacts the inner wall of the sub-channel protrudes beyond the edge of the first surface away from the gate structure in the thickness direction of the substrate.

[0022] This setup meets the existing process requirements for manufacturing inner walls, thereby reducing the difficulty of manufacturing semiconductor devices.

[0023] In one possible implementation, the first surface further includes a second protrusion protruding toward the channel layer thereon, the second protrusion being located on the side of the first protrusion away from the gate structure; the surface of the channel layer that is in contact with the first surface has a second target recess that is in contact with the second protrusion.

[0024] This configuration increases the contact area between the inner wall and the channel layer by utilizing the first and second protrusions. Furthermore, by repeatedly altering the extension direction of the inner wall surface near the channel layer using the first and second protrusions, the difficulty of forming the gap connecting the gate structure to the source and drain is further increased. This further reduces the probability of short circuits between the gate structure and the source and drain, thereby improving the electrical performance of the semiconductor device.

[0025] In one possible implementation, the inner wall further includes a plurality of second sub-inner walls disposed between the channel layer adjacent to the substrate and the substrate and located on both sides of the gate structure, for isolating the source and drain from the gate structure. The second sub-inner walls have uneven second surfaces that respectively conform to the channel layer and the substrate on both sides.

[0026] This configuration utilizes the morphology of the second surface of the second sub-inner wall to increase the difficulty of the etching gas used in the channel release process propagating along the interface between the second sub-inner wall and the channel layer / substrate towards the source or drain. This mitigates the problem of gaps forming between the second sub-inner wall and the channel layer due to etching gas propagation along the interface. It also helps reduce the probability of short circuits between the gate structure and the source / drain, improving the electrical performance of the semiconductor device. Therefore, the semiconductor device provided in this application embodiment can effectively improve the reliability of the semiconductor device by reducing the probability of short circuits between the gate structure and the source / drain through a simple structural configuration.

[0027] A second aspect of this application provides an electronic device. The electronic device includes a circuit board and a semiconductor device. The semiconductor device is located on the circuit board and is electrically connected to the circuit board. The semiconductor device includes the semiconductor device described in any of the first aspects.

[0028] The beneficial effects of the electronic device provided in this application embodiment can be referred to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here.

[0029] A third aspect of this application provides a method for fabricating a semiconductor device. The method includes: forming a plurality of channel layers and a plurality of sacrificial layers, wherein the sacrificial layers and channel layers are alternately disposed; forming inner sidewalls; the inner sidewalls include a plurality of first sub-inner sidewalls, each located on both sides of a sacrificial layer and disposed between adjacent channel layers, the first sub-inner sidewalls having an uneven first surface respectively conforming to the channel layers on both sides; forming a source and a drain; the source and drain are located on both sides of a channel layer; the source is connected to one end of the channel layer, and the drain is connected to the other end of the channel layer; and forming a gate structure; the gate structure surrounds each channel layer. The plurality of first sub-inner sidewalls are located on both sides of the gate structure to isolate the source and drain from the gate structure.

[0030] The semiconductor device fabrication method provided in this application involves a secondary processing of the sacrificial layer to make the first trench wall of the formed second trench (a first type of second trench) uneven. Therefore, when forming the first sub-inner wall within the first type of second trench, the first surface of the first sub-inner wall in contact with the channel layer can be uneven. This alters the morphology of the first sub-inner wall, making the surface of the first sub-inner wall near the channel layer uneven. This increases the difficulty of the etching gas used in the channel release process transporting along the interface between the first sub-inner wall and the channel layer towards the source or drain, thus mitigating the problem of gaps forming between the first sub-inner wall and the channel layer due to etching gas transport along the interface. This helps reduce the probability of short circuits between the gate structure and the source or drain.

[0031] In one possible implementation, before forming the inner sidewall, the semiconductor device fabrication method further includes: forming a plurality of sacrificial layers on one side of a substrate. The sacrificial layers and channel layers are alternately disposed along the thickness direction of the substrate. Forming the inner sidewall on one side of the substrate includes: forming a first groove on both sides of the sacrificial layer along the length direction of the gate structure. The channel layer and the first groove are passivated to form a first protective layer. The first protective layer includes a first portion and a second portion, the first portion being located on the side of the channel layer and the second portion being located within the first groove. The first portion is removed to expose the channel layer. The second portion is removed to form a second groove. A first groove wall of the second groove that contacts the channel layer has a first target recess. A sub-inner sidewall is formed within the second groove. The portion of the sub-inner sidewall located within the first target recess serves as a first protrusion.

[0032] Based on this, during the formation of the sub-inner sidewall, a first protrusion can be formed on the first surface of the sub-inner sidewall in contact with the channel layer through a secondary etching process. This allows the undulation of the first protrusion to alter the morphology of the first surface of the sub-inner sidewall, making the surface of the sub-inner sidewall near the channel layer uneven. This increases the difficulty of the etching gas extending towards the source and drain sides, reduces the formation of gaps between the etching gas and the sacrificial layer and the channel layer, and lowers the probability of short circuits between the gate structure and the source and drain.

[0033] In one possible implementation, passivation treatment is performed on the channel layer and the first groove to form a first protective layer, including: introducing a passivation gas into the channel layer and the first groove; the passivation gas reacts with the channel layer to form a first portion with a first thickness; and the passivation gas reacts with the first groove to form a second portion with a second thickness. The first thickness is greater than the second thickness.

[0034] This configuration utilizes the thickness difference between the first and second thicknesses to compensate for the issue where the etching rate of the first portion on the outer side is greater than that of the second portion on the inner side due to the loading effect (etching effect). This reduces the difference in time required for the first and second portions to be completely etched. Consequently, it reduces the likelihood that the second portion needs to be etched even after the first portion is completely removed, which could damage the sides of the channel layer facing the source and drain regions due to the etching gas. This is beneficial for improving the electrical performance of semiconductor devices.

[0035] In one possible implementation, the thickness of the first part ranges from 0.5 nm to 10 nm.

[0036] With this configuration, the thickness of the first part is in the range of 0.5nm to 10nm, which can both protect the channel layer and meet the requirements of the etching process.

[0037] In one possible implementation, the second part includes a first sub-part and a second sub-part. The second sub-part is in contact with the sacrificial layer, and the thickness of the first sub-part is greater than the thickness of the second sub-part.

[0038] With this configuration, the second sub-section will be completely removed before the first sub-section. Furthermore, due to the loading effect (etching effect), the etching rate of the etching gas on the outer end of the second sub-section closer to the first sub-section is greater than the etching rate on the inner end of the second sub-section farther from the first sub-section. Therefore, the end of the second sub-section closer to the first sub-section will be completely removed first, and the etching gas will continue to etch the channel layer at the corresponding position of the end of the second sub-section closer to the first sub-section, removing this portion of the channel layer structure and making the corresponding surface of the channel layer uneven. That is, the first groove wall in contact with the channel layer of the second groove is uneven.

[0039] In one possible implementation, the thickness of the second part ranges from 0.1 nm to 5 nm.

[0040] With this configuration, when the thickness of the second part is between 0.1nm and 5nm, it is possible to ensure that the end of the second sub-part closer to the first sub-part and the end of the second sub-part farther from the first sub-part are completely removed first, and then the etching gas will continue to etch the channel layer at the corresponding position of the end of the second sub-part closer to the first sub-part, removing this part of the channel layer structure so that the corresponding surface of the channel layer is uneven; and it can also meet the requirements of the etching process.

[0041] In one possible implementation, the passivation gas includes oxygen or nitrogen.

[0042] Both oxidizing and nitriding gases can react with the channel layer and sacrificial layer to form the first protective layer. Furthermore, oxidizing and nitriding gases are readily available, relatively stable, and easy to passivate.

[0043] In one possible implementation, the first portion is removed to expose the channel layer. The second portion is then removed to form a second recess, comprising: introducing etching gas into a first protective layer while simultaneously removing the first and second portions. When removing the first and second sub-parts of the second portion, firstly, the end of the second sub-part closest to the first sub-part is removed to expose the channel layer, and a portion of the second sub-part away from the first sub-part is also removed. Then, the remaining end of the second sub-part away from the first sub-part is removed, along with a portion of the exposed channel layer, to form the first target recess.

[0044] Based on this, when forming the first sub-inner wall within the second groove, the surface of the first sub-inner wall adheres to the second groove. It can be understood that the first surface of the first sub-inner wall will adhere to the location of the channel layer with the first target recess. The first sub-inner wall fills the first target recess as a first protrusion. That is, the first surface of the first sub-inner wall has a first protrusion protruding towards the adjacent channel layer. Furthermore, the first protrusion can be used to change the morphology of the first sub-inner wall, making the surface of the first sub-inner wall near the channel layer uneven, thereby reducing the probability of etching gas forming gaps between the first sub-inner wall and the channel layer, and reducing the probability of short circuits between the gate structure and the source and drain.

[0045] In one possible implementation, the method for fabricating the semiconductor device after the second groove is formed and before the inner sidewall is formed includes cleaning the second groove.

[0046] Based on this, the remaining first protective layer from the etching process can be removed during the cleaning process, so that the first protective layer is completely removed. In addition, byproducts generated in other etching processes can also be removed, so as to facilitate the formation of inner sidewalls in the second groove.

[0047] In one possible implementation, the etching gas includes halogen-containing gases and hydrogen-reducing gases.

[0048] The sacrificial layer can be partially removed by reacting it with halogen-containing gases and hydrogen-reducing gases to form the first and second grooves. Furthermore, halogen-containing gases and hydrogen-reducing gases are readily available, thus saving costs.

[0049] In one possible implementation, the halogen-containing gas includes at least one of fluorine-based, chlorine-based, or bromine-based gases.

[0050] Any one of fluorine-based, chlorine-based, or bromine-based gases can react with the sacrificial layer to form a first and a second groove on both sides of the sacrificial layer, in combination with a hydrogen-reducing gas. Furthermore, fluorine-based, chlorine-based, or bromine-based gases are all readily available, thus saving costs. Attached Figure Description

[0051] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0052] Figure 2A is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0053] Figure 2B is a partial structural diagram of the semiconductor device in Figure 2A;

[0054] Figure 3 is a cross-sectional view along the A1-A1' direction in Figure 2A;

[0055] Figure 4 is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of this application;

[0056] Figure 5A is a schematic diagram of the fabrication process of a semiconductor device provided in an embodiment of this application;

[0057] Figure 5B is a magnified view of F1 in Figure 5A;

[0058] Figure 5C is a schematic diagram of one of the structures in the preparation process of F1 in Figure 5A;

[0059] Figure 5D is another structural schematic diagram of the F1 preparation process in Figure 5A;

[0060] Figure 6A is a second schematic diagram of the fabrication process of a semiconductor device provided in an embodiment of this application;

[0061] Figure 6B is a schematic diagram of the fabrication process of a semiconductor device provided in an embodiment of this application.

[0062] Figure 7 is a schematic diagram of the fabrication process of a semiconductor device provided in an embodiment of this application;

[0063] Figure 8A is a schematic diagram of the fabrication process of a semiconductor device provided in an embodiment of this application.

[0064] Figure 8B is a magnified view of F2 in Figure 8A;

[0065] Figure 8C is a magnified view of part F3 in Figure 3;

[0066] Figure 9 is a schematic flowchart of another semiconductor device fabrication method provided in an embodiment of this application;

[0067] Figure 10A is a schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application;

[0068] Figure 10B is a second schematic diagram of the fabrication process of another semiconductor device provided in the embodiments of this application;

[0069] Figure 10C is a schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application;

[0070] Figure 10D is a magnified view of Q1 in Figure 10C;

[0071] Figure 10E is a schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application;

[0072] Figure 10F is a magnified view of Q2 in Figure 10E;

[0073] Figure 11A is a schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application;

[0074] Figure 11B is a schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application;

[0075] Figure 12 is a cross-sectional schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application;

[0076] Figure 13A is a cross-sectional schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application;

[0077] Figure 13B is a cross-sectional schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application;

[0078] Figure 13C is a magnified view of Q3 in Figure 13B;

[0079] Figure 14A is a cross-sectional schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application;

[0080] Figure 14B is a magnified view of Q4 in Figure 14A;

[0081] Figure 15A is a cross-sectional schematic diagram eleven showing the fabrication process of another semiconductor device provided in an embodiment of this application;

[0082] Figure 15B is a magnified view of Q5 in Figure 15A.

[0083] Reference numerals: 1-Electronic device; 2-Display module; 3-Middle frame; 4-Housing; 5-Cover plate; 10-Substrate; 20-Channel layer; 21-Edge of the surface of the channel layer in contact with the sub-inner wall; 30-Gate structure; 31-Sub-section of the gate structure; 40-Source; 41-Source region; 50-Drain; 51-Drain region; 61-First sub-inner wall; 62-Second sub-inner wall; 60A-Forming the initial inner wall; W1-First surface; M1-Surface where the channel layer is attached to the first surface; W11-First surface Edge of the first surface near the gate structure; W12 - Edge of the first surface away from the gate structure; W2 - Second surface; E - Sacrificial layer; E0 - Gate channel; E1 - Small foot structure; E2 - Gap; T1 - First protrusion; G1 - Recess on the first surface; T2 - Second protrusion; T3 - Third protrusion; T4 - Fourth protrusion; G2 - Recess on the second surface; J1 - First target recess; J2 - Second target recess; J3 - Third target recess; J4 - Fourth target recess; O - Dummy gate; U - Inner wall groove; Ua - First type of inner wall groove; Ub - Second type of inner wall groove; U1 - First groove; U2 - Second groove; U2a - First type of second groove; U2b - Second type of second groove; L1 - First center line; L2 - Second center line; V1 - First protective layer; V11 - First part; V12 - Second part; V121 - First sub-part; V122 - Second sub-part; d1 - Minimum distance between the most prominent point of the first protrusion and the second center line; d2 - First surface near the gate structure d3 - Minimum spacing between the edge and the second centerline; d4 - Minimum distance between the surface of the sub-section of the gate structure in contact with the channel layer and its centerline; d5 - Minimum spacing between the edge of the first surface away from the gate structure and the second centerline of the first sub-inner wall; d6 - Minimum spacing between the edge of the channel layer and the extension of the second centerline of its adjacent first sub-inner wall; X - First direction; Z - Second direction; Y - Third direction; 100 - Semiconductor device. Detailed Implementation

[0084] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0085] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0086] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0087] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0088] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0089] This application provides an electronic device that can be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device (e.g., smartwatch, smart bracelet, pedometer, etc.), in-vehicle device (e.g., car, bicycle, electric vehicle, airplane, ship, train, high-speed rail, etc.), virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, smart home device (e.g., refrigerator, television, air conditioner, electricity meter, etc.), intelligent robot, workshop equipment, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, or wireless terminal in smart home, or flying device (e.g., intelligent robot, hot air balloon, drone, airplane), etc. This application does not impose any special limitations on the specific form of the above-mentioned electronic device.

[0090] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0091] In this case, as shown in Figure 1, the electronic device 1 mainly includes a display module 2, a middle frame 3, a housing (or battery cover, back cover) 4, and a cover plate 5.

[0092] The display module 2 has a light-emitting side from which the display image can be seen and a back side opposite to the light-emitting side. The back side of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.

[0093] The aforementioned display module 2 includes a display panel (DP).

[0094] In one possible embodiment of this application, the display module 2 is a liquid crystal display module. In this case, the aforementioned display screen is a liquid crystal display (LCD). Based on this, the display module 2 also includes a backlight unit (BLU) located on the back of the LCD (away from the side surface of the LCD used to display images).

[0095] The backlight module provides a light source to the LCD screen, enabling each sub-pixel in the LCD screen to emit light and display an image.

[0096] Alternatively, in another possible embodiment of this application, display module 2 is an organic light-emitting diode (OLED) display module. In this case, the aforementioned display screen is an organic light-emitting diode (OLED) display screen. Since each subpixel in an OLED display screen has an electroluminescent layer, the OLED display screen can achieve self-illumination after receiving an operating voltage. In this case, the aforementioned backlight module is not required in display module 2 with an OLED display screen.

[0097] The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, a cover glass (CG), which can have a certain degree of toughness.

[0098] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to mount internal components such as batteries, printed circuit boards (PCBs), cameras, and antennas. After the housing 4 is closed with the middle frame 3, the aforementioned internal components are located between the housing 4 and the middle frame 3.

[0099] The aforementioned electronic device 1 also includes semiconductor devices 100 such as a center processing unit (CPU) chip, a dynamic random access memory (DRAM) chip, a radio frequency chip, a radio frequency power amplifier (PA) chip, and a system on a chip (SOC) disposed on a PCB. The PCB is used to carry the aforementioned semiconductor devices 100 and to connect with the aforementioned semiconductor devices 100 to complete signal interaction.

[0100] In some embodiments, the semiconductor device 100 includes any one of a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (Fin FET), or a gate all around field-effect transistor (GAA FET).

[0101] Among them, GAA FET is a new type of semiconductor device with a gate-all-around structure, which is developed based on Fin FET. The gate structure in GAA FET can surround the area where the channel layer is located from all four sides. Compared with Fin FET, the gate structure of GAA FET extends the control of the channel layer from three sides to four sides, which greatly improves the control capability of the gate structure and can better suppress the short-channel effect. Therefore, it is widely used in semiconductor devices 100.

[0102] Figure 2A is a schematic diagram of a semiconductor device provided in an embodiment of this application, and Figure 2B is a partial structural diagram of the semiconductor device in Figure 2A. The difference between Figure 2B and Figure 2A is that the source 40 and drain 50 are not shown in Figure 2B. Therefore, Figure 2B can illustrate the channel layer 20 that is blocked by the source 40 and drain 50 in Figure 2A.

[0103] This application provides a semiconductor device 100. The semiconductor device 100 includes a GAA FET. For example, as shown in Figures 2A and 2B, the GAA FET includes a substrate 10, and a plurality of channel layers 20, a gate structure 30, a source 40, and a drain 50 located on the same side of the substrate 10.

[0104] For example, the material of substrate 10 includes semiconductor materials. For instance, the material of substrate 10 includes any one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), and silicon germanium-on-insulator (SGOI).

[0105] For example, the material of the channel layer 20 includes silicon (Si). Of course, the material of the channel layer 20 provided in the embodiments of this application is not limited thereto.

[0106] A gate structure 30 is located between the source 40 and the drain 50. Multiple channel layers 20 are located within the gate structure 30, surrounding each channel layer 20. Along the first direction (the length direction of the gate structure 30) X, each channel layer 20 penetrates the gate structure 30, and its two ends are connected to the source 40 and the drain 50, respectively. The multiple channel layers 20 are spaced apart along the second direction (the thickness direction of the substrate 10) Z.

[0107] Figure 3 is a cross-sectional view along the A1-A1' direction in Figure 2A.

[0108] For example, as shown in FIG3, the source 40 is located to the left of the gate structure 30 at the middle position, and the drain 50 is located to the right of the gate structure 30 at the middle position. In other examples, the drain 50 may be located to the left of the gate structure 30 at the middle position, and the source 40 may be located to the right of the gate structure 30 at the middle position.

[0109] For example, as shown in Figure 3, the number of channel layers 20 is three. However, the embodiments of this application do not specifically limit the number of channel layers 20, and Figure 3 is only an example.

[0110] By having the gate structure 30 surround the surface of each channel layer 20 in the multilayer channel layer 20, the control capability of the gate structure 30 over the channels in the channel layer 20 can be effectively improved, thereby enhancing the electrical performance of the semiconductor device 100.

[0111] As shown in Figure 3, the semiconductor device 100 also includes an inner sidewall 60. The inner sidewall 60 includes a plurality of first sub-inner sidewalls 61. The plurality of first sub-inner sidewalls 61 are respectively disposed between adjacent channel layers 20, and the plurality of first sub-inner sidewalls 61 are located on both sides of the gate structure 30. The first sub-inner sidewalls 61 are used to isolate the source 40, drain 50 and gate structure 30.

[0112] The gaps between adjacent channel layers 20 are filled with first sub-inner walls 61, which can be used to support the channel layers 20, thereby improving the problem that the channel layers 20 are prone to collapse before the gate structure 30 is formed.

[0113] Furthermore, a first sub-inner wall 61 is filled within the gap formed by the two adjacent channel layers 20 and the source 40. This is equivalent to setting a first sub-inner wall 61 between the gate structure 30 and the source 40, which can isolate the gate structure 30 and the source 40, reducing the probability of a short circuit between them. Similarly, filling the gap formed by the two adjacent channel layers 20 and the drain 50 with a first sub-inner wall 61 is equivalent to setting a first sub-inner wall 61 between the gate structure 30 and the drain 50, which can isolate the gate structure 30 and the drain 50, further reducing the probability of a short circuit between them. Therefore, this improves the reliability of the semiconductor device 100.

[0114] For example, the inner wall 60 also includes a plurality of second sub-inner walls 62, which are disposed between the adjacent channel layer 20 and the substrate 10, and are located on both sides of the gate structure 30. The plurality of second sub-inner walls 62 are used to isolate the source 40, drain 50 and gate structure 30.

[0115] The gap between the channel layer 20 adjacent to the substrate 10 and the substrate 10 is filled with a second sub-inner wall 62. The second sub-inner wall 62 can be used to support the channel layer 20, thereby improving the problem that the channel layer 20 is prone to collapse before the gate structure 30 is formed.

[0116] Furthermore, a second sub-inner wall 62 is filled in the gap enclosed by the adjacent substrate 10, channel layer 20 and source 40, which is equivalent to setting a second sub-inner wall 62 between the gate structure 30 and the source 40. The second sub-inner wall 62 can be used to isolate the gate structure 30 and the source 40, reducing the probability of short circuit between the gate structure 30 and the source 40.

[0117] Furthermore, a second sub-inner wall 62 is filled within the gap formed by the substrate 10, the channel layer 20, and the drain 50. This is equivalent to setting a second sub-inner wall 62 between the gate structure 30 and the drain 50. The second sub-inner wall 62 can be used to isolate the gate structure 30 and the drain 50, reducing the probability of short circuits between them. Therefore, it is beneficial to improve the reliability of the semiconductor device 100.

[0118] Figure 4 is a schematic flowchart of a semiconductor device fabrication method according to an embodiment of this application. Figures 5A to 8C are schematic structural diagrams of a semiconductor device fabrication process according to an embodiment of this application.

[0119] This application provides a method for fabricating a semiconductor device, which can be used to fabricate the aforementioned semiconductor device 100. As shown in Figure 4, the method for fabricating the semiconductor device includes:

[0120] S11: As shown in Figure 5A, an alternating sacrificial layer E and channel layer 20, as well as a source region 41 and a drain region 51 are formed.

[0121] For example, an overlapping sacrificial layer E and a channel layer 20, as well as a source region 41 and a drain region 51 are formed on one side of the substrate 10.

[0122] For example, a dummy gate stack O is formed on the side of the channel layer 20 furthest from the substrate 10 among the multiple channel layers 20. The dummy gate stack O is used as a mask to etch the stack consisting of the channel layer 20 and the sacrificial layer E to remove the structure of the stack not covered by the dummy gate stack O, so as to form the source region 41 and the drain region 51.

[0123] After the source region 41 and the drain region 51 are formed in step S11, an inner wall groove U is formed on both sides of the sacrificial layer E facing the source region 41 and the drain region 51 along the first direction X.

[0124] Based on this, the formed plurality of inner wall grooves U can include a first type of inner wall groove Ua and a second type of inner wall groove Ub. The first type of inner wall groove Ua can be understood as the space enclosed by two adjacent channel layers 20 and the sacrificial layer E located between the two adjacent channel layers 20. The second type of inner wall groove Ub can be understood as the space enclosed by the channel layer 20 adjacent to the substrate 10, the substrate 10, and the sacrificial layer E located between the channel layer 20 and the substrate 10. Alternatively, it can be understood that the bottom of the inner wall groove U can be the side surface of the sacrificial layer E, and the wall of the inner wall groove U can be the surface of the channel layer 20.

[0125] For example, the opening of the inner wall groove U adjacent to the source region 41 faces the source region 41, and the opening of the inner wall groove U adjacent to the drain region 51 faces the drain region 51.

[0126] For example, by means of etching, the sacrificial layer E is etched along the source region 41 to the side facing the source region 41 to form the inner sidewall groove U, and the sacrificial layer E is etched along the drain region 51 to the side facing the drain region 51 to form the inner sidewall groove U.

[0127] For example, as shown in FIG5B, the bottom of the inner wall groove U may include an arc-shaped bottom. For instance, the sacrificial layer E includes a first centerline L1 extending along a first direction X. The portion of the inner wall groove U closer to the first centerline L1 of the sacrificial layer E is recessed further into the sacrificial layer E. However, the structure of the inner wall groove U in this embodiment is not limited thereto. FIG5B is merely an example.

[0128] Based on the structure of the inner wall groove U, there will be residue (SiGe residue) at the boundary of both sides of the sacrificial layer E. This residue can also be referred to in the art as the footing / rounding structure E1.

[0129] For example, the reasons for forming the small foot structure E1 described above may include the following three situations.

[0130] The first scenario involves a lack of a stop layer within the sacrificial layer E. During etching of the sacrificial layer E, it is impossible to completely remove the residue at the boundaries on both sides of the sacrificial layer E. This results in the formation of a small-foot structure E1 during the etching of the sacrificial layer E.

[0131] For example, the material of the stop layer includes materials that will not be etched.

[0132] The second scenario, as shown in Figure 5C, involves the dielectric of the sacrificial layer E (e.g., SiGe) diffusing into the channel layer 20 (e.g., Si) in contact with it. This results in the formation of a transition layer C1 at the surface where the channel layer 20 contacts the sacrificial layer E. The presence of the transition layer C1 reduces the selectivity between the sacrificial layer E and the channel layer 20, thereby affecting the etching rate of the sacrificial layer E and causing a small-leg structure E1 to form during etching of the sacrificial layer E.

[0133] For example, the transition layer C1 is composed of a portion of the channel layer 20 and a portion of the sacrificial layer E.

[0134] The third scenario, as shown in Figure 5D, involves selective etching of the sacrificial layer E and the channel layer 20. The etching gas exhibits a strong boundary transfer effect at the junction of the sacrificial layer E and the channel layer 20. Consequently, the etching efficiency of the etching gas on the side of the sacrificial layer E near the channel layer 20 is lower than that on the side of the sacrificial layer E away from the channel layer 20. Therefore, etching the sacrificial layer E results in the formation of a small-foot structure E1 within the sacrificial layer E.

[0135] Regardless of the reason or combination thereof, a small-leg structure E1 will be generated during the etching of the sacrificial layer E. The presence of the small-leg structure E1 will affect the structure of the subsequently formed inner sidewall 60 and gate structure 30, thus affecting the electrical performance of the semiconductor device 100. How it affects the electrical performance of the semiconductor device 100 will be explained below.

[0136] S12: Form an inner wall 60.

[0137] An inner wall 60 is formed on one side of the base 10, and the inner wall 60 is formed on the same side of the base 10 as the sacrificial layer E and the channel layer 20.

[0138] For example, step S12 includes: S121: As shown in FIG6A, an initial inner wall 60A is formed in the source region 41 and the drain region 51, the initial inner wall 60A covering the side of the channel layer 20 and the sacrificial layer E facing the source region 41 and the drain region 51.

[0139] S122: As shown in Figure 6B, the initial inner wall 60A is etched to remove the portion of the initial inner wall 60A located in the source region 41 and the drain region 51, exposing the source region 41 and the drain region 51; the portion of the initial inner wall 60A located in the first type of inner wall groove Ua is retained to form the first sub-inner wall 61, and the portion of the initial inner wall 60A located in the second type of inner wall groove Ub is retained to form the second sub-inner wall 62.

[0140] S13: As shown in Figure 7, a source 40 is formed in the source region 41 and a drain 50 is formed in the drain region 51.

[0141] S14: Form gate structure 30.

[0142] A gate structure 30 is formed on one side of the substrate 10, and the gate structure 30 is formed on the same side of the substrate 10 as the sacrificial layer E and the channel layer 20.

[0143] For example, step S14 includes: S141: As shown in Figures 8A and 8B, removing the sacrificial layer E to form the gate channel E0.

[0144] For example, the sacrificial layer E can be removed using a channel release process to form the gate channel E0. During the channel release process, an ultra-high selectivity etching technique is used. Therefore, during the channel release process, the ultra-high selectivity reactants used will not react with the channel layer 20, source 40, and drain 50; instead, the reactants can react with the sacrificial layer E to remove it.

[0145] Due to the requirements of subsequent processes and electrical properties of the semiconductor device 100, a certain amount of over-etching occurs during the channel release process to prevent some sacrificial layer E from being completely removed, thus facilitating the flattening of the gate channel E0. The reactants in the over-etching stage have high concentrations and strong diffusion, which can cause chaotic collisions within the gate channel E0, potentially invading the small lead structure E1 (as shown in Figure 5B). Therefore, the small lead structure E1 is completely removed during the over-etching stage, resulting in a gap E2 extending along the first direction X between the first sub-inner wall 61 and its adjacent channel layer 20. Alternatively, a gap extending along the first direction X can be formed between the second sub-inner wall 62 and its adjacent substrate 10 and channel layer 20. Furthermore, because the gap E2 extends along the first direction X, the etchant will continue to propagate along the gap E2 towards the source 40 and drain 50, exposing or even damaging the source 40 and drain 50, affecting the electrical performance of the semiconductor device 100.

[0146] S142: As shown in Figure 8C, a gate structure 30 is formed in the gate channel E0.

[0147] The gate structure 30 is disposed around the surface of each channel layer 20 in the multilayer channel layer 20, which can enhance the control of the current in the channel layer 20 by the gate structure 30, which helps to reduce the short-channel effect and thus improve the electrical performance of the semiconductor device 100.

[0148] However, due to the gap E2 formed in step S15, the gate structure 30 is formed in step S16, and a portion of the gate structure 30 will fill the gap E2, which is commonly referred to in the art as metal gate extrusion (MGEX). The portion of the gate structure 30 located in the gap E2 will contact and connect with the source 40 and the drain 50, resulting in a short circuit between the gate structure 30 and the source 40 and drain 50.

[0149] The presence of the small-leg structure E1 directly affects the morphology of the first sub-inner wall 61 and the second sub-inner wall 62, thus causing the formation of a gap E2 when the sacrificial layer E is removed. Since the gate structure 30 is formed in the gate channel E0 vacated by removing the sacrificial layer E, part of the gate structure 30 will fill the gap E2, leading to a short circuit between the gate structure 30 and the source 40 and drain 50, thus reducing the electrical performance of the semiconductor device 100.

[0150] Figure 9 is a schematic flowchart of another semiconductor device fabrication method provided in the embodiments of this application. Figures 10A to 15B are schematic structural diagrams of another semiconductor device fabrication process provided in the embodiments of this application.

[0151] Some embodiments of this application provide another method for fabricating a semiconductor device, as shown in FIG9. The method for fabricating a semiconductor device includes:

[0152] S21: As shown in Figure 10A, multiple channel layers 20 and multiple sacrificial layers E are formed.

[0153] Along the second direction Z, multiple channel layers 20 and multiple sacrificial layers E are alternately arranged.

[0154] For example, step S21 includes: S211: forming an alternately stacked sacrificial film E' and channel film 20' on one side of the substrate 10, processing the stacked structure formed by the sacrificial film E' and channel film 20', removing part of the stacked structure formed by the sacrificial film E' and channel film 20' to form the source region 41 and the drain region 51, and the remaining stacked structure formed by the sacrificial film E' and channel film 20' can be understood as an alternately stacked sacrificial layer E and channel layer 20.

[0155] For example, the material of the sacrificial layer E includes germanium silicon (GeSi), and the material of the channel layer 20 includes silicon (Si).

[0156] S212: Along the first direction X, a second groove U2 is formed on both sides of the sacrificial layer E. The first groove wall U21 that contacts the channel layer 20 is uneven.

[0157] Step S212 includes: S2121: As shown in FIG10B, a first groove U1 is formed on both sides of the sacrificial layer E along the first direction X. The opening of the first groove U1 faces the source region 41 or the drain region 51. For example, the opening of the first groove U1 adjacent to the source region 41 faces the source region 41, and the opening of the first groove U1 adjacent to the drain region 51 faces the drain region 51.

[0158] For example, the bottom of the first groove U1 may include an arc-shaped bottom. Along the first direction X, the depth of the first groove U1 is less than the depth of the inner wall groove U (as shown in Figure 6B). The structure of the first groove U1 is similar to the structure of the inner wall groove U.

[0159] For example, by utilizing the high selectivity of the sacrificial layer E and the channel layer 20, a first groove U1 is formed on both sides of the sacrificial layer E facing the source region 41 and the drain region 51 by selective etching.

[0160] For example, etching gas is introduced into both sides of the sacrificial layer E toward the source region 41 and the drain region 51, and the two sides of the sacrificial layer E are etched to form the first groove U1.

[0161] In some examples, the etching gas used in step S2121 is, for example, a halogen-containing gas and a hydrogen-reducing gas.

[0162] The sacrificial layer E can be partially removed by reacting it with a halogen-containing gas and a hydrogen-reducing gas to form the first groove U1. Furthermore, the halogen-containing gas and the hydrogen-reducing gas are readily available, thus saving costs.

[0163] For example, the halogen-containing gas includes at least one of fluorine-based gas, chlorine-based gas, or bromine-based gas.

[0164] Any one of the following gases—fluorine-based, chlorine-based, or bromine-based—can react with the sacrificial layer E to form the first groove U1 on both sides of the sacrificial layer E in combination with a hydrogen-reducing gas. Furthermore, fluorine-based, chlorine-based, or bromine-based gases are all readily available, thus saving costs.

[0165] For example, a hydrogen-reducing gas includes at least one of hydrogen (H2) and ammonia (NH3).

[0166] In some examples, in step S2121, auxiliary gases can also be used to enhance plasma stability, increase the degree of compound dissociation, make reactants more uniformly distributed in local areas, and facilitate the removal of byproducts more rapidly, thereby assisting the etching process and improving etching efficiency.

[0167] For example, the auxiliary gas may include at least one of oxygen (O2), helium (He) or argon (Ar).

[0168] S2122: As shown in Figures 10C and 10D, the channel layer 20 and the first groove U1 are passivated to form a first protective layer V1. The first protective layer V1 includes a first part V11 and a second part V12. The first part V11 is located on the side of the channel layer 20, and the second part V12 is located in the first groove U1.

[0169] In some examples, the channel layer 20 and the first groove U1 are passivated on both sides facing the source region 41 and the drain region 51 to form a first protective layer V1 on the sides of the channel layer 20 facing the source region 41 and the drain region 51 and the surface of the first groove U1 facing the source region 41 and the drain region 51.

[0170] In some examples, passivation gas can be introduced into the channel layer 20 and the first groove U1 on both sides toward the source region 41 and the drain region 51. The passivation gas reacts with the channel layer 20 to form a first portion V11 with a first thickness, and the passivation gas reacts with the first groove U1 to form a second portion V12 with a second thickness.

[0171] When passivating gas is introduced into the channel layer 20 and the first groove U1, due to the principle of molecular diffusion, the concentration of passivating gas at the outer position of the channel layer 20 is higher than the concentration of passivating gas at the inner position of the first groove U1. Therefore, the first thickness of the first portion V11 formed on the side of the channel layer 20 is greater than the second thickness of the second portion V12 formed on the surface of the first groove U1.

[0172] For example, the first thickness being greater than the second thickness can be understood as the average thickness of the first part V11 being greater than the average thickness of the second part V12.

[0173] For example, the first thickness being greater than the second thickness can be understood as the minimum thickness of the first part V11 being greater than the maximum thickness of the second part V12.

[0174] In some examples, the second portion V12 may include a first sub-part V121 and a second sub-part V122. The second sub-part V122 is in contact with the sacrificial layer E. Alternatively, it can be understood that the second sub-part V122 is located between the first sub-part V121 and the sacrificial layer E.

[0175] When passivating gas is introduced into the first groove U1, due to the principle of molecular diffusion, the passivating gas concentration at the outer first sub-section V121 is higher than that at the inner second sub-section V122. Therefore, the thickness of the first sub-section V121 is greater than the thickness of the second sub-section V122.

[0176] For example, the thickness of the first sub-part V121 is greater than the thickness of the second sub-part V122. This can be understood as the average thickness of the first sub-part V121 being greater than the average thickness of the second sub-part V122.

[0177] For example, the thickness of the first sub-part V121 is greater than the thickness of the second sub-part V122. This can be understood as the minimum thickness of the first sub-part V121 being greater than the maximum thickness of the second sub-part V122.

[0178] The contact between the second sub-part V122 and the sacrificial layer E can include the following two cases.

[0179] The first type: The second sub-section V122 completely covers the surface of the sacrificial layer E facing the source region 41 and the drain region 51. Alternatively, it can be understood that the boundary between the first sub-section V121 and the second sub-section V122 can roughly coincide with the boundary between the sacrificial layer E and the channel layer 20.

[0180] The second type: The second sub-part V122 not only includes the portion in contact with the sacrificial layer E, but also includes the portion that adheres to the channel layer 20. Alternatively, it can be understood that the second sub-part V122 completely covers the surface of the sacrificial layer E facing the source region 41 and the drain region 51, and the second sub-part V122 extends outward to the channel layer 20.

[0181] However, this application embodiment does not specifically limit the boundary between the first sub-part V121 and the second sub-part V122. It is acceptable as long as the boundary between the first sub-part V121 and the second sub-part V122 is located at the boundary between the sacrificial layer E and the channel layer 20, or the boundary between the first sub-part V121 and the second sub-part V122 extends beyond the channel layer 20. This prevents the residual sacrificial layer between the second groove U2 and the channel layer 20 due to the thickness difference between the first sub-part V121 and the second sub-part V122, which could affect the structure and electrical performance of the subsequent semiconductor device 100.

[0182] In some examples, the passivation gas may include an oxidizing gas or a nitriding gas.

[0183] Both oxidizing and nitriding gases can react with the channel layer 20 and the sacrificial layer E to form the first protective layer V1. Furthermore, oxidizing and nitriding gases are readily available, relatively stable, and easy to passivate.

[0184] For example, oxidizing gases include oxygen (O2) or ozone (O3). However, the embodiments of this application are not limited to oxidizing gases; oxygen and ozone are merely illustrative examples, and other oxygen-containing gases may also be applicable.

[0185] For example, nitriding gases include nitrogen (N2). However, the embodiments of this application are not limited to nitriding gases; nitrogen is merely an illustration, and other nitrogen-containing gases may also be applied.

[0186] S2123: As shown in Figures 10E and 10F, the first portion V11 is removed to expose the channel layer 20. The second portion V12 is removed to form the second groove U2. The first groove wall U21, which contacts the channel layer 20, is uneven.

[0187] Based on this, the multiple second grooves U2 formed can include a first type of second groove U2a. The first type of second groove U2a can be understood as the space enclosed by two adjacent channel layers 20 and the sacrificial layer E located between the two adjacent channel layers 20. Alternatively, it can be understood that the bottom of the second groove U2 can be the side of the sacrificial layer E, and the wall of the second groove U2 can be the surface of the channel layer 20.

[0188] Remove the first portion V11 of the first protective layer V1 located on the side of the channel layer 20, exposing the side of the channel layer 20 facing the source region 41 and the drain region 51. This facilitates the direct contact and connection of the source 40 and drain 50 with the side of the channel layer 20 during subsequent formation. Remove the second portion V2 of the first protective layer V1 located on the first groove U1, exposing the first groove U1. This allows for subsequent modification of the morphology of the first groove U1 to form the second groove U2.

[0189] For example, an etching method is used to introduce an etching gas into the first protective layer V1. The etching gas reacts with the first part V11 and the second part V12 of the first protective layer V1, and simultaneously removes the first part V11 and the second part V12 of the first protective layer V1.

[0190] By setting the first thickness of the first portion V11 to be greater than the second thickness of the second portion V12, the problem of the etching gas having a higher etching rate on the outer part of the first portion V11 than on the inner part of the second portion V12 due to the loading effect (etching effect) can be compensated for. This reduces the difference in time required for the first portion V11 and the second portion V12 to be completely etched. Consequently, the probability of the etching gas damaging the sides of the channel layer 20 facing the source region 41 and the drain region 51 when the first portion V11 is completely removed is reduced. This is beneficial for improving the electrical performance of the semiconductor device 100.

[0191] In some examples, the thickness of the first part V11 ranges from 0.5 nm to 10 nm.

[0192] For example, the thickness of the first portion V11 is approximately any one of 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, 8.5nm, 9nm, 9.5nm, and 10nm. However, the embodiments of this application do not limit the thickness of the first portion V11 to this.

[0193] When the thickness of the first portion V11 is less than 0.5 nm, it is too thin to effectively protect the channel layer 20, increasing the likelihood of damage during etching. When the thickness of the first portion V11 is greater than 10 nm, it is too thick, requiring a longer etching time. After the etching process, there is a possibility that the first portion V11 may not be completely removed, affecting the contact between the source 40 and drain 50 and the channel layer 20.

[0194] It is understandable that the example given is that the thickness of the first part V11 is approximately 5nm. Due to certain uncontrollable errors (such as manufacturing process errors, equipment precision, measurement errors, etc.), the error range of the thickness of the first part V11 is within 5% × 5nm. That is, when the thickness of the first part V11 fluctuates within the range of 5 ± 0.25nm, it can be considered that the thickness of the first part V11 meets the condition of being equal to 5nm.

[0195] It should be noted that the simultaneous removal of the first part V11 and the second part V12 of the first protective layer V1 can be understood as the removal of the first part V11 and the second part V12 in the same process.

[0196] For example, the materials of the first portion V11 and the second portion V12 are different. Based on the difference in material properties between the first portion V11 and the second portion V12, the etching process can be adjusted to change the etch selectivity ratio of the sacrificial layer E and the channel layer 20, thereby removing the first portion V11 and exposing the channel layer 20. The second portion V12 is then removed to form the second groove U2.

[0197] In some examples, an etching method is used to introduce an etching gas into the first protective layer V1. The etching gas reacts with the first sub-part V121 and the second sub-part V122 of the second part V12, and the first sub-part V121 and the second sub-part V122 are removed simultaneously.

[0198] When removing the first sub-part V121 and the second sub-part V122 of the second part V12, first remove the end of the second sub-part V122 close to the first sub-part V121 to expose the channel layer 20, and remove part of the end of the second sub-part V122 away from the first sub-part V121; then remove the remaining end of the second sub-part V122 away from the first sub-part V121, and remove part of the exposed channel layer 20, so that the corresponding surface M1 of the channel layer 20 is uneven.

[0199] Because the thickness of the second sub-section V122 is less than the thickness of the first sub-section V121, the second sub-section V122 will be completely removed before the first sub-section V121. Furthermore, due to the loading effect (etching effect), the etching rate of the etching gas on the outer end of the second sub-section V122 near the first sub-section V121 is greater than the etching rate on the inner end of the second sub-section V122 away from the first sub-section V121.

[0200] Based on this, the end of the second sub-part V122 closest to the first sub-part V121, and the end of the second sub-part V122 furthest from the first sub-part V121, will be completely removed first. Then, the etching gas will continue to etch the channel layer 20 at the corresponding position of the end of the second sub-part V122 closest to the first sub-part V121, removing this portion of the channel layer 20 and making the corresponding surface M1 of the channel layer 20 uneven. In other words, the first groove wall U21 that contacts the channel layer 20 in the second groove U2 is uneven.

[0201] For example, the simultaneous removal of the first sub-part V121 and the second sub-part V122 can be understood as the removal of the first sub-part V121 and the second sub-part V122 in the same process.

[0202] In some examples, the thickness of the second part V12 ranges from 0.1 nm to 5 nm.

[0203] For example, the thickness of the second portion V12 is approximately any one of 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, and 5nm. However, the embodiments of this application do not limit the thickness of the second portion V12 to this.

[0204] When the thickness of the second portion V12 is less than 0.5 nm, its thinness results in a small thickness difference between the first sub-part V121 and the second sub-part V122 within the second portion V12. This makes it difficult for the end of the second sub-part V122 closest to the first sub-part V121 to be removed before the rest of the second sub-part V122, thus failing to expose part of the channel layer 20 and preventing the corresponding surface M1 of the channel layer 20 from becoming uneven. When the thickness of the second portion V12 is greater than 5 nm, its thickness is too large, requiring a longer etching time. Furthermore, excessive etching of the channel layer 20 may affect its performance, thereby impacting the electrical performance of the semiconductor device 100.

[0205] It is understandable that the example given is that the thickness of the second part, V12, is approximately 2 nm. Due to certain uncontrollable errors (such as manufacturing process errors, equipment precision, measurement errors, etc.), the thickness of the second part, V12, may fluctuate within the range of 5% × 2 nm. That is, when the thickness of the second part, V12, fluctuates within the range of 2 ± 0.25 nm, it can be considered that the thickness of the second part, V12, satisfies the condition of being equal to 2 nm.

[0206] In some examples, in step S2123, etching gas can be introduced into the first protective layer V1 to remove the first protective layer V1 by selective etching, thereby converting the first groove U1 into the second groove U2.

[0207] For example, the etching gas used in step S2123 may include a halogen-containing gas and a hydrogen-reducing gas.

[0208] The sacrificial layer E can be partially removed by reacting it with a halogen-containing gas and a hydrogen-reducing gas to form the second groove U2. Furthermore, the halogen-containing gas and the hydrogen-reducing gas are readily available, thus saving costs.

[0209] For example, the ratio of hydrogen-reducing gas to halogen-containing gas in the etching gas used in step S2123 is greater than the ratio of hydrogen-reducing gas to halogen-containing gas in the etching gas used in step S2121.

[0210] Based on this, the material of the first protective layer V1 can be better matched, so as to remove the first protective layer V1, expose the channel layer 20, and form the second groove U2.

[0211] For example, gases containing halogen elements may include at least one of fluorine-based gases, chlorine-based gases, or bromine-based gases.

[0212] Any one of the following gases—fluorine-based, chlorine-based, or bromine-based—can react with the sacrificial layer E to form a second groove U2 on both sides of the sacrificial layer E in combination with a hydrogen-reducing gas. Furthermore, fluorine-based, chlorine-based, or bromine-based gases are all readily available, thus saving costs.

[0213] For example, a hydrogen-reducing gas may include at least one of hydrogen (H2) and ammonia (NH3).

[0214] In some examples, step S2123 may also use auxiliary gases to enhance plasma stability, increase the degree of compound dissociation, make reactants more uniformly distributed in local areas, and facilitate the removal of byproducts more rapidly, thereby assisting the etching process.

[0215] For example, the auxiliary gas is at least one of oxygen (O2), helium (He), or argon (Ar). In step S2123, oxygen (O2), helium (He), or argon (Ar) can be used to improve etching efficiency.

[0216] For example, along the first direction X, the groove depth of the second groove U2 is approximately equal to the groove depth of the inner wall groove U (as shown in Figure 6B).

[0217] In some examples, the second groove U2 is cleaned after it is formed.

[0218] Based on this, the remaining first protective layer V1 from the etching process can be removed during the cleaning process, so that the first protective layer V1 can be completely removed. In addition, byproducts generated in other etching processes can also be removed, so as to facilitate the formation of inner sidewalls in the second groove U2.

[0219] For example, the second groove U2 can be cleaned using a wet method. However, the cleaning method for the second groove U2 in this embodiment is not limited to this.

[0220] In some embodiments, the above steps S2121, S2122 and S2123 can be operated in one machine without changing the semiconductor device 100, thus not increasing the fabrication difficulty when performing secondary processing on the sacrificial layer E to form the second groove U2, which is easy to implement.

[0221] S22: Form an inner wall 60.

[0222] An inner wall 60 is formed on one side of the substrate 10, and the inner wall 60 and the channel layer 20 are located on the same side of the substrate 10. The inner wall 60 includes a plurality of first sub-inner walls 61, which are located between adjacent channel layers 20 and on both sides of the sacrificial layer E. The first sub-inner walls 61 have uneven first surfaces W1 that respectively conform to the channel layers 20 on both sides.

[0223] For example, the first surface W1 can be the entire surface of the first sub-inner wall 61 adjacent to the trench layer 20. Alternatively, the first surface W1 can also be a portion of the surface of the first sub-inner wall 61 adjacent to the trench layer 20.

[0224] The dimensions of the first surface W1 of the first sub-inner wall 61 are not limited to this in the embodiments of this application. As long as at least a portion of the surface of the first sub-inner wall 61 near the channel layer 20 is in contact with the channel layer 20, the first sub-inner wall 61 can be used to isolate the gate structure 30 from the source 40 and drain 50, so as to prevent the gate structure 30 from being short-circuited with the source 40 and drain 50, and to ensure the electrical performance of the semiconductor device 100.

[0225] For example, a portion of the surface of the first sub-inner wall 61 near the channel layer 20 is a first surface W1 that contacts the channel layer 20, and another portion of the surface of the first sub-inner wall 61 near the channel layer 20 can be the remaining surface, which may not be in contact with the channel layer 20. Alternatively, it can be understood that a gap may be formed between the remaining surface and the channel layer 20. However, since the first surface W1 is in contact with the channel layer 20, the first surface W1 can be used to cut off the gap between the remaining surface and the channel layer 20, thereby preventing the gate structure 30 from connecting to the source 40 and the drain 50 through the gap between the remaining surface and the channel layer 20.

[0226] For example, step S22 includes: S221: As shown in FIG11A, an initial inner wall 60A is formed in the source region 41 and the drain region 51, the initial inner wall 60A covering the side of the channel layer 20 and the sacrificial layer E facing the source region 41 and the drain region 51.

[0227] For example, since the opening of the second groove U2 adjacent to the source region 41 faces the source region 41, this portion of the second groove U2 is connected to the source region 41. Therefore, when the initial inner wall 60A is formed in the source region 41, the initial inner wall 60A also fills into the second groove U2. Furthermore, since the opening of the second groove U2 adjacent to the drain region 51 faces the drain region 51, this portion of the second groove U2 is connected to the drain region 51. Therefore, when the initial inner wall 60A is formed in the drain region 51, the initial inner wall 60A also fills into the second groove U2.

[0228] For example, when the first groove wall U21 is uneven, after the initial inner wall 60A fills into the second groove U2, the first surface of the initial inner wall 60A that is in contact with the channel layers 20 on both sides is uneven.

[0229] S222: As shown in Figures 11A and 11B, the initial inner wall 60A is etched to remove the portion of the initial inner wall 60A located in the source region 41, exposing the source region 41; the portion of the initial inner wall 60A located in the drain region 51 is removed, exposing the drain region 51; the portion of the initial inner wall 60A located in the second groove U2 is retained.

[0230] Removing the portion of the initial inner wall 60A located in the source region 41 is equivalent to removing the portion of the initial inner wall 60A located on the side of the channel layer 20 facing the source region 41, exposing the side of the channel layer 20 facing the source region 41. Similarly, removing the portion of the initial inner wall 60A located in the drain region 51 is equivalent to removing the portion of the initial inner wall 60A located on the side of the channel layer 20 facing the drain region 51, exposing the side of the channel layer 20 facing the drain region 51.

[0231] Based on this, the two sides of the channel layer 20 facing the source region 41 and the drain region 51 can be exposed, which makes it easier for the source 40 and drain 50 to be directly connected to the two sides of the channel layer 20 when the source 40 and drain 50 are formed.

[0232] For example, the side of the first sub-inner wall 61 facing the source region 41 is substantially parallel to the side of the channel layer 20 facing the source region 41, and the side of the first sub-inner wall 61 facing the drain region 51 is substantially parallel to the side of the channel layer 20 facing the drain region 51.

[0233] For example, the side of the first sub-inner wall 61 facing the source region 41 is recessed relative to the side of the channel layer 20 facing the source region 41, and the side of the first sub-inner wall 61 facing the drain region 51 is recessed relative to the side of the channel layer 20 facing the drain region 51.

[0234] In this case, the portion of the initial inner wall 60A located on the two sides of the channel layer 20 facing the source region 41 and the drain region 50 can be completely removed, exposing the two sides of the channel layer 20 facing the source region 41 and the drain region 51, which facilitates the subsequent direct connection of the source 40 and the drain 50 to the sides of the channel layer 20.

[0235] As shown in Figure 11B, the portion of the initial inner wall 60A located within the first type of second groove U2a can serve as the first sub-inner wall 61.

[0236] When the initial inner wall 60A is filled into the first type of second groove U2a, the initial inner wall 60A will fit against the first groove wall U21 of the first type of second groove U2a. That is, the first surface W1 of the first sub-inner wall 61 formed in the first type of second groove U2a will fit against the first groove wall U21 of the first type of second groove U2a, and the morphology of the first surface W1 will be affected by the first groove wall U21, so that the first surface W1 of the first sub-inner wall 61 is uneven.

[0237] Among them, the first groove wall U21 is the groove wall that contacts the first type of second groove U2a and the channel layer 20.

[0238] For example, the material of the inner sidewall 60 may include a low dielectric constant material. For instance, the material of the inner sidewall 60 may include silicon nitride (SiN). However, the embodiments of this application are not limited to this material for the inner sidewall 60.

[0239] S23: As shown in Figure 12, source 40 and drain 50 are formed.

[0240] A source electrode 40 and a drain electrode 50 are formed on one side of the substrate 10, and a channel layer 20 is located between the source electrode 40 and the drain electrode 50. One end of the channel layer 20 is connected to the source electrode 40, and the other end of the channel layer 20 is connected to the drain electrode 50.

[0241] In some examples, an epitaxial process is used to form a source electrode 40 in the source region 41. The formed source electrode 40 is in contact with the side of the channel layer 20 facing the source region 41. Furthermore, the source electrode 40 is located on the side of the first sub-inner wall 61 and the second sub-inner wall 62 away from the sacrificial layer E. Simultaneously, an epitaxial process is used to form a drain electrode 50 in the drain region 51. The formed drain electrode 50 is in contact with the side of the channel layer 20 facing the drain region 51. Furthermore, the drain electrode 50 is located on the side of the first sub-inner wall 61 and the second sub-inner wall 62 away from the sacrificial layer E.

[0242] For example, an epitaxial process is used to grow epitaxial layers in the source region 41 and the drain region 51, and then a doping process is used to make the epitaxial layers grown in the source and drain regions have a certain doping concentration to form the source 40 and the drain 50.

[0243] For example, the epitaxial layer may include materials such as silicon or germanium silicon.

[0244] For example, if the semiconductor device 100 is a P-type metal oxide silicon (PMOS) device, then during the epitaxial growth process, the material of the epitaxial layer can be selected as silicon and germanium doped with boron ions.

[0245] For example, if the semiconductor device 100 is an N-type metal oxide silicon (NMOS) device, then during the epitaxial growth process, the material of the epitaxial layer can be selected as silicon doped with phosphorus ions.

[0246] S24: Form gate structure 30.

[0247] A gate structure 30 is formed on one side of the substrate 10. For example, step S24 may include: S241: As shown in FIG13A, the sacrificial layer E is removed to form a gate channel E0.

[0248] It is understandable that the gate channel E0 is equivalent to the space enclosed by the adjacent channel layer 20 and the inner sidewall 60.

[0249] For example, the sacrificial layer E can be removed using a channel release process to form the gate channel E0. During the channel release process, an ultra-high selectivity etching technique is used. Therefore, during the channel release process, the ultra-high selectivity reactants used will not react with the channel layer 20, source 40, and drain 50; the reactants can react only with the sacrificial layer E to remove it.

[0250] In some examples, after removing the sacrificial layer E in step S241, the dummy gate O also needs to be removed. The space formed by removing the dummy gate O is also part of the gate channel E0.

[0251] S242: As shown in Figures 13B and 13C, a gate structure 30 is formed in the gate channel E0.

[0252] Along the first direction X, the first sub-inner wall 61 is also located on both sides of the gate structure 30. The first sub-inner wall 61 can be used to isolate the gate structure 30 from the source 40, reducing the probability of a short circuit between the gate structure 30 and the source 40. The first sub-inner wall 61 can also be used to isolate the gate structure 30 from the drain 50, reducing the probability of a short circuit between the gate structure 30 and the drain 50.

[0253] For example, along the first direction X, the second sub-inner wall 62 is also located on both sides of the gate structure 30. The second sub-inner wall 62 can be used to isolate the gate structure 30 from the source 40, reducing the probability of a short circuit between the gate structure 30 and the source 40, and the second sub-inner wall 62 can be used to isolate the gate structure 30 from the drain 50, reducing the probability of a short circuit between the gate structure 30 and the drain 50.

[0254] Gate structure 30 surrounds each channel layer 20. For example, along the second direction Z, portions of gate structure 30 are stacked with channel layer 20 such that portions of gate structure 30 are positioned above and below channel layer 20 (taking the orientation in FIG13B as an example), and along the third direction Y, portions of gate structure 30 are located on opposite sides of channel layer 20.

[0255] As can be understood, as shown in Figure 13B, along the first direction X, the two opposite sides of the channel layer 20 are used to contact the source 40 and the drain 50, and therefore are not covered by the gate structure 30. For example, from the perspective of Figure 13B, the left and right sides of the channel layer 20 are not covered by the gate structure 30.

[0256] The gate structure 30 is used to control the formation of a channel in the channel layer 20, thereby controlling the conduction between the source 40 and drain 50 located on both sides of the channel layer 20, or to control the non-formation of a channel in the channel layer 20, so that the source 40 and drain 50 located on both sides of the channel layer 20 are disconnected. Alternatively, it can be understood that the gate structure 30 is used to control the turning on and off of the GAA FET in the semiconductor device 100.

[0257] By having the gate structure 30 surround the surface of each channel layer 20 in the multilayer channel layer 20, the control capability of the gate structure 30 over the channels in the channel layer 20 can be effectively improved, thereby enhancing the electrical performance of the semiconductor device 100.

[0258] In summary, the method for fabricating the semiconductor device 100 provided in this application involves a secondary processing of the sacrificial layer E to make the first trench wall U21 of the formed second trench U2 (first type of second trench U2a) uneven. Therefore, when forming the first sub-inner wall 61 within the first type of second trench U2a, the first surface W1 of the first sub-inner wall 61 in contact with the channel layer 20 can be uneven. This alters the morphology of the first sub-inner wall 61, making the surface of the first sub-inner wall near the channel layer 20 uneven. This increases the difficulty of the etching gas used in the channel release process transporting along the interface between the first sub-inner wall 61 and the channel layer 20 towards the source 40 or drain 50, thus mitigating the problem of gap E2 (as shown in FIG. 8B) forming between the first sub-inner wall 61 and the channel layer 20 due to the transport of etching gas along the interface between the first sub-inner wall 61 and the channel layer 20. This helps reduce the probability of short circuits between the gate structure 30 and the source 40 and drain 50.

[0259] In some embodiments, in step S2123, when removing the first sub-part V121 and the second sub-part V122 of the second portion V12, firstly, the end of the second sub-part V122 near the first sub-part V121 is removed to expose the channel layer 20, and a portion of the end of the second sub-part V122 away from the first sub-part V121 is also removed; then, the remaining end of the second sub-part V122 away from the first sub-part V121 is removed, and a portion of the exposed channel layer 20 is removed to form a first target recess J1. That is, the first groove wall U21 of the formed first type of second groove U2a has the first target recess J1.

[0260] Because the thickness of the second sub-section V122 is less than the thickness of the first sub-section V121, the second sub-section V122 will be completely removed before the first sub-section V121. Furthermore, due to the loading effect (etching effect), the etching rate of the etching gas on the outer end of the second sub-section V122 near the first sub-section V121 is greater than the etching rate on the inner end of the second sub-section V122 away from the first sub-section V121. Therefore, the end of the second sub-section V122 near the first sub-section V121 will be completely removed first, exposing a portion of the channel layer 20.

[0261] Therefore, by continuing to introduce etching gas into the first protective layer V1, the etching gas can react directly with the exposed channel layer 20, removing part of the channel layer 20. It can be understood that part of the structure on the exposed surface of the channel layer 20 will be etched away to form a depression, and this depression is designated as the first target depression J1.

[0262] Based on this, when the first sub-inner wall 61 is formed in the second groove U2, the surface of the first sub-inner wall 61 is in contact with the second groove U2. It can be understood that the first surface W1 of the first sub-inner wall 61 will be in contact with the location of the first target recess J1 in the channel layer 20. The first sub-inner wall 61 fills the first target recess J1 as a first protrusion T1. That is, the first surface W1 of the first sub-inner wall 61 has a first protrusion T1 protruding towards the adjacent channel layer 20. Furthermore, the first protrusion T1 can be used to change the morphology of the first sub-inner wall 61, making the surface of the first sub-inner wall near the channel layer 20 uneven, thereby reducing the probability of etching gas forming a gap between the first sub-inner wall 61 and the channel layer 20, and reducing the probability of short circuit between the gate structure 30 and the source 40 and drain 50.

[0263] In some examples, the formed first target depression J1 extends along a third direction Y. Correspondingly, the first protrusion T1 extends along a third direction Y.

[0264] This configuration allows the first protrusion T1 to span the transmission path of the etching gas, thus further hindering the transmission of the etching gas to the source 40 or drain 50 side and reducing the probability of the etching gas forming a gap between the first sub-inner wall 61 and the channel layer 20.

[0265] For example, the third direction Y is approximately perpendicular to the first direction X. In this case, the angle between the third direction Y and the first direction X is approximately 90°. For example, the angle between the third direction Y and the first direction X can be 85°, 90°, or 95°. The third direction Y is approximately perpendicular to the second direction Z. In this case, the angle between the third direction Y and the second direction Z is approximately 90°. For example, the angle between the third direction Y and the second direction Z can be 85°, 90°, or 95°. Alternatively, it can be understood that the third direction Y is the width direction of the gate structure.

[0266] In some embodiments, as shown in Figures 14A and 14B, steps S2122 and S2123 in step S212 can be repeated. Each time steps S2122 and S2123 are repeated, an additional second target recess J2 can be formed on the first groove wall U21 of the first type of second groove U2a. The principle of forming the second target recess J2 is the same as the principle of forming the first target recess J1.

[0267] As shown in Figures 15A and 15B, when forming the first sub-inner wall 61, the portion of the first sub-inner wall 61 located within the second target recess J1 serves as the second protrusion T2. ​​The second protrusion T2 can be located on the side of the first protrusion T1 closest to the gate structure 30. In this case, the extension direction of the first sub-inner wall 61 near the surface of the channel layer 20 can be changed multiple times using the first protrusion T1 and the second protrusion T2, further increasing the difficulty of forming the gap connecting the gate structure 30 with the source 40 and drain 50. This further reduces the probability of short circuits between the gate structure 30 and the source 40 and drain 50, thereby improving the electrical performance of the semiconductor device 100.

[0268] In some embodiments, as shown in Figures 14A and 14B, when the first type of second groove U2a is formed in step 2123, the first groove wall U21 of the first type of second groove U2a has a first target protrusion I1, which is located on the side of the first target depression J1 away from the sacrificial layer E.

[0269] As shown in Figures 15A and 15B, the portion of the first sub-inner wall 61 that engages with the first target protrusion I1 is called a recess G1. The recess G1 is located on the side of the first protrusion T1 away from the sacrificial layer E, and the recess G1 extends along the third direction Y.

[0270] With this configuration, the semiconductor device 100 fabrication method provided in this application embodiment, when forming the first type of second groove U2a through secondary etching, can form a first target protrusion I1 and a first target depression J1 on the first groove wall U21 of the first type of second groove U2a. Subsequently, when forming the first sub-inner wall 61 in the first type of second groove U2a, a first protrusion T1 and a depression G1 can be formed simultaneously on the first surface W1 of the first sub-inner wall 61. Thus, the morphology of the first sub-inner wall 61 can be modified a second time using the first protrusion T1 and the depression G1, further increasing the surface unevenness of the first sub-inner wall 61 near the channel layer 20, thereby reducing the probability of etching gas forming gaps between the first sub-inner wall 61 and the channel layer 20. This further reduces the probability of short circuits between the gate structure 30 and the source 40 and drain 50, improving the electrical performance of the semiconductor device 100.

[0271] In some embodiments, as shown in Figures 14A and 14B, the first sub-inner wall 61 is a centrally symmetrical structure. This can be understood as the two first surfaces W1 of the first sub-inner wall 61 being symmetrical about the second midline L2.

[0272] This arrangement allows for a more regular structure of the multiple first sub-inner walls 61 within the inner wall 60, which is beneficial for improving the electrical performance of the semiconductor device 100.

[0273] In some embodiments, as shown in Figures 14A and 14B, the plurality of second grooves U2 formed in step S2123 may further include a second type of second groove U2b. The second type of second groove U2b can be understood as the space enclosed by the channel layer 20 adjacent to the substrate 10, the substrate 10, and the sacrificial layer E located between the channel layer 20 and the substrate 10.

[0274] The second type of second groove U2b differs from the first type of second groove U2a only in its location; both are formed in the same process and based on the same principle. Therefore, when the first groove wall U21 of the first type of second groove U2a is uneven, the second groove wall U22 of the second type of second groove U2b is simultaneously made uneven. The second groove wall U22 is the sidewall of the second type of second groove U2b where it contacts the channel layer 20; alternatively, it can be the groove wall where the second type of second groove U2b contacts the substrate 10.

[0275] The portion of the initial inner wall 60A located within the second type of second groove U2b can serve as the second sub-inner wall 62. All the first sub-inner walls 61 and the second sub-inner walls 62 together form the inner wall 60.

[0276] When the initial inner wall 60A is filled into the second type of second groove U2b, the initial inner wall 60A will fit against the second groove wall U22 of the second type of second groove U2b. That is, the second surface W2 of the second sub-inner wall 62 formed in the second type of second groove U2b will fit against the second groove wall U22, and the morphology of the second surface W2 will be affected by the morphology of the second groove wall U22, so that the second surface W2 of the second sub-inner wall 62 is uneven.

[0277] This increases the difficulty of the etching gas used in the channel release process traveling along the interface between the second sub-inner wall 62 and the channel layer 20 to the source 40 or drain 50, and along the interface between the second sub-inner wall 62 and the substrate 10 to the source 40 or drain 50, thereby improving the problem of gap E2 (as shown in Figure 8B) forming between the second sub-inner wall 62 and the substrate 10 and the channel layer 20. This helps reduce the probability of short circuits occurring between the gate structure 30 and the source 40 and drain 50.

[0278] In some embodiments, as shown in Figures 14A and 14B, when a first target recess J1 is formed on the first groove wall U21 of the first type of second groove U2a, a third target recess J3 is simultaneously formed on the second groove wall U22 of the second type of second groove U2b.

[0279] In step S222, as shown in Figures 15A and 15B, the portion of the second sub-inner wall 62 located within the third target recess J3 serves as the third protrusion T3.

[0280] Therefore, the third protrusion T3 can be used to make the second surface W2 uneven, thereby increasing the degree of unevenness of the surface where the second sub-inner wall 62 adheres to the substrate 10 and the channel layer 20. This increases the difficulty for the etching gas used in the channel release process to travel along the interface between the second sub-inner wall 62 and the channel layer 20 and the substrate 10 to the source 40 or drain 50, thus reducing the probability of a gap E2 forming between the second sub-inner wall 62 and the channel layer 20 and the substrate 10 (as shown in Figure 8B). This also reduces the probability of a short circuit occurring between the gate structure 30 and the source 40 and drain 50.

[0281] In some embodiments, as shown in Figures 14A and 14B, when a second target recess J2 is formed on the first groove wall U21 of the first type of second groove U2a, a fourth target recess J4 can similarly be formed on the second groove wall U22 of the second type of second groove U2b.

[0282] As shown in Figures 15A and 15B, the portion of the second sub-inner wall 62 located within the fourth target recess J4 serves as the fourth protrusion T4. The fourth protrusion T4 can be located on the side of the third protrusion T3 near the gate structure 30.

[0283] Based on this, the third protrusion T3 and the fourth protrusion T4 can be used to make the second surface W2 uneven, thereby increasing the degree of unevenness of the surface where the second sub-inner wall 62 adheres to the substrate 10 and the channel layer 20, and further increasing the difficulty of forming the gap connecting the gate structure 30 with the source 40 and drain 50. This further reduces the probability of short circuits between the gate structure 30 and the source 40 and drain 50, thereby improving the electrical performance of the semiconductor device 100.

[0284] In some embodiments, as shown in Figures 14A and 14B, when a first target protrusion I1 is formed on the first groove wall U21 of the first type of second groove U2a, a second target protrusion I2 can similarly be formed on the second groove wall U22 of the second type of second groove U2b.

[0285] The second target protrusion I2 is located on the side of the third target depression J3 away from the sacrificial layer E.

[0286] As shown in Figures 15A and 15B, when the second sub-inner wall 62 is formed in the second type of second groove U2b, the part of the second sub-inner wall 62 that engages with the second target protrusion I2 is called the recess G2. The recess G2 is located on the side of the third protrusion T3 away from the sacrificial layer E.

[0287] For example, the recess G2 extends along a third direction Y.

[0288] With this configuration, when the second type of second groove U2b is formed by secondary etching, a second target protrusion I2 and a third target depression J3 can be formed on the second groove wall U22 of the second type of second groove U2b. Subsequently, when the second sub-inner wall 62 is formed in the second type of second groove U2b, a third protrusion T3 and a depression G2 can be formed simultaneously on the second surface W2 of the second sub-inner wall 62.

[0289] Based on this, the third protrusion T3 and the recess G2 can be used to increase the surface unevenness of the second sub-inner wall 62 in contact with the substrate 10 and the channel layer 20, thereby reducing the probability of etching gas forming gaps between the second sub-inner wall 62 and the substrate 10 and the channel layer 20. This further reduces the probability of short circuits between the gate structure 30 and the source 40 and drain 50, improving the electrical performance of the semiconductor device 100.

[0290] The above embodiments, in conjunction with the accompanying drawings, mainly describe a method for fabricating a semiconductor device 100, which reduces the probability of short circuits between the gate structure 30 and the source 40 and drain 50 in the formed semiconductor device 100 without increasing the complexity of the process, thereby improving the electrical performance of the formed semiconductor device 100. The following section, in conjunction with the accompanying drawings, mainly describes the structure of the semiconductor device 100. For example, the semiconductor device 100 described below can be formed using the fabrication method described above.

[0291] This application provides a semiconductor device 100 in some embodiments. As shown in Figures 13B and 13C, the semiconductor device 100 includes a substrate 10, and a plurality of channel layers 20, a gate structure 30, a source 40, and a drain 50 located on the same side of the substrate 10. Along a first direction X, one end of each channel layer 20 is connected to the source 40, and the other end of each channel layer 20 is connected to the drain 50. Furthermore, along the length direction (first direction) X of the gate structure 30, the gate structure 30 is located between the source 40 and the drain 50, and the gate structure 30 surrounds each channel layer 20. The plurality of channel layers 20 are spaced apart along the thickness direction (second direction) Z of the substrate 10.

[0292] The semiconductor device 100 also includes an inner sidewall 60. The inner sidewall 60 includes a plurality of first sub-inner sidewalls 61, which are respectively disposed between adjacent channel layers 20 and on both sides of the gate structure 30. The first sub-inner sidewalls 61 are used to isolate the source 40, drain 50, and gate structure 30. Each first sub-inner sidewall 61 has an uneven first surface W1 that is respectively attached to the channel layers 20 on both sides.

[0293] Furthermore, the first surface W1 of the first sub-inner wall 61 is uneven. The morphology of the first surface W1, which is attached to the adjacent channel layer 20, can be used to increase the difficulty of the etching gas used in the channel release process traveling along the interface between the first sub-inner wall 61 and the channel layer 20 towards the source 40 or drain 50. This improves the problem of gap E2 forming between the first sub-inner wall 61 and the channel layer 20 due to the etching gas traveling along the interface between the first sub-inner wall 61 and the channel layer 20. This helps reduce the probability of short circuits between the gate structure 30 and the source 40 and drain 50, improving the electrical performance of the semiconductor device 100. Therefore, the semiconductor device 100 provided in this embodiment can reduce the probability of short circuits between the gate structure 30 and the source 40 and drain 50 through a simple structural design, effectively improving the reliability of the semiconductor device 100.

[0294] In some embodiments, as shown in Figures 13B and 13C, the first surface W1 of the first sub-inner wall 61 includes a first protrusion T1. The surface M1 of the channel layer 20 that is in contact with the first surface W1 has a first target recess JI that is in contact with the first protrusion T1.

[0295] In other words, the first protrusion T1 engages with the first target recess J1, thereby increasing the contact area between the first surface W1 of the first sub-inner wall 61 and the channel layer 20. This reduces the probability of a gap E2 forming between the first sub-inner wall 61 and the channel layer 20 (as shown in Figure 8B). Furthermore, the presence of the first protrusion T1 directly alters the morphology of the first surface W1 of the first sub-inner wall 61, making the surface of the first sub-inner wall 61 near the channel layer 20 uneven, further reducing the probability of etching gas forming a gap between the first sub-inner wall 61 and the channel layer 20.

[0296] For example, the first protrusion T1 extends along the third direction Y. This configuration allows the first protrusion T1 to span the transmission path of the etching gas, thereby further hindering the transmission of the etching gas to the source 40 or drain 50 side and reducing the probability of the etching gas forming a gap between the first sub-inner wall 61 and the channel layer 20.

[0297] In some examples, the number of first protrusions T1 on the first surface W1 of the first sub-inner wall 61 can be one or more. This application embodiment does not limit the number of first protrusions T1 on the first surface W1 of the first sub-inner wall 61 to this.

[0298] For example, when there are multiple first protrusions T1 on the first surface W1 of the first inner wall 61, the multiple first protrusions T1 located on the same first surface W1 are arranged along the first direction X and extend along the third direction Y.

[0299] In some embodiments, as shown in Figures 13B and 13C, along the second direction Z, a first protrusion T1 protrudes from the first surface W1 near the edge W11 of the gate structure 30.

[0300] The first inner wall 61 has a second centerline L2 extending along the first direction X. Along the second direction Z, the minimum distance d1 between the most convex point of the first protrusion T1 and the second centerline L2 is greater than the minimum distance d2 between the edge W11 of the first surface W1 near the gate structure 30 and the second centerline L2. d1 > d2.

[0301] Based on this, the first protrusion T1 of the first surface W1 can be made further away from the second centerline L2 relative to the edge W11 of the first surface W1 near the gate structure 30. That is, the first protrusion T1 of the first surface W1 is made closer to the interior of the channel layer 20 relative to the edge W11 of the first surface W1 near the gate structure 30. This allows the first protrusion T1 of the first surface W1 to be embedded within the channel layer 20, thereby increasing the contact area between the first surface W1 of the first sub-inner wall 61 and the channel layer 20. This reduces the probability of gaps appearing between the first sub-inner wall 61 and the channel layer 20.

[0302] Additionally, the sub-section 31 of the gate structure 30, located between two adjacent channel layers 20 and between two first sub-inner walls 61, may include a centerline whose extension may coincide with the second centerline L2 of its adjacent first sub-inner wall 61. Thus, in FIG13C, the second centerline L2 simultaneously represents the centerline of the first sub-inner wall 61 and the centerline of the sub-section 31.

[0303] At this time, the minimum distance between the surface of the sub-section 31 of the gate structure 30 that contacts the channel layer 20 and its centerline (represented by the second centerline L2 in FIG. 13C) is d3. Wherein, d2 = d3.

[0304] Based on this, the first protrusion T1 of the first surface W1 is closer to the interior of the adjacent channel layer 20 than the edge W11 of the first surface W1 near the gate structure 30, which allows the first protrusion T1 of the first surface W1 to be closer to the interior of the adjacent channel layer 20 than the sub-section 31 of the adjacent gate structure 30. Alternatively, it can be understood that the line connecting the boundary between the first protrusion T1 of the first surface W1 and the adjacent sub-section 31 of the gate structure 30 forms an inclined surface. This inclined surface intersects with the surface of the gate structure in the second direction Z.

[0305] This further increases the difficulty of forming the gap connecting the gate structure 30 with the source 40 and drain 50. It reduces the probability of short circuits occurring between the gate structure 30 and the source 40 and drain 50, thereby improving the electrical performance of the semiconductor device 100.

[0306] In some embodiments, as shown in Figures 13B and 13C, the first surface W1 further includes a recess G1 located on the side of the first protrusion T1 away from the gate structure 30. The surface M1 of the channel layer 20 that is attached to the first surface W1 has a first target protrusion I1 that is attached to the recess G1.

[0307] In other words, the recess G1 engages with the first target protrusion I1, thereby increasing the contact area between the first surface W1 of the first sub-inner wall 61 and the channel layer 20. This reduces the probability of a gap E2 forming between the first sub-inner wall 61 and the channel layer 20 (as shown in Figure 8B). Furthermore, the presence of the recess G1 directly alters the morphology of the first surface W1 of the first sub-inner wall 61, making the surface of the first sub-inner wall 61 near the channel layer 20 uneven, further reducing the probability of etching gas forming a gap between the first sub-inner wall 61 and the channel layer 20.

[0308] In some examples, the recess G1 and the first protrusion T1 are continuously disposed on the first surface W1.

[0309] At this point, the first protrusion T1 corresponds to the high position of the first surface W1, and the recess G1 corresponds to the low position of the first surface W1. The simultaneous presence of the first protrusion T1 and the recess G1 on the first surface W1 increases the surface unevenness of the first sub-inner wall 61 near the channel layer 20, making it more difficult to form the gap connecting the gate structure 30 with the source 40 and drain 50. This further reduces the probability of short circuits between the gate structure 30 and the source 40 and drain 50, thereby improving the electrical performance of the semiconductor device 100.

[0310] For example, the recess G1 and the first protrusion T1 are arranged along the first direction X and extend in the third direction Y.

[0311] In some examples, the minimum distance between the deepest point of the depression G1 and the second median L2 is d4, where d1 > d4 ≥ d2.

[0312] Setting d4 < d1 ensures that the first protrusion T1 is further away from the second centerline L2 of the first sub-inner wall 61 relative to the recess G1. This further increases the surface unevenness of the first sub-inner wall 61 near the channel layer 20 by utilizing the first protrusion T1 and the recess G1, thereby increasing the difficulty of forming the gap connecting the gate structure 30 with the source 40 and drain 50. This reduces the probability of short circuits occurring between the gate structure 30 and the source 40 and drain 50.

[0313] Set d4 ≥ d2. That is, set d4 ≥ d3. This is to prevent d4 < d3, which would result in a sacrificial layer remaining between the first sub-inner wall 61 and the channel layer 20 when the inner wall 60 is formed. This reduces the probability of a gap forming between the first sub-inner wall 61 and the channel layer 20 after the sacrificial layer is removed. As a result, the probability of a short circuit occurring between the gate structure 30 and the source 40 and drain 50 is reduced.

[0314] In some embodiments, as shown in Figures 13B and 13C, along the second direction Z, the first surface W1 protrudes from the edge W12 away from the gate structure 30 from the recess G1.

[0315] The minimum distance between the edge W12 of the first surface W1 away from the gate structure 30 and the second centerline L2 of the first sub-inner wall 61 is d5, where d5 > d4. The edge W12 of the first surface W1 away from the gate structure 30 is closer to the interior of the adjacent channel layer 20 than the recess G1 of the first surface W1.

[0316] Based on this, the unevenness of the surface of the first sub-inner wall 61 near the channel layer 20 can be further increased by utilizing the edge W12 of the first surface W1 away from the gate structure 30, thus increasing the difficulty of forming the gap connecting the gate structure 30 with the source 40 and drain 50. This further reduces the probability of short circuits between the gate structure 30 and the source 40 and drain 50, improving the electrical performance of the semiconductor device 100.

[0317] In some examples, d5 ≥ d2. That is, d5 ≥ d3 is set to prevent d5 < d3, which would result in a sacrificial layer remaining between the first sub-inner wall 61 and the channel layer 20 when the inner wall 60 is formed. This reduces the probability of a gap forming between the first sub-inner wall 61 and the channel layer 20 after the sacrificial layer is removed. This, in turn, reduces the probability of a short circuit occurring between the gate structure 30 and the source 40 and drain 50.

[0318] In this application embodiment, the relationship between d5 and d1 is not specifically limited, and can be adjusted according to the actual preparation process precision.

[0319] In some embodiments, as shown in Figures 13B and 13C, the surface of the channel layer 20 that contacts the first sub-inner wall 61 along the first direction X has an edge 21. Along the second direction Z, the edge 21 of the channel layer 20 protrudes from the edge W12 of the first surface W1 away from the gate structure 30. Alternatively, it can be understood that along the second direction Z, the minimum distance between the edge 21 of the channel layer 20 and the extension of the second centerline L2 of its adjacent first sub-inner wall 61 is d6, where d6 > d5.

[0320] Along the first direction X, the edge 21 of the channel layer 20 is further away from the gate structure 30 than the edge W12 of the first surface W1 away from the gate structure 30. When forming the inner wall groove U that accommodates the first sub-inner wall 61 (as shown in Figure 6B), the concentration of the etching reactant at the edge 21 of the channel layer 20 is relatively higher than the concentration at the edge W12 of the first surface W1 away from the gate structure 30. Therefore, the etching rate at the edge 21 of the channel layer 20 is relatively higher than the etching rate at the edge W12 of the first surface W1 away from the gate structure 30.

[0321] Therefore, setting the edge 21 of the channel layer 20 to protrude in the third direction Y from the edge W12 of the first surface W1 away from the gate structure 30 can meet the requirements of reactant diffusion and simplify the process difficulty of the inner sidewall 60.

[0322] In some embodiments, as shown in Figures 15A and 15B, the first surface W1 further includes a second protrusion T2 extending in the third direction Y. The second protrusion T2 is located on the side of the first protrusion T1 away from the gate structure 30. The surface M1 of the channel layer 20 that is in contact with the first surface W1 has a second target recess J2 that is in contact with the second protrusion T2.

[0323] In other words, the second protrusion T2 engages with the second target recess J2, thereby increasing the contact area between the first surface W1 of the first sub-inner wall 61 and the channel layer 20. This reduces the probability of a gap E2 forming between the first sub-inner wall 61 and the channel layer 20 (as shown in Figure 8B). Furthermore, the presence of the second protrusion T2 directly alters the morphology of the first surface W1 of the first sub-inner wall 61, making the surface of the first sub-inner wall 61 near the channel layer 20 uneven, further reducing the probability of etching gas forming a gap between the first sub-inner wall 61 and the channel layer 20.

[0324] Furthermore, in the first direction X, the first surface W1 of the first sub-inner wall 61 is provided with a first protrusion T1 and a second protrusion T2. ​​The first protrusion T1 and the second protrusion T2 can be used to increase the unevenness of the surface of the first sub-inner wall 61 near the channel layer 20, thereby increasing the difficulty of forming the gap connecting the gate structure 30 with the source 40 and the drain 50.

[0325] In some examples, when the first surface W1 of the first sub-inner wall 61 has multiple second protrusions T2, the multiple second protrusions T2 are arranged along the first direction X and extend along the third direction Y.

[0326] Therefore, the first surface W1 of the first sub-inner wall 61 can be made uneven near the channel layer 20 by using multiple second protrusions T2, which increases the difficulty of forming the gap connecting the gate structure 30 with the source 40 and drain 50.

[0327] In some examples, as shown in Figures 15A and 15B, the recess G can be located between the first protrusion T1 and the second protrusion T2.

[0328] Therefore, the first surface W1 of the first sub-inner wall 61 can utilize the undulations of the first protrusion T1, the depression G1, and the second protrusion T2 to further increase the unevenness of the surface of the first sub-inner wall 61 near the channel layer 20, thereby further increasing the difficulty of forming the gap connecting the gate structure 30 with the source 40 and the drain 50. This reduces the probability of short circuits occurring between the gate structure 30 and the source 40 and the drain 50.

[0329] In other examples, where the second protrusion T2 is located on the side of the first protrusion T1 away from the gate structure 30, the recess G may be located between the second protrusion T2 and the edge W12 of the first surface W1 away from the gate structure 30.

[0330] Therefore, by utilizing the undulations of the first protrusion T1, the second protrusion T2, the recess G1, and the edge W12 of the first surface W1 away from the gate structure 30, the surface of the first sub-inner wall 61 near the channel layer 20 is further made more uneven, thereby increasing the difficulty of forming a gap connecting the gate structure 30 with the source 40 and drain 50. This reduces the probability of short circuits occurring between the gate structure 30 and the source 40 and drain 50.

[0331] In some other examples, when there are multiple first protrusions T1 on the first surface W1 of the first sub-inner wall 61, the recess G1 may be located between two adjacent first protrusions T1.

[0332] At this point, the undulations of the previous first protrusion T1, the depression G1, and the subsequent first protrusion T1 further increase the unevenness of the surface of the first sub-inner wall 61 near the channel layer 20, thereby further increasing the difficulty of forming the gap connecting the gate structure 30 with the source 40 and drain 50. This reduces the probability of short circuits occurring between the gate structure 30 and the source 40 and drain 50.

[0333] In some other examples, when there are multiple second protrusions T2 on the first surface W1 of the first sub-inner wall 61, the recess G1 may be located between two adjacent second protrusions T2.

[0334] At this point, the undulations of the previous second protrusion T2, the depression G1, and the subsequent second protrusion T2 further increase the unevenness of the surface of the first sub-inner wall 61 near the channel layer 20, thereby further increasing the difficulty of forming the gap connecting the gate structure 30 with the source 40 and drain 50. This reduces the probability of short circuits occurring between the gate structure 30 and the source 40 and drain 50.

[0335] In some embodiments, as shown in Figures 15A and 15B, the inner wall 60 includes a plurality of second sub-inner walls 62. The plurality of second sub-inner walls 62 are disposed between the channel layer 20 adjacent to the substrate 10 and the substrate 10, and are located on both sides of the gate structure 30. The second sub-inner walls 62 are used to isolate the source 40 and drain 50 from the gate structure 30. The second sub-inner walls 62 have uneven second surfaces W2 that respectively conform to the channel layer 20 and the substrate 10 on both sides.

[0336] Based on this, the morphology of the second surface W2 of the second sub-inner wall 62 can be utilized to increase the difficulty of the etching gas used in the channel release process transporting along the interface between the second sub-inner wall 62 and the channel layer 20 and the substrate 10 to the source 40 or drain 50. This improves the problem of gap E2 forming between the second sub-inner wall 62 and the channel layer 20 due to the transport of etching gas along the interface between the second sub-inner wall 62 and the channel layer 20 and the substrate 10. This helps to reduce the probability of short circuits between the gate structure 30 and the source 40 and drain 50, and improves the electrical performance of the semiconductor device 100. Therefore, the semiconductor device 100 provided in this application embodiment can reduce the probability of short circuits between the gate structure 30 and the source 40 and drain 50 through a simple structural arrangement, effectively improving the reliability of the semiconductor device 100.

[0337] In some examples, as shown in Figures 15A and 15B, the second surface W2 of the second sub-inner wall 62 includes a third protrusion T3. Exemplarily, the third protrusion T3 extends in the third direction Y.

[0338] The structure of the third protrusion T3 on the second surface W2 of the second sub-inner wall 62 is similar to the structure of the first protrusion T1 on the first surface W1 of any first sub-inner wall 61. It can be combined with the description of the structure of the first protrusion T1 above, and will not be repeated here.

[0339] In some examples, as shown in Figures 15A and 15B, the second surface W2 of the second sub-inner wall 62 may further include a fourth protrusion T4 located on the side of the third protrusion T3 away from the gate structure 30. Exemplarily, the fourth protrusion T4 extends along a third direction Y.

[0340] The structure of the fourth protrusion T4 on the second surface W2 of the second sub-inner wall 62 can be similar to the structure of the second protrusion T2 on the first surface W1 of any first sub-inner wall 61. It can be combined with the description of the structure of the second protrusion T2 above, and will not be repeated here.

[0341] In some examples, the second surface W2 of the second sub-inner wall 62 may also include a recess G2 located on the side of the third protrusion T3 away from the gate structure 30.

[0342] The recess G2 on the second surface W2 of the second sub-inner wall 62 can be similar in structure to the recess G1 on the first surface W1 of any first sub-inner wall 61. This can be combined with the description of the structure of the recess G2 above, and will not be repeated here.

[0343] In some embodiments, as shown in Figures 15A and 15B, the second sub-inner wall 62 is a centrally symmetrical structure. This can be understood as the two second surfaces W2 of the second sub-inner wall 62 being symmetrical about the second midline L2.

[0344] This arrangement allows for a more regular structure of the multiple second sub-inner walls 62 within the inner wall 60, which is beneficial for improving the electrical performance of the semiconductor device 100.

[0345] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; a source electrode and a drain electrode disposed on one side of the substrate; a plurality of channel layers disposed on the same side of the substrate as the source electrode and the drain electrode, the plurality of channel layers being located between the source electrode and the drain electrode, one end of the channel layers being connected to the source electrode, and the other end of the channel layers being connected to the drain electrode; the plurality of channel layers being spaced apart along the thickness direction of the substrate; a gate structure surrounding each of the channel layers; an inner sidewall comprising a plurality of first sub-inner sidewalls, the plurality of first sub-inner sidewalls being respectively disposed between adjacent channel layers and on both sides of the gate structure, for isolating the source electrode, the drain electrode and the gate structure, the first sub-inner sidewalls having a first uneven surface respectively abutting the channel layers on both sides.

2. The semiconductor device according to claim 1, wherein The first surface comprises a first protrusion protruding towards the channel layer abutting the first surface, and the surface of the channel layer abutting the first surface has a first target recess abutting the first protrusion.

3. The semiconductor device of claim 2, wherein, The first protrusion protrudes from the first surface towards the edge of the gate structure along the thickness direction of the substrate.

4. The semiconductor device according to claim 2 or 3, characterized by The first surface has a recess away from the channel layer abutting the first surface, and the recess is located on the side of the first protrusion away from the gate structure; the surface of the channel layer abutting the first surface has a first target protrusion abutting the recess.

5. The semiconductor device according to claim 4, wherein The recess and the first protrusion are continuously disposed on the first surface.

6. The semiconductor device according to claim 4 or 5, characterized by The first surface protrudes from the recess away from the edge of the gate structure along the thickness direction of the substrate.

7. The semiconductor device according to any one of Claims 2 to 6, wherein The first surface further comprises a second protrusion protruding towards the channel layer abutting the first surface, and the second protrusion is located on the side of the first protrusion away from the gate structure; the surface of the channel layer abutting the first surface has a second target recess abutting the second protrusion.

8. The semiconductor device of claim 1, wherein The inner sidewall further comprises a plurality of second sub-inner sidewalls, the plurality of second sub-inner sidewalls being disposed between the channel layer adjacent to the substrate and the substrate and on both sides of the gate structure, for isolating the source electrode, the drain electrode and the gate structure, the second sub-inner sidewalls having a second uneven surface respectively abutting the channel layers and the substrate on both sides.

9. An electronic device, comprising: It comprises: a circuit board; a semiconductor device located on the circuit board and electrically connected to the circuit board; wherein the semiconductor device comprises any one of the semiconductor devices according to claims 1-8.

10. A method of manufacturing a semiconductor device, characterized by, The preparation method comprises: forming a plurality of channel layers and a plurality of sacrificial layers; the sacrificial layers and the channel layers are alternately disposed; forming an inner sidewall; the inner sidewall comprises a plurality of first sub-inner sidewalls, the plurality of first sub-inner sidewalls being respectively located on both sides of the sacrificial layers and respectively disposed between adjacent channel layers, the first sub-inner sidewalls having a first uneven surface respectively abutting the channel layers on both sides; forming a source electrode and a drain electrode; the source electrode and the drain electrode are respectively located on both sides of the channel layers; the source electrode is connected to one end of the channel layers, and the drain electrode is connected to the other end of the channel layers; forming a gate structure; the gate structure surrounds each of the channel layers; wherein a plurality of the first sub-inner spacers are located on both sides of the gate structure, for isolating the source and drain from the gate structure.

11. The method of claim 10, wherein, The forming of the inner spacers comprises: forming a first recess on both sides of the sacrificial layer along the length direction of the gate structure; performing a passivation treatment on the channel layers and the first recess to form a first protective layer; the first protective layer comprises a first part and a second part, the first part is located on the side of the channel layer, and the second part is located in the first recess; removing the first part to expose the channel layer; removing the second part to form a second recess; the first groove wall of the second recess in contact with the channel layer has a first target recess; forming the first sub-inner spacers in the second recess; the part of the first sub-inner spacers located in the first target recess constitutes a first protrusion.

12. The preparation method of claim 11, wherein, performing a passivation treatment on the channel layers and the first recess to form a first protective layer comprises: passing a passivation gas into the channel layers and the first recess; the passivation gas reacts with the channel layers to form the first part with a first thickness, and the passivation gas reacts with the first recess to form the second part with a second thickness; wherein the first thickness is greater than the second thickness.

13. The preparation method of claim 12, wherein, the thickness of the first part ranges from 0.5 nm to 10 nm; and the thickness of the second part ranges from 0.1 nm to 5 nm.

14. The production method according to claim 12 or 13, characterized by, the second part comprises a first sub-part and a second sub-part; the second sub-part is in contact with the sacrificial layer, and the thickness of the first sub-part is greater than the thickness of the second sub-part.

15. The method of claim 14, wherein, the passivation gas comprises oxygen or nitrogen.

16. The production method according to claim 14 or 15, characterized in that, removing the first part to expose the channel layer; removing the second part to form a second recess comprises: passing an etching gas into the first protective layer to simultaneously remove the first part and the second part; when removing the first sub-part and the second sub-part of the second part, first remove one end of the second sub-part close to the first sub-part to expose the channel layer, and remove part of the other end of the second sub-part away from the first sub-part; then remove the other end of the remaining second sub-part away from the first sub-part, and remove part of the exposed channel layer to form the first target recess.

17. The preparation method according to claim 16, characterized in that, the etching gas comprises a halogen element-containing gas and a hydrogen-reducing gas.

18. The preparation method of claim 17, wherein, the halogen element-containing gas comprises at least one of a fluorine-based gas, a chlorine-based gas, or a bromine-based gas.

19. The production method according to any one of claims 11 to 18, characterized by, after forming the second recess and before forming the sub-inner spacers, the preparation method of the semiconductor device comprises: cleaning the second recess.

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