Coplanar waveguide transmission line, quantum chip and construction method for wiring model thereof

Abstract

The present invention relates to a coplanar waveguide transmission line, a quantum chip and a construction method for a wiring model thereof. The coplanar waveguide transmission line comprises a central conduction band, grounding conduction bands, and a trapezoidal module. The grounding conduction bands are arranged on two sides of the central conduction band, and gaps are maintained between the grounding conduction bands and the central conduction band. The trapezoidal module comprises a plurality of trapezoidal units, and the plurality of trapezoidal units are arranged, at equally spaced intervals, on any side of the central conduction band. This design can reduce far-end crosstalk and reduce electromagnetic radiation. The trapezoidal structure increases the capacitive impedance, which not only solves the problem of impedance increase caused by the reduction of the trace width due to high-density wiring, but also reduces the far-end crosstalk because far-end crosstalk is generally created inductively. When applied to quantum chips, the design helps improve the performance and stability of quantum chips and promote the development of quantum technology.

Description

A method for constructing a coplanar waveguide transmission line, a quantum chip, and their wiring model. Technical Field

[0001] This invention relates to the field of quantum chip technology, and in particular to a method for constructing a coplanar waveguide transmission line, a quantum chip, and its wiring model. Background Technology

[0002] In quantum computing technology, quantum chips are the core components for realizing quantum computing and information processing. However, as the number of qubits increases, the wiring on quantum chips becomes increasingly complex, and the wiring density also shows a significant upward trend. This high-density wiring design is similar to carefully arranging a large number of wires in a limited space, ensuring that each wire is accurately and efficiently connected to a predetermined location.

[0003] However, this presents a significant technical challenge—crosstalk between signal lines. This crosstalk is particularly pronounced in wavefront co-conducting traces. Analogous to a busy communications market, numerous lines transmitting signals simultaneously inevitably experience mutual interference. In quantum chips, this interference can lead to malfunctions of qubits, adversely affecting the accuracy and overall performance of quantum computing.

[0004] To address this challenge, researchers have explored various solutions, such as increasing trace spacing, using dielectric materials with low dielectric constants, optimizing the length design of parallel traces, and introducing techniques like air bridges. While these measures can alleviate crosstalk to some extent, they still have many limitations in practical applications. For example, with the continuous increase in the number of qubits, simply increasing trace spacing to reduce crosstalk becomes increasingly difficult; and the application of advanced technologies such as air bridges is accompanied by increased complexity and cost in manufacturing processes.

[0005] Of particular note is that existing technical solutions fall short in addressing far-end crosstalk in wavefront co-conducting traces. Far-end crosstalk refers to the phenomenon where even weak interference signals at the far end of the signal transmission path can significantly affect sensitive quantum devices (such as bit capacitors), leading to erroneous interactions between qubits and ultimately causing errors in measurement, control, and readout operations.

[0006] In summary, there is an urgent need for a new technical solution that can maintain high wiring density while effectively reducing signal interference, especially for crosstalk problems in wavefront co-conducting traces in quantum chips. Summary of the Invention

[0007] To address the aforementioned technical problems, this application provides a method for constructing a coplanar waveguide transmission line, a quantum chip, and its wiring model.

[0008] This application provides a coplanar waveguide transmission line for use in quantum devices, comprising:

[0009] A central conduction band, which is used for electrical signal transmission in the quantum device;

[0010] The grounding conductor is disposed on both sides of the central conductor, with a gap between them, to serve as a grounding element.

[0011] A trapezoidal module, comprising multiple trapezoidal units, which are equally spaced on either side of the central conductor to provide capacitive impedance.

[0012] As a further improvement of this application, the grounding conductor includes a first grounding conductor, a second grounding conductor, and a third grounding conductor, which are arranged in parallel at equal intervals; the center conductor includes a first center conductor and a second center conductor, which are arranged in parallel between the first grounding conductor and the second grounding conductor, and the second center conductor is arranged in parallel between the second grounding conductor and the third grounding conductor; the plurality of trapezoidal units include a first trapezoidal unit portion disposed on any side of the first center conductor and a second trapezoidal unit portion disposed on any side of the second center conductor.

[0013] As a further improvement of this application, the first trapezoidal unit portion and the second trapezoidal unit portion are arranged symmetrically one-to-one with the second grounding conductor as the central axis; or, the first trapezoidal unit portion and the second trapezoidal unit portion are arranged alternately with the second grounding conductor as the central axis.

[0014] To achieve the above objectives, this application also provides a quantum chip, comprising:

[0015] substrate;

[0016] A quantum device disposed on the substrate;

[0017] A coplanar waveguide transmission line, wherein the coplanar waveguide transmission line is connected to the quantum device, and the coplanar waveguide transmission line is any one of the coplanar waveguide transmission lines described above.

[0018] To achieve the above objectives, this application also provides a method for constructing a wiring model for a quantum chip layout, the method comprising:

[0019] Step S1: Obtain simulation reference information. The simulation reference information is obtained by performing impedance simulation and crosstalk simulation through a quantum chip wiring model. The simulation reference information includes time-domain impedance value and frequency-domain crosstalk S-parameter.

[0020] Step S2: Based on the quantum chip wiring model, obtain at least one quantum chip wiring model, and use simulation software to perform parametric scanning simulation on each of the quantum chip wiring models to obtain the design parameter range of each of the quantum chip wiring models.

[0021] Step S3: Based on the simulation reference information, select a target design parameter range from the design parameter ranges of each quantum chip routing model, and adjust the corresponding quantum chip routing model according to the target design parameter range, and use the adjusted quantum chip routing model as the target quantum chip routing model.

[0022] The quantum chip routing model is obtained based on any one or more of the coplanar waveguide transmission lines described above, and the target design parameters include the design parameters of the trapezoidal structure corresponding to the quantum chip routing model.

[0023] As a further improvement to this application, obtaining at least one quantum chip wiring model based on the quantum chip wiring model includes:

[0024] Based on the quantum chip wiring model, a quantum chip wiring model including coplanar waveguide traces and trapezoidal structures is established. The design parameters of the trapezoidal structure include the spacing S, the upper width w1, the lower width w2, and the height h. The parameterized model expression of the quantum chip wiring model is as follows: F = f(S, w1, w2, h).

[0025] Where F represents the magnitude of the far-end crosstalk.

[0026] As a further improvement to this application, step S3 includes:

[0027] Based on the currently obtained design parameter range, the far-end crosstalk value is obtained using the expression of the parameterized model of the quantum chip wiring model;

[0028] When the far-end crosstalk value obtained based on the simulation reference information meets the target crosstalk value, the currently obtained design parameter range is used as the target design parameter; otherwise, step S2 is executed.

[0029] As a further improvement to this application, the frequency domain crosstalk S-parameters include near-end frequency domain S-parameters and far-end frequency domain S-parameters; for any quantum chip routing model, when the far-end crosstalk value obtained based on the simulation reference information meets the target crosstalk value, the currently acquired design parameter range is used as the target design parameter, including:

[0030] Using simulation software, the design parameters of the trapezoidal structure of the quantum chip wiring model are adjusted, and the design parameters that meet the preset design requirements are used as a set of design parameters. The set of design parameters is used to indicate the range of design parameters for the trapezoidal structure of the quantum chip wiring model.

[0031] When the set of design parameters is empty, it is considered that the far-end crosstalk value obtained based on the simulation reference information does not meet the target crosstalk value; otherwise, the set of design parameters is taken as the target design parameter.

[0032] The design requirements include: under the premise that the impedance change is within a preset impedance change range and the near-end crosstalk change is within a preset near-end crosstalk change range, the far-end crosstalk should reach a preset far-end crosstalk range.

[0033] To achieve the above objectives, this application also provides a wiring structure construction apparatus, the construction apparatus comprising: a memory and a processor, the memory having a computer program executable on the processor, the processor executing the program to implement the steps of the method described in any of the above-mentioned embodiments.

[0034] To achieve the above objectives, this application also provides a computer storage medium storing a computer program, wherein the computer program, when executed, causes the device in which the computer storage medium is located to perform the steps of the method according to any one of the preceding claims.

[0035] To achieve the above objectives, this application also provides a program product, including a computer program that, when executed by a processor, implements the method as described in any one of the preceding claims.

[0036] The beneficial effects of this application are as follows:

[0037] This application provides a coplanar waveguide transmission line, a quantum chip, and a construction method. The coplanar waveguide transmission line of this application can optimize the distribution of the electromagnetic field, effectively reduce energy loss during transmission, and thus improve the efficiency of energy transmission. Furthermore, the trapezoidal module designed in this application is composed of multiple trapezoidal units, and these trapezoidal units are equally spaced on either side of the central conductor. The trapezoidal structure increases capacitive impedance, which not only solves the problem of increased impedance caused by the reduction in linewidth in high-density wiring, but also reduces far-end crosstalk, as far-end crosstalk is generally inductive. Attached Figure Description

[0038] Figure 1 is a schematic diagram of the structure of a coplanar waveguide transmission line according to an embodiment;

[0039] Figure 2 is a schematic diagram of the structure of a coplanar waveguide transmission line according to another embodiment;

[0040] Figure 3 is a schematic diagram of the structure of a coplanar waveguide transmission line according to another embodiment;

[0041] Figure 4 is a flowchart illustrating a method for constructing a wiring model of a quantum chip layout according to an embodiment.

[0042] In the figure: 11, first grounding conductor; 12, second grounding conductor; 13, third grounding conductor; 21, first center conductor; 22, second center conductor; 31, trapezoidal unit. Detailed Implementation

[0043] The technical solution of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0044] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to specific embodiments.

[0045] Example 1

[0046] Referring to Figures 1 to 3, this embodiment provides a coplanar waveguide transmission line for quantum devices, comprising: a central conductor strip for transmitting electrical signals in the quantum device; a grounding conductor strip disposed on both sides of the central conductor strip with a gap between them for grounding purposes; and a trapezoidal module comprising multiple trapezoidal units 31, which are equally spaced on any side of the central conductor strip to provide capacitive impedance.

[0047] Based on the above technical solution, the coplanar waveguide transmission line of this application can optimize the distribution of the electromagnetic field, effectively reduce energy loss during transmission, and thus improve the efficiency of energy transmission. Furthermore, the trapezoidal module designed in this application is composed of multiple trapezoidal units, which are equally spaced on either side of the central conductor. The trapezoidal structure increases capacitive impedance, not only solving the problem of increased impedance caused by the reduction in linewidth in high-density wiring, but also reducing far-end crosstalk, which is generally inductive.

[0048] In an optional embodiment, as shown in the structural schematic diagrams of Figures 1, 2, and 3, the grounding conductor includes a first grounding conductor 11, a second grounding conductor 12, and a third grounding conductor 13, which are arranged parallel to each other at equal intervals. The central conductor includes a first central conductor 21 and a second central conductor 22, with the first central conductor 21 arranged parallel between the first grounding conductor 11 and the second grounding conductor 12, and the second central conductor 22 arranged parallel between the second grounding conductor 12 and the third grounding conductor 13. The plurality of trapezoidal units include a first trapezoidal unit portion disposed on any side of the first central conductor 21 and a second trapezoidal unit portion disposed on any side of the second central conductor 22.

[0049] Based on the above structural design, the grounding conductor adopts a three-strip design with equal spacing and parallel arrangement. This not only enhances the structural stability of the entire transmission line but also helps maintain a uniform distribution of the electromagnetic field, further reducing signal interference and energy loss. Dual-center conductor design: By setting a first center conductor 21 and a second center conductor 22, the coplanar waveguide transmission line of this application can support more complex and efficient signal transmission modes, improving the overall data processing capability.

[0050] As a further improvement of this application, the first trapezoidal unit portion and the second trapezoidal unit portion are arranged symmetrically one-to-one with the second grounding conductor 12 as the central axis, as shown in the structural schematic diagrams of Figures 1 and 2; or, the first trapezoidal unit portion and the second trapezoidal unit portion are arranged alternately with the second grounding conductor 12 as the central axis, as shown in the structural schematic diagram of Figure 3. The structure of the trapezoidal module is a very important factor affecting electromagnetic field distribution, multipath propagation, frequency selective filtering, etc. The optimized trapezoidal unit arrangement structure of this application has the following advantages: 1) It evenly adjusts the distribution of the electromagnetic field between the central conductor and the grounding conductor, reducing the radiation of electromagnetic energy into the surrounding space; 2) It can filter out or attenuate frequency components that are prone to far-end crosstalk, improving the purity of the signal and the transmission quality; 3) It controls the direction and intensity of the beam during signal propagation, reducing unnecessary radiation and interference; 4) Multiple identical trapezoidal units not only improve the consistency and precision of manufacturing, but also reduce signal distortion and crosstalk problems caused by manufacturing differences. This reduces interference to other signal lines, i.e., reduces far-end crosstalk. The specially designed trapezoidal module in this application works together to reduce far-end crosstalk in coplanar waveguide transmission lines through multiple mechanisms, including waveform matching, electromagnetic field distribution optimization, multipath propagation suppression, frequency-selective filtering, and improved structural stability and consistency. These principles work synergistically, making the trapezoidal module an effective means of improving the performance of coplanar waveguide transmission lines.

[0051] Example 2

[0052] This embodiment provides a quantum chip, including:

[0053] substrate;

[0054] A quantum device disposed on the substrate;

[0055] A coplanar waveguide transmission line is provided, which is connected to the quantum device. This coplanar waveguide transmission line is the same as described in Example 1. The optimized structure and efficient energy transfer characteristics of the coplanar waveguide transmission line in Example 1 contribute to improving the performance and stability of the quantum device, thus promoting the development of quantum technology.

[0056] Example 3

[0057] Referring to Figure 4, this embodiment provides a method for constructing a wiring model of a quantum chip layout, the method including steps S1 to S3.

[0058] Step S1: Obtain simulation reference information. The simulation reference information is obtained by performing impedance simulation and crosstalk simulation through a quantum chip wiring model. The simulation reference information includes time-domain impedance value and frequency-domain crosstalk S-parameter.

[0059] Impedance simulation is used to obtain time-domain impedance values, which helps to understand the resistance and inductance characteristics of signals propagating in the cabling. Crosstalk simulation is used to obtain frequency-domain crosstalk S-parameters, which helps to quantify the degree of electromagnetic interference between different signal lines. The obtained simulation reference information can help to understand and quantify the electrical characteristics of the cabling model, providing a data foundation for subsequent optimization design.

[0060] Step S2: Based on the quantum chip wiring model, obtain at least one quantum chip wiring model, and use simulation software to perform parametric scanning simulation on each of the quantum chip wiring models to obtain the design parameter range of each of the quantum chip wiring models.

[0061] Multiple quantum chip routing models can be created based on the initial quantum chip routing model. Parametric sweep simulations are then performed on these models using simulation software to obtain the design parameter range for each model. The parametric sweep simulation evaluates the performance of the quantum chip routing models by adjusting various parameters, aiming to find design parameters that minimize far-end crosstalk while keeping impedance and near-end crosstalk almost constant.

[0062] Specifically, simulation software can be used to evaluate the performance under different parameter configurations by adjusting parameters (such as spacing, width, and height) in the quantum chip wiring model.

[0063] Step S3: Based on the simulation reference information, select a target design parameter range from the design parameter ranges of each quantum chip routing model, and adjust the corresponding quantum chip routing model according to the target design parameter range, and use the adjusted quantum chip routing model as the target quantum chip routing model.

[0064] The quantum chip routing model is obtained based on any one or more of the coplanar waveguide transmission lines described in Embodiment 1, and the target design parameters include the design parameters of the trapezoidal module corresponding to the routing model of the coplanar waveguide transmission line.

[0065] Based on the simulation reference information obtained in step S1, target design parameters can be selected from the multiple design parameter ranges obtained in step S2. The corresponding quantum chip routing model is then adjusted according to the selected target design parameters to form the final target quantum chip routing model.

[0066] Compared to related technologies that address the challenge of crosstalk between signal lines by increasing trace spacing, using low-dielectric-constant dielectric materials, optimizing parallel trace length design, and introducing air bridges, these methods still have many limitations in practical applications. The quantum chip layout routing model construction method provided in this application optimizes the quantum chip routing model through simulation and parameter optimization, reducing signal interference and loss during transmission and improving signal integrity. The method pays particular attention to reducing far-end crosstalk, which is crucial for sensitive qubit operations in quantum chips and can improve the accuracy of quantum computing. Compared to traditional technologies such as air bridges, the coplanar waveguide transmission line and quantum chip corresponding to the method proposed in this embodiment have lower manufacturing costs and higher process compatibility.

[0067] In summary, the method for constructing a wiring model for a quantum chip layout provided in this application aims to achieve high-density wiring while effectively reducing far-end crosstalk and improving the performance and reliability of the quantum chip.

[0068] In an optional implementation, obtaining at least one quantum chip wiring model based on the quantum chip wiring model (i.e., step S2) includes:

[0069] Based on the quantum chip wiring model, a quantum chip wiring model including coplanar waveguide traces and trapezoidal structures is established. The design parameters of the trapezoidal structure include the spacing S, the upper width w1, the lower width w2, and the height h. The parameterized model expression of the quantum chip wiring model is as follows: F = f(S, w1, w2, h).

[0070] Where F represents the magnitude of the far-end crosstalk.

[0071] Remote crosstalk is mainly addressed by optimizing the design by adjusting the spacing S, upper width w1, lower width w2, and height h of the trapezoidal structure.

[0072] It can be considered that, based on the quantum chip wiring model, a quantum chip wiring model including coplanar waveguide traces and trapezoidal structures is created. The coplanar waveguide traces are the signal transmission paths, while the trapezoidal structure is the geometry used in the design to optimize electromagnetic characteristics. The design parameters of the trapezoidal structure collectively determine the electromagnetic performance of the wiring model, especially the magnitude of far-end crosstalk. By adjusting the above four design parameters, the far-end crosstalk F can be reduced, thus optimizing the wiring model. Specifically, three-dimensional electromagnetic simulation software can be used to perform parametric scanning simulations of the wiring model to evaluate the far-end crosstalk performance under different parameter combinations.

[0073] Therefore, by digitally adjusting the parameters of the trapezoidal structure, far-end crosstalk can be effectively controlled and reduced, improving signal transmission quality and precisely controlling crosstalk. The trapezoidal structure design helps optimize the distribution of the electromagnetic field, reduce energy loss, and improve transmission efficiency. The parametric model provides high design flexibility, allowing designers to adjust the wiring model according to specific needs to achieve optimal performance. Reducing far-end crosstalk helps improve the operational accuracy of qubits, thereby enhancing the overall performance of the quantum chip.

[0074] In an optional implementation, step S3 includes:

[0075] Based on the currently obtained design parameter range, the far-end crosstalk value is obtained using the expression of the parameterized model of the quantum chip wiring model;

[0076] When the far-end crosstalk value obtained based on the simulation reference information meets the target crosstalk value, the currently obtained design parameter range is used as the target design parameter; otherwise, step S2 is executed.

[0077] First, the far-end crosstalk value F under the current design parameter range is calculated using the expression of the parametric model. The calculated far-end crosstalk value is then compared with the target crosstalk value in the simulation reference information. If the current far-end crosstalk value meets the requirement of the target crosstalk value, the current design parameter range is considered appropriate and is determined as the target design parameter. If the target crosstalk value is not met, it is necessary to return to step S2, select a new quantum chip routing model, and re-perform the parametric scan simulation until a design parameter range that meets the target crosstalk value is found.

[0078] Therefore, by using the target crosstalk value as a guide, we ensure that the direction of design optimization is consistent with the final performance requirements. Through iterative methods, we can quickly converge to the optimal design parameters, improving design efficiency and reducing unnecessary simulations. By comparing the final design parameters with the target crosstalk value, we ensure that the final design parameters meet performance requirements, reducing product development risks.

[0079] In a specific application, when a preset number of new quantum chip wiring models fail to find a design parameter range that satisfies the target crosstalk value, a prompt message is sent to the operator's user equipment. The user equipment could be a laptop, mobile phone, or computer.

[0080] In an optional implementation, the frequency domain crosstalk S-parameters include near-end frequency domain S-parameters and far-end frequency domain S-parameters; for any quantum chip routing model, when the far-end crosstalk value obtained based on the simulation reference information meets the target crosstalk value, the currently acquired design parameter range is used as the target design parameter, including:

[0081] Using simulation software, the design parameters of the trapezoidal structure of the quantum chip wiring model are adjusted, and the design parameters that meet the preset design requirements are used as a set of design parameters. The set of design parameters is used to indicate the range of design parameters for the trapezoidal structure of the quantum chip wiring model.

[0082] When the set of design parameters is empty, it is considered that the far-end crosstalk value obtained based on the simulation reference information does not meet the target crosstalk value; otherwise, the set of design parameters is taken as the target design parameter.

[0083] The design requirements include: under the premise that the impedance change is within a preset impedance change range and the near-end crosstalk change is within a preset near-end crosstalk change range, the far-end crosstalk should reach a preset far-end crosstalk range.

[0084] Using simulation software and based on simulation reference information, the design parameters (spacing S, upper width w1, lower width w2, height h) of the trapezoidal structure in the quantum chip wiring model are adjusted. The design parameters that meet the preset design requirements are then grouped together to form a design parameter set. This set indicates the range of design parameters for the trapezoidal structure, which has been verified through simulation to meet the specific performance requirements. If the design parameter set is empty, meaning no parameter combination meeting the design requirements is found, the far-end crosstalk value is considered not to meet the target value. If the design parameter set is not empty, meaning a parameter combination meeting the design requirements is found, these parameters are used as the target design parameters. The design requirements include maintaining impedance variation and near-end crosstalk variation within preset ranges while keeping far-end crosstalk within preset ranges.

[0085] Therefore, by precisely adjusting the design parameters of the trapezoidal structure, far-end crosstalk can be effectively controlled to meet specific performance requirements. Simulation verification ensures that the design parameter set meets the preset requirements for impedance, near-end crosstalk, and far-end crosstalk, reducing product development risks.

[0086] In a specific application, a method for constructing a wiring model for a quantum chip layout is provided, the method comprising:

[0087] Step S1: Obtain simulation reference information. The simulation reference information is obtained by performing impedance simulation and crosstalk simulation using a quantum chip wiring model. The simulation reference information includes time-domain impedance values ​​and frequency-domain crosstalk S-parameters. The frequency-domain crosstalk S-parameters include near-end frequency-domain S-parameters and far-end frequency-domain S-parameters.

[0088] Step S2: Based on the quantum chip wiring model, establish at least one quantum chip wiring model that includes coplanar waveguide traces and a trapezoidal structure. The design parameters of the trapezoidal structure include the spacing S, the upper width w1, the lower width w2, and the height h. The expression of the parameterized model of the quantum chip wiring model is as follows: F = f(S, w1, w2, h).

[0089] Where F represents the magnitude of the far-end crosstalk;

[0090] The simulation software was used to perform parametric scanning simulation on each of the quantum chip wiring models to obtain the design parameter range of each of the quantum chip wiring models;

[0091] Step S3: Based on the currently obtained design parameter range, obtain the far-end crosstalk value using the expression of the parameterized model of the quantum chip wiring model;

[0092] For any quantum chip wiring model, simulation software is used to adjust the design parameters of the trapezoidal structure of the quantum chip wiring model. The design parameters that meet the preset design requirements are used as a set of design parameters, which are used to indicate the range of design parameters for the trapezoidal structure of the quantum chip wiring model.

[0093] When the design parameter set is empty, it is considered that the far-end crosstalk value obtained based on the simulation reference information does not meet the target crosstalk value, and step S2 is executed until the target design parameter is obtained; otherwise, the design parameter set is used as the target design parameter.

[0094] The quantum chip routing model is adjusted according to the target design parameter range, and the adjusted quantum chip routing model is used as the target quantum chip routing model.

[0095] The quantum chip routing model is obtained based on any one or more of the coplanar waveguide transmission lines described in Example 1, and the target design parameters include the design parameters of the trapezoidal structure corresponding to the quantum chip routing model.

[0096] For any quantum chip routing model, when the far-end crosstalk value obtained based on the simulation reference information meets the target crosstalk value, the currently acquired design parameter range is used as the target design parameter, including:

[0097] Using simulation software, the design parameters of the trapezoidal structure of the quantum chip wiring model are adjusted, and the design parameters that meet the preset design requirements are used as a set of design parameters. The set of design parameters is used to indicate the range of design parameters for the trapezoidal structure of the quantum chip wiring model.

[0098] When the set of design parameters is empty, it is considered that the far-end crosstalk value obtained based on the simulation reference information does not meet the target crosstalk value; otherwise, the set of design parameters is taken as the target design parameter.

[0099] The design requirements include: under the premise that the impedance change is within a preset impedance change range and the near-end crosstalk change is within a preset near-end crosstalk change range, the far-end crosstalk should reach a preset far-end crosstalk range.

[0100] Example 4

[0101] This embodiment provides a wiring structure construction apparatus, which includes a memory and a processor. The memory has a computer program that can run on the processor. When the processor executes the program, it implements the steps of the method described in any one of Embodiment 3.

[0102] Example 5

[0103] This embodiment provides a computer storage medium storing a computer program, and the computer program, when executed, causes the device containing the computer storage medium to perform the steps of the method according to any one of Embodiment 3.

[0104] Example 6

[0105] This embodiment provides a program product, including a computer program, which, when executed by a processor, implements the method described in any one of Embodiment 3.

[0106] Although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0107] The detailed descriptions listed above are merely specific descriptions of feasible implementation methods of this application and are not intended to limit the scope of protection of this application. All equivalent implementation methods or modifications made without departing from the spirit of the art of this application should be included within the scope of protection of this application.

Claims

1. An in-plane waveguide transmission line for quantum devices, characterized in that, The application relates to a quantum device, which comprises: a center strip for electric signal transmission of the quantum device; a ground strip arranged on both sides of the center strip and leaving a gap between the center strip and the ground strip, which serves as a ground; a ladder module comprising a plurality of ladder units arranged at equal intervals on any side of the center strip, which is used for providing capacitive impedance.

2. The coplanar waveguide transmission line of claim 1, wherein, The ground strip comprises a first ground strip, a second ground strip and a third ground strip, which are arranged at equal intervals in parallel; The center strip comprises a first center strip and a second center strip, wherein the first center strip is arranged in parallel between the first ground strip and the second ground strip, and the second center strip is arranged in parallel between the second ground strip and the third ground strip; The plurality of ladder units comprises a first ladder unit part arranged on any side of the first center strip and a second ladder unit part arranged on any side of the second center strip.

3. The coplanar waveguide transmission line of claim 2, wherein, The first ladder unit part and the second ladder unit part are arranged in symmetry with the second ground strip as a central axis, or the first ladder unit part and the second ladder unit part are arranged in alternation with the second ground strip as a central axis.

4. A quantum chip, characterized by The application relates to a quantum device, which comprises: a substrate; a quantum device arranged on the substrate; a coplanar waveguide transmission line connected with the quantum device, wherein the coplanar waveguide transmission line is the coplanar waveguide transmission line according to any one of claims 1-3.

5. A method for constructing a wiring model of a quantum chip layout, characterized by, The method comprises: S1, obtaining simulation reference information, wherein the simulation reference information is obtained through impedance simulation and crosstalk simulation of a quantum chip wiring model, the simulation reference information comprises time domain impedance values and frequency domain crosstalk S parameters; S2, on the basis of the quantum chip wiring model, obtaining at least one quantum chip wiring model, and performing parameterized scanning simulation on each quantum chip wiring model by using simulation software to obtain a design parameter range of each quantum chip wiring model; S3, according to the simulation reference information, selecting a target design parameter range from the design parameter range of each quantum chip wiring model, and adjusting the quantum chip wiring model corresponding to the target design parameter range according to the target design parameter range, taking the adjusted quantum chip wiring model as a target quantum chip wiring model; wherein the quantum chip wiring model is obtained according to any one or more of the coplanar waveguide transmission lines according to claims 1-3, and the target design parameter comprises a design parameter of a ladder structure corresponding to the quantum chip wiring model.

6. The method of constructing a wiring model according to claim 5, wherein, The method comprises: On the basis of the quantum chip wiring model, a quantum chip wiring model containing coplanar waveguide wiring and trapezoidal structure is established, design parameters of the trapezoidal structure include spacing S of the trapezoidal structure, upper width w1, lower width w2 and height h of the trapezoidal structure, and an expression of a parameterized model of the quantum chip wiring model is as follows: F=f(S,w1,w2,h) Wherein, F represents far-end crosstalk size.

7. The method of constructing a wiring model according to claim 5, wherein, The step S3 comprises: According to the current obtained design parameter range, the expression of the parameterized model of the quantum chip wiring model is used to obtain far-end crosstalk value; When the far-end crosstalk value obtained according to the simulation reference information meets the target crosstalk value, the current obtained design parameter range is taken as the target design parameter; otherwise, step S2 is executed.

8. The method of constructing a wiring model according to claim 7, wherein, The frequency domain crosstalk S parameter includes near-end frequency domain S parameter and far-end frequency domain S parameter; For any quantum chip wiring model, when the far-end crosstalk value obtained according to the simulation reference information meets the target crosstalk value, the current obtained design parameter range is taken as the target design parameter, comprising: Using simulation software, adjusting the design parameters of the trapezoidal structure of the quantum chip wiring model, taking the design parameters meeting the preset design requirements as a design parameter set, the design parameter set is used to indicate the design parameter range of the trapezoidal structure of the quantum chip wiring model; When the design parameter set is empty set, it is considered that the far-end crosstalk value obtained according to the simulation reference information does not meet the target crosstalk value; otherwise, the design parameter set is taken as the target design parameter; The design requirements include: under the premise that the change of impedance is in the preset impedance change range and the change of near-end crosstalk is in the preset near-end crosstalk change range, making the far-end crosstalk reach the preset far-end crosstalk preset range.

9. A wiring model construction device characterized by comprising: The construction device comprises a memory and a processor, the memory has a computer program which can run on the processor, and the processor executes the program to realize the steps of the method in any one of claims 5-8.

10. A computer storage medium, characterized in that, The computer program is stored in the computer storage medium, and the computer program runs to cause the device where the computer storage medium is located to execute the steps of the method according to any one of claims 5-8.

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