Server control method and apparatus, device, medium and computer program product

Abstract

The embodiments of the present application relate to the technical field of computers. Provided are a server control method and apparatus, a device, a medium and a computer program product. The method comprises: if a multiplexer receives a first control signal sent by a complex programmable logic device, sending a first reset signal to a high-speed serial bus endpoint module in a baseboard management controller by means of a target host; if the baseboard management controller detects the first reset signal, sending a second reset signal to a high-speed serial bus module of a field programmable gate array by means of the baseboard management controller; and if the multiplexer receives a second control signal sent by the complex programmable logic device, sending a third reset signal to the high-speed serial bus module of the field programmable gate array by means of the baseboard management controller. The embodiments of the present application ensure normal communication between the baseboard management controller and the field programmable gate array.

Description

Server control methods, devices, equipment, media, and computer program products

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410994120.1, filed on July 24, 2024, entitled “Server Control Method, Apparatus, Device, Medium and Computer Program Product”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a server control method, apparatus, device, medium, and computer program product. Background Technology

[0004] With the rise of big data and AI (Artificial Intelligence), the market demand for servers with high computing performance is increasing. The Grace (NVIDIA's data center processor) platform was developed to meet this need, combining NVIDIA's expertise with Arm processors, on-chip architecture, system-on-a-chip design, and flexible high-bandwidth, low-power memory technology to create the world's first superchip for computing. At the heart of this superchip is NVLink (NVIDIA's high-speed chip-to-chip interconnect technology) chip-to-chip (C2C) interconnect technology, which allows NVIDIA Grace CPUs (Central Processing Units) to communicate with another NVIDIA Grace CPU or NVIDIA Hopper GPU within the superchip at a bidirectional bandwidth of 900 GB / s (Gigabytes per second).

[0005] In the Grace C2 architecture platform, the Baseboard Management Controller (BMC) acts as a PCIe RC (Peripheral Component Interconnect Express Root Complex) to communicate with devices such as FPGAs via MCTP (Management Component Transport Protocol over PCI Express). In a design integrating a graphics and remote management controller BMC chip (ASPEED AST2600), the MCTP Controller attached to the PCIe RC / EP (Root Complex / Endpoint) shares a single MCTP Reset signal. The BMC not only provides VGA (Video Graphics Array) functionality to the host as a PCIe EP but also performs MCTP over PCIe communication with the FPGA as a PCIe RC.

[0006] However, when the BMC acts as a PCIe EP to provide VGA functionality to the host, the MCTP Reset signal is controlled by the HOST. This causes interference with the normal communication between the BMC and the FPGA when the HOST resets the VGA module. Furthermore, because the BMC cannot sense the reset timing of the PCIe EP, it cannot handle the interference with the normal communication between the BMC and the FPGA in a timely manner. Summary of the Invention

[0007] The purpose of some embodiments of this application is to provide a server control method, apparatus, device, medium, and computer program product, the specific technical solutions of which are as follows:

[0008] In a first aspect of some embodiments of this application, a method is provided for use with a target server, including a target host, a complex programmable logic device, a field-programmable gate array, a baseboard management controller, and a multiplexer, comprising:

[0009] If the multiplexer receives the first control signal sent by the complex programmable logic device, it sends the first reset signal to the high-speed serial bus endpoint module in the baseboard management controller through the target host.

[0010] If the baseboard management controller detects the first reset signal, it sends a second reset signal to the high-speed serial bus module of the field-programmable gate array (FPGA) to ensure normal communication between the baseboard management controller and the FPGA.

[0011] If the multiplexer receives a second control signal from a complex programmable logic device, it sends a third reset signal to the high-speed serial bus module of the field-programmable gate array through the board management controller, thereby ensuring normal communication between the board management controller and the field-programmable gate array.

[0012] In some embodiments of this application, the baseboard management controller includes a first pin, a second pin, a third pin, a reset pin, and an auxiliary reset pin. A first control signal controls the multiplexer to activate the first link, and a second control signal controls the multiplexer to activate the second link. The first pin is connected to the multiplexer and is used to obtain the activation status of the links within the multiplexer.

[0013] The second pin is connected to the field-programmable gate array (FPGA) and ensures normal communication between the board management controller and the FPGA when it is at a high level.

[0014] The third pin is connected to the target host and is used to obtain the power-on status of the target host;

[0015] The reset pin is connected to the multiplexer, and the state of the level signal is controlled by the target host or the board management controller.

[0016] The auxiliary reset pin is connected to the multiplexer, and the state of the level signal is controlled by the baseboard management controller.

[0017] In some embodiments of this application, complex programmable logic devices are used to control the power state of the target host and control the multiplexer to switch links;

[0018] The baseboard management controller is used to provide video graphics array output function for the target host, conduct target communication with the field programmable gate array through the communication protocol between intelligent devices based on the peripheral component interconnection fast link, and control the state of the level signals of the pins within the baseboard management controller.

[0019] Multiplexers are used to switch links to select the reset signal controlled by the board management controller or the target host.

[0020] In some embodiments of this application, the multiplexer includes a fourth pin, a fifth pin, and a sixth pin;

[0021] The fourth pin is connected to the target host, the fifth pin is connected to the auxiliary reset pin, and the sixth pin is connected to the reset pin;

[0022] The second link refers to the link connected by pins 5 and 6;

[0023] The first link refers to the link connected by the fourth and sixth pins, where each pin includes both high and low level signal states.

[0024] In some embodiments of this application, if the multiplexer receives a second control signal from a complex programmable logic device, it sends a third reset signal to the high-speed serial bus module of the field-programmable gate array via the board management controller, including:

[0025] When the target server is powered on and the target host is powered off, if the multiplexer receives a second control signal from the complex programmable logic device, it controls the multiplexer to establish the target link.

[0026] If the target link is determined to be the second link by the first pin of the baseboard management controller, the working status of the baseboard management controller is obtained.

[0027] If the working state is normal, the auxiliary reset pin, the second pin and the reset pin will output a high level and send a third reset signal to the high-speed serial bus module of the field programmable gate array through the baseboard management controller.

[0028] In some embodiments of this application, after obtaining the operating status of the baseboard management controller, the method further includes:

[0029] If the working state is abnormal, the auxiliary reset pin is controlled, and the second pin is at a low level;

[0030] The level signal of the auxiliary reset pin is transmitted to the reset pin through the second link;

[0031] The control reset pin outputs a low level.

[0032] In some embodiments of this application, if the multiplexer receives a first control signal sent by a complex programmable logic device, it sends a first reset signal to the high-speed serial bus endpoint module within the baseboard management controller via the target host, including:

[0033] If the multiplexer receives the first control signal sent by the complex programmable logic device, it controls the multiplexer to open the target link;

[0034] When the target link is determined to be the first link by the first pin, the first reset signal is sent by the target host to the high-speed serial bus endpoint module in the baseboard management controller.

[0035] In some embodiments of this application, if the baseboard management controller detects a first reset signal, it sends a second reset signal to the high-speed serial bus module of the field-programmable gate array, including:

[0036] If the baseboard management controller detects the first reset signal, it obtains the power-on status of the target host;

[0037] If the target host is powered on, a second reset signal is sent to the high-speed serial bus module of the field-programmable gate array through the baseboard management controller.

[0038] In some embodiments of this application, before the baseboard management controller detects the first reset signal and obtains the power-on state of the target host, the method further includes:

[0039] If the target host is in a powered-off state, a power-on command is sent to the complex programmable logic device through the baseboard management controller;

[0040] Alternatively, in response to the user's input of the power button on the target host, a power-on command is sent to the complex programmable logic device;

[0041] The target host is controlled to enter the power-on preparation state by the power-on command;

[0042] After waiting for the preset target time, control the target host to enter the power-on state.

[0043] In some embodiments of this application, after controlling the target host to enter the power-on preparation state via a power-on command, the method further includes:

[0044] The third pin and the fourth pin inside the multiplexer are kept at a low level, and a synchronization strategy is set for the auxiliary reset pin and the second pin with the level signal of the third pin;

[0045] The first level signal state of the fourth pin is sent to the reset pin via the first link;

[0046] The control reset pin is at a low level.

[0047] In some embodiments of this application, after setting a level signal synchronization strategy between the auxiliary reset pin and the second pin and the third pin, the method further includes:

[0048] The auxiliary reset pin and the second pin are adjusted to low level by the first level signal state of the third pin.

[0049] In some embodiments of this application, the target server further includes: a management component, a transport protocol controller;

[0050] After adjusting the auxiliary reset pin and the second pin to low level through the first level signal state of the third pin, the following is also included:

[0051] The substrate management controller and the management component transmission protocol controller enter the reset state;

[0052] Communication between the baseboard management controller and the field-programmable gate array is abnormal.

[0053] In some embodiments of this application, after waiting for a preset target time, the target host is controlled to enter the power-on state, including:

[0054] The complex programmable logic device controls the board management controller to maintain a reset state and starts the first timer;

[0055] Once the duration of the first timer reaches the target preset duration, the target host is controlled to enter the power-on state.

[0056] In some embodiments of this application, after determining that the duration of the first timer has reached the target preset duration, and controlling the target host to enter the power-on state, the method further includes:

[0057] The first reset signal is sent through the reset output pin of the target host;

[0058] The rising edge change at the third pin is controlled by the first reset signal;

[0059] The high level output of the third pin is determined by the rising edge change.

[0060] In some embodiments of this application, before controlling the target host to enter the power-on state after waiting for a preset target time, the method further includes:

[0061] Pre-register an edge-triggered interrupt for the third pin of the substrate management controller;

[0062] When an edge change occurs on the third pin, the edge change of the third pin is sent to the board management controller via an edge-triggered interrupt. The edge change includes a rising edge change from low level to high level and a falling edge change from high level to low level.

[0063] In some embodiments of this application, after the multiplexer receives a second control signal from a complex programmable logic device, and then sends a third reset signal to the high-speed serial bus module of the field-programmable gate array via the board management controller, the method includes:

[0064] When the target server is determined to be powered down, a falling edge change occurs at the third control pin.

[0065] The multiplexer is controlled by a complex programmable logic device to switch to the second link;

[0066] The falling edge change is sent to the substrate management controller so that the substrate management controller controls the auxiliary reset pin, and the second pin outputs a low level.

[0067] In a second aspect of this application, a server control device is also provided, applied to a target server, including a target host, a complex programmable logic device, a field-programmable gate array, a baseboard management controller, and a multiplexer. The device includes:

[0068] The first transmitting module is used to send a first reset signal to the high-speed serial bus endpoint module in the baseboard management controller through the target host if the multiplexer receives a first control signal sent by the complex programmable logic device.

[0069] The second transmitting module is used to send a second reset signal to the high-speed serial bus module of the field-programmable gate array (FPGA) through the baseboard management controller if the baseboard management controller detects the first reset signal, thereby ensuring normal communication between the baseboard management controller and the FPGA.

[0070] The third transmitting module is used to send a third reset signal to the high-speed serial bus module of the field-programmable gate array through the baseboard management controller if the multiplexer receives the second control signal sent by the complex programmable logic device, thereby ensuring normal communication between the baseboard management controller and the field-programmable gate array.

[0071] In a third aspect of this application, a communication device is also provided, comprising: a transceiver, a memory, a processor, and a program stored in the memory and executable on the processor;

[0072] A processor for reading programs from memory to implement server control methods such as any of the first aspects.

[0073] In a fourth aspect of this application, a computer non-volatile readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to implement any of the server control methods of the first aspect.

[0074] In a fifth aspect of this application, a computer program product is also provided, including a computer program / instructions that, when executed by a processor, implement any of the server control methods of the first aspect.

[0075] The server control method provided in some embodiments of this application is applied to a target server, including a target host, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a baseboard management controller (BJM), and a multiplexer. The method includes: if the multiplexer receives a first control signal sent by the CPLD, then the target host sends a first reset signal to a high-speed serial bus endpoint module within the BJM; if the BJM detects the first reset signal, then the BJM sends a second reset signal to the high-speed serial bus module of the FPGA, thereby ensuring normal communication between the BJM and the FPGA; if the multiplexer receives a second control signal sent by the CPLD, then the BJM sends a third reset signal to the high-speed serial bus module of the FPGA, thereby ensuring normal communication between the BJM and the FPGA. Some embodiments of this application use complex programmable logic devices to send different control signals to the multiplexer to sense the source of the current reset signal, which can handle abnormal problems in a timely manner. Moreover, when the target host controls the reset signal, the baseboard management controller will subsequently send a second reset signal to restore normal communication between the BMC and the FPGA. When the baseboard management controller controls the reset signal, it is not affected by the host, thus ensuring normal communication between the BMC and the FPGA. Attached Figure Description

[0076] To more clearly illustrate the technical solutions in some embodiments or related technologies of this application, the accompanying drawings used in the description of some embodiments or related technologies will be briefly introduced below.

[0077] Figure 1 is a design diagram of an integrated graphics and remote baseboard management controller chip provided in some embodiments of this application;

[0078] Figure 2 is an architecture diagram of the target server in the server control method provided in some embodiments of this application;

[0079] Figure 3 is a flowchart of the steps of a server control method provided in some embodiments of this application;

[0080] Figure 4 is a flowchart of step 102 in a server control method provided by some embodiments of this application shown in Figure 3;

[0081] Figure 5 is a flowchart of step 103 in a server control method provided by some embodiments of this application as shown in Figure 3;

[0082] Figure 6 is a flowchart of the power-on reset logic steps in a server control method provided by some embodiments of this application, as shown in Figure 3.

[0083] Figure 7 is a flowchart of the level tracking logic steps in a server control method provided by some embodiments of this application, as shown in Figure 3.

[0084] Figure 8 is a flowchart of the power-down reset logic steps in a server control method provided by some embodiments of this application, as shown in Figure 3.

[0085] Figure 9 is a device block diagram of a server control apparatus provided in some embodiments of this application;

[0086] Figure 10 is a schematic diagram of a communication device provided in some embodiments of this application. Detailed Implementation

[0087] To make the objectives, technical solutions, and advantages of some embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of some embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this application. Some embodiments can be combined with and referenced to each other without contradiction.

[0088] Referring to Figure 1, in a design of an integrated graphics and remote board management controller (BMC) chip (ASPEED AST2600), the Management Component Transport Protocol (MCTP) controller 1 and the Management Component Transport Protocol (MCTP) controller 2, which are attached to the PCIe RC / EP (Root Complex / Endpoint), share a single MCTP Reset signal via a power event reset signal pin. This means that the reset signal of PCIe1 simultaneously resets both MCTP controllers. When the host resets PCIe1, the MCTP controller is reset, which in turn interrupts the MCTP information on PCIe2. Because the reset signal of PCIe1 is unpredictable, this leads to an abnormal MCTP interruption, rendering monitoring information unusable.

[0089] Therefore, in some embodiments of this application, a new architecture is designed based on the Grace C2 platform. For example, as shown in Figure 2, the target server (Grace C2 platform) includes a target host, a complex programmable logic device (FPGA), a field-programmable gate array (FPGA), a baseboard management controller (BJC), and a multiplexer. The BJC includes a first pin, a second pin, a third pin, a reset pin, and an auxiliary reset pin. The first pin is connected to the multiplexer and is used to obtain the connection status of the links within the multiplexer. The second pin is connected to the FPGA and is high to ensure normal communication between the BJC and the FPGA. The third pin is connected to the target host and is used to obtain the power-on status of the target host. The reset pin is connected to the multiplexer and is controlled by the target host or the BJC to maintain the state of the level signal. The auxiliary reset pin is connected to the multiplexer and is controlled by the BJC to maintain the state of the level signal. The multiplexer includes pins 4, 5, and 6; pin 4 is connected to the target host, pin 5 is connected to the auxiliary reset pin, and pin 6 is connected to the reset pin; the second link refers to the link connected by pins 5 and 6, and a successful second link indicates that the reset signal is controlled by the board management controller; the first link refers to the link connected by pins 4 and 6, and a successful first link indicates that the reset signal is controlled by the target host. Each pin includes both high and low level signal states.

[0090] It should be noted that the complex programmable logic device (CPL) is used to control the power state of the target host and control the multiplexer to switch links; the baseboard management controller (BMC) is used to provide video graphics array output functions for the target host, conduct target communication with the field-programmable gate array (FPGA) based on the peripheral component interconnection fast link (PCIe) communication protocol, and control the level signal state of the pins within the BMC; the multiplexer is used to switch the target link to select whether the reset signal is controlled by the BMC or the target host; the target host is the main computing unit of the target server, and has an I2C (Inter-Integrated Circuit) link with the FPGA, transmitting monitoring information to the FPGA via the I2C link. The FPGA is the main component for system monitoring, collecting data such as CPU temperature information through the I2C link, and is responsible for providing monitoring information to the BMC. The BMC and FPGA communicate via MCTP over PCIe; if MCTP is abnormally interrupted, the FPGA will be unable to provide monitoring information to the BMC.

[0091] Based on the above architecture, a server control method is proposed in some embodiments of this application. Referring to FIG3, a flowchart of the steps of a server control method provided in some embodiments of this application is shown, the method may include:

[0092] Step 101: If the multiplexer receives the first control signal sent by the complex programmable logic device, it sends the first reset signal to the high-speed serial bus endpoint module in the baseboard management controller through the target host.

[0093] In some embodiments of this application, the complex programmable logic device may be an MB CPLD (Megabit Complex Programmable Logic Device). A CPLD (Complex Programming Logic Device) is an integrated circuit that contains multiple programmable logic blocks (PLDs) and programmable interconnect resources, allowing users to implement specific logic functions through programming. The "MB" in MB CPLD indicates that its storage capacity is measured in megabits, meaning it has a larger logic capacity and higher complexity, enabling more complex logic designs.

[0094] In some embodiments of this application, the first control signal indicates that the first link in the multiplexer is enabled, at which point the target host controls the reset signal. Specific steps include:

[0095] If the multiplexer receives the first control signal sent by the complex programmable logic device, it controls the multiplexer to open the target link;

[0096] When the target link is determined to be the first link by the first pin, the first reset signal is sent by the target host to the high-speed serial bus endpoint module in the baseboard management controller.

[0097] Step 102: If the baseboard management controller detects the first reset signal, it sends a second reset signal to the high-speed serial bus module of the field-programmable gate array through the baseboard management controller, thereby ensuring normal communication between the baseboard management controller and the field-programmable gate array.

[0098] In some embodiments of this application, after the baseboard management controller detects the first reset signal, it needs a complex programmable logic device to adjust the target host to a power-on state. When the target host is powered on, the baseboard management controller sends a second reset signal to the high-speed serial bus module of the field-programmable gate array to ensure normal communication between the baseboard management controller and the field-programmable gate array.

[0099] Further, referring to Figure 4, step 102 includes:

[0100] Step 1021: If the baseboard management controller detects the first reset signal, it obtains the power-on status of the target host.

[0101] Step 1022: If the target host is in the power-on state, a second reset signal is sent to the high-speed serial bus module of the field programmable gate array through the baseboard management controller.

[0102] It should be noted that in some embodiments of this application, the power state of the target host is controlled by a complex programmable logic device (CPLD). If the target host is in a powered-off state, a power-on signal needs to be sent to the CPLD. There are several ways the power-on signal can be generated, including when the BMC receives a power-on command (which may be sent remotely over a network or via a local management interface), it sends a signal to the CPLD to instruct it to begin the system's power-on process. Alternatively, the user can press the power button on the chassis; this action is detected by the system and converted into a power-on command, which is then sent to the CPLD. The CPLD will then begin executing the power-on process according to the received command. However, the power-on process takes time, so the target host is in a power-on preparation state before it is fully powered on. The specific steps include:

[0103] If the target host is in a powered-off state, a power-on command is sent to the complex programmable logic device through the baseboard management controller;

[0104] Alternatively, in response to the user's input of the power button on the target host, a power-on command is sent to the complex programmable logic device;

[0105] The target host is controlled to enter the power-on preparation state by the power-on command;

[0106] After waiting for the preset target time, control the target host to enter the power-on state.

[0107] During the aforementioned waiting period, preparatory work such as initializing hardware components, checking system status, and loading BIOS or UEFI firmware may also occur. This process demonstrates how to boot a computer system using different triggering mechanisms and ensure a smooth transition from shutdown to power-on. The CPLD plays a crucial role in this process because it is responsible for processing and executing boot commands, ensuring that the system's hardware and firmware respond correctly to the boot request.

[0108] Furthermore, after determining that the target host is in the power-on preparation state, since the target host is not fully powered on at this time, the third pin connected to the target host and the fourth pin in the multiplexer are in a low-level state due to the pull-down resistor. Moreover, since the first link is connected by the fourth and sixth pins in the multiplexer, and the fourth pin is connected to the target host and the sixth pin is connected to the reset pin of the board management controller, the first link sends the first-level signal state of the fourth pin to the reset pin. At the same time, since the target host is in the power-on preparation state, it will control the third pin to output a low level. The specific steps include:

[0109] The third pin and the fourth pin inside the multiplexer are kept at a low level, and a synchronization strategy is set for the auxiliary reset pin and the second pin with the level signal of the third pin;

[0110] The first level signal state of the fourth pin is sent to the reset pin via the first link;

[0111] The control reset pin is at a low level.

[0112] It should be noted that, since the reset signal of the reset pin is controlled by the target host at this time, the reset signal of the target host affects the communication between the board management controller and the field programmable gate array, causing the communication to be interrupted.

[0113] In addition, after the first link is established, the baseboard management controller loses control over the reset signal, and the target host takes over control of the reset signal. Therefore, the synchronous auxiliary reset pin and the second pin track the level signal state of the third pin. Thus, the auxiliary reset pin and the second pin are also adjusted to a low level. The specific steps include:

[0114] The auxiliary reset pin and the second pin are adjusted to low level by the first level signal state of the third pin.

[0115] Furthermore, the target server also includes: a management component transmission protocol controller; when the reset pin, auxiliary reset pin, and second pin are all low, the baseboard management controller enters a reset state, and the management component transmission protocol controller also enters a reset state. The baseboard management controller cannot communicate with the FPGA via MCTP Over PCIe. Specific steps include:

[0116] The substrate management controller and the management component transmission protocol controller enter the reset state;

[0117] Communication between the baseboard management controller and the field-programmable gate array is abnormal.

[0118] Additionally, the reset signal sent during the target host's power-on preparation will affect the communication between the board management controller and the field-programmable gate array (FPGA). However, this impact from the host is unavoidable. Therefore, the board management controller needs to remain in a reset state for a certain period, and a preset duration is set for this purpose. This duration is the maximum allowable waiting time. After this time is exceeded, the target host will enter the power-on state. The specific steps include:

[0119] The complex programmable logic device controls the board management controller to maintain a reset state and starts the first timer;

[0120] Once the duration of the first timer reaches the target preset duration, the target host is controlled to enter the power-on state.

[0121] For example, the target preset duration is set to 100ms. The complex programmable logic device (CPL) control board management controller remains in a reset state for 100ms, allowing the BMC AST2600EP / FPGA EP to complete the reset action. Afterward, the CPL controls the target host to enter the power-on state.

[0122] It should be noted that after the target host enters the power-on state during the above process, the third pin connected to the target host will experience a rising edge change. The BMC can detect this information because the BMC has pre-registered an edge-triggered interrupt for the third pin. When the edge of the third pin changes, the BMC will detect the level change of the third pin in the shortest possible time. The specific steps include:

[0123] Pre-register an edge-triggered interrupt for the third pin of the substrate management controller;

[0124] When an edge change occurs on the third pin, the edge change of the third pin is sent to the board management controller via an edge-triggered interrupt. The edge change includes a rising edge change from low level to high level and a falling edge change from high level to low level.

[0125] Furthermore, after the target host powers on, it first releases the first reset signal (i.e., the PCIe reset signal) through the target host's reset output pin. At this time, the BMC will detect a rising edge on the third pin, and the third pin will output a high level, which also includes:

[0126] The first reset signal is sent through the reset output pin of the target host;

[0127] The rising edge change at the third pin is controlled by the first reset signal;

[0128] The high level output of the third pin is determined by the rising edge change.

[0129] Step 103: If the multiplexer receives the second control signal sent by the complex programmable logic device, it sends a third reset signal to the high-speed serial bus module of the field-programmable gate array through the board management controller, thereby ensuring normal communication between the board management controller and the field-programmable gate array.

[0130] In some embodiments of this application, the target server refers to the Grace C2 platform. After the target server is powered on, the target host is initially in a powered-off state by default. When the target host is powered off, the complex programmable logic device sends a second control signal to control the multiplexer to establish the second link. Regarding the link within the multiplexer, in some embodiments of this application, a first pin is set for the board management controller, connected to the multiplexer, to obtain the connection status of the link within the multiplexer, thereby determining the source of the reset signal at this time. The establishment of the second link indicates that the reset signal is controlled by the board management controller. The second pin is connected to the field-programmable gate array (FPGA) and communicates normally when it is at a high level.

[0131] Since the second link being established indicates that the reset signal is controlled by the baseboard management controller, the target host will not affect the communication between the BMC and the FPGA. Therefore, it is only necessary to obtain the working status of the baseboard management controller to determine the communication status between the BMC and the FPGA.

[0132] Further, referring to Figure 5, step 103 includes:

[0133] Step 1031: When it is determined that the target server is powered on and the target host is powered off, if the multiplexer receives the second control signal sent by the complex programmable logic device, it controls the multiplexer to open the target link.

[0134] Step 1032: If the target link is determined to be the second link by the first pin of the baseboard management controller, the working status of the baseboard management controller is obtained.

[0135] Step 1033: If the working state is normal, control the auxiliary reset pin, the second pin and the reset pin to output a high level and send a third reset signal to the high-speed serial bus module of the field programmable gate array through the board management controller.

[0136] It should be noted that when the baseboard management controller is working normally, the auxiliary reset pin and the second pin will be at a high level by default. Because the first link is connected to the auxiliary reset pin and the reset pin, the auxiliary reset pin can transmit a high-level signal to the reset pin through the first link. Then, the reset pin will also output a high level based on the received information. At this time, the baseboard management controller will send a third reset signal to the high-speed serial bus module of the field-programmable gate array to ensure normal communication between the baseboard management controller and the field-programmable gate array.

[0137] However, while the baseboard management controller operates normally most of the time, malfunctions can occur. When a malfunction occurs, the auxiliary reset pin and the second pin need to be pulled low to output a low level. Similarly, a low-level signal is transmitted to the reset pin via the first link, and the reset pin then outputs a low level based on this received information. The specific steps include:

[0138] If the working state is abnormal, the auxiliary reset pin is controlled, and the second pin is at a low level;

[0139] The level signal of the auxiliary reset pin is transmitted to the reset pin through the second link;

[0140] The control reset pin outputs a low level.

[0141] When the reset pin outputs a low level, the board management controller and the field-programmable gate array (FPGA) will communicate abnormally, and an attempt will be made to restore normal system operation. The above steps demonstrate how to determine whether a system reset is needed based on the BMC's operating state, and how to achieve this operation by controlling different pins. This mechanism helps ensure that the system can be reset promptly when problems occur, thereby improving system stability and reliability.

[0142] In addition, some embodiments of this application also include a system power-down scenario. In this scenario, the target host's reset output pin has no output level, and the third pin remains low due to the pull-down resistor. At this time, a falling edge interrupt is triggered on the third pin. The complex programmable logic device controls the first link to be turned on via the reset selection pin. The board management controller then pulls the auxiliary reset pin low, and the second pin signal causes the AST2600EP / MCTP and FPGA EP to enter a reset state. The specific steps include:

[0143] When the target server is determined to be powered down, a falling edge change occurs at the third control pin.

[0144] The multiplexer is controlled by a complex programmable logic device to switch to the second link;

[0145] The falling edge change is sent to the substrate management controller so that the substrate management controller controls the auxiliary reset pin, and the second pin outputs a low level.

[0146] Afterwards, the BMC senses the reset signal through the first pin and obtains the permission control. After 100ms, the BMC releases the auxiliary reset pin and the second pin reset signal, and the AST2600EP / MCTP and FPGA EP enter normal working state.

[0147] The above process includes power-on reset logic, as shown in Figure 6. The complex programmable logic device receives the power-on command and establishes the first link. At this time, the board management controller synchronizes the status of the auxiliary reset pin and the second pin. The complex programmable logic device controls the target host to prepare for power-on. After the target host is powered on, the board management controller senses the reset output signal of the high-speed serial bus module on the target host through the third pin.

[0148] It also includes the level tracking logic of the third pin of the board management controller. As shown in Figure 7, the BMC registers the edge-triggered interrupt of the third pin. When the third pin detects a falling edge, it synchronizes a low level to the auxiliary reset pin and the second pin through a level signal synchronization strategy, and the high-speed serial bus module is reset (i.e., the communication between the board management controller and the field programmable gate array is interrupted). When the third pin detects a rising edge, it synchronizes a high level to the auxiliary reset pin and the second pin through a level signal synchronization strategy, and the high-speed serial bus module enters the normal working state (the board management controller communicates normally with the field programmable gate array).

[0149] It also includes power-down reset logic, as shown in Figure 8. When the complex programmable logic device receives the power-down command, the target host is powered down, and the second link is established. At this time, the board management controller synchronizes the status of the auxiliary reset pin and the second pin. After 100ms, the voltage of the auxiliary reset pin and the second pin is pulled high to restore normal communication between the board management controller and the field programmable gate array.

[0150] The server control method provided in some embodiments of this application is applied to a target server, including a target host, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a baseboard management controller (BJM), and a multiplexer. The method includes: if the multiplexer receives a first control signal sent by the CPLD, then the target host sends a first reset signal to a high-speed serial bus endpoint module within the BJM; if the BJM detects the first reset signal, then the BJM sends a second reset signal to the high-speed serial bus module of the FPGA, thereby ensuring normal communication between the BJM and the FPGA; if the multiplexer receives a second control signal sent by the CPLD, then the BJM sends a third reset signal to the high-speed serial bus module of the FPGA, thereby ensuring normal communication between the BJM and the FPGA. Some embodiments of this application use complex programmable logic devices to send different control signals to the multiplexer to sense the source of the current reset signal, which can handle abnormal problems in a timely manner. Moreover, when the target host controls the reset signal, the baseboard management controller will subsequently send a second reset signal to restore normal communication between the BMC and the FPGA. When the baseboard management controller controls the reset signal, it is not affected by the host, thus ensuring normal communication between the BMC and the FPGA.

[0151] Referring to Figure 9, a schematic diagram of a server control device provided in some embodiments of this application is shown. Applied to a target server, the device includes a target host, a complex programmable logic device (CLP), a field-programmable gate array (FPGA), a baseboard management controller, and a multiplexer. The device includes:

[0152] The first transmitting module 201 is used to transmit a first reset signal to the high-speed serial bus endpoint module in the baseboard management controller through the target host if the multiplexer receives a first control signal transmitted by the complex programmable logic device.

[0153] The second transmitting module 202 is used to send a second reset signal to the high-speed serial bus module of the field-programmable gate array (FPGA) through the baseboard management controller if the baseboard management controller detects the first reset signal, thereby ensuring normal communication between the baseboard management controller and the FPGA.

[0154] The third transmitting module 203 is used to send a third reset signal to the high-speed serial bus module of the field-programmable gate array through the baseboard management controller if the multiplexer receives the second control signal sent by the complex programmable logic device, thereby ensuring normal communication between the baseboard management controller and the field-programmable gate array.

[0155] In some embodiments of this application, the baseboard management controller includes a first pin, a second pin, a third pin, a reset pin, and an auxiliary reset pin. A first control signal controls the multiplexer to activate a first link, and a second control signal controls the multiplexer to activate a second link. The first pin is connected to the multiplexer and is used to obtain the activation status of the links within the multiplexer.

[0156] The second pin is connected to the field-programmable gate array (FPGA) and ensures normal communication between the board management controller and the FPGA when it is at a high level.

[0157] The third pin is connected to the target host and is used to obtain the power-on status of the target host.

[0158] The reset pin is connected to the multiplexer, and the state of the level signal is controlled by the target host or board management controller.

[0159] The auxiliary reset pin is connected to the multiplexer, and the state of the level signal is controlled by the baseboard management controller.

[0160] In some embodiments of this application, complex programmable logic devices are used to control the power state of the target host and control the multiplexer to switch the target link.

[0161] The board management controller is used to provide video graphics array output functions for the target host, conduct target communication with the field programmable gate array (FPGA) through a communication protocol between intelligent devices based on a high-speed interconnection link for peripheral components, and control the state of the level signals of the pins within the board management controller.

[0162] Multiplexers are used to switch links to select the reset signal controlled by the board management controller or the target host.

[0163] In some embodiments of this application, the multiplexer includes a fourth pin, a fifth pin, and a sixth pin.

[0164] The fourth pin is connected to the target host, the fifth pin is connected to the auxiliary reset pin, and the sixth pin is connected to the reset pin.

[0165] The second link refers to the link connected by pins 5 and 6.

[0166] The first link refers to the link connected by the fourth and sixth pins, where each pin includes both high and low level signal states.

[0167] In some embodiments of this application, the third sending module 203 specifically includes:

[0168] The first control submodule is used to control the multiplexer to establish the target link when the target server is powered on and the target host is powered off, if the multiplexer receives a second control signal sent by the complex programmable logic device.

[0169] The first acquisition submodule is used to acquire the operating status of the baseboard management controller when the target link is determined to be the second link through the first pin of the baseboard management controller.

[0170] The second control submodule is used to control the auxiliary reset pin if the working state is normal. The second pin and the reset pin output a high level and send a third reset signal to the high-speed serial bus module of the field programmable gate array through the board management controller.

[0171] The third control submodule is used to control the auxiliary reset pin if the working state is abnormal, and the second pin is at a low level.

[0172] The first transmission submodule is used to transmit the level signal of the auxiliary reset pin to the reset pin via the second link.

[0173] The fourth control submodule is used to control the reset pin to output a low level.

[0174] In some embodiments of this application, the first sending module 201 specifically includes:

[0175] The fifth control submodule is used to control the multiplexer to establish the target link if the multiplexer receives the first control signal sent by the complex programmable logic device.

[0176] The first transmitting submodule is used to send a first reset signal to the high-speed serial bus endpoint module in the baseboard management controller through the target host when the target link is determined to be the first link by the first pin.

[0177] In some embodiments of this application, the second sending module 202 specifically includes:

[0178] The second acquisition submodule is used to acquire the power-on status of the target host if the baseboard management controller detects the first reset signal.

[0179] The second transmitting submodule is used to send a second reset signal to the high-speed serial bus module of the field-programmable gate array through the baseboard management controller if the target host is in the power-on state.

[0180] The third transmitting submodule is used to send a power-on command to the complex programmable logic device through the baseboard management controller if the target host is in a powered-off state.

[0181] Alternatively, in response to the user's input of the power button on the target host, a power-on command is sent to the complex programmable logic device.

[0182] The sixth control submodule is used to control the target host to enter the power-on preparation state through the power-on command.

[0183] The seventh control submodule is used to control the target host to enter the power-on state after waiting for the target preset time.

[0184] The eighth control submodule is used to control the third pin and the fourth pin in the multiplexer to be at a low level, and to set a synchronization strategy between the auxiliary reset pin and the second pin and the level signal of the third pin.

[0185] The fourth transmitting submodule is used to transmit the first level signal state of the fourth pin to the reset pin via the first link.

[0186] The ninth control submodule is used to control the reset pin to be at a low level.

[0187] The first adjustment submodule is used to adjust the auxiliary reset pin and the second pin to a low level by means of the first level signal state of the third pin.

[0188] In some embodiments of this application, the target server further includes a management component, a transport protocol controller.

[0189] The baseboard management controller and the management component transmission protocol controller enter the reset state.

[0190] Communication between the baseboard management controller and the field-programmable gate array is abnormal.

[0191] The timing submodule is used to control the board management controller to maintain a reset state and start the first timer via a complex programmable logic device.

[0192] The ninth control submodule is used to control the target host to enter the power-on state when the timing duration of the first timer reaches the target preset duration.

[0193] The fourth transmitting submodule is used to transmit the first reset signal through the reset output pin of the target host.

[0194] The tenth control submodule is used to control the rising edge change at the third pin through the first reset signal.

[0195] The first determining submodule is used to determine the high level output of the third pin by the rising edge change.

[0196] The registration submodule is used to pre-register edge-triggered interrupts for the third pin of the baseboard management controller.

[0197] The fifth transmitting submodule is used to send the edge change of the third pin to the board management controller through an edge-triggered interrupt when an edge change occurs on the third pin. The edge change includes a rising edge change from low level to high level and a falling edge change from high level to low level.

[0198] In some embodiments of this application, the server control device further includes:

[0199] The first control module is used to control the falling edge change at the third pin when it is determined that the target server is powered down.

[0200] The second control module is used to control the multiplexer to switch to the second link through a complex programmable logic device.

[0201] The fourth transmitting module is used to send the falling edge change to the substrate management controller so that the substrate management controller controls the auxiliary reset pin and the second pin outputs a low level.

[0202] The server control method provided in some embodiments of this application is applied to a target server, including a target host, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a baseboard management controller (BJM), and a multiplexer. The method includes: if the multiplexer receives a first control signal sent by the CPLD, then the target host sends a first reset signal to a high-speed serial bus endpoint module within the BJM; if the BJM detects the first reset signal, then the BJM sends a second reset signal to the high-speed serial bus module of the FPGA, thereby ensuring normal communication between the BJM and the FPGA; if the multiplexer receives a second control signal sent by the CPLD, then the BJM sends a third reset signal to the high-speed serial bus module of the FPGA, thereby ensuring normal communication between the BJM and the FPGA. Some embodiments of this application use complex programmable logic devices to send different control signals to the multiplexer to sense the source of the current reset signal, which can handle abnormal problems in a timely manner. Moreover, when the target host controls the reset signal, the baseboard management controller will subsequently send a second reset signal to restore normal communication between the BMC and the FPGA. When the baseboard management controller controls the reset signal, it is not affected by the host, thus ensuring normal communication between the BMC and the FPGA.

[0203] Some embodiments of this application also provide a communication device, as shown in FIG10, including a processor 301, a communication interface 302, a memory 303, and a communication bus 304, wherein the processor 301, the communication interface 302, and the memory 303 communicate with each other through the communication bus 304.

[0204] Memory 303 is used to store computer programs;

[0205] When processor 301 executes the program stored in memory 303, it can perform the following steps:

[0206] If the multiplexer receives the first control signal sent by the complex programmable logic device, it sends the first reset signal to the high-speed serial bus endpoint module in the baseboard management controller through the target host.

[0207] If the baseboard management controller detects the first reset signal, it sends a second reset signal to the high-speed serial bus module of the field-programmable gate array (FPGA) to ensure normal communication between the baseboard management controller and the FPGA.

[0208] If the multiplexer receives a second control signal from a complex programmable logic device, it sends a third reset signal to the high-speed serial bus module of the field-programmable gate array through the board management controller, thereby ensuring normal communication between the board management controller and the field-programmable gate array.

[0209] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and the memory. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor can be transmitted over a wired medium or wirelessly via an antenna, which further receives and transmits data to the processor. The processor manages the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management, and other control functions. The memory can be used to store data used by the processor during operation.

[0210] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0211] The communication interface is used for communication between the aforementioned terminal and other devices.

[0212] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. In some embodiments of this application, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0213] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0214] In other embodiments provided in this application, a computer non-volatile readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform any of the server control methods described in the above embodiments.

[0215] In other embodiments provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the server control methods described in the above embodiments.

[0216] In some of the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to some embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer non-volatile readable storage medium or transmitted from one computer non-volatile readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer non-volatile readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0217] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0218] Some embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Some embodiments focus on describing the differences from other embodiments. In particular, system embodiments are basically similar to method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0219] The above are merely some preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A server control method characterized by comprising: The method is applied to a target server, including a target host, a complex programmable logic device, a field programmable gate array, a baseboard management controller, a multiplexer, and the method comprises: If the multiplexer receives a first control signal sent by the complex programmable logic device, a first reset signal is sent to a high-speed serial bus endpoint module in the baseboard management controller through the target host; If the baseboard management controller detects the first reset signal, a second reset signal is sent to a high-speed serial bus module of the field programmable gate array through the baseboard management controller, so as to ensure normal communication between the baseboard management controller and the field programmable gate array; If the multiplexer receives a second control signal sent by the complex programmable logic device, a third reset signal is sent to the high-speed serial bus module of the field programmable gate array through the baseboard management controller, so as to ensure normal communication between the baseboard management controller and the field programmable gate array.

2. The server control method according to claim 1, wherein The baseboard management controller comprises a first pin, a second pin, a third pin, a reset pin and an auxiliary reset pin, the first control signal controls the multiplexer to open the first link, the second control signal controls the multiplexer to open the second link, the first pin is in communication with the multiplexer and is configured to obtain the opening state of the link in the multiplexer; The second pin is in communication with the field programmable gate array and ensures normal communication between the baseboard management controller and the field programmable gate array when it is at a high level; The third pin is in communication with the target host and is configured to obtain the power-on state of the target host; The reset pin is in communication with the multiplexer and is controlled by the target host or the baseboard management controller to control the state of the level signal; The auxiliary reset pin is in communication with the multiplexer and is controlled by the baseboard management controller to control the state of the level signal.

3. The server control method according to claim 1, wherein The complex programmable logic device is configured to control the power state of the target host and control the multiplexer to switch the link; The baseboard management controller is configured to provide a video graphics array output function for the target host, target communication based on a peripheral component interconnect express link intelligent device communication protocol between the baseboard management controller and the field programmable gate array, and control the state of the level signal of the pin in the baseboard management controller; The multiplexer is configured to switch the link to select the reset signal controlled by the baseboard management controller or the target host.

4. The server control method according to claim 2, wherein The multiplexer comprises a fourth pin, a fifth pin and a sixth pin; The fourth pin is in communication with the target host, the fifth pin is in communication with the auxiliary reset pin, and the sixth pin is in communication with the reset pin; The second link refers to the link connected by the fifth pin and the sixth pin; The first link refers to the link connected by the fourth pin and the sixth pin, wherein each pin comprises two level signal states of high level and low level.

5. The server control method of claim 1, wherein If the multiplexer receives the second control signal sent by the complex programmable logic device, a third reset signal is sent by the baseboard management controller to the high-speed serial bus module of the field programmable gate array, including: When it is determined that the target server is powered on and the target host is in a shutdown state, if the multiplexer receives the second control signal sent by the complex programmable logic device, the multiplexer is controlled to open the target link; If the first pin of the baseboard management controller determines that the target link is the second link, the working state of the baseboard management controller is acquired; If the working state is normal, the auxiliary reset pin, the second pin and the reset pin output high level, and a third reset signal is sent by the baseboard management controller to the high-speed serial bus module of the field programmable gate array.

6. The server control method according to claim 5, wherein After the working state of the baseboard management controller is acquired, the method further includes: If the working state is abnormal, the auxiliary reset pin and the second pin are controlled to be low level; The level signal of the auxiliary reset pin is transmitted to the reset pin through the second link; The reset pin is controlled to output low level.

7. The server control method of claim 1, wherein If the multiplexer receives the first control signal sent by the complex programmable logic device, a first reset signal is sent by the target host to the high-speed serial bus endpoint module in the baseboard management controller, including: If the multiplexer receives the first control signal sent by the complex programmable logic device, the multiplexer is controlled to open the target link; If the first pin determines that the target link is the first link, a first reset signal is sent by the target host to the high-speed serial bus endpoint module in the baseboard management controller.

8. The server control method of claim 1, wherein If the baseboard management controller detects the first reset signal, a second reset signal is sent by the baseboard management controller to the high-speed serial bus module of the field programmable gate array, including: If the baseboard management controller detects the first reset signal, the power-on state of the target host is acquired; If the target host is in a power-on state, a second reset signal is sent by the baseboard management controller to the high-speed serial bus module of the field programmable gate array.

9. The server control method according to claim 8, wherein Before the baseboard management controller detects the first reset signal and acquires the power-on state of the target host, the method further includes: If the target host is in a shutdown state, a power-on instruction is sent by the baseboard management controller to the complex programmable logic device; Or, in response to the input of a power-on key of the target host by a user, a power-on instruction is sent to the complex programmable logic device; The target host is controlled to enter a power-on preparation state by the power-on instruction; After waiting for a target preset time, the target host is controlled to enter a power-on state.

10. The server control method according to claim 9, wherein After the target host is controlled to enter a power-on preparation state by the power-on instruction, the method further includes: If the working state is abnormal, the auxiliary reset pin and the second pin are controlled to be low level; The level signal of the auxiliary reset pin is transmitted to the reset pin through the second link; The reset pin is controlled to output low level. controlling the third pin and the fourth pin in the multiplexer to be low, and setting a synchronization strategy for the auxiliary reset pin and the second pin with the level signal of the third pin; sending the first level signal state of the fourth pin to the reset pin through the first link; controlling the reset pin to be low.

11. The server control method according to claim 10, wherein After the synchronization strategy for the auxiliary reset pin and the second pin with the level signal of the third pin is set, the method further comprises: adjusting the auxiliary reset pin and the second pin to be low through the first level signal state of the third pin.

12. The server control method according to claim 11, wherein The target server further comprises a management component transmission protocol controller. After the auxiliary reset pin and the second pin are adjusted to be low through the first level signal state of the third pin, the method further comprises: The baseboard management controller and the management component transmission protocol controller enter a reset state. The communication between the baseboard management controller and the field programmable gate array is abnormal.

13. The server control method according to claim 9, wherein After waiting for the target preset time length, the target host is controlled to enter a power-on state, comprising: controlling the baseboard management controller to remain in a reset state through the complex programmable logic device, and starting a first timer; In a case where the timing duration of the first timer reaches a target preset time length, the target host is controlled to enter a power-on state.

14. The server control method according to claim 13, wherein After the target host is controlled to enter a power-on state in the case where the timing duration of the first timer reaches a target preset time length, the method further comprises: sending a first reset signal through the reset output pin of the target host; controlling the third pin to have a rising edge change through the first reset signal; determining that the third pin outputs a high level through the rising edge change.

15. The server control method according to Claim 9, wherein Before the target host is controlled to enter a power-on state after waiting for the target preset time length, the method further comprises: pre-registering an edge-triggered interrupt about the third pin for the baseboard management controller; In a case where the third pin has an edge change, the edge change of the third pin is sent to the baseboard management controller through the edge-triggered interrupt, wherein the edge change includes a rising edge change from low to high, and a falling edge change from high to low.

16. The server control method of claim 1, wherein After the multiplexer receives the second control signal sent by the complex programmable logic device, the method further comprises: controlling the third pin to have a falling edge change in a case where the target server is powered off; controlling the multiplexer to switch to a second link through the complex programmable logic device; sending the falling edge change to the baseboard management controller, so that the baseboard management controller controls the auxiliary reset pin and the second pin to output a low level.

17. A server control device characterized by comprising: The device is applied to a target server, comprising a target host, a complex programmable logic device, a field programmable gate array, a baseboard management controller, a multiplexer, and the device comprises: The first sending module is configured to send a first reset signal to a high-speed serial bus endpoint module in the baseboard management controller through the target host if the multiplexer receives a first control signal sent by the complex programmable logic device; The second sending module is configured to send a second reset signal to a high-speed serial bus module of the field programmable gate array through the baseboard management controller if the baseboard management controller detects the first reset signal, so as to ensure normal communication between the baseboard management controller and the field programmable gate array; The third sending module is configured to send a third reset signal to the high-speed serial bus module of the field programmable gate array through the baseboard management controller if the multiplexer receives a second control signal sent by the complex programmable logic device, so as to ensure normal communication between the baseboard management controller and the field programmable gate array.

18. A communication device, comprising: Comprise: a transceiver, a memory, a processor and a program stored in the memory and executable on the processor; The processor is configured to read the program in the memory to implement the server control method according to any one of claims 1-16.

19. A non-volatile readable storage medium configured to store a program, characterized in that, The storage program is executed by the processor to implement the server control method according to any one of claims 1-16.

20. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to implement the server control method according to any one of claims 1-16.

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