Embedded memory chip and embedded storage method

Abstract

An embedded memory chip and an embedded storage method, relating to the field of data storage. The embedded memory chip comprises: a first magnetic random access memory, used for storing data that needs to be erased and written at least twice; a second magnetic random access memory, used for storing data that needs to be erased and written at least twice, wherein the number of times of erasing and writing the data in the second magnetic random access memory is not greater than the number of times of erasing and writing the data in the first magnetic random access memory; and a third magnetic random access memory, used for storing data only written once, so as to write the data in the third magnetic random access memory into the second magnetic random access memory when the embedded memory chip operates for the first time, and write the data in the third magnetic random access memory into the second magnetic random access memory when it is detected that the data in the second magnetic random access memory is lost. The present application simplifies the manufacturing process of the memory and reduces the manufacturing cost while satisfying the storage requirements on the chip.

Description

Embedded memory chip and embedded memory method

[0001] The present application claims priority to the Chinese patent application No. 202411004354.3, filed on July 25, 2024, and entitled "Embedded memory chip and embedded memory method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of data storage, and in particular, to an embedded memory chip and an embedded memory method. BACKGROUND

[0003] A single bit structure cannot fully meet the requirements of high erase-write times, fast read-write, high data retention capability, low power consumption and other functions in a chip, so in actual chips, a combination of multiple volatile and non-volatile memories from static random access memory (SRAM) to flash is used to achieve the requirements.

[0004] As shown in FIG. 1, an MCU (Microcontroller Unit) chip uses two types of memories, Flash ROM (Read-Only Memory) and SRAM, and uses a CPU (Central Processing Unit) to control the two memories through a bus. Among them, the Flash ROM is used to store code that needs to be erased and written a small amount of times, and has certain anti-reflow soldering capability; the SRAM is used to store data that needs to be frequently erased and written, supports erase-write speed <40ns, erase-write times ≥1E9 times, and has low write power consumption. Since the SRAM is a volatile storage device, a small backup battery needs to be connected to continue to supply power to the SRAM when the main power is disconnected, so as to maintain the integrity of the data, which leads to an increase in cost and complexity of the overall design scheme during the design process. Moreover, since the Flash ROM and the SRAM are two different types of memories, their manufacturing processes are also different, which not only increases the manufacturing complexity, but also increases the manufacturing cost. In addition, the compatibility of the Flash in embedded advanced process nodes is poor, and the lower the process node, the more the manufacturing cost of the Flash will increase significantly. Therefore, how to meet the chip storage requirements while simplifying the manufacturing process of the memory and reducing the manufacturing cost is a technical problem that needs to be solved by those skilled in the art at present. SUMMARY

[0005] The application aims to provide an embedded storage chip and an embedded storage method, in which all the storage chips with different functions in a traditional chip are replaced by different magnetic random memories, so that a simpler and more unified manufacturing process and design scheme are realized.

[0006] To achieve the above-mentioned purpose, the application provides an embedded storage chip, which comprises:

[0007] a first magnetic random memory for storing data needing to be erased and written at least twice;

[0008] a second magnetic random memory for storing data needing to be erased and written at least twice, and the number of times of erasing and writing the data in the second magnetic random memory is not higher than that in the first magnetic random memory;

[0009] a third magnetic random memory for storing data needing to be written only once, so that when the embedded storage chip is used for the first time, the data in the third magnetic random memory is written into the second magnetic random memory, and when it is detected that the data in the second magnetic random memory is lost, the data in the third magnetic random memory is written into the second magnetic random memory.

[0010] Optionally, the first magnetic random memory, the second magnetic random memory and the third magnetic random memory all comprise magnetic tunnel junctions with the same structure and thickness.

[0011] The magnetic tunnel junction comprises a fixed magnetic layer and a free magnetic layer, and a tunnel barrier insulating layer located between the fixed magnetic layer and the free magnetic layer.

[0012] Optionally, the first magnetic random memory, the second magnetic random memory and the third magnetic random memory are all connected in series with metal oxide semiconductor transistors.

[0013] Optionally, the first magnetic random memory, the second magnetic random memory and the third magnetic random memory have the same magnetic tunnel junction size.

[0014] The first magnetic random memory and the second magnetic random memory use a first number of metal oxide semiconductor transistors, the third magnetic random memory uses a second number of metal oxide semiconductor transistors, and the first number is less than the second number.

[0015] Optionally, the first magnetic random memory has a first magnetic tunnel junction size, the second magnetic random memory and the third magnetic random memory both have a second magnetic tunnel junction size, and the second magnetic tunnel junction size is greater than the first magnetic tunnel junction size.

[0016] The first magnetic random access memory uses a first number of metal oxide semiconductor transistors; the second magnetic random access memory and the third magnetic random access memory use a second number of metal oxide semiconductor transistors; the first number is less than the second number.

[0017] Optionally, the first magnetic random access memory has a first magnetic tunnel junction size; the second magnetic random access memory has a second magnetic tunnel junction size; the third magnetic random access memory has a third magnetic tunnel junction size; the second magnetic tunnel junction size is greater than the first magnetic tunnel junction size; the first magnetic tunnel junction size is greater than the third magnetic tunnel junction size.

[0018] The first magnetic random access memory uses a first number of metal oxide semiconductor transistors; the second magnetic random access memory and the third magnetic random access memory use a second number of metal oxide semiconductor transistors; the first number is less than the second number.

[0019] Optionally, the second magnetic random access memory and the third magnetic random access memory share a reference circuit; the reference circuit includes a reference resistor.

[0020] When the resistance of the second magnetic random access memory is greater than the reference resistor, the second magnetic random access memory is in an anti-parallel state; when the resistance of the second magnetic random access memory is less than the reference resistor, the second magnetic random access memory is in a parallel state.

[0021] When the resistance of the third magnetic random access memory is greater than the reference resistor, the second magnetic random access memory is in a parallel state; when the resistance of the third magnetic random access memory is less than the reference resistor, the third magnetic random access memory is in a breakdown state.

[0022] Optionally, the first magnetic random access memory, the second magnetic random access memory, and the third magnetic random access memory are all in series with a metal oxide semiconductor transistor group; the metal oxide semiconductor transistor group includes a single or multiple metal oxide semiconductor transistors in series and parallel.

[0023] Optionally, the embedded storage chip includes: a first magnetic random access memory array, a second magnetic random access memory array, and a third magnetic random access memory array; the first magnetic random access memory array includes a plurality of first magnetic random access memories; the second magnetic random access memory array includes a plurality of second magnetic random access memories; the third magnetic random access memory array includes a plurality of third magnetic random access memories.

[0024] To achieve the above object, the application further provides an embedded storage method, characterized in that: storing data needing to be erased and written at least twice in a first magnetic random memory; storing data needing to be written only once in a third magnetic random memory, so as to write the data in the third magnetic random memory into a second magnetic random memory when the embedded storage chip works for the first time; and write the data in the third magnetic random memory into the second magnetic random memory when it is detected that the data in the second magnetic random memory is lost; the second magnetic random memory is used to store data needing to be erased and written at least twice, and the number of times of erasing and writing the data in the second magnetic random memory is not higher than that of the data in the first magnetic random memory.

[0025] Obviously, the application provides an embedded storage chip, which uses a first magnetic random memory to store data needing to be frequently updated, a second magnetic random memory to store data needing to be updated in a small amount, and a third magnetic random memory to store data needing to be written only once, so as to consider the storage of data with different block characteristics. On the one hand, the three partitioned magnetic random memories replace the multiple different types of memories in the existing chip, and since it is not necessary to additionally design a multilayer magnetic tunnel junction device or a partitioned magnetic tunnel junction, only one device structure is used, so that different storage applications are realized, compared with the traditional scheme using multiple different types of memories, the storage demand of the chip is met, the manufacturing process of the memory is simplified, and the manufacturing cost is reduced, so that a simpler and more unified manufacturing process and design scheme are realized. On the other hand, the third magnetic random memory is used to store data needing to be written only once, so that the data can be ensured not to change in the use process in various harsh environments. When the embedded storage chip works for the first time, the data in the third magnetic random memory is written into the second magnetic random memory, and the update and reading of subsequent data are only performed between the first magnetic random memory and the second magnetic random memory; when it is detected that the data in the second magnetic random memory is lost, the embedded storage chip writes the data in the third magnetic random memory into the second magnetic random memory according to the first working mode, initializes the data to be reloaded, so that the embedded storage chip can support OTA upgrade and other functions, and has strong anti-reflow soldering, anti-magnetic and other anti-interference capabilities; meanwhile, the high speed and high erasing resistance of the magnetic random memory can be fully utilized, and the system competitiveness is improved. The application further provides an embedded storage method, which has the above beneficial effects. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only part of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0027] Fig. 1 is a structural schematic diagram of a conventional embedded memory chip;

[0028] Fig. 2 is a structural schematic diagram of an embedded memory chip provided by an embodiment of the present application;

[0029] Fig. 3 is a structural schematic diagram of a first specific embodiment provided by an embodiment of the present application;

[0030] Fig. 4 is a structural schematic diagram of a second specific embodiment provided by an embodiment of the present application;

[0031] Fig. 5 is a structural schematic diagram of a third specific embodiment provided by an embodiment of the present application;

[0032] Fig. 6 is a schematic diagram of resistance values of different states of a different magnetic random memory provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present application.

[0034] Please refer to Fig. 2, which is a structural schematic diagram of an embedded memory chip provided by an embodiment of the present application. The embedded memory chip can include:

[0035] A first magnetic random memory for storing data that needs to be erased and written at least twice;

[0036] A second magnetic random memory for storing data that needs to be erased and written at least twice, and the number of erasing and writing of the data in the second magnetic random memory is not higher than that of the data in the first magnetic random memory;

[0037] A third magnetic random memory for storing data that needs to be written only once, so that when the embedded memory chip is first used, the data in the third magnetic random memory is written into the second magnetic random memory; and when it is detected that the data in the second magnetic random memory is lost, the data in the third magnetic random memory is written into the second magnetic random memory.

[0038] It should be noted that the magnetic random access memory (MRAM) used in this embodiment is a non-volatile memory technology that uses the magnetization state of a magnetic material to store data. Compared with traditional semiconductor memory, magnetic random access memory has faster read and write speed, higher storage density and lower power consumption. In addition to its performance advantages, magnetic random access memory can be adjusted by a certain parameter to achieve a very large performance adjustment range, which can be adjusted from a magnetic random access memory similar to SRAM to a magnetic random access memory similar to Flash. Therefore, all the storage chips with different functions (two or more) in the traditional chip can be replaced by different magnetic random access memories to achieve a simpler and more unified manufacturing process and design scheme.

[0039] The embodiment is not limited to the specific application scenarios of the first magnetic random access memory, the second magnetic random access memory and the third magnetic random access memory. The specific types of data stored in the first magnetic random access memory, the second magnetic random access memory and the third magnetic random access memory can be determined according to the actual application scenario, for example:

[0040] The first magnetic random access memory has a high number of erasing and writing times and can be used for daily data storage and erasing, for example, it can store data in the process of fast reading and writing of the chip.

[0041] The second magnetic random access memory can support a small amount of erasing and writing, has stronger stability (data retention capability) than the first magnetic random access memory, and can be used to store data generated during the use of the system after it is shipped or updated data. Moreover, when the data in the second magnetic random access memory is lost, the data in the third magnetic random access memory can be written into the second magnetic random access memory, so that the system can support functions such as OTA (Over-the-Air Technology) upgrade.

[0042] The third magnetic random access memory can store data that is written only once. Even in other harsh environments such as reflow soldering, wafer-level chip packaging and large magnetic fields, it can still ensure that the data will not change during use, so it can be used to store some data that cannot be changed, such as basic data before the system is shipped, including hard-burned BIOS system (Basic Input Output System), security code and other codes, or user settings for the system. These data stored in the third magnetic random access memory can be ensured not to be lost during reflow soldering, wafer-level chip packaging and large magnetic field processes.

[0043] The embodiment is not limited to a specific control manner of storing data, and can include but is not limited to using a CPU to control the first magnetic random memory, the second magnetic random memory and the third magnetic random memory through a bus.

[0044] The embodiment is not limited to a specific number of the first magnetic random memory, the second magnetic random memory and the third magnetic random memory, and the specific number can be determined according to an actual amount of data to be stored. For example, the embedded memory chip in the embodiment can include a first magnetic random memory array, a second magnetic random memory array and a third magnetic random memory array. The first magnetic random memory array includes a plurality of first magnetic random memories. The second magnetic random memory array includes a plurality of second magnetic random memories. The third magnetic random memory array includes a plurality of third magnetic random memories.

[0045] The embodiment is not limited to a specific structure of the first magnetic random memory, the second magnetic random memory and the third magnetic random memory, as long as the magnetization state of the magnetic material can be used to store data. For example, the first magnetic random memory, the second magnetic random memory and the third magnetic random memory can each include a magnetic tunnel junction (MTJ) with the same structure and thickness. The magnetic tunnel junction can include a fixed magnetic layer and a free magnetic layer, and a tunnel barrier insulating layer located between the fixed magnetic layer and the free magnetic layer.

[0046] The embodiment is not limited to a specific driving manner of the first magnetic random memory, the second magnetic random memory and the third magnetic random memory, as long as the first magnetic random memory and the second magnetic random memory can be driven to realize the erasing and writing functions, and the third magnetic random memory can be driven to realize the one-time writing function. For example, the first magnetic random memory, the second magnetic random memory and the third magnetic random memory can each be connected in series with a metal oxide semiconductor (MOS) transistor. The MOS transistor connected in series with the third magnetic random memory can apply a programming voltage as a writing voltage by crossing the magnetic tunnel junction of the third magnetic random memory, so as to break the magnetic tunnel junction of the third magnetic random memory. It should be noted that, on one hand, the MOS transistor supplies current for the first magnetic random memory and the second magnetic random memory, so as to realize the flipping of the magnetic moment direction of the magnetic tunnel junction, thereby realizing the writing or erasing of data. On the other hand, the MOS transistor applies the programming voltage to the magnetic tunnel junction of the third magnetic random memory, so as to break the magnetic tunnel junction, thereby realizing that the data in the third magnetic random memory can be written only once.

[0047] The embodiment is not limited to the specific number and arrangement of metal oxide semiconductor transistors, for example, the first magnetic random access memory, the second magnetic random access memory and the third magnetic random access memory can each be connected in series with the metal oxide semiconductor transistor group; the metal oxide semiconductor transistor group can include single or multiple metal oxide semiconductor transistors connected in series and in parallel. The embodiment is not limited to the specific type of metal oxide semiconductor transistor, which can include but is not limited to a complementary metal oxide semiconductor (CMOS) transistor.

[0048] The embodiment is not limited to the specific implementation of the first magnetic random access memory, the second magnetic random access memory and the third magnetic random access memory to achieve different storage functions, for example, the magnetic tunnel junction size (CD) can be adjusted; different magnetic tunnel junctions can also be designed to adjust the anisotropic field of the magnetic tunnel junction. It should be noted that the latter has a larger adjustable range, and the manufacturing cost and difficulty are also larger; the former has a smaller adjustable range, but the manufacturing cost and difficulty are smaller.

[0049] Three different magnetic random access memories with different magnetic tunnel junction sizes are provided below, but are not limited to the following three:

[0050] (1) The first magnetic random access memory, the second magnetic random access memory and the third magnetic random access memory have the same magnetic tunnel junction size; the first magnetic random access memory and the second magnetic random access memory use a first number of metal oxide semiconductor transistors; the third magnetic random access memory uses a second number of metal oxide semiconductor transistors; the first number is less than the second number.

[0051] Please refer to FIG. 3, which is a structural schematic diagram of a first specific embodiment provided by the present application. In the figure, the MRAM DATA (representing a magnetic random access memory for storing data that needs to be frequently updated) and the MRAM MTP (representing a magnetic random access memory for storing code that needs to be updated in small amounts) use the same device (including the same MTJ stack and MTJ CD, etc.), so the same number of CMOS transistors (2 in this embodiment) can be used for current supply. The MRAM OTP (a magnetic random access memory for storing code that is written only once) needs to break through the MTJ, so it needs more current, i.e., more CMOS transistors (3 in this embodiment) for current supply. It can adjust the MTJ CD as needed to ensure more efficient breakdown, and the specific value of the MTJ CD is not limited here.

[0052] (2) The first magnetic random access memory has a first magnetic tunnel junction size; the second magnetic random access memory and the third magnetic random access memory have a second magnetic tunnel junction size; the second magnetic tunnel junction size is greater than the first magnetic tunnel junction size; the first magnetic random access memory uses a first number of metal oxide semiconductor transistors; the second magnetic random access memory and the third magnetic random access memory use a second number of metal oxide semiconductor transistors; the first number is less than the second number.

[0053] Please refer to FIG. 4, which is a structural diagram of a second specific embodiment provided by the present application. In the figure, MRAM DATA uses normal MTJ CD (CD1) and normal CMOS transistors (2 in this embodiment) for current supply; MRAM OTP and MRAM MTP use the same MTJ CD (CD2), but since CD2>CD1, more CMOS transistors with stronger current supply capability are needed for driving, and both of them have 3 CMOS transistors in the figure.

[0054] (3) The first magnetic random access memory has a first magnetic tunnel junction size; the second magnetic random access memory has a second magnetic tunnel junction size; the third magnetic random access memory has a third magnetic tunnel junction size; the second magnetic tunnel junction size is greater than the first magnetic tunnel junction size; the first magnetic tunnel junction size is greater than the third magnetic tunnel junction size; the first magnetic random access memory uses a first number of metal oxide semiconductor transistors; the second magnetic random access memory and the third magnetic random access memory use a second number of metal oxide semiconductor transistors; the first number is less than the second number.

[0055] Please refer to FIG. 5, which is a structural diagram of a third specific embodiment provided by the present application. In the figure, MRAM DATA uses normal MTJ CD (CD1) and normal CMOS transistors (2 in this embodiment) for current supply; MRAM OTP and MRAM MTP use different MTJ CDs respectively, in which the MTJ CD of MRAM MTP is CD2, and the MTJ CD of MRAM OTP is CD3, but more CMOS transistors with stronger current supply capability are needed for driving, and both of them have 3 CMOS transistors in the figure, in which the CMOS transistors for MRAM OTP supply current for breaking down the MTJ, and the CMOS transistors for MRAM MTP supply current for flipping the direction of the magnetic moment of the MTJ. In which CD2>CD1>CD3, CD3 is smaller and the corresponding voltage division is higher, which is conducive to breaking down the MTJ; CD2 is larger and the corresponding data retention capability is stronger, which is conducive to improving the stability of MRAM MTP.

[0056] Further, the second magnetic random memory and the third magnetic random memory share the reference circuit in the embodiment; the reference circuit includes a reference resistor; when the resistance of the second magnetic random memory is greater than the reference resistance, the second magnetic random memory is in the anti-parallel state; when the resistance of the second magnetic random memory is less than the reference resistance, the second magnetic random memory is in the parallel state; when the resistance of the third magnetic random memory is greater than the reference resistance, the second magnetic random memory is in the parallel state; and when the resistance of the third magnetic random memory is less than the reference resistance, the third magnetic random memory is in the breakdown state.

[0057] Referring to FIG. 6, which is a diagram of resistance values of different states of different magnetic random memories according to an embodiment of the present application. The resistance values of the same magnetic random memory in the parallel state (P state), the anti-parallel state (AP state), and the breakdown state (BD state) are different. In the diagram, the resistance values of MRAM MTP in the P state and the AP state are 2000 and 5000, respectively; and the resistance values of MRAM OTP in the BD state and the AP state are <1000 and 5000, respectively. As can be seen from the diagram, when the reference resistance in the reference circuit is set to a value in the range of 2000-5000, the P state and the AP state of MRAM MTP can be distinguished (i.e., the two operations of erasing and writing can be distinguished), and the BD state and the AP state of MRAM OTP can also be distinguished (i.e., the two operations of erasing and writing can be distinguished). Therefore, by reasonably designing the CD to adjust the resistance of MRAM OTP and MRAM MTP, the reference circuit design for the code storage area MRAM OTP and MRAM MTP can be realized.

[0058] Based on the above embodiments, the application uses the first magnetic random memory to store data that needs to be frequently updated, the second magnetic random memory to store data that needs to be updated in small amounts, and the third magnetic random memory to store data that is written only once, thereby taking into account the storage of data with different block characteristics. On the one hand, the three partitioned magnetic random memories replace the various different types of memories in the existing chip, and since there is no need to additionally design a multi-layer magnetic tunnel junction device or a partitioned magnetic tunnel junction, only one device structure is used to achieve different storage applications, compared with the traditional scheme of using various different types of memories, the chip storage requirements are met while the manufacturing process of the memory is simplified and the manufacturing cost is reduced, and a simpler and more unified manufacturing process and design scheme is achieved. On the other hand, the third magnetic random memory stores data that is written only once, which can ensure that the data will not change during use in various harsh environments. When the embedded storage chip is first used, the data in the third magnetic random memory is written into the second magnetic random memory, and subsequent updates and reading of data are only performed between the first magnetic random memory and the second magnetic random memory; when it is detected that the data in the second magnetic random memory is lost, the embedded storage chip writes the data in the third magnetic random memory into the second magnetic random memory in the first use mode, initializes the data for reloading, so that the embedded storage chip can support OTA upgrade and other functions, and has strong anti-reflow soldering, anti-magnetic and other anti-interference capabilities; at the same time, the high speed and high erasability characteristics of the magnetic random memory can be fully utilized to improve the competitiveness of the system.

[0059] The application also provides an embedded storage method, which can include:

[0060] storing data that needs to be erased and written at least twice in the first magnetic random memory;

[0061] storing data that is written only once in the third magnetic random memory, so that when the embedded storage chip is first used, the data in the third magnetic random memory is written into the second magnetic random memory; and when it is detected that the data in the second magnetic random memory is lost, the data in the third magnetic random memory is written into the second magnetic random memory; the second magnetic random memory is used to store data that needs to be erased and written at least twice, and the number of times of erasing and writing the data in the second magnetic random memory is not higher than the number of times of erasing and writing the data in the first magnetic random memory.

[0062] Based on the above-mentioned embedded storage chip embodiments, the application executes the above-mentioned embedded storage method, and also has the beneficial effects of the above-mentioned embedded storage chip.

[0063] The following provides a specific application embodiment of the above-mentioned embedded storage chip.

[0064] The embedded memory chip in the embodiment includes three different types of MRAM, MRAM OTP, MRAM MTP and MRAM DATA, wherein:

[0065] The MRAM OTP is used to store basic data before the system is shipped (including hard-burned BIOS system, security code and other codes) or user settings of the system, and the part of the memory can ensure that the data will not change during use even in other harsh environments such as reflow soldering, wafer-level chip packaging, large magnetic field, etc.

[0066] The MRAM MTP is used to store data generated during use after the system is shipped or updated data, and the part of the memory has OTA upgrade capability, that is, it can support a small number (<105 times) of fast speed (<1μs) erasing and writing, and has a large data retention capability (10 years @ 125 / 150℃).

[0067] The MRAM DATA is used to store data in the process of fast reading and writing of the chip, and the part of the memory has a high number of erasing times (>1010 times), a fast erasing and writing speed (<50ns) and a low writing power consumption.

[0068] A method for storing data using the above embedded memory chip is provided, and the method includes:

[0069] The basic data before the system is shipped (including hard-burned BIOS system, security code and other codes) or user settings of the system are stored in the MRAM OTP, so as to ensure that important data is not lost during the process such as reflow soldering, wafer-level chip packaging, large magnetic field, etc.

[0070] The data generated during use after the system is shipped or updated data are stored in the MRAM MTP, so that the system supports OTA upgrade and other functions, and has a strong data retention capability, ensuring that the data is not lost in a general environment; in case of data loss in the MRAM MTP due to harsh external environment (such as high temperature, large magnetic field, etc.), the system restores the factory settings, updates the data from the MRAM OTP, and then performs OTA upgrade to the latest state.

[0071] The data in the process of fast reading and writing of the chip are stored in the MRAM DATA, and the high speed, high erasing resistance, low power consumption and non-volatile characteristics of the MRAM DATA are fully utilized.

[0072] The principles and implementations of the present application are described herein with the specific examples, and each embodiment is progressive, and each embodiment focuses on the difference from other embodiments, and the same and similar parts between each embodiment can be referred to each other. The above embodiment is only used to help understand the method and its core idea of the present application. For ordinary skilled in the art, some improvements and modifications can be made without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0073] It should also be noted that the relational terms herein such as first and second and the like are used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more limitations, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Claims

1. An embedded memory chip, characterized by, Comprising: a first magnetic random access memory for storing data requiring at least two erasures; a second magnetic random access memory for storing data requiring at least two erasures, and the number of erasures of data in the second magnetic random access memory is not higher than that of the first magnetic random access memory; a third magnetic random access memory for storing data written only once, to write the data in the third magnetic random access memory into the second magnetic random access memory when the embedded memory chip is first operated, and to write the data in the third magnetic random access memory into the second magnetic random access memory when the loss of data in the second magnetic random access memory is detected.

2. The embedded memory chip of claim 1, wherein, The first, second and third magnetic random access memories all comprise magnetic tunnel junctions of the same structure and thickness; The magnetic tunnel junctions comprise a fixed magnetic layer and a free magnetic layer, and a tunnel barrier insulating layer between the fixed magnetic layer and the free magnetic layer.

3. The embedded memory chip of claim 2, wherein, The first, second and third magnetic random access memories are all in series with metal oxide semiconductor transistors.

4. The embedded memory chip of claim 3, wherein, The first, second and third magnetic random access memories have the same magnetic tunnel junction size; The first and second magnetic random access memories use a first number of metal oxide semiconductor transistors; The third magnetic random access memory uses a second number of metal oxide semiconductor transistors; the first number is less than the second number.

5. The embedded memory chip of claim 3, wherein, The first magnetic random access memory has a first magnetic tunnel junction size; the second and third magnetic random access memories both have a second magnetic tunnel junction size; the second magnetic tunnel junction size is greater than the first magnetic tunnel junction size; The first magnetic random access memory uses a first number of metal oxide semiconductor transistors; The second and third magnetic random access memories use a second number of metal oxide semiconductor transistors; the first number is less than the second number.

6. The embedded memory chip of claim 3, wherein, The first magnetic random access memory has a first magnetic tunnel junction size; the second magnetic random access memory has a second magnetic tunnel junction size; the third magnetic random access memory all has a third magnetic tunnel junction size; the second magnetic tunnel junction size is greater than the first magnetic tunnel junction size; the first magnetic tunnel junction size is greater than the third magnetic tunnel junction size; The first magnetic random access memory uses a first number of metal oxide semiconductor transistors; The second and third magnetic random access memories use a second number of metal oxide semiconductor transistors; the first number is less than the second number.

7. The embedded memory chip of claim 3, wherein, The second and third magnetic random access memories share a reference circuit; the reference circuit comprises a reference resistor; When the resistance of the second magnetic random memory is greater than the reference resistance, the second magnetic random memory is in an anti-parallel state; when the resistance of the second magnetic random memory is less than the reference resistance, the second magnetic random memory is in a parallel state; When the resistance of the third magnetic random memory is greater than the reference resistance, the second magnetic random memory is in a parallel state; when the resistance of the third magnetic random memory is less than the reference resistance, the third magnetic random memory is in a breakdown state.

8. The embedded memory chip of claim 3, wherein, The first magnetic random memory, the second magnetic random memory and the third magnetic random memory are all in series with a metal oxide semiconductor transistor group; the metal oxide semiconductor transistor group includes single or multiple metal oxide semiconductor transistors in series and parallel.

9. The embedded memory chip of claim 1, wherein, Comprising: A first magnetic random memory array, a second magnetic random memory array and a third magnetic random memory array; the first magnetic random memory array includes a plurality of first magnetic random memories; the second magnetic random memory array includes a plurality of second magnetic random memories; and the third magnetic random memory array includes a plurality of third magnetic random memories.

10. An embedded storage method, characterized by, Comprising: Storing data that needs to be erased at least twice in the first magnetic random memory; Storing data that needs to be written only once in the third magnetic random memory, writing data in the third magnetic random memory to the second magnetic random memory when the embedded storage chip is first operated; and writing data in the third magnetic random memory to the second magnetic random memory when data loss in the second magnetic random memory is detected; the second magnetic random memory is used to store data that needs to be erased at least twice, and the number of erasures of data in the second magnetic random memory is not higher than the number of erasures of data in the first magnetic random memory.

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