Packaging structure and electronic device

Abstract

The present application provides a packaging structure and an electronic device. The packaging structure comprises a substrate, a chip, a packaging layer, a first metal member, and a shielding layer. The substrate comprises a substrate body and a ground line; and the ground line is connected to the substrate body. The chip is connected to the substrate body. The packaging layer covers the substrate body and the chip. The first metal member passes through the packaging layer to be connected to the surface of the chip facing away from the substrate body, and in the thickness direction of the substrate, the orthographic projection of the first metal member is within the surface of the chip facing away from the substrate. The shielding layer electrically connects the end of the first metal member facing away from the substrate body to the ground line. In embodiments of the present application, a metal shielding structure can be flexibly configured, thereby achieving an electromagnetic shielding effect for the packaging structure.

Description

Package structure and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411020206.0, filed on July 26, 2024, with the State Intellectual Property Office of China, and the Chinese patent application No. 202411020206.0 has the title of “Package structure and electronic device”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of chip packaging, in particular to a package structure and an electronic device. BACKGROUND

[0003] With the continuous maturation of chip packaging technology, some packaging technologies can produce higher density and smaller volume packaging structures through more compact and reliable design and process to adapt to the miniaturization trend of electronic devices. However, due to the high density of electrical functions, the packaging structure will usually cause electromagnetic interference to the electrical components nearby, thereby affecting the signal transmission stability of the electronic device. SUMMARY

[0004] Embodiments of the present application provide a package structure and an electronic device, which can flexibly set up a metal shielding structure, thereby achieving the effect of electromagnetic shielding of the package structure.

[0005] In a first aspect, the present application provides a package structure, comprising a substrate, a chip, a packaging layer, a first metal piece and a shielding layer. The substrate comprises a board body and a ground wire, and the ground wire is connected to the board body. The chip is connected to the board body. The packaging layer covers the board body and the chip. The first metal piece is connected to the surface of the chip away from the board body through the packaging layer, and the orthographic projection of the first metal piece in the thickness direction of the substrate is located in the surface of the chip away from the substrate. The shielding layer electrically connects one end of the first metal piece away from the board body to the ground wire.

[0006] In the present embodiment, the ground wire helps to reduce the electromagnetic radiation interference (EMI) of the package structure to the external environment and prevent the interference (EMS) of the external electromagnetic field to the inside of the package structure. Through reasonable layout and connection of the ground wire, the electromagnetic compatibility of the package structure can be improved to ensure its stable operation in a complex electromagnetic environment.

[0007] In addition, the ground wire can also help to dissipate heat from the package structure. This helps to improve the heat dissipation efficiency of the package structure and prevent the performance degradation or damage of the chip due to overheating.

[0008] Furthermore, the ground wire can effectively isolate and reduce the crosstalk and cross interference between different signal lines. In high-speed signal transmission, the interference between signals is an important problem, and the ground wire can reduce the mutual influence between signals by providing a stable potential reference point, thereby improving the integrity and accuracy of the signals.

[0009] The encapsulation layer can provide a physical barrier for the chip to prevent dust, moisture and mechanical impact in the external environment from damaging the chip. The encapsulation layer can also prevent the chip from reacting with chemical substances in the external environment, thereby prolonging the service life of the encapsulation structure. The encapsulation layer also provides a firm and reliable mechanical support for the chip, and the encapsulation layer can maintain the structural stability and reliability of the chip. The encapsulation layer hides the internal complex structure and only retains the necessary external interface for user use. This allows users to not need to care about the internal complex structure and principle, and only need to complete the use and maintenance of the product through simple operation.

[0010] The first metal piece can be connected to the side of the chip away from the board through the encapsulation layer. The shielding layer electrically connects the end of the first metal piece away from the board to the ground wire, thereby forming an electromagnetic shielding structure.

[0011] Directly connecting the first metal piece to the surface of the chip can flexibly use the space above the chip, and since the first metal piece is directly connected to the chip, the first metal piece can directly reduce the electromagnetic waves near the chip, avoid the propagation of external electromagnetic waves to the chip to affect the signal transmission of the chip, and at the same time avoid the electromagnetic waves generated by the chip during operation from being transmitted to the outside of the encapsulation structure to affect the operation of other electronic elements.

[0012] The first metal piece can be perpendicular to the plane in which the board is located. Therefore, the length of the first metal piece is relatively small, and the surface area of the first metal piece subjected to external force is also relatively small. During the processing or assembly of the encapsulation structure, the first metal piece is less likely to deform or break due to the small force position, thereby ensuring the shielding effect of the first metal piece and making the overall electromagnetic shielding effect of the encapsulation structure more stable.

[0013] In a possible implementation, the encapsulation structure further includes a second metal piece, one end of the second metal piece is connected to the board, the second metal piece penetrates through the encapsulation layer along the thickness direction of the encapsulation layer, and the end of the second metal piece away from the board is connected to the shielding layer.

[0014] In the present embodiment, the first metal piece and the second metal piece and the shielding layer together form a shielding cover structure, which not only encapsulates the chip, but also effectively reduces the influence of external electromagnetic fields on the chip, prevents the electromagnetic field generated by the chip from interfering with the external environment, and changes the resonance frequency to prevent interference and crosstalk between the chip and other devices, thereby achieving high suppression and isolation between high-frequency signals and between analog signals and digital signals.

[0015] In a possible implementation, the packaging layer is provided with a through hole and a recess, the through hole penetrates the packaging layer along the thickness direction of the packaging layer, and the recess is recessed from the surface of the packaging layer away from the board body and communicates with the through hole. The first metal piece is arranged in the through hole, and an end of the first metal piece away from the chip protrudes relative to the bottom of the recess and is covered by the shielding layer.

[0016] In the embodiment, the shielding layer can cover one end of the first metal piece and the second metal piece. The radius of the first metal piece is r, and the length of the first metal piece beyond the bottom of the first recess is d. The area of the shielding layer covering the first metal piece is (πr2+2πrd). At this time, the area of the shielding layer combined with the first metal piece is increased by 2πrd. When the length d of the first metal piece beyond the bottom of the first recess is greater than the radius r of the first metal piece, the combined area of the shielding layer and the first metal piece is increased by more than 2 times. Increasing the combined area of the shielding layer and the first metal piece can improve the electrical connection stability of the first metal piece and the ground wire of the substrate, thereby improving the electromagnetic shielding stability of the overall packaging structure.

[0017] In a possible implementation, the packaging layer is provided with a first accommodating groove, the first accommodating groove penetrates the packaging layer along the thickness direction of the packaging layer, the first accommodating groove is located on the side of the chip away from the board body, the first accommodating groove extends along a first direction, and the first metal piece is embedded in the first accommodating groove. The first direction intersects the thickness direction of the packaging structure.

[0018] The first metal piece can be a metal barrier wall formed by silver paste.

[0019] In the embodiment, since the metal barrier wall has high bonding strength with the shielding layer, the electromagnetic shielding structure formed by the first metal piece and the shielding layer has good effect, thereby eliminating the phenomenon of self-excited oscillation in the packaging structure and ensuring stable operation of the packaging structure.

[0020] In a possible implementation, the first metal piece includes a first part and a second part, the first part penetrates the packaging layer and is connected to the surface of the chip away from the board body, the second part is connected to an end of the first part away from the chip, the peripheral side surface of the second part is arranged protruding relative to the peripheral side surface of the first part, and the end surface of the second part away from the first part is connected to the shielding layer.

[0021] In the embodiment, the second part has a larger bonding area with the shielding layer, the transmission path of the current between the first metal piece and the shielding layer is wider and more uniform, and the current concentration and hot spot effect caused by small bonding area are reduced, thereby improving the continuity of the current. This helps to reduce the leakage of electromagnetic radiation of the packaging structure and improve the shielding effect.

[0022] In a possible implementation, the packaging layer is provided with a second accommodating groove, the second accommodating groove penetrates through the packaging layer along the thickness direction of the packaging layer to expose the surface of the board body, the second accommodating groove is arranged at a distance from the edge of the chip, and the second metal piece is embedded in the second accommodating groove.

[0023] In a possible implementation, the substrate further includes a signal line connected to the board body, the chip includes a chip body and a lead wire, the chip body is connected to the board body, the chip body is provided with an electrical connection point away from the surface of the board body, one end of the lead wire is connected to the chip body away from the surface of the board body, and the other end is electrically connected to the signal line. The first metal piece is electrically connected to the electrical connection point.

[0024] In a possible implementation, the substrate further includes a signal line connected to the board body, the chip includes a chip body, a conductive bump and an electrical connection piece, the chip body is arranged in a stack with the board body, the conductive bump is connected between the chip body and the board body, and the electrical connection piece is arranged on the side of the chip body away from the conductive bump. The first metal piece is electrically connected to the electrical connection piece.

[0025] In a possible implementation, the number of the first metal pieces is plural, one chip includes two electrical connection points, and the two electrical connection points are arranged at opposite ends of the chip along the first direction. Each first metal piece is electrically connected to one electrical connection point.

[0026] In the embodiment, the electrical connection points are distributed at opposite ends of the surface of the chip, so that a reasonable spacing is formed to improve the packaging effect of the packaging structure.

[0027] In a second aspect, the application provides an electronic device, which includes a circuit board and the packaging structure as described above, and the circuit board is electrically connected to the signal line. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following only are some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0029] FIG. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the application;

[0030] FIG. 2 is a structural schematic diagram of a first embodiment of the packaging structure shown in FIG. 1;

[0031] FIG. 3 is a sectional schematic diagram of A-A of the packaging structure shown in FIG. 2;

[0032] FIG. 4 is a sectional schematic diagram of a second embodiment of the packaging structure shown in FIG. 1;

[0033] FIG. 5 is a schematic diagram of resonance simulation results of different packaging structures;

[0034] FIG. 6 is a schematic diagram of a structure of a third embodiment of the packaging structure shown in FIG. 1;

[0035] FIG. 7 is a schematic diagram of a cross section at B-B of the packaging structure shown in FIG. 6;

[0036] FIG. 8 is a schematic diagram of a cross section of a fourth embodiment of the packaging structure shown in FIG. 1. DETAILED DESCRIPTION

[0037] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in other ways different from those described herein, and therefore the present application is not limited to the following embodiments.

[0038] For the convenience of understanding, the terms involved in the embodiments of the present application are first explained.

[0039] Multiple: refers to two or more than two.

[0040] Connection: should be understood broadly, for example, A and B are connected, which can be that A and B are directly connected, or A and B are indirectly connected through intermediate media.

[0041] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0042] Please refer to FIG. 1, which is a schematic diagram of a structure of an electronic device 100 provided by the embodiments of the present application. The electronic device 100 includes a circuit board 10 and a packaging structure 20, and the circuit board 10 is electrically connected with signal lines in the packaging structure 20.

[0043] It should be noted that the purpose of FIG. 1 is only to schematically describe the connection relationship between the circuit board 10 and the packaging structure 20, and not to specifically limit the connection position, specific structure and quantity of each device. The structure shown in the embodiments of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 can include more or fewer components than shown, or combine certain components, or split certain components, or different component arrangements.

[0044] The electronic device 100 can be a mobile phone, a tablet, a computer, etc. The circuit board 10 can be a printed circuit board (PCB) or a package substrate, etc. The circuit board 10 can be electrically connected with the package structure 20, so as to ensure that signals can be smoothly transmitted in the circuit structure of the package structure 20 and the circuit board 10. The circuit board 10 can also provide physical support and protection for the package structure 20. For example, the package structure 20 can be a PA Module integrated with Duplexer (PAMid) or a Front-end Module (FEM) applied to a terminal device.

[0045] With the continuous maturity of chip packaging technology, some packaging technologies can prepare higher density and smaller volume packaging structures through more compact and reliable design and process, so as to adapt to the development trend of miniaturization of electronic devices. However, the packaging structure will usually cause electromagnetic interference to the electrical components near it due to the high density of electrical functions. For example, since some chips contained in the PAMid and FEM have a large power, a large electromagnetic interference signal is often generated during use, which leads to a high total radiation level of the electronic device, and finally affects the signal transmission quality of the electronic device.

[0046] Therefore, the application provides a package structure 20, which can perform electromagnetic shielding on the chips inside the package structure 20, so as to reduce the electromagnetic interference of the chips to other circuits.

[0047] Please refer to FIG. 2 and FIG. 3. FIG. 2 is a structural schematic diagram of a first embodiment of the package structure 20 shown in FIG. 1, wherein the package layer 23 of the package structure 20 is not shown. FIG. 3 is a sectional schematic diagram of the package structure 20 shown in FIG. 2 at A-A. The package structure 20 includes a substrate 21, a chip 22, a package layer 23, a first metal piece 24, a second metal piece 25, and a shielding layer 26.

[0048] The substrate 21 includes a board body 211, a ground line 212, and signal lines (not labeled in the figure). The board body 211 can be a hard package substrate, such as a Bismaleimide Triazine Substrate (BT Substrate), an Ajinomoto Build-up Film Substrate (ABF Substrate), a Molded Interconnect Substrate (MIS), or the like. Alternatively, the board body 211 can be a flexible package substrate. Further alternatively, the board body 211 can be a ceramic package substrate. The present application does not limit the material of the board body 211.

[0049] The board body 211 can include multiple sub-layers. For example, the board body 211 can include three sub-layers, which are a first sub-layer 2111, a second sub-layer 2112, and a third sub-layer 2113, respectively. The first sub-layer 2111, the second sub-layer 2112, and the third sub-layer 2113 are sequentially stacked along the thickness direction of the board body 211.

[0050] The ground line 212 is connected to the board body 211. Specifically, the ground line 212 can include a first ground line 2121 and a second ground line 2122. The first ground line 2121 is arranged between the first sub-layer 2111 and the second sub-layer 2112. The second ground line 2122 is arranged between the second sub-layer 2112 and the third sub-layer 2113.

[0051] In the present embodiment, the ground line 212 helps to reduce electromagnetic radiation interference (EMI) of the package structure 20 to the external environment and prevent external electromagnetic field interference (EMS) to the internal of the package structure 20. By reasonable layout and connection of the ground line 212, the electromagnetic compatibility of the package structure 20 can be improved, and its stable operation in a complex electromagnetic environment can be ensured.

[0052] In addition, in some cases, the ground line 212 can also help to dissipate heat in the package structure 20. This helps to improve the heat dissipation efficiency of the package structure 20 and prevent performance degradation or damage of the chip 22 due to overheating.

[0053] Further, the ground line 212 can effectively isolate and reduce crosstalk and cross-interference between different signal lines. In high-speed signal transmission, the interference between signals is an important problem, and the ground line 212 can reduce the mutual influence between signals by providing a stable potential reference point, thereby improving the integrity and accuracy of the signals.

[0054] The signal line is connected to the board body 211, and the signal line is arranged apart from the ground line 212. The connection mode of the signal line and the board body 211 can refer to the connection mode of the conductive line and the substrate of the common circuit board 10, and the application does not repeat the connection mode of the signal line and the board body 211.

[0055] The chip 22 is connected to the board body 211. The chip 22 is electrically connected to the signal line of the substrate 21. The number of the chip 22 can be multiple. The multiple chips 22 can include at least one positive chip 221 and at least one inverted chip 222.

[0056] The positive chip 221 includes a chip body 2211 and a lead 2212. The chip body 2211 is connected to the board body 211. The chip body 2211 can be provided with an electrical connection point 2213. The electrical connection point 2213 is arranged on the side of the chip body 2211 away from the board body 211. The electrical connection point 2213 can be a pad on the surface of the chip body 2211. The number of the electrical connection point 2213 is multiple, and each electrical connection point 2213 can be used for electrical connection with the first metal piece 24.

[0057] For example, one positive chip 221 can be provided with two electrical connection points 2213. The two electrical connection points 2213 are arranged at opposite positions of the positive chip 221.

[0058] One end of the lead 2212 is connected to the chip body 2211. The other end of the lead 2212 is electrically connected to the signal line of the substrate 21, so as to communicate the positive chip 221 with the substrate 21. For example, the surface of the chip body 2211 away from the board body 211 can be provided with a pad (not shown in the figure). The surface of the board body 211 facing the chip body can also be provided with a pad (not shown in the figure). The pad on the board body 211 can be electrically connected to the signal line of the substrate 21. One end of the lead 2212 can be electrically connected to the chip body 2211 through the pad on the surface of the chip body 2211. The other end of the lead 2212 can be electrically connected to the signal line of the substrate 21 through the pad on the board body 211.

[0059] The inverted chip 222 includes a chip body 2221, a conductive bump 2222 and an electrical connection piece 2223. The electrical connection piece 2223 and the conductive bump 2222 are respectively connected to the opposite sides of the chip body 2221 along the thickness direction. The side of the chip body 2221 provided with the conductive bump 2222 is connected to the board body 211 of the substrate 21, and the conductive bump 2222 is electrically connected to the signal line of the substrate 21. The electrical connection piece 2223 is used for electrical connection with the first metal piece 24. The electrical connection piece 2223 can be a pad on the surface of the side of the inverted chip 222 away from the conductive bump 2222. Alternatively, the electrical connection piece 2223 can be a metal layer provided on the surface of the side of the inverted chip 222 away from the conductive bump 2222.

[0060] Referring to Fig. 3 again, the encapsulation layer 23 is connected to the surface of the substrate 21 where the chip 22 is located. The encapsulation layer 23 covers part of the surface of the substrate 21 and the chip 22.

[0061] In the present embodiment, the encapsulation layer 23 can provide a physical barrier for the chip 22 to prevent dust, moisture and mechanical impact in the external environment from damaging the chip 22. The encapsulation layer 23 can also prevent the chip 22 from reacting with chemical substances in the external environment, thereby prolonging the service life of the encapsulation structure 20. The encapsulation layer 23 also provides a firm and reliable mechanical support for the chip 22, and the encapsulation layer 23 can maintain the structural stability and reliability of the chip 22. The encapsulation layer 23 hides the internal complex structure and only retains the necessary external interface for the user to use. This allows the user to not need to care about the internal complex structure and principle, and only needs to complete the use and maintenance of the product through simple operation.

[0062] The first metal piece 24 can be connected to the side of the chip 22 away from the board body 211 through the encapsulation layer 23. The shielding layer 26 electrically connects the end of the first metal piece 24 away from the board body 211 to the ground wire 212, thereby forming an electromagnetic shielding structure. The second metal piece 25 can penetrate the encapsulation layer 23 along the thickness direction of the encapsulation layer 23. One end of the second metal piece 25 is connected to the board body 211, and the end of the second metal piece 25 away from the board body 211 is connected to the shielding layer 26, thereby forming an electromagnetic shielding structure. The following will illustrate various different structures of the first metal piece 24 and the second metal piece 25.

[0063] In a first possible embodiment, referring to Fig. 3 again, the first metal piece 24 and the second metal piece 25 can be metal wires.

[0064] Specifically, the encapsulation layer 23 can be provided with a plurality of first through holes 231 and a plurality of second through holes 232. The first through holes 231 and the second through holes 232 penetrate the encapsulation layer 23 along the thickness direction of the encapsulation layer 23. The extension direction of the first through holes 231 and the second through holes 232 can be perpendicular to the plane where the board body 211 is located. The first through holes 231 and the second through holes 232 are arranged in a spaced manner. The first through holes 231 are located at the side of the chip 22 away from the board body 211 of the substrate 21. The second through holes 232 are arranged in a staggered manner with the chip 22. The second through holes 232 are located at the side of the board body 211.

[0065] The first metal piece 24 is arranged in the first through hole 231. The end surface of the first metal piece 24 away from the chip 22 can be flush with the surface of the packaging layer 23 away from the board body 211. The first metal piece 24 can be perpendicular to the plane in which the board body 211 is located. In the thickness direction of the packaging structure 20, the orthogonal projection of the first metal piece 24 to the chip 22 falls within the surface range of the chip 22 away from the substrate 21. When the chip 22 is a positive chip 221, the first metal piece 24 can be electrically connected to the electrical connection point 2213 of the positive chip 221. The two first metal pieces 24 can be connected to the diagonal positions of the positive chip 221 through the electrical connection point 2213. When the chip 22 is a flip chip 222, the first metal piece 24 can be electrically connected to the electrical connection piece 2223 of the flip chip 222. The two first metal pieces 24 can be connected to the diagonal positions of the flip chip 222.

[0066] In other embodiments, the two first metal pieces 24 can be located on both sides in the width direction of the chip 22, or on both sides in the length direction of the chip 22.

[0067] The second metal piece 25 is arranged in the second through hole 232. The side end surface of the second metal piece 25 away from the board body 211 can be flush with the surface of the packaging layer 23 away from the board body 211. The second metal piece 25 can be perpendicular to the plane in which the board body 211 is located.

[0068] The shielding layer 26 is electrically connected to the end surface of the first metal piece 24 away from the chip 22 and the end surface of the second metal piece 25 away from the board body 211. Specifically, the shielding layer 26 covers the surface of the packaging layer 23 away from the board body 211, the circumferential surface of the packaging layer 23, and part of the circumferential surface of the board body 211. The shielding layer 26 is electrically connected to the ground wire 212 of the substrate 21. The shielding layer 26 can be formed by sputtering or other processes, for example. The radius of the first metal piece 24 is r, and the area of the shielding layer 26 combined with the first metal piece 24 is the area of the end surface of the first metal piece 24, πr2.

[0069] In the present embodiment, the first metal piece 24, the second metal piece 25, and the shielding layer 26 together form a shielding structure, which effectively reduces the influence of external electromagnetic fields on the chip 22 while achieving packaging, and also prevents the electromagnetic field generated by the chip 22 from interfering with the outside world, while changing the resonance frequency to prevent interference and crosstalk between the chip 22 and other devices, achieving high suppression and isolation between high-frequency signals and between analog signals and digital signals.

[0070] In addition, the first metal piece 24 is directly connected to the surface of the chip 22, the space above the chip 22 can be flexibly used, and since the first metal piece 24 is directly connected to the chip 22, the first metal piece 24 can directly reduce the electromagnetic waves near the chip 22, avoid the electromagnetic waves from the outside to the chip 22 to affect the signal transmission of the chip 22, and at the same time avoid the electromagnetic waves generated by the chip 22 during operation to be transmitted to the outside of the packaging structure 20 to affect the operation of other electronic elements.

[0071] The first metal piece 24 can be perpendicular to the plane where the plate body 211 is located. Therefore, the length of the first metal piece 24 is smaller, and the surface area of the first metal piece 24 subjected to external force is also smaller. During the processing or assembly of the packaging structure 20, the first metal piece 24 is less likely to deform or break due to the less force position, thereby ensuring the shielding effect of the first metal piece 24, so that the overall electromagnetic shielding effect of the packaging structure 20 is more stable.

[0072] For example, the packaging structure 20 can include a plurality of chips 22. The plurality of chips 22 are arranged at intervals on the plate. The number of chips 22 can be five, and the five chips 22 are one first chip 2201 and four second chips 2202. The area of the first chip 2201 occupying the substrate 21 is larger than the area of the second chip 2202 occupying the substrate 21. The first chip 2201 can be arranged at the middle region of the plate. The four second chips 2202 can be arranged at the four corner positions of the plate. Among them, the first chip 2201 and the second chip 2202 can be one of a positive chip 221 or a flip chip 222, and the present application only describes the different sizes of the chips 22 of the packaging structure 20 through the description of the first chip 2201 and the second chip 2202.

[0073] A plurality of pads 214 can be arranged on the substrate 21. The pads 214 can be separate metal blocks connected to the surface of the plate and electrically connected to the ground 212 of the substrate 21. Alternatively, the pads 214 can also be strips and distributed in the gap between the two connected chips 22.

[0074] Each positive chip 221 can be provided with two electrical connection points 2213. Each electrical connection point 2213 can be electrically connected to a first metal piece 24.

[0075] The electrical connection piece 2223 of each flip chip 222 can be electrically connected to two second metal pieces 25.

[0076] In a second possible embodiment, please refer to FIG. 4, which is a sectional view of a second embodiment of the packaging structure 20 shown in FIG. 1. Different from the first possible embodiment, the shielding layer 26 in this embodiment also covers the end of the first metal piece 24 and the second metal piece 25 away from the substrate 21.

[0077] Specifically, the packaging layer 23 further comprises a first recess 233 and a second recess 234. The first recess 233 is recessed from the surface of the plate body 211 and communicates with the first through hole 231. The opening of the first through hole 231 away from the substrate 21 can be located in the middle region of the bottom of the first recess 233.

[0078] The second recess 234 is recessed from the surface of the plate body 211 and communicates with the second through hole 232. The second recess 234 can be arranged separately from the first recess 233, or the second recess 234 can also communicate with the first recess 233, and the present application does not limit the positional relationship between the second recess 234 and the first recess 233.

[0079] The first metal piece 24 penetrates the first through hole 231. One end of the first metal piece 24 away from the chip 22 protrudes relative to the bottom of the first recess 233. The shielding layer 26 covers the wall of the first recess 233 and the end of the first metal piece 24 away from the chip 22.

[0080] The second metal piece 25 penetrates the second through hole 232. One end of the second metal piece 25 away from the plate body 211 protrudes relative to the bottom of the second recess 234, and the shielding layer 26 covers the wall of the second recess 234 and the end of the second metal piece 25 away from the chip 22.

[0081] In the present embodiment, the shielding layer 26 can cover one end of the first metal piece 24 and the second metal piece 25. The radius of the first metal piece 24 is r, and the length of the first metal piece 24 beyond the bottom of the first recess 233 is d. The area of the shielding layer 26 covering the first metal piece 24 is (πr2+2πrd). At this time, the combined area of the shielding layer 26 and the first metal piece 24 increases by 2πrd. When the length d of the first metal piece 24 beyond the bottom of the first recess 233 is greater than the radius r of the first metal piece 24, the combined area of the shielding layer 26 and the first metal piece 24 increases by more than 2 times. Increasing the combined area of the shielding layer 26 and the first metal piece 24 can improve the electrical connection stability of the first metal piece 24 and the ground line 212 of the substrate 21, thereby improving the electromagnetic shielding stability of the overall packaging structure 20.

[0082] Referring to FIG. 5, FIG. 5 is a diagram of simulation results of different packaging structures. In the diagram, a represents simulation results of a packaging structure without the shielding layer, the first metal piece and the second metal piece, b represents simulation results of a packaging structure including only the shielding layer and without the first metal piece and the second metal piece, c represents simulation results of a packaging structure including the shielding layer and one chip provided with one first metal piece, and d represents simulation results of a packaging structure including the shielding layer and one chip provided with two first metal pieces. As can be seen from the diagram, the electromagnetic shielding effect of the simulation structure shown in d of the packaging structure 20 is better, and the isolation degree is -68.89 dB at an electromagnetic frequency of 30 GHz. The isolation degree of the simulation results shown in b of the packaging structure provided with only the shielding layer 26 and without the first metal piece 24 and the second metal piece 25 is -52.08 dB at an electromagnetic frequency of 30 GHz, and the isolation degree of the packaging structure 20 provided in the embodiment has a yield of more than 16 dB compared with the packaging structure 20 provided with only the shielding layer 26.

[0083] In a third possible embodiment, referring to FIG. 6, FIG. 6 is a diagram of a structure of a third embodiment of the packaging structure 20 shown in FIG. 1. Different from the first possible embodiment, the first metal piece 24 and the second metal piece 25 in the embodiment can be a metal barrier structure with a width greater than that of the metal wire. The first metal piece 24 and the second metal piece 25 can be formed after silver glue is filled in the slotted position of the packaging layer 23 and solidified.

[0084] Specifically, the packaging layer 23 is provided with a first accommodating groove 235 and a second accommodating groove 236. The first accommodating groove 235 penetrates through the packaging layer 23 along the thickness direction of the packaging layer 23 to expose the surface of the chip 22. The first accommodating groove 235 extends along a first direction, wherein the first direction intersects the thickness direction of the packaging structure 20. The first direction can be any direction in the plane where the substrate 21 of the packaging structure 20 is located.

[0085] The second accommodating groove 236 penetrates through the packaging layer 23 along the thickness direction of the packaging layer 23 to expose the surface of the board body 211 of the substrate 21. The second accommodating groove 236 extends along any direction in the plane where the substrate 21 is located. The second accommodating groove 236 is arranged in a spaced manner with the first accommodating groove 235, and the second accommodating groove 236 is arranged in a spaced manner with the edge of the chip 22. The extension directions of the second accommodating grooves 236 can be the same or different. The second accommodating grooves 236 can extend along the gaps between the plurality of chips 22.

[0086] The first metal piece 24 is embedded in the first accommodating groove 235. The side of the first metal piece 24 away from the chip 22 is arranged in a flush manner with the side of the packaging layer 23 away from the substrate 21, and is connected with the shielding layer 26.

[0087] The second metal piece 25 is embedded in the second accommodating groove 236. The side of the second metal piece 25 away from the chip 22 is flush with the side of the packaging layer 23 away from the substrate 21, and is connected with the shielding layer 26.

[0088] In the embodiment, the interval and the setting position of the first metal piece 24 and the second metal piece 25 can be determined by simulation test, so that the packaging structure 20 has better electromagnetic shielding effect. Since the combination strength of the metal barrier wall formed by the silver paste and the shielding layer 26 is high, the electromagnetic shielding structure formed by the first metal piece 24, the second metal piece 25 and the shielding layer 26 has better effect, so that the phenomenon of self-excited oscillation is eliminated in the packaging structure 20, and the stable operation of the packaging structure 20 is ensured.

[0089] For example, referring to FIG. 7, FIG. 7 is a cross-sectional view of the packaging structure 20 at B-B in FIG. 6, wherein the packaging layer 23 is not shown. The number of the second metal pieces 25 can be multiple. The multiple second metal pieces 25 are arranged at intervals and are located between two adjacent chips 22 (the first chip 2201 or the second chip 2202). The number of the second metal pieces 25 can be six. The six second metal pieces 25 can be divided into three groups. They are the first group of second metal pieces 25, the second group of second metal pieces 25, and the third group of second metal pieces 25. The first group of second metal pieces 25 includes two second metal pieces 25, which are respectively located at two opposite sides of the first chip 2201, so as to block the first chip 2201 and the second chip 2202.

[0090] The second group of second metal pieces 25 includes two second metal pieces 25 arranged at intervals, which are arranged between two adjacent second chips 2202, so as to block the two second chips 2202. The second group of second metal pieces 25 can be extended and connected to the first group of second metal pieces 25, and is arranged intersecting with one second metal piece 25 in the first group.

[0091] In addition, another second group of second metal pieces 25 is connected between another two second chips 2202. The specific arrangement can be referred to the description above.

[0092] In the embodiment, the second metal piece 25 can separate different chips 22. The first metal piece 24 can be directly connected to the chip 22, so as to further reduce the electromagnetic interference received or emitted by the chip 22.

[0093] In the fourth possible embodiment, referring to FIG. 8, FIG. 8 is a cross-sectional view of the fourth embodiment of the packaging structure 20 shown in FIG. 1. Different from the third possible embodiment, the combination area of the end of the first metal piece 24 and the second metal piece 25 away from the substrate 21 with the shielding layer 26 is increased.

[0094] Specifically, the first accommodating groove 235 includes a first sub-groove 2351 and a second sub-groove 2352. The first sub-groove 2351 penetrates the encapsulation layer 23 along the thickness direction of the encapsulation layer 23. The second sub-groove 2352 is recessed from one side of the encapsulation layer 23 away from the board body 211 of the substrate 21, and is in communication with the first sub-groove 2351. The first sub-groove 2351 can penetrate the middle region of the second sub-groove 2352 through the opening of the groove bottom wall of the second sub-groove 2352.

[0095] The second accommodating groove 236 includes a third sub-groove 2361 and a fourth sub-groove 2362. The third sub-groove 2361 penetrates the encapsulation layer 23 along the thickness direction of the encapsulation layer 23. The fourth sub-groove 2362 is recessed from one side of the encapsulation layer 23 away from the board body 211 of the substrate 21, and is in communication with the third sub-groove 2361. The third sub-groove 2361 can penetrate the middle region of the fourth sub-groove 2362 through the opening of the groove bottom wall of the fourth sub-groove 2362.

[0096] The first metal piece 24 includes a first part 241 and a second part 242. The first part 241 penetrates the encapsulation layer 23, and is connected to the surface of the chip 22 away from the board body 211. The first part 241 is embedded in the first sub-groove 2351. The second part 242 is embedded in the second sub-groove 2352. The second part 242 is connected to one end of the first part 241 away from the chip 22. The peripheral side surface of the second part 242 is arranged protruding relative to the peripheral side surface of the first part 241, and the end surface of the second part 242 away from the first part 241 is connected to the shielding layer 26.

[0097] The second metal piece 25 includes a third part 251 and a fourth part 252. The third part 251 penetrates the encapsulation layer 23, and is connected to the surface of the board body 211. The third part 251 is embedded in the third sub-groove 2361. The fourth part 252 is embedded in the fourth sub-groove 2362. The fourth part 252 is connected to one end of the third part 251 away from the chip 22, and the peripheral side surface of the third part 251 is arranged protruding relative to the peripheral side surface of the fourth part 252. The end surface of the fourth part 252 away from the third part 251 is connected to the shielding layer 26.

[0098] In the present embodiment, the second part 242 and the fourth part 252 have a larger area combined with the shielding layer 26, and the transmission path of the current between the metal piece and the shielding layer 26 is more extensive and uniform, reducing the current concentration and hot spot effect caused by the small connection area, thereby improving the continuity of the current. This helps to reduce the leakage of electromagnetic radiation of the packaging structure 20, and improves the shielding effect.

[0099] The greater connection area between the second portion 242 and the fourth portion 252 and the shielding layer 26 can enable the shielding layer 26 to better perform its role of blocking or reducing the transmission of electromagnetic energy. When an external electromagnetic field attempts to penetrate the shielding layer 26, the greater connection area increases the dissipation path of the electromagnetic energy within the shielding layer 26, thereby enhancing the shielding layer's 26 ability to attenuate electromagnetic waves.

[0100] Increasing the connection area of the metal pieces (the first metal piece 24 and the second metal piece 25) with the shielding layer 26 is equivalent to increasing the contact points and contact area between them, which helps to enhance the connection strength between them. When subjected to external forces or vibrations, a stronger connection can reduce the risk of shielding failure due to loosening or breaking of the metal pieces.

[0101] In some cases, the shielding layer 26 of the packaging structure 20 also needs to bear the function of heat dissipation. Increasing the connection area of the metal pieces with the shielding layer 26 can improve the heat conduction performance between them, so that heat can be transferred from the inside to the outside more quickly, thereby reducing the working temperature of the chip 22 and improving the overall performance.

[0102] Increasing the connection area of the metal pieces with the shielding layer 26 can reduce the coupling effect between the metal pieces and the shielding layer 26. Coupling effect is an important form of electromagnetic interference, which can cause electromagnetic energy to be transmitted and interfered between different components. Reducing this coupling effect can reduce the impact of electromagnetic interference on the performance of the electronic device 100.

[0103] The above is an exemplary embodiment of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, some improvements and refinements can be made, which are also considered within the scope of protection of the present application.

Claims

1. A package structure, characterized by, The package structure comprises: a substrate comprising a substrate body and a ground wire connected to the substrate body; a chip connected to the substrate body; a packaging layer covering the substrate body and the chip; a first metal piece connected to a surface of the chip away from the substrate body through the packaging layer, wherein a normal projection of the first metal piece in a thickness direction of the substrate is located in a surface of the chip away from the substrate body; and a shielding layer electrically connecting one end of the first metal piece away from the substrate body to the ground wire.

2. The package structure of claim 1, wherein, The package structure further comprises a second metal piece, one end of which is connected to the substrate body, and the second metal piece penetrates the packaging layer in the thickness direction of the packaging layer, and one end of the second metal piece away from the substrate body is connected to the shielding layer.

3. The package structure of claim 1 or 2, wherein, The packaging layer is provided with a through hole penetrating the packaging layer in the thickness direction of the packaging layer and a recess recessed from a surface of the packaging layer away from the substrate body and communicating with the through hole; the first metal piece is arranged in the through hole, and one end of the first metal piece away from the chip protrudes relative to a bottom of the recess and is covered by the shielding layer.

4. The package structure of claim 1 or 2, wherein, The packaging layer is provided with a first accommodating groove penetrating the packaging layer in the thickness direction of the packaging layer, the first accommodating groove is located on a side of the chip away from the substrate body, the first accommodating groove extends in a first direction, and the first metal piece is embedded in the first accommodating groove, wherein the first direction intersects the thickness direction of the package structure.

5. The package structure of claim 4, wherein, The first metal piece comprises a first part and a second part, the first part penetrates the packaging layer and is connected to a surface of the chip away from the substrate body, the second part is connected to one end of the first part away from the chip, a peripheral side surface of the second part is arranged protruding relative to a peripheral side surface of the first part, and an end surface of the second part away from the first part is connected to the shielding layer.

6. The package structure of claim 2, wherein, The packaging layer is provided with a second accommodating groove penetrating the packaging layer in the thickness direction of the packaging layer to expose a surface of the substrate body, the second accommodating groove is arranged spaced apart from an edge of the chip, and the second metal piece is embedded in the second accommodating groove.

7. The package structure of claim 1 or 2, wherein, The substrate further comprises a signal line connected to the substrate body, the chip comprises a chip body and a lead wire, the chip body is connected to the substrate body, a surface of the chip body away from the substrate body is provided with an electrical connection point, one end of the lead wire is connected to the surface of the chip body away from the substrate body, and the other end is electrically connected to the signal line; the first metal piece is electrically connected to the electrical connection point.

8. The package structure of claim 1 or 2, wherein, The substrate further comprises a signal line connected to the substrate body, the chip comprises a chip body, a conductive bump and an electrical connection piece, the chip body and the substrate body are arranged in a stack, the conductive bump is connected between the chip body and the substrate body, and the electrical connection piece is arranged on a side of the chip body away from the conductive bump; the first metal piece is electrically connected to the electrical connection piece.

9. The package structure of claim 7, wherein, The number of the first metal pieces is at least two, and one chip includes two electric connection points, which are respectively arranged at opposite ends of the chip along a first direction, and each first metal piece is electrically connected with one electric connection point.

10. An electronic device, comprising: The electronic device includes a circuit board and the packaging structure according to any one of claims 1-9, and the circuit board is electrically connected with the signal line.

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