Storage space management method and apparatus, and electronic device and medium

Abstract

A storage space management method and apparatus, and an electronic device and a medium, which relate to the technical field of electronic devices. The method comprises: on the basis of the size of a first storage area in a first storage space of an electronic device, configuring a target cache in a second storage space of the electronic device.

Description

Storage space management methods, devices, electronic devices and media

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410999995.0, filed in China on July 24, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application belongs to the field of electronic equipment technology, and specifically relates to a storage space management method, device, electronic device and medium. Background Technology

[0004] Memory Tagging Extension (MTE) is a mechanism for checking the proper use of data in memory. MTE adds tags to memory to track and prevent common illegal memory operations. These tags typically include both key and lock information.

[0005] In related technologies, the key stores a pointer, while the tag lock is stored in external memory. However, due to the slow access speed of external memory, the bus design supports MTE (Matching Entity Cache) functionality by setting up a dedicated MTE tag cache on the chip to cache the lock information stored in external memory, and then reading the lock information from the MTE tag cache. However, the MTE tag cache is a large storage space specifically designed for storing lock information. The MTE tag cache is typically large, requiring a significant amount of chip area, and it cannot be used for other storage purposes, leading to a waste of system resources and consequently poor system performance. Summary of the Invention

[0006] The purpose of this application is to provide a storage space management method, apparatus, electronic device, and medium that can save system resources and thus improve system performance.

[0007] In a first aspect, embodiments of this application provide a storage space management method, the method comprising: configuring a target cache area in a first storage space of an electronic device; wherein the target cache area is used to cache lock information corresponding to a first storage area, the first storage area being a storage area in a second storage space of the electronic device that needs to be marked by lock information; the first storage space comprising any one of the following: system-level cache, level 3 cache, static random access memory (SRAM).

[0008] Secondly, embodiments of this application provide a storage space management device, which includes: a processing module; the processing module is configured to configure a target cache area in a first storage space of an electronic device, wherein the target cache area is used to cache lock information corresponding to a first storage area, the first storage area being a storage area in a second storage space of the electronic device that needs to be marked by lock information; the first storage space includes any one of the following: system-level cache, level 3 cache, static random access memory (SRAM).

[0009] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, the memory storing programs or instructions executable on the processor, the programs or instructions, when executed by the processor, implementing the steps of the method described in the first aspect.

[0010] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0011] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0012] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the method described in the first aspect.

[0013] In this embodiment, a target cache area is configured in the first storage space of the electronic device. This target cache area is used to cache lock information corresponding to the first storage area, which is a storage area in the second storage space of the electronic device that needs to be marked with lock information. The first storage space includes any one of the following: system-level cache, level 3 cache, or static random access memory (SRAM). This method allows for the flexible configuration of a cache area in the first storage space of the electronic device to store the lock information corresponding to that storage area, replacing a fixed-size storage space specifically designed for storing lock information. This saves system resources occupied by a fixed-size storage area, thereby improving system performance. Attached Figure Description

[0014] Figure 1 is a schematic diagram of one of the system architectures used in the storage space management method provided in the embodiments of this application;

[0015] Figure 2 is a second schematic diagram of the system architecture used in the storage space management method provided in this application embodiment;

[0016] Figure 3 is a flowchart illustrating the storage space management method provided in an embodiment of this application;

[0017] Figure 4 is a schematic diagram of the storage space management device provided in an embodiment of this application;

[0018] Figure 5 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0019] Figure 6 is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0022] The terms "at least one," "at least one of," etc., used in the specification and claims of this application refer to any one, any two, or a combination of two or more of the included items. For example, at least one of a, b, and c can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple. Similarly, "at least two" refers to two or more items, and its meaning is similar to that of "at least one."

[0023] MTE is a feature of the Advanced Reduced Instruction Set Machine (ARM) architecture. When implementing MTE, it utilizes the Top Byte Ignore (TBI) feature of the Armv8-A architecture. It uses the high 4 bits of the pointer to store key information and uses dedicated memory to store lock information for the protected memory space. Each time it is accessed, it checks whether the key information and lock information match. If the value of the key information and the value of the lock information are the same, it means that access to the memory space is allowed; otherwise, an error is reported.

[0024] Specifically, this needs to be stored in external memory, such as in the tag space (zone) of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). Because DDR access speed is relatively slow, the ARM bus design incorporates an MTE Tag Cache to support MTE functionality. This cache is specifically used to cache lock information in the DDR tag zones, eliminating the need to read lock information from DDR every time, thus accelerating lock information retrieval. However, the MTE Tag Cache is a large storage space designed specifically for storing lock information. Its size is typically large, requiring significant chip area, and it cannot be used for other storage purposes, leading to wasted system resources and consequently poor system performance.

[0025] The storage space management method provided in this application embodiment can flexibly configure a cache area for storing lock information corresponding to the storage area in the first storage space of the electronic device. In this way, by configuring a cache area for storing lock information instead of designing a fixed-size cache area on the chip through hardware, system resources are saved and system performance is improved.

[0026] Figure 1 is a schematic diagram of the system architecture used in the storage space management method provided in this application embodiment. As shown in Figure 1, the system architecture may include: CPU, L3 cache, split logic module, check logic module, AXI / ACE-lite, system-level cache, and DDR. The CPU sends an access address to the L3 cache, which includes the memory address of the data to be accessed and a tag key. The L3 cache sends the access request to the split logic module, which separates the memory address and tag key and continues to access the data from memory. Simultaneously, it passes the tag key to the check logic module, which then passes the tag lock address to the tag cache in the system cache. The tag cache retrieves the tag lock from memory according to the corresponding tag lock address. The check logic obtains the corresponding tag lock from the tag cache, compares the tag key and the tag lock, and returns a check result to the CPU.

[0027] Figure 2 is a schematic diagram of the system architecture used in the storage space management method provided in this application embodiment. As shown in Figure 2, the system architecture may include: CPU, L3 cache, split logic module, check logic module, AXI / ACE-lite, system-level cache, and DDR. Specifically, the CPU sends an access address to the L3 cache, which includes the memory address of the data to be accessed and a tag key. The L3 cache sends the access request to the split logic module, which separates the memory address and tag key, continues to access the data from memory, and simultaneously passes the tag key to the check logic module. The check logic module then passes the tag lock address to the Tag Cache in the L3 cache. The Tag Cache retrieves the tag lock from memory according to the corresponding tag lock address. The check logic retrieves the corresponding tag lock from the Tag Cache, compares the tag key and the tag lock, and returns a check result to the CPU.

[0028] The storage space management method provided in this application can be executed by an electronic device, or by at least one of the functional modules and physical modules in the electronic device that can implement the storage space management method. The specific implementation can be determined according to actual usage requirements, and this invention does not limit it.

[0029] The storage space management method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0030] Figure 3 is a flowchart illustrating the storage space management method provided in an embodiment of this application. As shown in Figure 3, the storage space management method may include the following step 201:

[0031] Step 201: Configure the target cache in the first storage space of the electronic device.

[0032] The aforementioned target cache area is used to cache the lock information corresponding to the first storage area, which is the storage area in the second storage space of the electronic device that needs to be marked by the lock information.

[0033] In some embodiments of this application, the first storage area mentioned above refers to the physical memory space in the entire physical memory space of the electronic device that needs to be protected by the memory tag mechanism.

[0034] It should be noted that the memory tagging mechanism tracks and prevents illegal operations on memory by marking allocated memory, that is, by assigning lock information (Key) and lock information (Lock) to the memory.

[0035] In some embodiments of this application, the first storage region described above may be a memory block.

[0036] It should be noted that a memory block is a contiguous memory space allocated by the system from physical memory for storing data.

[0037] In some embodiments of this application, the second storage space may include at least one of the following: Random Access Memory (RAM), Novel Non-Volatile Memory (NVM), Read-Only Memory (ROM), or Flash Memory (FLASH).

[0038] In some embodiments of this application, RAM includes, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).

[0039] It should be noted that DDR SDRAM can also be called DDR.

[0040] In some embodiments of this application, NVM includes, but is not limited to, flash memory, magnetic random-access memory (MRAM), phase-change memory, or Oversinski effect unified memory (PCM).

[0041] As is understandable, NVM is a memory technology that retains stored data even after power is lost. Unlike traditional volatile random access memory, NVM can store data for extended periods without requiring a continuous power supply.

[0042] It should be noted that the memory listed above is only an exemplary description of the second storage space. In practice, the second storage space can also be other storage spaces that need to be protected, and this application embodiment does not limit this.

[0043] In some embodiments of this application, the first storage area may be part or all of the storage space (i.e., memory space) of the second storage space.

[0044] For example, taking DDR as the second storage space, the first storage area can be the memory space between address 0x8000 and address 0x9000 in DDR.

[0045] It should be noted that the memory space between 0x8000 and 0x9000 is a contiguous memory space from address 0x8000 to address 0x8FFF (excluding 0x9000), containing a total capacity of 10KB.

[0046] For another example, taking DDR as the second storage space, the first storage area can be a contiguous memory space in DDR with a total size of 1MB (i.e., 0x100000 bytes) of data starting from address 0x20000000.

[0047] It should be noted that the size of DDR memory can typically range from tens of MB (megabytes) to tens of GB (gigabytes), depending on the type and capacity of memory supported by the motherboard and the number of memory modules installed by the user. The size of the DDR memory space that needs to be protected depends on the system's security policy and potential security threats, and this application does not limit this. For example, memory areas containing sensitive data and execution areas of critical code usually need to be protected; therefore, the first storage area can be the memory area containing sensitive data, the execution area of ​​critical code, etc.

[0048] In some embodiments of this application, the lock information corresponding to the first storage area is used to protect the first storage area. Access is only allowed when the key information of the pointer attempting to access the first storage area matches the lock information of the first storage area.

[0049] In some embodiments of this application, the key information is stored in physical memory associated with the first memory region and at a location aligned with the first memory region.

[0050] It should be noted that the lock information mentioned above can also be called a memory tag, and the key information mentioned above can be called an address tag.

[0051] In some embodiments of this application, the first storage space described above may include any of the following: system-level cache, level 3 cache, static random access memory (SRAM).

[0052] It should be noted that system-level cache is a form of cache located between the CPU and main memory, designed to address the speed difference between CPU and main memory.

[0053] In some embodiments of this application, the system-level cache includes, but is not limited to, any one of the following: Level 1 cache, Level 2 cache, and Level 3 cache.

[0054] It should be noted that the L3 cache can be built into the CPU or located outside the CPU.

[0055] In some embodiments of this application, SRAM includes, but is not limited to, SRMA inside the SOC chip, asynchronous SRAM (AsyncSRAM), synchronous SRAM (Sync SRAM), pipelined burst SRAM (PBSRAM), etc.

[0056] In some embodiments of this application, the SRMA inside the SOC chip includes, but is not limited to, the always-on subsystem AON internal memory and the AON internal volatile memory.

[0057] In some embodiments of this application, in a SoC with a system-level cache, at least a portion of the storage space of the system cache can be configured as the target cache; or, in a SoC without a system-level cache, at least a portion of the storage space of the L3 cache can be configured as the target cache.

[0058] In some embodiments of this application, the target cache area may include at least a portion of the storage space in the first storage space.

[0059] For example, taking the first storage space as a system-level cache, the target cache area can be a contiguous 128KB storage space in the system-level cache, or a non-contiguous 128KB storage space in the system-level cache.

[0060] In some embodiments of this application, the electronic device can use the Application Processor Central Processing Unit (AP CPU) to set the size of the target cache area according to the size of the first storage area, and call the hardware interface driver of the first storage space to configure the target cache area in the first storage space.

[0061] The storage space management method provided in this application configures a target cache area in the first storage space of an electronic device. The target cache area is used to cache lock information corresponding to a first storage area, which is a storage area in the second storage space of the electronic device that needs to be marked with lock information. The first storage space includes any one of the following: system-level cache, level 3 cache, or static random access memory (SRAM). This method allows for the flexible configuration of a cache area in the first storage space of the electronic device to store lock information corresponding to that storage area, replacing a fixed-size storage space specifically designed for storing lock information, thus eliminating the need for a separate MTE Tag Cache module within the SOC chip. This saves system resources occupied by a fixed-size storage area, thereby improving system performance.

[0062] In some embodiments of this application, after step 201 described above, the storage space management method provided in this application may further include steps 202 and 203:

[0063] Step 202: If the first process accesses the first storage area, obtain the lock information corresponding to the first storage area from the target cache.

[0064] Step 203: If the lock information matches the key information corresponding to the first storage area, the first process is allowed to access the first storage area.

[0065] In some embodiments of this application, the first process described above can be any region that accesses the first storage region.

[0066] In some embodiments of this application, when a first process accesses a first storage area, the electronic device can obtain the lock information corresponding to the first storage area from the target cache and obtain the key information corresponding to the first storage area from the pointer corresponding to the first storage area. Then, if the lock information and the key information match, the first process is allowed to access the first storage area, or if the lock information and the key information do not match, the first process is prohibited from accessing the first storage area.

[0067] In this embodiment of the application, when the first process accesses the first storage area, the electronic device can obtain the lock information of the first storage area from the configured target cache area, thereby enabling it to quickly obtain the lock information of the first storage area and improve information access efficiency.

[0068] In some embodiments of this application, step 201 may include steps 201a and 201b:

[0069] Step 201a: Determine the target cache size based on the size of the first storage area in the second storage space.

[0070] Step 201b: From the target storage space, determine a storage region that matches the target cache size, and configure the storage region as the target cache.

[0071] In some embodiments of this application, the electronic device can obtain the start physical address and end physical address of the first storage area, and then determine the size of the first storage area based on the start physical address and end physical address.

[0072] In some embodiments of this application, the electronic device can determine the target cache size based on the correspondence between the size of the storage area and the size of the cache area, according to the size of the first storage area.

[0073] In some embodiments of this application, the above correspondence can be a pre-set correspondence. For example, the above correspondence can be as follows: if the storage area size is between 0GB and 8GB, the corresponding cache size is 0KB to 64KB; if the storage area size is between 8GB and 16GB, the corresponding cache size is 64KB to 128KB; if the storage area size is between 16GB and 32GB, the corresponding cache size is 128KB to 256KB; if the storage area size is between 32KB and 64GB, the corresponding cache size is 256KB to 512KB; and if the storage area size is between 64GB and 128GB, the corresponding cache size is 512KB to 1MB.

[0074] It should be noted that the above-listed correspondences are only some possible examples, and there may be other correspondences in actual applications. This application does not limit these correspondences.

[0075] For example, taking the first storage area as the memory area that needs to be protected in DDR, assuming that the size of the memory area that needs to be protected in DDR is 16GB, the target cache size is determined to be 128KB.

[0076] For another example, taking the first storage area as the memory area that needs to be protected in DDR, assuming that the size of the memory area that needs to be protected in DDR is 8GB, then the target cache size is determined to be 64KB.

[0077] In some embodiments of this application, the electronic device can, during system initialization, determine a storage region matching the size of the target cache region from the target storage space based on the size of the first storage region, and configure the storage region as the target cache region.

[0078] For example, taking DDR as the second storage space and system-level cache as the first storage space, when the electronic device is powered on, a portion of the cache in the System Cache is allocated as a dedicated Tag Cache according to the size of the storage area that needs to be protected in the DDR. Assuming the entire 16GB of DDR memory space needs to be protected, the AP CPU can set the Tag Cache size to 128KB in the boot code during system initialization, and then call the hardware interface driver of the System Cache to configure the 128KB Tag Cache in the System Cache. If 8GB of DDR address space needs to be protected, then a 64KB cache size is set in the System Cache as the Tag Cache.

[0079] It should be noted that the target cache area in this embodiment of the application may be referred to as Tag Cache.

[0080] In this embodiment, a target cache area is configured in the first storage space of the electronic device according to the size of the first storage area in the second storage space of the electronic device. By precisely matching the size of the storage area and the target cache area, it can be ensured that the cache area is not too large or too small, thereby avoiding the waste or insufficiency of memory resources. In turn, efficient use of storage space can avoid frequent memory allocation and reclamation operations, thereby improving the overall performance of the system.

[0081] In some embodiments of this application, after step 201 above, the storage space management method provided in this application may further include the following step 204:

[0082] Step 204: Adjust the size of the target cache area according to the resource usage status of the electronic device.

[0083] In some embodiments of this application, the above-mentioned resource usage status, i.e. the system resource usage of the electronic device, is used to characterize the system load of the electronic device, such as bus latency, memory traffic over a specific duration, etc.

[0084] In some embodiments of this application, the above-mentioned resource usage status includes, but is not limited to, at least one of the following: system memory access latency, system memory access count, size of remaining physical memory space of electronic device, size of remaining system-level cache space of electronic device, access frequency of cached information in target cache area, etc.

[0085] In some embodiments of this application, the electronic device can monitor the resource usage status in real time or periodically, and dynamically adjust the size of the target cache area according to the resource usage status.

[0086] In some embodiments of this application, the electronic device can release at least a portion of the storage space of the target cache to reduce the size of the target cache when the system load is high, or the electronic device can allocate a portion of the storage space to the target cache to increase the size of the target cache when the system load is low.

[0087] For example, when an electronic device is powered on, the 16GB DDR memory initially sets up 128KB of Tag Cache. When a high system load is detected, 64KB of Cache is released for system use, and 64KB of Tag Cache is reserved. Then, when a low system load is detected, 64KB of space is reallocated to Tag Cache.

[0088] In this embodiment, the size of the allocated cache area can be dynamically adjusted according to the resource usage status of the electronic device, thereby enabling reasonable allocation of system memory resources and dynamic adjustment in performance and system load, thereby improving system performance.

[0089] In some embodiments of this application, step 204 described above can be implemented by step 204a.

[0090] Step 204a: When the resource usage status of the electronic device meets the space release condition, release at least a portion of the cache space of the target cache area in the first storage space.

[0091] The aforementioned space release conditions include at least one of the following:

[0092] The system memory access latency is greater than or equal to the first threshold;

[0093] The number of system memory accesses is greater than or equal to the second threshold;

[0094] The remaining physical memory space of the electronic device is less than or equal to the third threshold;

[0095] The remaining system-level cache space of the electronic device is less than or equal to the fourth threshold;

[0096] The access frequency in the target cache is less than or equal to the fifth threshold.

[0097] In some embodiments of this application, when the resource usage state of the electronic device meets the space release condition, the electronic device can determine the size of the cache space that needs to be released, and then release the cache space of that size in the target cache area.

[0098] In some embodiments of this application, the electronic device can determine the size of the cache space to be released according to preset rules, or according to the free cache space in the target cache area, or randomly determine the size of the cache space to be released.

[0099] For example, when the resource usage status of the electronic device meets the space release conditions, the size of the cache space to be released can be determined according to preset rules as 1 / 2, 1 / 3 or 1 / 4 of the target cache space size.

[0100] As another example, when the resource usage status of the electronic device meets the space release condition, the free cache space in the target cache area is released.

[0101] For example, when the resource usage state of the electronic device meets the space release condition, a portion of the cache space in the target cache area is randomly released, such as 64KB of cache space.

[0102] It should be noted that the aforementioned system memory can be the entire physical memory space of an electronic device, or it can be the entire physical memory space or part of the physical memory space of a specific memory (such as SDRAM) in an electronic device. This application embodiment does not limit this.

[0103] It should be noted that the aforementioned system memory access latency can refer to the latency when accessing system memory via the bus. For example, an electronic device can release a portion of the Tag Cache cache space when the system memory access latency is high.

[0104] It should be noted that the above-mentioned number of system memory accesses refers to the number of accesses within a preset time period, such as the number of system memory accesses within 1 minute or 10 minutes. For example, when the number of system memory accesses is high, the electronic device can release a portion of the Tag Cache cache space.

[0105] In some embodiments of this application, electronic devices can monitor data transmission on the bus through internal chip hardware modules (such as Bus Monitor) to obtain the system memory access latency or access count.

[0106] For example, the Bus Monitor module monitors data transmission on the bus to obtain resource usage status information such as bus latency and memory traffic over a specific period of time.

[0107] In some embodiments of this application, the electronic device can obtain the remaining physical memory space or remaining system-level cache space of the electronic device through the operating system's system monitoring tools or application programming interfaces. For example, the electronic device can release a portion of the Tag Cache cache space when the remaining physical memory space is insufficient.

[0108] In some embodiments of this application, the electronic device can obtain access information of cached information in the target cache area through the statistical capabilities of the caching system itself, including the number of accesses, the most recent access time, and the access frequency of each cache item. For example, the electronic device can release a portion of the Tag Cache cache space when the access frequency of the Tag Cache is low.

[0109] It should be noted that the threshold values ​​in the embodiments of this application, such as the first threshold value, can be set according to actual needs, and the embodiments of this application do not limit this.

[0110] In this embodiment, by monitoring resource usage status such as bus latency, memory traffic over a specific duration, remaining physical memory space, remaining system cache space, and system cache access frequency, the size of the target cache is reset when resource usage status meets space release conditions. This allows for dynamic adjustment of MTE performance and system load, preventing insufficient Tag Cache space or wasted Tag Cache space.

[0111] In some embodiments of this application, step 201 described above can be implemented by step 201c.

[0112] Step 201c: With the MTE function of the electronic device enabled, configure the target cache area in the first storage space of the electronic device according to the size of the first storage area in the second storage space of the electronic device.

[0113] In some embodiments of this application, the electronic device can configure a target cache in a first storage space when it detects that the MTE function is enabled.

[0114] For example, an electronic device can obtain the status of the MTE function through an application programming interface, and when the MTE function is enabled, configure a Tag Cache in the system cache to store the lock information of the memory space as needed to protect the memory space.

[0115] In some embodiments of this application, the target buffer is not configured when the MTE function of the electronic device is not enabled.

[0116] In this embodiment of the application, when the MTE function is not enabled, the system-level cache will not be used to store lock information, thereby avoiding the waste of system resources.

[0117] In some embodiments of this application, after step 201 above, the storage space management method provided in this application may further include the following step 205:

[0118] Step 205: Release the target buffer while the MTE function of the electronic device is turned off.

[0119] In some embodiments of this application, the electronic device can release the entire cache space of the configured target cache area when the MTE function is detected to be off.

[0120] For example, an electronic device can release all cache space configured with Tag Cache in the system cache area after detecting that the MTE function is turned off.

[0121] It is understandable that when the MTE function is enabled, electronic devices need to protect the memory space that needs to be protected through the TAG mechanism. In this case, the lock information of the memory space needs to be cached in the buffer. When the MTE function is disabled, it means that the TAG mechanism is not needed to protect the memory space. In this case, the lock information of the memory space does not need to be cached in the buffer.

[0122] In this embodiment of the application, after disabling the MTE function, the entire target cache can be released, thereby avoiding the waste of system resources.

[0123] The following example uses DDR as the second storage space and Tag Cache in System Cache as the target cache to illustrate the storage space management method provided in this application.

[0124] For example, the storage space management method may include the following steps 21 to 25:

[0125] Step 21: During system initialization, the AP CPU sets the corresponding Tag Cache size in the Boot Code according to the size that DDR needs to protect, calls the System cache hardware interface driver for configuration, and configures the tag cache in the system cache.

[0126] Step 21: The electronic device sends the access address through the CPU.

[0127] For example, the access address contains the memory address of the target data to be accessed and the corresponding Tag Key.

[0128] Step 22: The electronic device separates the memory address and Tag Key of the target data through the split logic module of the MTE mechanism, and continues to access the data in memory. At the same time, it passes the Tag Key to the MTE check logic module and passes the Tag Lock address to the Tag Cache in the System Cache.

[0129] Step 23: The electronic device retrieves the Tag Lock from memory and caches it according to the corresponding Tag Lock address through Tag Cache.

[0130] Step 24: The MTE check logic obtains the corresponding Tag Lock from the Tag Cache, compares the Tag Key and the Tag Lock, and returns the check result to the CPU.

[0131] Step 25: The electronic device dynamically adjusts the size of the Tag Cache in the System Cache according to the system load.

[0132] In this embodiment, the System Cache is reused as the Tag Cache, eliminating the fixed-size MTE Tag Cache configured in the prior art, thereby saving chip area. Furthermore, by dynamically determining the size of the Tag Cache based on the size of the storage area to be protected, the system can be made more flexible and scalable. When storage requirements change, the system can adjust the size of the cache area accordingly to meet new performance requirements.

[0133] The above-described method embodiments, or various possible implementations of the method embodiments, can be executed individually, or, provided there are no contradictions, they can be combined with each other. The specific implementation can be determined according to actual usage requirements, and this application embodiment does not impose any restrictions on this.

[0134] The storage space management method provided in this application can be executed by a storage space management device. This application uses the execution of the storage space management method by a storage space management device as an example to illustrate the storage space management device provided in this application.

[0135] Figure 4 is a schematic diagram of the storage space management device provided in the embodiment of this application. As shown in Figure 4, the storage space management device may include a processing module 401. The processing module 401 is used to configure a target cache area in the first storage space of the electronic device. The target cache area is used to cache the lock information corresponding to the first storage area. The first storage area is a storage area in the second storage space of the electronic device that needs to be marked by the lock information. The first storage space includes any one of the following: system-level cache, level 3 cache, static random access memory (SRAM).

[0136] In some embodiments of this application, the processing module is specifically used to, after configuring a target cache in the first storage space of the electronic device according to the size of the first storage area in the second storage space of the electronic device, obtain lock information corresponding to the first storage area from the target cache when the first process accesses the first storage area;

[0137] If the lock information matches the key information of the first storage area, the first process is allowed to access the first storage area.

[0138] In some embodiments of this application, the processing module is specifically used to: determine the size of the target cache area based on the size of the first storage area; and configure the storage area in the first storage space that matches the size of the target cache area as the target cache area.

[0139] In some embodiments of this application, the processing module is further configured to adjust the size of the target cache area according to the resource usage status of the electronic device after configuring the target cache area in the first storage space of the electronic device.

[0140] In some embodiments of this application, the processing module is specifically used to release at least a portion of the cache space of the target cache area from the first storage space when the resource usage state of the electronic device meets the space release condition;

[0141] The space release conditions include at least one of the following:

[0142] The system memory access latency is greater than or equal to the first threshold;

[0143] The number of system memory accesses is greater than or equal to the second threshold;

[0144] The remaining physical memory space of the electronic device is less than or equal to the third threshold;

[0145] The remaining system-level cache space of the electronic device is less than or equal to the fourth threshold;

[0146] The access frequency of cached information in the target cache is less than or equal to the fifth threshold.

[0147] In some embodiments of this application, the processing module is specifically used to: configure a target cache area in the first storage space of the electronic device when the memory tag extension (MTE) function of the electronic device is enabled.

[0148] In some embodiments of this application, the processing module is further configured to release the target cache after configuring the target cache in the first storage space of the electronic device, while disabling the MTE function of the electronic device.

[0149] In some embodiments of this application, the processing module is further configured to: after configuring a target cache in the first storage space of the electronic device according to the size of the first storage area in the second storage space of the electronic device, when the first process accesses the first storage area, obtain lock information corresponding to the first storage area from the target cache; and allow the first process to access the first storage area if the lock information matches the key information of the first storage area.

[0150] The storage space management device provided in this application configures a target cache area in the first storage space of an electronic device. The target cache area is used to cache lock information corresponding to a first storage area, which is a storage area in the second storage space of the electronic device that needs to be marked with lock information. The first storage space includes any one of the following: system-level cache, level 3 cache, or static random access memory (SRAM). This method allows for the flexible configuration of a cache area in the first storage space of the electronic device to store lock information corresponding to that storage area, replacing a fixed-size storage space specifically designed for storing lock information in related technologies. This saves system resources occupied by a fixed-size storage area, thereby improving system performance.

[0151] The storage space management device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television set (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0152] The storage space management device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0153] The storage space management device provided in this application embodiment can implement the various processes implemented in the above method embodiments, and will not be described again here to avoid repetition.

[0154] Optionally, as shown in FIG5, this application embodiment also provides an electronic device 500, including a processor 501 and a memory 502. The memory 502 stores a program or instructions that can run on the processor 501. When the program or instructions are executed by the processor 501, they implement the various steps of the above-described storage space management method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0155] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0156] Figure 6 is a schematic diagram of the hardware structure of an electronic device that implements an embodiment of this application.

[0157] The electronic device 100 includes, but is not limited to, components such as: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, and processor 110.

[0158] Those skilled in the art will understand that the electronic device 100 may also include a power supply (such as a battery) for powering various components. The power supply may be logically connected to the processor 110 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. The electronic device structure shown in Figure 6 does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0159] The processor 110 is configured to configure a target cache area in the first storage space of the electronic device. The target cache area is used to cache lock information corresponding to the first storage area. The first storage area is a storage area in the second storage space of the electronic device that needs to be marked by lock information. The first storage space includes any one of the following: system-level cache, level 3 cache, and static random access memory (SRAM).

[0160] In some embodiments of this application, the processing module is further configured to: after configuring a target cache in the first storage space of the electronic device according to the size of the first storage area in the second storage space of the electronic device, when the first process accesses the first storage area, obtain lock information corresponding to the first storage area from the target cache; and allow the first process to access the first storage area if the lock information matches the key information of the first storage area.

[0161] In some embodiments of this application, the processing module is specifically used to: determine the size of the target cache area based on the size of the first storage area; and configure the storage area in the first storage space that matches the size of the target cache area as the target cache area.

[0162] In some embodiments of this application, the processing module is further configured to adjust the size of the target cache area according to the resource usage status of the electronic device after configuring the target cache area in the first storage space of the electronic device.

[0163] In some embodiments of this application, the processor 110 is specifically configured to release at least a portion of the cache space of the target cache area from the first storage space when the resource usage state of the electronic device meets the space release condition;

[0164] The space release conditions include at least one of the following:

[0165] The system memory access latency is greater than or equal to the first threshold;

[0166] The number of system memory accesses is greater than or equal to the second threshold;

[0167] The remaining physical memory space of the electronic device is less than or equal to the third threshold;

[0168] The remaining system-level cache space of the electronic device is less than or equal to the fourth threshold;

[0169] The access frequency of cached information in the target cache is less than or equal to the fifth threshold.

[0170] In some embodiments of this application, the processor 110 is specifically configured to: configure a target cache in the first storage space of the electronic device when the memory tag extension (MTE) function of the electronic device is enabled.

[0171] In some embodiments of this application, the processor 110 is further configured to release the target cache after configuring the target cache in the first storage space of the electronic device, while disabling the MTE function of the electronic device.

[0172] The electronic device provided in this application embodiment configures a target cache area in its first storage space. The target cache area is used to cache lock information corresponding to a first storage area, which is a storage area in the second storage space of the electronic device that needs to be marked with lock information. The first storage space includes any one of the following: system-level cache, level 3 cache, or static random access memory (SRAM). This method allows for flexible configuration of a cache area in the first storage space of the electronic device to store lock information corresponding to that storage area, replacing a fixed-size storage space specifically designed for storing lock information in related technologies. This saves system resources occupied by a fixed-size storage area, thereby improving system performance.

[0173] It should be understood that, in this embodiment, the input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042. The GPU 1041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 106 may include a display panel 1061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0174] The memory 109 can be used to store software programs and various data. The memory 109 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 109 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 109 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0175] Processor 110 may include one or more processing units; optionally, processor 110 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 110.

[0176] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described storage space management method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0177] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0178] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described storage space management method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0179] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0180] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes of the storage space management method embodiments described above, and can achieve the same technical effects. To avoid repetition, it will not be described again here.

[0181] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0182] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0183] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A storage space management method, the method comprising: Configure the target cache area in the first storage space of the electronic device; The target cache area is used to cache the lock information corresponding to the first storage area, which is the storage area in the second storage space of the electronic device that needs to be marked by the lock information. The first storage space includes any of the following: system-level cache, level 3 cache, and static random access memory (SRAM).

2. The method according to claim 1, wherein, After configuring the target cache area in the first storage space of the electronic device, the method further includes: When the first process accesses the first storage area, the lock information corresponding to the first storage area is obtained from the target cache. If the lock information matches the key information corresponding to the first storage area, the first process is allowed to access the first storage area.

3. The method according to claim 1, wherein, Configuring the target cache area in the first storage space of the electronic device includes: The target cache size is determined based on the size of the first storage area; Configure the storage area in the first storage space that matches the size of the target cache area as the target cache area.

4. The method according to claim 1, wherein, After configuring the target cache area in the first storage space of the electronic device, the method further includes: The size of the target cache is adjusted according to the resource usage status of the electronic device.

5. The method according to claim 4, wherein, Adjusting the size of the target cache area according to the resource usage status of the electronic device includes: When the resource usage state of the electronic device meets the space release condition, at least a portion of the cache space of the target cache area in the first storage space is released; The space release condition includes at least one of the following: The system memory access latency is greater than or equal to the first threshold; The number of system memory accesses is greater than or equal to the second threshold; The remaining physical memory space of the electronic device is less than or equal to the third threshold. The remaining system-level cache space of the electronic device is less than or equal to the fourth threshold; The access frequency of the target cache is less than or equal to the fifth threshold.

6. The method according to claim 1, wherein, Configuring the target cache area in the first storage space of the electronic device includes: When the Memory Tag Extension (MTE) function of the electronic device is enabled, the target cache area is configured in the first storage space of the electronic device.

7. The method according to claim 1, wherein, After configuring the target cache area in the first storage space of the electronic device, the method further includes: The target buffer is released when the MTE function of the electronic device is disabled.

8. A storage space management device, the device comprising: Processing module; The processing module is used to configure a target cache area in the first storage space of the electronic device; The target cache area is used to cache the lock information corresponding to the first storage area, and the first storage area is the storage area in the second storage space of the electronic device that needs to be marked by the lock information; The first storage space includes any of the following: system-level cache, level 3 cache, and static random access memory (SRAM).

9. The apparatus according to claim 8, wherein, The processing module is further configured to: After configuring a target cache in the first storage space of the electronic device according to the size of the first storage area in the second storage space of the electronic device, when the first process accesses the first storage area, the lock information corresponding to the first storage area is obtained from the target cache. If the lock information matches the key information of the first storage area, the first process is allowed to access the first storage area.

10. The apparatus according to claim 8, wherein, The processing module is specifically used for: The target cache size is determined based on the size of the first storage area; Configure the storage area in the first storage space that matches the size of the target cache area as the target cache area.

11. The apparatus according to claim 8, wherein, The processing module is further configured to, after configuring the target cache in the first storage space of the electronic device, adjust the size of the target cache according to the resource usage status of the electronic device.

12. The apparatus according to claim 11, wherein, The processing module is specifically used to release at least a portion of the cache space of the target cache area in the first storage space when the resource usage state of the electronic device meets the space release condition; The space release condition includes at least one of the following: The system memory access latency is greater than or equal to the first threshold; The number of system memory accesses is greater than or equal to the second threshold; The remaining physical memory space of the electronic device is less than or equal to the third threshold. The remaining system-level cache space of the electronic device is less than or equal to the fourth threshold; The access frequency of cached information in the target cache area is less than or equal to the fifth threshold.

13. The apparatus according to claim 8, wherein, The processing module is specifically used for: With the Memory Tag Extension (MTE) function of the electronic device enabled, a target cache area is configured in the first storage space of the electronic device.

14. The apparatus according to claim 8, wherein, The processing module is further configured to, after configuring the target cache in the first storage space of the electronic device, release the target cache while disabling the MTE function of the electronic device.

15. An electronic device comprising a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the storage space management method as claimed in any one of claims 1-7.

16. A readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of the memory space management method as claimed in any one of claims 1-7.

17. A computer program product stored in a storage medium, the computer program product being executed by at least one processor to implement the memory space management method as claimed in any one of claims 1 to 7.

18. A chip comprising a processor and a communication interface, the communication interface being coupled to the processor, the processor being configured to run a program or instructions to implement the memory space management method as described in any one of claims 1 to 7.

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