DSI3 slave device, and method for operating a DSI3 slave device

Abstract

The invention relates to a DSI3 slave device (120, 120') for a vehicle (100), comprising: a digital processor (122, 122'); at least one analogue circuit element (128, 128', C1, C1'); a DSI3 transceiver (124, 124') which is designed to receive a signal sent by a DSI3 master device (140), to convert the received signal into a digital signal, and to output the digital signal to the digital processor (122, 122'); and a reset-pulse decoder (126, 126') which is designed to output a reset signal to the digital processor (122, 122') in response to a reset pulse in the received signal or in the digital signal.

Description

[0001] DSI3-SLAVE DEVICE AND METHOD FOR OPERATING A DSI3-SLAVE DEVICE

[0002] The present invention relates to a DSI3 slave device and a method for operating a DSI3 slave device.

[0003] When using DSI3 slave devices, situations arise where the processor of the DSI3 slave device freezes, meaning it is trapped in an endless loop while executing stored program code. Once the processor has frozen, it is no longer able to receive and execute signals and instructions from a DSI3 master device. To reset the processor and thus end the endless loop, the power supply to the DSI3 slave device is currently interrupted. However, since the DSI3 slave device also contains analog components, such as capacitors or diodes, the capacitance of these analog components means that it takes a certain amount of time before the processor is no longer powered on, due to the limitations of these components.During the period until the processor is no longer powered and the processor reset is complete, the DSI3 slave device cannot be used properly. Since DSI3 slave devices are used, for example, in ultrasonic sensors or airbag systems in vehicles, such a long downtime of the DSI3 slave device is detrimental because the safety of the vehicle occupants is no longer guaranteed.

[0004] Against this background, one object of the present invention is to provide an improved DSI3 slave device.

[0005] According to a first aspect, a DSI3 slave device is provided for a vehicle. The DSI3 slave device comprises: a digital processor; at least one analog circuit element; a DSI3 transceiver configured to receive a signal transmitted by a DSI3 master device, convert the received signal into a digital signal, and output the digital signal to the digital processor; and a reset pulse decoder configured to output a reset signal to the digital processor in response to a reset pulse in the received or digital signal.

[0006] The DSI3 slave device has the advantage that the reset signal from the reset pulse decoder is output directly to the digital processor, thereby resetting it. The digital processor has, for example, a reset input connected to an output of the reset pulse decoder. For instance, a high voltage is constantly applied to the reset input of the digital processor. In this case, the reset signal is configured to reduce this voltage to a low level for a predetermined period. This reset signal from the reset pulse decoder allows the digital processor to be reset quickly and at any time, thus minimizing the downtime of the digital processor and, consequently, the downtime of the DSI3 slave device.

[0007] The vehicle is, for example, a passenger car or a truck.

[0008] DSI3 (Distributed System Interface 3) is a bus protocol used particularly in safety-critical applications in vehicles. DSI3 uses two lines to connect a master device to one or more slave devices. DSI3 can provide a cost-effective and robust medium-speed connection while exhibiting good electromagnetic compatibility (EMC). Advantageously, DSI3 can operate in a fail-safe and deterministic manner for safety-critical applications. Robustness can be ensured, for example, through checksums (CRC).

[0009] The master device and, in particular, the multiple slave devices can be arranged, for example, in a daisy-chain configuration, where the multiple slave devices are connected in series with the master device, or in a star configuration, where multiple slave devices are each connected to the master device.

[0010] The digital processor of the DSI3 slave device is specifically configured to implement the DSI3 slave protocol for communication with the DSI3 master device. Furthermore, the digital processor is configured to act as an interface for sensors and / or actuators. The digital processor can be configured, in particular, to read sensor data, preprocess the read data, and convert it into a DSI3 data format. The digital processor can also be configured to control actuators based on commands from the DSI3 master device. Preferably, the digital processor is also configured to perform fault detection and / or self-diagnostic functions. Preferably, the digital processor has a dedicated reset input configured to be connected to the reset pulse decoder via a reset connection.

[0011] The at least one analog circuit element can be, for example, a resistor, a capacitor, an inductor, a diode, a transistor, or an operational amplifier. Multiple analog circuit elements can also be arranged in the DSI3 slave device. These can be different analog circuit elements or multiple analog circuit elements of the same type.

[0012] The DSI3 transceiver is specifically configured to receive signals and commands from the DSI3 master device and send them to the digital processor of the DSI3 slave device. The DSI3 transceiver is further specifically configured to receive signals from the digital processor and output them to the DSI3 master device. The reset pulse decoder has a particularly simple design. This means that the reset pulse decoder does not contain and execute any complex program code or the like, thus preventing the reset pulse decoder from freezing. This is particularly advantageous because it prevents a situation in which the reset pulse decoder freezes and the digital processor cannot be reset.The reset pulse decoder is advantageously designed to detect a reset pulse and, in response, output a reset signal to the digital processor. This allows the digital processor to be reset at any time. One output of the reset pulse decoder is connected to the reset input of the digital processor via the reset connection.

[0013] According to one embodiment, the reset pulse decoder reads the digital signal output by the DSI3 transceiver and decodes a reset pulse contained therein.

[0014] The reset pulse decoder can be arranged to read the signal output by the DSI3 transceiver to the digital processor. Specifically, the reset pulse decoder is positioned to read the output signal at a node between the DSI3 transceiver and the digital processor.

[0015] This arrangement of the reset pulse decoder is particularly advantageous because the reset pulse decoder can be designed simply. Therefore, the hardware costs can be kept low in such an arrangement. Furthermore, a simple reset pulse decoder design has the advantage that it cannot freeze and can thus output the reset signal to the digital processor at any time.

[0016] According to one embodiment, the reset pulse decoder reads the signal from the DSI3-

[0017] The reset pulse decoder reads the signal output by the master device and converts it into a digital signal. The reset pulse decoder can be arranged to read the signal output by the DSI3 master device to the DSI3 transceiver. In this configuration, the reset pulse decoder is positioned to read the output signal from the DSI3 master device at a junction between the DSI3 master device and the DSI3 transceiver. According to this arrangement, the reset pulse decoder is further configured to convert the read signal from the DSI3 master device into a digital signal. The reset pulse decoder then continues to operate with the converted digital signal.

[0018] This reset pulse decoder arrangement has the advantage that the reset pulse decoder is independent of the signal output by the DSI3 transceiver. This means that the reset pulse decoder will function even if the DSI3 transceiver is defective or malfunctioning, for example, due to interference caused by the stalled processor. This ensures that the digital processor reset will still work even if the DSI3 transceiver is temporarily malfunctioning. Optionally, the reset pulse decoder can output the reset signal not only to the digital processor but also to the DSI3 transceiver.

[0019] According to one embodiment, the reset pulse decoder detects a pattern in the read or converted digital signal and outputs the reset signal to the digital processor depending on the detected pattern.

[0020] The instruction to reset the digital processor is issued by the DSI3 master device as a reset pulse. The reset pulse is preferably a pattern in the output signal. The reset pulse decoder is configured to recognize the pattern in the signal by which the DSI3 master device instructs the digital processor to be reset. If the reset pulse decoder recognizes this pattern, it outputs the reset signal to the digital processor. According to one embodiment, the pattern has n bytes in the signal, where n > 4.

[0021] The pattern that instructs the digital processor to reset comprises a predetermined number of n bytes. One specific byte, for example, the first of the n bytes, can be an instruction number that identifies the pattern as a reset instruction. Furthermore, another specific byte, for example, the nth of the n bytes, can be a checksum against which the reset instruction can be verified. The pattern instructing the digital processor to reset is present in both the signal transmitted by the DSI3 master device and in the converted digital signal.

[0022] According to one embodiment, the digital processor is configured to be reset when the reset signal is received.

[0023] When the digital processor receives the reset signal, it is reset. Specifically, the reset input of the digital processor is configured to receive this signal. "Resetting" the digital processor means that it begins executing a stored program code from the beginning. The program code stored on the digital processor can be application-specific and can be adapted to the specific application of the DSI3 slave device. The digital processor is configured to be reset upon receiving the reset signal, regardless of its current state or execution position within the stored program code.

[0024] According to one embodiment, the signal is Manchester-encoded.

[0025] A Manchester-coded signal is specifically a line code in which binary data values ​​are encoded by phase shifts of a square wave signal. Each bit is divided into two half-bit periods, with a phase reversal occurring in the middle of each bit period. A falling edge in the middle of the bit period represents a logical 1, while a rising edge represents a logical 0. This encoding ensures that the signal always contains at least one phase change per bit, thus enabling clock recovery and eliminating DC interference. The Manchester-coded signal is therefore self-synchronizing and does not require a separate clock signal.

[0026] The Manchester-coded signal can therefore be advantageously robust against interference and noise on a transmission line. Furthermore, Manchester coding offers the advantage that errors, for example in the data or during transmission, can be detected easily and quickly. In particular, the signal exhibits a Manchester-coded voltage level.

[0027] According to one embodiment, the reset signal is a digital signal.

[0028] Preferably, the reset signal is a digital signal output by the reset pulse decoder to the digital processor via a reset connection. The reset connection is an electrically conductive link between the reset pulse decoder and the digital processor, particularly the reset input of the digital processor. The reset connection can, for example, be configured to continuously apply a high voltage. In this case, the reset signal output by the reset pulse decoder is configured to reduce the voltage to a low level for a predetermined period. Alternatively, the reset connection can, for example, be configured to continuously apply a low voltage.The reset signal output by the reset pulse decoder is configured in this case to set the voltage to a high level for a predetermined period. Changing the level for a predetermined period is thus interpreted as the reset signal of the reset pulse decoder.

[0029] According to one embodiment, the digital processor, the at least one analog circuit element, and the DSI3 transceiver are designed as an application-specific integrated circuit. Designing it as an application-specific integrated circuit (ASIC) offers the advantage of increased performance and efficiency compared to designs using individual components, since the ASIC is optimized for the specific application. Therefore, the power consumption of the DSI3 slave device can also be optimized, and furthermore, the space requirements of the DSI3 slave device can be reduced by using an ASIC.

[0030] According to one embodiment, the reset pulse decoder is formed in the application-specific integrated circuit.

[0031] In addition to the digital processor, at least one analog circuit element, and the DSI3 transceiver, the reset pulse decoder can also be integrated into the application-specific integrated circuit. This further reduces the space requirements of the DSI3 slave device.

[0032] According to one embodiment, the analog circuit element, the DSI3 transceiver and the reset pulse decoder are each designed as a separate section of the application-specific integrated circuit.

[0033] A separate section in the application-specific integrated circuit is configured to operate independently of the other sections of the application-specific integrated circuit. In particular, a separate section of the application-specific integrated circuit continues to operate even if another section has crashed. Furthermore, preferably each of the separate sections, or at least the digital processor, is resettable independently of the other separate sections. According to one embodiment, the at least one analog circuit element includes a buffer capacitor of a power supply circuit of the DSI3 slave device.

[0034] The buffer capacitor in the power supply circuit of the DSI3 slave device is designed, for example, to compensate for short-term voltage dips in a power supply and thereby stabilize the power supply of the DSI3 slave device.

[0035] According to one embodiment, the DSI3 slave device is an ultrasonic sensor of the vehicle.

[0036] The ultrasonic sensor is designed to detect objects in the vehicle's vicinity. The DSI3 slave device can be configured as an element of the ultrasonic sensor or can incorporate other elements of the ultrasonic sensor, such as a diaphragm. Furthermore, the DSI3 slave device can be a component of the vehicle's airbag system. In this case, the DSI3 slave device can be configured as an actuator element or it can also include an actuator.

[0037] According to a second aspect, a method for operating a DSI3 slave device, comprising a digital processor, at least one analog circuit element, a DSI3 transceiver, and a reset pulse decoder, is provided. The method comprises the following steps:

[0038] Receiving, by the DSI3 transceiver, a signal emitted by a DSI3 master device;

[0039] Converting the received signal into a digital signal using the DSI3 transceiver;

[0040] Output, through the DSI3 transceiver, of the digital signal to the digital processor; output, through the reset pulse decoder, of a reset signal to the digital processor in response to a reset pulse decoded from the received signal or the digital signal.

[0041] This method allows the digital processor to be reset using the reset signal if it has frozen.

[0042] The embodiments and features described for the proposed device apply accordingly to the proposed method.

[0043] Other possible implementations of the invention also include combinations of features or embodiments described previously or subsequently with regard to the exemplary embodiments, even if not explicitly mentioned. In such cases, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention.

[0044] Further advantageous embodiments and aspects of the invention are the subject of the dependent claims and the exemplary embodiments of the invention described below.

[0045] The invention will now be explained in more detail with reference to preferred embodiments and the accompanying figures.

[0046] Fig. 1 shows a vehicle with ultrasonic sensors;

[0047] Fig. 2 shows a DSI3 slave device according to a first embodiment;

[0048] Fig. 3 shows a DSI3 slave device according to a second embodiment; and Fig. 4 shows a method for operating a DSI3 slave device according to an embodiment.

[0049] In the figures, identical or functionally equivalent elements have been given the same reference symbols, unless otherwise indicated.

[0050] Fig. 1 shows a schematic bird's-eye view of a vehicle 100. The vehicle 100 is located in an environment 200. Several ultrasonic sensors 110 are arranged on the vehicle 100. The ultrasonic sensors 110 are configured to detect the distance to objects located in the environment 200 and to output a corresponding sensor signal. For example, each ultrasonic sensor 110 is configured to output a sensor signal, for example, to the parking assistance system or driver assistance system of the vehicle 100, which can perform semi-autonomous or fully autonomous driving depending on the detected sensor signals. Each of the ultrasonic sensors 110 has a DSI3 slave device 120, 120' (Figs. 2, 3). In other embodiments not shown, the ultrasonic sensor 110 can be configured as a DSI3 slave device 120, 120' (Fig. 2, 3).

[0051] Fig. 2 shows a DSI3 slave device 120 according to a first embodiment. As already explained with reference to Fig. 1, in the present embodiment the DSI3 slave device 120 is an element of the ultrasonic sensor 110 (Fig. 1). The DSI3 slave device 120 according to the first embodiment comprises a digital processor 122, a DSI3 transceiver 124, and a reset pulse decoder 126. Furthermore, the DSI3 slave device 120 comprises a diode 128 and a capacitor C1. The diode 128 and the capacitor C1 are examples of analog circuit elements.

[0052] According to the first embodiment, the digital processor 122, the DSI3 transceiver 124, the reset pulse decoder 126, the diode 128, and the capacitor C1 are configured as an application-specific integrated circuit 130. In the present embodiment, the respective elements of the application-specific integrated circuit 130 are configured as separate sections of the application-specific integrated circuit 130. In this embodiment, the capacitor C1 is a buffer capacitor in a power supply circuit of the DSI3 slave device 120.

[0053] The DSI3 slave device 120 is electrically connected to a DSI3 master device 140. Specifically, the DSI3 master device 140 is electrically connected to the digital processor 120 of the DSI3 slave device 120, with the electrically conductive connection 129 being grounded (GND). Furthermore, the DSI3 master device 140 is electrically connected to the DSI3 transceiver 124 of the DSI3 slave device 120.

[0054] According to the present embodiment, the DSI3 master device 140 is configured to supply the DSI3 slave device 120 with both a signal and a voltage via a conductive connection 125. A power supply circuit for the digital processor 122 comprises a first junction K1, a diode 128, and a capacitor C1. The first junction K1 is located on the electrically conductive connection 125 between the DSI3 master device 140 and the DSI3 transceiver 124. An anode of the diode 128 is electrically connected to the DSI3 master device 140 via the first junction K1. The cathode of the diode 128 is electrically connected to the digital processor 122. One terminal of the capacitor C1 is also electrically connected to the cathode of the diode 128.The other terminal of capacitor C1 is electrically connected to the electrically conductive connection 129 of the DSI3 master device 140 with the digital processor 122, which is connected to ground GND.

[0055] In other embodiments not shown, the DSI3 master device 140 can alternatively be configured to provide signal and voltage separately, that is, on two different electrically conductive connections. The DSI3 slave device 120 is then configured to receive signal and voltage separately.

[0056] The DSI3 transceiver 124 is electrically connected to the digital processor 122. The second node K2 is located on the electrically conductive connection between the DSI3 transceiver 124 and the digital processor 122. An input of the reset pulse decoder 126 is electrically connected to the second node K2. The reset pulse decoder 126 is configured to read the signal output by the DSI3 transceiver 124 to the digital processor 122 via node K2.

[0057] An output of the reset pulse decoder 126 is electrically connected to the digital processor 122. Specifically, the output of the reset pulse decoder 126 is electrically connected to a reset input 123 of the digital processor 122. This electrically conductive connection between the reset pulse decoder 126 and the reset input 123 of the digital processor 122 can also be referred to as the reset connection 127. The reset pulse decoder 126 outputs the reset signal to the reset input 123 of the digital processor 122 via this reset connection 127.

[0058] The reset pulse decoder 126 is further configured to decode a reset pulse such as that contained in the signal emitted by the DSI3 master device 140 or in the digital signal converted by the transmit receiver 124.

[0059] The DSI3 slave device 120 according to the first embodiment is configured to execute a method for operating the DSI3 slave device 120 according to an embodiment. The method for operating the DSI3 slave device 120 is explained below with reference to method steps S1 to S4, which are shown in Fig. 4. Reference is made to Fig. 2 and Fig. 4. According to step S1, the signal transmitted by the DSI3 master device 140 is received. In the present embodiment, the DSI3 transceiver 124 is configured to receive the signal transmitted by the DSI3 master device 140. The signal transmitted by the DSI3 master device 140 is an analog signal. This transmitted analog signal includes, for example, instructions for the digital processor 122, which are present in the analog signal as predetermined amplitudes and / or shapes.In particular, the signal from the DSI3 master device 140 is a Manchester-coded signal that has a Manchester-coded voltage level.

[0060] In step S2, the received signal is converted into a digital signal. In the present embodiment, the analog signal received by the DSI3 transceiver 124 is converted into a digital signal. The DSI3 transceiver 124 thus has the functionality of an analog-to-digital converter.

[0061] According to step S3, the digital signal is output to the digital processor 122. According to the present embodiment, the DSI3 transceiver 124 outputs the converted digital signal to the digital processor 122.

[0062] According to step S4, a reset signal is output to the digital processor 122 in response to a reset pulse decoded from the digital signal. In the present embodiment, the reset pulse decoder 126 decodes a reset pulse from the read signal and, in response to the decoded reset pulse, outputs the reset signal via the reset connection 127 to the reset input 123 of the digital processor 122.

[0063] When the digital processor 122 receives the reset signal, it is reset. In the present embodiment, the digital processor 122 then begins executing the stored program code from the beginning. In alternative embodiments, resetting the digital processor 122 can also mean that it executes the program code from a predetermined point that differs from the beginning of the program code.

[0064] In the present embodiment, the pattern comprising the converted digital signal is a 4-byte pattern. The first byte contains a number for the corresponding command, i.e., a number indicating the reset command. The fourth byte of the pattern is a checksum used to verify the pattern. The second and third bytes can be assigned any value according to a predefined instruction code. It should be noted that the pattern can be any n-byte instruction code that has not been used previously and is now reserved for resetting the digital processor 122.

[0065] According to the previously described embodiment, a reset pulse decoder 126 is provided, which reads the signal from the DSI3 transceiver 124 at node K2 and, upon detecting a reset pulse, outputs a reset signal 127 to the digital processor 122. Accordingly, the digital processor 122 can be reset by the DSI3 master device 140 if it has crashed. This reset can be performed significantly faster than if the power supply on lines 125 and 129 were interrupted for the reset, since it is not necessary to wait for capacitor C1 to discharge. Furthermore, an additional reset signal line is advantageously not required.

[0066] Furthermore, the reset pulse decoder can have a particularly simple design, as it reads the signal output by the DSI3 transceiver.

[0067] This can, for example, reduce the costs of manufacturing the reset pulse decoder. Furthermore, a simpler design of the reset pulse decoder has the advantage that it is less prone to freezing and can therefore output the reset signal to the digital processor at any time. Fig. 3 shows a DSI3 slave device 120' according to a second embodiment. The DSI3 slave device 120' differs from the DSI slave device 120 (Fig. 2) in the arrangement of the second node K2' and in the design of the application-specific integrated circuit 130'. Functionally identical elements of the DSI3 slave device 120' are provided with the same reference numerals as in the DSI3 slave device 120 (Fig. 2). Only differences will be discussed below.

[0068] According to the second embodiment, the digital processor 122, the DSI3 transceiver 124, the diode 128, and the capacitor C1 are designed as an application-specific integrated circuit 130'. The reset pulse decoder 126 is not implemented in the application-specific integrated circuit 130' in the present embodiment.

[0069] In this second embodiment, node K2' is located between the DSI3 master device 140 and the DSI3 transceiver 124. In this embodiment, the reset pulse decoder 126' is configured to read the signal output by the DSI3 master device 140. The signal output by the DSI3 master device 140 is an analog signal that may include a reset pulse. The reset pulse decoder 126' is configured to decode the read signal, convert it into a digital signal, and recognize a pattern in the converted digital signal. Furthermore, depending on the recognized pattern, the reset pulse decoder 126' is configured to output a reset signal via the reset connection 127 to a reset input 123 of the digital processor 122.

[0070] The DSI3 slave device 120' according to the second embodiment is configured to execute a method for operating the DSI3 slave device 120'. The method for operating the DSI3 slave device 120' is explained below with reference to method steps S1 to S4, which are shown in Fig. 4. Reference is made below to Fig. 3 and Fig. 4. According to step S1, the signal transmitted by the DSI3 master device 140 is received. The signal transmitted by the DSI3 master device 140 is an analog signal. This transmitted analog signal includes, for example, instructions for the digital processor 122, which are present in the analog signal as predetermined amplitudes and / or shapes. The reset pulse decoder 126' is configured to read this transmitted analog signal by means of node K2'. Furthermore, the signal emitted by the DSI3 master device 140 is received by the DSI3 transceiver 124.

[0071] In step S2, the received signal is converted into a digital signal. In the present second embodiment, the analog signal read by the reset pulse decoder 126' is converted into a digital signal. The reset pulse decoder 126' thus functions as an analog-to-digital converter. Furthermore, the signal received by the DSI3 transceiver 124 is also converted into a digital signal by the DSI3 transceiver 124.

[0072] According to step S3, the digital signal is output to the digital processor 122. According to the present embodiment, the DSI3 transceiver 124 outputs the converted digital signal to the digital processor 122.

[0073] According to step S4, a reset signal is output to the digital processor 122 in response to a reset pulse decoded from the digital signal. In the present embodiment, the reset pulse decoder 126' decodes a reset pulse from the converted signal and, in response to the decoded reset pulse, outputs the reset signal to the reset input 123 of the digital processor 122 via the reset connection 127.

[0074] When the digital processor 122 receives the reset signal from the reset pulse decoder 126', the digital processor 122 is reset. Although the present invention has been described with reference to exemplary embodiments, it can be modified in many ways.

[0075] In the described embodiments, the DSI3 slave device (120, 120') is configured as an element of an ultrasonic sensor (110). However, the described DSI3 slave device (120, 120') is not limited to this. For example, the DSI3 slave device (120, 120') can also be configured as an ultrasonic sensor (110). Furthermore, the application area of ​​the described DSI3 slave device (120, 120') is not limited to ultrasonic sensors (110). The DSI3 slave device (120, 120') can, for example, also be configured as an element of an airbag system.

[0076] Although the embodiments described above each include a capacitor (C1) and a diode (128), the analog circuit elements are not limited to these. Other analog circuit elements, such as transistors, resistors, and the like, may be included.

[0077] Although two analog circuit elements are arranged in the embodiments described above, the number of circuit elements is not limited to this. In particular, a number of identical analog circuit elements can be arranged, or different analog circuit elements can be arranged, or only a single analog circuit element can be arranged.

[0078] Although the sections of the application-specific integrated circuit (130, 130') were described as separate sections in the embodiments described above, the application-specific integrated circuit (130, 130') is not limited to this. In particular, the elements of the application-specific integrated circuit (130, 130') described above can also be configured as a single section. Furthermore, different elements can also be configured as separate or single sections. Although in the embodiments described above the reset pulse decoder (126, 126') is configured to decode the received signal, the reset pulse decoder (126, 126') can also be configured to decode the received signal only when required.Furthermore, the reset pulse decoder (126, 126') can also be configured to detect a pattern and / or the reset pulse of the DSI3 master device (140) in the received signal without decoding the signal.

[0079] REFERENCE MARK LIST

[0080] 100 vehicles

[0081] 110 Ultrasonic sensor

[0082] 120, 120' DSI3 slave device

[0083] 122 Digital Processor

[0084] 123 Reset Input

[0085] 124 DSI3 transceiver

[0086] 125, 129 electrically conductive connection

[0087] 126, 126' Reset pulse decoder

[0088] 127 Reset connection

[0089] 128 Diode

[0090] 130, 130' application-specific integrated circuit

[0091] 140 DSI3 master device

[0092] 200 surroundings

[0093] C1 Capacitor

[0094] GND Ground

[0095] S1 ... S4 Process steps

Claims

PATENT CLAIMS 1. DSI3 slave device (120, 120') for a vehicle (100), comprising: a digital processor (122, 122'); at least one analog circuit element (128, 128', C1 , C1 '); a DSI3 transceiver (124, 124') configured to receive a signal transmitted by a DSI3 master device (140), convert the received signal into a digital signal and output the digital signal to the digital processor (122, 122'); and a reset pulse decoder (126, 126') configured to output a reset signal to the digital processor (122, 122') in response to a reset pulse in the received or the digital signal.

2. DSI3 slave device (120, 120') according to claim 1, characterized in that the reset pulse decoder (126) reads the digital signal output by the DSI3 transmitter receiver (124, 124').

3. DSI3 slave device (120, 120') according to claim 1 , characterized in that the reset pulse decoder (126') reads the signal output by the DSI3 master device (140) and converts it into a digital signal.

4. DSI3 slave device (120, 120') according to one of the preceding claims, characterized in that the reset pulse decoder (126, 126') detects a pattern in the read or converted digital signal and outputs the reset signal to the digital processor (122, 122') depending on the detected pattern.

5. DSI3 slave device (120, 120') according to one of the preceding claims, characterized in that the pattern has n bytes in the signal, wherein n > 4.

6. DSI3 slave device (120, 120') according to one of the preceding claims, characterized in that the digital processor (122, 122') is configured to be reset when the reset signal is received.

7. DSI3 slave device (120, 120') according to one of the preceding claims, characterized in that the signal is Manchester-encoded.

8. DSI3 slave device (120, 120') according to one of the preceding claims, characterized in that the reset signal is a digital signal.

9. DSI3 slave device (120, 120') according to one of the preceding claims, characterized in that the digital processor (122, 122'), the at least one analog circuit element (128, 128', C1 , C1 ') and the DSI3 transceiver (124, 124') are designed as an application-specific integrated circuit (130, 130').

10. DSI3 slave device (120, 120') according to claim 9, characterized in that the reset pulse decoder (126, 126') is formed in the application-specific integrated circuit (130, 130').

11. DSI3 slave device (120, 120') according to claim 9 or 10, wherein the analog circuit element (128, 128', C1 , C1 '), the DSI3 transceiver (124, 124') and the reset pulse decoder (126, 126') are each designed as a separate section of the application-specific integrated circuit (130, 130').

12. DSI3 slave device (120, 120') according to one of the preceding claims, wherein the at least one analog circuit element (128, 128', C1 , C1 ') comprises a buffer capacitor (C1 , C1 ') of a power supply circuit of the DSI3 slave device (120, 120').

13. DSI3 slave device (120, 120') according to any one of the preceding claims, wherein the DSI3 slave device (120, 120') is an ultrasonic sensor (110) of the vehicle (100).

14. Method for operating a DSI3 slave device (120, 120') comprising a digital processor (122, 122'), at least one analog circuit element (128, 128', C1, C1'), a DSI3 transceiver (124, 124') and a reset pulse decoder (126, 126'), comprising: Receiving (S1) by the DSI3 transceiver (124, 124') a signal emitted by a DSI3 master device (140); Converting (S2) the received signal into a digital signal by the DSI3 transceiver (124, 124'); Output (S3), through the DSI3 transceiver (124, 124'), of the digital signal to the digital processor (122, 122'); - Output (S4), through the reset pulse decoder (126, 126'), in response to a reset pulse decoded from the received signal or the digital signal, of a reset signal to the digital processor (122, 122').

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