Electronic computer

Abstract

An electronic computer according to the present invention comprises a control unit, a storage unit, and a plurality of arithmetic units. The storage unit stores a program including a plurality of processes, and a performance table including at least one performance index when each of the plurality of arithmetic units executes each of the plurality of processes. The control unit is configured to allocate at least one of the plurality of processes to one of the plurality of arithmetic units for each process so as to satisfy a request condition for executing the program, on the basis of the performance index included in the performance table. The plurality of arithmetic units are FPGA devices, and the performance index includes the number of times of rewriting the program in an FPGA device.

Description

electronic computer

[0001] The present invention relates to electronic computers that perform calculations electronically.

[0002] Devices such as smartphones, personal computers, and servers are made up of electronic computers. For example, a personal computer consists of a storage device that stores programs, a general-purpose processor that reads the programs from the storage device and executes calculations, and a communication means that connects the storage device and the general-purpose processor. There is a continuous demand for improved performance in these electronic computers, including higher throughput, smaller size, lower power consumption, more flexible processing, and improved user convenience. To meet these demands, computing units with various features have been developed.

[0003] For example, types of computing devices include GPUs (Graphics Processing Units) that can process video and AI at high speeds, ASICs (Application Specific Integrated Circuits) that can process only specific functions at ultra-high speeds but the processing content cannot be changed, and FPGAs (Field Programmable Gate Arrays) that are high-speed but the processing content can be changed after manufacturing.

[0004] In recent years, configurations have emerged that combine computing units with various characteristics in order to improve the overall performance of the computer. A typical configuration of a conventional electronic computer that combines multiple types of computing units is shown in Figure 23. Conventionally, such a computer is composed of a control unit 10 such as a general-purpose processor, a memory unit 20 of a storage device, multiple types of computing units (#1 to #N) such as FPGAs and CPUs (Central Processing Units), and communication means 200 that connects them.

[0005] When a program is executed in this configuration, the control unit 10 reads and executes the execution program stored in the storage unit 20. Here, the control unit 10 offloads part or all of the execution program 60 to each computing unit, thereby improving performance such as higher throughput, smaller size, lower power consumption, more efficient processing, more flexible processing, and user convenience.

[0006] R. Takano and T. Kudoh, "Flow-centric computing leveraged by photonic circuit switching for the post-moore era," 2016 Tenth IEEE / ACM International Symposium on Networks-on-Chip (NOCS), Nara, Japan, 2016

[0007] In the conventional configuration, the control unit 10 of the electronic computer is unable to know the processing capacity of each computing unit, and is therefore forced to allocate processing appropriately without considering the performance of each computing unit, making it impossible to maximize the performance of the electronic computer.

[0008] The present invention was made in consideration of the above-mentioned problems of the prior art, and has as its object to provide an electronic computer capable of improving performance such as power consumption and throughput.

[0009] In order to solve the above problem, the electronic computer of the present invention is an electronic computer having a control unit, a memory unit, and a plurality of arithmetic units, wherein the memory unit stores a program including a plurality of processes and a performance table including at least one performance index when each of the plurality of arithmetic units executes each of the plurality of processes, and the control unit is configured to assign at least one of the plurality of processes to any one of the plurality of arithmetic units for each process based on the performance index included in the performance table so as to satisfy requirements when executing the program, and the plurality of arithmetic units are FPGA devices, and the performance index includes the number of times the program is rewritten in the FPGA device.

[0010] According to the present invention, it is possible to provide an electronic computer that can improve performance such as power consumption and throughput by having the control unit of the electronic computer allocate processing to the computing units based on performance information of each computing unit.

[0011] FIG. 1 is a configuration example of a computer according to a first embodiment of the present invention. FIG. 2 is a flowchart of an execution program according to the first embodiment of the present invention. FIG. 3 is a configuration example of a performance table according to the first embodiment of the present invention. FIG. 4 is a configuration example of a computing unit according to a second embodiment of the present invention. FIG. 5 is a configuration example of a performance table according to the second embodiment of the present invention. FIG. 6 is a configuration example of a computer according to the second embodiment of the present invention. FIG. 7 is a configuration example of a computing unit according to a third embodiment of the present invention. FIG. 8 is a configuration example of a computer according to the third embodiment of the present invention. FIG. 9 is a configuration example of a computer according to a fourth embodiment of the present invention. FIG. 10 is a configuration example of a performance table according to a fifth embodiment of the present invention. FIG. 11 is a configuration example of a computer according to a sixth embodiment of the present invention. FIG. 12 is a configuration example of a performance table according to the sixth embodiment of the present invention. FIG. 13 is a flowchart of an allocation program according to the sixth embodiment of the present invention. FIG. 14 is a configuration example of a computer according to a seventh embodiment of the present invention. FIG. 15 is a configuration example of a computer according to an eighth embodiment of the present invention. Fig. 16 is an example of the configuration of a conventional computer. Fig. 17 is an example of the configuration of a computer according to an embodiment of the present invention. Fig. 18 is an example of a flowchart of an execution program according to an embodiment of the present invention. Fig. 19 is an example of the configuration of a table according to an embodiment of the present invention. Fig. 20 is an example of the configuration of an FPGA according to an embodiment of the present invention. Fig. 21 is an example of the configuration of a table according to an embodiment of the present invention. Fig. 22 is an example of the configuration of a table according to an embodiment of the present invention. Fig. 23 is an example of the configuration of a conventional computer.

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments of the present invention described below.

[0013] [First embodiment] In the first embodiment of the present invention, in addition to the execution program 60 executed by the arithmetic units (#1 to #N) (30-1 to 30-N), the storage unit 20 of the electronic computer 1 is provided with a performance table 80 that describes the performance of each arithmetic unit (#1 to #N) (30-1 to 30-N), and an allocation program that calculates to which arithmetic unit (#1 to #N) (30-1 to 30-N) each process should be allocated based on the performance table 80, thereby realizing low power consumption of the entire computer.

[0014] An example of the configuration of this embodiment is shown in Figure 1. The configuration of this embodiment differs from the conventional configuration in that the storage unit 20 of the electronic computer 1 has an allocation program 70 and a performance table 80. In this configuration, the performance table 80 describes the performance when each computing unit executes each process of the execution program 60. A feature of this embodiment is that the allocation program 70 refers to this performance table 80 and allocates the processing of the execution program 60 to each computing unit (#1 to #N) (30-1 to 30-N) according to the performance requirements desired by the user.

[0015] The operation of this embodiment will be specifically described with reference to FIG. 2. For example, in this embodiment, the execution program 60 executed by the control unit 10 includes multiple processes (process A, process B, and process C), and the processes are executed sequentially in the order of process A → process B → process C. In this configuration, it is assumed that five types of arithmetic units (#1 to #5) are available. Here, the multiple types of arithmetic units are GPUs, FPGAs, ASICs, etc.

[0016] 3, the performance table 80 lists the power consumption (W) when each process (processes A to C) of the execution program 60 is executed by the computing units (#1 to #5). Specifically, the computing unit #1 has (processes A, B, C) = (10, 20, 25), the computing unit #2 has (processes A, B, C) = (5, 50, 100), the computing unit #3 has (processes A, B, C) = (30, 5, 30), the computing unit #4 has (processes A, B, C) = (25, 30, 5), and the computing unit #5 has (processes A, B, C) = (20, 20, 20).

[0017] With this performance table 80, if it is desired to run the execution program 60 with as little power consumption as possible, the allocation program 70 can simply assign process A to arithmetic unit #2, process B to arithmetic unit #3, and process C to arithmetic unit #4. Regarding the transmission and reception of data between the arithmetic units when the execution program 60 is executed, the processing results of the arithmetic units may be transmitted and received via the control unit 10, or the processing results may be transmitted and received between the arithmetic units based on instructions from the control unit 10.

[0018] As described above, according to this embodiment, the allocation program 70 refers to the performance table 80 and allocates processes to optimize performance, thereby making it possible to realize, for example, a computer 1 with low power consumption.

[0019] In this embodiment, an example has been described in which the power consumption of each arithmetic unit is recorded in the performance table 80 as a performance index, and a low-power electronic computer 1 can be realized by referring to the performance table 80. However, the performance index of the present invention is not limited to power consumption. For example, throughput, temperature, area of ​​the arithmetic unit, variability of processing in the arithmetic unit, usability, I / O type and bit width in the arithmetic unit, etc. may also be recorded in the performance table 80 as performance indexes. By determining the arithmetic unit that will perform processing by referring to the performance table 80 in which various performance indexes are recorded, it is possible to realize an electronic computer 1 that can improve various performance indexes.

[0020] In this embodiment, an example has been shown in which all processes (processes A to C) of the execution program 60 are assigned to each computing unit by referring to the performance table 80. However, the present invention is not limited to the case in which all processes of the execution program 60 are assigned to computing units by referring to the performance table 80. For example, in the above-described embodiment, the user may decide which computing units to assign to processes A and B, and then assign a computing unit to process C by referring to the performance table 80.

[0021] Second Embodiment In a second embodiment of the present invention, each arithmetic unit of the electronic computer 1 has a communication function, and the performance table 80 can be rewritten through communication.

[0022] The features of this embodiment will be described with reference to Figures 4 and 5. Figure 4 shows an example of the configuration of the computing unit 30 in this embodiment. In this embodiment, the computing unit 30 is composed of a computing block 31 and a communication block 32. The computing block 31 is a block that performs computations, and the communication block 32 is a block that communicates with the control unit 10 and other computing units.

[0023] This embodiment is characterized in that the communication block 32 notifies the control unit 10 of the state of the calculation block 31 via communication, and the control unit 10 rewrites the performance table 80 based on that information. For example, an example of the performance table 80 used in this embodiment is shown in FIG.

[0024] The present embodiment differs from the first embodiment in that availability information indicating whether each computing unit is available or not is added. In FIG. 5 , for example, it can be seen that computing unit #2 is not available for some reason. Therefore, in this embodiment, the combination of computing units that results in the lowest power consumption is the combination in which process A is assigned to computing unit #1, process B to computing unit #3, and process C to computing unit #4.

[0025] In this embodiment, in Fig. 4, the communication block 32 monitors the status of the arithmetic units and notifies the control unit 10 of the results (availability), thereby making it possible to rewrite the performance table 80 as described above. However, the configuration of the electronic computer 1 is not limited to this. For example, as shown in Fig. 6, a configuration may be adopted in which a communication device 40 connected to a communication means 200 monitors each arithmetic unit and notifies the control unit 10 of the results.

[0026] Third Embodiment A third embodiment of the present invention is characterized in that each arithmetic unit 30 of the electronic computer 1 has a measurement block 33 that measures the performance of the arithmetic unit, and the performance table 80 is rewritten based on the results.

[0027] An example of the configuration of the computing unit 30 of this embodiment is shown in Fig. 7. In Fig. 7, each computing unit 30 includes a measurement block 33 in addition to a calculation block 31 and a communication block 32. For example, when the control unit 10 causes computing unit #1 to execute process A, the measurement block 33 of computing unit #1 measures the power consumption of computing unit #1. The measurement result of the power consumption is then notified to the control unit 10 via the communication block 32 at regular intervals.

[0028] The control unit 10 can rewrite the values ​​in the performance table 80 based on the measurement results notified from each computing unit. The control unit 10 causes the computing units to execute various processes (processes A, B, C, etc.) and notifies the computing units of the measurement results of the power consumption at that time, thereby making it possible to create a more accurate performance table 80.

[0029] In this embodiment, the measurement block 33 measures the power consumption of the arithmetic unit 30, but the performance index to be measured is not limited to power consumption. For example, other performance indexes such as throughput and temperature may be measured depending on the configuration of the performance table 80.

[0030] In this embodiment, an example has been described in which each arithmetic unit 30 has a measurement block 33, but the location of the function to be measured is not limited to such a configuration. For example, as shown in Figure 8, a configuration may be adopted in which a measurement unit 50 is connected to the communication means 200 of the electronic computer 1, and the measurement unit 50 measures the performance of each arithmetic unit.

[0031] Fourth Embodiment A fourth embodiment of the present invention is characterized in that the electronic computer 1 has a training program 90 for creating a performance table 80 .

[0032] An example of the configuration of the electronic computer 1 of this embodiment is shown in Fig. 9. The control unit 10 of this embodiment has a function of measuring the performance of each arithmetic unit when the training program 90 is started and updating the performance table 80 based on the results. The training program 90 may measure the overall performance of all arithmetic units in order, or may measure the performance of only newly added arithmetic units. Furthermore, the training program 90 may be configured to measure only specific performance indicators.

[0033] In the present embodiment, the training program 90 has been described as a software program stored in the storage unit 20, but the training program 90 is not limited to such a configuration. For example, the training program 90 may be configured as hardware.

[0034] [Fifth embodiment] The fifth embodiment of the present invention is characterized in that a plurality of performance indicators are recorded in the performance table 80 of the electronic computer 1, and processing is assigned to the arithmetic units based on one or more performance indicators.

[0035] Fig. 10 shows an example of a performance table 80 in this embodiment. In the first embodiment, as shown in Fig. 3, only performance related to power was recorded in the performance table 80. The performance table 80 of this embodiment is characterized in that it records not only power consumption but also performance indicators related to throughput, for example.

[0036] The control unit 10 can select a specific performance index from these multiple performance indexes in accordance with the required conditions specified by the user, and determine the computing unit that will perform the processing based on the selected performance index. For example, if the user specifies that the required conditions are that power consumption be as low as possible, then processing A can be assigned to computing unit #2, processing B to computing unit #3, and processing C to computing unit #4. On the other hand, if the user specifies that the required conditions are that throughput be as high as possible, then processing A can be assigned to computing unit #1, processing B to computing unit #2, and processing C to computing unit #5.

[0037] Furthermore, allocation may be performed based on a performance index that combines multiple performance indexes. For example, a configuration may be adopted in which power / throughput is calculated to create an index of the power required to process 1-bit data, and the most efficient allocation (lowest power required to process 1-bit data) is performed. In this case, process A is assigned to arithmetic unit #2, process B to arithmetic unit #3, and process C to arithmetic unit #5.

[0038] In this embodiment, no configuration example of the arithmetic unit is described, but it goes without saying that in order to incorporate a plurality of performance indexes into the performance table 80, a plurality of types of measurement blocks 33 may be required.

[0039] Sixth Embodiment In the first to fifth embodiments, the computing units of the electronic computer 1 were of different types, such as GPUs, FPGAs, and ASICs, and the processing performance for each process was also different. The sixth embodiment is characterized by a configuration in which there are multiple computing units of the same type.

[0040] FIG. 11 shows an example of the configuration of the electronic computer 1 of this embodiment. FIG. 11 shows an example of the configuration in which multiple computing units of the same type are pooled. For example, if there are M computing units #1, the respective computing units are written as computing units #1-1, #1-2, ..., #1-M. Similarly, if there are Y computing units #N, the respective computing units are written as computing units #N-1, #N-2, ..., computing unit #N-Y. Here, even if the type of computing unit is the same, different model numbers may result in different processing performance. In such a case, multiple computing units may be pooled according to the type and model number of the computing unit.

[0041] In this way, in a configuration in which multiple identical computing units are pooled and connected, computing units of the same type have the same performance. In this case, as shown in Figure 12, a performance index can be entered for each type of computing unit in the performance table 80. This has the effect of reducing the size of the performance table.

[0042] When there are multiple arithmetic units of the same type in the electronic computer 1, as in this embodiment, the operation of the allocation program 70 may differ from that of the first to fifth embodiments. Specifically, in the first to fifth embodiments, allocation was completed by selecting an arithmetic unit that satisfies the performance index specified by the user. In this embodiment, since there are multiple arithmetic units of the same type, the allocation program 70 must allocate the arithmetic units in two stages.

[0043] FIG. 13 is an example of a flowchart of an allocation program 70 according to an embodiment of the present invention. In FIG. 13, the type of arithmetic unit to be used is determined in the first stage, and which arithmetic unit to use from among multiple arithmetic units of the same type is determined in the second stage. The allocation in the first stage may be determined in the same manner as in the previous embodiments, but the allocation in the second stage is implementation-dependent and can be changed as appropriate. For example, allocation can be performed according to the number of times processing is assigned to the arithmetic unit. For example, it is conceivable to allocate in order from the least frequently used arithmetic unit, but this is not limited to this.

[0044] In this embodiment as well, it goes without saying that it is possible to execute a training program 90 for measuring the performance of the arithmetic unit to create the performance table 80, and to provide the arithmetic unit with a performance measurement function.

[0045] [Seventh Embodiment] A seventh embodiment of the present invention is characterized by a configuration in which the electronic computer 1 has a virtualized arithmetic unit. As shown in Fig. 14, even if there is one physical arithmetic unit, if multiple virtualized arithmetic units (VMs, etc.) are configured within the one arithmetic unit, it is possible to treat the single virtualized arithmetic unit in the same way as the arithmetic units in the sixth embodiment.

[0046] 14, when M virtualized computing units (Virtual Machines: VMs) are configured in the physical computing unit #1 (30-1), the computing units are described as #1-1, #1-2, ..., #1-M, as in the sixth embodiment. In this case, the multiple VMs are regarded as computing units of the same type, and are described as computing unit #1 in the performance table 80.

[0047] Eighth Embodiment In an electronic computer 1 according to an eighth embodiment of the present invention, for example, in a computing unit such as an FPGA, physically different implementations are treated as different types of computing units. Although an FPGA is a single physical computing unit, it is possible to create multiple different computing circuits within the FPGA. Therefore, as shown in FIG. 15, if two types of computing circuits, Circuit A (30-2) and Circuit B (30-3), are created within the FPGA, Circuit A (30-2) is listed as computing unit #2, and Circuit B (30-3) is listed as computing unit #3, in the performance table 80 as separate computing units. While this embodiment has been described assuming an FPGA, the same applies to ASICs and the like.

[0048] [Ninth embodiment] Fig. 16 shows a configuration example in which an FPGA is used as the arithmetic unit of the electronic computer 1 in Fig. 23. Conventionally, the control unit 10 appropriately offloads part or all of the execution program without considering the FPGA device information. FPGAs have a limited number of rewrites, and uneven allocation can cause a problem of early breakdown of some FPGA devices. In this embodiment, processing allocation is performed based on the number of FPGA rewrites listed in a table.

[0049] Fig. 17 shows an example of the configuration of an electronic computer according to an embodiment of the present invention. The configuration of this embodiment differs from the conventional configuration of Fig. 16 in that an allocation program 70 and a table 80 are stored in the storage unit 20. In this configuration, the table 80 lists the number of times each FPGA has been rewritten. A feature of this embodiment is that the allocation program 70 refers to this table 80 and allocates the processing of each program to each FPGA according to the number of times each FPGA has been rewritten.

[0050] The operation of this embodiment will be specifically described with reference to Fig. 18. For example, in this embodiment, the execution program 60 executed by the control unit 10 includes multiple processes (process A, process B, and process C), and the processes are executed sequentially in the order of process A → process B → process C. In this configuration, it is assumed that five types of FPGAs (#1 to #5) can execute process A, process B, and process C.

[0051] 19, the number of times each of FPGAs #1 to #5 has been rewritten is recorded in table 80. Specifically, the number of times each of FPGAs #1 to #5 has been rewritten is recorded as 10 times, 50 times, 30 times, 25 times, and 20 times, respectively.

[0052] When the allocation program 70 wants to allocate processes to FPGAs that are rewritten less frequently, it can refer to this table 80 and, for example, allocate process A to FPGA #1, process B to FPGA #4, and process C to FPGA #5.

[0053] FIG. 20 shows an example of the configuration of an FPGA 30 according to an embodiment of the present invention. As described in FIG. 15, the FPGA 30 is a single physical arithmetic unit, but it is possible to create multiple different circuits within the FPGA 30. In this case, circuits that are physically implemented differently within the FPGA 30 are treated as different types of arithmetic units. If multiple write blocks (34-1, 34-2) are created within the FPGA 30, each write block will be listed in the table as a separate arithmetic unit, as shown in FIG. 21.

[0054] Even when FPGAs are used as computing units, multiple performance indicators can be entered in table 80. Fig. 22 shows an example of the configuration of table 80 in which multiple performance indicators are entered. Table 80 in Fig. 22 includes not only the number of times each FPGA is rewritten, but also the power consumption when each FPGA performs process A, process B, and process C. Here, as described in the fourth embodiment, table 80 may be created or rewritten based on the results of executing processes using a training program.

[0055] The control unit 10 can select a specific performance index from these multiple performance indexes in accordance with the requirements specified by the user, and determine the arithmetic unit that will perform the processing based on the selected performance index. For example, if the user specifies that the lowest possible power consumption is desired as a requirement, the control unit 10 can assign process A to FPGA #2, process B to FPGA #3, and process C to FPGA #4. On the other hand, if the user specifies that the number of times the FPGA is rewritten is prioritized as a requirement, the control unit 10 can select and assign the FPGA with the lowest number of times the FPGA is rewritten. For example, in the example of FIG. 22, process A can be assigned to FPGA #1, process B to FPGA #2, and process C to FPGA #5. Here, as described with reference to FIGS. 20 and 21, the allocation of processes may be performed using a table that lists the number of times each write block in the FPGA is rewritten.

[0056] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration of the present invention within the scope of the present invention.

[0057] Some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0058] [Supplementary Note 1] An electronic computer comprising a control unit, a memory unit, and a plurality of arithmetic units, wherein the memory unit stores a program including a plurality of processes and a performance table including at least one performance index when each of the plurality of arithmetic units executes each of the plurality of processes, the control unit is configured to assign at least one of the plurality of processes to any one of the plurality of arithmetic units for each of the processes based on the performance index included in the performance table so as to satisfy requirements for executing the program, the plurality of arithmetic units are FPGA devices, and the performance index includes the number of times the program is rewritten in the FPGA device. [Supplementary Note 2] The electronic computer according to Supplementary Note 1, wherein the FPGA device is made up of a plurality of write blocks, and the performance table includes the number of times the program is rewritten in each of the plurality of write blocks. [Supplementary Note 3] The electronic computer according to Supplementary Note 1 or Supplementary Note 2, wherein the performance table includes a plurality of performance indexes, and the control unit selects at least one performance index from the plurality of performance indexes so as to satisfy requirements for executing the program, and assigns at least one process of the plurality of processes to any one of the plurality of arithmetic units based on the selected performance index. [Supplementary Note 4] The electronic computer according to any of Supplementary Note 1 to Supplementary Note 3, wherein the control unit is configured to create or rewrite the performance table in accordance with results when each of the plurality of arithmetic units executes each of the plurality of processes.

[0059] The present invention can be applied to electronic computers.

[0060] 1...electronic computer, 10...control unit, 20...storage unit, 30-1 to 30-N...arithmetic units, 60...execution program, 70...assignment program, 80...performance table, 200...communication means.

Claims

1. An electronic computer having a control unit, a memory unit, and a plurality of arithmetic units, wherein the memory unit stores a program including a plurality of processes and a performance table including at least one performance index when each of the plurality of arithmetic units executes each of the plurality of processes, and the control unit is configured to assign at least one of the plurality of processes to any one of the plurality of arithmetic units for each process based on the performance index included in the performance table so as to satisfy requirements when executing the program, and at least one of the plurality of arithmetic units is an FPGA device, and the performance index includes the number of times the program is rewritten in the FPGA device.

2. The electronic computer according to claim 1, wherein the FPGA device is made up of a plurality of write blocks, and the performance table includes the number of rewrites in each of the plurality of write blocks.

3. The electronic computer according to claim 1, wherein the performance table includes a plurality of performance indicators, and the control unit selects at least one performance indicator from the plurality of performance indicators so as to satisfy the requirements for executing the program, and assigns at least one of the plurality of processes to any one of the plurality of arithmetic units based on the selected performance indicator.

4. The electronic computer according to claim 1, wherein the control unit is configured to create or rewrite the performance table according to the results when each of the plurality of arithmetic units executes each of the plurality of processes.

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