Imaging element and driving method

Abstract

The present technology relates to an imaging element and a driving method that make it possible to expand a saturation margin. The present invention comprises: an ADC that performs AD conversion, the ADC including a comparator that compares an electrical signal from a pixel with a reference signal, and a counter that counts the time required for the electrical signal and the reference signal to match; and a control unit that includes a first even number of resistors, a first switch, and a first even number of second switches, with a first even number of ADCs regarded as one unit, and a second even number of comparators included in one ADC. In an auto-zero period, the control unit controls the first switch to be turned on in accordance with the number of comparators to be driven, and performs control such that a current is supplied to the comparators to be driven via the resistors connected to the first switch that is turned on. In a period other than the auto-zero period, the control unit controls the second switches to be turned on in accordance with the number of comparators to be driven, and performs control such that a current is supplied to the comparators to be driven via the second switches that are turned on. The present technology can be applied to, e.g., an imaging element.

Description

Image sensor and driving method

[0001] The present technology relates to an imaging element and a driving method, and more particularly to an imaging element and a driving method that enable an increase in the saturation margin of a comparator, for example.

[0002] For example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor has an ADC (AD Converter) for each pixel column, which converts analog pixel signals output by pixels having photoelectric conversion elements such as PDs (Photodiodes) that perform photoelectric conversion, into AD (Analog to Digital) signals.

[0003] An example of an ADC for a CMOS image sensor is a so-called single-slope ADC, which has a comparator and a counter and performs AD conversion of a pixel signal by comparing the pixel signal output by the pixel with a predetermined reference signal.

[0004] In a single-slope ADC, a comparator compares a reference signal, such as a ramp signal, whose voltage changes at a constant slope, with the pixel signal output by the pixel, and a counter counts the time required for the voltage of the reference signal to change until the levels of the reference signal and pixel signal match, thereby performing AD conversion on the pixel signal output by the pixel.

[0005] In a CMOS image sensor, correlated double sampling (CDS) is performed to find the difference between the AD conversion result of the reset level, which is the pixel signal immediately after the pixel is reset, and the AD conversion result of the signal level, which is the pixel signal corresponding to the charge including the charge accumulated in the PD of the pixel after the reset. The difference obtained as a result of CDS is output as the pixel value.

[0006] In a CMOS image sensor that uses a single-slope ADC, an auto-zero operation is performed before AD conversion to determine the operating point potential of the comparator. In the auto-zero operation, the comparator is set so that the pixel signal and the reference signal input to the comparator (the differential pair that makes up the comparator) are at the same potential, called the auto-zero potential.

[0007] Japanese Patent Application Laid-Open No. 2015-233184

[0008] It is desirable to increase the saturation margin so that the comparator can always operate in the saturation region.

[0009] The present technology has been made in view of such circumstances, and makes it possible to expand the saturation margin.

[0010] According to one aspect of the present technology, there is provided an imaging element including: a pixel having a photoelectric conversion element that performs photoelectric conversion and that outputs an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; a counter that counts a time required for the reference signal to change until the electric signal and the reference signal match based on an output signal output from the comparator; and an AD (Analog to Digital) signal of the electric signal, the image sensor including the comparator and the counter. and an ADC that performs ADC-to-Analog (Analog to Digital) conversion, wherein a first even number of the ADCs are regarded as one unit, and a second even number of the comparators are included in one ADC, and the control unit further includes the first even number of resistors, first switches connected to each of the resistors, and the first even number of second switches that are not connected to the resistors, wherein the control unit controls the first switches to be turned on in accordance with the number of the comparators to be driven during an auto-zero period, and controls so that a current is supplied to the comparator to be driven via the resistors connected to the first switches that have been turned on, and outside the auto-zero period, controls the second switches to be turned on in accordance with the number of the comparators to be driven, and controls so that a current is supplied to the comparator to be driven via the second switches that have been turned on.

[0011] According to a first aspect of the present technology, there is provided a driving method for an imaging element including: pixels each having a photoelectric conversion element that performs photoelectric conversion and that output an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; a counter that counts a time required for the reference signal to change until the electric signal and the reference signal match based on an output signal output from the comparator; and an AD (Analog to Digital) signal of the electric signal including the comparator and the counter. a control unit including the first even number of resistors, first switches connected to each of the resistors, and the first even number of second switches not connected to any of the resistors, wherein during an auto-zero period, the control unit controls which of the first switches to be turned on in accordance with the number of comparators to be driven, so that a current is supplied to the comparator to be driven via the resistors connected to the first switches that have been turned on; and outside the auto-zero period, the control unit controls which of the second switches to be turned on in accordance with the number of comparators to be driven, so that a current is supplied to the comparator to be driven via the second switches that have been turned on.

[0012] According to a second aspect of the present technology, the imaging element includes: a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; and a counter that counts, based on the output signal output by the comparator, a time required for the reference signal to change until the electric signal matches the reference signal, wherein the comparator includes a current mirror and a differential pair, and includes a switch and a resistor connected in parallel between the current mirror and a power supply line that is connected to a power supply, and the switch is turned off during an auto-zero period, and the switch is turned on outside the auto-zero period.

[0013] a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electrical signal output from the pixel with the reference signal output from the reference signal output unit; and a counter that counts a time required for the reference signal to change until the electrical signal matches the reference signal, based on the output signal output from the comparator; the comparator includes a current mirror and a differential pair, and includes a switch and a resistor connected in parallel between the current mirror and a power supply line that is connected to a power supply; and the comparator turns off the switch during an auto-zero period and turns on the switch outside the auto-zero period.

[0014] According to a third aspect of the present technology, the image sensor includes: a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; and a counter that counts a time required for the reference signal to change until the electric signal matches the reference signal, based on the output signal output by the comparator; the comparator includes a current mirror and a differential pair; and a switch and a resistor connected in parallel between the current mirror and the differential pair; the switch is turned off during an auto-zero period, and the switch is turned on outside the auto-zero period.

[0015] A third driving method according to one aspect of the present technology is a driving method including: a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; and a counter that counts a time required for the reference signal to change until the electric signal matches the reference signal, based on the output signal output by the comparator; the comparator including a current mirror and a differential pair, and including a switch and a resistor connected in parallel between the current mirror and the differential pair; and the comparator turning off the switch during an auto-zero period and turning on the switch outside the auto-zero period.

[0016] A first image sensor and a driving method according to one aspect of the present technology include pixels each having a photoelectric conversion element that performs photoelectric conversion and outputs an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; a counter that counts, based on the output signal output by the comparator, a time required for the reference signal to change until the electric signal matches the reference signal; and an ADC that includes the comparator and the counter and performs AD (Analog to Digital) conversion of the electric signal. The control unit further includes a control unit including a first even number of the ADCs as one unit, a second even number of the comparators in one ADC, the first even number of resistors, first switches connected to each of the resistors, and the first even number of second switches not connected to any of the resistors, wherein during an auto-zero period, the control unit controls which of the first switches to be turned on in accordance with the number of the comparators to be driven, and controls so that current is supplied to the comparator to be driven via the resistors connected to the first switches that have been turned on, and outside the auto-zero period, controls which of the second switches to be turned on in accordance with the number of the comparators to be driven, and controls so that current is supplied to the comparator to be driven via the second switches that have been turned on.

[0017] According to a second aspect of the present technology, there is provided an imaging device and a driving method thereof, the imaging device including: a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; and a counter that counts a time required for the reference signal to change until the electric signal matches the reference signal, based on the output signal output from the comparator. The comparator includes a current mirror and a differential pair, and a switch and a resistor connected in parallel between the current mirror and a power supply line connected to a power source. The comparator turns off the switch during an auto-zero period and turns on the switch outside the auto-zero period.

[0018] According to a third aspect of the present technology, there is provided an imaging device and a driving method thereof, the imaging device including: a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; and a counter that counts a time required for the reference signal to change until the electric signal matches the reference signal, based on the output signal output from the comparator. The comparator includes a current mirror and a differential pair, and a switch and a resistor connected in parallel between the current mirror and the differential pair, the switch being turned off during an auto-zero period and being turned on outside the auto-zero period.

[0019] The imaging device may be an independent device or an internal block constituting a single device.

[0020] 1 is a diagram illustrating a configuration example of an embodiment of a digital camera to which the present technology is applied. FIG. 1 is a diagram illustrating a configuration example of an image sensor. FIG. 2 is a diagram illustrating a configuration example of a pixel. FIG. 3 is a diagram illustrating a configuration example of an ADC. FIG. 4 is a diagram illustrating a configuration example of a comparator. FIG. 5 is a diagram illustrating a configuration example of a comparator in a first embodiment. FIG. 6 is a diagram illustrating a configuration example of a comparator in a second embodiment. FIG. 7 is a diagram illustrating a configuration example of a comparator in a third embodiment. FIG. 8 is a diagram illustrating a configuration example of a comparator in a fourth embodiment. FIG. 9 is a diagram illustrating a configuration example of a comparator in a fifth embodiment. FIG. 10 is a diagram illustrating a configuration example of a comparator in a sixth embodiment. FIG. 11 is a diagram illustrating a pattern in which two comparators operate. FIG. 12 is a diagram illustrating a pattern in which two comparators operate. FIG. 13 is a diagram illustrating a pattern in which four comparators operate. FIG. 14 is a diagram illustrating a pattern in which four comparators operate. FIG. 15 is a diagram illustrating a pattern in which six comparators operate. FIG. 16 is a diagram illustrating a pattern in which six comparators operate. FIG. 17 is a diagram illustrating a pattern in which eight comparators operate. FIG. 18 is a diagram illustrating a pattern in which eight comparators operate. FIG. 1 is a diagram for explaining a pattern in which two comparators operate. FIG. 2 is a diagram for explaining a pattern in which two comparators operate. FIG. 3 is a diagram for explaining a pattern in which four comparators operate. FIG. 4 is a diagram for explaining a pattern in which four comparators operate. FIG. 5 is a diagram for explaining a pattern in which six comparators operate. FIG. 6 is a diagram for explaining a pattern in which six comparators operate. FIG. 7 is a diagram for explaining a pattern in which eight comparators operate. FIG. 8 is a diagram for explaining a pattern in which eight comparators operate. A diagram showing an example of a schematic configuration of an endoscopic surgery system. A block diagram showing an example of the functional configuration of a camera head and a CCU. A block diagram showing an example of a schematic configuration of a vehicle control system. A diagram illustrating an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0021] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.

[0022] <One embodiment of a digital camera to which the present technology is applied>

[0023] 1 is a block diagram showing an example of the configuration of an embodiment of a digital camera to which the present technology is applied. Note that the digital camera is capable of capturing both still images and moving images.

[0024] In FIG. 1, the digital camera includes an optical system 1 , an image sensor 2 , a memory 3 , a signal processing unit 4 , an output unit 5 , and a control unit 6 .

[0025] The optical system 1 includes, for example, a zoom lens, a focus lens, an aperture, and the like (not shown), and causes external light to be incident on the image sensor 2 .

[0026] The image sensor 2 is an imaging device such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which receives incident light from the optical system 1, performs photoelectric conversion, and outputs image data corresponding to the incident light from the optical system 1.

[0027] The memory 3 temporarily stores the image data output by the image sensor 2 .

[0028] The signal processing unit 4 performs signal processing using the image data stored in the memory 3 , such as noise removal and white balance adjustment, and supplies the resulting data to the output unit 5 .

[0029] The output unit 5 outputs the image data from the signal processing unit 4. That is, the output unit 5 has a display (not shown) configured of, for example, a liquid crystal display or the like, and displays an image corresponding to the image data from the signal processing unit 4 as a so-called through image.

[0030] The output unit 5 has a driver (not shown) for driving a recording medium such as a semiconductor memory, a magnetic disk, or an optical disk, and records the image data from the signal processing unit 4 on the recording medium.

[0031] The control unit 6 controls each block that constitutes the digital camera in accordance with user operations and the like.

[0032] In the digital camera configured as above, the image sensor 2 receives incident light from the optical system 1 and outputs image data in accordance with the incident light.

[0033] The image data output by the image sensor 2 is supplied to and stored in a memory 3. The image data stored in the memory 3 is subjected to signal processing by a signal processing unit 4, and the resulting image data is supplied to and output from an output unit 5.

[0034] <Image sensor configuration example>

[0035] FIG. 2 is a block diagram showing an example of the configuration of the image sensor 2 shown in FIG.

[0036] 2, the image sensor 2 includes a pixel array 10, a control unit 20, a pixel driving unit 21, a column-parallel AD conversion unit 22, and an output unit 23.

[0037] The pixel array 10 includes M×N pixels 11 (M and N are integers equal to or greater than 1) that perform photoelectric conversion. 1,1 , 11 1,2 , ..., 11 1,N , 11 2,1 , 11 2,2 , ..., 11 2,N , ..., 11 M,1 , 11 M,2 , ..., 11 M,N and functions as an imaging unit (image sensor) that captures an image.

[0038] M×N pixels 11 1,1 From 11 M,N are arranged in a matrix (grid) of M rows and N columns on a two-dimensional plane.

[0039] N pixels 11 arranged in the row direction (horizontal direction) of the mth row (m=1, 2, . . . , M) (from the top) of the pixel array 10 m,1 From 11 m,N A pixel control line 41m extending in the row direction is connected to the pixel electrode 41c.

[0040] Also, M pixels 11 arranged in the column direction (vertical direction) in the nth column (n=1, 2, . . . , N) (from the left) 1,n From 11 M,n A VSL (Vertical Signal Line) 42n extending in the column direction is connected to the pixel electrodes 42a.

[0041] Pixel 11 m,n performs photoelectric conversion of light incident thereon (incident light). m,n outputs a pixel signal as a voltage corresponding to the charge obtained by photoelectric conversion to a VSL 42n connected to a current source 43n in accordance with control from the pixel drive unit 21 via a pixel control line 41m.

[0042] In addition, pixel 11 m,n For example, the photoelectric conversion element 100 can perform photoelectric conversion of light of a predetermined color that is incident via a color filter (not shown) such as a Bayer array.

[0043] The control unit 20 controls the pixel driving unit 21, the column parallel AD conversion unit 22 (including the auto-zero control unit 32, the reference signal output unit 33, etc.) and other necessary blocks according to predetermined logic or the like.

[0044] The pixel driving unit 21 drives the pixel 11 connected to the pixel control line 41m via the pixel control line 41m in accordance with the control of the control unit 20. m,1 From 11 m,N Control (drive)

[0045] The column-parallel AD conversion unit 22 converts the pixels 11 arranged in a row m,1 From 11 m,N and VSL421 to 42 N , and therefore pixel 11 m,n VSL42 n The pixel signal (voltage) output upward (hereinafter also referred to as a VSL signal) is supplied to a column-parallel AD conversion unit 22 .

[0046] The column-parallel AD conversion unit 22 converts the pixels 11 arranged in a row m,1 From 11 m,N From each of these, VSL421 to 42 NThe AD conversion of the VSL signal supplied via the m,1 From 11 m,N The pixel values ​​(pixel data) are supplied to the output unit 23.

[0047] Here, the column-parallel AD conversion unit 22 converts N pixels 11 arranged in one row. m,1 From 11 m,N AD conversion of all pixel signals is performed in parallel, and the N pixels 11 m,1 From 11 m,N Among these, AD conversion of pixel signals of one or more pixels (less than N pixels) can be performed in parallel.

[0048] However, in the following, for the sake of simplicity, the column-parallel AD conversion unit 22 is assumed to convert N pixels 11 arranged in one row. m,1 From 11 m,N The AD conversion of all VSL signals is performed in parallel.

[0049] The column-parallel AD conversion unit 22 converts N pixels 11 arranged in one row. m,1 From 11 m,N In order to perform AD conversion of all VSL signals in parallel, N ADCs (Analog to Digital Converters) 311 to 311 are used. N It has.

[0050] Furthermore, the column parallel AD conversion unit 22 includes an auto-zero control unit 32, a reference signal output unit 33, and a clock output unit .

[0051] The auto-zero control unit 32 controls the ADC 31 n The auto-zero pulse (auto-zero signal) which is a signal for controlling the auto-zero operation of the comparator 61n is transmitted from the ADC 311 to the ADC 31n via the auto-zero signal line 32A. N The output is supplied to the

[0052] The reference signal output unit 33 is configured by, for example, a DAC (Digital to Analog Converter), and outputs a reference signal having a period in which the voltage changes from a predetermined initial value to a predetermined final value with a constant gradient like a ramp signal from the ADC 31 to the ADC 31 via a reference signal line 33A.N The output is supplied to the

[0053] The clock output unit 34 outputs a clock of a predetermined frequency to the ADCs 311 to 313 via a clock signal line 34A. N The output is supplied to the

[0054] ADC31 n is VSL41 n and therefore ADC31 n Pixel 11 m,n VSL41 n The VSL signal (pixel signal) to be output above is supplied.

[0055] ADC31 n is pixel 11 m,n The VSL signal output from the reference signal output unit 33 is AD converted using a reference signal from the reference signal output unit 33 and a clock from the clock output unit 34, and then CDS (Correlated Double Sampling) is performed to obtain digital data as pixel values.

[0056] Here, ADC31 n is pixel 11 m,n The VSL signal of the pixel 11 is compared with the reference signal from the reference signal output unit 33. m,n By counting the time required for the voltage of the reference signal to change until the voltages of the VSL signal and the reference signal match (until the magnitude relationship between the VSL signal and the reference signal is reversed), the pixel 11 m,n Performs AD conversion of the VSL signal.

[0057] ADC31 n In this case, pixel 11 m,n The time required for the voltage of the reference signal to change until the voltages of the VSL signal and the reference signal match is counted by counting the clocks from the clock output unit 34 .

[0058] N ADCs 311 to 31 N In the pixel array 10, N pixels 11 in each of the first to Mth rows are m,1 From 11 m,NThe VSL signals are supplied sequentially, for example, starting from the first row, and AD conversion and CDS of the VSL signals are performed row by row.

[0059] The output unit 23 selects a column n from which pixel values ​​are to be read, and outputs the selected column n to the ADC 31 n From that ADC31 n Pixel 11 obtained by m,n The result of the AD conversion (and CDS) is read out as a pixel value and output to the outside (in this embodiment, memory 3 (FIG. 1)).

[0060] Here, ADC31 n In addition to AD conversion, we decided to perform CDS, but ADC31 n In the case of the digital signal processing unit 20, only AD conversion is performed, and CDS can be performed by the output unit 23. In the following, the description of CDS will be omitted as appropriate.

[0061] <Configuration Example of Pixel> FIG. 3 is a circuit diagram showing a configuration example of the pixel 11m,n in FIG.

[0062] In FIG. 3, pixel 11 m,n has a PD 51 and four NMOS (negative channel MOS) FETs (Field Effect Transistors) 52, 54, 55, and 56.

[0063] In pixel 11m,n, the drain of FET 52, the source of FET 54, and the gate of FET 55 are connected, and at the connection point, a floating diffusion (FD) (capacitor) 53 is formed to convert charge into voltage.

[0064] The PD 51 is an example of a photoelectric conversion element that performs photoelectric conversion, and performs photoelectric conversion by receiving incident light and storing an electric charge corresponding to the incident light.

[0065] The anode of the PD 51 is connected to ground (earthed), and the cathode of the PD 51 is connected to the source of the FET 52 .

[0066] The FET 52 is an FET for transferring the charge stored in the PD 51 from the PD 51 to the FD 53, and is hereinafter also referred to as a transfer transistor 52.

[0067] The source of the transfer transistor 52 is connected to the cathode of the PD 51 , and the drain of the transfer transistor 52 is connected to the source of the FET 54 via the FD 53 .

[0068] The gate of the transfer transistor 52 is connected to the pixel control line 41 m The gate of the transfer transistor 52 is connected to the pixel control line 41 m A transfer pulse TRG is supplied via

[0069] Here, the pixel driving unit 21 (FIG. 2) drives the pixel control line 41 m via pixel 11 m,n In order to drive (control) the pixel control line 41 m The control signals (voltages) supplied to the transistors 11 and 12 include a transfer pulse TRG, a reset pulse RST (to be described later), and a selection pulse SEL.

[0070] The FD 53 is a region formed at the connection point of the drain of the transfer transistor 52, the source of the FET 54, and the gate of the FET 55, and converts electric charge into voltage like a capacitor.

[0071] The FET 54 is an FET for resetting the charge (voltage (potential)) charged in the FD 53, and is hereinafter also referred to as a reset transistor 54.

[0072] The drain of the reset transistor 54 is connected to the power supply Vdd. The gate of the reset transistor 54 is connected to the pixel control line 41. m The gate of the reset transistor 54 is connected to the pixel control line 41 m A reset pulse RST is supplied via

[0073] The FET 55 is an FET for buffering the voltage of the FD 53 and is hereinafter also referred to as an amplifying transistor 55 .

[0074] The gate of the amplifier transistor 55 is connected to the FD 53, the drain of the amplifier transistor 55 is connected to the power supply Vdd, and the source of the amplifier transistor 55 is connected to the drain of the FET 56.

[0075] The FET 56 is an FET for selecting the output of the pixel signal (VSL signal) to the VSL 42 n, and will hereinafter also be referred to as the selection transistor 56 .

[0076] The source of the selection transistor 56 is VSL42 n The gate of the selection transistor 56 is connected to the pixel control line 41 m The gate of the selection transistor 56 is connected to the pixel control line 41 m A selection pulse SEL is supplied via

[0077] Here, the source of the amplifier transistor 55 is connected to the select transistor 56 and VSL 42. n via the current source 43 n , the amplifier transistor 55 and the current source 43 n Therefore, the voltage of the FD 53 is supplied to the VSL 42 via the SF. n This is the VSL signal above.

[0078] In addition, pixel 11 m,n can be configured without the select transistor 56. m,n As the configuration of (2), a shared pixel configuration can be adopted in which the FD 53 to the selection transistor 56 are shared by a plurality of PDs 51 and transfer transistors 52 .

[0079] The pixel 11 configured as above m,n The PD 51 receives light incident thereon and performs photoelectric conversion, thereby starting to store an electric charge according to the amount of incident light received. For simplicity of explanation, it is assumed here that the selection pulse SEL is at H level and the selection transistor 56 is in the on state.

[0080] When a predetermined time (exposure time) has elapsed since the PD 51 started to charge, the pixel driving unit 21 (FIG. 2) temporarily changes the transfer pulse TRG (from L (Low) level) to H (High) level.

[0081] When the transfer pulse TRG temporarily goes high, the transfer transistor 52 temporarily goes into an on state.

[0082] When the transfer transistor 52 is turned on, the charge stored in the PD 51 is transferred to and charged in the FD 53 via the transfer transistor 52 .

[0083] Before temporarily setting the transfer pulse TRG to H level, the pixel driving unit 21 temporarily sets the reset pulse RST to H level, thereby temporarily setting the reset transistor 54 to an ON state.

[0084] When the reset transistor 54 is turned on, the FD 53 is connected to the power supply Vdd via the reset transistor 54, and the charge in the FD 53 is swept out to the power supply Vdd via the reset transistor 54 and reset.

[0085] Here, as described above, the FD 53 is connected to the power supply Vdd, and the charge in the FD 53 is reset. m,n This is a reset.

[0086] After resetting the charge of the FD 53, the pixel driving unit 21 temporarily sets the transfer pulse TRG to H level as described above, which temporarily turns on the transfer transistor 52.

[0087] When the transfer transistor 52 is turned on, the charge stored in the PD 51 is transferred to and charged in the reset FD 53 via the transfer transistor 52 .

[0088] The voltage (potential) corresponding to the charge stored in the FD 53 is output as a VSL signal to the VSL 42 via the amplifier transistor 55 and the selection transistor 56. n is output above.

[0089] VSL42n ADC31 connected to n In FIG. 2, pixel 11 m,n The reset level, which is the VSL signal immediately after the reset, is converted into an AD signal.

[0090] Furthermore, ADC31 n In this case, the signal level (including the reset level and the level that becomes the pixel value) of the VSL signal (the voltage corresponding to the charge charged in the PD 51 and transferred to the FD 53) after the transfer transistor 52 is temporarily turned on is AD converted.

[0091] Then, the ADC 31n performs CDS to obtain the difference between the AD conversion result of the reset level (hereinafter also referred to as the reset level AD value) and the AD conversion result of the signal level (hereinafter also referred to as the signal level AD value) as a pixel value.

[0092] <Configuration example of ADC> FIG. 4 shows the ADC 31 in FIG. n 1 is a block diagram showing an example of the configuration of the ADC 31. n is the comparator 61 n and counter 62 n It performs single-slope AD conversion and CDS.

[0093] Comparator 61 n has two input terminals: an inverting input terminal (-) and a non-inverting input terminal (+).

[0094] Comparator 61 n The inverting input terminal (-) of the two input terminals receives a reference signal from the reference signal output unit 33 and a reference signal from the pixel 11. m,n The comparator 61 is supplied with a VSL signal (a reset level, a signal level), for example, a reference signal. n The other of the two input terminals, that is, the non-inverting input terminal (+), receives a reference signal from the reference signal output unit 33 and a reference signal from the pixel 11 m,n The other of the VSL signals, for example, VSL signal, is provided.

[0095] Comparator 61 ncompares the reference signal supplied to the inverting input terminal with the VSL signal supplied to the non-inverting input terminal, and outputs the comparison result.

[0096] That is, the comparator 61 n outputs one of H and L levels, for example, L level, when the reference signal supplied to the inverting input terminal is greater than the VSL signal supplied to the non-inverting input terminal.

[0097] Comparator 61 n When the VSL signal supplied to the non-inverting input terminal is greater than the voltage of the reference signal supplied to the inverting input terminal, the output is an H level, which is the other of the H and L levels.

[0098] In addition, the comparator 61 n The auto-zero control unit 32 outputs an auto-zero signal line 32 A The auto-zero pulse is provided via comparator 61. n In response to the auto-zero pulse from the auto-zero control unit 32, the comparator 61 n An auto-zero operation is performed to determine the auto-zero potential, which is the operating point potential of the amplifier.

[0099] Here, in the auto-zero operation, the comparator 61 n The comparator is set so that the pixel signal and the reference signal input (supplied) to the comparator 61 have the same auto-zero potential. n In this case, the comparator 61 n The two input signals currently applied to comparator 61, i.e. n The comparator 61 is configured to compare the signal currently supplied to the inverting input terminal of the comparator 61 with the signal currently supplied to the non-inverting input terminal of the comparator 61 so as to obtain a comparison result indicating that the signal currently supplied to the inverting input terminal of the comparator 61 is the same as the signal currently supplied to the non-inverting input terminal of the comparator 61. n is set.

[0100] Counter 62 n The comparator 61 n and a clock from the clock output section 34 are supplied.

[0101] Counter 62 nFor example, the reference signal output unit 33 outputs the signal to the comparator 61. n The clock output unit 34 starts counting the clock at the timing when the reference signal (voltage) supplied to the comparator 61 starts to change. n For example, when the output of the comparator 61 changes from L level to H level (or from H level to L level), that is, n When the voltages of the reference signal supplied to the inverting input terminal and the VSL signal supplied to the non-inverting input terminal become equal (when the magnitude relationship between the reference signal and the VSL signal is reversed), counting of the clock from the clock output unit 34 ends.

[0102] And counter 62 n The clock count value is input to the comparator 61. n The AD conversion result of the VSL signal supplied to the non-inverting input terminal of the DAC is output.

[0103] Here, the reference signal output unit 33 outputs, as a reference signal, for example, a RAMP signal having a slope (sloped waveform) in which the voltage decreases or increases at a constant rate from a predetermined initial value to a predetermined final value.

[0104] Counter 62 n Now, from the start of the slope, the reference signal is input to the comparator 61. n The time until the voltage changes to match the VSL signal supplied to the non-inverting input terminal of the comparator 61 is counted, and the count value obtained by counting is input to the comparator 61. n The AD conversion result of the VSL signal supplied to the non-inverting input terminal of the AK4124 is used.

[0105] ADC31 n is pixel 11 m,n to comparator 61 n The reset level as the VSL signal supplied to the non-inverting input terminal of the ADC 31 and the AD conversion result of the signal level are obtained. n performs CDS to obtain the difference between the AD conversion result of the signal level (signal level AD value) and the AD conversion result of the reset level (reset level AD value), and the difference obtained by CDS is used as a pixel value for the pixel 11. m,n The pixel value is output as

[0106] In addition, ADC31 n In the above, the CDS is performed by actually executing a calculation to obtain the difference between the signal level AD value and the reset level AD value. n This can be done by controlling the count of the clock at the

[0107] That is, counter 62 n In this case, for the reset level, for example, clocks are counted while the count value is decremented by one, and for the signal level, the count value of the clock for the reset level is set as the initial value, and the count value is counted while incrementing by one, in the opposite manner to the case of the reset level.This allows CDS to be performed to find the difference between the signal level (the AD conversion result of the signal level) and the reset level (the AD conversion result of the signal level) while performing AD conversion of the reset level and the signal level.

[0108] <Configuration Example of Comparator> FIG. 5 shows the configuration example of the comparator 61 in FIG. n 1 is a circuit diagram showing a configuration example of a comparator 61. n includes NMOS FETs 101 and 102, PMOS (positive channel MOS) FETs 103 and 104, NMOS FETs 105 and 106, switches 107 and 108, a PMOS FET 109, an NMOS FET 110, and capacitors C0, C1, C2, and C3.

[0109] The FET 101 and the FET 102 form a differential pair, with their sources connected to each other. The connection point between the sources of the FET 101 and the FET 102 is connected to the drain of the FET 105.

[0110] The gate of the FET 101 is connected to the comparator 61 via a capacitor C1. n The gate of the FET 101 is connected to the inverting input terminal of the comparator 61 via a capacitor C1, and a RAMP signal as a reference signal is supplied to the gate of the FET 102 via a capacitor C2.n The gate of the FET 102 is connected to the non-inverting input terminal of the pixel 11 via a capacitor C2. m,n The VSL signal (pixel signal) output from the

[0111] Comparator 61 n As described above, the input stage of the differential pair is made up of the FET 101 and the FET 102, and the gates of the FETs 101 and 102 serving as the input stage of the differential pair are provided with capacitors C1 and C2, respectively.

[0112] FET 103 and FET 104 form a current mirror and function as an active load for the differential pair formed by FETs 101 and 102. The gates of FET 103 and FET 104 are connected to each other, and the sources are connected to a power supply (voltage) VDD (>0). The connection point between the gates of FET 103 and FET 104 is connected to the drain of FET 103.

[0113] Of the FET 103 and FET 104 that form a current mirror, the drain of the FET 103 is connected to the drain of the FET 101, and the drain of the FET 104 is connected to the drain of the FET .

[0114] The connection point between the drains of FET 102 and FET 104 is connected to the gate of FET 109, and therefore the signal at the connection point between the drains of FET 102 and FET 104 is given to FET 109 as an input signal to FET 109.

[0115] The switches 107 and 108 are switches configured by, for example, FETs or the like, and are turned on or off in response to an auto-zero pulse supplied from the auto-zero control unit 32 .

[0116] That is, switch 107 turns on or off in response to the auto-zero pulse to connect or disconnect the gate and drain of FET 101. Switch 108 turns on or off in response to the auto-zero pulse to connect or disconnect the gate and drain of FET 102.

[0117] Here, switches 107 and 108 are turned on during the auto-zero operation. When switches 107 and 108 are turned on, capacitors C1 and C2 are charged so that the gate voltage and drain voltage of each of FET 101 and FET 102 become equal. Therefore, according to the auto-zero operation, the voltage of the DIFF_DAC signal, which is the RAMP signal supplied to the gate of FET 101 via capacitor C1, and the voltage of the DIFF_VSL signal, which is the VSL signal supplied to the gate of FET 102 via capacitor C2, become the same.

[0118] The voltages of the DIFF_DAC signal and the DIFF_VSL signal, which become equal by this auto-zero operation, are the auto-zero potential, which is the operating point potential of comparator 61n.

[0119] The drain of FET 105 is connected to the connection point between the sources of FET 101 and FET 102, which form a differential pair, as described above. The source of FET 105 is connected to the drain of FET 106, and a BIASCUT signal as a control signal is supplied to the gate of FET 105 from a circuit not shown.

[0120] The gate and source of FET 106 are connected to one end and the other end of capacitor C0, respectively. A VGCM signal as a control signal is supplied to the connection point between the gate of FET 106 and one end of capacitor C0 from a circuit not shown, and the connection point between the source of FET 106 and the other end of capacitor C0 is connected to the power supply (voltage) VSS (<VDD). FET 105 and 106, and capacitor C0 constitute a current source.

[0121] The source of FET 109 is connected to the power supply VDD, and the drain is connected to the drain of FET 110.

[0122] The gate and source of the FET 110 are connected to one end and the other end of the capacitor C3, respectively. A VBIAS signal is supplied as a control signal from a circuit (not shown) to the connection point between the gate of the FET 110 and one end of the capacitor C3, and the connection point between the source of the FET 110 and the other end of the capacitor C3 is connected to the power supply VSS. The FET 110 and the capacitor C3 form a current source.

[0123] The comparator 61 configured as above n In this case, a current i1 corresponding to the DIFF_DAC signal as the gate voltage of FET 101 flows through FET 101 (from its drain to its source), and a current i2 corresponding to the DIFF_VSL as the gate voltage of FET 102 flows through FET 102 (from its drain to its source).

[0124] A current identical to the current i1 flowing through the FET 101 flows through the FET 103 and FET 104 (from the source to the drain) that constitute a current mirror.

[0125] When the DIFF_DAC signal serving as the gate voltage of the FET 101 is greater than the DIFF_VSL signal serving as the gate voltage of the FET 102 , the current i 1 flowing through the FET 101 becomes greater than the current i 2 flowing through the FET 102 .

[0126] In this case, the same current as the current i1 flowing through FET 101 flows through FET 104, which forms a current mirror with FET 103 connected to FET 101 as the mirror source. However, the current i2 flowing through FET 102 connected to FET 104 is smaller than the current i1, so FET 102 attempts to increase the current i2, increasing the drain-source voltage.

[0127] As a result, the voltage at the connection point between the FET 102 and the FET 104 becomes H level.

[0128] On the other hand, when the DIFF_VSL signal serving as the gate voltage of the FET 102 is greater than the DIFF_DAC signal serving as the gate voltage of the FET 101, the current i2 flowing through the FET 102 becomes greater than the current i1 flowing through the FET 101.

[0129] In this case, the same current as the current i1 flowing through FET 101 flows through FET 104, which forms a current mirror with FET 103 connected to FET 101 as the mirror source. However, the current i2 flowing through FET 102 connected to FET 104 is larger than the current i1, so FET 102 tries to reduce the current i2, thereby reducing the drain-source voltage.

[0130] As a result, the voltage at the connection point between the FET 102 and the FET 104 becomes L level.

[0131] The voltage at the connection point between FET 102 and FET 104 is supplied as a differential output, which is the output of a differential amplifier composed of a differential pair and a current mirror, to the gate of FET 109, which constitutes an output amplifier that outputs an OUT signal, which is the output signal of comparator 61n.

[0132] The FET 110 outputs an OUT signal, which is the output signal of the comparator 61n, in response to the differential output supplied to its gate.

[0133] That is, when the differential output is at H level, the FET 109 is turned off and outputs an OUT signal at L level, and when the differential output is at L level, the FET 109 is turned on and outputs an OUT signal at H level.

[0134] From the above, when the voltage of the RAMP signal as a reference signal is higher than the voltage of the VSL signal, the OUT signal, which is the output signal of the comparator 61n, becomes L level. On the other hand, when the VSL signal is higher than the RAMP signal, n The output signal OUT goes to H level.

[0135] The comparator 61 configured as above n In this case, an auto-zero operation and a comparison operation are performed.

[0136] In the auto-zero operation, the switches 107 and 108 are turned on.

[0137] When the switches 107 and 108 are turned on, the gate and drain of the FET 101 are connected together, and the gate and drain of the FET 102 are connected together, so that the gate voltages of the FET 101 and FET 102 become the same.

[0138] The gate voltage of FET 101 is the DIFF_DAC signal, which is a RAMP signal supplied via capacitor C1, and the gate voltage of FET 102 is the DIFF_VSL signal, which is a VSL signal supplied via capacitor C2. In the auto-zero operation, the capacitors C1 and C2 are charged so that the DIFF_DAC signal and the DIFF_VSL signal match.

[0139] After that, in the comparator 61n, the switches 107 and 108 are turned off, and the comparator 61 n A comparison operation is started to compare the RAMP signal supplied to the VSL signal with the RAMP signal supplied to the VSL signal supply terminal 104. By turning off the switches 107 and 108, the charges stored in the capacitors C1 and C2 while the switches 107 and 108 were on are maintained.

[0140] As a result, comparator 61 n is set so that the RAMP signal as the DIFF_DAC signal and the VSL signal as the DIFF_VSL signal given to the comparator 61n match when the switches 107 and 108 are on.

[0141] The above-described comparator 61 n The operation in which the above setting is performed is the auto-zero operation.

[0142] By performing the auto-zero operation, the comparator 61 n In the auto-zero operation, the comparator 61 n Based on the fact that the RAMP signal (voltage) applied to the VSL signal matches the VSL signal (voltage), it is possible to determine whether the RAMP signal is larger than the VSL signal.

[0143] Comparator 61 shown in FIG. nIn this case, the transistor may not be able to operate in the saturation region.

[0144] When the drain voltage of a transistor is Vds, the gate voltage is Vgs, and the threshold voltage is Vth, the saturation margin of the transistor is expressed as Vds-(Vgs-Vth), and when this value is greater than 0, it is in the saturation region, and when it is less than 0, it is in the linear region. When the threshold voltage Vth becomes smaller, the saturation margin also becomes smaller, and the comparator 61 n When the output DIFF_VOUT is inverted, the FETs 101 and 102 that make up the differential pair may not be able to operate in the saturation region, and even a slight voltage drop from auto-zero may cause them to move out of the saturation region.

[0145] Comparator 61 n The transistors constituting the comparator 61 are always operable in the saturation region. n This is explained below.

[0146] 6 is a diagram showing a configuration example of a comparator to which the present technology is applied in a first embodiment. n a. The comparator 61 shown in FIG. n The same parts are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0147] Comparator 61 shown in FIG. n a is the comparator 61 shown in FIG. n 2. The difference is that resistors 201-1 to 201-3 and switches 202-1 to 202-3 are added to the above, but other points are the same.

[0148] A resistor 201-1 and a switch 202-1 connected in parallel are provided between the power supply VDD and the FET 103. A resistor 201-2 and a switch 202-2 connected in parallel are provided between the power supply VDD and the FET 104. A resistor 201-3 and a switch 202-3 connected in parallel are provided between the power supply VDD and the FET 109. The switch 202 may be formed of, for example, a FET.

[0149] Switches 202-1 to 202-3 are turned off during the auto-zero period and turned on outside the auto-zero period. During the auto-zero period, switches 202-1 to 202-3 are turned off, so current flows through resistors 201-1 to 201-3, respectively, and outside the auto-zero period, switches 202-1 to 202-3 are turned on, so current flows through switches 202-1 to 202-3, respectively.

[0150] Let Vgsp be the gate voltage of FET 103 and FET 104 that form the current mirror of comparator 61na, Vgsn be the gate voltage of FET 101 and FET 102 that form the differential pair, Vg1 be the input voltage to the differential pair during the auto-zero period, R1 be the offset application resistance during the auto-zero period, R2 be the offset application resistance outside the auto-zero period, I1 be the current value flowing through the offset application resistance, Vds1 be the drain voltage of FET 101 and FET 102 that form the differential pair during the auto-zero period, and Vds2 be the drain voltage of FET 101 and FET 102 that form the differential pair outside the auto-zero period, then the following equation holds true.

[0151] Vds1=Vgsn=(VDD-R1×I1-Vgsp)-(Vg1-Vgsn) Vds2=(VDD-R2×I1-Vgsp)-(Vg1-Vgsn) Vds2-Vds1=(R1-R2)×I1

[0152] From the above equation, it can be seen that when R1 > R2, the difference between the drain voltage Vds2 of the differential pair outside the auto-zero period and the drain voltage Vds1 of the differential pair during the auto-zero period becomes positive, and the drain voltage Vds increases. During the auto-zero period, switch 202 is turned off, so current flows through resistor 201, and outside the auto-zero period, switch 202 is turned on, so current flows through switch 202. Therefore, the offset application resistance R1 during the auto-zero period is larger than the offset application resistance R2 outside the auto-zero period, and because R1 > R2 is satisfied, the drain voltage Vds increases.

[0153] If the differential pair voltage Vds is low, when the comparator 61n inverts, if the first stage output drops even slightly from auto-zero, there is a possibility that it will go outside the saturation region and vertical streaks will occur. However, by increasing the differential pair voltage Vds, it is possible to prevent the output from going outside the saturation region and prevent vertical streaks from occurring.

[0154] Second Embodiment Fig. 7 is a diagram showing a configuration example of a comparator to which the present technology is applied in a second embodiment. n b. The comparator 61 shown in FIG. n The same parts are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0155] Comparator 61 shown in FIG. n b is the comparator 61 shown in FIG. n The difference is that FETs 221-1 to 221-3 and switches 222-1 to 222-3 are added to the comparator 61 shown in FIG. n b is the comparator 61 shown in FIG. n FETs 221-1 to 221-3 are provided in place of the resistors 201-1 to 201-3 of the circuit a.

[0156] An FET 221-1 and a switch 222-1 connected in parallel are provided between the power supply VDD and the FET 103. An FET 221-2 and a switch 222-2 connected in parallel are provided between the power supply VDD and the FET 104. An FET 221-3 and a switch 222-3 connected in parallel are provided between the power supply VDD and the FET 109. A PMOS transistor can be used for each of the FETs 221-1 to 221-3.

[0157] The source of the FET 221-1 is connected to one end of the switch 222-1 and the power supply VDD, and the drain is connected to the other end of the switch 222-1 and the source of the FET 103 that forms a current mirror.

[0158] The source of the FET 221-2 is connected to one end of the switch 222-2 and the power supply VDD, and the drain is connected to the other end of the switch 222-2 and the source of the FET 104 that forms a current mirror.

[0159] The source of the FET 221 - 3 is connected to one end of the switch 222 - 3 and the power supply VDD, and the drain is connected to the other end of the switch 222 - 3 and the source of the FET 109 .

[0160] The gate of the FET 221-1, the gate of the FET 221-2, the gate of the FET 103, the gate of the FET 104, and the gate of the FET 221-3 are connected together.

[0161] Switches 222-1 to 222-3 are each turned off during the auto-zero period and turned on outside the auto-zero period. During the auto-zero period, switches 222-1 to 222-3 are turned off, allowing current to flow through FETs 221-1 to 221-3, respectively. Outside the auto-zero period, switches 222-1 to 222-3 are turned on, allowing current to flow through switches 222-1 to 222-3, respectively.

[0162] Comparator 61 in the second embodiment n In the case of b, the comparator 61 in the first embodiment n As in a, the voltage Vds of the differential pair increases, so deviation from the saturation region can be prevented, and vertical stripes can be prevented from occurring.

[0163] 8 is a diagram showing a configuration example of a comparator to which the present technology is applied in a third embodiment. n c. The comparator 61 shown in FIG. n The same parts are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0164] Comparator 61 shown in FIG. n c is the comparator 61 shown in FIG. nThe difference is that the comparator 61 shown in FIG. 8 has the same configuration as the comparator 61 shown in FIG. 8 except that it has the additional resistors 241-1, 241-2, switches 242-1, and 242-2. n c is the comparator 61 shown in FIG. n When compared with a, the positions at which the resistors 241-1 and 241-2 and the switches 242-1 and 242-2 are provided are different.

[0165] A resistor 241-1 and a switch 242-1 connected in parallel are provided between the drain of FET 103 and the drain of FET 101, and a resistor 241-2 and a switch 242-2 connected in parallel are provided between the drain of FET 104 and the drain of FET 102.

[0166] Switches 242-1 and 242-2 are turned off during the auto-zero period and turned on outside the auto-zero period. During the auto-zero period, switches 242-1 and 242-2 are turned off, allowing current to flow through resistors 241-1 and 241-2. Outside the auto-zero period, switches 242-1 and 242-2 are turned on, allowing current to flow through switches 242-1 and 242-2.

[0167] Comparator 61 in the third embodiment n In the case of the comparator 61 in the first embodiment, n As in a, the voltage Vds of the differential pair increases, so deviation from the saturation region can be prevented, and vertical stripes can be prevented from occurring.

[0168] 9 is a diagram showing a configuration example of a comparator to which the present technology is applied in a fourth embodiment. n d. The comparator 61 shown in FIG. n The same parts are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0169] Comparator 61 shown in FIG. n d is the comparator 61 shown in FIG. nThe difference is that the comparator 61 shown in FIG. 9 has been configured with the addition of FETs 261-1, 261-2, switches 262-1, and 262-2, but is otherwise similar. n d is the comparator 61 shown in FIG. n When compared with b, the positions at which the FETs 261-1 and 261-2 and the switches 262-1 and 262-2 are provided are different.

[0170] An FET 261-1 and a switch 262-1 connected in parallel are provided between the FET 103 and the FET 101, and an FET 261-2 and a switch 262-2 connected in parallel are provided between the FET 104 and the FET 102. PMOS transistors can be used for the FET 261-1 and the FET 261-2.

[0171] The source of FET 261-1 is connected to one end of switch 262-1 and the drain of FET 103, and the drain of FET 261-1 is connected to the other end of switch 262-1 and the drain of FET 101. The source of FET 261-2 is connected to one end of switch 262-2 and the drain of FET 104, and the drain of FET 261-2 is connected to the other end of switch 262-2 and the drain of FET 102.

[0172] The gate of the FET 261-1 is connected to the drain of the FET 261-1, and the gate of the FET 261-2 is connected to the drain of the FET 261-2.

[0173] Switches 262-1 and 262-2 are turned off during the auto-zero period and turned on outside the auto-zero period. During the auto-zero period, switches 262-1 and 262-2 are turned off, allowing current to flow through FETs 261-1 and 261-2. Outside the auto-zero period, switches 262-1 and 262-2 are turned on, allowing current to flow through switches 262-2 and 262-2.

[0174] Comparator 61 in the fourth embodiment n In the case of d, the comparator 61 in the first embodiment nAs in a, the voltage Vds of the differential pair increases, so deviation from the saturation region can be prevented, and vertical stripes can be prevented from occurring.

[0175] 10 is a diagram showing a configuration example of a comparator to which the present technology is applied in a fifth embodiment. n e. The comparator 61 shown in FIG. n The same parts are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0176] Comparator 61 shown in FIG. n e is the comparator 61 shown in FIG. n The difference is that FETs 281-1, 281-2, 282-1, and 282-2 are added to the above, but other points are similar. For example, SVT transistors having a standard threshold voltage can be used for FETs 281-1 and 281-2, and LVT transistors having a low threshold voltage can be used for FETs 282-1 and 282-2.

[0177] Between the FET 103 and the FET 101, there are provided FETs 281-1 and 282-1 connected in parallel, and between the FET 104 and the FET 102, there are provided FETs 281-2 and 282-2 connected in parallel.

[0178] The drain of the FET 281-1 is connected to the drain of the FET 282-2 and the drain of the FET 103, and the source of the FET 281-1 is connected to the source of the FET 282-2 and the drain of the FET 101.

[0179] The drain of the FET 281-2 is connected to the drain of the FET 282-2 and the drain of the FET 104, and the source of the FET 281-2 is connected to the source of the FET 282-2 and the drain of the FET 102.

[0180] The gates of FET 281-1 and FET 281-2 are connected to signal lines from an on / off control unit (not shown). FET 281-1 and FET 281-2, which are SVT transistors, are turned on during the auto-zero period or are always on.

[0181] The gates of FET 282-1 and FET 282-2 are connected to signal lines from an on / off control unit (not shown). FET 282-1 and FET 282-2, which are LVT transistors, are turned off during the auto-zero period and turned on outside the auto-zero period.

[0182] During the auto-zero period, FET 281-1 is turned on and FET 282-2 is turned off, causing current to flow through FET 281-1. Outside the auto-zero period, FET 281-1 and FET 282-2 are turned on, causing current to flow through FET 282-2 and FET 282-2, respectively, or FET 281-1 is turned off and FET 282-2 is turned on, causing current to flow through FET 281-2.

[0183] Comparator 61 in the fifth embodiment n In the case of the comparator 61 in the first embodiment, n As in a, the voltage Vds of the differential pair increases, so deviation from the saturation region can be prevented, and vertical stripes can be prevented from occurring.

[0184] 11 is a diagram showing a configuration example of a comparator to which the present technology is applied in a sixth embodiment. n f. The comparator 61 shown in FIG. n The same parts are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0185] Comparator 61 in the sixth embodiment n f is one ADC31 n Two comparators 61 inside n Contains four ADC31 n is treated as one unit, and ADC31 is treated as one unitn A saturation margin control unit 300 for controlling the saturation margin is provided in the cascade circuit.

[0186] ADC31 n The comparator 61 n -1 and comparator 61 n -2 is included, ADC31 n+1 The comparator 61 n+1 -1 and comparator 61 n+1 -2 is included, ADC31 n+2 The comparator 61 n+2 -1 and comparator 61 n+2 -2 is included, ADC31 n+3 The comparator 61 n+3 -1 and comparator 61 n+3 -2 is included.

[0187] Each comparator 61 n is the value of each comparator 61 shown in FIG. n Each comparator 61 has a similar configuration. n is connected to a voltage line 310. The voltage line 310 is connected to a saturation margin control unit 300. The saturation margin control unit 300 includes resistors 301-1 to 301-4 and switches 302-1 to 302-8. In FIG. 11, an example is shown in which each of the switches 302-1 to 302-8 is configured by a PMOS transistor.

[0188] Resistors 301-1, 301-2, 301-3, and 301-4 have the same resistance value R.

[0189] The resistor 301-1 and the switch 302-1 are connected in series, the other end of the resistor 301-1 is connected to a voltage line 303, and the other end of the switch 302-1 is connected to a power supply VDD. The voltage line 303 is connected to a voltage line 310, and the voltage lines 303 and 310 are at the same voltage.

[0190] Resistor 301-2 and switch 302-2 are connected in series, the other end of resistor 301-2 is connected to voltage line 303, and the other end of switch 302-2 is connected to power supply VDD. Resistor 301-3 and switch 302-3 are connected in series, the other end of resistor 301-1 is connected to voltage line 303, and the other end of switch 302-3 is connected to power supply VDD. Resistor 301-4 and switch 302-4 are connected in series, the other end of resistor 301-4 is connected to voltage line 303, and the other end of switch 302-4 is connected to power supply VDD.

[0191] One end of switch 302-5 is connected to voltage line 303, and the other end is connected to power supply VDD. One end of switch 302-6 is connected to voltage line 303, and the other end is connected to power supply VDD. One end of switch 302-7 is connected to voltage line 303, and the other end is connected to power supply VDD. One end of switch 302-8 is connected to voltage line 303, and the other end is connected to power supply VDD.

[0192] Four ADC31s n is set as one unit, and a horizontal connection switch 311 is provided at the division position of each unit. The horizontal connection switch 311 and the horizontal connection switch 311+1 are provided on the voltage line 310. The horizontal connection switch 311 is turned on during the auto-zero period, and is provided to average all the ADCs 31.

[0193] By providing a horizontal connection switch 311 and turning it on during the auto-zero period, in other words, by keeping all ADCs 31 connected during the auto-zero period, it is possible to reduce mismatches due to variations in the ADCs 31 (such as the comparators 61 included in the ADCs 31).

[0194] The horizontal connection switch 311 is turned off outside the auto-zero period. By turning off the horizontal connection switch 311 outside the auto-zero period, the ADC 31 for each unit is disconnected, and the occurrence of streaking can be suppressed.

[0195] 12 to 19, the eight comparators 61 included in one unit nThe control logic based on the operation pattern of the two comparators 61 will now be explained. n The operation pattern in which the four comparators 61 operate n The operation pattern in which six comparators 61 operate. n and eight comparators 61 n There is a pattern of operation that works.

[0196] The operation pattern is switched when the resolution is changed, for example. For example, at low resolution, two comparators 61 n At high resolution, eight comparators 61 are used. n The operation pattern is applied.

[0197] <Operation Pattern in Which Two Comparators Operate> FIG. 12 shows an operation pattern in which two comparators 61 operate during the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and ADC31 n+2 Comparator 61 included in n+2 Two comparators 61 with -1 n operates, and the other comparator 61 n In the figure, the comparator 61 shown with diagonal lines is in the standby state. n indicates that the device is in standby mode.

[0198] Two comparators 61 n When the saturation margin control unit 300 operates, one switch 302 in the saturation margin control unit 300 is turned on, and the comparator 61 n 12, the switch 302-4 is turned on, and the other switches 302-1 to 302-3 and 301-5 to 301-8 are turned off.

[0199] When the switch 302-4 is turned on, the comparator 61 n-1 and comparator 61 n+2 12, a case where the switch 302-4 is turned on has been described as an example, but it is sufficient if any one of the switches 302-1 to 302-4 is turned on.

[0200] In an operating pattern in which two comparators 61n operate, the voltage drop can be expressed as follows: 2×I×R+Vds,sw=2IR+Vds,sw In this formula, I represents the current flowing through one comparator 61n, and Vds,sw represents the drain-source voltage of the switch 302. R represents the resistance value of the resistor 301. Resistor 301-1 = Resistor 301-2 = Resistor 301-3 = Resistor 301-4 = R.

[0201] Comparator 61 n -1 and comparator 61 n+2 The current flowing through each of the comparators 61 is the current I. n -1 and comparator 61 n+2 The currents flowing through the terminals -1 and -2 are controlled to be the same.

[0202] This is an operating pattern for operating two comparators 61n, and during the auto-zero period, switches 302-5 to 302-8, which are switches that short-circuit the power supply (hereinafter, appropriately referred to as power supply short-circuit control switches 302), are turned off, and one of switches 302-1 to 302-4, which are switches that control the connection of the resistor (hereinafter, appropriately referred to as resistor control switch 302), is turned on, so that the current becomes a path that flows through resistor 301, and a voltage drop can be created.

[0203] FIG. 13 shows the two comparators 61 outside the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and ADC31 n+2 Comparator 61 included in n+2 Two comparators 61 with -1 noperates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0204] Two comparators 61 n When the auto-zero period is not in operation, one power supply short control switch 302 in the saturation margin control unit 300 is turned on, and the comparator 61 n 13, the switch 302-5 is turned on, and the other switches 302-1 to 302-4 and 302-6 to 302-8 are turned off.

[0205] When the switch 302-5 is turned on, the comparator 61 n -1 and comparator 61 n+2 13, the case where the switch 302-5 is turned on has been described as an example, but it is sufficient if any one of the power supply short control switches 302 from the switches 302-5 to 302-8 is turned on.

[0206] This is an operating pattern in which two comparators 61n operate, and outside the auto-zero period, the voltage drop is Vds,sw. Vds,sw is the drain-source voltage of the switch 302, and it can be seen that the voltage drops by that amount.

[0207] This is an operating pattern in which two comparators 61n are operated, and when it is outside the auto-zero period, any one of the switches 302-5 to 302-8, which are power supply short control switches 302, is turned on, and the switches 302-1 to 302-4, which are resistance control switches 302, are turned off, so that the current flows through switch 302, and a voltage drop can be created by the amount that passes through switch 302.

[0208] During the auto-zero period, the drain potential Vpch of FET 103 and FET 104 (FIG. 5) that form the current mirror of comparator 61n is VDD-Vds,sw-IR, and the drain voltage and gate voltage of FET 101 and FET 102 that form the differential pair are the same, Vpch-Vds,pch.

[0209] Outside the auto-zero period, the drain potential Vpch of FET 103 and FET 104 (FIG. 5) that form the current mirror of comparator 61n becomes VDD-Vds,sw, and the drain potential of FET 101 and FET 102 that form the differential pair can be increased by IR. Outside the auto-zero period, switches 107 and 108 (FIG. 5) are off, so the gate potential does not change and it is possible to increase the saturation margin (Vds-Vgs) by IR.

[0210] By applying the sixth embodiment, even in the case of an operation pattern in which two comparators 61n are operating, deviation from the saturation region can be prevented, and vertical streaks can be prevented from occurring.

[0211] <Operation Pattern in Which Four Comparators Operate> FIG. 14 shows the operation pattern of the four comparators 61 during the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -2 four comparators 61 n operates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0212] Four comparators 61 n When the saturation margin control unit 300 operates, two resistor control switches 302 in the saturation margin control unit 300 are turned on, and the comparator 61 n14, the switches 302-3 and 302-4 are turned on, and the other switches 302-1, 302-2, 302-5 to 302-8 are turned off.

[0213] When the switches 302-2 and 302-4 are turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+2 -1, comparator 61 n+2 14, a case where the switches 302-3 and 302-4 are turned on has been described as an example, but it is sufficient if any two of the switches 302-1 to 302-4 are turned on.

[0214] In an operation pattern in which four comparators 61 operate, the voltage drop can be expressed as follows: 2×I×R+Vds,sw=2IR+Vds,sw The voltage drop is the same value as in the operation pattern in which two comparators 61 operate.

[0215] Comparator 61 n -1, comparator 61 n -2, comparator 61 n+2 -1, comparator 61 n+2 The current flowing through each of the comparators 61 is the current I. n -1, comparator 61 n -2, comparator 61 n+2 -1, comparator 61 n+2 The current flowing through -2 is controlled to be the same.

[0216] This is an operating pattern in which four comparators 61n are operated, and during the auto-zero period, the power supply short control switch 302 is turned off and any two of the switches 302-1 to 302-4, which are the resistance control switches 302, are turned on, so that the current flows through the resistor 301, creating a voltage drop.

[0217] FIG. 15 shows the four comparators 61 outside the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2, ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -2 four comparators 61 n operates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0218] Four comparators 61 n When the saturation margin control unit 300 operates, the two power supply short control switches 302 in the saturation margin control unit 300 are turned on, and the comparator 61 n 15, the switches 302-5 and 302-6 are turned on, and the other switches 302-1 to 302-4, 302-7, and 302-8 are turned off.

[0219] When the switches 302-5 and 302-6 are turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+2 -1, and comparator 61 n+2 15, an example has been described in which the switches 302-5 and 302-6 are turned on, but it is sufficient if any two of the power supply short control switches 302 from the switches 302-5 to 302-8 are turned on.

[0220] In this operating pattern, four comparators 61 operate, and outside the auto-zero period, the voltage drop is Vds,sw. Vds,sw is the drain-source voltage of switch 302, and it can be seen that the voltage drops by that amount.

[0221] This is an operating pattern for operating four comparators 61n, and when it is outside the auto-zero period, any two of the switches 302-5 to 302-8, which are power supply short control switches 302, are turned on, and the switches 302-1 to 302-4, which are resistance control switches 302, are turned off, so that the current flows through the switches 302, and a voltage drop can be created by the amount that passes through the switches 302.

[0222] In the case of an operation pattern in which four comparators 61n are operating, it is possible to expand the saturation margin (Vds-Vgs) by the amount of IR, just as in the case of an operation pattern in which two comparators 61n are operating.

[0223] By applying the sixth embodiment, even in the case of an operation pattern in which four comparators 61n are operating, deviation from the saturation region can be prevented, and vertical streaks can be prevented from occurring.

[0224] <Operation Pattern in Which Six Comparators Operate> FIG. 16 shows the operation pattern of the six comparators 61 during the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+1 Comparator 61 included in n+1 -1, ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -2, and ADC31 n+3 Comparator 61 included in n+3 -1 six comparators 61 n operates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0225] Six comparators 61 n When the saturation margin control unit 300 operates, the three resistor control switches 302 in the saturation margin control unit 300 are turned on, and the comparator 61n 16, the switches 302-2, 302-3, and 302-4 are turned on, and the other switches 302-1, 302-5 to 302-8 are turned off.

[0226] When the switches 302-2 to 302-4 are turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2 -1, comparator 61 n+2 -2, and comparator 61 n+3 16, an example in which the switches 302-2 to 302-4 are turned on has been described, but it is sufficient if any three of the switches 302-1 to 302-4 are turned on.

[0227] In an operation pattern in which six comparators 61 operate, the voltage drop can be expressed as follows: 2×I×R+Vds,sw=2IR+Vds,sw The voltage drop is the same value as in the operation pattern in which two comparators 61 operate.

[0228] Comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2 -1, comparator 61 n+2 -2, and comparator 61 n+3 The current flowing through each of the comparators 61 is the current I. n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2 -1, comparator 61 n+2 -2, and comparator 61 n+3 The current flowing through -1 is controlled to be the same.

[0229] This is an operating pattern in which six comparators 61n are operated, and during the auto-zero period, the power supply short control switch 302 is turned off and any three of the switches 302-1 to 302-4, which are the resistance control switches 302, are turned on, so that the current flows through the resistor 301, creating a voltage drop.

[0230] FIG. 17 shows the six comparators 61 outside the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+1 Comparator 61 included in n+1 -1, ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -2, and ADC31 n+3 Comparator 61 included in n+3 -1 six comparators 61 n operates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0231] Six comparators 61 n When the auto-zero period is not in operation, the three power supply short control switches 302 in the saturation margin control unit 300 are turned on, and the six comparators 61 are outputted via the power supply short control switches 302 that are turned on. n 17, the switches 302-5 to 302-7 are turned on, and the other switches 302-1 to 302-4 and 302-8 are turned off.

[0232] When the switches 302-5 to 302-7 are turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2-1, comparator 61 n+2 -2, and comparator 61 n+3 17, an example has been described in which the switches 302-5 to 302-7 are turned on, but it is sufficient if any three of the power supply short control switches 302 among the switches 302-5 to 302-8 are turned on.

[0233] In an operating pattern in which six comparators 61n are operating, the voltage drop is Vds,sw. Vds,sw is the drain-source voltage of the switch 302, and it can be seen that the voltage drops by that amount.

[0234] This is an operating pattern for operating six comparators 61n, and when it is outside the auto-zero period, any three of the switches 302-5 to 302-8, which are power supply short control switches 302, are turned on, and the switches 302-1 to 302-4, which are resistance control switches 302, are turned off, so that the current flows through the switches 302, and a voltage drop can be created by the amount that passes through the switches 302.

[0235] In the case of an operation pattern in which six comparators 61n are operating, it is possible to expand the saturation margin (Vds-Vgs) by the amount of IR, just as in the case of an operation pattern in which two comparators 61n are operating.

[0236] By applying the sixth embodiment, even in the case of an operation pattern in which six comparators 61n are operating, deviation from the saturation region can be prevented, and vertical streaks can be prevented from occurring.

[0237] <Operation Pattern in Which Eight Comparators Operate> FIG. 18 shows the operation pattern of the eight comparators 61 during the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+1 Comparator 61 included in n+1-1 and comparator 61 n+1 -2, ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -1, and ADC31 n+3 Comparator 61 included in n+3 -1 and comparator 61 n+3 -2 eight comparators 61 n operates, and the comparator 61 in the standby state n indicates a non-existent state.

[0238] 8 comparators 61 n When the resistor control circuit 302 is activated, all four resistor control switches 302 in the saturation margin control section 300 are turned on, and the resistors 301 are connected to the comparator 61. n 18, the switches 302-1 to 302-4 that are the resistance control switches 302 are turned on, and the switches 302-5 to 302-8 that are the power supply short control switches 302 are turned off.

[0239] When the switches 302-1 to 302-4 are turned on, the comparators 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+1 -2, comparator 61 n+2 -1, comparator 61 n+2 -2, comparator 61 n+3 -1, and comparator 61 n+3 -2 are supplied with current.

[0240] In an operation pattern in which eight comparators 61 operate, the voltage drop can be expressed as follows: 2×I×R+Vds,sw=2IR+Vds,sw The voltage drop is the same value as in the operation pattern in which two comparators 61 operate.

[0241] Comparator 61 n -1, comparator 61 n-2, comparator 61 n+1 -1, comparator 61 n+1 -2, comparator 61 n+2 -1, comparator 61 n+2 -2, comparator 61 n+3 -1, and comparator 61 n+3 The current flowing through each of the comparators 61 is the current I. n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2 -1, comparator 61 n+2 -1, and comparator 61 n+3 The current flowing through -1 is controlled to be the same.

[0242] This is an operating pattern in which eight comparators 61n are operated, and during the auto-zero period, the power supply short control switch 302 is turned off and the resistance control switch 302 is turned on, so that the current flows through the resistor 301, creating a voltage drop.

[0243] FIG. 19 shows the eight comparators 61 outside the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+1 Comparator 61 included in n+1 -1 and comparator 61 n+1 -2, ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -2, and ADC31 n+3 Comparator 61 included in n+3 -1 and comparator 61 n+3 -2 eight comparators 61 n is working.

[0244] 8 comparators 61 nWhen the saturation margin control unit 300 operates, all four power supply short control switches 302 in the saturation margin control unit 300 are turned on, and the eight comparators 61 are turned on via the power supply short control switches 302 that are turned on. n 19, the switches 302-5 to 302-8 are turned on, and the switches 302-1 to 302-4, which are the resistance control switches 302, are turned off.

[0245] When the switches 302-5 to 302-8 are turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+1 -2, comparator 61 n+2 -1, comparator 61 n+2 -2, comparator 61 n+3 -1, and comparator 61 n+3 -2, and a current flows through them.

[0246] This is an operating pattern in which eight comparators 61n operate, and outside the auto-zero period, the voltage drop is Vds,sw. Vds,sw is the drain-source voltage of the switch 302, and it can be seen that the voltage drops by that amount.

[0247] This is an operating pattern for operating eight comparators 61n, and when it is outside the auto-zero period, all of the switches 302-5 to 302-8 that are power supply short control switches 302 are turned on, and all of the switches 302-1 to 302-4 that are resistance control switches 302 are turned off, so that the current flows through the switches 302, and a voltage drop can be created that is equal to the amount that passes through the switches 302.

[0248] In the case of an operation pattern in which eight comparators 61n are operating, it is possible to expand the saturation margin (Vds-Vgs) by the amount of IR, just as in the case of an operation pattern in which two comparators 61n are operating.

[0249] By applying the sixth embodiment, even in the case of an operation pattern in which eight comparators 61n are operating, deviation from the saturation region can be prevented, and vertical streaks can be prevented from occurring.

[0250] In the sixth embodiment, too, if the drain voltage of FET 101 and FET 102 that form a differential pair during the auto-zero period is Vds1 and the drain voltage of FET 101 and FET 102 that form a differential pair outside the auto-zero period is Vds2, the following equation holds true:

[0251] Vds1=(VDD-IR-Vds,sw-Vgsp)-(Vg1-Vgsn) Vds2=(VDD-Vds,sw-Vgsp)-(Vg1-Vgsn) Vds2-Vds1=IR

[0252] It can be seen that the voltage difference between the differential pair during the auto-zero period and outside the auto-zero period is IR. n f, the comparator 61 in the first embodiment n As in a, the voltage Vds of the differential pair increases, so deviation from the saturation region can be prevented, and vertical stripes can be prevented from occurring.

[0253] 20 is a diagram showing a configuration example of a comparator to which the present technology is applied in a seventh embodiment. n g. The comparator 61 shown in FIG. n , and the comparator 61 shown in FIG. n The same parts as those in f are given the same reference numerals, and the description thereof will be omitted as appropriate.

[0254] Comparator 61 in the seventh embodiment n g is the comparator 61 in the sixth embodiment. n It has basically the same configuration as f, and has one ADC31 n Two comparators 61 inside n Contains four ADC31 n is treated as one unit, and ADC31 is treated as one unit nA saturation margin control unit 400 for controlling the saturation margin is provided in the cascade circuit.

[0255] Comparator 61 in the seventh embodiment n g is the comparator 61 in the sixth embodiment. n Compared to FIG. 11, the internal configuration of the saturation margin control unit 400 is different from that of the saturation margin control unit 300 (FIG. 11).

[0256] ADC31 n The comparator 61 n -1 and comparator 61 n -2 is included, ADC31 n+1 The comparator 61 n+1 -1 and comparator 61 n+1 -2 is included, ADC31 n+2 The comparator 61 n+2 -1 and comparator 61 n+2 -2 is included, ADC31 n+3 The comparator 61 n+3 -1 and comparator 61 n+3 -2 is included.

[0257] The saturation margin control section 400 includes resistors 401-1 to 401-4 and switches 402-1 to 402-8. In Fig. 11, each of the switches 402-1 to 402-8 is configured by a PMOS transistor.

[0258] One end of resistor 401-1 is connected to one end of switch 402-1, the other end of switch 402-1 is connected to power supply VDD, the other end of resistor 401-1 is connected to one end of resistor 401-2 and one end of switch 402-2, the other end of switch 402-2 is connected to power supply VDD, and the other end of resistor 401-2 is connected to one end of resistor 401-3 and one end of switch 402-3.

[0259] The other end of the switch 402-3 is connected to the power supply VDD, and the other end of the resistor 401-3 is connected to one end of a resistor 401-4 and one end of a switch 402-4. The other end of the switch 402-4 is connected to the power supply VDD.

[0260] The switches 402-5 to 402-8 are connected in parallel, one end of which is connected to the power supply VDD and the other end of which is connected to the voltage line 310.

[0261] The switches 402-1 to 402-4 function as resistance control switches 402, and the switches 402-5 to 402-8 function as power supply short-circuit control switches 402.

[0262] The resistance value of resistor 401-1 is 6R, the resistance value of resistor 401-2 is 2R, the resistance value of resistor 401-3 is R, and the resistance value of resistor 401-4 is 3R. When the resistance value of resistor 401-3 is used as a reference, the resistance value of resistor 401-1 is six times the resistance value of resistor 401-3, the resistance value of resistor 401-2 is twice the resistance value of resistor 401-3, and the resistance value of resistor 401-4 is three times the resistance value of resistor 401-3.

[0263] Four ADC31s n is set as one unit, and a horizontal connection switch 311 is provided at the division position of each unit. The horizontal connection switch 311 and the horizontal connection switch 311+1 are provided on the voltage line 310. The horizontal connection switch 311 is turned on during the auto-zero period, and is provided to average all the ADCs 31.

[0264] The comparator 61 in the seventh embodiment shown in FIG. n In the sixth embodiment, the comparator 61 n As with f, two comparators 61 n The operation pattern in which the four comparators 61 operate n The operation pattern in which six comparators 61 operate. n and eight comparators 61 n There is a pattern of operation that works.

[0265] <Operation Pattern in Which Two Comparators Operate> FIG. 21 shows an operation pattern in which two comparators 61 operate during the auto-zero period. n In the operation pattern shown in FIG. nComparator 61 included in n -1 and ADC31 n+2 Comparator 61 included in n+2 Two comparators 61 with -1 n operates, and the other comparator 61 n In the figure, the comparator 61 shown with diagonal lines is in the standby state. n indicates that the device is in standby mode.

[0266] Two comparators 61 n When the saturation margin control unit 400 operates, one switch 402 in the saturation margin control unit 400 is turned on, and the comparator 61 n 21, the switch 402-1 is turned on, and the other switches 402-2 to 402-8 are turned off.

[0267] When the switch 402-1 is turned on, a voltage Vout is applied to the comparator 61 via the resistors 401-1, 401-2, 401-3, and 401-4 connected in series. n -1 and comparator 61 n+2 A current is supplied to -1. In this case, the resistance value is 12R (=6R+2R+R+3R).

[0268] In an operating pattern in which two comparators 61n are operating, the voltage drop can be expressed as follows: 2×I×12R+Vds,sw=24IR+Vds,sw In this formula, I represents the current flowing through one comparator 61n, and Vds,sw represents the drain-source voltage of the switch 402. R represents 1 / 12 of the combined resistance value of resistors 401-1 to 401-4.

[0269] Comparator 61 n -1 and comparator 61 n+2 The current flowing through each of the comparators 61 is the current I. n -1 and comparator 61 n+2 The currents flowing through the terminals -1 and -2 are controlled to be the same.

[0270] This is an operating pattern for operating two comparators 61n, and during the auto-zero period, switches 402-5 to 402-8, which are power supply short control switches 402, are turned off, and switch 402-1, which is resistor connection control switch 402, is turned on, so that the current flows through resistor 401, creating a voltage drop.

[0271] FIG. 22 shows the two comparators 61 outside the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and ADC31 n+2 Comparator 61 included in n+2 Two comparators 61 with -1 n operates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0272] Two comparators 61 n When the auto-zero period is not in operation, one power supply short control switch 402 in the saturation margin control unit 400 is turned on, and the comparator 61 n 22, the switch 402-5 is turned on, and the other switches 402-1 to 402-4 and 402-6 to 402-8 are turned off.

[0273] When the switch 402-5 is turned on, the comparator 61 n -1 and comparator 61 n+2 22, the case where the switch 402-5 is turned on has been described as an example, but it is sufficient if any one of the power supply short control switches 402 from the switches 402-5 to 402-8 is turned on.

[0274] This is an operating pattern in which two comparators 61n operate, and outside the auto-zero period, the voltage drop is Vds,sw. Vds,sw is the drain-source voltage of the switch 402, and it can be seen that the voltage drops by that amount.

[0275] This is an operating pattern for operating two comparators 61n, and when it is outside the auto-zero period, any one of switches 402-5 to 402-8, which are power supply short control switches 402, is turned on, and switches 402-1 to 402-4, which are resistance control switches 402, are turned off, so that the current flows through switch 402, and a voltage drop can be created by the amount that passes through switch 402.

[0276] During the auto-zero period, the drain potential Vpch of FET 103 and FET 104 (FIG. 5) that form the current mirror of comparator 61n is VDD-Vds,sw-24IR, and the drain voltage and gate voltage of FET 101 and FET 102 that form the differential pair are the same, Vpch-Vds,pch.

[0277] Outside the auto-zero period, the drain potential Vpch of FET 103 and FET 104 (FIG. 5) that form the current mirror of comparator 61n becomes VDD-Vds,sw, and the drain potential of FET 101 and FET 102 that form the differential pair can be increased by IR. Outside the auto-zero period, switches 107 and 108 (FIG. 5) are off, so the gate potential does not change and it is possible to increase the saturation margin (Vds-Vgs) by 24IR.

[0278] By applying the seventh embodiment, even in the case of an operation pattern in which two comparators 61n are operating, deviation from the saturation region can be prevented, and vertical stripes can be prevented from occurring.

[0279] <Operation Pattern in Which Four Comparators Operate> FIG. 23 shows the operation pattern of the four comparators 61 during the auto-zero period. n In the operation pattern shown in FIG.n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -2 four comparators 61 n operates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0280] Four comparators 61 n When the saturation margin control unit 400 operates, one resistor control switch 402 in the saturation margin control unit 400 is turned on, and the comparator 61 n 23, the switch 402-2 is turned on, and the other switches 402-1, 402-3 to 402-8 are turned off.

[0281] When the switch 402-2 is turned on, a voltage Vout is applied to the comparator 61 via the resistors 401-2, 401-3, and 401-4 connected in series. n -1, comparator 61 n -2, comparator 61 n+2 -1, comparator 61 n+2 -2. In this case, the resistance value is 6R (=2R+R+3R).

[0282] In an operation pattern in which four comparators 61 operate, the voltage drop can be expressed as follows: 4×I×6R+Vds,sw=24IR+Vds,sw The voltage drop is the same value as in the operation pattern in which two comparators 61 operate.

[0283] Comparator 61 n -1, comparator 61 n -2, comparator 61 n+2 -1, comparator 61 n+2 The current flowing through each of the comparators 61 is the current I. n -1, comparator 61 n -2, comparator 61 n+2-1, comparator 61 n+2 The current flowing through -2 is controlled to be the same.

[0284] This is an operating pattern in which four comparators 61n are operated, and during the auto-zero period, the power supply short control switch 402 is turned off and the switch 402-2, which is the resistance control switch 402, is turned on, so that the current flows through the resistor 401, creating a voltage drop.

[0285] FIG. 24 shows the four comparators 61 outside the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2, ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -2 four comparators 61 n operates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0286] Four comparators 61 n When the power supply short circuit control switch 402 in the saturation margin control unit 400 is turned on, the power supply short circuit control switch 402 is turned on, and the comparator 61 n 24, the switches 402-5 and 402-6 are turned on, and the other switches 402-1 to 402-4, 402-7, and 402-8 are turned off.

[0287] When the switches 402-5 and 402-6 are turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+2 -1, and comparator 61 n+224, an example has been described in which the switches 402-5 and 402-6 are turned on, but it is sufficient if any two of the power supply short control switches 402 from the switches 402-5 to 402-8 are turned on.

[0288] In this operating pattern, four comparators 61n are operating, and outside the auto-zero period, the voltage drop is Vds,sw. Vds,sw is the drain-source voltage of the switch 402, and it can be seen that the voltage drops by that amount.

[0289] This is an operating pattern for operating four comparators 61n, and when it is outside the auto-zero period, any two of the switches 402-5 to 402-8, which are power supply short control switches 402, are turned on, and the switches 402-1 to 402-4, which are resistance control switches 402, are turned off, so that the current flows through the switches 402, and a voltage drop can be created by the amount that passes through the switches 402.

[0290] In the case of an operation pattern in which four comparators 61n are operating, it is possible to expand the saturation margin (Vds-Vgs) by 24IR, just as in the case of an operation pattern in which two comparators 61n are operating.

[0291] By applying the seventh embodiment, even in the case of an operation pattern in which four comparators 61n are operating, deviation from the saturation region can be prevented, and vertical streaks can be prevented from occurring.

[0292] <Operation Pattern in Which Six Comparators Operate> FIG. 25 shows the operation pattern of the six comparators 61 during the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+1 Comparator 61 included in n+1 -1, ADC31 n+2 Comparator 61 included inn+2 -1 and comparator 61 n+2 -2, and ADC31 n+3 Comparator 61 included in n+3 -1 six comparators 61 n operates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0293] Six comparators 61 n When the saturation margin control unit 400 operates, one resistor control switch 402 in the saturation margin control unit 400 is turned on, and the comparator 61 is turned on via two resistors 401. n 25, the switch 402-3 is turned on, and the other switches 402-1, 402-2, 402-4 to 402-8 are turned off.

[0294] When the switch 402-3 is turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2 -1, comparator 61 n+2 -2, and comparator 61 n+3 A current is supplied to -1. In this case, the resistance value is 4R (=R+3R).

[0295] In an operation pattern in which six comparators 61 operate, the voltage drop can be expressed as follows: 6×I×4R+Vds,sw=24IR+Vds,sw The voltage drop is the same value as in the operation pattern in which two comparators 61 operate.

[0296] Comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2 -1, comparator 61 n+2 -2, and comparator 61 n+3 The current flowing through each of the comparators 61 is the current I. n-1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2 -1, comparator 61 n+2 -2, and comparator 61 n+3 The current flowing through -1 is controlled to be the same.

[0297] This is an operating pattern that operates six comparators 61n, and during the auto-zero period, the power supply short control switch 402 is turned off and the switch 402-3, which is the resistance control switch 402, is turned on, so that the current flows through the resistor 401, creating a voltage drop.

[0298] FIG. 26 shows the six comparators 61 outside the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+1 Comparator 61 included in n+1 -1, ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -2, and ADC31 n+3 Comparator 61 included in n+3 -1 six comparators 61 n operates, and the other comparator 61 n indicates the case where the device is in standby mode.

[0299] Six comparators 61 n When the auto-zero period is not in operation, the three power supply short control switches 402 in the saturation margin control section 400 are turned on, and the six comparators 61 are outputted via the power supply short control switches 402 that are turned on. n 26, the switches 402-5 to 402-7 are turned on, and the other switches 402-1 to 402-4 and 402-8 are turned off.

[0300] When the switches 402-5 to 402-7 are turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2 -1, comparator 61 n+2 -2, and comparator 61 n+3 26, an example has been described in which switches 402-5 to 402-7 are turned on, but it is sufficient if any three of the power supply short control switches 402 among switches 402-5 to 402-8 are turned on.

[0301] In an operating pattern in which six comparators 61n are operating, the voltage drop is Vds,sw. Vds,sw is the drain-source voltage of the switch 402, and it can be seen that the voltage drops by that amount.

[0302] This is an operating pattern for operating six comparators 61n, and when it is outside the auto-zero period, any three of the switches 402-5 to 402-8 that are power supply short control switches 402 are turned on, and the switches 402-1 to 402-4 that are resistance control switches 402 are turned off, so that the current flows through the switches 402, and a voltage drop can be created that is equal to the amount that passes through the switches 402.

[0303] In the case of an operation pattern in which six comparators 61n are operating, it is possible to expand the saturation margin (Vds-Vgs) by 24IR, just as in the case of an operation pattern in which two comparators 61n are operating.

[0304] By applying the seventh embodiment, even in the case of an operation pattern in which six comparators 61n are operating, deviation from the saturation region can be prevented, and vertical stripes can be prevented from occurring.

[0305] <Operation Pattern in Which Eight Comparators Operate> FIG. 27 shows the operation pattern of the eight comparators 61 during the auto-zero period. nIn the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+1 Comparator 61 included in n+1 -1 and comparator 61 n+1 -2, ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61 n+2 -1, and ADC31 n+3 Comparator 61 included in n+3 -1 and comparator 61 n+3 -2 eight comparators 61 n operates, and the comparator 61 in the standby state n indicates a non-existent state.

[0306] 8 comparators 61 n When the saturation margin control unit 400 operates, one resistor control switch 402 in the saturation margin control unit 400 is turned on, and the comparator 61 n 27, the switch 402-4, which is the resistance control switch 402, is turned on, and the switches 402-5 to 402-8, which are the power supply short-circuit control switches 402, and the switches 402-1 to 402-3, which are the resistance control switches 402, are turned off.

[0307] When the switch 402-4 is turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+1 -2, comparator 61 n+2 -1, comparator 61 n+2 -2, comparator 61 n+3 -1, and comparator 61 n+3 -2. In this case, the resistance value is 3R.

[0308] In an operation pattern in which eight comparators 61 operate, the voltage drop can be expressed as follows: 8×I×R+3Vds,sw=24IR+Vds,sw The voltage drop is the same value as in the operation pattern in which two comparators 61 operate.

[0309] Comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+1 -2, comparator 61 n+2 -1, comparator 61 n+2 -2, comparator 61 n+3 -1, and comparator 61 n+3 The current flowing through each of the comparators 61 is the current I. n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+2 -1, comparator 61 n+2 -1, and comparator 61 n+3 The current flowing through -1 is controlled to be the same.

[0310] This is an operating pattern in which eight comparators 61n are operated, and during the auto-zero period, the power supply short control switch 402 is turned off and the resistance control switch 402 is turned on, so that the current flows through the resistor 401, creating a voltage drop.

[0311] FIG. 28 shows the eight comparators 61 outside the auto-zero period. n In the operation pattern shown in FIG. n Comparator 61 included in n -1 and comparator 61 n -2 and ADC31 n+1 Comparator 61 included in n+1 -1 and comparator 61 n+1 -2, ADC31 n+2 Comparator 61 included in n+2 -1 and comparator 61n+2 -2, and ADC31 n+3 Comparator 61 included in n+3 -1 and comparator 61 n+3 -2 eight comparators 61 n is working.

[0312] 8 comparators 61 n When the saturation margin control unit 400 operates, all four power supply short control switches 402 in the saturation margin control unit 400 are turned on, and the eight comparators 61 are turned on via the power supply short control switches 402 that are turned on. n 28, the switches 402-5 to 402-8 are turned on, and the switches 402-1 to 402-4, which are the resistance control switches 402, are turned off.

[0313] When the switches 402-5 to 402-8 are turned on, the comparator 61 n -1, comparator 61 n -2, comparator 61 n+1 -1, comparator 61 n+1 -2, comparator 61 n+2 -1, comparator 61 n+2 -2, comparator 61 n+3 -1, and comparator 61 n+3 -2, and a current flows through them.

[0314] This is an operating pattern in which eight comparators 61n operate, and outside the auto-zero period, the voltage drop is Vds,sw. Vds,sw is the drain-source voltage of the switch 402, and it can be seen that the voltage drops by that amount.

[0315] This is an operating pattern for operating eight comparators 61n, and when it is outside the auto-zero period, all of the switches 402-5 to 402-8 that are power supply short control switches 402 are turned on, and all of the switches 402-1 to 402-4 that are resistance control switches 402 are turned off, so that the current flows through the switches 402, and a voltage drop can be created that is equal to the amount that passes through the switches 402.

[0316] In the case of an operation pattern in which eight comparators 61n are operating, it is possible to expand the saturation margin (Vds-Vgs) by 24IR, just as in the case of an operation pattern in which two comparators 61n are operating.

[0317] By applying the seventh embodiment, even in the case of an operation pattern in which eight comparators 61n are operating, deviation from the saturation region can be prevented, and vertical streaks can be prevented from occurring.

[0318] In the seventh embodiment, too, if the drain voltage of FET 101 and FET 102 that form a differential pair during the auto-zero period is Vds1 and the drain voltage of FET 101 and FET 102 that form a differential pair outside the auto-zero period is Vds2, the following equation holds true:

[0319] Vds1=(VDD-24IR-Vds,sw-Vgsp)-(Vg1-Vgsn) Vds2=(VDD-Vds,sw-Vgsp)-(Vg1-Vgsn) Vds2-Vds1=24IR

[0320] It can be seen that the voltage difference between the differential pair during the auto-zero period and outside the auto-zero period is 24IR. n f, the comparator 61 in the first embodiment n As in a, the voltage Vds of the differential pair increases, so deviation from the saturation region can be prevented, and vertical stripes can be prevented from occurring.

[0321] In the sixth and seventh embodiments, an example has been described in which four ADCs 31 are treated as one unit and a saturation margin control unit 300 (400) is provided for each unit, but the present technology can also be applied to cases in which one unit includes a plurality of ADCs 31 other than four, for example, two or six ADCs 31. Furthermore, an example has been described in which one ADC 31 includes two comparators 61 n, but the present technology can also be applied to cases in which one ADC 31 includes a plurality of comparators 61 n other than two.

[0322] The number of resistors 301 (401) and switches 302 (402) included in the saturation margin control section 300 (400) corresponds to the number of comparators 61n included in one unit.

[0323] In the above embodiment, an example was given in which one unit includes eight comparators 61n, and therefore the saturation margin control unit 300 (400) is configured with eight switches 302 (402) and half of that number, four resistors 301 (401). If one unit includes an even number of comparators 61n other than eight, the saturation margin control unit 300 (400) is configured with the same number of switches 302 (402) as the even number and half of that number of resistors 301 (401).

[0324] <Application Example to Endoscopic Surgery System> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0325] FIG. 29 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0326] 29 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0327] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0328] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0329] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0330] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0331] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0332] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical area, etc.

[0333] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0334] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0335] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0336] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0337] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0338] FIG. 30 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0339] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0340] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0341] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0342] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0343] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0344] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0345] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0346] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0347] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0348] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0349] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0350] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0351] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0352] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0353] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0354] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0355] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0356] FIG. 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0357] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 31 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0358] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0359] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0360] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0361] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0362] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0363] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0364] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0365] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0366] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 31, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0367] FIG. 32 is a diagram showing an example of the installation position of the imaging unit 12031.

[0368] In FIG. 32, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0369] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0370] 32 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0371] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0372] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0373] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0374] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0375] In this specification, a system refers to an entire device made up of multiple devices.

[0376] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0377] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology.

[0378] The present technology can also be configured as follows: (1) A pixel having a photoelectric conversion element that performs photoelectric conversion and that outputs an electric signal, a reference signal output unit that outputs a reference signal whose level changes, a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit, a counter that counts the time required for the reference signal to change until the electric signal matches the reference signal based on the output signal output from the comparator, and an ADC that includes the comparator and the counter and performs AD (Analog-to-Digital) conversion of the electric signal, wherein a first even number of the ADCs are defined as one unit, and one ADC includes a second even number of the comparators, and further includes a control unit that includes the first even number of resistors, first switches connected to each of the resistors, and the first even number of second switches that are not connected to the resistors, and the control unit (2) An image sensor that controls the first switches to be turned on according to the number of comparators to be driven during an auto-zero period, so that a current is supplied to the comparator to be driven via the resistor connected to the first switch that has been turned on, and controls the second switches to be turned on outside the auto-zero period, so that a current is supplied to the comparator to be driven via the second switch that has been turned on. (3) The image sensor of (1), in which half of the first switches of the comparators to be driven are turned on. (4) The image sensor of any of (1) to (3), in which the same number of second switches as half of the comparators to be driven are turned on. (5) The image sensor according to (2), wherein the first even number of resistors have the same resistance value. (6) The image sensor according to (3), wherein the first even number of resistors have different resistance values.(7) An imaging element includes: pixels each having a photoelectric conversion element for performing photoelectric conversion and outputting an electric signal; a reference signal output unit for outputting a reference signal whose level changes; a comparator for comparing the electric signal output from the pixel with the reference signal output from the reference signal output unit; a counter for counting, based on the output signal from the comparator, a time required for the reference signal to change until the electric signal matches the reference signal; and an ADC including the comparator and the counter and performing AD (Analog-to-Digital) conversion of the electric signal, wherein a first even number of the ADCs are one unit, and one ADC includes a second even number of the comparators; and a control unit including the first even number of resistors, first switches connected to each of the resistors, and the first even number of second switches not connected to the resistors, wherein the control unit a driving method for controlling the first switches to be turned on during an auto-zero period in accordance with the number of comparators to be driven, and controlling so that a current is supplied to the comparator to be driven via the resistor connected to the first switches that have been turned on; and a driving method for controlling the second switches to be turned on outside the auto-zero period in accordance with the number of comparators to be driven, and controlling so that a current is supplied to the comparator to be driven via the second switches that have been turned on. (8) An imaging element comprising: a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electrical signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electrical signal output from the pixel with the reference signal output from the reference signal output unit; and a counter that counts the time required for the reference signal to change until the electrical signal matches the reference signal based on the output signal from the comparator, wherein the comparator includes a current mirror and a differential pair, and a switch and a resistor are connected in parallel between the current mirror and a power supply line connected to a power source, and the switch is turned off during an auto-zero period, and the switch is turned on outside the auto-zero period.(9) The imaging element according to (8), wherein the resistor is a PMOS (positive channel MOS) transistor. (10) A driving method for an imaging element comprising: pixels each having a photoelectric conversion element for performing photoelectric conversion and outputting an electric signal; a reference signal output unit outputting a reference signal whose level changes; a comparator for comparing the electric signal output from the pixel with the reference signal output from the reference signal output unit; and a counter for counting, based on the output signal from the comparator, a time required for the reference signal to change until the electric signal matches the reference signal, wherein the comparator includes a current mirror and a differential pair, and a switch and a resistor connected in parallel between the current mirror and a power supply line connected to a power supply, wherein the comparator turns off the switch during an auto-zero period and turns on the switch outside the auto-zero period. (11) An image sensor comprising: a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; and a counter that counts a time required for the reference signal to change until the electric signal matches the reference signal, based on the output signal from the comparator, wherein the comparator includes a current mirror and a differential pair; and a switch and a resistor connected in parallel between the current mirror and the differential pair, wherein the switch is turned off during an auto-zero period and the switch is turned on outside the auto-zero period. (12) The image sensor according to (11), wherein the resistor is a PMOS transistor. (13) The image sensor according to (11), wherein the switch is an LVT transistor having a low threshold voltage, and the resistor is an SVT transistor having a standard threshold voltage.(14) A driving method comprising: a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electric signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electric signal output from the pixel with the reference signal output from the reference signal output unit; and a counter that counts the time required for the reference signal to change until the electric signal matches the reference signal based on the output signal output from the comparator, wherein the comparator includes a current mirror and a differential pair, and a switch and a resistor connected in parallel between the current mirror and the differential pair, and the comparator turns off the switch during an auto-zero period and turns on the switch outside the auto-zero period.

[0379] REFERENCE SIGNS LIST 1 Optical system, 2 Image sensor, 3 Memory, 4 Signal processing unit, 5 Output unit, 6 Control unit, 10 Pixel array, 20 Control unit, 21 Pixel driving unit, 22 Column parallel AD conversion unit, 23 Output unit, 32 Auto-zero control unit, 33 Reference signal output unit, 34 Clock output unit, 52 Transfer transistor, 54 Reset transistor, 55 Amplification transistor, 56 Selection transistor, 61 Comparator, 107 Switch, 108 Switch, 111 Pixel, 201 Resistor, 202 Switch, 300 Saturation margin control unit, 301 Resistor, 302 Switch, 303 Voltage line, 310 Voltage line, 311 Horizontal connection switch, 400 Saturation margin control unit, 401 Resistor, 402 Switch

Claims

a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electrical signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electrical signal output from the pixel with the reference signal output from the reference signal output unit; a counter that counts the time required for the reference signal to change until the electrical signal and the reference signal match, based on the output signal output by the comparator; an ADC including the comparator and the counter, which performs AD (Analog-to-Digital) conversion of the electrical signal; Equipped with A first even number of the ADCs is taken as one unit, one ADC includes a second even number of the comparators; a control unit including the first even number of resistors, first switches connected to each of the resistors, and the first even number of second switches not connected to the resistors; The control unit during an auto-zero period, controlling the first switches to be turned on in accordance with the number of comparators to be driven, and controlling so that current is supplied to the comparators to be driven via the resistors connected to the first switches that have been turned on; Outside the auto-zero period, the second switches to be turned on are controlled in accordance with the number of the comparators to be driven, and control is performed so that a current is supplied to the comparators to be driven via the second switches that have been turned on. Image sensor. 　 Turning on the first switches of half of the comparators to be driven The imaging device according to claim 1 . 　 the first even number of resistors are connected in series; the first switch is arranged so that the number of resistors through which a current flows varies depending on the number of comparators to be driven; The first switches corresponding to the number of the comparators to be driven are turned on. The imaging device according to claim 1 . 　 The second switches are turned on in the same number as half of the comparators to be driven. The imaging device according to claim 1 . 　 The first even number of resistors have the same resistance value. The imaging device according to claim 2 . 　 The first even number of resistors have different resistance values. The imaging device according to claim 3 . 　 The image sensor is a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electrical signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electrical signal output from the pixel with the reference signal output from the reference signal output unit; a counter that counts the time required for the reference signal to change until the electrical signal and the reference signal match, based on the output signal output by the comparator; an ADC including the comparator and the counter, which performs AD (Analog-to-Digital) conversion of the electrical signal; Equipped with A first even number of the ADCs is taken as one unit, one ADC includes a second even number of the comparators; a control unit including the first even number of resistors, first switches connected to each of the resistors, and the first even number of second switches not connected to the resistors; The control unit during an auto-zero period, controlling the first switches to be turned on in accordance with the number of comparators to be driven, and controlling so that current is supplied to the comparators to be driven via the resistors connected to the first switches that have been turned on; Outside the auto-zero period, the second switches to be turned on are controlled in accordance with the number of the comparators to be driven, and control is performed so that a current is supplied to the comparators to be driven via the second switches that have been turned on. Drive method. 　 a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electrical signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electrical signal output from the pixel with the reference signal output from the reference signal output unit; a counter that counts the time required for the reference signal to change until the electrical signal and the reference signal match, based on the output signal output by the comparator; Equipped with the comparator includes a current mirror and a differential pair; a switch and a resistor connected in parallel between the current mirror and a power supply line connected to a power supply; During the auto-zero period, the switch is turned off, Outside the auto-zero period, the switch is turned on. Image sensor. 　 The resistor is a PMOS (positive channel MOS) transistor. The imaging device according to claim 8 . 　 The image sensor is a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electrical signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electrical signal output from the pixel with the reference signal output from the reference signal output unit; a counter that counts the time required for the reference signal to change until the electrical signal and the reference signal match, based on the output signal output by the comparator; Equipped with the comparator includes a current mirror and a differential pair; a switch and a resistor connected in parallel between the current mirror and a power supply line connected to a power supply; The comparator During the auto-zero period, the switch is turned off. Outside the auto-zero period, the switch is turned on. Drive method. 　 a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electrical signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electrical signal output from the pixel with the reference signal output from the reference signal output unit; a counter that counts the time required for the reference signal to change until the electrical signal and the reference signal match, based on the output signal output by the comparator; Equipped with the comparator includes a current mirror and a differential pair; a switch and a resistor connected in parallel between the current mirror and the differential pair; During the auto-zero period, the switch is turned off, Outside the auto-zero period, the switch is turned on. Image sensor. 　 The resistor is a PMOS transistor The imaging device according to claim 11. 　 the switch is an LVT transistor with a low threshold voltage; The resistor is an SVT transistor with a standard threshold voltage The imaging device according to claim 11. 　 a pixel having a photoelectric conversion element that performs photoelectric conversion and outputs an electrical signal; a reference signal output unit that outputs a reference signal whose level changes; a comparator that compares the electrical signal output from the pixel with the reference signal output from the reference signal output unit; a counter that counts the time required for the reference signal to change until the electrical signal and the reference signal match, based on the output signal output by the comparator; Equipped with the comparator includes a current mirror and a differential pair; a switch and a resistor connected in parallel between the current mirror and the differential pair; The comparator During the auto-zero period, the switch is turned off. Outside the auto-zero period, the switch is turned on. Drive method.

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