Display panel and electronic device comprising same

Abstract

An embodiment of the present invention provides a display device comprising a first pixel circuit including: a first conductive pattern disposed on a substrate; a second conductive pattern disposed on the first conductive pattern and disposed to overlap the first conductive pattern; a first semiconductor pattern including a semiconductor layer of the driving transistor disposed on the second conductive pattern; a second semiconductor pattern disposed on the same layer as the first semiconductor pattern and spaced apart from the first semiconductor pattern; and a third conductive pattern disposed on the first semiconductor pattern and connecting the first semiconductor pattern and the second conductive pattern, wherein the first conductive pattern is electrically connected to the second semiconductor pattern, and a partial region of the second semiconductor pattern extends in a first direction and overlaps a hold gate line electrically connected to the first pixel circuit.

Description

Display panel and electronic device including same

[0001] The present invention relates to a display panel and an electronic device including the same.

[0002] As display device usage rapidly expands, their applications are expanding beyond mobile devices and wearable technology to automotive displays and large-scale signage. As display technology advances, the demand for higher resolution and improved image quality is also growing to meet the expectations of various industries and consumers. Implementing high-resolution displays may require integrating various electronic components into increasingly tight spaces. This presents numerous technical challenges, including managing signal interference, ensuring power efficiency, and maintaining device reliability. Addressing these challenges requires innovative design approaches that optimize performance, reduce power consumption, and reduce manufacturing complexity for display panels, pixel circuits, and related components.

[0003] Embodiments of the present invention aim to provide a display panel with improved display quality and an electronic device including the same. However, these tasks are exemplary and should not be construed as limiting the scope of the present invention.

[0004] One embodiment of the present invention provides a display panel including: a substrate; a first pixel circuit disposed on the substrate and including a driving transistor; and a light emitting diode connected to the first pixel circuit; wherein the first pixel circuit comprises: a first conductive pattern disposed on the substrate; a second conductive pattern disposed on the first conductive pattern and overlapping the first conductive pattern; a first semiconductor pattern including a semiconductor layer of the driving transistor disposed on the second conductive pattern; a second semiconductor pattern disposed on the same layer as the first semiconductor pattern but spaced apart from the first semiconductor pattern; a third conductive pattern disposed on the first semiconductor pattern and connecting the first semiconductor pattern and the second conductive pattern; the first conductive pattern is electrically connected to the second semiconductor pattern, and a portion of the second semiconductor pattern extends in a first direction and overlaps a hold gate line electrically connected to the first pixel circuit.

[0005] In one embodiment, the first conductive pattern and the second conductive pattern can form a hold capacitor of the first pixel circuit.

[0006] In one embodiment, the device further includes a reference voltage line extending along the first direction and electrically connected to the first pixel circuit, wherein one end of the second semiconductor pattern is electrically connected to the first conductive pattern, and the other end of the second semiconductor pattern is electrically connected to the reference voltage line.

[0007] In one embodiment, the first pixel circuit further includes a fourth conductive pattern disposed on the same layer as the third conductive pattern but spaced apart from the third conductive pattern, and the second semiconductor pattern can be electrically connected to the first conductive pattern through the fourth conductive pattern.

[0008] In one embodiment, the hold gate line may be arranged between the first semiconductor pattern and the third conductive pattern based on the thickness direction of the substrate.

[0009] In one embodiment, the hold gate line may be disposed on the same layer as the gate electrode of the driving transistor.

[0010] In one embodiment, the first pixel circuit further includes a third semiconductor pattern disposed on the same layer as the first semiconductor pattern, but spaced apart from the first semiconductor pattern; and a fifth conductive pattern connecting the gate electrode of the driving transistor and the third semiconductor pattern; wherein the fifth conductive pattern can be disposed on the same layer as the third conductive pattern.

[0011] In one embodiment, the semiconductor device further includes a scan line extending along the first direction and electrically connected to the first pixel circuit; and a data line extending along a second direction intersecting the first direction and electrically connected to the first pixel circuit; wherein a portion of the third semiconductor pattern overlaps a portion of the scan line, and one end of the third semiconductor pattern can be electrically connected to the data line.

[0012] In one embodiment, on a plane, the hold gate line may be arranged to cross between the semiconductor pattern and the third semiconductor pattern.

[0013] In one embodiment, on a plane, a portion of the hold gate line may overlap with the fifth conductive pattern.

[0014] In one embodiment, the first pixel circuit further includes a fourth semiconductor pattern disposed between the substrate and the first conductive pattern; and a sixth conductive pattern connecting one end of the first semiconductor pattern and the fourth semiconductor pattern; wherein the sixth conductive pattern may be disposed on the same layer as the third conductive pattern.

[0015] In one embodiment, the first semiconductor pattern and the fourth semiconductor pattern may include different materials.

[0016] In one embodiment, the first semiconductor pattern may include an oxide semiconductor material, and the fourth semiconductor pattern may include a silicon semiconductor material.

[0017] In one embodiment, the device further includes a first light-emitting control line extending along the first direction and electrically connected to the first pixel circuit; and a driving voltage line extending along the first direction or a second direction intersecting the first direction and electrically connected to the first pixel circuit; wherein a part of the fourth semiconductor pattern overlaps the first light-emitting control line, and one end of the fourth semiconductor pattern can be electrically connected to the driving voltage line.

[0018] In one embodiment, on a plane, the hold gate line may be arranged to cross between the first semiconductor pattern and the fourth semiconductor pattern.

[0019] In one embodiment, on a plane, a portion of the hold gate line may overlap with the sixth conductive pattern.

[0020] In one embodiment, the first pixel circuit further includes a fifth semiconductor pattern disposed on the same layer as the first semiconductor pattern, but spaced apart from the first semiconductor pattern; the third conductive pattern includes a central portion and a protrusion branching from the central portion, and the protrusion of the third conductive pattern can be electrically connected to the fifth semiconductor pattern.

[0021] In one embodiment, a second light-emitting control line extending along the first direction and electrically connected to the first pixel circuit; and a portion of the fifth semiconductor pattern overlaps the second light-emitting control line, and one end of the fifth semiconductor pattern can be electrically connected to the light-emitting diode.

[0022] In one embodiment, on a plane, the hold gate line may be arranged to cross between the first semiconductor pattern and the fifth semiconductor pattern.

[0023] In one embodiment, on a plane, a portion of the hold gate line may overlap with a protrusion of the third conductive pattern.

[0024] Another embodiment of the present invention provides a display panel including: a substrate; a first pixel circuit disposed on the substrate; a hold gate line extending in a first direction and electrically connected to the first pixel circuit; and a light-emitting diode electrically connected to the first pixel circuit; wherein the first pixel circuit includes: a first transistor; a first connection electrode connecting the first transistor and the light-emitting diode; a hold capacitor including a first hold electrode and a second hold electrode facing the first hold electrode and electrically connected to the first connection electrode; and a second transistor electrically connected to the first hold electrode; wherein the hold gate line includes a gate electrode of the second transistor.

[0025] In one embodiment, based on the thickness direction of the substrate, the second hold electrode may be disposed on the first hold electrode, the semiconductor layer of the first transistor may be disposed on the second hold electrode, and the first connection electrode may be disposed on the semiconductor layer of the first transistor.

[0026] In one embodiment, based on the thickness direction of the substrate, the hold gate line may be interposed between the semiconductor layer of the first transistor and the first connection electrode.

[0027] In one embodiment, the first pixel circuit may further include a third transistor connected between a data line and a gate electrode of the first transistor; and a fourth transistor connected between a reference voltage line and a gate electrode of the first transistor.

[0028] In one embodiment, the second transistor may be connected between the hold capacitor and the reference voltage line.

[0029] In one embodiment, on a plane, the hold gate line may be arranged to cross between the first transistor and the third transistor.

[0030] In one embodiment, the first pixel circuit further includes a second connection electrode connecting the gate electrode of the first transistor and the semiconductor layer of the second transistor, and a portion of the hold gate line may overlap the second connection electrode.

[0031] In one embodiment, the second connecting electrode may be disposed on the same layer as the first connecting electrode, but may be disposed spaced apart from each other.

[0032] In one embodiment, the first pixel circuit may further include a fifth transistor connected between the driving voltage line and the first transistor; and a sixth transistor connected between the first transistor and the light-emitting diode.

[0033] In one embodiment, the hold gate line may include a stem portion extending along the first direction; and a branch portion branching from the stem portion and extending in a second direction intersecting the first direction.

[0034] In one embodiment, the gate electrode of the second transistor may be formed on a branch portion of the hold gate line.

[0035] In one embodiment, on a plane, the stem of the hold gate line may be arranged to cross between the first transistor and the fifth transistor.

[0036] In one embodiment, the first connection electrode is connected to the semiconductor layer of the sixth transistor, and a portion of the stem of the hold gate line may overlap with the first connection electrode.

[0037] In one embodiment, the first pixel circuit further includes a third connection electrode connecting the semiconductor layer of the first transistor and the semiconductor layer of the fifth transistor, and a portion of the stem portion of the hold gate line may overlap with the third connection electrode.

[0038] In one embodiment, the third connecting electrode may be disposed on the same layer as the first connecting electrode, but may be disposed spaced apart from the first connecting electrode.

[0039] In one embodiment, the semiconductor layer of the first transistor and the semiconductor layer of the fifth transistor may be disposed on different layers.

[0040] In one embodiment, the semiconductor layer of the first transistor may include an oxide semiconductor material, and the semiconductor layer of the fifth transistor may include a silicon-based semiconductor material.

[0041] In one embodiment, the second pixel circuit is further included, which is disposed on the substrate and is disposed adjacent to the first pixel circuit along the first direction; and the first transistor, the hold capacitor, and the second transistor of the first pixel circuit can be symmetrical with respect to an imaginary straight line extending in a second direction intersecting the first direction with respect to each of the first transistor, the hold capacitor, and the second transistor of the second pixel circuit.

[0042] In one embodiment, the device further includes a third pixel circuit disposed on the substrate and adjacent to the second pixel circuit along the first direction, wherein the first transistor, the hold capacitor, and the second transistor of the second pixel circuit can be symmetrical with respect to an imaginary straight line extending in a second direction intersecting the first direction with respect to each of the first transistor, the hold capacitor, and the second transistor of the third pixel circuit.

[0043] In one embodiment, the hold gate line includes a stem portion extending along the first direction; and a branch portion branching from the stem portion and extending in the second direction; and the branch portion of the hold gate line may include a first branch portion protruding toward the second transistor of the first pixel circuit; and a second branch portion protruding toward the second transistor of the second pixel circuit and the second transistor of the third pixel circuit.

[0044] Another embodiment of the present invention comprises a display panel; and a lower cover forming an exterior and having an opening exposing a portion of the display panel on a front surface; wherein the display panel comprises: a substrate; a first pixel circuit disposed on the substrate and including a driving transistor; a hold gate line extending in a first direction and electrically connected to the first pixel circuit; and a light emitting diode connected to the first pixel circuit; wherein the first pixel circuit comprises: a first conductive pattern disposed on the substrate; a second conductive pattern disposed on the first conductive pattern and overlapping the first conductive pattern; a first semiconductor pattern including a semiconductor layer of the driving transistor disposed on the second conductive pattern; a second semiconductor pattern disposed on the same layer as the first semiconductor pattern but spaced apart from the first semiconductor pattern; a third conductive pattern disposed on the first semiconductor pattern and connecting the first semiconductor pattern and the second conductive pattern; An electronic device is provided, wherein the first conductive pattern is electrically connected to the second semiconductor pattern, and a portion of the second semiconductor pattern overlaps the hold gate line.

[0045] According to some embodiments of the present invention, a display panel and electronic device can be provided that improve power consumption and provide high-quality images. The aforementioned effects are exemplary, and the effects of the present invention are not limited to those described above.

[0046] FIG. 1 is a perspective view showing an electronic device according to one embodiment of the present invention.

[0047] Figure 2 is an exploded perspective view showing an electronic device according to one embodiment of the present invention.

[0048] FIG. 3 is a block diagram showing an electronic device according to one embodiment of the present invention.

[0049] FIG. 4 is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0050] FIG. 5 is a side view schematically illustrating a display panel according to one embodiment of the present invention.

[0051] Figure 6 is a plan view schematically showing a display panel according to one embodiment of the present invention.

[0052] FIG. 7 is a plan view schematically showing pixel circuits of a display panel according to one embodiment of the present invention.

[0053] FIG. 8 is a cross-sectional view of a display panel according to one embodiment of the present invention, showing a cross-section taken along line Ⅷ-Ⅷ' of FIG. 6.

[0054] FIGS. 9 to 16 are plan views illustrating a process for forming a pixel circuit of a display panel according to one embodiment of the present invention.

[0055] Fig. 17 is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0056] FIG. 18 is a plan view schematically showing pixel circuits of a display panel according to another embodiment of the present invention.

[0057] FIGS. 19 to 26 are plan views illustrating a process for forming a pixel circuit of a display panel according to another embodiment of the present invention.

[0058] Fig. 27 is an enlarged plan view of a portion of a display panel according to another embodiment of the present invention.

[0059] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In this case, similar reference numerals may indicate similar components throughout the specification and drawings. The embodiments may have various forms and should not be construed as limited to the contents set forth in the specification. Therefore, the embodiments are described only by way of example with reference to the drawings for the purpose of explaining various aspects of the present invention. The term "and / or" used herein means any combination including at least one of the listed items. In addition, the expression "at least one of a, b, or c" includes variations such as a case where only a is included, a case where only b is included, a case where only c is included, a combination of a and b, a and c, b and c, or a case where all of a, b, and c are included.

[0060] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not necessarily limited to the embodiments disclosed below and may be implemented in various forms.

[0061] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. In the description referring to the drawings, the same reference numerals may be assigned to identical or substantially identical components. If a specific component is not described in detail in the drawings, it is understood that it is at least similar to a corresponding component described elsewhere in this specification.

[0062] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0063] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0064] In the examples below, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0065] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0066] Each drawing illustrates one or more specific embodiments of the present disclosure and may be drawn to scale so that relative lengths, thicknesses, angles, etc., may be inferred from the drawings; however, the present disclosure is not necessarily limited to the relative lengths, thicknesses, and angles depicted in the drawings. These values ​​may be modified within the spirit and scope of the present disclosure, for example, in consideration of manufacturing constraints. If an embodiment is otherwise feasible, a particular process sequence may be performed differently from the order described. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in the reverse order of the order described.

[0067] In the following examples, when it is said that a film, region, component, etc. are connected, it includes not only cases where the films, regions, and components are directly connected, but also cases where other films, regions, and components are interposed between the films, regions, and components and thus indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it includes not only cases where the films, regions, and components are directly electrically connected, but also cases where other films, regions, and components are interposed between them and thus indirectly electrically connected.

[0068] Embodiments of the present disclosure relate to the specific structure and arrangement of a display panel and its associated components for enhancing the functionality and efficiency of a high-resolution display. This can be achieved through an innovative pixel circuit design that minimizes power loss and optimizes signal transmission, thereby enhancing display performance, by introducing a pixel circuit structure comprising a driving transistor, multiple transistors, and capacitors.

[0069] A variety of semiconductor materials, such as oxide-based or silicon-based layers, can be used to achieve high carrier mobility and low leakage current. These materials can be stacked to increase reliability and reduce interference.

[0070] By symmetrically configuring the arrangement of pixel circuits, consistency in signal processing and display quality can be maintained.

[0071] By integrating flexible and rigid elements, displays can be implemented that are adaptable to various applications such as smartphones, wearable devices, and automotive displays.

[0072] This approach aims to deliver superior visual quality, reduced energy consumption, and increased design and functional flexibility.

[0073] Depending on the method, power loss can be minimized by using a dual-gate driving transistor in display pixel design. For example, the driving transistor (T1) may have a dual-gate structure including a lower gate electrode connected to a capacitor (Chd) and a node electrode (N2). This configuration can ensure a stable voltage level and reduce signal interference, thereby minimizing power consumption.

[0074] The transistor can use oxide semiconductor materials such as InGaZnO or InSnZnO, which provide high carrier mobility and low leakage current, thereby reducing power loss during operation and increasing the efficiency of current flow.

[0075] Capacitors such as hold capacitors (Chd) and storage capacitors (Cst) can be strategically placed to stabilize voltage and reduce transient power loss, thereby preventing unnecessary current consumption.

[0076] The symmetrical and modular layout of pixel circuits minimizes signal overlap and wiring inefficiency, allowing power to be transmitted efficiently without unnecessary consumption.

[0077] The pixel circuit may include light-emitting control transistors (T5 and T6) that control the current flowing to the light-emitting elements, and these transistors can precisely control the current to flow only during the active light-emitting section, thereby minimizing power waste.

[0078] By utilizing capacitive coupling between transistors and voltage lines, voltage levels throughout the circuit can be stabilized, reducing signal noise and power loss.

[0079] These various measures improve the power efficiency of the display panel, making it suitable for high-performance and power-sensitive applications.

[0080] FIG. 1 is a perspective view showing an electronic device (1) according to one embodiment of the present invention, FIG. 2 is an exploded perspective view showing an electronic device (1) according to one embodiment of the present invention, and FIG. 3 is a block diagram showing an electronic device (1) according to one embodiment of the present invention.

[0081] Referring to FIGS. 1 and 2, an electronic device (1) according to one embodiment is a device that displays a moving image or a still image, and can be used as a display screen for various products such as portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a computer monitor, a billboard such as a digital billboard, and the Internet of Things (IOT). The electronic device (1) according to one embodiment can be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). An electronic device (1) according to one embodiment can be used as a dashboard of a vehicle, a CID (Center Information Display) placed on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, and a display placed on the back of a front seat as entertainment for the rear seat of a vehicle.

[0082] For convenience of explanation, FIGS. 1 and 2 illustrate an electronic device (1) according to one embodiment being used as a smart phone. The electronic device (1) according to one embodiment may include a cover window (70), a display panel (10), a data driver (20), a display circuit board (30), a component (40), a bracket (60), a main circuit board (50), a battery (80), and a lower cover (90).

[0083] In the plan view of this specification, “left,” “right,” “upper,” and “lower” indicate directions when looking at the display panel (10) from a direction perpendicular to the display panel (10). For example, “left” indicates the -x direction, “right” indicates the +x direction, “upper” indicates the +y direction, and “lower” indicates the -y direction.

[0084] The electronic device (1) may be formed in a rectangular shape on a plane. For example, the electronic device (1) may have a rectangular shape on a plane having a pair of short sides extending in the x direction and a pair of long sides extending in the y direction, as shown in FIG. 1. The corner where the short side in the x direction and the long side in the y direction meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the electronic device (1) is not necessarily limited to a rectangle, and may be formed in another polygonal, oval, or irregular shape.

[0085] The cover window (70) can be placed on the upper part of the display panel (10) to cover the upper surface of the display panel (10). As a result, the cover window (70) can function to protect the upper surface of the display panel (10).

[0086] The cover window (70) may include a transparent cover portion (DA70) corresponding to the display panel (10) and a light-blocking cover portion (NDA70) surrounding the transparent cover portion (DA70). The light-blocking cover portion (NDA70) may include an opaque material (e.g., a colored opaque material) that blocks light. The light-blocking cover portion (NDA70) may include a pattern that can be shown to a user when an image is not displayed.

[0087] The display panel (10) can be placed at the bottom of the cover window (70). The display panel (10) can overlap with the transparent cover portion (DA70) of the cover window (70).

[0088] The display panel (10) includes a display area (DA). The display area (DA) is an area where an image is displayed, and the display area (DA) may include an area (hereinafter, referred to as a component area) that transmits light emitted from a component (40) positioned at the bottom of the display panel (10). The component may include a sensor or camera that utilizes visible light, infrared rays, or sound.

[0089] The display panel (10) may be a light-emitting display panel including a light-emitting diode. The light-emitting diode may include an organic light-emitting diode (OLED) including an organic light-emitting layer. In some embodiments, the light-emitting diode may be an inorganic light-emitting diode including an inorganic material. The inorganic light-emitting diode may include a PN diode including inorganic semiconductor-based materials. When a voltage is applied in the forward direction to the PN junction diode, holes and electrons are injected, and energy generated by the recombination of the holes and electrons is converted into light energy to emit light of a predetermined color. The above-described inorganic light-emitting diode may have a width of several to several hundred micrometers, and in some embodiments, the inorganic light-emitting diode may be referred to as a micro LED.

[0090] The display panel (10) may include a rigid display panel that is rigid and does not bend easily, or a flexible display panel that is flexible and can be bent, folded, or rolled easily to a noticeable degree, but does not cause cracks or other damage. For example, the display panel (10) may be a foldable display panel that can be folded and unfolded, a curved display panel with a curved display surface, a bent display panel with an area other than the display surface bent, a rollable display panel that can be rolled and unfolded, and a stretchable display panel that can be stretched.

[0091] The display panel (10) may be a transparent display panel that is implemented transparently so that an object or background placed on the lower surface of the display panel (10) can be viewed from the upper surface of the display panel (10). Alternatively, the display panel (10) may be a reflective display panel that can reflect an object or background on the upper surface of the display panel (10).

[0092] The data driver (20) may be placed on the display panel (10) in the form of an integrated circuit (IC). As another embodiment, the data driver (20) may be placed on a display circuit board (30).

[0093] A display circuit board (30) can be attached to one side of the display panel (10). The display circuit board (30) can be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that is hard and does not bend easily, or a composite printed circuit board including both a rigid printed circuit board and a flexible printed circuit board.

[0094] In one embodiment, a touch sensor driver may be disposed on a display circuit board (30). The touch sensor driver may be formed as an integrated circuit. The touch sensor driver may be attached to the display circuit board (30). The touch sensor driver may be electrically connected to touch electrodes of a touch screen layer of a display panel (10) via the display circuit board (30).

[0095] The touch screen layer of the display panel (10) can detect a user's touch input using at least one of various touch methods such as a resistive film method and an electrostatic capacitance method. For example, when the touch screen layer of the display panel (10) detects a user's touch input using an electrostatic capacitance method, the touch sensor driver can determine whether a user's touch has occurred by applying drive signals to the drive electrodes among the touch electrodes and detecting voltages charged in the mutual capacitance (hereinafter referred to as "mutual capacitance") between the drive electrodes and the sense electrodes through the sense electrodes among the touch electrodes. The user's touch may include a contact touch and a proximity touch. A contact touch refers to a case where an object such as a user's finger or a pen directly contacts a cover window (70) disposed on the touch screen layer. A proximity touch refers to a case where an object such as a user's finger or a pen is positioned close to the cover window (70), such as hovering. The touch sensor driving unit transmits sensor data to the main processor (510) according to the detected voltages, and the main processor (510) can calculate the touch coordinates where the touch input occurred by analyzing the sensor data.

[0096] A control unit for supplying driving voltages for driving pixels, a gate driver, and a data driver (20) of the display panel (10) may be placed on the display circuit board (30).

[0097] A bracket (60) for supporting the display panel (10) may be arranged at the bottom of the display panel (10). The bracket (60) may include plastic, metal, or both plastic and metal. A first camera hole (CMH1) into which a camera device (531) is inserted, a battery hole (BH) into which a battery (80) is arranged, and a cable hole (CAH) through which a cable connected to the display circuit board (30) passes may be formed in the bracket (60). A component hole (CPH) overlapping the display panel (10) may be provided in the bracket (60). The component hole (CPH) may overlap with components (40) of the main circuit board (50) in a third direction (z direction). In one embodiment, the display area (DA) of the display panel (10) may overlap with components (40) of the main circuit board (50) in the third direction (z direction). In another embodiment, the bracket (60) may not have a component hole (CPH) formed therein.

[0098] In one embodiment, the component (40) may include first to fourth components (41, 42, 43, 44) that overlap the display panel (10). The first to fourth components (41, 42, 43, 44) may be provided with a proximity sensor, an illuminance sensor, an iris sensor, a facial recognition sensor, and a camera (or an image sensor), respectively. The proximity sensor using infrared rays can detect an object placed close to the upper surface of the electronic device (1), and the illuminance sensor can detect the brightness of light incident on the upper surface of the electronic device (1). In addition, the iris sensor can photograph the iris of a person placed on the upper surface of the electronic device (1), and the camera can photograph an object placed on the upper surface of the electronic device (1). The component (40) is not limited to the proximity sensor, the illuminance sensor, the iris sensor, the facial recognition sensor, and the camera, and various sensors described below may be placed.

[0099] A main circuit board (50) and a battery (80) may be placed at the bottom of the bracket (60). The main circuit board (50) may be a printed circuit board or a flexible printed circuit board.

[0100] The main circuit board (50) may include a main processor (510), a camera device (531), a main connector (55), and components (40). The main processor (510) may be formed as an integrated circuit. The camera device (531) may be disposed on both the upper and lower surfaces of the main circuit board (50), and each of the main processor (510) and the main connector (55) may be disposed on either the upper or lower surface of the main circuit board (50).

[0101] The main processor (510) can control all functions of the electronic device (1). For example, the main processor (510) can output digital video data to the data driver (20) through the display circuit board (30) so that the display panel (10) can display an image. The main processor (510) can receive detection data from the touch sensor driver. The main processor (510) can determine whether a user touches the screen based on the detection data and execute an operation corresponding to the user's direct touch or proximity touch. The main processor (510) can be an application processor, a central processing unit, or a system chip formed of an integrated circuit.

[0102] The camera device (531) processes image frames, such as still images or moving images, obtained by the image sensor in camera mode and outputs them to the main processor (510). The camera device (531) may include at least one of a camera sensor (e.g., CCD, CMOS, etc.), a photo sensor (or image sensor), and a laser sensor. The camera device (531) may be connected to an image sensor among components (40) overlapping the display area (DA) and may process images input to the image sensor.

[0103] A cable (35) passing through a cable hole (CAH) of a bracket (60) can be connected to the main connector (55), and thus the main circuit board (50) can be electrically connected to the display circuit board (30).

[0104] In addition to the main processor (510), camera device (531), and main connector (55), the main circuit board (50) may further include a wireless communication unit (520), an input unit (530), a sensor unit (540), an output unit (550), an interface unit (560), a memory (570), and / or a power supply unit (580) as shown in FIG. 3.

[0105] The wireless communication unit (520) may include at least one of a broadcast reception module (521), a mobile communication module (522), a wireless Internet module (523), a short-range communication module (524), and a location information module (525).

[0106] The broadcast reception module (521) receives broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include a satellite channel or a terrestrial channel.

[0107] The mobile communication module (522) transmits and receives wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network constructed according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc.). The wireless signal may include various types of data according to voice call signals, video call call signals, or text / multimedia message transmission and reception.

[0108] The wireless Internet module (523) refers to a module for wireless Internet access. The wireless Internet module (523) can be configured to transmit and receive wireless signals in a communication network according to wireless Internet technologies. Wireless Internet technologies include, for example, WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, and DLNA (Digital Living Network Alliance).

[0109] The short-range communication module (524) is for short-range communication, and can support short-range communication using at least one of Bluetooth, RFID (Radio Frequency Identification), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee, NFC (Near Field Communication), Wi-Fi (Wireless-Fidelity), Wi-Fi Direct, and Wireless USB (Wireless Universal Serial Bus) technologies. The short-range communication module (524) can support wireless communication between an electronic device (1) and a wireless communication system, between an electronic device (1) and another electronic device, or between an electronic device (1) and a network where another electronic device (or an external server) is located through a short-range wireless communication network (Wireless Area Network). The short-range wireless communication network may be a short-range wireless personal area network (Wireless Personal Area Network). The other electronic device may be a wearable device capable of exchanging (or linking) data with the electronic device (1).

[0110] The location information module (525) is a module for obtaining the location (or current location) of the electronic device (1), and may include a GPS (Global Positioning System) module or a WiFi (Wireless Fidelity) module.

[0111] The input unit (530) may include a video input unit such as a camera device (531) for inputting a video signal, an audio input unit such as a microphone (532) for inputting an audio signal, and an input device (533) for receiving information from a user.

[0112] The camera device (531) processes image frames, such as still images or moving images, obtained by an image sensor in video call mode or shooting mode. The processed image frames can be displayed on a display panel (10) or stored in a memory (570).

[0113] A microphone (532) processes external acoustic signals into electrical voice data. The processed voice data can be utilized in various ways depending on the function being performed (or the application being executed) by the electronic device (1).

[0114] The main processor (510) can control the operation of the electronic device (1) to correspond to information input through the input device (533). The input device (533) can include a mechanical input means or a touch input means, such as a button, a dome switch, a jog wheel, a jog switch, etc., located on the rear or side of the electronic device (1). The touch input means can be formed of a touch screen layer of the display panel (10).

[0115] The sensor unit (540) may include one or more sensors that sense at least one of information within the electronic device (1), information about the surrounding environment surrounding the electronic device (1), and user information, and generate a sensing signal corresponding thereto. Based on these sensing signals, the main processor (510) may control the operation or behavior of the electronic device (1), or perform data processing, functions, or operations related to an application installed in the electronic device (1). The sensor unit (540) may include at least one of a proximity sensor, an illumination sensor, an acceleration sensor, a magnetic sensor, a G-sensor, a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor (IR sensor), a fingerprint recognition sensor, an ultrasonic sensor, an optical sensor, a battery gauge, an environmental sensor (e.g., a barometer, a hygrometer, a thermometer, a radiation detection sensor, a heat detection sensor, a gas detection sensor, etc.), and a chemical sensor (e.g., an electronic nose, a healthcare sensor, a biometric recognition sensor, etc.).

[0116] The output unit (550) is for generating output related to visual, auditory, or tactile sensations, and may include at least one of a display panel (10), an audio output unit (551), a haptic module (552), and an optical output unit (553).

[0117] The display panel (10) displays (outputs) information processed in the electronic device (1). For example, the display panel (10) may display execution screen information of an application running in the electronic device (1), or UI (User Interface) or GUI (Graphical User Interface) information according to the execution screen information. The display panel (10) may include a display layer that displays an image and a touch screen layer that detects a user's touch input. Accordingly, the display panel (10) may function as one of the input devices (533) that provides an input interface between the electronic device (1) and the user, and at the same time, function as one of the output units (550) that provides an output interface between the electronic device (1) and the user.

[0118] The audio output unit (551) can output audio data received from the wireless communication unit (520) or stored in the memory (570) in a call signal reception mode, a call mode or a recording mode, a voice recognition mode, a broadcast reception mode, etc. The audio output unit (551) also outputs audio signals related to functions performed in the electronic device (1) (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit (551) may include a receiver and a speaker. At least one of the receiver and the speaker may be a sound generating device attached to the lower portion of the display panel (10) to vibrate the display panel (10) and output audio. The audio generating device may be a piezoelectric element or piezoelectric actuator that contracts and expands according to an electric signal, or an exciter that generates magnetic force using a voice coil to vibrate the display panel (10).

[0119] The haptic module (552) generates various tactile effects that can be felt by the user. The haptic module (552) can provide vibrations to the user as tactile effects. The haptic module (552) can not only deliver tactile effects through direct contact, but can also be implemented so that the user can feel the tactile effects through the kinesthetic senses of the fingers or arms.

[0120] The light output unit (553) outputs a signal to notify the occurrence of an event using light from a light source. Examples of events occurring in the electronic device (1) may include receiving a message, receiving a call signal, receiving a missed call, an alarm, receiving a schedule reminder, receiving an email, receiving information through an application, etc. The signal output by the light output unit (553) is implemented by the electronic device (1) emitting light of a single color or multiple colors from the front or rear. The signal output may be terminated when the electronic device (1) detects the user's confirmation of an event.

[0121] The interface unit (560) serves as a passageway for various types of external devices connected to the electronic device (1). The interface unit (560) may include at least one of a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio I / O (Input / Output) port, a video I / O (Input / Output) port, and an earphone port. The electronic device (1) may perform appropriate control related to the connected external device in response to the external device being connected to the interface unit (560).

[0122] The memory (570) stores data that supports various functions of the electronic device (1). The memory (570) can store a plurality of applications (application programs) running on the electronic device (1), data for the operation of the electronic device (1), and commands. At least some of the plurality of applications can be downloaded from an external server via wireless communication. The memory (570) can store applications for the operation of the main processor (510), and can also temporarily store input / output data, such as phone books, messages, still images, and moving images. In addition, the memory (570) can store haptic data for various patterns of vibration provided to the haptic module (552) and audio data regarding various sounds provided to the audio output unit (551). The memory (570) may include at least one type of storage medium among a flash memory type, a hard disk type, an SSD (Solid State Disk type), an SDD (Silicon Disk Drive type), a multimedia card micro type, a card type memory (e.g., SD or XD memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, and an optical disk.

[0123] The power supply unit (580) receives external power and internal power under the control of the main processor (510) and supplies power to each component included in the electronic device (1). The power supply unit (580) may include a battery (80). In addition, the power supply unit (580) is provided with a connection port, and the connection port may be configured as an example of an interface unit (560) to which an external charger that supplies power for charging the battery is electrically connected. Alternatively, the power supply unit (580) may be configured to charge the battery (80) wirelessly without using the connection port. The battery (80) may be arranged so as not to overlap the main circuit board (50) in the third direction (z direction). The battery (80) may overlap the battery hole (BH) of the bracket (60).

[0124] The lower cover (90) can be placed under the main circuit board (50) and the battery (80). The lower cover (90) can be fixed by being connected to the bracket (60). The lower cover (90) can form the lower exterior of the electronic device (1). The lower cover (90) can include plastic, metal, or both plastic and metal.

[0125] A second camera hole (CMH2) exposing the lower surface of the camera device (531) may be formed in the lower cover (90). The position of the camera device (531) and the positions of the first and second camera holes (CMH1, CMH2) corresponding to the camera device (531) are not necessarily limited to the embodiments illustrated in FIGS. 1 and 2 and may be varied in various ways.

[0126] FIG. 4 is a plan view schematically illustrating a display panel (10) according to one embodiment of the present invention, and FIG. 5 is a side view schematically illustrating a display panel (10) according to one embodiment of the present invention.

[0127] The display panel (10) may include a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) is a portion for displaying an image, and a plurality of pixels may be arranged. The display area (DA) may have various shapes, such as a circle, an oval, a polygon, or a shape of a specific shape. For example, FIG. 4 illustrates that the display area (DA) has a roughly rectangular shape with rounded corners.

[0128] A peripheral area (PA) may be arranged outside the display area (DA). The peripheral area (PA) may include a first peripheral area (PA1) arranged to surround at least a portion of the display area (DA) and a second peripheral area (PA2) adjacent to one side of the display area (DA) and extending in a second direction (e.g., -y direction). A width of the second peripheral area (PA2) along the first direction (e.g., x-axis direction) may be narrower than a width of the display area (DA). This structure may facilitate bending of at least a portion of the second peripheral area (PA2).

[0129] The shape of the plane of the display panel (10) illustrated in FIG. 4 may be substantially the same as the shape of the substrate (100) included in the display panel (10). When the display panel (10) is said to include a display area (DA) and a peripheral area (PA) outside the display area (DA), this may indicate that the substrate (100) includes the display area (DA) and a peripheral area (PA) outside the display area (DA). Hereinafter, for convenience, it will be described that the substrate (100) has a display area (DA) and a peripheral area (PA).

[0130] The display panel (10) may include a main region (MR), a bending region (BR) outside the main region (MR), and a sub-region (SR) spaced apart from the main region (MR) with the bending region (BR) therebetween. The main region (MR) may be arranged on one side of the bending region (BR), and the sub-region (SR) may be arranged on the other side of the bending region (BR). The display panel (10) may be bent in the bending region (BR), as illustrated in FIG. 5, and at least a portion of the sub-region (SR) may overlap the main region (MR) when viewed in a third direction (e.g., the z-direction). Although FIG. 5 illustrates the display panel (10) being bent, the present invention is not limited thereto. In another embodiment, the display panel (10) may be a foldable display panel, and the display region (DA) may be bent around a bending axis crossing the display region (DA). In yet another embodiment, the display panel (10) may not be bent. The sub-region (SR) may be a non-display area.

[0131] A data driver (20) may be placed in a sub-region (SR) of a display panel (10). The data driver (20) may be placed in the display panel (10) in the form of an integrated circuit (IC). For example, the data driver (20) may be a data driving integrated circuit that generates a data signal.

[0132] A display circuit board (30) may be attached to an end of a sub-area (SR) of a display panel (10). The display circuit board (30) may be electrically connected to a data driver (20) or the like through a pad of the sub-area (SR) of the display panel (10).

[0133] Figure 6 is a plan view schematically showing a display panel (10) according to one embodiment of the present invention.

[0134] Referring to FIG. 6, the display panel (10) may include a substrate (100). Various components constituting the display panel (10) may be arranged on the substrate (100).

[0135] The substrate (100) may include glass, metal, or a polymer resin. The substrate (100) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate (100) may have a multilayer structure including two layers including the aforementioned polymer resin and an inorganic layer interposed between the layers.

[0136] Pixels are arranged in a display area (DA), and the display area (DA) can provide an image using light emitted from the pixels. Each pixel can include a light-emitting diode (LED), and the light-emitting diode (LED) can be electrically connected to a pixel circuit (PC). The pixel circuit (PC) and the light-emitting diode (LED) can be arranged in the display area (DA).

[0137] A gate driving circuit (e.g., a first scan driving circuit (11), a second scan driving circuit (12), a light emission control driving circuit (13), a pad (14), a first power supply line (15), and a second power supply line (16)) may be arranged in the peripheral area (PA).

[0138] The first scan driving circuit (11) can provide a scan signal to the pixel circuit (PC) through the gate line (SL). The second scan driving circuit (12) can be arranged on the opposite side of the first scan driving circuit (11) with the display area (DA) therebetween. Some of the pixel circuits (PC) arranged in the display area (DA) can be electrically connected to the first scan driving circuit (11), and the rest can be connected to the second scan driving circuit (12). In another embodiment, the second scan driving circuit (12) can be omitted.

[0139] The light emission control driving circuit (13) is arranged on the side of the first scan driving circuit (11) and can provide a light emission control signal to the pixel (P) through the light emission control line (EL). In Fig. 6, the light emission control driving circuit (13) is illustrated as being arranged only on one side of the display area (DA), but the present invention is not limited thereto. In another embodiment, the light emission control driving circuits (13) may be arranged on both sides of the display area (DA).

[0140] The pad (14) may be placed in the second peripheral area (PA2) of the substrate (100). The pad (14) may be exposed without being covered by an insulating layer and may be electrically connected to the display circuit board (30). The pad (34) of the display circuit board (30) may be electrically connected to the pad (14) of the display panel (10).

[0141] The display circuit board (30) transmits a signal or power of the control unit to the display panel (10). The control signal generated by the control unit can be transmitted to the gate driving circuit through the display circuit board (30), respectively. In addition, the control unit can provide a driving voltage and a common voltage to the first and second power supply lines (15, 16), respectively. The driving voltage is provided to each pixel circuit (PC) through a driving voltage line (PL) connected to the first power supply line (15), and the common voltage can be provided to the opposite electrode of a light emitting diode (LED) connected to the second power supply line (16). The first power supply line (15) can extend in a first direction (e.g., x direction). The second power supply line (16) has a loop shape with one end open, so as to partially surround the display area (DA).

[0142] The data signal of the data driver (20) can be transmitted to the pixel circuit (PC) through the data line (DL) electrically connected to the input line (IL) via the input line (IL).

[0143] Fig. 7 is a plan view schematically illustrating pixel circuits of a display panel according to one embodiment of the present invention. For convenience of explanation, Fig. 7 illustrates three pixel circuits, for example, a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3), arranged in the same row along a first direction (e.g., x-direction), but the present invention is not limited thereto. The display panel (10) includes a plurality of pixel circuits arranged to form rows in the first direction (e.g., x-direction) and columns in the second direction (e.g., y-direction).

[0144] Referring to FIG. 7, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include transistors and capacitors. In one embodiment, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include first to seventh transistors (T1, T2, T3, T4, T5, T6, T7), a storage capacitor (Cst), and a hold capacitor (Chd). At this time, the first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal, and the second to seventh transistors (T2, T3, T4, T5, T7) may be switching transistors that transmit signals.

[0145] In one embodiment, at least one of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may be a p-channel MOSFET (PMOS), and the others may be n-channel MOSFETs (NMOS). For example, the fifth transistor (T5) may be a PMOS, and the first, second, third, fourth, sixth, and seventh transistors (T1, T2, T3, T4 T6, T7) may be NMOS. In another embodiment, the fifth transistor (T5) and the sixth transistor (T6) may be PMOS, and the first, second, third, and fourth transistors (T1, T2, T3, T4) may be NMOS. Alternatively, the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may all be NMOS or all may be PMOS. Hereinafter, an embodiment will be described in which the fifth transistor (T5) is a PMOS (p-channel MOSFET) including a silicon semiconductor, and the first, second, third, fourth, sixth, and T7 transistors (T1, T2, T3, T4, T6, and T7) are NMOS (n-channel MOSFETs) including an oxide semiconductor.

[0146] At least one of the plurality of transistors (T1, T2, T3, T4, T5, T6, T7) may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of the plurality of transistors (T1, T2, T3, T4, T5, T6, T7) may be a transistor having an oxide semiconductor layer. For example, the fifth transistor (T5) may include a semiconductor layer made of polycrystalline silicon having high reliability, and the first, second, third, fourth, sixth, and seventh transistors (T1, T2, T3, T4, T6, T7) may include an oxide semiconductor layer having high carrier mobility and low leakage current.

[0147] The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be electrically connected to gate lines that transmit signals to the gates of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7), respectively. For example, the pixel circuit (PC) may be connected to a scan line (GWL) that transmits a scan signal, an initialization gate line (GBL) that transmits an initialization signal, a reference gate line (GRL) that transmits a reference signal, a first emission control line (EML) that transmits a first emission control signal, a second emission control line (EMBL) that transmits a second emission control signal, a hold gate line (GHL) that transmits a hold signal, and a data line (DL) that transmits a data signal. Additionally, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) can be connected to a driving voltage line (PL) that transmits a driving voltage, a reference voltage line (VRL) that transmits a reference voltage, and an initialization voltage line (VL) that transmits an initialization voltage.

[0148] Specifically, the first transistor (T1) may be electrically connected between a driving voltage line (PL) and a light emitting diode (LED, FIG. 6). The first transistor (T1) may include a gate electrode connected to a first node electrode (N1) connected to a second transistor (T2) and a third transistor (T3). The first transistor (T1) may include a first terminal connected to the driving voltage line (PL) and a second terminal connected to a second node electrode (N2) connected to a sixth transistor (T6). The first transistor (T1) may have a dual gate structure. In addition to the gate electrode connected to the first node electrode (N1), the first transistor (T1) may further include a lower gate electrode overlapping a channel region of the first transistor (T1). The lower gate electrode may be connected to the second node electrode (N2) and a hold capacitor (Chd).

[0149] A first terminal of a first transistor (T1) is connected to a driving voltage line (PL) via a fifth transistor (T5), and a second terminal of the first transistor (T1) can be connected to a pixel electrode of a light-emitting diode (LED, Fig. 6). The first transistor (T1) can receive a data signal according to a switching operation of the second transistor (T2) and control the amount of driving current flowing to the light-emitting diode (LED, Fig. 6).

[0150] The second transistor (T2) may be electrically connected between the data line (DL) and the first node electrode (N1). The second transistor (T2) may include a gate connected to the scan line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node electrode (N1). The second transistor (T2) may be turned on by a scan signal transmitted to the scan line (GWL) to electrically connect the data line (DL) and the first node electrode (N1), and may transmit a data signal transmitted to the data line (DL) to the first node electrode (N1).

[0151] A third transistor (T3) may be electrically connected between a first node electrode (N1) and a reference voltage line (VRL). The third transistor (T3) may include a gate connected to the reference gate line (GRL), a first terminal connected to the first node electrode (N1), and a second terminal connected to the reference voltage line (VRL). The third transistor (T3) may be turned on by a reference signal transmitted to the reference gate line (GRL) and may transmit a reference voltage transmitted to the reference voltage line (VRL) to the first node electrode (N1).

[0152] The fourth transistor (T4) may be electrically connected between the first transistor (T1) and the initialization voltage line (VL). The fourth transistor (T4) may include a gate connected to the initialization gate line (GIL), a first terminal connected to the sixth transistor (T6), and a second terminal connected to the initialization voltage line (VL). The fourth transistor (T4) may be turned on by an initialization signal transmitted to the initialization gate line (GIL) and may transmit the initialization voltage transmitted to the initialization voltage line (VL) to a pixel electrode of a light emitting diode (LED, FIG. 6).

[0153] The fifth transistor (T5) may be electrically connected between the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate connected to the first emission control line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first transistor (T1). The fifth transistor (T5) may be turned on or off according to the first emission control signal transmitted to the first emission control line (EML).

[0154] The sixth transistor (T6) may be connected between the first transistor (T1) and a light emitting diode (LED, FIG. 6). The sixth transistor (T6) may include a gate connected to a second light emitting control line (EMBL), a first terminal connected to a second node electrode (N2), and a second terminal connected to the light emitting diode (LED, FIG. 6). The sixth transistor (T6) may be turned on by a second light emitting control signal transmitted to the second light emitting control line (EMBL) to connect the second node electrode (N2) and the pixel electrode of the light emitting diode (LED, FIG. 6) to each other.

[0155] Although Fig. 7 illustrates that the fifth transistor (T5) and the sixth transistor (T6) operate in response to different light emission control signals, the present invention is not limited thereto. In another embodiment, the fifth transistor (T5) and the sixth transistor (T6) may operate in response to the same light emission control signal.

[0156] A seventh transistor (T7) may be electrically connected between a hold capacitor (Chd) and a reference voltage line (VRL). The seventh transistor (T7) may include a gate connected to a hold gate line (GHL), a first terminal connected to the hold capacitor (Chd), and a second terminal connected to the reference voltage line (VRL). The seventh transistor (T7) may be turned on or off according to a hold signal transmitted to the hold gate line (GHL), thereby controlling the hold capacitor (Chd).

[0157] The storage capacitor (Cst) may be connected between the first node electrode (N1) and the second node electrode (N2). In other words, the pixel circuit (PC) according to an embodiment of the present invention may be a source follower type circuit in which the storage capacitor (Cst) is connected between the first node electrode (N1) and the second node electrode (N2). The storage capacitor (Cst) may include a first storage electrode and a second storage electrode that face each other. The first storage electrode may be connected to the first node electrode (N1), and the second storage electrode may be connected to the second node electrode (N2). The storage capacitor (Cst) may store a voltage corresponding to a threshold voltage of the first transistor (T1) and a data signal.

[0158] A hold capacitor (Chd) may be connected between the seventh transistor (T7) and the second node electrode (N2). The hold capacitor (Chd) may include a first hold electrode and a second hold electrode that are opposite to each other. The first hold electrode may be connected to the seventh transistor (T7), and the second hold electrode may be connected to the second node electrode (N2). The hold capacitor (Chd) allows the voltage of the lower gate electrode of the first transistor (T1) and the second node electrode (N2) to remain constant and not fluctuate even when a peripheral signal fluctuates.

[0159] Referring to FIG. 7, the transistors and capacitors of the first pixel circuit (PC1) may be arranged symmetrically with the transistors and capacitors of the second pixel circuit (PC2), respectively. For example, the first transistor (T1) of the first pixel circuit (PC1) may be symmetrical with the first transistor (T1) of the second pixel circuit (PC2) with respect to an imaginary line (IML1) passing between the first pixel circuit (PC1) and the second pixel circuit (PC2) along the second direction (e.g., the y direction). Similarly, the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the first pixel circuit (PC1) may be symmetrical with respect to the imaginary line (IML1) with respect to the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the second pixel circuit (PC2), respectively.

[0160] Similarly, the transistors and capacitors of the second pixel circuit (PC2) may be arranged symmetrically with the transistors and capacitors of the third pixel circuit (PC3), respectively. For example, the first transistor (T1) of the second pixel circuit (PC2) may be symmetrical with the first transistor (T1) of the third pixel circuit (PC3) with respect to an imaginary line (IML2) passing between the second pixel circuit (PC2) and the third pixel circuit (PC3) along the second direction (e.g., the y direction). Similarly, the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the second pixel circuit (PC2) may be symmetrical with respect to the imaginary line (IML2) with respect to the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the third pixel circuit (PC3), respectively.

[0161] Gate lines electrically connected to the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3), such as a scan line (GWL), an initialization gate line (GIL), a reference gate line (GRL), a first emission control line (EML), a second emission control line (EMBL), and a hold gate line (GHL), can extend in a first direction (e.g., an x-direction).

[0162] The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be electrically connected to a data line (DL) passing through each pixel circuit (PC). For example, the first pixel circuit (PC1) may be electrically connected to a first data line (DL1) passing through the first pixel circuit (PC1), the second pixel circuit (PC2) may be electrically connected to a second data line (DL2) passing through the second pixel circuit (PC2), and the third pixel circuit (PC3) may be connected to a third data line (DL3) passing through the third pixel circuit (PC3). The data line (DL) may extend along a second direction (e.g., a y direction). With respect to the first direction (e.g., x-direction), the first data line (DL1) may be arranged to the left of the first transistor (T1) within the first pixel circuit (PC1), the second data line (DL2) may be arranged to the right of the first transistor (T1) within the second pixel circuit (PC2), and the third data line (DL3) may be arranged to the left of the first transistor (T1) within the third pixel circuit (PC3). In other words, the first data line (DL1) and the second data line (DL2) may be arranged far apart with respect to an imaginary line (IML1), and the second data line (DL2) and the third data line (DL3) may be arranged adjacent with respect to an imaginary straight line (IML2).

[0163] The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be electrically connected to voltage lines passing through the respective pixel circuits (PC). For example, the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be electrically connected to a reference voltage line (VRL), an initialization voltage line (VL), a driving voltage line (PL), and a common voltage line (VSL), respectively. The reference voltage line (VRL) may include a horizontal reference voltage line (HVRL) extending along a first direction (e.g., an x-direction) and a vertical reference voltage line (VVRL) extending along a second direction (e.g., a y-direction). The horizontal reference voltage line (HVRL) and the vertical reference voltage line (VVRL) may be electrically connected to each other in an intersecting region. In one embodiment, the vertical reference voltage line (VVRL) may be disposed on an region where the third pixel circuit (PC3) is disposed.

[0164] The initialization voltage line (VL) may include a horizontal initialization voltage line (HVL) extending along a first direction (e.g., x-direction) and a vertical initialization voltage line (VVL) extending along a second direction (e.g., y-direction). The horizontal initialization voltage line (HVL) and the vertical initialization voltage line (VVL) may be electrically connected to each other in an intersecting region. In one embodiment, the vertical initialization voltage line (VVL) may be arranged on a boundary between the first pixel circuit (PC1) and the second pixel circuit (PC2). For example, the vertical initialization voltage line (VVL) may be arranged on the aforementioned virtual line (IML1), such that some of the vertical initialization voltage line (VVL) may be arranged on an area where the first pixel circuit (PC1) is arranged, and other parts of the vertical initialization voltage line (VVL) may be arranged on an area where the second pixel circuit (PC2) is arranged. Meanwhile, the horizontal initialization voltage line (HVL) may include a plurality of wires. For example, the horizontal initialization voltage line (HVL) may include a first horizontal initialization voltage line (HVL1) that transmits an initialization voltage to a first pixel circuit (PC1), a second horizontal initialization voltage line (HVL2) that transmits an initialization voltage to a second pixel circuit (PC2), and a third horizontal initialization voltage line (HVL3) that transmits an initialization voltage to a third pixel circuit (PC3).

[0165] The driving voltage line (PL) may include a horizontal driving voltage line (HPL) extending along a first direction (e.g., x direction) and a vertical driving voltage line (VPL) extending along a second direction (e.g., y direction). In one embodiment, the vertical driving voltage line (VPL) may be respectively disposed on an area where the first pixel circuit (PC1) is disposed and an area where the second pixel circuit (PC2) is disposed. The driving voltage line (PL) disposed on the first pixel circuit (PC1) and the driving voltage line (PL) disposed on the second pixel circuit (PC2) may be symmetrical with respect to the aforementioned virtual line (IML1).

[0166] A common voltage line (VSL) can extend along a first direction (e.g., x-direction) and pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The common voltage line (VSL) is a wire arranged in a display area (DA, Fig. 6) and can be electrically connected to a second power supply wire (16, Fig. 6) arranged in a peripheral area (PA) to transmit a common voltage.

[0167] FIG. 8 is a cross-sectional view of a display panel according to one embodiment of the present invention, showing a cross-section taken along line Ⅷ-Ⅷ' of FIG. 6.

[0168] Referring to FIG. 8, the display panel (10) may include a circuit layer including transistors and capacitors disposed on a substrate (100), and a display element layer disposed on the aforementioned circuit layer and including a light-emitting diode (LED). The circuit layer may include the transistors and capacitors described above with reference to FIG. 7, and FIG. 8 illustrates a first transistor (T1), a fifth transistor (T5), a seventh transistor (T7), and a hold capacitor (Chd).

[0169] The substrate (100) may include a glass material, a ceramic material, a metal material, a plastic material, or a material having flexible or bendable properties. When the substrate (100) has flexible or bendable properties, the substrate (100) may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyether imide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, and cellulose acetate propionate (CAP).

[0170] The substrate (100) may have a single-layer or multi-layer structure of the above material, and in the case of a multi-layer structure, may further include an inorganic layer. For example, the substrate (100) may have a structure in which a layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material are alternately laminated.

[0171] A buffer layer (101) may be disposed on a substrate (100). The buffer layer (101) may be an inorganic insulating layer including an inorganic insulating material such as silicon nitride and / or silicon oxide, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0172] A transistor including a silicon semiconductor layer may be arranged on the buffer layer (101). In this regard, FIG. 8 illustrates a fifth semiconductor layer (A5) of a fifth transistor (T5). The fifth semiconductor layer (A5) may include polysilicon. The fifth semiconductor layer (A5) may include a channel region (C5) and impurity regions (S5, D5) doped with impurities and arranged on both sides of the channel region (C5). One of the impurity regions (S5, D5) of the fifth semiconductor layer (A5) may be a source and the other may be a drain.

[0173] In some embodiments, a lower metal layer may be added between the buffer layer (101) and the silicon semiconductor layer. The lower metal layer may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The lower metal layer may have a voltage level of a constant voltage. For example, the lower metal layer may be electrically connected to the first power supply wiring (15, FIG. 6) at the periphery of the display area (DA, FIG. 6).

[0174] The first gate insulating layer (103) may be disposed on the fifth semiconductor layer (A5). The first gate insulating layer (103) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0175] The fifth gate electrode (G5) is disposed on the first gate insulating layer (103) and may overlap the channel region (C5) of the fifth semiconductor layer (A5). A first hold electrode (CEh1) of a hold capacitor (Chd) may be disposed on the same layer as the fifth gate electrode (G5), for example, on the first gate insulating layer (103).

[0176] The fifth gate electrode (G5) and the first hold electrode (CEh1) of the hold capacitor (Chd) may include the same material. The fifth gate electrode (G5) and the first hold electrode (CEh1) of the hold capacitor (Chd) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. In one embodiment, the fifth gate electrode (G5) and the first hold electrode (CEh1) of the hold capacitor (Chd) may be a single layer including molybdenum.

[0177] The second gate insulating layer (105) may be disposed on the fifth gate electrode (G5) and the first hold electrode (CEh1) of the hold capacitor (Chd). The second gate insulating layer (105) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the second gate insulating layer (105) may include a different material from the first gate insulating layer (103). For example, the first gate insulating layer (103) may include silicon oxide, and the second gate insulating layer (105) may include silicon nitride.

[0178] The second hold electrode (CEh2) of the hold capacitor (Chd) may be disposed on the second gate insulating layer (105). The second hold electrode (CEh2) may overlap the first hold electrode (CEh1) of the hold capacitor (Chd). The second hold electrode (CEh2) of the hold capacitor (Chd) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. In one embodiment, the second hold electrode (CEh2) may be a single layer including molybdenum.

[0179] The third gate insulating layer (107) may be disposed on the second hold electrode (CEh2). The third gate insulating layer (107) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0180] A first lower gate electrode (G1b) of a first transistor (T1) may be disposed on the third gate insulating layer (107). As described above, the first transistor (T1) may have a dual gate structure and may include a first gate electrode (G1a) and a first lower gate electrode (G1b) overlapping a channel region of the first transistor (T1). The first lower gate electrode (G1b) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0181] A first interlayer insulating layer (109) may be disposed on the first lower gate electrode (G1b). The first interlayer insulating layer (109) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. For example, the first interlayer insulating layer (109) may have a stacked structure of a layer including silicon oxide and a layer including silicon nitride.

[0182] The first semiconductor layer (A1) of the first transistor (T1) and the seventh semiconductor layer (A7) of the seventh transistor (T7) may be disposed on the first interlayer insulating layer (109) and may include the same material. The first semiconductor layer (A1) of the first transistor (T1) and the seventh semiconductor layer (A7) of the seventh transistor (T7) may include an oxide semiconductor, and the oxide semiconductor may be an oxide semiconductor including at least one element selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor may include ITZO (InSnZnO) or IGZO (InGaZnO).

[0183] The first semiconductor layer (A1) may include a channel region (C1) and conductive regions (S1, D1) arranged on both sides of the channel region (C1). One of the conductive regions (S1, D1) may be a source and the other may be a drain. Similarly, the seventh semiconductor layer (A7) may include a channel region (C7) and conductive regions (S7, D7) arranged on both sides of the channel region (C7). One of the conductive regions (S7, D7) may be a source and the other may be a drain.

[0184] The first semiconductor layer (A1) and the seventh semiconductor layer (A7) may be arranged on different layers from the fifth semiconductor layer (A5) described above. The vertical distance from the substrate (100) to the first semiconductor layer (A1) may be greater than the vertical distance from the substrate (100) to the fifth semiconductor layer (A5).

[0185] The fourth gate insulating layer (111) may be disposed on the first semiconductor layer (A1) and the seventh semiconductor layer (A7). The fourth gate insulating layer (111) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the fourth gate insulating layer (111) may be a single-layer including silicon oxide.

[0186] FIG. 8 illustrates that the fourth gate insulating layer (111) passes through the side surface of the first semiconductor layer (A1) and contacts the upper surface of the first interlayer insulating layer (109), but the present invention is not limited thereto. In another embodiment, the fourth gate insulating layer (111) may be formed to have substantially the same pattern and / or the same width as the first gate electrode (G1a) and the seventh gate electrode (G7) described later. Alternatively, in another embodiment, the fourth gate insulating layer (111) may be formed to have a larger pattern and / or a larger width than the first gate electrode (G1a) described later, and may be formed to have a smaller pattern and / or a smaller width than the first semiconductor layer (A1). Similarly, the fourth gate insulating layer (111) may be formed to have a larger pattern and / or a larger width than the seventh gate electrode (G7) described later, and may be formed to have a smaller pattern and / or a smaller width than the seventh semiconductor layer (A7). In other words, the fourth gate insulating layer (111) may not come into contact with the upper surface of the first interlayer insulating layer (109) beyond the side surface of the first semiconductor layer (A1).

[0187] The first gate electrode (G1a) and the seventh gate electrode (G7) may be disposed on the fourth gate insulating layer (111). The first gate electrode (G1a) may overlap with the channel region (C1) of the first semiconductor layer (A1), and the seventh gate electrode (G7) may overlap with the channel region (C7) of the seventh semiconductor layer (A7). As will be described later, the seventh gate electrode (G7) may be a portion of the hold gate line (GHL). The first gate electrode (G1a) and the seventh gate electrode (G7) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. In one embodiment, the first gate electrode (G1a) and the seventh gate electrode (G7) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0188] The second interlayer insulating layer (113) may be disposed on the first gate electrode (G1a) and the seventh gate electrode (G7). The second interlayer insulating layer (113) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the second interlayer insulating layer (113) may have a stacked structure of a layer including silicon nitride and a layer including silicon oxynitride.

[0189] The eighth conductive pattern (1710), the eleventh conductive pattern (1740), the twelfth conductive pattern (1750), the reference gate line (GRL), and the second horizontal reference voltage line (HVRL2) may be arranged on the same layer, for example, the second interlayer insulating layer (113). The twelfth conductive pattern (1750) may be a connection electrode connecting the fifth semiconductor layer (A5) and the first semiconductor layer (A1), and the eleventh conductive pattern (1740) may be a connection electrode connecting the first hold electrode (CEh1) and the seventh semiconductor layer (A7). The eighth conductive pattern (1710), the eleventh conductive pattern (1740), the twelfth conductive pattern (1750), the reference gate line (GRL), and the second horizontal reference voltage line (HVRL2) may include the same material. The eighth conductive pattern (1710), the eleventh conductive pattern (1740), the twelfth conductive pattern (1750), the reference gate line (GRL), and the second horizontal reference voltage line (HVRL2) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials. In one embodiment, the eighth conductive pattern (1710), the eleventh conductive pattern (1740), the twelfth conductive pattern (1750), the reference gate line (GRL), and the second horizontal reference voltage line (HVRL2) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0190] The first organic insulating layer (115) may be disposed on the eighth conductive pattern (1710), the eleventh conductive pattern (1740), the twelfth conductive pattern (1750), the reference gate line (GRL), and the second horizontal reference voltage line (HVRL2). The first organic insulating layer (115) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0191] The first data line (DL1) and the vertical driving voltage line (VPL) may be arranged on the first organic insulating layer (115). The first data line (DL1) and the vertical driving voltage line (VPL) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. In one embodiment, the first data line (DL) and the vertical driving voltage line (VPL) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0192] The second organic insulating layer (117) may be disposed on the data line (DL) and the vertical driving voltage line (VPL). The second organic insulating layer (117) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0193] A light emitting diode (LED) may be disposed on the second organic insulating layer (117). The light emitting diode (LED) may include a pixel electrode (210), an intermediate layer (220), and a counter electrode (230) on the second organic insulating layer (117).

[0194] An outer portion of the pixel electrode (210) may be covered by a bank layer (119), and an inner portion of the pixel electrode (210) may overlap an intermediate layer (220) through an opening (119OP) of the bank layer (119). The pixel electrode (210) may be arranged to correspond to each light emitting diode (LED), and the counter electrode (230) may be arranged to correspond to a plurality of light emitting diodes (LED). For example, the counter electrode (230) may be extended to overlap a plurality of pixel electrodes (210). A plurality of light emitting diodes (LED) may share the counter electrode (230), and a stacked structure of the pixel electrode (210), the intermediate layer (220), and the counter electrode (230) may correspond to a light emitting diode (LED).

[0195] The intermediate layer (220) may include an emission layer. In some embodiments, the intermediate layer (220) may further include an emission layer and a functional layer. The functional layer may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL). In some further embodiments, the intermediate layer (220) may include a first stack including an emission layer and a functional layer, a second stack including an emission layer and a functional layer, and a charge generation layer between the first stack and the second stack. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The light emission efficiency of a tandem light emitting diode (LED) including a plurality of emission layers can be further increased by the negative charge generation layer and the positive charge generation layer.

[0196] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0197] The counter electrode (230) may be formed of a conductive material having a low work function. The counter electrode (230) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0198] An encapsulation layer may be disposed on a light emitting diode (LED). The encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer therebetween.

[0199] FIGS. 9 to 16 are plan views illustrating a process for forming a pixel circuit of a display panel according to an embodiment of the present invention. FIGS. 9 to 16 illustrate a process for forming components corresponding to the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) described with reference to FIG. 7. For convenience of explanation, the first pixel circuit (PC1) is positioned in the (i)-th row and the (j)-th column, the second pixel circuit (PC2) is positioned in the (i)-th row and the (j+1)-th column, and the third pixel circuit (PC3) is positioned in the (i)-th row and the (j+2)-th column. Here, i and j are positive integers.

[0200] Referring to FIG. 9, a silicon semiconductor layer (1100) may be disposed on a substrate. For example, the silicon semiconductor layer (1100) may include amorphous silicon or polysilicon. For example, the silicon semiconductor layer (1100) may include polysilicon crystallized at a low temperature. The silicon semiconductor layer (1100) may include a first silicon semiconductor pattern (1110) and a first horizontal reference voltage line (HVRL1), as shown in FIG. 9.

[0201] The first silicon semiconductor pattern (1110) may include a 1-1 silicon semiconductor pattern (1110a) disposed in the first pixel circuit (PC1), a 1-2 silicon semiconductor pattern (1110b) disposed in the second pixel circuit (PC2), and a 1-3 silicon semiconductor pattern (1110c) disposed in the third pixel circuit (PC3). The 1-1 silicon semiconductor pattern (1110a) may have an isolated shape and may include a curved portion. The 1-1 silicon semiconductor pattern (1110a) may include the fifth semiconductor layer (A5) of the first pixel circuit (PC1). The 1-2 silicon semiconductor pattern (1110b) and the 1-3 silicon semiconductor pattern (1110c) may be connected to each other and formed as an integral body. The first-second silicon semiconductor pattern (1110b) and the first-third silicon semiconductor pattern (1110c) may be symmetrical with respect to an imaginary line (IML2). The first-second silicon semiconductor pattern (1110b) may include a fifth semiconductor layer (A5) of the second pixel circuit (PC2), and the first-third silicon semiconductor pattern (1110c) may include a fifth semiconductor layer (A5) of the third pixel circuit (PC3). For example, the fifth semiconductor layer (A5) of the second pixel circuit (PC2) and the fifth semiconductor layer (A5) of the third pixel circuit (PC3) may be integrally connected.

[0202] A first horizontal reference voltage line (HVRL1) may extend along a first direction (e.g., x direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The first horizontal reference voltage line (HVRL1) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The first horizontal reference voltage line (HVRL1) may be electrically connected to a second horizontal reference voltage line (HVRL2, FIG. 15) and a vertical reference voltage line (VVRL, FIG. 16) to transmit a reference voltage to each pixel circuit. The first horizontal reference voltage line (HVRL1) may be arranged to overlap with the second horizontal reference voltage line (HVRL2, FIG. 15) on a plane.

[0203] Referring to FIG. 10, a first conductive layer (1200) may be disposed on a silicon semiconductor layer (1100). The first conductive layer (1200) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0204] The first conductive layer (1200) may include a first emission control line (EML), a first conductive pattern (1210), and a second conductive pattern (1220). The first emission control line (EML), the first conductive pattern (1210), and the second conductive pattern (1220) may be arranged to be spaced apart from each other.

[0205] The first emission control line (EML) can extend along a first direction (e.g., x-direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The first emission control line (EML) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3).

[0206] The first emission control line (EML) may include a fifth gate electrode (G5) of a fifth transistor (T5) of each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). A region of the first emission control line (EML) overlapping with the first silicon semiconductor pattern (1110) may correspond to the fifth gate electrode (G5) of the fifth transistor (T5). The fifth semiconductor layer (A5, FIG. 9) of the fifth transistor (T5) may include a channel region (C5) overlapping with the fifth gate electrode (G5), and doped regions (S5, D5) disposed on both sides of the channel region (C5) and doped with impurities. One of the doped regions (S5, D5) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source and drain regions can be interchanged depending on the properties of the transistor.

[0207] The first challenge pattern (1210) and the second challenge pattern (1220) can be arranged in the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3), respectively. The first conductive pattern (12100) and the second conductive pattern (1220) may each have an isolated shape. The first conductive pattern (1210) and the second conductive pattern (1220) of the first pixel circuit (PC1) may be symmetrically arranged with respect to the first conductive pattern (1210) and the second conductive pattern (1220) of the second pixel circuit (PC2) and the virtual line (IML1) as the center. Similarly, the first conductive pattern (1210) and the second conductive pattern (1220) of the second pixel circuit (PC2) may be symmetrically arranged with respect to the first conductive pattern (12100) and the second conductive pattern (1220) of the third pixel circuit (PC3) and the virtual line (IML2) as the center.

[0208] The first conductive pattern (1210) may include the first storage electrode (CEs1) of the storage capacitor (Cst) described with reference to FIG. 7. The second conductive pattern (1220) may include the first hold electrode (CEh1) of the hold capacitor (Chd) described with reference to FIG. 7. At this time, the second conductive pattern (1220) may further include a protrusion (1220p) for connection to the seventh transistor (T7, FIG. 7). The seventh transistor (T7, FIG. 7) and the first hold electrode (CEh1) may be electrically connected through the protrusion (1220p) of the second conductive pattern (1220).

[0209] Referring to FIG. 11, a second conductive layer (1300) may be disposed on the first conductive layer (1200). The second conductive layer (1300) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0210] The second conductive layer (1300) may include a repair line (RPL) and a third conductive pattern (1310). The repair line (RPL) and the third conductive pattern (1310) may be arranged spaced apart from each other.

[0211] A repair line (RPL) can extend along a first direction (e.g., x direction) so as to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The repair line (RPL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). When a pixel circuit (PC, FIG. 7) is defective, a light emitting diode (LED) can be separated from the defective pixel circuit, and the light emitting diode (LED) can be connected to a dummy pixel circuit via the repair line (RPL). The dummy pixel circuit generates a driving current corresponding to a data signal, and supplies the driving current to the light emitting diode (LED) via the repair line, so that the light emitting diode (LED) can operate normally. Accordingly, the repair line (RPL) may be arranged to overlap with the 13th conductive pattern (1760, FIG. 15) and the 16th conductive pattern (1820, FIG. 16) connected to the light emitting diode (LED). The light emitting diode (LED) is arranged to be insulated from the repair line (RPL), but may be electrically connected to the repair line (RPL) in a later repair process.

[0212] The third conductive pattern (1310) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The third conductive pattern (1310) disposed in the first pixel circuit (PC1) and the third conductive pattern (1310) disposed in the second pixel circuit (PC2) may be spaced apart from each other and may be substantially symmetrically disposed with respect to the aforementioned virtual line (IML1). The third conductive pattern (1310) disposed in the second pixel circuit (PC2) and the third conductive pattern (1310) disposed in the third pixel circuit (PC3) may be spaced apart from each other and may be substantially symmetrically disposed with respect to the aforementioned virtual line (IML2).

[0213] The third conductive pattern (1310) may overlap with each of the first conductive pattern (1210, FIG. 10) and the second conductive pattern (1220, FIG. 10) of the first conductive layer (1200, FIG. 10). The third conductive pattern (1310) may include a second storage electrode (CEs2) of a storage capacitor (Cst, FIG. 7) and a second hold electrode (CEh2) of a hold capacitor (Chd, FIG. 7). An area of ​​the third conductive pattern (1310) overlapping with the first conductive pattern (1210, FIG. 10), which is the first storage electrode (CEs1, FIG. 10), may be the second storage electrode (CEs2) of the storage capacitor (Cst, FIG. 7). The area overlapping the second conductive pattern (1220, FIG. 10), which is the first hold electrode (CEh1, FIG. 10) among the third conductive patterns (1310), may be the second hold electrode (CEh2) of the hold capacitor (Chd, FIG. 7). In other words, the second storage electrode (CEs2) of the storage capacitor (Cst, FIG. 7) and the second hold electrode (CEh2) of the hold capacitor (Chd, FIG. 7) may be formed integrally. Meanwhile, the third conductive pattern (1310) may have a closed opening (1310OP) in the area overlapping the first conductive pattern (1210, FIG. 10).

[0214] Referring to FIG. 12, a third conductive layer (1400) may be disposed on the second conductive layer (1300). The third conductive layer (1400) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0215] The third challenge layer (1400) may include a fourth challenge pattern (1410).

[0216] The fourth conductive pattern (1410) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The fourth conductive pattern (1410) disposed in the first pixel circuit (PC1) may be spaced apart from the fourth conductive pattern (1410) disposed in the second pixel circuit (PC2) and may be substantially symmetrically disposed with respect to the aforementioned virtual line (IML1). The fourth conductive pattern (1410) disposed in the second pixel circuit (PC2) may be spaced apart from the fourth conductive pattern (1410) disposed in the third pixel circuit (PC3) and may be substantially symmetrically disposed with respect to the aforementioned virtual line (IML2).

[0217] In one embodiment, the fourth conductive pattern (1410) may be arranged to overlap the third conductive pattern (1310, FIG. 11). The fourth conductive pattern (1410) may include the first lower gate electrode (G1b, FIG. 8) of the first transistor (T1, FIG. 7) and may be electrically connected to the tenth conductive pattern (1730, FIG. 15) described below.

[0218] Referring to FIG. 13, an oxide semiconductor layer (1500) may be disposed on the third conductive layer (1400). Specifically, the oxide semiconductor layer (1500) may include an oxide semiconductor, and the oxide semiconductor may be an oxide semiconductor including at least one element selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor layer (1500) may include ITZO (InSnZnO) or IGZO (InGaZnO).

[0219] The oxide semiconductor layer (1500) may include a first oxide semiconductor pattern (1510), a second oxide semiconductor pattern (1520), a third oxide semiconductor pattern (1530), and a fourth oxide semiconductor pattern (1540). The first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may be arranged to be spaced apart from each other.

[0220] The first oxide semiconductor pattern (1510) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The first oxide semiconductor pattern (1510) may have a shape extending along the second direction (e.g., the y direction). The first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) and the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) may be symmetrically disposed with respect to an imaginary line (IML1), and the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) and the first oxide semiconductor pattern (1510) of the third pixel circuit (PC3) may be symmetrically disposed with respect to an imaginary line (IML2).

[0221] The first oxide semiconductor pattern (1510) may include a seventh semiconductor layer (A7) of a seventh transistor (T7, FIG. 7). The seventh semiconductor layer (A7) may overlap with a hold gate line (GHL, FIG. 14) of a fourth conductive layer (1600, FIG. 14) to be described later. One end of the first oxide semiconductor pattern (1510) may be electrically connected to a hold capacitor (Chd, FIG. 7) via an eleventh conductive pattern (1740, FIG. 15) to be described later. The other end of the first oxide semiconductor pattern (1510) may overlap with a first horizontal reference voltage line (HVRL1) and a second horizontal reference voltage line (HVRL2, FIG. 15) and may be electrically connected to the second horizontal reference voltage line (HVRL2, FIG. 15).

[0222] The second oxide semiconductor pattern (1520) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The second oxide semiconductor pattern (1520) may be bent to have an approximately “L” shape. The second oxide semiconductor pattern (1520) of the first pixel circuit (PC1) and the second oxide semiconductor pattern (1520) of the second pixel circuit (PC2) may be symmetrically disposed with respect to the aforementioned virtual line (IML1), and the second oxide semiconductor pattern (1520) of the second pixel circuit (PC2) and the second oxide semiconductor pattern (1520) of the third pixel circuit (PC3) may be symmetrically disposed with respect to the virtual line (IML2).

[0223] The second oxide semiconductor pattern (1520) may include a second semiconductor layer (A2) of a second transistor (T2, FIG. 7) and a third semiconductor layer (A3) of a third transistor (T3, FIG. 7). In other words, the second semiconductor layer (A2) of the second transistor (T2, FIG. 7) and the third semiconductor layer (A3) of the third transistor (T3, FIG. 7) may be connected integrally. The second semiconductor layer (A2) may overlap with a first scan line (GWL1, FIG. 14) to be described later, and the third semiconductor layer (A3) may overlap with a seventh conductive pattern (1620, FIG. 14) to be described later.

[0224] The third oxide semiconductor pattern (1530) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The third oxide semiconductor pattern (1530) may have a shape extending along the second direction (e.g., the y direction). The third oxide semiconductor pattern (1530) of the first pixel circuit (PC1) and the third oxide semiconductor pattern (1530) of the second pixel circuit (PC2) may be symmetrically disposed with respect to an imaginary line (IML1), and the third oxide semiconductor pattern (1530) of the second pixel circuit (PC2) and the third oxide semiconductor pattern (1530) of the third pixel circuit (PC3) may be symmetrically disposed with respect to an imaginary line (IML2).

[0225] The third oxide semiconductor pattern (1530) may include a first semiconductor layer (A1) of a first transistor (T1, FIG. 7). The first semiconductor layer (A1) may overlap with a fourth conductive pattern (1410, FIG. 12) and a sixth conductive pattern (1610, FIG. 14) described below. The fourth conductive pattern (1410, FIG. 12) and the sixth conductive pattern (1610, FIG. 14) may form a dual gate structure of the first transistor (T1, FIG. 7).

[0226] The fourth oxide semiconductor pattern (1540) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The fourth oxide semiconductor pattern (1540) may have a shape extending along the second direction (e.g., the y direction). The fourth oxide semiconductor pattern (1540) of the first pixel circuit (PC1) and the fourth oxide semiconductor pattern (1540) of the second pixel circuit (PC2) may be symmetrically disposed with respect to an imaginary line (IML1). However, the fourth oxide semiconductor pattern (1540) of the third pixel circuit (PC3) may have an inverted 'L' shape including a portion extending in the first direction (e.g., the x direction) in comparison with the fourth oxide semiconductor pattern (1540) of the first pixel circuit (PC1).

[0227] The fourth oxide semiconductor pattern (1540) may include a fourth semiconductor layer (A4) and a sixth semiconductor layer (A6). In other words, the fourth semiconductor layer (A4) and the sixth semiconductor layer (A6) may be connected integrally. One end of the fourth oxide semiconductor pattern (1540) may overlap with the third conductive pattern (1310, FIG. 11) and be connected to the tenth conductive pattern (1730, FIG. 15) to be described later. The other end of the fourth oxide semiconductor pattern (1540) may overlap with and be connected to a horizontal initialization voltage line (HVL, FIG. 7). For example, the fourth oxide semiconductor pattern (1540) of the first pixel circuit (PC1) may be connected to the first horizontal initialization voltage line (HVL1, FIG. 7), the fourth oxide semiconductor pattern (1540) of the second pixel circuit (PC2) may be connected to the second horizontal initialization voltage line (HVL2, FIG. 7), and the fourth oxide semiconductor pattern (1540) of the third pixel circuit (PC3) may be connected to the third horizontal initialization voltage line (HVL3, FIG. 7).

[0228] Each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may include at least a partially conductive region. For example, a conductive process using plasma or the like may be performed on at least a portion of each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540).

[0229] Referring to FIG. 14, a fourth conductive layer (1600) may be disposed on an oxide semiconductor layer (1500). The fourth conductive layer (1600) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0230] The fourth conductive layer (1600) may include a first scan line (GWL1), a hold gate line (GHL), a second emission control line (EMBL), an initialization gate line (GIL), a third horizontal initialization voltage line (HVL3), a sixth conductive pattern (1610), and a seventh conductive pattern (1620). The first scan line (GWL1), the hold gate line (GHL), the second emission control line (EMBL), the initialization gate line (GIL), the third horizontal initialization voltage line (HVL3), the sixth conductive pattern (1610), and the seventh conductive pattern (1620) may be spaced apart from each other.

[0231] A first scan line (GWL1) may extend along a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The first scan line (GWL1) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2). The first scan line (GWL1) may overlap with a second scan line (GWL2, FIG. 15), which will be described later, but may be electrically connected to the second scan line (GWL2, FIG. 15).

[0232] The first scan line (GWL1) may include a stem portion extending in a first direction (e.g., x-direction) and a branch portion branching off from the stem portion and protruding in a second direction (e.g., y-direction). The branch portion of the first scan line (GWL1) may include a region overlapping with the second oxide semiconductor pattern (1520, FIG. 13), i.e., the second gate electrode (G2) of the second transistor (T2). Referring to FIGS. 13 and 14, the second semiconductor layer (A2) of the second transistor (T2) may include a channel region (C2) overlapping with the first scan line (GWL1) and conductive regions (S2, D2) arranged on both sides of the channel region (C2). One of the conductive regions (S2, D2) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source and drain regions can be interchanged depending on the properties of the transistor.

[0233] The hold gate line (GHL) can extend along a first direction (e.g., x-direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The hold gate line (GHL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0234] The hold gate line (GHL) may include a region overlapping with the first oxide semiconductor pattern (1510, FIG. 13), i.e., the seventh gate electrode (G7) of the seventh transistor (T7). Referring to FIGS. 13 and 14, the seventh semiconductor layer (A7) of the seventh transistor (T7) may include a channel region (C7) overlapping with the hold gate line (GHL) and conductive regions (S7, D7) arranged on both sides of the channel region (C7). One of the conductive regions (S7, D7) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0235] The second emission control line (EMBL) may extend along the first direction (e.g., the x-direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second emission control line (EMBL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0236] The second emission control line (EMBL) may include a region overlapping with the fourth oxide semiconductor pattern (1540, FIG. 13), i.e., the sixth gate electrode (G6) of the sixth transistor (T6). Referring to FIGS. 13 and 14, the sixth semiconductor layer (A6) of the sixth transistor (T6) may include a channel region (C6) overlapping with the second emission control line (EMBL) and conductive regions (S6, D6) arranged on both sides of the channel region (C6). One of the conductive regions (S6, D6) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0237] An initialization gate line (GIL) can extend along a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The initialization gate line (GIL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0238] The initialization gate line (GIL) may include a region overlapping with the fourth oxide semiconductor pattern (1540, FIG. 13), i.e., the fourth gate electrode (G4) of the fourth transistor (T4). Referring to FIGS. 13 and 14, the fourth semiconductor layer (A4) of the fourth transistor (T4) may include a channel region (C4) overlapping with the initialization gate line (GIL) and conductive regions (S4, D4) arranged on both sides of the channel region (C4). One of the conductive regions (S4, D4) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0239] The third horizontal initialization voltage line (HVL3) may extend along the first direction (e.g., the x-direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The third horizontal initialization voltage line (HVL3) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2). The third horizontal initialization voltage line (HVL3) may be connected to the fourth oxide semiconductor pattern (1540, FIG. 13) of the third pixel circuit (PC3) through the fourteenth conductive pattern (1770, FIG. 15) to be described later.

[0240] The sixth conductive pattern (1610) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The sixth conductive pattern (1610) of the first pixel circuit (PC1) may be symmetrically disposed with respect to the sixth conductive pattern (1610) of the second pixel circuit (PC2) and the virtual line (IML1), and the sixth conductive pattern (1610) of the second pixel circuit (PC2) may be symmetrically disposed with respect to the sixth conductive pattern (1610) of the third pixel circuit (PC3) and the virtual line (IML2).

[0241] Each of the sixth conductive patterns (1610) of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include a first gate electrode (G1) of the first transistor (T1). Referring to FIGS. 13 and 14, the first semiconductor layer (A1) of the first transistor (T1) may include a channel region (C1) overlapping the sixth conductive pattern (1610) and conductive regions (S1, D1) arranged on both sides of the channel region (C1). One of the conductive regions (S1, D1) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor. At this time, a part of the fourth conductive pattern (1410, Fig. 12) and the first gate electrode (G1) may overlap each other with the channel region (C1) therebetween. A part of the fourth conductive pattern (1410, Fig. 12) overlapping the channel region (C1) of the first transistor (T1) may correspond to the first lower gate electrode (G1b, Fig. 8) of the first transistor (T1).

[0242] The seventh conductive pattern (1620) may have an isolated shape, but may have a shape extending along the first direction (e.g., the x-direction). The seventh conductive pattern (1620) may be arranged across the first pixel circuit (PC1) and the second pixel circuit (PC2). The seventh conductive pattern (1620) may intersect the virtual line (IML1). Similarly, the seventh conductive pattern (1620) may be arranged across the third pixel circuit (PC3) and the first pixel circuit (PC1). However, the seventh conductive pattern (1620) may not be arranged across the second pixel circuit (PC2) and the third pixel circuit (PC3). For example, the seventh conductive pattern (1620) may not be arranged on the virtual line (IML2), which is a boundary between the second pixel circuit (PC2) and the third pixel circuit (PC3).

[0243] Each of the seventh conductive patterns (1620) of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include a third gate electrode (G3) of a third transistor (T3). Referring to FIGS. 13 and 14, the third semiconductor layer (A3) of the third transistor (T3) may include a channel region (C3) overlapping the seventh conductive pattern (1620) and conductive regions (S3, D3) arranged on both sides of the channel region (C3). One of the conductive regions (S3, D3) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0244] Referring to FIG. 15, a fifth conductive layer (1700) may be disposed on a fourth conductive layer (1600). The fifth conductive layer (1700) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0245] The fifth conductive layer (1700) may include a second scan line (GWL2), a second horizontal reference voltage line (HVRL2), a reference gate line (GRL), a horizontal driving voltage line (HPL), a first horizontal initialization voltage line (HVL1), a second horizontal initialization voltage line (HVL2), a common voltage line (VSL), and eighth to fourteenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770). The second scan line (GWL2), the second horizontal reference voltage line (HVRL2), the reference gate line (GRL), the horizontal drive voltage line (HPL), the first horizontal initialization voltage line (HVL1), the second horizontal initialization voltage line (HVL2), the common voltage line (VSL), and the eighth to fourteenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770) may be arranged to be spaced apart from each other.

[0246] The second scan line (GWL2) can extend along a first direction (e.g., x direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second scan line (GWL2) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second scan line (GWL2) can be arranged to overlap the first scan line (GWL1, FIG. 14), and can be electrically connected to the first scan line (GWL1, FIG. 14) through the first contact hole (CNT1).

[0247] The second horizontal reference voltage line (HVRL2) may extend along the first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second horizontal reference voltage line (HVRL2) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second horizontal reference voltage line (HVRL2) may be arranged to overlap the first horizontal reference voltage line (HVRL1, FIG. 9).

[0248] The second horizontal reference voltage line (HVRL2) can be electrically connected to the first horizontal reference voltage line (HVRL1, FIG. 9) through the second contact hole (CNT2). In addition, the second horizontal reference voltage line (HVRL2) can be connected to the second oxide semiconductor pattern (1520, FIG. 13) through the fourth contact hole (CNT4) to transmit a reference voltage to the third transistor (T3, FIG. 14). The second horizontal reference voltage line (HVRL2) can be connected to the first oxide semiconductor pattern (1510, FIG. 13) through the fifth contact hole (CNT5) to transmit a reference voltage to the seventh transistor (T7, FIG. 14).

[0249] A reference gate line (GRL) may extend along a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The reference gate line (GRL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The reference gate line (GRL) may be electrically connected to a seventh conductive pattern (1620, FIG. 14) through a sixth contact hole (CNT6) to transmit a reference signal to a gate electrode of a third transistor (T3, FIG. 14).

[0250] The eighth conductive pattern (1710) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The eighth conductive pattern (1710) of the first pixel circuit (PC1) and the eighth conductive pattern (1710) of the second pixel circuit (PC2) may be symmetrically arranged with respect to the virtual line (IML1), and the eighth conductive pattern (1710) of the second pixel circuit (PC2) and the eighth conductive pattern (1710) of the third pixel circuit (PC3) may be symmetrically arranged with respect to the virtual line (IML2).

[0251] The eighth conductive pattern (1710) may be a connection electrode connecting a second oxide semiconductor pattern (1520, FIG. 23) including a second semiconductor layer (A2, FIG. 13) and a data line (DL, FIG. 18). The eighth conductive pattern (1710) may be connected to one end of the second oxide semiconductor pattern (1520, FIG. 23) through a seventh contact hole (CNT7).

[0252] The ninth conductive pattern (1720) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The ninth conductive pattern (1720) of the first pixel circuit (PC1) and the ninth conductive pattern (1720) of the second pixel circuit (PC2) may be symmetrically arranged with respect to the virtual line (IML1), and the ninth conductive pattern (1720) of the second pixel circuit (PC2) and the ninth conductive pattern (1720) of the third pixel circuit (PC3) may be symmetrically arranged with respect to the virtual line (IML2).

[0253] The ninth conductive pattern (1720) may be a connection electrode connecting the second oxide semiconductor pattern (1520, FIG. 13) including the second semiconductor layer (A2, FIG. 13) and the third semiconductor layer (A3, FIG. 13) and the sixth conductive pattern (1610, FIG. 14) including the first gate electrode (G1, FIG. 14) of the first transistor (T1, FIG. 14). In other words, the ninth conductive pattern (1720) may be a first node electrode (N1) connecting the first transistor (T1, FIG. 14), the second transistor (T2, FIG. 14), and the third transistor (T3, FIG. 14). The ninth conductive pattern (1720) can be connected to the second oxide semiconductor pattern (1520, FIG. 13) through the eighth contact hole (CNT8) and can be connected to the sixth conductive pattern (1610, FIG. 14) through the ninth contact hole (CNT9). In addition, the ninth conductive pattern (1720) can also be electrically connected to the storage capacitor (Cst, FIG. 7). The ninth conductive pattern (1720) can be connected to the first storage electrode (CEs1, FIG. 10) of the storage capacitor (Cst, FIG. 7) through the tenth contact hole (CNT10).

[0254] The tenth conductive pattern (1730) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The tenth conductive pattern (1730) may be arranged to overlap the third conductive pattern (1310, FIG. 11). The tenth conductive pattern (1730) of the first pixel circuit (PC1) and the tenth conductive pattern (1730) of the second pixel circuit (PC2) may be arranged symmetrically with respect to the virtual line (IML1), and the tenth conductive pattern (1730) of the second pixel circuit (PC2) and the tenth conductive pattern (1730) of the third pixel circuit (PC3) may be arranged symmetrically with respect to the virtual line (IML2).

[0255] The tenth conductive pattern (1730) may be a connection electrode connecting a third oxide semiconductor pattern (1530, FIG. 13) including a first semiconductor layer (A1, FIG. 13) and a fourth oxide semiconductor pattern (1540, FIG. 13) including a sixth semiconductor layer (A6, FIG. 13). For example, the tenth conductive pattern (1730) may be a second node electrode (N2) connecting a first transistor (T1, FIG. 14) and a sixth transistor (T6, FIG. 14). The tenth conductive pattern (1730) may be connected to the third oxide semiconductor pattern (1530, FIG. 13) through an eleventh contact hole (CNT11) and may be connected to the fourth oxide semiconductor pattern (1540, FIG. 13) through a twelfth contact hole (CNT12).

[0256] Additionally, the 10th conductive pattern (1730) may be electrically connected to a storage capacitor (Cst, FIG. 7), a hold capacitor (Chd, FIG. 7), and a first lower gate electrode (G1b, FIG. 8) of a first transistor (T1, FIG. 14). The 10th conductive pattern (1730) may be electrically connected to a third conductive pattern (1310, FIG. 11) including a second storage electrode (CEs2, FIG. 11) and a second hold electrode (CEh2, FIG. 11) through a 13th contact hole (CNT13). The 10th conductive pattern (1730) may be electrically connected to a fourth conductive pattern (1410, FIG. 12) including a first lower gate electrode (G1b, FIG. 8) through a 14th contact hole (CNT14).

[0257] The 11th conductive pattern (1740) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The 11th conductive pattern (1740) may have a shape extending along the second direction (e.g., the y direction). The 11th conductive pattern (1740) of the first pixel circuit (PC1) and the 11th conductive pattern (1740) of the second pixel circuit (PC2) may be symmetrically arranged with respect to the virtual line (IML1), and the 11th conductive pattern (1740) of the second pixel circuit (PC2) and the 11th conductive pattern (1740) of the third pixel circuit (PC3) may be symmetrically arranged with respect to the virtual line (IML2).

[0258] The eleventh conductive pattern (1740) may be a connection electrode connecting a first hold electrode (CEh1, FIG. 10) of a hold capacitor (Chd, FIG. 7) and a first oxide semiconductor pattern (1510, FIG. 13) including a seventh semiconductor layer (A7, FIG. 13). One end of the eleventh conductive pattern (1740) may be electrically connected to a second conductive pattern (1220, FIG. 10) including the first hold electrode (CEh1, FIG. 10) through a fifteenth contact hole (CNT15). The other end of the eleventh conductive pattern (1740) may be electrically connected to the first oxide semiconductor pattern (1510, FIG. 13) through a sixteenth contact hole (CNT16).

[0259] The 12th conductive pattern (1750) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The 12th conductive pattern (1750) may have a shape extending along the first direction (e.g., the x direction). The 12th conductive pattern (1750) of the first pixel circuit (PC1) and the 12th conductive pattern (1750) of the second pixel circuit (PC2) may be symmetrically arranged with respect to the imaginary line (IML1), and the 12th conductive pattern (1750) of the second pixel circuit (PC2) and the 12th conductive pattern (1750) of the third pixel circuit (PC3) may be symmetrically arranged with respect to the imaginary line (IML2).

[0260] The 12th conductive pattern (1750) may be a connection electrode connecting a third oxide semiconductor pattern (1530, FIG. 13) including a first semiconductor layer (A1, FIG. 13) and a first silicon semiconductor pattern (1110, FIG. 9) including a fifth semiconductor layer (A5, FIG. 9). One end of the 12th conductive pattern (1750) may be electrically connected to the third oxide semiconductor pattern (1530, FIG. 13) through a 17th contact hole (CNT17), and the other end of the 12th conductive pattern (1750) may be electrically connected to the first silicon semiconductor pattern (1110, FIG. 9) through an 18th contact hole (CNT18).

[0261] A horizontal driving voltage line (HPL) may extend along a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The horizontal driving voltage line (HPL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The horizontal driving voltage line (HPL) may be electrically connected to a first silicon semiconductor pattern (1110, FIG. 9) through a 19th contact hole (CNT19) to transmit a driving voltage to a fifth transistor (T5, FIG. 10).

[0262] The 13th conductive pattern (1760) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The 13th conductive pattern (1760) may have a shape extending along the first direction (e.g., the x-direction). The 13th conductive pattern (1760) may be arranged to overlap the repair line (RPL). The 13th conductive pattern (1760) of the first pixel circuit (PC1) and the 13th conductive pattern (1760) of the second pixel circuit (PC2) may be arranged symmetrically with respect to the imaginary line (IML1). The 13th conductive pattern (1760) of the third pixel circuit (PC3) may further include a protrusion extending diagonally in the same shape as the 13th conductive pattern (1760) of the first pixel circuit (PC1).

[0263] The 13th conductive pattern (1760) may be a connection electrode connecting a fourth oxide semiconductor pattern (1540, FIG. 13) including a fourth semiconductor layer (A4, FIG. 13) and a sixth semiconductor layer (A6, FIG. 13) and a light emitting diode (LED, FIG. 8). The 13th conductive pattern (1760) may be electrically connected to the fourth oxide semiconductor pattern (1540, FIG. 13) through the 20th contact hole (CNT20) and may be electrically connected to a repair wiring (RPL, FIG. 11) through the 21st contact hole (CNT21).

[0264] A first horizontal initialization voltage line (HVL1) and a second horizontal initialization voltage line (HVL2) may extend along a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The first horizontal initialization voltage line (HVL1) and the second horizontal initialization voltage line (HVL2) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The first horizontal initialization voltage line (HVL1) may be electrically connected to a fourth oxide semiconductor pattern (1540, FIG. 13) of the first pixel circuit (PC1) through a twenty-second contact hole (CNT22) to transmit an initialization voltage to a fourth transistor (T4, FIG. 14) of the first pixel circuit (PC1). The second horizontal initialization voltage line (HVL2) is electrically connected to the fourth oxide semiconductor pattern (1540, FIG. 13) of the second pixel circuit (PC2) through the 23rd contact hole (CNT23), and can transmit an initialization voltage to the fourth transistor (T4, FIG. 14) of the second pixel circuit (PC2).

[0265] The 14th conductive pattern (1770) may have an isolated shape and may be arranged on an imaginary line (IML2) which is a boundary between the second pixel circuit (PC2) and the third pixel circuit (PC3). The 14th conductive pattern (1770) may have a shape extending along the first direction (e.g., the x-direction). The 14th conductive pattern (1770) may be a connecting electrode connecting the fourth oxide semiconductor pattern (1540, FIG. 13) of the third pixel circuit (PC3) and the third horizontal initialization voltage line (HVL3, FIG. 14). The 14th challenge pattern (1770) is electrically connected to the third horizontal initialization voltage line (HVL3, FIG. 14) through the 24th contact hole (CNT24) and is electrically connected to the fourth oxide semiconductor pattern (1540, FIG. 13) of the third pixel circuit (PC3) through the 25th contact hole (CNT25), so as to transmit the initialization voltage to the fourth transistor (T4, FIG. 14) of the third pixel circuit (PC3).

[0266] A common voltage line (VSL) may extend along a first direction (e.g., x direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The common voltage line (VSL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The common voltage line (VSL) may be electrically connected to a second power supply line (16, FIG. 6) arranged in a peripheral area (PA, FIG. 6) to transmit a common voltage to a light emitting diode (LED, FIG. 8).

[0267] Referring to FIG. 16, a sixth conductive layer (1800) may be disposed on a fifth conductive layer (1700). The sixth conductive layer (1800) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0268] The sixth conductive layer (1800) may include a data line (DL), a vertical driving voltage line (VPL), a vertical initialization voltage line (VVL), a vertical reference voltage line (VRL), a fifteenth conductive pattern (1810), and a sixteenth conductive pattern (1820). The data line (DL), the vertical driving voltage line (VPL), the vertical initialization voltage line (VVL), the vertical reference voltage line (VRL), the fifteenth conductive pattern (1810), and the sixteenth conductive pattern (1820) may be arranged to be spaced apart from each other.

[0269] The data line (DL) may extend along a second direction (e.g., the y direction). The data line (DL) may include a first data line (DL1) electrically connected to a first pixel circuit (PC1), a second data line (DL2) electrically connected to a second pixel circuit (PC2), and a third data line (DL3) electrically connected to a third pixel circuit (PC3). The data line (DL) may be electrically connected through an eighth conductive pattern (1710, FIG. 15) and a twenty-sixth contact hole (CNT26) connected to a second oxide semiconductor pattern (1520, FIG. 13). That is, the data line (DL) may transmit a data signal to the second semiconductor layer (A2, FIG. 13) through the eighth conductive pattern (1710).

[0270] The first data line (DL1) may be arranged to pass through the first pixel circuit (PC2), the second data line (DL2) may be arranged to pass through the second pixel circuit (PC2), and the third data line (DL3) may be arranged to pass through the third pixel circuit (PC3) except for some areas. The first data line (DL1) may be arranged on the left side of the first vertical driving voltage line (VPL1). The second data line (DL2) and the third data line (DL3) may be arranged in parallel between the second vertical driving voltage line (VPL2) and the vertical reference voltage line (VVRL).

[0271] The vertical driving voltage line (VPL) may extend along a second direction (e.g., y direction). The vertical driving voltage line (VPL) may include a first vertical driving voltage line (VPL1) disposed on a first pixel circuit (PC1) and a second vertical driving voltage line (VPL2) disposed on a second pixel circuit (PC2). The first vertical driving voltage line (VPL1) and the second vertical driving voltage line (VPL2) may be symmetrically disposed with respect to an imaginary line (IML1). The first vertical driving voltage line (VPL1) may be electrically connected to a horizontal driving voltage line (HPL, FIG. 15) through a 27-1 contact hole (CNT27a), and the second vertical driving voltage line (VPL2) may be electrically connected to a horizontal driving voltage line (HPL, FIG. 15) through a 27-2 contact hole (CNT27b).

[0272] The vertical initialization voltage line (VVL) may extend along the second direction (e.g., the y direction). The vertical initialization voltage line (VVL) may be arranged between the first vertical driving voltage line (VPL1) and the second vertical driving voltage line (VPL2). The vertical initialization voltage line (VVL) may be arranged on an imaginary line (IML1) which is a boundary between the first pixel circuit (PC1) and the second pixel circuit (PC2). The vertical initialization voltage line (VVL) may be electrically connected to the second horizontal initialization voltage line (HVL2, FIG. 15) through the 28th contact hole (CNT28).

[0273] The vertical reference voltage line (VVRL) may extend along the second direction (e.g., the y-direction). The vertical reference voltage line (VVRL) may be arranged on the third pixel circuit (PC3). The vertical reference voltage line (VVRL) may be electrically connected to the second horizontal reference voltage line (HVRL2, FIG. 15) through the 29th contact hole (CNT29).

[0274] The 15th conductive pattern (1810) and the 16th conductive pattern (1820) may each have an isolated shape. The 15th conductive pattern (1810) and the 16th conductive pattern (1820) may be arranged in the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3), respectively. The 15th conductive pattern (1810) may be electrically connected to the 10th conductive pattern (1730, FIG. 15) through the 30th contact hole (CNT30) and may have a shape extending along the second direction (e.g., the y direction) to cover the 9th conductive pattern (1720, FIG. 15). Since the 15th conductive pattern (1810) shields the 9th conductive pattern (1720, FIG. 15) that is electrically connected to the storage capacitor (Cst), image quality characteristics may be improved. The 16th conductive pattern (1820) may be a connecting electrode connecting the 4th oxide semiconductor pattern (1540, FIG. 13) and the light-emitting diode (LED, FIG. 8). The 16th conductive pattern (1820) may be electrically connected to the 13th conductive pattern (1760, FIG. 15) through the 31st contact hole (CNT31) and may be electrically connected to the pixel electrode (210, FIG. 8) of the light-emitting diode (LED, FIG. 8) through the 32nd contact hole (CNT32).

[0275] Fig. 17 is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention. For convenience of explanation, Fig. 17 illustrates a structure in which only a silicon semiconductor layer (1100, Fig. 9), a first conductive layer (1200, Fig. 10), a second conductive layer (1300, Fig. 11), a third conductive layer (1400, Fig. 12), an oxide semiconductor layer (1500, Fig. 13), a fourth conductive layer (1600, Fig. 14), and a fifth conductive layer (1700, Fig. 15) are accumulated.

[0276] Referring to FIG. 17, the hold gate line (GHL) may be arranged to extend along the first direction (e.g., the x-direction). The hold gate line (GHL) may overlap a portion of the first oxide semiconductor pattern (1510), and the portion of the hold gate line (GHL) that overlaps the first oxide semiconductor pattern (1510) may become the seventh gate electrode (G7) of the seventh transistor (T7). The portion of the first oxide semiconductor pattern (1510) that overlaps the hold gate line (GHL) may become the channel region (C7) of the seventh transistor (T7). One end of the first oxide semiconductor pattern (1510) is connected to the second horizontal reference voltage line (HVRL2), so that the seventh transistor (T7) may receive a reference voltage. The other end of the first oxide semiconductor pattern (1510) can be electrically connected to the first hold electrode (CEh1, FIG. 10) of the hold capacitor (Chd) included in the second conductive pattern (1220) through the eleventh conductive pattern (1740).

[0277] In one embodiment, the hold gate line (GHL) may be arranged to cross between the first transistor (T1) and the second transistor (T2) on a planar surface. For example, the hold gate line (GHL) may be arranged to cross between the third oxide semiconductor pattern (1530) on which the first semiconductor layer (A1, FIG. 13) is arranged on a planar surface and the second oxide semiconductor pattern (1520) on which the second semiconductor layer (A2, FIG. 13) is arranged.

[0278] As the hold gate line (GHL) is arranged to cross the first transistor (T1) and the second transistor (T2), the hold gate line (GHL) may be arranged to overlap a connection electrode connecting the first transistor (T1) and the second transistor (T2). For example, the hold gate line (GHL) may include a first overlapping area (OA1) overlapping with the ninth conductive pattern (1720). In this case, the ninth conductive pattern (1720) may be a first node electrode (N1) connecting the first gate electrode (G1, FIG. 14) of the first transistor (T1) and the second semiconductor layer (A2, FIG. 13).

[0279] According to an embodiment of the present invention, a display panel includes a seventh transistor (T7) connected to a hold capacitor (Chd) and a hold gate line (GHL), so that the hold capacitor (Chd) can be controlled through a hold signal transmitted to the hold gate line (GHL). Since the hold capacitor (Chd) may have a large capacitance of about 100 fF, when the hold capacitor (Chd) is operated in the light-emitting section, the hold capacitor (Chd) may have a negative effect on the second node electrode (N2) to which it is electrically connected. In addition, since the second node electrode (N2) may also be connected to the first node electrode (N1) through the storage capacitor (Cst, FIG. 7), when the hold capacitor (Chd) becomes visible in the light-emitting section, the image quality characteristics of the display panel (10, FIG. 2) may be degraded.

[0280] At this time, as shown in Fig. 17, when the display panel includes the seventh transistor (T7) and the hold gate line (GHL) connected to the hold capacitor (Chd), the hold capacitor (Chd) can be adjusted to be formed only in the data writing section and the compensation section, and to be blocked in the light emitting section. When the hold capacitor (Chd) is blocked in the light emitting section, the voltages of the second node electrode (N2) and the first node electrode (N1) can be maintained more stably, so that the coupling of the pixel circuit can be formed more robustly. For example, when the display panel includes the seventh transistor (T7) and the hold gate line (GHL), even if noise occurs in the data voltage due to other parameters, the difference in luminance of the pixel is small, so that the display panel can stably implement a high-quality image.

[0281] Meanwhile, as the hold gate line (GHL) extends along the first direction (e.g., x-direction), the hold gate line (GHL) may inevitably partially overlap with the node electrode of the first transistor (T1). For example, as shown in FIG. 17, when the hold gate line (GHL) is arranged to cross between the first transistor (T1) and the second transistor (T2), the hold gate line (GHL) may overlap with the first node electrode (N1). As the area of ​​the overlapping region where the hold gate line (GHL) and the node electrode overlap increases, the voltage of the node electrode may fluctuate due to coupling, and there is a concern that a defective phenomenon such as ghost mura may occur.

[0282] However, as shown in Fig. 17, when the hold gate line (GHL) includes only the first overlapping area (OA1) overlapping the first node electrode (N1), the area of ​​the overlapping area may be relatively small compared to a structure in which the hold gate line (GHL) overlaps a plurality of node electrodes. For example, in a display panel according to an embodiment of the present invention, since the hold gate line (GHL) is arranged to cross between the first transistor (T1) and the second transistor (T2), the overlapping area between the hold gate line (GHL) and the node electrode is minimized, thereby preventing defects such as ghost mura due to the coupling phenomenon and implementing a high-quality image.

[0283] Fig. 18 is a plan view schematically showing pixel circuits of a display panel according to another embodiment of the present invention. Figs. 19 to 26 are plan views according to a process of forming pixel circuits of a display panel according to another embodiment of the present invention. Referring to Figs. 18 to 26, except for the features of the hold gate line (GHL) and the seventh transistor (T7), other features are the same as those described with reference to Figs. 7 to 17. For components of Figs. 18 to 26 that are indicated by the same reference numerals as those of Figs. 7 to 17, reference may be made to the descriptions of Figs. 7 to 17, and in the following, mainly different aspects will be described, and if a specific component is not described in detail with respect to the drawings, it can be understood that it is at least similar to a corresponding component described in other parts of the present specification.

[0284] First, referring to FIG. 18, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include transistors and capacitors. In one embodiment, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include first to seventh transistors (T1, T2, T3, T4, T5, T6, T7), a storage capacitor (Cst), and a hold capacitor (Chd).

[0285] The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be electrically connected to gate lines that transmit signals to the gates of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7), respectively. For example, the pixel circuit (PC) may be connected to a scan line (GWL) that transmits a scan signal, an initialization gate line (GBL) that transmits an initialization signal, a reference gate line (GRL) that transmits a reference signal, a first emission control line (EML) that transmits a first emission control signal, a second emission control line (EMBL) that transmits a second emission control signal, a hold gate line (GHL) that transmits a hold signal, and a data line (DL) that transmits a data signal. Additionally, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) can be connected to a driving voltage line (PL) that transmits a driving voltage, a reference voltage line (VRL) that transmits a reference voltage, and an initialization voltage line (VL) that transmits an initialization voltage.

[0286] Referring to FIG. 19, a silicon semiconductor layer (1100) may be arranged on a substrate. The silicon semiconductor layer (1100) may include a first silicon semiconductor pattern (1110) and a first horizontal reference voltage line (HVRL1).

[0287] The first silicon semiconductor pattern (1110) may include a 1-1 silicon semiconductor pattern (1110a) disposed in a first pixel circuit (PC1), a 1-2 silicon semiconductor pattern (1110b) disposed in a second pixel circuit (PC2), and a 1-3 silicon semiconductor pattern (1110c) disposed in a third pixel circuit (PC3). The 1-1 silicon semiconductor pattern (1110a) may have an isolated shape and may include a curved portion. The 1-2 silicon semiconductor pattern (1110b) and the 1-3 silicon semiconductor pattern (1110c) may be connected to each other and formed as an integral part. The 1-1 silicon semiconductor pattern (1110a), the 1-2 silicon semiconductor pattern (1110b), and the 1-3 silicon semiconductor pattern (1110c) may each include a fifth semiconductor layer (A5).

[0288] The first horizontal reference voltage line (HVRL1) can extend along the first direction (e.g., the x-direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3).

[0289] Referring to FIG. 20, a first conductive layer (1200) may be disposed on a silicon semiconductor layer (1100). The first conductive layer (1200) may include a first emission control line (EML), a first conductive pattern (1210), and a second conductive pattern (1220).

[0290] A first emission control line (EML) may extend in a first direction (e.g., x-direction) so as to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The first emission control line (EML) may include a fifth gate electrode (G5) of a fifth transistor (T5) of each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). A fifth semiconductor layer (A5, FIG. 19) of the fifth transistor (T5) may include a channel region (C5) overlapping the fifth gate electrode (G5), and doped regions (S5, D5) doped with impurities and disposed on both sides of the channel region (C5), respectively.

[0291] The first conductive pattern (1210) and the second conductive pattern (1220) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The first conductive pattern (1210) may include a first storage electrode (CEs1) of a storage capacitor (Cst, FIG. 18). The second conductive pattern (1220) may include a first hold electrode (CEh1) of a hold capacitor (Chd, FIG. 18). At this time, the second conductive pattern (1220) may further include a protrusion (1220p) for connecting to the seventh transistor (T7, FIG. 18).

[0292] Referring to FIG. 21, a second conductive layer (1300) may be disposed on a first conductive layer (1200). The second conductive layer (1300) may include a repair line (RPL) and a third conductive pattern (1310).

[0293] The repair line (RPL) can extend along a first direction (e.g., x direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3).

[0294] The third conductive pattern (1310) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The third conductive pattern (1310) may overlap with each of the first conductive pattern (1210, FIG. 20) and the second conductive pattern (1220, FIG. 20) of the first conductive layer (1200, FIG. 20). The third conductive pattern (1310) may include a second storage electrode (CEs2) of a storage capacitor (Cst, FIG. 18) and a second hold electrode (CEh2) of a hold capacitor (Chd, FIG. 18). The third conductive pattern (1310) may have a closed opening (1310OP) in an area overlapping with the first conductive pattern (1210, FIG. 20).

[0295] Referring to FIG. 22, a third conductive layer (1400) may be disposed on the second conductive layer (1300). The third conductive layer (1400) may include a fourth conductive pattern (1410).

[0296] The fourth conductive pattern (1410) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The fourth conductive pattern (1410) may be disposed to overlap the third conductive pattern (1310, FIG. 11). The fourth conductive pattern (1410) may include the first lower gate electrode (G1b, FIG. 8) of the first transistor (T1, FIG. 18).

[0297] Referring to FIG. 23, an oxide semiconductor layer (1500) may be disposed on the third conductive layer (1400). The oxide semiconductor layer (1500) may include a first oxide semiconductor pattern (1510), a second oxide semiconductor pattern (1520), a third oxide semiconductor pattern (1530), and a fourth oxide semiconductor pattern (1540).

[0298] The first oxide semiconductor pattern (1510) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The first oxide semiconductor pattern (1510) may include a seventh semiconductor layer (A7) of a seventh transistor (T7, FIG. 18). The seventh semiconductor layer (A7) may overlap with a hold gate line (GHL, FIG. 24) of a fourth conductive layer (1600, FIG. 24) to be described later. One end of the first oxide semiconductor pattern (1510) may be electrically connected to a hold capacitor (Chd, FIG. 18) via an eleventh conductive pattern (1740, FIG. 25) to be described later. The other end of the first oxide semiconductor pattern (1510) overlaps with the first horizontal reference voltage line (HVRL1) and the second horizontal reference voltage line (HVRL2, FIG. 25), and can be electrically connected to the second horizontal reference voltage line (HVRL2, FIG. 25).

[0299] The second oxide semiconductor pattern (1520) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The second oxide semiconductor pattern (1520) may be bent to have an approximately “L” shape. The second oxide semiconductor pattern (1520) may include a second semiconductor layer (A2) of the second transistor (T2, FIG. 18) and a third semiconductor layer (A3) of the third transistor (T3, FIG. 18). For example, the second semiconductor layer (A2) of the second transistor (T2, FIG. 18) and the third semiconductor layer (A3) of the third transistor (T3, FIG. 18) may be integrally connected. The second semiconductor layer (A2) may overlap with the first scan line (GWL1, FIG. 24) to be described later, and the third semiconductor layer (A3) may overlap with the seventh conductive pattern (1620, FIG. 24) to be described later.

[0300] The third oxide semiconductor pattern (1530) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The third oxide semiconductor pattern (1530) may have a shape extending along the second direction (e.g., the y direction). The third oxide semiconductor pattern (1530) may include the first semiconductor layer (A1) of the first transistor (T1, FIG. 18). The first semiconductor layer (A1) may overlap the fourth conductive pattern (1410, FIG. 22) and the sixth conductive pattern (1610, FIG. 24) described below. The fourth conductive pattern (1410, FIG. 22) and the sixth conductive pattern (1610, FIG. 24) may form a dual gate structure of the first transistor (T1, FIG. 18).

[0301] The fourth oxide semiconductor pattern (1540) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The fourth oxide semiconductor pattern (1540) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may be bent to have an inverted 'L' shape. The fourth oxide semiconductor pattern (1540) of the third pixel circuit (PC3) may have the same shape as the fourth oxide semiconductor pattern (1540) of the first pixel circuit (PC1), and may further include a protrusion extending in the first direction (e.g., the x direction) from an end.

[0302] The fourth oxide semiconductor pattern (1540) may include a fourth semiconductor layer (A4) and a sixth semiconductor layer (A6). For example, the fourth semiconductor layer (A4) and the sixth semiconductor layer (A6) may be connected integrally. One end of the fourth oxide semiconductor pattern (1540) may overlap with the first emission control line (EML). However, one end of the fourth oxide semiconductor pattern (1540) may be connected to a protrusion of the tenth conductive pattern (1730, FIG. 25) to be described later. The other end of the fourth oxide semiconductor pattern (1540) may overlap and be connected with a horizontal initialization voltage line (HVL, FIG. 18).

[0303] Referring to FIG. 24, a fourth conductive layer (1600) may be disposed on an oxide semiconductor layer (1500). The fourth conductive layer (1600) may include a first scan line (GWL1), a hold gate line (GHL), a second emission control line (EMBL), an initialization gate line (GIL), a third horizontal initialization voltage line (HVL3), a sixth conductive pattern (1610), and a seventh conductive pattern (1620).

[0304] A first scan line (GWL1) may extend in a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The first scan line (GWL1) may include a stem portion extending in the first direction (e.g., x-direction) and a branch portion protruding from the stem portion and protruding in a second direction (e.g., y-direction). The branch portion of the first scan line (GWL1) may include a region overlapping with a second oxide semiconductor pattern (1520, FIG. 23), i.e., a second gate electrode (G2) of a second transistor (T2).

[0305] The hold gate line (GHL) may include a stem portion (GHt) extending in a first direction (e.g., an x-direction) and a branch portion (GHb) protruding from the stem portion. The stem portion (GHt) of the hold gate line (GHL) may extend along the first direction (e.g., an x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The stem portion (GHt) of the hold gate line (GHL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0306] The branch portion (GHb) of the hold gate line (GHL) may include a vertical branch portion (GHvb) that protrudes from the stem portion and extends in a second direction (e.g., the y direction), and a horizontal branch portion (GHhb) that protrudes from the vertical branch portion and extends in a first direction (e.g., the x direction). The horizontal branch portion (GHhb) of the hold gate line (GHL) may include a region overlapping with the first oxide semiconductor pattern (1510, FIG. 23), that is, the seventh gate electrode (G7) of the seventh transistor (T7). Referring to FIGS. 23 and 24, the seventh semiconductor layer (A7) of the seventh transistor (T7) may include a channel region (C7) overlapping with the hold gate line (GHL) and conductive regions (S7, D7) arranged on both sides of the channel region (C7). One of the conductive regions (S7, D7) may be a source region and the other may be a drain region. The source region and drain region may correspond to the source electrode and the drain electrode, respectively. The positions of the source region and drain region may be interchanged depending on the properties of the transistor.

[0307] The second emission control line (EMBL) may extend along the first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second emission control line (EMBL) may include an area overlapping with the fourth oxide semiconductor pattern (1540, FIG. 23), i.e., the sixth gate electrode (G6) of the sixth transistor (T6).

[0308] The initialization gate line (GIL) may extend along a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The initialization gate line (GIL) may include an area overlapping with the fourth oxide semiconductor pattern (1540, FIG. 23), i.e., the fourth gate electrode (G4) of the fourth transistor (T4).

[0309] The third horizontal initialization voltage line (HVL3) may extend along the first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The third horizontal initialization voltage line (HVL3) may be connected to the fourth oxide semiconductor pattern (1540, FIG. 23) of the third pixel circuit (PC3) via the 14th conductive pattern (1770, FIG. 25) described later.

[0310] The sixth conductive pattern (1610) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The sixth conductive pattern (1610) of each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include a first gate electrode (G1) of the first transistor (T1).

[0311] The seventh conductive pattern (1620) may have an isolated shape, but may have a shape extending along the first direction (e.g., the x-direction). The seventh conductive pattern (1620) may be arranged across the first pixel circuit (PC1) and the second pixel circuit (PC2), or may be arranged across the third pixel circuit (PC3) and the first pixel circuit (PC1). The seventh conductive pattern (1620) of each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include a third gate electrode (G3) of the third transistor (T3).

[0312] Referring to FIG. 25, a fifth conductive layer (1700) may be disposed on a fourth conductive layer (1600). The fifth conductive layer (1700) may include a second scan line (GWL2), a second horizontal reference voltage line (HVRL2), a reference gate line (GRL), a horizontal driving voltage line (HPL), a first horizontal initialization voltage line (HVL1), a second horizontal initialization voltage line (HVL2), a common voltage line (VSL), and eighth to fourteenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770).

[0313] The second scan line (GWL2) may extend along the first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second scan line (GWL2) may be arranged to overlap the first scan line (GWL1, FIG. 24), but may be electrically connected to the first scan line (GWL1, FIG. 24) through the first contact hole (CNT1).

[0314] The second horizontal reference voltage line (HVRL2) may extend along a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second horizontal reference voltage line (HVRL2) may be electrically connected to the first horizontal reference voltage line (HVRL1, FIG. 19) through the second contact hole (CNT2). In addition, the second horizontal reference voltage line (HVRL2) may be connected to the second oxide semiconductor pattern (1520, FIG. 23) through the fourth contact hole (CNT4) and may be connected to the first oxide semiconductor pattern (1510, FIG. 23) through the fifth contact hole (CNT5).

[0315] The reference gate line (GRL) may extend along a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The reference gate line (GRL) may be electrically connected to the seventh conductive pattern (1620, FIG. 14) through the sixth contact hole (CNT6).

[0316] The eighth conductive pattern (1710) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The eighth conductive pattern (1710) may be a connection electrode connecting a second oxide semiconductor pattern (1520, FIG. 23) including a second semiconductor layer (A2, FIG. 13) and a data line (DL, FIG. 18). The eighth conductive pattern (1710) may be connected to one end of the second oxide semiconductor pattern (1520, FIG. 23) through a seventh contact hole (CNT7).

[0317] The ninth conductive pattern (1720) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The ninth conductive pattern (1720) may be a connection electrode connecting the second oxide semiconductor pattern (1520, FIG. 23) including the second semiconductor layer (A2, FIG. 23) and the third semiconductor layer (A3, FIG. 23) and the sixth conductive pattern (1610, FIG. 24) including the first gate electrode (G1, FIG. 24) of the first transistor (T1, FIG. 24). In other words, the ninth conductive pattern (1720) may be a first node electrode (N1) connecting the first transistor (T1, FIG. 24), the second transistor (T2, FIG. 24), and the third transistor (T3, FIG. 24). The ninth conductive pattern (1720) can be connected to the second oxide semiconductor pattern (1520, FIG. 23) through the eighth contact hole (CNT8) and can be connected to the sixth conductive pattern (1610, FIG. 24) through the ninth contact hole (CNT9). In addition, the ninth conductive pattern (1720) can also be electrically connected to the storage capacitor (Cst, FIG. 18). The ninth conductive pattern (1720) can be connected to the first storage electrode (CEs1, FIG. 20) of the storage capacitor (Cst, FIG. 18) through the tenth contact hole (CNT10).

[0318] The tenth conductive pattern (1730) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The tenth conductive pattern (1730) may be a connection electrode connecting a third oxide semiconductor pattern (1530, FIG. 23) including a first semiconductor layer (A1, FIG. 23) and a fourth oxide semiconductor pattern (1540, FIG. 23) including a sixth semiconductor layer (A6, FIG. 23). In other words, the tenth conductive pattern (1730) may be a second node electrode (N2) connecting a first transistor (T1, FIG. 24) and a sixth transistor (T6, FIG. 24).

[0319] The tenth conductive pattern (1730) may include a central portion (1730c) overlapping with the third conductive pattern (1310, FIG. 21) and a protrusion (1730p) protruding from the central portion (1730c). The protrusion (1730p) of the tenth conductive pattern (1730) may have a shape extending from the central portion (1730c) in a second direction (e.g., -y direction). The central portion (1730c) of the tenth conductive pattern (1730) may be connected to the third oxide semiconductor pattern (1530, FIG. 23) through the eleventh contact hole (CNT11). The protrusion (1730p) of the tenth conductive pattern (1730) may be connected to the fourth oxide semiconductor pattern (1540, FIG. 23) through the twelfth contact hole (CNT12).

[0320] Additionally, the 10th conductive pattern (1730) may be electrically connected to a storage capacitor (Cst, FIG. 18), a hold capacitor (Chd, FIG. 18), and a first lower gate electrode (G1b, FIG. 8) of a first transistor (T1, FIG. 24). The 10th conductive pattern (1730) may be electrically connected to a third conductive pattern (1310, FIG. 21) including a second storage electrode (CEs2, FIG. 21) and a second hold electrode (CEh2, FIG. 21) through a 13th contact hole (CNT13). The 10th conductive pattern (1730) may be electrically connected to a fourth conductive pattern (1410, FIG. 22) including a first lower gate electrode (G1b, FIG. 8) through a 14th contact hole (CNT14).

[0321] The eleventh conductive pattern (1740) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The eleventh conductive pattern (1740) may have a shape extending along the second direction (e.g., the y direction). The eleventh conductive pattern (1740) may be a connection electrode connecting the first hold electrode (CEh1, FIG. 20) of the hold capacitor (Chd, FIG. 18) and the first oxide semiconductor pattern (1510, FIG. 23) including the seventh semiconductor layer (A7, FIG. 23). One end of the eleventh conductive pattern (1740) may be electrically connected to the second conductive pattern (1220, FIG. 20) including the first hold electrode (CEh1, FIG. 20) through the fifteenth contact hole (CNT15). The other end of the 11th challenge pattern (1740) can be electrically connected to the first oxide semiconductor pattern (1510, FIG. 23) through the 16th contact hole (CNT16).

[0322] The 12th conductive pattern (1750) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The 12th conductive pattern (1750) may have a shape extending along the first direction (e.g., the x-direction). The 12th conductive pattern (1750) may be a connection electrode connecting the third oxide semiconductor pattern (1530, FIG. 23) including the first semiconductor layer (A1, FIG. 23) and the first silicon semiconductor pattern (1110, FIG. 19) including the fifth semiconductor layer (A5, FIG. 19). One end of the 12th conductive pattern (1750) can be electrically connected to the third oxide semiconductor pattern (1530, FIG. 23) through the 17th contact hole (CNT17), and the other end of the 12th conductive pattern (1750) can be electrically connected to the first silicon semiconductor pattern (1110, FIG. 19) through the 18th contact hole (CNT18).

[0323] A horizontal driving voltage line (HPL) may extend along a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The horizontal driving voltage line (HPL) may be electrically connected to a first silicon semiconductor pattern (1110, FIG. 19) through a 19th contact hole (CNT19) to transmit a driving voltage to a fifth transistor (T5, FIG. 20).

[0324] The 13th conductive pattern (1760) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The 13th conductive pattern (1760) may have a shape extending along the first direction (e.g., the x-direction). The 13th conductive pattern (1760) may be a connection electrode connecting the fourth oxide semiconductor pattern (1540, FIG. 23) including the fourth semiconductor layer (A4, FIG. 23) and the sixth semiconductor layer (A6, FIG. 23) and a light-emitting diode (LED, FIG. 8). The 13th challenge pattern (1760) can be electrically connected to the 4th oxide semiconductor pattern (1540, FIG. 23) through the 20th contact hole (CNT20) and can be electrically connected to the repair wiring (RPL, FIG. 21) through the 21st contact hole (CNT21).

[0325] A first horizontal initialization voltage line (HVL1) and a second horizontal initialization voltage line (HVL2) may extend along a first direction (e.g., x-direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The first horizontal initialization voltage line (HVL1) may be electrically connected to a fourth oxide semiconductor pattern (1540, FIG. 23) of the first pixel circuit (PC1) through a twenty-second contact hole (CNT22), and the second horizontal initialization voltage line (HVL2) may be electrically connected to a fourth oxide semiconductor pattern (1540, FIG. 23) of the second pixel circuit (PC2) through a twenty-third contact hole (CNT23).

[0326] The 14th conductive pattern (1770) may have an isolated shape and may be arranged on an imaginary line (IML2) which is a boundary between the second pixel circuit (PC2) and the third pixel circuit (PC3). The 14th conductive pattern (1770) may have a shape extending along the first direction (e.g., the x-direction). The 14th conductive pattern (1770) may be a connecting electrode connecting the fourth oxide semiconductor pattern (1540, FIG. 23) of the third pixel circuit (PC3) and the third horizontal initialization voltage line (HVL3, FIG. 24). The 14th challenge pattern (1770) can be electrically connected to the third horizontal initialization voltage line (HVL3, FIG. 24) through the 24th contact hole (CNT24) and electrically connected to the fourth oxide semiconductor pattern (1540, FIG. 23) of the third pixel circuit (PC3) through the 25th contact hole (CNT25).

[0327] The common voltage line (VSL) can extend along the first direction (e.g., the x direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3).

[0328] Referring to FIG. 26, a sixth conductive layer (1800) may be disposed on a fifth conductive layer (1700). The sixth conductive layer (1800) may include a data line (DL), a vertical driving voltage line (VPL), a vertical initialization voltage line (VVL), a vertical reference voltage line (VRL), a fifteenth conductive pattern (1810), and a sixteenth conductive pattern (1820).

[0329] The data line (DL) may extend along the second direction (e.g., the y direction). The data line (DL) may be electrically connected to the eighth conductive pattern (1710, FIG. 25) and the 26th contact hole (CNT26) connected to the second oxide semiconductor pattern (1520, FIG. 23). The first data line (DL1) may be arranged to pass through the first pixel circuit (PC2), the second data line (DL2) may be arranged to pass through the second pixel circuit (PC2), and the third data line (DL3) may be arranged to pass through the third pixel circuit (PC3) except for some areas.

[0330] The vertical driving voltage line (VPL) may extend along a second direction (e.g., y direction). The vertical driving voltage line (VPL) may include a first vertical driving voltage line (VPL1) disposed on a first pixel circuit (PC1) and a second vertical driving voltage line (VPL2) disposed on a second pixel circuit (PC2). The first vertical driving voltage line (VPL1) may be electrically connected to a horizontal driving voltage line (HPL, FIG. 25) through a 27-1 contact hole (CNT27a), and the second vertical driving voltage line (VPL2) may be electrically connected to a horizontal driving voltage line (HPL, FIG. 25) through a 27-2 contact hole (CNT27b).

[0331] The vertical initialization voltage line (VVL) may extend along the second direction (e.g., the y-direction). The vertical initialization voltage line (VVL) may be arranged between the first vertical driving voltage line (VPL1) and the second vertical driving voltage line (VPL2). The vertical initialization voltage line (VVL) may be electrically connected to the second horizontal initialization voltage line (HVL2, FIG. 25) through the 28th contact hole (CNT28).

[0332] The vertical reference voltage line (VVRL) may extend along the second direction (e.g., the y-direction). The vertical reference voltage line (VVRL) may be arranged on the third pixel circuit (PC3). The vertical reference voltage line (VVRL) may be electrically connected to the second horizontal reference voltage line (HVRL2, FIG. 25) through the 29th contact hole (CNT29).

[0333] The 15th conductive pattern (1810) and the 16th conductive pattern (1820) may each have an isolated shape. The 15th conductive pattern (1810) may be electrically connected to the 10th conductive pattern (1730, FIG. 25) through the 30th contact hole (CNT30) and may have a shape extending along the second direction (e.g., the y direction) to cover the 9th conductive pattern (1720, FIG. 25). The 16th conductive pattern (1820) may be a connecting electrode connecting the 4th oxide semiconductor pattern (1540, FIG. 23) and a light-emitting diode (LED, FIG. 8). The 16th challenge pattern (1820) can be electrically connected to the 13th challenge pattern (1760, FIG. 25) through the 31st contact hole (CNT31) and can be electrically connected to the pixel electrode (210, FIG. 8) of a light-emitting diode (LED, FIG. 8) through the 32nd contact hole (CNT32).

[0334] Fig. 27 is an enlarged plan view of a portion of a display panel according to another embodiment of the present invention. For convenience of explanation, Fig. 27 illustrates a structure in which only a silicon semiconductor layer (1100, Fig. 19), a first conductive layer (1200, Fig. 20), a second conductive layer (1300, Fig. 21), a third conductive layer (1400, Fig. 22), an oxide semiconductor layer (1500, Fig. 23), a fourth conductive layer (1600, Fig. 24), and a fifth conductive layer (1700, Fig. 25) are accumulated.

[0335] Referring to FIG. 27, the hold gate line (GHL) may include a stem portion (GHt) extending in a first direction (e.g., x-direction) and a branch portion (GHb) protruding from the stem portion. The stem portion (GHt) of the hold gate line (GHL) may extend along the first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The stem portion (GHt) of the hold gate line (GHL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0336] The branch portion (GHb) of the hold gate line (GHL) may include a vertical branch portion (GHvb) that protrudes from the stem portion (GHt) and extends in a second direction (e.g., in the y direction), and a horizontal branch portion (GHhb) that protrudes from the vertical branch portion (GHvb) and extends in a first direction (e.g., in the x direction). The horizontal branch portion (GHhb) of the hold gate line (GHL) may include a region overlapping with the first oxide semiconductor pattern (1510, FIG. 23), i.e., the seventh gate electrode (G7) of the seventh transistor (T7).

[0337] The vertical branch (GHvb) may include a first vertical branch (GHvb1) protruding toward the seventh transistor (T7) of the first pixel circuit (PC1), and a second vertical branch (GHvb2) protruding toward the seventh transistor (T7) of the second pixel circuit (PC2) and the seventh transistor (T7) of the third pixel circuit (PC3). The first vertical branch (GHvb1) may be arranged to the left of the tenth conductive pattern (1730) of the first pixel circuit (PC1) within the area of ​​the first pixel circuit (PC1). The second vertical branch (GHvb2) may be arranged on an imaginary line (IML2) which is a boundary between the second pixel circuit (PC2) and the third pixel circuit (PC3). A portion of the second vertical branch (GHvb2) may be arranged in the area of ​​the second pixel circuit (PC2), and the remaining portion may be arranged in the area of ​​the third pixel circuit (PC3). For example, the second vertical branch (GHvb2) may be arranged between the tenth conductive pattern (1730) of the second pixel circuit (PC2) and the tenth conductive pattern (1730) of the third pixel circuit (PC3).

[0338] The horizontal branch (GHvb) may include a first horizontal branch (GHhb1) including a seventh gate electrode (G7) of a first pixel circuit (PC1), a second horizontal branch (GHhb2) including a seventh gate electrode (G7) of a second pixel circuit (PC2), and a third horizontal branch (GHhb3) including a seventh gate electrode (G7) of a third pixel circuit (PC3). The first horizontal branch (GHhb1) may be a portion protruding from the end of the first vertical branch (GHvb1) toward the tenth conductive pattern (1730), the second horizontal branch (GHhb1) may be a portion protruding from the end of the second vertical branch (GHvb2) toward the tenth conductive pattern (1730), and the third horizontal branch (GHhb3) may be a portion protruding from the end of the second vertical branch (GHvb2) toward the tenth conductive pattern (1730).

[0339] However, the structure of the hold gate line (GHL) is not necessarily limited thereto. In another embodiment, the vertical branch portion (GHvb) may include a first vertical branch portion, a second vertical branch portion, and a third vertical branch portion that protrude from the stem portion (GHt) and extend in a second direction (e.g., the y direction). The first to third vertical branches may be arranged on the left side of the tenth conductive pattern (1730) of the corresponding pixel circuit, respectively. In this case, the first to third horizontal branches may be integrally connected to the first to third vertical branches, respectively.

[0340] An area overlapping with the hold gate line (GHL) among the first oxide semiconductor patterns (1510) may become a channel area (C7) of the seventh transistor (T7). One end of the first oxide semiconductor pattern (1510) may be connected to a second horizontal reference voltage line (HVRL2, FIG. 25), so that the seventh transistor (T7) may receive a reference voltage. The other end of the first oxide semiconductor pattern (1510) may be electrically connected to a first hold electrode (CEh1, FIG. 20) of a hold capacitor (Chd, FIG. 18) included in the second conductive pattern (1220) via the eleventh conductive pattern (1740).

[0341] In one embodiment, the hold gate line (GHL) may be arranged to cross between the first transistor (T1) and the fifth transistor (T5) on a planar surface. For example, the hold gate line (GHL) may be arranged to cross between the third oxide semiconductor pattern (1530) on which the first semiconductor layer (A1, FIG. 23) is arranged on a planar surface and the first silicon semiconductor pattern (1110) on which the fifth semiconductor layer (A5, FIG. 19) is arranged.

[0342] As the hold gate line (GHL) is arranged to cross the first transistor (T1) and the fifth transistor (T5), the hold gate line (GHL) may be arranged to overlap with a connection electrode connecting the first transistor (T1) and the fifth transistor (T5). Specifically, the hold gate line (GHL) may include a second overlapping area (OA2) overlapping with the twelfth conductive pattern (1750). In this case, the twelfth conductive pattern (1750) may be a third node electrode (N3) connecting the first semiconductor layer (A1, FIG. 23) and the fifth semiconductor layer (A5, FIG. 19).

[0343] In one embodiment, the hold gate line (GHL) may be arranged to cross between the first transistor (T1) and the sixth transistor (T6) on a plane. For example, the hold gate line (GHL) may be arranged to cross between the third oxide semiconductor pattern (1530) on which the first semiconductor layer (A1, FIG. 23) is arranged on a plane and the fourth oxide semiconductor pattern (1540) on which the sixth semiconductor layer (A6, FIG. 23) is arranged.

[0344] As the hold gate line (GHL) is arranged to cross the first transistor (T1) and the sixth transistor (T6), the hold gate line (GHL) may be arranged to overlap with a connection electrode connecting the first transistor (T1) and the sixth transistor (T6). Specifically, the hold gate line (GHL) may include a third overlapping area (OA3) overlapping with a protrusion (1730p) of the tenth conductive pattern (1730). The protrusion (1730p) of the tenth conductive pattern (1730) may be an area protruding in a second direction (e.g., -y direction) from the center (1730c). In this case, the tenth conductive pattern (1730) may be a second node electrode (N2) connecting the first semiconductor layer (A1, FIG. 23) and the sixth semiconductor layer (A6, FIG. 23).

[0345] In conclusion, the hold gate line (GHL) may include a second overlapping area (OA2) overlapping with the 12th conductive pattern (1750), which is the third node electrode (N3), and a third overlapping area (OA3) overlapping with the protrusion (1730p) of the 10th conductive pattern (1730), which is the second node electrode (N2).

[0346] According to an embodiment of the present invention, a display panel includes a seventh transistor (T7) connected to a hold capacitor (Chd) and a hold gate line (GHL), and thus the hold capacitor (Chd) can be controlled through a hold signal transmitted to the hold gate line (GHL). At this time, as shown in FIG. 27, when the display panel includes the seventh transistor (T7) and the hold gate line (GHL) connected to the hold capacitor (Chd), the hold capacitor (Chd) can be controlled to be formed only in the data writing section and the compensation section, and to be blocked in the light emission section. When the hold capacitor (Chd) is blocked in the light emission section, the voltages of the second node electrode (N2) and the first node electrode (N1) can be maintained more stably, and thus the coupling of the pixel circuit can be formed more robustly.

[0347] Meanwhile, as the hold gate line (GHL) extends along the first direction (e.g., x-direction), the hold gate line (GHL) may inevitably partially overlap with the node electrode of the first transistor (T1). For example, as shown in FIG. 27, when the hold gate line (GHL) is arranged to cross between the first transistor (T1) and the fifth transistor (T5) and between the first transistor (T1) and the sixth transistor (T6), the hold gate line (GHL) may overlap with each of the second node electrode (N2) and the third node electrode (N3).

[0348] As shown in Fig. 27, when the hold gate line (GHL) includes only the second overlapping area (OA2) and the third overlapping area (OA3), the hold gate line (GHL) may not overlap the first node electrode (N1, Fig. 25). Accordingly, in the display panel according to another embodiment of the present invention, since unexpected coupling between the first node electrode (N1, Fig. 25) and the hold gate line (GHL) does not occur, defects such as a brighter image than the reference when implementing a monochrome image can be prevented, and a high-quality image can be implemented.

[0349] The embodiments described herein are to be understood as illustrative, not limiting. The description of features or aspects in each embodiment should generally be considered applicable to similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the drawings, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. Substrate; A first pixel circuit disposed on the substrate and including a driving transistor; and A light emitting diode connected to the first pixel circuit; The above first pixel circuit, A first conductive pattern disposed on the substrate; A second challenge pattern disposed on the first challenge pattern and arranged to overlap with the first challenge pattern; A first semiconductor pattern including a semiconductor layer of the driving transistor disposed on the second conductive pattern; A second semiconductor pattern disposed on the same layer as the first semiconductor pattern, but spaced apart from the first semiconductor pattern; and A third conductive pattern is disposed on the first semiconductor pattern and connects the first semiconductor pattern and the second conductive pattern; The above first challenge pattern is electrically connected to the above second semiconductor pattern, A display panel, wherein a portion of the second semiconductor pattern extends along the first direction and overlaps a hold gate line electrically connected to the first pixel circuit.

2. In paragraph 1, A display panel, wherein the first conductive pattern and the second conductive pattern form a hold capacitor of the first pixel circuit.

3. In paragraph 1, Further comprising a reference voltage line extending along the first direction and electrically connected to the first pixel circuit; One end of the second semiconductor pattern is electrically connected to the first conductive pattern, A display panel, wherein the other end of the second semiconductor pattern is electrically connected to the reference voltage line.

4. In paragraph 3, The first pixel circuit further includes a fourth conductive pattern disposed on the same layer as the third conductive pattern, but spaced apart from the third conductive pattern; A display panel, wherein the second semiconductor pattern is electrically connected to the first conductive pattern through the fourth conductive pattern.

5. In paragraph 1, Based on the thickness direction of the above substrate, A display panel, wherein the above-mentioned hold gate line is disposed between the first semiconductor pattern and the third conductive pattern.

6. In paragraph 5, A display panel wherein the above hold gate line is arranged on the same layer as the gate electrode of the driving transistor.

7. In paragraph 1, The above first pixel circuit, A third semiconductor pattern disposed on the same layer as the first semiconductor pattern, but spaced apart from the first semiconductor pattern; Further comprising a fifth conductive pattern connecting the gate electrode of the driving transistor and the third semiconductor pattern; A display panel in which the fifth challenge pattern is arranged on the same layer as the third challenge pattern.

8. In paragraph 7, A scan line extending along the first direction and electrically connected to the first pixel circuit; and Further comprising a data line extending along a second direction intersecting the first direction and electrically connected to the first pixel circuit; A portion of the third semiconductor pattern overlaps a portion of the scan line, A display panel in which one end of the third semiconductor pattern is electrically connected to the data line.

9. In paragraph 7, A display panel, wherein on a plane, the hold gate line is arranged to cross between the first semiconductor pattern and the third semiconductor pattern.

10. In paragraph 7, A display panel, wherein, on a plane, a portion of the hold gate line overlaps with the fifth conductive pattern.

11. In paragraph 1, The above first pixel circuit, A fourth semiconductor pattern disposed between the substrate and the first conductive pattern; Further comprising a sixth conductive pattern connecting one end of the first semiconductor pattern and the fourth semiconductor pattern; A display panel in which the sixth challenge pattern is arranged on the same layer as the third challenge pattern.

12. In paragraph 11, A display panel wherein the first semiconductor pattern and the fourth semiconductor pattern include different materials.

13. In paragraph 12, A display panel, wherein the first semiconductor pattern includes an oxide semiconductor material, and the fourth semiconductor pattern includes a silicon semiconductor material.

14. In paragraph 11, A first light-emitting control line extending along the first direction and electrically connected to the first pixel circuit; and Further comprising a driving voltage line extending along the first direction or a second direction intersecting the first direction and electrically connected to the first pixel circuit; A part of the fourth semiconductor pattern overlaps with the first light-emitting control line, A display panel, wherein one end of the fourth semiconductor pattern is electrically connected to the driving voltage line.

15. In paragraph 11, A display panel, wherein on a plane, the hold gate line is arranged to cross between the first semiconductor pattern and the fourth semiconductor pattern.

16. In paragraph 11, A display panel, wherein, on a plane, a portion of the hold gate line overlaps with the sixth conductive pattern.

17. In paragraph 1, The above first pixel circuit, Further comprising a fifth semiconductor pattern disposed on the same layer as the first semiconductor pattern, but spaced apart from the first semiconductor pattern; The third challenge pattern includes a central portion and a protrusion branching from the central portion, A display panel in which the protrusion of the third challenge pattern is electrically connected to the fifth semiconductor pattern.

18. In paragraph 17, A second light-emitting control line extending along the first direction and electrically connected to the first pixel circuit; and A part of the fifth semiconductor pattern overlaps with the second light-emitting control line, A display panel, wherein one end of the fifth semiconductor pattern is electrically connected to the light-emitting diode.

19. In paragraph 17, A display panel, wherein on a plane, the hold gate line is arranged to cross between the first semiconductor pattern and the fifth semiconductor pattern.

20. In paragraph 17, A display panel, wherein, on a plane, a portion of the hold gate line overlaps with a protrusion of the third conductive pattern.

21. Substrate; A first pixel circuit arranged on the substrate; A hold gate line extending along the first direction and electrically connected to the first pixel circuit; and A light emitting diode electrically connected to the first pixel circuit; The above first pixel circuit, 1st transistor; A first connecting electrode connecting the first transistor and the light-emitting diode; A hold capacitor including a first hold electrode and a second hold electrode facing the first hold electrode and electrically connected to the first connection electrode; A second transistor electrically connected to the first hold electrode; A display panel, wherein the hold gate line includes a gate electrode of the second transistor.

22. In paragraph 21, Based on the thickness direction of the above substrate, The second hold electrode is placed on the first hold electrode, The semiconductor layer of the first transistor is disposed on the second hold electrode, A display panel in which the first connection electrode is disposed on the semiconductor layer of the first transistor.

23. In paragraph 22, Based on the thickness direction of the above substrate, A display panel in which the above-mentioned hold gate line is interposed between the semiconductor layer of the first transistor and the first connection electrode.

24. In paragraph 21, The above first pixel circuit, a third transistor connected between the data line and the gate electrode of the first transistor; and A display panel further comprising a fourth transistor connected between a reference voltage line and a gate electrode of the first transistor.

25. In paragraph 24, The display panel, wherein the second transistor is connected between the hold capacitor and the reference voltage line.

26. In paragraph 24, A display panel, wherein on a plane, the hold gate line is arranged to cross between the first transistor and the third transistor.

27. In paragraph 24, The first pixel circuit further includes a second connection electrode connecting the gate electrode of the first transistor and the semiconductor layer of the second transistor; A display panel in which a portion of the above hold gate line overlaps with the second connection electrode.

28. In paragraph 27, A display panel wherein the second connecting electrode is disposed on the same layer as the first connecting electrode, but is disposed spaced apart from each other.

29. In paragraph 21, The above first pixel circuit, A fifth transistor connected between the driving voltage line and the first transistor; and A display panel further comprising a sixth transistor connected between the first transistor and the light emitting diode.

30. In paragraph 29, The above hold gate line is, a stem portion extending along the first direction; and A display panel comprising a branch portion branching from the stem portion and extending in a second direction intersecting the first direction.

31. In paragraph 30, A display panel in which the gate electrode of the second transistor is formed on a branch portion of the hold gate line.

32. In paragraph 30, A display panel, wherein, on a plane, the stem of the hold gate line is arranged to cross between the first transistor and the fifth transistor.

33. In paragraph 30, The above first connection electrode is connected to the semiconductor layer of the sixth transistor, A display panel, wherein a portion of the stem of the above-mentioned hold gate line overlaps with the first connection electrode.

34. In paragraph 30, The first pixel circuit further includes a third connection electrode connecting the semiconductor layer of the first transistor and the semiconductor layer of the fifth transistor; A display panel, wherein a portion of the stem of the above-mentioned hold gate line overlaps with the third connecting electrode.

35. In paragraph 34, A display panel wherein the third connecting electrode is disposed on the same layer as the first connecting electrode, but is disposed spaced apart from the first connecting electrode.

36. In paragraph 29, A display panel in which the semiconductor layer of the first transistor and the semiconductor layer of the fifth transistor are arranged on different layers.

37. In paragraph 36, The semiconductor layer of the first transistor includes an oxide semiconductor material, A display panel, wherein the semiconductor layer of the fifth transistor includes a silicon-based semiconductor material.

38. In paragraph 21, Further comprising a second pixel circuit disposed on the substrate and adjacent to the first pixel circuit along the first direction; The first transistor, the hold capacitor, and the second transistor of the first pixel circuit, A display panel having line symmetry based on an imaginary straight line extending in a second direction intersecting the first direction with respect to each of the first transistor, the hold capacitor, and the second transistor of the second pixel circuit.

39. In paragraph 38, Further comprising a third pixel circuit arranged on the substrate and arranged adjacent to the second pixel circuit along the first direction; The first transistor, the hold capacitor, and the second transistor of the second pixel circuit are A display panel having line symmetry based on an imaginary straight line extending in a second direction intersecting the first direction, with respect to each of the first transistor, the hold capacitor, and the second transistor of the third pixel circuit.

40. In paragraph 39, The above hold gate line is a stem portion extending along the first direction; and including a branch portion branching from the stem portion and extending in the second direction; The branch of the above hold gate line is, A first branch portion protruding toward the second transistor of the first pixel circuit; and A display panel including a second branch portion protruding toward the second transistor of the second pixel circuit and the second transistor of the third pixel circuit.

41. Display panel; and A lower cover forming an exterior and having an opening exposing a portion of the display panel on the front surface; The above display panel, substrate; A first pixel circuit disposed on the substrate and including a driving transistor; A hold gate line extending along the first direction and electrically connected to the first pixel circuit; A light emitting diode connected to the first pixel circuit; The above first pixel circuit A first conductive pattern disposed on the substrate; A second challenge pattern disposed on the first challenge pattern and arranged to overlap with the first challenge pattern; A first semiconductor pattern including a semiconductor layer of the driving transistor disposed on the second conductive pattern; A second semiconductor pattern disposed on the same layer as the first semiconductor pattern, but spaced apart from the first semiconductor pattern; A third conductive pattern disposed on the first semiconductor pattern and connecting the first semiconductor pattern and the second conductive pattern; The above first challenge pattern is electrically connected to the above second semiconductor pattern, An electronic device, wherein a portion of the second semiconductor pattern overlaps with the hold gate line.

42. In paragraph 41, An electronic device wherein the first conductive pattern and the second conductive pattern form a hold capacitor of the first pixel circuit.

43. In paragraph 41, The display panel further includes a reference voltage line extending along the first direction and electrically connected to the first pixel circuit; One end of the second semiconductor pattern is electrically connected to the first conductive pattern, An electronic device, wherein the other end of the second semiconductor pattern is electrically connected to the reference voltage line.

44. In paragraph 41, The above first pixel circuit, A third semiconductor pattern disposed on the same layer as the first semiconductor pattern, but spaced apart from the first semiconductor pattern; Further comprising a fourth conductive pattern connecting the gate electrode of the driving transistor and the third semiconductor pattern; An electronic device, wherein on a plane, the hold gate line is arranged to cross between the first semiconductor pattern and the third semiconductor pattern.

45. In paragraph 44, A scan line extending along the first direction and electrically connected to the first pixel circuit; and Further comprising a data line extending along a second direction intersecting the first direction and electrically connected to the first pixel circuit; A portion of the third semiconductor pattern overlaps a portion of the scan line, An electronic device, wherein one end of the third semiconductor pattern is electrically connected to the data line.

46. ​​In paragraph 44, The fourth challenge pattern is arranged on the same layer as the third challenge pattern, An electronic device, wherein, on a plane, a portion of the hold gate line overlaps with the fourth conductive pattern.

47. In paragraph 41, The above first pixel circuit, A fourth semiconductor pattern positioned below the first challenge pattern; Further comprising a fifth conductive pattern connecting one end of the first semiconductor pattern and the fourth semiconductor pattern; An electronic device, wherein on a plane, the hold gate line is arranged to cross between the first semiconductor pattern and the fourth semiconductor pattern.

48. In paragraph 47, A first light-emitting control line extending along the first direction and electrically connected to the first pixel circuit; and Further comprising a driving voltage line extending along the first direction or a second direction intersecting the first direction and electrically connected to the first pixel circuit; A part of the fourth semiconductor pattern overlaps with the first light-emitting control line, An electronic device, wherein one end of the fourth semiconductor pattern is electrically connected to the driving voltage line.

49. In paragraph 47, An electronic device, wherein the first semiconductor pattern includes an oxide semiconductor material, and the fourth semiconductor pattern includes a silicon semiconductor material.

50. In paragraph 47, The fifth challenge pattern is arranged on the same layer as the third challenge pattern, An electronic device, wherein, on a plane, a portion of the hold gate line overlaps with the fifth conductive pattern.

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