Display device and electronic device comprising same

Abstract

An embodiment of the present invention provides a display device comprising: a substrate; a first pixel circuit disposed on the substrate and including a driving transistor and a storage capacitor; a light-emitting diode electrically connected to the first pixel circuit; and a repair line disposed on the substrate and extending in a first direction, wherein the first pixel circuit further includes: a first pixel connection electrode electrically connected to a pixel electrode of the light-emitting diode; and a repair bridge pattern disposed between the repair line and the first pixel connection electrode, and when viewed in a direction perpendicular to the substrate, the repair bridge pattern overlaps each of the repair line and the first pixel connection electrode.

Description

Display device and electronic device including same

[0001] The present invention relates to a display device and an electronic device including the same.

[0002] In recent years, display devices have become increasingly versatile. Furthermore, as their applications expand, the demand for high-resolution displays is increasing. Manufacturing high-resolution displays requires arranging electronic components of various configurations within a narrow area.

[0003] Embodiments of the present invention aim to provide a display device with improved display quality and an electronic device including the same. However, these tasks are exemplary and should not be construed as limiting the scope of the present invention.

[0004] One embodiment of the present invention provides a display device including: a substrate; a first pixel circuit disposed on the substrate, the first pixel circuit including a driving transistor and a storage capacitor; a light emitting diode electrically connected to the first pixel circuit; and a repair line disposed on the substrate and extending in a first direction; wherein the first pixel circuit further includes: a first pixel connection electrode electrically connected to a pixel electrode of the light emitting diode; and a repair bridge pattern disposed between the repair line and the first pixel connection electrode; wherein, when viewed in a direction perpendicular to the substrate, the repair bridge pattern overlaps the repair line and the first pixel connection electrode.

[0005] In one embodiment, the first pixel circuit may further include: a first conductive pattern disposed on the substrate and including a first electrode of the storage capacitor; a second conductive pattern disposed on the first conductive pattern to overlap the first conductive pattern and including a second electrode of the storage capacitor; a third conductive pattern disposed on the second conductive pattern and including a lower gate electrode of the driving transistor; a first semiconductor pattern disposed on the third conductive pattern and including a semiconductor layer of the driving transistor; and a fourth conductive pattern disposed on the first semiconductor pattern and including an upper gate electrode of the driving transistor.

[0006] In one embodiment, the repair line may be disposed on the same layer as the first conductive pattern or the second conductive pattern, and the repair bridge pattern may be disposed on the same layer as the third conductive pattern.

[0007] In one embodiment, the first semiconductor pattern may include an oxide semiconductor material.

[0008] In one embodiment, the first pixel circuit may further include a fifth conductive pattern disposed on the fourth conductive pattern and disposed on the same layer as the first pixel connection electrode; a second semiconductor pattern disposed on the same layer as the first semiconductor pattern, connected to the fifth conductive pattern, and including a semiconductor layer of a light-emitting control transistor;

[0009] In one embodiment, when viewed in a direction perpendicular to the substrate, a first portion of the first pixel connection electrode may overlap the second semiconductor pattern, and a second portion of the first pixel connection electrode may overlap the repair bridge pattern.

[0010] In one embodiment, the first pixel circuit further includes a second pixel connection electrode disposed on the first pixel connection electrode and connecting the first pixel connection electrode and the light-emitting diode; and the first pixel connection electrode and the second pixel connection electrode can electrically connect the second semiconductor pattern and the light-emitting diode.

[0011] In one embodiment, the first pixel circuit further includes a plurality of voltage lines disposed on the substrate and extending in the first direction or a second direction intersecting the first direction; wherein the first pixel circuit further includes a dummy wiring disposed on the same layer as the repair bridge pattern and extending in the first direction; wherein the dummy wiring can be electrically connected to at least one of the plurality of voltage lines.

[0012] In one embodiment, the plurality of voltage lines include a reference voltage line extending in the first direction, the first pixel circuit further includes a reference transistor connected between the driving transistor and the reference voltage line, and the dummy wiring can be electrically connected to the reference voltage line.

[0013] In one embodiment, the reference voltage line includes an upper reference voltage line disposed on the same layer as the first pixel connection electrode, and the dummy wiring can be connected to the upper reference voltage line through a contact hole.

[0014] In one embodiment, the reference voltage line further includes a lower reference voltage line positioned lower than the upper reference voltage line, and the lower reference voltage line may include a silicon semiconductor material.

[0015] In one embodiment, the plurality of voltage lines extend in the first direction and include a common voltage line electrically connected to the light emitting diode, and the dummy wiring can be electrically connected to the common voltage line.

[0016] In one embodiment, the plurality of voltage lines include a driving voltage line extending in the first direction, the first pixel circuit further includes a driving control transistor connected between the driving transistor and the driving voltage line, and the dummy wiring can be electrically connected to the driving voltage line.

[0017] In one embodiment, the plurality of voltage lines include an initialization voltage line extending in the first direction, and the first pixel circuit further includes a light-emitting control transistor connected between the driving transistor and the light-emitting diode; and an initialization transistor connected between the light-emitting control transistor and the initialization voltage line; and the dummy wiring can be electrically connected to the initialization voltage line.

[0018] Another embodiment of the present invention provides an electronic device comprising: a substrate; a first pixel circuit disposed on the substrate, the first pixel circuit including a first transistor and a storage capacitor; a light-emitting diode electrically connected to the first pixel circuit; and a plurality of voltage lines disposed on the substrate and extending in a first direction; wherein the first pixel circuit further comprises: a first conductive pattern including a lower gate electrode of the first transistor; and a dummy wiring disposed on the same layer as the first conductive pattern and extending in the first direction; wherein the dummy wiring is electrically connected to at least one of the plurality of voltage lines.

[0019] In one embodiment, the device further includes a data line extending in a second direction intersecting the first direction and connected to the first pixel circuit; wherein the plurality of voltage lines include a reference voltage line extending in the first direction; and wherein the first pixel circuit further includes a second transistor connected between the data line and the first transistor; and a third transistor connected between the reference voltage line and the first transistor; wherein the dummy wiring can be electrically connected to the reference voltage line.

[0020] In one embodiment, the plurality of voltage lines extend in the first direction and include a common voltage line electrically connected to the light emitting diode, and the dummy wiring can be electrically connected to the common voltage line.

[0021] In one embodiment, the plurality of voltage lines include an initialization voltage line extending in the first direction, the first pixel circuit further includes a fourth transistor connected between the initialization voltage line and the light-emitting diode, and the dummy wiring can be electrically connected to the initialization voltage line.

[0022] In one embodiment, the plurality of voltage lines include a driving voltage line extending in the first direction, the first pixel circuit further includes a fifth transistor connected between the driving voltage line and the first transistor, and the dummy wiring can be electrically connected to the driving voltage line.

[0023] In one embodiment, the semiconductor layer of the first transistor and the semiconductor layer of the fifth transistor may be disposed on different layers.

[0024] In one embodiment, the first pixel circuit further includes a repair line disposed on the substrate and extending in the first direction; and the first pixel circuit further includes a first pixel connection electrode electrically connected to the pixel electrode of the light-emitting diode; and a repair bridge pattern disposed between the repair line and the first pixel connection electrode, the repair bridge pattern being disposed on the same layer as the first conductive pattern; and when viewed in a direction perpendicular to the substrate, the repair bridge pattern may overlap each of the repair line and the first pixel connection electrode.

[0025] In one embodiment, the first pixel circuit further includes a second conductive pattern disposed on the substrate and including a first electrode of the storage capacitor; and a third conductive pattern disposed on the second conductive pattern and including a second electrode of the storage capacitor; wherein the repair line may be disposed on the same layer as the second conductive pattern or the third conductive pattern.

[0026] Another embodiment of the present invention provides an electronic device including a display device, the display device including: a substrate; a first pixel circuit disposed on the substrate and including a driving transistor and a storage capacitor; a light emitting diode electrically connected to the first pixel circuit; and a repair line disposed on the substrate and extending in a first direction; wherein the first pixel circuit further includes: a first pixel connection electrode electrically connected to a pixel electrode of the light emitting diode; and a repair bridge pattern disposed between the repair line and the first pixel connection electrode; wherein, when viewed in a direction perpendicular to the substrate, the repair bridge pattern overlaps each of the repair line and the first pixel connection electrode.

[0027] According to some embodiments of the present invention, a display device and an electronic device capable of providing high-quality images can be provided. The aforementioned effects are exemplary, and the effects of the present invention are not limited to those described above.

[0028] A more complete understanding of this specification and its various aspects may be more readily obtained by reading the detailed description taken in conjunction with the following drawings.

[0029] FIG. 1 is a plan view schematically illustrating a display device according to one embodiment of the present invention.

[0030] FIG. 2 is a side view schematically illustrating a display device according to one embodiment of the present invention.

[0031] Figure 3 is a plan view schematically showing a display device according to one embodiment of the present invention.

[0032] FIG. 4A is a drawing schematically illustrating a part of a display device according to one embodiment of the present invention.

[0033] FIG. 4b is a drawing for explaining a method of repairing a defective pixel in a display device according to one embodiment of the present invention.

[0034] FIG. 5 is an equivalent circuit diagram of a light-emitting diode and pixel circuit of a display device according to one embodiment of the present invention.

[0035] FIG. 6 is a plan view schematically illustrating pixel circuits of a display device according to one embodiment of the present invention.

[0036] FIG. 7 is a schematic cross-sectional view of a display device according to one embodiment of the present invention, showing a cross-section taken along line VII-VII' of FIG. 3.

[0037] FIGS. 8 to 15 are plan views illustrating a process for forming a pixel circuit of a display device according to one embodiment of the present invention.

[0038] FIG. 16a and FIG. 16b are plan views schematically showing pixel circuits of a display device according to one embodiment of the present invention, respectively.

[0039] FIG. 17a and FIG. 17b are plan views schematically showing pixel circuits of a display device according to one embodiment of the present invention, respectively.

[0040] FIG. 18a and FIG. 18b are plan views schematically illustrating pixel circuits of a display device according to one embodiment of the present invention, respectively.

[0041] Figure 19 is a block diagram of an electronic device according to one embodiment of the present invention.

[0042] FIG. 20 is a schematic diagram of electronic devices according to various embodiments of the present invention.

[0043] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals may represent the same or similar elements throughout the specification and drawings. Even if a particular element is not described in detail in the drawings, it will be understood that the element is at least similar to a corresponding element described elsewhere in the specification.

[0045] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0046] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0047] In the examples below, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0048] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0049] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0050] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0051] In the following examples, when it is said that a film, region, component, etc. are connected, it includes not only cases where the films, regions, and components are directly connected, but also cases where other films, regions, and components are interposed between the films, regions, and components and thus indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it includes not only cases where the films, regions, and components are directly electrically connected, but also cases where other films, regions, and components are interposed between them and thus indirectly electrically connected.

[0052] Embodiments of the present invention relate to a display device design including a repair bridge pattern to improve reliability, manufacturability, and repairability in high-resolution electronic displays such as OLED panels.

[0053] A display device may include a substrate having pixel circuits arranged thereon. Each pixel circuit includes a driving transistor, a storage capacitor, and a light-emitting diode (LED) electrically connected to the circuit. One of the key features of the present invention is the integration of a repair line and a repair bridge pattern. The repair bridge pattern is formed to physically overlap both the repair line and the first pixel connection electrode in a plan view, thereby providing a means for simply and efficiently repairing defective pixel circuits after manufacturing.

[0054] Each pixel circuit is precisely laminated, with multiple conductive and semiconductor patterns stacked vertically and interconnected. Repair lines can be formed on the same layer as the underlying conductive patterns, and repair bridge patterns are aligned with upper conductive patterns, such as gate electrodes. This configuration enables precision laser repair, insulating defective pixel circuits and replacing them with healthy circuits via dummy lines and repair bridges. Furthermore, the use of oxide semiconductors in the transistor layer enables high electron mobility and low leakage current, meeting the performance requirements of modern displays.

[0055] Additionally, the display device includes dummy circuits and dummy lines strategically connected to the voltage lines. These dummy structures allow signals and voltages to be diverted around defective pixels without altering the main data drive mechanism. This design facilitates repairs by allowing post-manufacturing laser processing to melt insulating layers or conductive bridges at specific points, connecting or breaking electrical paths.

[0056] In broader applications, this display device can be applied to foldable or flexible electronic devices, enhancing their durability and lifespan by facilitating field repair and defect management. The laminated structure and repair-friendly architecture provide a robust solution for maintaining high production yields and ensuring high-quality displays in commercial electronic devices.

[0057] FIG. 1 is a plan view schematically illustrating a display device (1) according to one embodiment of the present invention, and FIG. 2 is a side view schematically illustrating a display device (1) according to one embodiment of the present invention.

[0058] A display device (1) may include a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) is a portion that displays an image, and a plurality of pixels may be arranged. The display area (DA) may have various shapes, such as a circle, an oval, a polygon, or a shape of a specific shape. For example, Fig. 1 illustrates that the display area (DA) has a roughly rectangular shape with rounded corners.

[0059] A peripheral area (PA) may be arranged outside the display area (DA). The peripheral area (PA) may include a first peripheral area (PA1) arranged to surround at least a portion of the display area (DA) and a second peripheral area (PA2) adjacent to one side of the display area (DA) and extending in a second direction (e.g., -y direction). A width of the second peripheral area (PA2) along the first direction (e.g., x-axis direction) may be narrower than a width of the display area (DA). This structure may facilitate bending of at least a portion of the second peripheral area (PA2).

[0060] The shape of the plane of the display device (1) illustrated in FIG. 1 may be substantially the same as the shape of the substrate (100) included in the display device (1). When the display device (1) is said to include a display area (DA) and a peripheral area (PA) outside the display area (DA), this may indicate that the substrate (100) includes the display area (DA) and a peripheral area (PA) outside the display area (DA). Hereinafter, for convenience, it will be described that the substrate (100) has a display area (DA) and a peripheral area (PA).

[0061] The display device (1) may include a main region (MR), a bending region (BR) outside the main region (MR), and a sub-region (SR) spaced apart from the main region (MR) with the bending region (BR) therebetween. The main region (MR) may be arranged on one side of the bending region (BR), and the sub-region (SR) may be arranged on the other side of the bending region (BR). The display device (1) may be bent in the bending region (BR) as illustrated in FIG. 2, and at least a portion of the sub-region (SR) may overlap the main region (MR) when viewed in a third direction (e.g., the z-direction). Although FIG. 2 illustrates the display device (1) being bent, the present invention is not limited thereto. In another embodiment, the display device (1) is a foldable display device, and the display region (DA) may be bent around a bending axis crossing the display region (DA). In yet another embodiment, the display device (1) may not be bent. The sub-region (SR) may be a non-display area.

[0062] A data driver (20) may be placed in a sub-region (SR) of a display device (1). The data driver (20) may be placed in the display device (1) in the form of an integrated circuit (IC). For example, the data driver (20) may be a data driving integrated circuit that generates a data signal.

[0063] A display circuit board (30) may be attached to an end of a sub-area (SR) of a display device (1). The display circuit board (30) may be electrically connected to a data driver (20) or the like through a pad of the sub-area (SR) of the display device (1).

[0064] Figure 3 is a plan view schematically showing a display device (1) according to one embodiment of the present invention.

[0065] Referring to FIG. 3, the display device (1) may include a substrate (100). Various components constituting the display device (1) may be arranged on the substrate (100).

[0066] The substrate (100) may include glass, metal, or a polymer resin. The substrate (100) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate (100) may have a multilayer structure including two layers including the aforementioned polymer resin and an inorganic layer interposed between the layers.

[0067] Pixels are arranged in a display area (DA), and the display area (DA) can provide an image using light emitted from the pixels. Each pixel can include a light-emitting diode (LED), and the light-emitting diode (LED) can be electrically connected to a pixel circuit (PC). The pixel circuit (PC) and the light-emitting diode (LED) can be arranged in the display area (DA).

[0068] A gate driving circuit (e.g., a first scan driving circuit (11), a second scan driving circuit (12)), a light emission control driving circuit (13), a pad (14), a first power supply wiring (15), and a second power supply wiring (16) can be arranged in the peripheral area (PA).

[0069] The first scan driving circuit (11) can provide a scan signal to the pixel circuit (PC) through the gate line (SL). The second scan driving circuit (12) can be arranged on the opposite side of the first scan driving circuit (11) with the display area (DA) therebetween. Some of the pixel circuits (PC) arranged in the display area (DA) can be electrically connected to the first scan driving circuit (11), and the rest can be connected to the second scan driving circuit (12). In another embodiment, the second scan driving circuit (12) can be omitted.

[0070] The light emission control driving circuit (13) is arranged on the side of the first scan driving circuit (11) and can provide a light emission control signal to the pixel (P) through the light emission control line (EL). In Fig. 3, the light emission control driving circuit (13) is illustrated as being arranged only on one side of the display area (DA), but the present invention is not limited thereto. In another embodiment, the light emission control driving circuits (13) may be arranged on both sides of the display area (DA).

[0071] The pad (14) may be placed in the second peripheral area (PA2) of the substrate (100). The pad (14) may be exposed without being covered by an insulating layer and may be electrically connected to the display circuit board (30). The pad (34) of the display circuit board (30) may be electrically connected to the pad (14) of the display device (1).

[0072] The display circuit board (30) transmits a signal or power of the control unit to the display device (1). The control signal generated by the control unit can be transmitted to the gate driving circuit through the display circuit board (30), respectively. In addition, the control unit can provide a driving voltage and a common voltage to the first and second power supply lines (15, 16), respectively. The driving voltage is provided to each pixel circuit (PC) through a driving voltage line (PL) connected to the first power supply line (15), and the common voltage can be provided to the opposite electrode of a light emitting diode (LED) connected to the second power supply line (16). The first power supply line (15) can extend in a first direction (e.g., x direction). The second power supply line (16) has a loop shape with one end open, so as to partially surround the display area (DA).

[0073] The data signal of the data driver (20) can be transmitted to the pixel circuit (PC) through the input line (IL) and the data line (DL) electrically connected to the input line (IL).

[0074] FIG. 4A is a drawing schematically illustrating a part of a display device according to one embodiment of the present invention.

[0075] Referring to Fig. 4a, the display device (1) may include a display area (DA) that displays an image by light emission and a dummy area (DMA) surrounding the display area (DA). The dummy area (DMA) may be located in the peripheral area (PA, Fig. 3) or may be located on the periphery of the display area (DA).

[0076] A pixel (P) arranged in a display area (DA) may include a pixel circuit (PC) and a light-emitting element (E) that receives a driving current from the pixel circuit (PC) and emits light. Here, the light-emitting element (E) may include a light-emitting diode (LED) of FIG. 3. The light-emitting element (E) and the pixel circuit (PC) may be detachably connected to each other. The pixel circuit (PC) may include one or more thin-film transistors and capacitive elements. In the present specification, the capacitive element may mean a capacitor. The pixel (P) emits light of one color, and may emit light of one color among red, blue, green, and white, for example. However, the present invention is not limited thereto, and may emit light of a color other than red, blue, green, and white.

[0077] A control line (CL), a repair line (RPL), and a data line (DL) may be arranged in the display area (DA) and the dummy area (DMA). A pixel (P) of the display area (DA) may be connected to a control line (CL) extending along a first direction (e.g., x direction) and a data line (DL) extending along a second direction (e.g., y direction), respectively. Similarly, a dummy pixel (P) of the dummy area (DMA) may be connected to a control line (CL) extending along a first direction (e.g., x direction) and a dummy data line (DDL) extending along a second direction (e.g., y direction), respectively. In FIG. 4A, the control line (CL) is illustrated as one signal line for convenience, but the control line (CL) may be composed of a plurality of signal lines. For example, the control line (CL) may include a gate line (SL, FIG. 3) and an emission control line (EL, FIG. 3).

[0078] Meanwhile, the display device (1) may further include a connection line (GL) connecting the dummy data line (DDL) and the data line (DL). The connection line (GL) may extend along a first direction (e.g., x-direction). The connection line (GL) may be arranged in a dead space outside the display area (DA) and the dummy area (DMA). The connection line (GL) and the data line (DL) are insulated from each other, and one of the connection line (GL) and the data line (DL) may be electrically connected to each other during a repair process.

[0079] A dummy pixel (DP) arranged in a dummy area (DMA) may include a dummy circuit (DC). For example, when a pixel (P) illustrated in FIG. 2 is a defective pixel, a light-emitting element (E) of the defective pixel may be separated from a pixel circuit (PC) of the defective pixel and connected to a corresponding dummy pixel (DP) via a repair line (RPL). In addition, among the data lines (DL), a data line (DL) connected to the defective pixel may be connected to a dummy data line (DDL) via a connection line (GL). A data signal applied to the defective pixel may be applied to the dummy pixel (DP) via the data line (DL), the connection line (GL) connected to the data line (DL), and the dummy data line (DDL) connected to the connection line (GL). The dummy pixel (DP) generates a driving current corresponding to the data signal and supplies the driving current to the light-emitting element (E) of the defective pixel via the repair line (RPL). The light-emitting element (E) emits light of a brightness corresponding to the data signal. Therefore, the light emitting element (E) of the defective pixel can operate normally by means of the dummy pixel (DP).

[0080] The light emitting element (E) of the pixel (P) is insulated from the repair line (RPL) of the same row, and can be electrically connected to the repair line (RPL) in a later repair process. That is, the light emitting element (E) of the pixel (P) can be arranged so as to be connectable to the repair line (RPL) of the same row. For example, the light emitting element (E) can be electrically connected to the first connecting member (21), and the first connecting member (21) can be formed to partially overlap the repair line (RPL) with an insulating film therebetween. The first connecting member (21) can include one or more conductive layers formed of a conductive material. In the repair process, when a laser is irradiated to the overlapping area of ​​the first connecting member (21) and the repair line (RPL), the insulating film is destroyed, so that the first connecting member (21) and the repair line (RPL) can be short-circuited and electrically connected. Accordingly, the light emitting element (E) can be electrically connected to the repair line (RPL).

[0081] A dummy pixel (DP) includes a dummy circuit (DC) and does not include a light-emitting element. The dummy circuit (DC) may be identical to the pixel circuit (PC). In other embodiments, the dummy circuit (DC) may be different from the pixel circuit (PC). For example, the dummy circuit (DC) may omit or add transistors and / or capacitive elements of the pixel circuit (PC), or the sizes and characteristics of the transistors and capacitive elements may be different.

[0082] In this specification, the term "connectable" or "connectably" may mean a state in which connection can be made using a laser or the like during a repair process. For example, when a first member and a second member are arranged to be connectable, it may mean that the first member and the second member are not actually connected, but are in a state in which they can be connected to each other during a repair process. From a structural perspective, the first member and the second member that are "connectable" to each other may be arranged to intersect each other with an insulating film interposed therebetween in an overlapping area. When a laser is irradiated to the overlapping area during the repair process, the insulating film within the overlapping area is destroyed, so that the first member and the second member can be electrically connected to each other.

[0083] In addition, in this specification, the term "separable" or "separably" may mean a state in which it can be separated using a laser or the like during a repair process. For example, when a first member and a second member are separably connected, it may mean that the first member and the second member are actually connected, but are in a state in which they can be separated during a repair process. From a structural point of view, the separably connected first member and the second member may be arranged to be connected to each other via a conductive connecting member. When a laser is irradiated to the conductive connecting member during the repair process, the conductive connecting member may be cut as the portion irradiated with the laser melts, and the first member and the second member may be electrically insulated from each other. For example, the conductive connecting member may include a silicon layer that can be melted by a laser. According to another example, the conductive connecting member may be cut as it melts due to Joule heat generated by an electric current.

[0084] FIG. 4b is a drawing for explaining a method of repairing a defective pixel in a display device according to one embodiment of the present invention.

[0085] Referring to FIG. 4b, a case where a defect occurs in a pixel (Pij) connected to the ith control line (CLi) and the jth data line (DLj) among the pixels (P) formed in the display area (DA), for example, a case where the pixel circuit (PC) of the pixel (Pij) is defective, will be described as an example. In this example, the pixel (Pij) is referred to as a defective pixel (Pij). The pixel (Pij) may be a pixel located in the ith row and the jth column. Here, i and j may be positive integers.

[0086] Referring to FIG. 4b, the light emitting element (E) of the defective pixel (Pij) can be separated from the pixel circuit (PC). For example, by irradiating a laser to the connection area between the light emitting element (E) and the pixel circuit (PC) to cut it, the light emitting element (E) of the defective pixel (Pij) can be separated from the pixel circuit (PC).

[0087] Next, the light emitting element (E) of the defective pixel (Pij) and the dummy circuit (DC) of the dummy pixel (DPi) can be electrically connected to each other. For this purpose, the light emitting element (E) of the defective pixel (Pij) can be connected to the repair line (RLi) of the same row. For example, by irradiating a laser to an overlapping area of ​​the first connecting member (21) connected to the light emitting element (E) of the defective pixel (Pij) and the repair line (RLi) of the same row, the light emitting element (E) can be electrically connected to the repair line (RLi). Since the repair line (RLi) is connected to the dummy circuit (DC), the light emitting element (E) of the defective pixel (Pij) can be connected to the dummy circuit (DC) of the dummy pixel (DPi).

[0088] Next, the data line (DLj) connected to the defective pixel (Pij) and the dummy data line (DDL) can be electrically connected to each other. For this purpose, the data line (DLj) can be connected to the connection line (GL). For example, by irradiating a laser on the overlapping area of ​​the data line (DLj) and the connection line (GL), the data line (DLj) and the connection line (GL) can be electrically connected to each other. Since the connection line (GL) is connected to the dummy data line (DDL), the data line (DLj) and the dummy data line (DDL) can be connected to each other.

[0089] The pixel circuit (PC) of the defective pixel (Pij) and the dummy circuit (DC) of the dummy pixel (DPi) can simultaneously respond to a scan signal applied to the same scan line among the control lines (CLi). Since the data line (DLj) connected to the pixel circuit (PC) of the defective pixel (Pij) is connected to the dummy data line (DDL) through the connection line (GL), the data signal (Dj) applied to the pixel circuit (PC) of the defective pixel (Pij) can also be applied to the dummy circuit (DC) of the dummy pixel (DPi). The dummy circuit (DC) can generate a driving current (Iij) corresponding to the data signal (Dj) and provide the driving current (Iij) to the light-emitting element (E) of the defective pixel (Pij) through the repair line (RLi). The light-emitting element (E) of the defective pixel (Pij) can emit light with a brightness corresponding to the data signal (Dj) by the driving current (Iij). Through this, defective pixels (Pij) can be repaired into normal pixels.

[0090] In this example, since the dummy data line (DDL) is connected to the data line (DLj) via the connection line (GL), there is no need to drive the dummy data line (DDL) separately. Therefore, there is no need to modify the source driver to drive the dummy data line (DDL) with separate timing, and the existing driver can be used as is.

[0091] FIG. 5 is an equivalent circuit diagram of a light emitting diode (LED) and a pixel circuit (PC) of a display device according to one embodiment of the present invention.

[0092] Referring to FIG. 5, a pixel circuit (PC) connected to a light emitting diode (LED) may include a plurality of transistors and a plurality of capacitors. In one embodiment, the pixel circuit (PC) may include first to sixth transistors (T1, T2, T3, T4, T5, and T6), a storage capacitor (Cst), and a hold capacitor (Chd). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal, and the second to sixth transistors (T2, T3, T4, T5, and T6) may be switching transistors that transmit signals. The first terminal (first electrode) of each of the first to sixth transistors (T1, T2, T3, T4, T5, and T6) may be a source or a drain, and the second terminal (second electrode) may be a terminal different from the first terminal. For example, when the first terminal is a drain, the second terminal may be a source.

[0093] In one embodiment, at least one of the first to sixth transistors (T1, T2, T3, T4, T5, T6) may be a p-channel MOSFET (PMOS), and the others may be n-channel MOSFETs (NMOS). For example, the fifth transistor (T5) may be a PMOS, and the first, second, third, fourth, and sixth transistors (T1, T2, T3, T4 T6) may be NMOS. In another embodiment, the fifth transistor (T5) and the sixth transistor (T6) may be PMOS, and the first, second, third, and fourth transistors (T1, T2, T3, T4) may be NMOS. Alternatively, the first to sixth transistors (T1, T2, T3, T4, T5, T6) may all be NMOS or all may be PMOS. Hereinafter, an embodiment will be described in which the fifth transistor (T5) is a PMOS (p-channel MOSFET) including a silicon semiconductor, and the first, second, third, fourth, and sixth transistors (T1, T2, T3, T4, and T6) are NMOS (n-channel MOSFETs) including an oxide semiconductor.

[0094] At least one of the plurality of transistors (T1, T2, T3, T4, T5, T6) may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of the plurality of transistors (T1, T2, T3, T4, T5, T6) may be a transistor having an oxide semiconductor layer. For example, the fifth transistor (T5) may include a semiconductor layer made of polycrystalline silicon having high reliability, and the first, second, third, fourth, and sixth transistors (T1, T2, T3, T4, T6) may include oxide semiconductor layers having high carrier mobility and low leakage current.

[0095] The pixel circuit (PC) may be electrically connected to a gate line transmitting a signal to each of the gates of the first to sixth transistors (T1, T2, T3, T4, T5, and T6). For example, the pixel circuit (PC) may be connected to a scan line (GWL) transmitting a scan signal (GW), an initialization gate line (GIL) transmitting an initialization signal (GI), a reference gate line (GRL) transmitting a reference signal (GR), a first emission control line (EML) transmitting a first emission control signal (EM), a second emission control line (EMBL) transmitting a second emission control signal (EMB), and a data line (DL) transmitting a data signal (DATA). In addition, the pixel circuit (PC) may be connected to a driving voltage line (PL) transmitting a driving voltage (ELVDD), a reference voltage line (VRL) transmitting a reference voltage (Vref), and an initialization voltage line (VL) transmitting an initialization voltage (Vaint).

[0096] A first transistor (T1) may be electrically connected between a driving voltage line (PL) and a second node (N2). The first transistor (T1) may include a gate connected to the first node (N1), a first terminal connected to the driving voltage line (PL), and a second terminal connected to a second node (N2). The first terminal may be a drain (D) and the second terminal may be a source (S). The first transistor (T1) may have a dual gate structure. In addition to the gate connected to the first node, the first transistor (T1) may further include a lower gate electrode overlapping a channel region of the first transistor (T1). The lower gate electrode may be connected to the second node (N2) and a second hold electrode (CEh2) of a hold capacitor (Chd).

[0097] A first terminal of a first transistor (T1) is connected to a driving voltage line (PL) via a fifth transistor (T5), and a second terminal of the first transistor (T1) can be connected to a pixel electrode of a light-emitting diode (LED). The first transistor (T1) can receive a data signal (DATA) according to a switching operation of the second transistor (T2) and control the amount of driving current (Id) flowing to the light-emitting diode (LED).

[0098] The second transistor (T2) may be electrically connected between the data line (DL) and the first node (N1). The second transistor (T2) may include a gate connected to the scan line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) may be turned on by a scan signal (GW) transmitted to the scan line (GWL) to electrically connect the data line (DL) and the first node (N1), and may transmit a data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0099] A third transistor (T3) may be electrically connected between a first node (N1) and a reference voltage line (VRL). The third transistor (T3) may include a gate connected to a reference gate line (GRL), a first terminal connected to a first node (N1), and a second terminal connected to the reference voltage line (VRL). The third transistor (T3) may be turned on by a reference signal (GR) transmitted to the reference gate line (GRL) and may transmit a reference voltage (Vref) transmitted to the reference voltage line (VRL) to the first node (N1). The third transistor (T3) may also be referred to as a reference transistor.

[0100] The fourth transistor (T4) may be electrically connected between the first transistor (T1) and the initialization voltage line (VL). The fourth transistor (T4) may include a gate connected to the initialization gate line (GIL), a first terminal connected to the sixth transistor (T6) and a light-emitting diode (LED), and a second terminal connected to the initialization voltage line (VL). The fourth transistor (T4) may be turned on by an initialization signal (GI) transmitted to the initialization gate line (GIL) and may transmit the initialization voltage (Vaint) transmitted to the initialization voltage line (VL) to the pixel electrode of the light-emitting diode (LED). The fourth transistor (T4) may also be referred to as an initialization transistor.

[0101] The fifth transistor (T5) may be electrically connected between the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate connected to the first emission control line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to the first emission control signal (EM) transmitted to the first emission control line (EML). The fifth transistor (T5) may also be referred to as a driving control transistor.

[0102] The sixth transistor (T6) may be connected between the first transistor (T1) and the light emitting diode (LED). The sixth transistor (T6) may include a gate connected to the second light emitting control line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the light emitting diode (LED). The sixth transistor (T6) may be turned on by the second light emitting control signal (EMB) transmitted to the second light emitting control line (EMBL) to connect the second node (N2) and the pixel electrode of the light emitting diode (LED) to each other. The sixth transistor (T6) may also be referred to as a light emitting control transistor.

[0103] Although Fig. 5 illustrates that the fifth transistor (T5) and the sixth transistor (T6) operate in response to different light emission control signals (EM, EMB), the present invention is not limited thereto. In another embodiment, the fifth transistor (T5) and the sixth transistor (T6) may operate in response to the same light emission control signal.

[0104] In one embodiment, the reference signal (GR) may be substantially synchronized with the scan signal (GW) of the pixel circuit (PC) located in the previous row. The initialization signal (GI) may be substantially synchronized with the scan signal (GW). In another embodiment, the initialization signal (GI) may be substantially synchronized with the scan signal (GW) or the reference signal (GR) of the pixel circuit (PC) located in the next row.

[0105] The storage capacitor (Cst) may be connected between the first node (N1) and the second node (N2). In other words, the pixel circuit (PC) according to an embodiment of the present invention may be a source follower type circuit in which the storage capacitor (Cst) is connected between the first node (N1) and the second node (N2). The first storage electrode (CEs1) of the storage capacitor (Cst) may be connected to the first node (N1), and the second storage electrode (CEs2) may be connected to the second node (N2). The storage capacitor (Cst) may store a threshold voltage of the first transistor (T1) and a voltage corresponding to a data signal (DATA).

[0106] In one embodiment, a hold capacitor (Chd) may be connected between a driving voltage line (PL) and a second node (N2). A first hold electrode (CEh1) of the hold capacitor (Chd) may be connected to the driving voltage line (PL), and a second hold electrode (CEh2) may be connected to a second node (N2). The hold capacitor (Chd) allows the voltage of the lower gate electrode of the first transistor (T1) and the second node (N2) to remain constant and not fluctuate even when a peripheral signal fluctuates.

[0107] A light emitting diode (LED) includes a pixel electrode connected to a second node (N2) and a counter electrode on the pixel electrode, and the counter electrode can be supplied with a common voltage (ELVSS). The counter electrode can be a common electrode shared by a plurality of light emitting diodes (LEDs).

[0108] Although FIG. 5 illustrates that the pixel circuit (PC) includes six transistors and two capacitors, the present invention is not limited thereto. In another embodiment, the pixel circuit (PC) may include five transistors and two capacitors. In yet another embodiment, the pixel circuit (PC) may include seven transistors and two capacitors.

[0109] Fig. 6 is a plan view schematically illustrating pixel circuits of a display device according to an embodiment of the present invention. For convenience of explanation, Fig. 6 illustrates three pixel circuits, for example, a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3), arranged in the same row along a first direction (e.g., x-direction), but the present invention is not limited thereto. The display device (1) includes a plurality of pixel circuits arranged to form rows in the first direction (e.g., x-direction) and columns in the second direction (e.g., y-direction).

[0110] Referring to FIG. 6, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include transistors and capacitors. In one embodiment, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include the first to sixth transistors (T1, T2, T3, T4, T5, T6), a storage capacitor (Cst), and a hold capacitor (Chd) described above with reference to FIG. 5.

[0111] The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be electrically connected to gate lines that transmit signals to the gates of the first to sixth transistors (T1, T2, T3, T4, T5, and T6), respectively. For example, the pixel circuit (PC) may be connected to a scan line (GWL) that transmits a scan signal, an initialization gate line (GIL) that transmits an initialization signal, a reference gate line (GRL) that transmits a reference signal, a first emission control line (EML) that transmits a first emission control signal, a second emission control line (EMBL) that transmits a second emission control signal, a hold gate line (GHL) that transmits a hold signal, and a data line (DL) that transmits a data signal. Additionally, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) can be connected to a driving voltage line (PL) that transmits a driving voltage, a reference voltage line (VRL) that transmits a reference voltage, and an initialization voltage line (VL) that transmits an initialization voltage.

[0112] Referring to FIG. 6, the transistors and capacitors of the first pixel circuit (PC1) may be arranged symmetrically with the transistors and capacitors of the second pixel circuit (PC2), respectively. For example, the first transistor (T1) of the first pixel circuit (PC1) may be symmetrical with the first transistor (T1) of the second pixel circuit (PC2) with respect to an imaginary line (IML1) passing between the first pixel circuit (PC1) and the second pixel circuit (PC2) along the second direction (e.g., the y direction). Similarly, the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the first pixel circuit (PC1) may be symmetrical with respect to the imaginary line (IML1) with respect to the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the second pixel circuit (PC2), respectively.

[0113] Similarly, the transistors and capacitors of the second pixel circuit (PC2) may be arranged symmetrically with the transistors and capacitors of the third pixel circuit (PC3), respectively. For example, the first transistor (T1) of the second pixel circuit (PC2) may be symmetrical with the first transistor (T1) of the third pixel circuit (PC3) with respect to an imaginary line (IML2) passing between the second pixel circuit (PC2) and the third pixel circuit (PC3) along the second direction (e.g., the y direction). Similarly, the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the second pixel circuit (PC2) may be symmetrical with respect to the imaginary line (IML2) with respect to the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the third pixel circuit (PC3), respectively.

[0114] Gate lines electrically connected to the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3), such as a scan line (GWL), an initialization gate line (GIL), a reference gate line (GRL), a first emission control line (EML), a second emission control line (EMBL), and a hold gate line (GHL), can extend in a first direction (e.g., an x-direction).

[0115] The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be electrically connected to a data line (DL) passing through each pixel circuit (PC). For example, the first pixel circuit (PC1) may be electrically connected to a first data line (DL1) passing through the first pixel circuit (PC1), the second pixel circuit (PC2) may be electrically connected to a second data line (DL2) passing through the second pixel circuit (PC2), and the third pixel circuit (PC3) may be connected to a third data line (DL3) passing through the third pixel circuit (PC3). The data line (DL) may extend along a second direction (e.g., a y direction). With respect to the first direction (e.g., x-direction), the first data line (DL1) may be arranged to the left of the first transistor (T1) within the first pixel circuit (PC1), the second data line (DL2) may be arranged to the right of the first transistor (T1) within the second pixel circuit (PC2), and the third data line (DL3) may be arranged to the left of the first transistor (T1) within the third pixel circuit (PC3). In other words, the first data line (DL1) and the second data line (DL2) may be arranged far apart with respect to an imaginary line (IML1), and the second data line (DL2) and the third data line (DL3) may be arranged adjacent with respect to an imaginary straight line (IML2).

[0116] A first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3) may be electrically connected to voltage lines passing through each pixel circuit (PC). For example, the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be electrically connected to a reference voltage line (VRL), an initialization voltage line (VL), a driving voltage line (PL), and a common voltage line (VSL), respectively. The reference voltage line (VRL) may include a horizontal reference voltage line (HVRL) extending along a first direction (e.g., an x-direction) and a vertical reference voltage line (VVRL) extending along a second direction (e.g., a y-direction). The horizontal reference voltage line (HVRL) and the vertical reference voltage line (VVRL) may be electrically connected to each other in an intersecting region. In one embodiment, the vertical reference voltage line (VVRL) may be disposed on an region where the third pixel circuit (PC3) is disposed. Meanwhile, in one embodiment, the vertical reference voltage line (VVRL) may also function as the first vertical common voltage line (VVSL1) among the vertical common voltage lines (VVSL) described later.

[0117] The initialization voltage line (VL) may include a horizontal initialization voltage line (HVL) extending along a first direction (e.g., x-direction) and a vertical initialization voltage line (VVL) extending along a second direction (e.g., y-direction). The horizontal initialization voltage line (HVL) and the vertical initialization voltage line (VVL) may be electrically connected to each other in an intersecting region. In one embodiment, the vertical initialization voltage line (VVL) may be arranged on a boundary between the first pixel circuit (PC1) and the second pixel circuit (PC2). For example, the vertical initialization voltage line (VVL) may be arranged on the aforementioned virtual line (IML1), such that some of the vertical initialization voltage line (VVL) may be arranged on an area where the first pixel circuit (PC1) is arranged, and other parts of the vertical initialization voltage line (VVL) may be arranged on an area where the second pixel circuit (PC2) is arranged. Meanwhile, in one embodiment, the vertical initialization voltage line (VVL) may also function as a second vertical common voltage line (VVSL2) among the vertical common voltage lines (VVSL) to be described later.

[0118] The horizontal initialization voltage line (HVL) may include a plurality of wires. For example, the horizontal initialization voltage line (HVL) may include a first horizontal initialization voltage line (HVL1) that transmits an initialization voltage to a first pixel circuit (PC1), a second horizontal initialization voltage line (HVL2) that transmits an initialization voltage to a second pixel circuit (PC2), and a third horizontal initialization voltage line (HVL3) that transmits an initialization voltage to a third pixel circuit (PC3).

[0119] The driving voltage line (PL) may include a horizontal driving voltage line (HPL) extending along a first direction (e.g., x direction) and a vertical driving voltage line (VPL) extending along a second direction (e.g., y direction). The horizontal driving voltage line (HPL) and the vertical driving voltage line (VPL) may be electrically connected to each other in an intersecting region. In one embodiment, the vertical driving voltage line (VPL) may be respectively disposed on an area where the first pixel circuit (PC1) is disposed and an area where the second pixel circuit (PC2) is disposed. That is, the vertical driving voltage line (VPL) may include a first vertical driving voltage line (VPL1) disposed on the first pixel circuit (PC1) and a second vertical driving voltage line (VPL2) disposed on the second pixel circuit (PC2). The first vertical driving voltage line (VPL1) and the second vertical driving voltage line (VPL2) may be symmetrical with respect to an imaginary line (IML1).

[0120] The common voltage line (VSL) may include a horizontal common voltage line (HVSL) extending along a first direction (e.g., x-direction) and a vertical common voltage line (VVSL) extending along a second direction (e.g., x-direction). The horizontal common voltage line (HVSL) and the vertical common voltage line (VVSL) may be electrically connected to each other at an intersecting region. The horizontal common voltage line (HVSL) may extend along the first direction (e.g., x-direction) and pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The vertical common voltage line (VVSL) may include a second vertical common voltage line (VVSL2) disposed on the third pixel circuit (PC3) and a second vertical common voltage line (VVSL2) disposed on an imaginary line (IML1). As previously described, in one embodiment, the first vertical common voltage line (VVSL1) may also function as a vertical reference voltage line (VVRL). In one embodiment, the second vertical common voltage line (VVSL2) may also function as a vertical initialization voltage line (VVL).

[0121] FIG. 7 is a schematic cross-sectional view of a display device according to one embodiment of the present invention, showing a cross-section taken along line VII-VII' of FIG. 3.

[0122] Referring to FIG. 7, the display device may include a circuit layer including transistors and capacitors disposed on a substrate (100), and a display element layer disposed on the aforementioned circuit layer and including a light-emitting diode (LED). The circuit layer may include the transistors and capacitors described above with reference to FIG. 6, and FIG. 7 illustrates only the first transistor (T1), the fifth transistor (T5), the sixth transistor (T6), and the hold capacitor (Chd) for convenience of explanation.

[0123] The substrate (100) may include a glass material, a ceramic material, a metal material, a plastic material, or a material having flexible or bendable properties. When the substrate (100) has flexible or bendable properties, the substrate (100) may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyether imide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, and cellulose acetate propionate (CAP).

[0124] The substrate (100) may have a single-layer or multi-layer structure of the above material, and in the case of a multi-layer structure, may further include an inorganic layer. For example, the substrate (100) may have a structure in which a layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material are alternately laminated.

[0125] A buffer layer (101) may be disposed on a substrate (100). The buffer layer (101) may be an inorganic insulating layer including an inorganic insulating material such as silicon nitride and / or silicon oxide, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0126] A transistor including a silicon semiconductor layer may be arranged on the buffer layer (101). In this regard, FIG. 7 illustrates a fifth semiconductor layer (A5) of a fifth transistor (T5). The fifth semiconductor layer (A5) may include polysilicon. The fifth semiconductor layer (A5) may include a channel region (C5) and impurity regions (S5, D5) doped with impurities and arranged on both sides of the channel region (C5). One of the impurity regions (S5, D5) of the fifth semiconductor layer (A5) may be a source and the other may be a drain.

[0127] In some embodiments, a lower metal layer (not shown) may be added between the buffer layer (101) and the silicon semiconductor layer. The lower metal layer may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The lower metal layer may have a voltage level of a constant voltage. For example, the lower metal layer may be electrically connected to the first power supply wiring (15, FIG. 3) at the periphery of the display area (DA, FIG. 3).

[0128] The first gate insulating layer (103) may be disposed on the fifth semiconductor layer (A5). The first gate insulating layer (103) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0129] The fifth gate electrode (G5) is disposed on the first gate insulating layer (103) and may overlap the channel region (C5) of the fifth semiconductor layer (A5). A first hold electrode (CEh1) of the hold capacitor (Chd) and an emission control line (EML) may be disposed on the same layer as the fifth gate electrode (G5), for example, on the first gate insulating layer (103). As will be described later, the fifth gate electrode (G5) may be formed in a portion of the emission control line (EML).

[0130] The fifth gate electrode (G5) and the first hold electrode (CEh1) of the hold capacitor (Chd) may include the same material. The fifth gate electrode (G5) and the first hold electrode (CEh1) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. In one embodiment, the fifth gate electrode (G5) and the first hold electrode (CEh1) of the hold capacitor (Chd) may be a single layer including molybdenum.

[0131] The second gate insulating layer (105) may be disposed on the fifth gate electrode (G5) and the first hold electrode (CEh1) of the hold capacitor (Chd). The second gate insulating layer (105) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the second gate insulating layer (105) may include a different material from the first gate insulating layer (103). For example, the first gate insulating layer (103) may include silicon oxide, and the second gate insulating layer (105) may include silicon nitride.

[0132] The second hold electrode (CEh2) of the hold capacitor (Chd) may be disposed on the second gate insulating layer (105). The second hold electrode (CEh2) may overlap the first hold electrode (CEh1) of the hold capacitor (Chd). A repair line (RPL) may be disposed on the same layer as the second hold electrode (CEh2), for example, on the second gate insulating layer (105).

[0133] The second hold electrode (CEh2) and the repair line (RPL) of the hold capacitor (Chd) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials. In one embodiment, the second hold electrode (CEh2) and the repair line (RPL) may be a single layer including molybdenum.

[0134] The third gate insulating layer (107) may be disposed on the second hold electrode (CEh2) and the repair line (RPL). The third gate insulating layer (107) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0135] A first lower gate electrode (G1b) of a first transistor (T1) and a fifth conductive pattern (1420) may be arranged on the third gate insulating layer (107). As described above, the first transistor (T1) may have a dual gate structure and may include a first upper gate electrode (G1a) and a first lower gate electrode (G1b) that overlap with a channel region of the first transistor (T1). As will be described later, the fifth conductive pattern (1420) may connect the repair line (RPL) and the 13th conductive pattern (1760) and may also be referred to as a repair bridge pattern.

[0136] The first lower gate electrode (G1b) and the fifth conductive pattern (1420) may include the same material. The first lower gate electrode (G1b) and the fifth conductive pattern (1420) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0137] A first interlayer insulating layer (109) may be disposed on the first lower gate electrode (G1b) and the fifth conductive pattern (1420). The first interlayer insulating layer (109) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. For example, the first interlayer insulating layer (109) may have a stacked structure of a layer including silicon oxide and a layer including silicon nitride.

[0138] The first semiconductor layer (A1) of the first transistor (T1) and the sixth semiconductor layer (A6) of the sixth transistor (T6) may be disposed on the first interlayer insulating layer (109) and may include the same material. The first semiconductor layer (A1) of the first transistor (T1) and the sixth semiconductor layer (A6) of the sixth transistor (T6) may include an oxide semiconductor, and the oxide semiconductor may be an oxide semiconductor including at least one element selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor may include ITZO (InSnZnO) or IGZO (InGaZnO).

[0139] The first semiconductor layer (A1) may include a channel region (C1) and conductive regions (S1, D1) arranged on both sides of the channel region (C1). One of the conductive regions (S1, D1) may be a source and the other may be a drain. Similarly, the sixth semiconductor layer (A6) may include a channel region (C6) and conductive regions (S6, D6) arranged on both sides of the channel region (C6). One of the conductive regions (S6, D6) may be a source and the other may be a drain.

[0140] The first semiconductor layer (A1) and the sixth semiconductor layer (A6) may be arranged on different layers from the fifth semiconductor layer (A5) described above. For example, the vertical distance from the substrate (100) to the first semiconductor layer (A1) may be greater than the vertical distance from the substrate (100) to the fifth semiconductor layer (A5).

[0141] The fourth gate insulating layer (111) may be disposed on the first semiconductor layer (A1) and the sixth semiconductor layer (A6). The fourth gate insulating layer (111) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the fourth gate insulating layer (111) may be a single-layer including silicon oxide.

[0142] Although FIG. 7 illustrates that the fourth gate insulating layer (111) passes through the side surface of the first semiconductor layer (A1) and contacts the upper surface of the first interlayer insulating layer (109), the present invention is not limited thereto. In another embodiment, the fourth gate insulating layer (111) may be formed to have substantially the same pattern and / or the same width as the first upper gate electrode (G1a) and the sixth gate electrode (G6) described later. Alternatively, in another embodiment, the fourth gate insulating layer (111) may be formed to have a larger pattern and / or a larger width than the first upper gate electrode (G1a) described later, and may be formed to have a smaller pattern and / or a smaller width than the first semiconductor layer (A1). Likewise, the fourth gate insulating layer (111) may be formed to have a larger pattern and / or a larger width than the sixth gate electrode (G6) described later, and may be formed to have a smaller pattern and / or a smaller width than the sixth semiconductor layer (A6). In other words, the fourth gate insulating layer (111) may not contact the upper surface of the first interlayer insulating layer (109) beyond the side surface of the first semiconductor layer (A1).

[0143] The first upper gate electrode (G1a) and the sixth gate electrode (G6) may be disposed on the fourth gate insulating layer (111). The first upper gate electrode (G1a) may overlap with the channel region (C1) of the first semiconductor layer (A1), and the sixth gate electrode (G6) may overlap with the channel region (C6) of the sixth semiconductor layer (A6). As will be described later, the sixth gate electrode (G6) may be formed in a portion of the second emission control line (EMBL, FIG. 13). The first upper gate electrode (G1a) and the sixth gate electrode (G6) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. In one embodiment, the first upper gate electrode (G1a) and the sixth gate electrode (G6) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0144] The second interlayer insulating layer (113) may be disposed on the first upper gate electrode (G1a) and the sixth gate electrode (G6). The second interlayer insulating layer (113) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the second interlayer insulating layer (113) may have a stacked structure of a layer including silicon nitride and a layer including silicon oxynitride.

[0145] The 11th conductive pattern (1740), the 10th conductive pattern (1730), the second horizontal driving voltage line (HPL2), and the 13th conductive pattern (1760) may be disposed on the same layer, for example, the second interlayer insulating layer (113). The 11th conductive pattern (1740) may be a connection electrode connecting the 5th semiconductor layer (A5) and the 1st semiconductor layer (A1), and the 10th conductive pattern (1730) may be a connection electrode connecting the 1st semiconductor layer (A1) and the 6th semiconductor layer (A6). As will be described later, the 13th conductive pattern (1760) may connect the 6th semiconductor layer (A6) and a light emitting diode (LED) via the 16th conductive pattern (1820). Therefore, the 13th conductive pattern (1760) may also be referred to as a first pixel connection electrode.

[0146] The 11th conductive pattern (1740), the 10th conductive pattern (1730), the second horizontal driving voltage line (HPL2), and the 13th conductive pattern (1760) may include the same material. The 11th conductive pattern (1740), the 10th conductive pattern (1730), the second horizontal driving voltage line (HPL2), and the 13th conductive pattern (1760) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials. In one embodiment, the 11th conductive pattern (1740), the 10th conductive pattern (1730), the second horizontal driving voltage line (HPL2), and the 13th conductive pattern (1760) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0147] The first organic insulating layer (115) may be disposed on the 11th conductive pattern (1740), the 10th conductive pattern (1730), the second horizontal driving voltage line (HPL2), and the 13th conductive pattern (1760). The first organic insulating layer (115) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0148] The vertical driving voltage line (VPL) and the 16th conductive pattern (1820) may be arranged on the first organic insulating layer (115). The 16th conductive pattern (1820) may connect the 6th semiconductor layer (A6) and the light emitting diode (LED) via the 13th conductive pattern (1760). Accordingly, the 16th conductive pattern (1820) may also be referred to as a second pixel connection electrode. The vertical driving voltage line (VPL) and the 16th conductive pattern (1820) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials. In one embodiment, the vertical driving voltage line (VPL) and the 16th conductive pattern (1820) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0149] The second organic insulating layer (117) may be disposed on the vertical driving voltage line (VPL) and the 16th conductive pattern (1820). The second organic insulating layer (117) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0150] A light emitting diode (LED) may be disposed on the second organic insulating layer (117). The light emitting diode (LED) may include a pixel electrode (210), an intermediate layer (220), and a counter electrode (230) on the second organic insulating layer (117).

[0151] An outer portion of the pixel electrode (210) may be covered by a bank layer (119), and an inner portion of the pixel electrode (210) may overlap an intermediate layer (220) through an opening in the bank layer (119). The pixel electrode (210) may be arranged to correspond to each light-emitting diode (LED), and the counter electrode (230) may be arranged to correspond to a plurality of light-emitting diodes (LED). In other words, the counter electrode (230) may be extended to overlap a plurality of pixel electrodes (210). A plurality of light-emitting diodes (LEDs) may share the counter electrode (230), and a stacked structure of the pixel electrode (210), the intermediate layer (220), and the counter electrode (230) may correspond to a light-emitting diode (LED).

[0152] The intermediate layer (220) may include an emission layer. In some embodiments, the intermediate layer (220) may further include an emission layer and a functional layer. The functional layer may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL). In some embodiments, the intermediate layer (220) may include a first stack including an emission layer and a functional layer, a second stack including an emission layer and a functional layer, and a charge generation layer between the first stack and the second stack. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The light emission efficiency of a tandem light emitting diode (LED) including a plurality of emission layers can be further increased by the negative charge generation layer and the positive charge generation layer.

[0153] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0154] The counter electrode (230) may be formed of a conductive material having a low work function. The counter electrode (230) may include a transparent or translucent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the transparent or translucent layer containing the aforementioned material.

[0155] Although not shown, an encapsulation layer may be disposed on the light emitting diode (LED). The encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer therebetween.

[0156] FIGS. 8 to 15 are plan views illustrating a process for forming a pixel circuit of a display device according to an embodiment of the present invention. FIGS. 8 to 15 illustrate a process for forming components corresponding to the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) described with reference to FIG. 6. For convenience of explanation, the first pixel circuit (PC1) is described as being located in the (i)-th row and the (j)-th column, the second pixel circuit (PC2) is described as being located in the (i)-th row and the (j+1)-th column, and the third pixel circuit (PC3) is described as being located in the (i)-th row and the (j+2)-th column.

[0157] Referring to FIG. 8, a silicon semiconductor layer (1100) may be disposed on a substrate. For example, the silicon semiconductor layer (1100) may include amorphous silicon or polysilicon. For example, the silicon semiconductor layer (1100) may include polysilicon crystallized at a low temperature. The silicon semiconductor layer (1100) may include a first silicon semiconductor pattern (1110) and a first horizontal reference voltage line (HVRL1), as shown in FIG. 8.

[0158] The first silicon semiconductor pattern (1110) may include a 1-1 silicon semiconductor pattern (1110a) disposed in the first pixel circuit (PC1), a 1-2 silicon semiconductor pattern (1110b) disposed in the second pixel circuit (PC2), and a 1-3 silicon semiconductor pattern (1110c) disposed in the third pixel circuit (PC3). The 1-1 silicon semiconductor pattern (1110a) may have an isolated shape and may include a curved portion. The 1-1 silicon semiconductor pattern (1110a) may include the fifth semiconductor layer (A5) of the first pixel circuit (PC1). The 1-2 silicon semiconductor pattern (1110b) and the 1-3 silicon semiconductor pattern (1110c) may be connected to each other and formed as an integral body. The first-second silicon semiconductor pattern (1110b) and the first-third silicon semiconductor pattern (1110c) may be symmetrical with respect to an imaginary line (IML2). The first-second silicon semiconductor pattern (1110b) may include a fifth semiconductor layer (A5) of the second pixel circuit (PC2), and the first-third silicon semiconductor pattern (1110c) may include a fifth semiconductor layer (A5) of the third pixel circuit (PC3). For example, the fifth semiconductor layer (A5) of the second pixel circuit (PC2) and the fifth semiconductor layer (A5) of the third pixel circuit (PC3) may be integrally connected.

[0159] A first horizontal reference voltage line (HVRL1) may extend along a first direction (e.g., x direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The first horizontal reference voltage line (HVRL1) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The first horizontal reference voltage line (HVRL1) may be electrically connected to a second horizontal reference voltage line (HVRL2, FIG. 14) and a dummy horizontal reference voltage line (HVRLd, FIG. 11) to transmit a reference voltage to each pixel circuit. The first horizontal reference voltage line (HVRL1) may be arranged to overlap with the second horizontal reference voltage line (HVRL2, FIG. 14) on a plane.

[0160] Referring to FIG. 9, a first conductive layer (1200) may be disposed on a silicon semiconductor layer (1100). The first conductive layer (1200) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0161] The first conductive layer (1200) may include a first emission control line (EML), a first conductive pattern (1210), and a second conductive pattern (1220). The first emission control line (EML), the first conductive pattern (1210), and the second conductive pattern (1220) may be arranged spaced apart from each other.

[0162] The first emission control line (EML) can extend along a first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The first emission control line (EML) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3).

[0163] The first emission control line (EML) may include a fifth gate electrode (G5) of a fifth transistor (T5) of each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). A region of the first emission control line (EML) overlapping with the first silicon semiconductor pattern (1110, FIG. 8) may correspond to the fifth gate electrode (G5) of the fifth transistor (T5). The fifth semiconductor layer (A5, FIG. 8) of the fifth transistor (T5) may include a channel region (C5) overlapping with the fifth gate electrode (G5), and doped regions (S5, D5) disposed on both sides of the channel region (C5) and doped with impurities. One of the doped regions (S5, D5) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source and drain regions can be interchanged depending on the properties of the transistor.

[0164] The first conductive pattern (1210) may be arranged in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The first conductive pattern (1210) may have an isolated shape. The first conductive pattern (1210) of the first pixel circuit (PC1) may be arranged symmetrically with respect to the first conductive pattern (1210) of the second pixel circuit (PC2) with respect to the virtual line (IML1). Similarly, the first conductive pattern (1210) of the second pixel circuit (PC2) and the first conductive pattern (1210) of the third pixel circuit (PC3) may be arranged symmetrically with respect to the virtual line (IML2). The first conductive pattern (1210) may include the first storage electrode (CEs1) of the storage capacitor (Cst, FIG. 6) described with reference to FIG. 6.

[0165] The second conductive pattern (1220) may extend in a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). For example, the second conductive pattern (1220) may include a stem portion (1220t) extending in the first direction (e.g., x-direction), a branch portion (1220b) branching from the stem portion (1220t) and extending in a second direction (e.g., y-direction), and a capacitor portion (1220c) extending from the stem portion (1220t) and having a rectangular shape.

[0166] The capacitor portion (1220c) of the second conductive pattern (1220) may be arranged in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The capacitor portion (1220c) of the second conductive pattern (1220) may include the first hold electrode (CEh1) of the hold capacitor (Chd, FIG. 6) described with reference to FIG. 6.

[0167] The second conductive pattern (1220) may include a branch portion (1220b) including a first branch portion (1220b1) and a second branch portion (1220b2). The first branch portion (1220b1) may refer to a portion of the second conductive pattern (1220) that branches off from the end of the stem portion (1220t) and extends in a second direction (e.g., y direction). The second branch portion (1220b2) may refer to a portion of the second conductive pattern (1220) that is arranged between the capacitor portion (1220c) of the second pixel circuit (PC2) and the capacitor portion (1220c) of the third pixel circuit (PC3), and branches off from the stem portion (1220t) and extends in a second direction (e.g., y direction). The branch portion (1220b) of the second conductive pattern (1220) is electrically connected to the second horizontal driving voltage line (HPL2, FIG. 14) and the vertical driving voltage line (VPL, FIG. 15), so as to transmit the driving voltage to the capacitor portion (1220c). Accordingly, the second conductive pattern (1220) may also be referred to as the first horizontal driving voltage line (HPL1).

[0168] Referring to FIG. 10, a second conductive layer (1300) may be disposed on the first conductive layer (1200). The second conductive layer (1300) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0169] The second conductive layer (1300) may include a repair line (RPL) and a third conductive pattern (1310). The repair line (RPL) and the third conductive pattern (1310) may be arranged spaced apart from each other.

[0170] The repair line (RPL) can extend along a first direction (e.g., the x-direction) so as to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The repair line (RPL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). As described above, when a pixel circuit is defective, a light emitting diode (LED) can be separated from the defective pixel circuit, and the light emitting diode (LED) can be connected to a dummy circuit via the repair line (RPL). The dummy circuit generates a driving current corresponding to a data signal, and supplies the driving current to the light emitting diode (LED) via the repair line, so that the light emitting diode (LED) can operate normally.

[0171] Accordingly, the repair line (RPL) may be arranged to overlap with the 13th conductive pattern (1760, FIG. 14) and the 16th conductive pattern (1820, FIG. 15), which are connected to the light emitting diode (LED) and are referred to as pixel connection electrodes. In addition, the repair line (RPL) may be arranged to overlap with the 13th conductive pattern (1760, FIG. 14) and the 5th conductive pattern (1420, FIG. 11), which may serve as an intermediate bridge between the repair line (RPL), for example, a repair bridge pattern. The light emitting diode (LED) is arranged to be insulated from the repair line (RPL), but may be electrically connected to the repair line (RPL) in a later repair process.

[0172] However, the repair line (RPL) is not necessarily limited to being disposed on the second conductive layer (1300). In some other embodiments, the repair line (RPL) may be disposed on the first conductive layer (1200, FIG. 9). For example, the repair line (RPL) may be disposed on the same layer as the first conductive pattern (1210, FIG. 9), the second conductive pattern (1220, FIG. 9), and the emission control line (EML, FIG. 9).

[0173] The third conductive pattern (1310) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The third conductive pattern (1310) disposed in the first pixel circuit (PC1) and the third conductive pattern (1310) disposed in the second pixel circuit (PC2) may be spaced apart from each other and may be substantially symmetrically disposed with respect to the aforementioned virtual line (IML1). The third conductive pattern (1310) disposed in the second pixel circuit (PC2) and the third conductive pattern (1310) disposed in the third pixel circuit (PC3) may be spaced apart from each other and may be substantially symmetrically disposed with respect to the aforementioned virtual line (IML2).

[0174] The third conductive pattern (1310) may overlap with each of the first conductive pattern (1210, FIG. 9) and the second conductive pattern (1220, FIG. 9) of the first conductive layer (1200, FIG. 9). The third conductive pattern (1310) may include a second storage electrode (CEs2) of a storage capacitor (Cst, FIG. 6) and a second hold electrode (CEh2) of a hold capacitor (Chd, FIG. 6). An area of ​​the third conductive pattern (1310) that overlaps with the first conductive pattern (1210, FIG. 9), which is the first storage electrode (CEs1, FIG. 9), may be the second storage electrode (CEs2) of the storage capacitor (Cst, FIG. 6). The area overlapping the second conductive pattern (1220, FIG. 9), which is the first hold electrode (CEh1, FIG. 9) among the third conductive patterns (1310), may be the second hold electrode (CEh2) of the hold capacitor (Chd, FIG. 6). In other words, the second storage electrode (CEs2) of the storage capacitor (Cst, FIG. 6) and the second hold electrode (CEh2) of the hold capacitor (Chd, FIG. 6) may be formed integrally. Meanwhile, the third conductive pattern (1310) may have a closed opening (1310OP) in the area overlapping the first conductive pattern (1210, FIG. 9).

[0175] Referring to FIG. 11, a third conductive layer (1400) may be disposed on the second conductive layer (1300). The third conductive layer (1400) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0176] The third conductive layer (1400) may include a fourth conductive pattern (1410), a fifth conductive pattern (1420), and a dummy horizontal reference voltage line (HVRLd). The fourth conductive pattern (1410), the fifth conductive pattern (1420), and the dummy horizontal reference voltage line (HVRLd) may be arranged to be spaced apart from each other.

[0177] The fourth conductive pattern (1410) may be arranged in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The fourth conductive pattern (1410) may have an isolated shape. The fourth conductive pattern (1410) of the first pixel circuit (PC1) may be arranged symmetrically with respect to the fourth conductive pattern (1410) of the second pixel circuit (PC2) with respect to the virtual line (IML1), and the fourth conductive pattern (1410) of the second pixel circuit (PC2) and the fourth conductive pattern (1410) of the third pixel circuit (PC3) may be arranged symmetrically with respect to the virtual line (IML2). The fourth conductive pattern (1410) may be arranged to overlap with the third conductive pattern (1310, FIG. 10). The first lower gate electrode (G1b) of the first transistor (T1, FIG. 6) of the fourth challenge pattern (1410) may be included, and may be electrically connected to the tenth challenge pattern (1730, FIG. 14) described later.

[0178] The fifth conductive pattern (1420) may be arranged in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The fifth conductive pattern (1420) may have an isolated rectangular shape. The fifth conductive pattern (1420) of the first pixel circuit (PC1) may be arranged symmetrically with respect to the fifth conductive pattern (1420) of the second pixel circuit (PC2) with respect to the virtual line (IML1), and the fifth conductive pattern (1420) of the second pixel circuit (PC2) and the fifth conductive pattern (1420) of the third pixel circuit (PC3) may be arranged symmetrically with respect to the virtual line (IML2).

[0179] The fifth conductive pattern (1420) may be arranged to partially overlap with the repair line (RPL), and may be arranged to partially overlap with the 13th conductive pattern (1760, FIG. 14) and the 16th conductive pattern (1820, FIG. 15) to be described later. The 13th conductive pattern (1760, FIG. 14) and the 16th conductive pattern (1820, FIG. 15) may be pixel connection electrodes that connect the third oxide semiconductor pattern (1530, FIG. 12) and the light emitting diode (LED, FIG. 9). When the pixel circuit is defective, the repair process may insulate the third oxide semiconductor pattern (1530, FIG. 12) and the pixel connection electrode, and electrically connect the pixel connection electrode and the repair line (RPL). At this time, the fifth conductive pattern (1420) is arranged between the repair line (RPL) and the 13th conductive pattern (1760, FIG. 14), which is a pixel connection electrode, and can serve as an intermediate bridge between the repair line (RPL) and the 13th conductive pattern (1760, FIG. 14). For example, the fifth conductive pattern (1420) can be referred to as a repair bridge pattern.

[0180] As the fifth conductive pattern (1420) is arranged between the repair line (RPL) and the 13th conductive pattern (1760, FIG. 14), the thickness of the insulating layers arranged between the repair line (RPL) and the 13th conductive pattern (1760, FIG. 14) can be reduced. In the repair process, the thicker the insulating layer between two conductive patterns that must be shorted, the lower the success rate of the repair process. Accordingly, in the display device according to one embodiment of the present invention, by arranging the repair bridge pattern between the repair line (RPL) and the pixel connection electrode, the thickness of the insulating layer between the repair line (RPL) and the pixel connection electrode can be reduced, and the repair success rate can be efficiently improved.

[0181] A dummy horizontal reference voltage line (HVRLd) can extend along a first direction (e.g., an x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The dummy horizontal reference voltage line (HVRLd) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The dummy horizontal reference voltage line (HVRLd) can be electrically connected to the first horizontal reference voltage line (HVRL1, FIG. 8) and the second horizontal reference voltage line (HVRL2, FIG. 14) to transmit a reference voltage to each pixel circuit.

[0182] For example, the dummy horizontal reference voltage line (HVRLd) may include a stem portion (HVRLd-t) extending in a first direction (e.g., x-direction) and a branch portion (HVRLd-b) branching from the stem portion (HVRLd-t) and extending in a second direction (e.g., y-direction). The branch portion (HVRLd-b) of the dummy horizontal reference voltage line (HVRLd) may extend to overlap with the first horizontal reference voltage line (HVRL1, FIG. 8) and the second horizontal reference voltage line (HVRL2, FIG. 14). As will be described later, the branch portion (HVRLd-b) of the dummy horizontal reference voltage line (HVRLd) may be connected to the second horizontal reference voltage line (HVRL2, FIG. 14) through a contact hole in an area overlapping with the second horizontal reference voltage line (HVRL2, FIG. 14).

[0183] The third conductive layer (1400) may include a dummy wiring electrically connected to at least one of the plurality of voltage lines, such as a dummy horizontal reference voltage line (HVRLd). As described above, the third conductive layer (1400) may include a fourth conductive pattern (1410) and a fifth conductive pattern (1420). However, since the planar areas of the fourth conductive pattern (1410) and the fifth conductive pattern (1420) are not large, the pattern density of the third conductive layer (1400) may be relatively small compared to other conductive layers or semiconductor layers. The conductive layer and the semiconductor layer may each include a pattern formed through a deposition process, a photolithography process, an etching process, or the like. In this case, when the pattern density of a specific layer is low, the pattern may be deposited unevenly, or process problems such as exposure defects, over-etching, or under-etching may occur.

[0184] Accordingly, the display device according to one embodiment of the present invention can increase the pattern density of the third conductive layer (1400) and improve the stability of the display device manufacturing process by additionally arranging dummy wiring on the third conductive layer (1400) having a relatively low pattern density. In addition, by electrically connecting the dummy wiring to one of a plurality of voltage lines connected to the pixel circuit, the voltage line can be designed more flexibly, and the resistance of the voltage line and the power consumption of the display device can be efficiently reduced.

[0185] Referring to FIG. 12, an oxide semiconductor layer (1500) may be disposed on the third conductive layer (1400). For example, the oxide semiconductor layer (1500) may include an oxide semiconductor, and the oxide semiconductor may be an oxide semiconductor including at least one element selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor layer (1500) may include ITZO (InSnZnO) or IGZO (InGaZnO).

[0186] The oxide semiconductor layer (1500) may include a first oxide semiconductor pattern (1510), a second oxide semiconductor pattern (1520), and a third oxide semiconductor pattern (1530). The first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), and the third oxide semiconductor pattern (1530) may be arranged to be spaced apart from each other.

[0187] The first oxide semiconductor pattern (1510) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The first oxide semiconductor pattern (1510) may be bent to have an approximately “L” shape. The first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) and the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) may be symmetrically disposed with respect to an imaginary line (IML1), and the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) and the first oxide semiconductor pattern (1510) of the third pixel circuit (PC3) may be symmetrically disposed with respect to an imaginary line (IML2).

[0188] The first oxide semiconductor pattern (1510) may include a second semiconductor layer (A2) of a second transistor (T2, FIG. 6) and a third semiconductor layer (A3) of a third transistor (T3, FIG. 6). In other words, the second semiconductor layer (A2) of the second transistor (T2, FIG. 6) and the third semiconductor layer (A3) of the third transistor (T3, FIG. 6) may be connected integrally. The second semiconductor layer (A2) may overlap with a first scan line (GWL1, FIG. 13) to be described later, and the third semiconductor layer (A3) may overlap with a seventh conductive pattern (1620, FIG. 13) to be described later.

[0189] The second oxide semiconductor pattern (1520) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The second oxide semiconductor pattern (1520) may have a shape extending along the second direction (e.g., the y direction). The second oxide semiconductor pattern (1520) of the first pixel circuit (PC1) and the second oxide semiconductor pattern (1520) of the second pixel circuit (PC2) may be symmetrically disposed with respect to an imaginary line (IML1), and the second oxide semiconductor pattern (1520) of the second pixel circuit (PC2) and the second oxide semiconductor pattern (1520) of the third pixel circuit (PC3) may be symmetrically disposed with respect to an imaginary line (IML2).

[0190] The second oxide semiconductor pattern (1520) may include a first semiconductor layer (A1) of a first transistor (T1, FIG. 6). The first semiconductor layer (A1) may overlap with a fourth conductive pattern (1410, FIG. 11) and a sixth conductive pattern (1610, FIG. 13) described below. The fourth conductive pattern (1410, FIG. 11) and the sixth conductive pattern (1610, FIG. 13) may form a dual gate structure of the first transistor (T1, FIG. 6).

[0191] The third oxide semiconductor pattern (1530) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The third oxide semiconductor pattern (1530) may have a shape extending along the second direction (e.g., the y direction). The third oxide semiconductor pattern (1530) of the first pixel circuit (PC1) and the third oxide semiconductor pattern (1530) of the second pixel circuit (PC2) may be symmetrically disposed with respect to an imaginary line (IML1). However, the third oxide semiconductor pattern (1530) of the third pixel circuit (PC3) may further include a portion extending in the first direction (e.g., the x direction) in comparison with the third oxide semiconductor pattern (1530) of the first pixel circuit (PC1) to have an inverted 'L' shape.

[0192] The third oxide semiconductor pattern (1530) may include a fourth semiconductor layer (A4) and a sixth semiconductor layer (A6). In other words, the fourth semiconductor layer (A4) and the sixth semiconductor layer (A6) may be connected integrally. The sixth semiconductor layer (A6) of the third oxide semiconductor pattern (1530) may overlap with the second emission control line (EMBL, FIG. 13) to be described later, and the fourth semiconductor layer (A4) of the third oxide semiconductor pattern (1530) may overlap with the initialization gate line (GIL, FIG. 13) to be described later.

[0193] One end of the third oxide semiconductor pattern (1530) may be connected to a tenth conductive pattern (1730, FIG. 14) to be described later, and may be electrically connected to the first transistor (T1, FIG. 6). The other end of the third oxide semiconductor pattern (1530) may be overlapped and connected to a horizontal initialization voltage line (HVL, FIG. 6). For example, the third oxide semiconductor pattern (1530) of the first pixel circuit (PC1) may be electrically connected to the first horizontal initialization voltage line (HVL1, FIG. 14), and the third oxide semiconductor pattern (1530) of the second pixel circuit (PC2) may be electrically connected to the second horizontal initialization voltage line (HVL2, FIG. 14). The third oxide semiconductor pattern (1530) of the third pixel circuit (PC3) can be electrically connected to the third horizontal initialization voltage line (HVL3, FIG. 13) through the 14th conductive pattern (1770, FIG. 14).

[0194] Each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may include at least a partially conductive region. For example, a conductive process using plasma or the like may be performed on at least a portion of each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540).

[0195] Referring to FIG. 13, a fourth conductive layer (1600) may be disposed on an oxide semiconductor layer (1500). The fourth conductive layer (1600) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0196] The fourth conductive layer (1600) may include a first scan line (GWL1), a second emission control line (EMBL), an initialization gate line (GIL), a third horizontal initialization voltage line (HVL3), a sixth conductive pattern (1610), and a seventh conductive pattern (1620). The first scan line (GWL1), the second emission control line (EMBL), the initialization gate line (GIL), the third horizontal initialization voltage line (HVL3), the sixth conductive pattern (1610), and the seventh conductive pattern (1620) may be arranged to be spaced apart from each other.

[0197] A first scan line (GWL1) may extend along a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The first scan line (GWL1) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2). The first scan line (GWL1) may overlap with a second scan line (GWL2, FIG. 14), which will be described later, but may be electrically connected to the second scan line (GWL2, FIG. 14).

[0198] The first scan line (GWL1) may include a stem portion extending in a first direction (e.g., x-direction) and a branch portion branching off from the stem portion and protruding in a second direction (e.g., y-direction). The branch portion of the first scan line (GWL1) may include a region overlapping with the first oxide semiconductor pattern (1510, FIG. 12), i.e., the second gate electrode (G2) of the second transistor (T2). Referring to FIGS. 12 and 13, the second semiconductor layer (A2) of the second transistor (T2) may include a channel region (C2) overlapping with the first scan line (GWL1) and conductive regions (S2, D2) arranged on both sides of the channel region (C2). One of the conductive regions (S2, D2) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source and drain regions can be interchanged depending on the properties of the transistor.

[0199] The second emission control line (EMBL) may extend along the first direction (e.g., the x-direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second emission control line (EMBL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0200] The second emission control line (EMBL) may include a region overlapping with the third oxide semiconductor pattern (153, FIG. 12), i.e., the sixth gate electrode (G6) of the sixth transistor (T6). Referring to FIGS. 12 and 13, the sixth semiconductor layer (A6) of the sixth transistor (T6) may include a channel region (C6) overlapping with the second emission control line (EMBL) and conductive regions (S6, D6) arranged on both sides of the channel region (C6). One of the conductive regions (S6, D6) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be changed depending on the properties of the transistor.

[0201] An initialization gate line (GIL) can extend along a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The initialization gate line (GIL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0202] The initialization gate line (GIL) may include a region overlapping with the third oxide semiconductor pattern (1530, FIG. 12), i.e., the fourth gate electrode (G4) of the fourth transistor (T4). Referring to FIGS. 12 and 13, the fourth semiconductor layer (A4) of the fourth transistor (T4) may include a channel region (C4) overlapping with the initialization gate line (GIL) and conductive regions (S4, D4) arranged on both sides of the channel region (C4). One of the conductive regions (S4, D4) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0203] A third horizontal initialization voltage line (HVL3) may extend in a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The third horizontal initialization voltage line (HVL3) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2). Specifically, the third horizontal initialization voltage line (HVL3) may include a stem portion extending in the first direction (e.g., x-direction) and a branch portion branching from the stem portion and extending in a second direction (e.g., y-direction). The branch portion of the third horizontal initialization voltage line (HVL3) may be connected to a third oxide semiconductor pattern (1530, FIG. 12) of the third pixel circuit (PC3) via a fourteenth conductive pattern (1770, FIG. 14) to be described later.

[0204] The sixth conductive pattern (1610) disposed in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The sixth conductive pattern (1610) of the first pixel circuit (PC1) may be symmetrically disposed with respect to the sixth conductive pattern (1610) of the second pixel circuit (PC2) and the virtual line (IML1), and the sixth conductive pattern (1610) of the second pixel circuit (PC2) may be symmetrically disposed with respect to the sixth conductive pattern (1610) of the third pixel circuit (PC3) and the virtual line (IML2).

[0205] Each of the sixth conductive patterns (1610) of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an 'L' shape. One end of the sixth conductive pattern (1610) may be electrically connected to the first oxide semiconductor pattern (1510, FIG. 12) via the ninth conductive pattern (1720, FIG. 14). The other end of the sixth conductive pattern (1610) may include the first upper gate electrode (G1a) of the first transistor (T1). Referring to FIGS. 12 and 13, the first semiconductor layer (A1) of the first transistor (T1) may include a channel region (C1) overlapping with the sixth conductive pattern (1610) and conductive regions (S1, D1) arranged on both sides of the channel region (C1). One of the conductive regions (S1, D1) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be changed depending on the properties of the transistor. At this time, a part of the fourth conductive pattern (1410, FIG. 11) and the first upper gate electrode (G1a) may overlap each other with the channel region (C1) therebetween. A part of the fourth conductive pattern (1410, FIG. 11) overlapping with the channel region (C1) of the first transistor (T1) may correspond to the first lower gate electrode (G1b, FIG. 11) of the first transistor (T1).

[0206] The seventh conductive pattern (1620) may have an isolated shape, but may have a shape extending along the first direction (e.g., the x-direction). For example, the seventh conductive pattern (1620) may include a 7-1 conductive pattern (1620a) arranged across the first pixel circuit (PC1) and the second pixel circuit (PC2), and a 7-2 conductive pattern (1620b) arranged in the third pixel circuit (PC3). The 7-1 conductive pattern (1620a) may be arranged to intersect the imaginary line (IML1). That is, the seventh conductive pattern (1620) arranged in the first pixel circuit (PC1) and the seventh conductive pattern (1620) arranged in the second pixel circuit (PC2) may be formed integrally.

[0207] The seventh conductive pattern (1620) of each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include a third gate electrode (G3) of a third transistor (T3). Referring to FIGS. 12 and 13, the third semiconductor layer (A3) of the third transistor (T3) may include a channel region (C3) overlapping the seventh conductive pattern (1620) and conductive regions (S3, D3) arranged on both sides of the channel region (C3). One of the conductive regions (S3, D3) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0208] Referring to FIG. 14, a fifth conductive layer (1700) may be disposed on a fourth conductive layer (1600). The fifth conductive layer (1700) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0209] The fifth conductive layer (1700) may include a second scan line (GWL2), a second horizontal reference voltage line (HVRL2), a reference gate line (GRL), a second horizontal driving voltage line (HPL2), a first horizontal initialization voltage line (HVL1), a second horizontal initialization voltage line (HVL2), a horizontal common voltage line (HVSL), and eighth to fourteenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770). The second scan line (GWL2), the second horizontal reference voltage line (HVRL2), the reference gate line (GRL), the second horizontal driving voltage line (HPL2), the first horizontal initialization voltage line (HVL1), the second horizontal initialization voltage line (HVL2), the horizontal common voltage line (HVSL), and the eighth to fourteenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770) may be arranged to be spaced apart from each other.

[0210] The second scan line (GWL2) can extend along a first direction (e.g., x direction) to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second scan line (GWL2) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second scan line (GWL2) can be arranged to overlap the first scan line (GWL1, FIG. 13), and can be electrically connected to the first scan line (GWL1, FIG. 13) through the first contact hole (CNT1).

[0211] The second horizontal reference voltage line (HVRL2) may extend along the first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second horizontal reference voltage line (HVRL2) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The second horizontal reference voltage line (HVRL2) may be arranged to overlap the first horizontal reference voltage line (HVRL1, FIG. 8).

[0212] The second horizontal reference voltage line (HVRL2) can be electrically connected to the first horizontal reference voltage line (HVRL1, FIG. 8) through the second contact hole (CNT2) and can be electrically connected to the dummy horizontal reference voltage line (HVRLd, FIG. 11) through the third contact hole (CNT3). For example, the first horizontal reference voltage line (HVRL1), the dummy horizontal reference voltage line (HVRLd), and the second horizontal reference voltage line (HVRL2) can be electrically connected to each other to transmit a reference voltage to each pixel circuit. In addition, the second horizontal reference voltage line (HVRL2) can be connected to the second oxide semiconductor pattern (1510, FIG. 12) through the fourth contact hole (CNT4) to transmit a reference voltage to the third transistor (T3, FIG. 13).

[0213] A reference gate line (GRL) may extend along a first direction (e.g., x direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The reference gate line (GRL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The reference gate line (GRL) may be electrically connected to a seventh conductive pattern (1620, FIG. 13) through a contact hole to transmit a reference signal to a gate electrode of a third transistor (T3, FIG. 13). For example, the reference gate line (GRL) can be electrically connected to the 7-1 conductive pattern (1620a, FIG. 13) through the 5-1 contact hole (CNT5a) and the 5-2 contact hole (CNT5b), and can be electrically connected to the 7-2 conductive pattern (1620b, FIG. 13) through the 5-3 contact hole (CNT5c).

[0214] The eighth conductive pattern (1710) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The eighth conductive pattern (1710) of the first pixel circuit (PC1) and the eighth conductive pattern (1710) of the second pixel circuit (PC2) may be symmetrically arranged with respect to the virtual line (IML1), and the eighth conductive pattern (1710) of the second pixel circuit (PC2) and the eighth conductive pattern (1710) of the third pixel circuit (PC3) may be symmetrically arranged with respect to the virtual line (IML2).

[0215] The eighth conductive pattern (1710) may be a connection electrode connecting the first oxide semiconductor pattern (1510, FIG. 12) including the second semiconductor layer (A2, FIG. 12) and the data line (DL, FIG. 15). The eighth conductive pattern (1710) may be connected to one end of the first oxide semiconductor pattern (1510, FIG. 12) through the sixth contact hole (CNT6).

[0216] The ninth conductive pattern (1720) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The ninth conductive pattern (1720) of the first pixel circuit (PC1) and the ninth conductive pattern (1720) of the second pixel circuit (PC2) may be symmetrically arranged with respect to the virtual line (IML1), and the ninth conductive pattern (1720) of the second pixel circuit (PC2) and the ninth conductive pattern (1720) of the third pixel circuit (PC3) may be symmetrically arranged with respect to the virtual line (IML2).

[0217] The ninth conductive pattern (1720) may be a connection electrode connecting the first oxide semiconductor pattern (1510, FIG. 12) including the second semiconductor layer (A2, FIG. 12) and the third semiconductor layer (A3, FIG. 12) and the sixth conductive pattern (1610, FIG. 13) including the first upper gate electrode (G1a, FIG. 13) of the first transistor (T1, FIG. 13). For example, the ninth conductive pattern (1720) may be a first node electrode connecting the first transistor (T1, FIG. 13), the second transistor (T2, FIG. 13), and the third transistor (T3, FIG. 13). (Here, the first node electrode may correspond to the first node (N1) of FIG. 5.) The ninth conductive pattern (1720) may be connected to the first oxide semiconductor pattern (1510, FIG. 12) through the seventh contact hole (CNT7) and may be connected to the sixth conductive pattern (1610, FIG. 13) through the ninth contact hole (CNT9).

[0218] Additionally, the ninth conductive pattern (1720) can be electrically connected to a storage capacitor (Cst, FIG. 6). The ninth conductive pattern (1720) can be connected to a first storage electrode (CEs1, FIG. 9) of the storage capacitor (Cst, FIG. 6) through the eighth contact hole (CNT8).

[0219] The tenth conductive pattern (1730) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The tenth conductive pattern (1730) may be arranged to overlap the third conductive pattern (1310, FIG. 10). The tenth conductive pattern (1730) of the first pixel circuit (PC1) and the tenth conductive pattern (1730) of the second pixel circuit (PC2) may be arranged symmetrically with respect to the virtual line (IML1), and the tenth conductive pattern (1730) of the second pixel circuit (PC2) and the tenth conductive pattern (1730) of the third pixel circuit (PC3) may be arranged symmetrically with respect to the virtual line (IML2).

[0220] The tenth conductive pattern (1730) may be a connection electrode connecting a second oxide semiconductor pattern (1520, FIG. 12) including a first semiconductor layer (A1, FIG. 12) and a third oxide semiconductor pattern (1530, FIG. 12) including a sixth semiconductor layer (A6, FIG. 12). For example, the tenth conductive pattern (1730) may be a second node electrode connecting a first transistor (T1, FIG. 13) and a sixth transistor (T6, FIG. 13). (Here, the second node electrode may correspond to the second node (N2) of FIG. 5.) The 10th conductive pattern (1730) may be connected to the second oxide semiconductor pattern (1520, FIG. 12) through the 12th contact hole (CNT12) and may be connected to the third oxide semiconductor pattern (1530, FIG. 12) through the 13th contact hole (CNT13).

[0221] Additionally, the tenth conductive pattern (1730) may be electrically connected to a storage capacitor (Cst, FIG. 6), a hold capacitor (Chd, FIG. 6), and a first lower gate electrode (G1b, FIG. 11) of a first transistor (T1, FIG. 13). The tenth conductive pattern (1730) may be electrically connected to a third conductive pattern (1310, FIG. 10) including a second storage electrode (CEs2, FIG. 10) and a second hold electrode (CEh2, FIG. 10) through a tenth contact hole (CNT10). The tenth conductive pattern (1730) may be electrically connected to a fourth conductive pattern (1410, FIG. 11) including a first lower gate electrode (G1b, FIG. 11) through an eleventh contact hole (CNT11).

[0222] The 11th conductive pattern (1740) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The 11th conductive pattern (1740) may have a shape extending along the first direction (e.g., the x-direction). The 11th conductive pattern (1740) of the first pixel circuit (PC1) and the 11th conductive pattern (1740) of the second pixel circuit (PC2) may be symmetrically arranged with respect to the virtual line (IML1), and the 11th conductive pattern (1740) of the second pixel circuit (PC2) and the 11th conductive pattern (1740) of the third pixel circuit (PC3) may be symmetrically arranged with respect to the virtual line (IML2).

[0223] The 11th conductive pattern (1740) may be a connection electrode connecting a second oxide semiconductor pattern (1520, FIG. 12) including a first semiconductor layer (A1, FIG. 12) and a first silicon semiconductor pattern (1110, FIG. 8) including a fifth semiconductor layer (A5, FIG. 8). One end of the 11th conductive pattern (1740) may be electrically connected to the second oxide semiconductor pattern (1520, FIG. 12) through a 14th contact hole (CNT14), and the other end of the 11th conductive pattern (1740) may be electrically connected to the first silicon semiconductor pattern (1110, FIG. 8) through a 15th contact hole (CNT15).

[0224] The twelfth conductive pattern (1750) may extend along the first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The twelfth conductive pattern (1750) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The twelfth conductive pattern (1750) may be electrically connected to a first vertical driving voltage line (VPL1, FIG. 15), a second vertical driving voltage line (VPL2, FIG. 15), and a first horizontal driving voltage line (HPL1, FIG. 9), which will be described later, to transmit a driving voltage to each pixel circuit. Accordingly, the twelfth conductive pattern (1750) may also be referred to as a second horizontal driving voltage line (HPL2).

[0225] For example, the 12th conductive pattern (1750) may include a stem portion (1750t) extending in a first direction (e.g., x-direction) and a branch portion (1750b) branching from the stem portion (1750t) and extending in a second direction (e.g., y-direction). The branch portion (1750b) of the 12th conductive pattern (1750) may include a first branch portion (1750b1) extending to overlap with a first branch portion (1220b1, FIG. 9) of a first horizontal driving voltage line (HPL1, FIG. 9) and a second branch portion (1750b2) extending to overlap with a second branch portion (1220b2, FIG. 9) of the first horizontal driving voltage line (HPL1, FIG. 9). For example, the first branch portion (1750b1) of the 12th conductive pattern (1750) may refer to a portion of the 12th conductive pattern (1750) that branches off from the end of the stem portion (1750t) and extends in a second direction (e.g., in the y direction). The second branch portion (1750b2) of the 12th conductive pattern (1750) may refer to a portion of the 12th conductive pattern (1750) that branches off from the stem portion (1750t) and extends in a second direction (e.g., in the y direction) on an imaginary line (IML2) and is arranged across the second pixel circuit (PC2) and the third pixel circuit (PC3).

[0226] The stem portion (1750t) of the 12th conductive pattern (1750) can receive a driving voltage from the first vertical driving voltage line (VPL1, FIG. 15) and the second vertical driving voltage line (VPL2, FIG. 15), which will be described later, and be electrically connected to the first silicon semiconductor pattern (1110, FIG. 8) through the 17th contact hole (CNT17). Accordingly, the 12th conductive pattern (1750), for example, the second horizontal driving voltage line (HPL2), can transmit a driving voltage to the fifth transistor (T5, FIG. 9).

[0227] Additionally, the first branch (1750b1) of the 12th conductive pattern (1750) can be electrically connected to the first branch (1220b1, FIG. 9) of the second conductive pattern (1220, FIG. 9) through the 16-1 contact hole (CNT16a). The second branch (1750b2) of the 12th conductive pattern (1750) can be electrically connected to the second branch (1220b2, FIG. 9) of the second conductive pattern (1220, FIG. 9) through the 16-2 contact hole (CNT16b). Accordingly, the 12th challenge pattern (1750), for example, the second horizontal driving voltage line (HPL2), can transmit a driving voltage to the first horizontal driving voltage line (HPL1, FIG. 9), and the first horizontal driving voltage line (HPL1, FIG. 9) can transmit a driving voltage to the first hold electrode (CEh1, FIG. 9) of the hold capacitor (Chd, FIG. 6).

[0228] The 13th conductive pattern (1760) positioned in each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have an isolated shape. The 13th conductive pattern (1760) may have a shape extending along the first direction (e.g., the x direction). The 13-1 conductive pattern (1760a) of the first pixel circuit (PC1) and the 13-2 conductive pattern (1760b) of the second pixel circuit (PC2) may be symmetrically arranged with respect to an imaginary line (IML1). The 13-3 conductive pattern (1760c) of the third pixel circuit (PC3) may further include a protrusion extending diagonally in the same shape as the 13-1 conductive pattern (1760a) of the first pixel circuit (PC1). The protrusion of the 13-3 challenge pattern (1760c) may be connected to the 16th challenge pattern (1820, Fig. 15) described later.

[0229] The 13th conductive pattern (1760) may be a connection electrode connecting a third oxide semiconductor pattern (1530, FIG. 12) including a fourth semiconductor layer (A4, FIG. 12) and a sixth semiconductor layer (A6, FIG. 12) and a light-emitting diode (LED, FIG. 7). For example, the 13th conductive pattern (1760) may be electrically connected to the third oxide semiconductor pattern (1530, FIG. 12) through a 19th contact hole (CNT19) and may be electrically connected to a light-emitting diode (LED, FIG. 7) through a 16th conductive pattern (1820, FIG. 15) to be described later. For example, the 13th conductive pattern (1760) may be a pixel connection electrode connecting a fourth transistor (T4, FIG. 13) and a sixth transistor (T6, FIG. 13) to a light-emitting diode (LED, FIG. 7). Accordingly, the 13th challenge pattern (1760) may also be referred to as the first pixel connection electrode.

[0230] Meanwhile, the 13th conductive pattern (1760) may be arranged to overlap with the repair line (RPL, FIG. 10) and the 5th conductive pattern (1420, FIG. 11). As described above, when the pixel circuit is defective, in the repair process, the 13th conductive pattern (1760), which is a pixel connection electrode, and the 3rd oxide semiconductor pattern (1530, FIG. 12) are insulated, and the 13th conductive pattern (1760) and the repair line (RPL, FIG. 10) are connected, so that normal driving current can be transmitted from the dummy circuit. The 5th conductive pattern (1420, FIG. 11), which is a repair bridge pattern, may be arranged between the 13th conductive pattern (1760) and the repair line (RPL, FIG. 10). The 13th conductive pattern (1760) can be electrically connected to the 5th conductive pattern (1420, FIG. 11) through the 18th contact hole (CNT18), and can short-circuit the repair line (RPL, FIG. 10) and the 5th conductive pattern (1420, FIG. 11) during a repair process. That is, as a pixel connection electrode, a part of the 13th conductive pattern (1760) can overlap the 3rd oxide semiconductor pattern (1530, FIG. 12), and another part of the 13th conductive pattern (1760) can overlap the 5th conductive pattern (1420, FIG. 11).

[0231] A first horizontal initialization voltage line (HVL1) and a second horizontal initialization voltage line (HVL2) may extend along a first direction (e.g., x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The first horizontal initialization voltage line (HVL1) and the second horizontal initialization voltage line (HVL2) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The first horizontal initialization voltage line (HVL1) may be electrically connected to a third oxide semiconductor pattern (1530, FIG. 12) of the first pixel circuit (PC1) through a 20-1 contact hole (CNT20a) to transmit an initialization voltage to a fourth transistor (T4, FIG. 13) of the first pixel circuit (PC1). The second horizontal initialization voltage line (HVL2) is electrically connected to the third oxide semiconductor pattern (1530, FIG. 12) of the second pixel circuit (PC2) through the 20-2 contact hole (CNT20b), and can transmit an initialization voltage to the fourth transistor (T4, FIG. 13) of the second pixel circuit (PC2).

[0232] The 14th conductive pattern (1770) may have an isolated shape and may be arranged on an imaginary line (IML2) which is a boundary between the second pixel circuit (PC2) and the third pixel circuit (PC3). The 14th conductive pattern (1770) may have a shape extending along the first direction (e.g., the x-direction). The 14th conductive pattern (1770) may be a connecting electrode connecting the third oxide semiconductor pattern (1530, FIG. 12) of the third pixel circuit (PC3) and the third horizontal initialization voltage line (HVL3, FIG. 13). The 14th challenge pattern (1770) is electrically connected to the third oxide semiconductor pattern (1530, FIG. 12) through the 20-3 contact hole (CNT20c) and electrically connected to the third horizontal initialization voltage line (HVL3, FIG. 13) through the 20-4 contact hole (CNT20d), so as to transmit an initialization voltage to the fourth transistor (T4, FIG. 13) of the third pixel circuit (PC3).

[0233] A horizontal common voltage line (HVSL) can extend along a first direction (e.g., x direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The horizontal common voltage line (HVSL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The horizontal common voltage line (HVSL) can be electrically connected to a first vertical common voltage line (VVSL1, FIG. 15) or a second vertical common voltage line (VVSL2, FIG. 15), which will be described later, to transmit a common voltage to a light emitting diode (LED, FIG. 8).

[0234] Referring to FIG. 15, a sixth conductive layer (1800) may be disposed on a fifth conductive layer (1700). The sixth conductive layer (1800) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0235] The sixth conductive layer (1800) may include a data line (DL), a vertical driving voltage line (VPL), a vertical initialization voltage line (VVL, or second vertical common voltage line), a first vertical common voltage line (VVSL1, or vertical reference voltage line), a fifteenth conductive pattern (1810), and a sixteenth conductive pattern (1820). The data line (DL), the vertical driving voltage line (VPL), the vertical initialization voltage line (VVL), the first vertical common voltage line (VVSL1), the fifteenth conductive pattern (1810), and the sixteenth conductive pattern (1820) may be arranged to be spaced apart from each other.

[0236] The data line (DL) may extend along a second direction (e.g., the y direction). The data line (DL) may include a first data line (DL1) electrically connected to a first pixel circuit (PC1), a second data line (DL2) electrically connected to a second pixel circuit (PC2), and a third data line (DL3) electrically connected to a third pixel circuit (PC3). The data line (DL) may be electrically connected through an eighth conductive pattern (1710, FIG. 14) and a twenty-first contact hole (CNT21) connected to a first oxide semiconductor pattern (1510, FIG. 12). For example, the data line (DL) may transmit a data signal to a second semiconductor layer (A2, FIG. 12) through the eighth conductive pattern (1710, FIG. 14).

[0237] A first data line (DL1) may be arranged to pass through a first pixel circuit (PC1), a second data line (DL2) may be arranged to pass through a second pixel circuit (PC2), and a third data line (DL3) may be arranged to pass through a third pixel circuit (PC3) except for some areas. The first data line (DL1) may be arranged on the left side of the first vertical driving voltage line (VPL1). The second data line (DL2) and the third data line (DL3) may be arranged in parallel between the second vertical driving voltage line (VPL2) and the vertical reference voltage line (VVRL, or second vertical common voltage line).

[0238] The vertical driving voltage line (VPL) may extend along a second direction (e.g., y direction). The vertical driving voltage line (VPL) may include a first vertical driving voltage line (VPL1) disposed on a first pixel circuit (PC1) and a second vertical driving voltage line (VPL2) disposed on a second pixel circuit (PC2). The first vertical driving voltage line (VPL1) and the second vertical driving voltage line (VPL2) may be symmetrically disposed with respect to an imaginary line (IML1). The first vertical driving voltage line (VPL1) may be electrically connected to a second horizontal driving voltage line (HPL2, FIG. 14) through a 22-1 contact hole (CNT22a), and the second vertical driving voltage line (VPL2) may be electrically connected to a second horizontal driving voltage line (HPL2, FIG. 14) through a 22-2 contact hole (CNT22b).

[0239] A vertical initialization voltage line (VVL) may extend along a second direction (e.g., y-direction). The vertical initialization voltage line (VVL) may be arranged between a first vertical driving voltage line (VPL1) and a second vertical driving voltage line (VPL2). The vertical initialization voltage line (VVL) may be arranged on a virtual line (IML1) which is a boundary between a first pixel circuit (PC1) and a second pixel circuit (PC2). The vertical initialization voltage line (VVL) may be electrically connected to a first horizontal initialization voltage line (HVL1, FIG. 14) through a 23rd contact hole (CNT23). In some other embodiments, the vertical initialization voltage line (VVL) may also function as a second vertical common voltage line (VVSL2) depending on a connection relationship.

[0240] The first vertical common voltage line (VVSL1) may extend along the second direction (e.g., the y direction). The first vertical common voltage line (VVSL1) may be arranged on the third pixel circuit (PC3). The first vertical common voltage line (VVSL1) may be electrically connected to a horizontal common voltage line (HVSL, FIG. 14) through a 24th contact hole (CNT24) and may be electrically connected to a light-emitting diode (LED, FIG. 7) through a 28th contact hole (CNT28). That is, the horizontal common voltage line (HVSL, FIG. 14) and the first vertical common voltage line (VVSL1) may be electrically connected to a common voltage wire (16, FIG. 3) arranged in a peripheral area (PA, FIG. 3) to transmit a common voltage to the light-emitting diode (LED, FIG. 7). In some other embodiments, the first vertical common voltage line (VVSL1) may also function as a vertical reference voltage line (VVRL) depending on the connection relationship.

[0241] The 15th conductive pattern (1810) and the 16th conductive pattern (1820) may each have an isolated shape. The 15th conductive pattern (1810) and the 16th conductive pattern (1820) may be arranged in the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3), respectively. The 15th conductive pattern (1810) may be electrically connected to the 10th conductive pattern (1730, FIG. 14) through the 25th contact hole (CNT25) and may have a shape extending along the second direction (e.g., the y direction) to cover the 9th conductive pattern (1720, FIG. 14). As the 15th challenge pattern (1810) shields the 9th challenge pattern (1720, FIG. 14) electrically connected to the storage capacitor (Cst, FIG. 6), image quality characteristics can be improved.

[0242] The 16th conductive pattern (1820) may be a connection electrode connecting the third oxide semiconductor pattern (1530, FIG. 12) and the light-emitting diode (LED, FIG. 7). The 16th conductive pattern (1820) may be electrically connected to the 13th conductive pattern (1760, FIG. 14) through the 26th contact hole (CNT26) and may be electrically connected to the pixel electrode (210, FIG. 7) of the light-emitting diode (LED, FIG. 7) through the 27th contact hole (CNT27). Accordingly, the 16th conductive pattern (1820) may also be referred to as a second pixel connection electrode.

[0243] FIG. 16a and FIG. 16b are plan views schematically showing pixel circuits of a display device according to one embodiment of the present invention, respectively.

[0244] Referring to FIGS. 16A and 16B, the third conductive layer (1400) may include a fourth conductive pattern (1410), a fifth conductive pattern (1420), and a dummy horizontal common voltage line (HVSLd). The fourth conductive pattern (1410), the fifth conductive pattern (1420), and the dummy horizontal common voltage line (HVSLd) may be arranged to be spaced apart from each other. Meanwhile, the fifth conductive layer (1700) may include a second scan line (GWL2), a second horizontal reference voltage line (HVRL2), a reference gate line (GRL), a second horizontal driving voltage line (HPL2), a first horizontal initialization voltage line (HVL1), a second horizontal initialization voltage line (HVL2), a horizontal common voltage line (HVSL), and eighth to fourteenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770).

[0245] A dummy horizontal common voltage line (HVSLd) may extend along a first direction (e.g., an x-direction) so as to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The dummy horizontal common voltage line (HVSLd) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The dummy horizontal common voltage line (HVSLd) may be arranged so as to overlap a portion of the horizontal common voltage line (HVSL) in a plane. The dummy horizontal common voltage line (HVSLd) may be electrically connected to the horizontal common voltage line (HVSL) through a 29th contact hole (CNT29).

[0246] As with the dummy horizontal common voltage line (HVSLd), the third conductive layer (1400) may include a dummy wiring electrically connected to at least one of the plurality of voltage lines. As described above, when the pattern density of a specific layer is low, the pattern may be unevenly deposited, or process problems such as poor exposure, over-etching, or under-etching may occur. Accordingly, the display device according to one embodiment of the present invention may place a dummy horizontal common voltage line (HVSLd) on the third conductive layer (1400) having a relatively low pattern density, thereby increasing the pattern density of the third conductive layer (1400) and improving the stability of the display device manufacturing process.

[0247] FIG. 17a and FIG. 17b are plan views schematically showing pixel circuits of a display device according to one embodiment of the present invention, respectively.

[0248] Referring to FIGS. 17A and 17B, the third conductive layer (1400) may include a fourth conductive pattern (1410), a fifth conductive pattern (1420), and a dummy horizontal driving voltage line (HPLd). The fourth conductive pattern (1410), the fifth conductive pattern (1420), and the dummy horizontal driving voltage line (HPLd) may be arranged to be spaced apart from each other. Meanwhile, the fifth conductive layer (1700) may include a second scan line (GWL2), a second horizontal reference voltage line (HVRL2), a reference gate line (GRL), a second horizontal driving voltage line (HPL2), a first horizontal initialization voltage line (HVL1), a second horizontal initialization voltage line (HVL2), a horizontal common voltage line (HVSL), and eighth to fourteenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770).

[0249] A dummy horizontal driving voltage line (HPLd) may extend along a first direction (e.g., an x-direction) so as to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The dummy horizontal driving voltage line (HPLd) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The dummy horizontal driving voltage line (HPLd) may be arranged so as to overlap a portion of the second horizontal driving voltage line (HPL2) in a plane. The dummy horizontal driving voltage line (HPLd) may be electrically connected to the second horizontal driving voltage line (HPL2) through a 30th contact hole (CNT30).

[0250] As with the dummy horizontal driving voltage line (HPLd), the third conductive layer (1400) may include a dummy wiring electrically connected to at least one of the plurality of voltage lines. As described above, when the pattern density of a specific layer is low, the pattern may be deposited unevenly, or process problems such as poor exposure, over-etching, or under-etching may occur. Accordingly, the display device according to one embodiment of the present invention may place the dummy horizontal driving voltage line (HPLd) on the third conductive layer (1400) having a relatively low pattern density, thereby increasing the pattern density of the third conductive layer (1400) and improving the stability of the display device manufacturing process.

[0251] FIG. 18a and FIG. 18b are plan views schematically illustrating pixel circuits of a display device according to one embodiment of the present invention, respectively.

[0252] Referring to FIGS. 18A and 18B, the third conductive layer (1400) may include a fourth conductive pattern (1410), a fifth conductive pattern (1420), and a dummy horizontal initialization voltage line (HVLd). The fourth conductive pattern (1410), the fifth conductive pattern (1420), and the dummy horizontal initialization voltage line (HVLd) may be arranged to be spaced apart from each other. Meanwhile, the fifth conductive layer (1700) may include a second scan line (GWL2), a second horizontal reference voltage line (HVRL2), a reference gate line (GRL), a second horizontal driving voltage line (HPL2), a first horizontal initialization voltage line (HVL1), a second horizontal initialization voltage line (HVL2), a horizontal common voltage line (HVSL), and eighth to fourteenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770).

[0253] A dummy horizontal initialization voltage line (HVLd) may extend along a first direction (e.g., an x-direction) to pass through a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3). The dummy horizontal initialization voltage line (HVLd) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3). The dummy horizontal initialization voltage line (HVLd) may further include a protrusion that extends so as to overlap a portion of the first horizontal initialization voltage line (HVL1) in a plane. The dummy horizontal initialization voltage line (HVLd) may be electrically connected to the first horizontal initialization voltage line (HVL1) through a 31st contact hole (CNT31). In another embodiment, the dummy horizontal initialization voltage line (HVLd) may be electrically connected to a second horizontal initialization voltage line (HVL2) or a third horizontal initialization voltage line (HVL3, FIG. 13).

[0254] As described above, when the pattern density of a specific layer is low, the pattern may be unevenly deposited, or process problems such as poor exposure, over-etching, or under-etching may occur. Accordingly, the display device according to an embodiment of the present invention may place the dummy horizontal initialization voltage line (HVLd) on the third conductive layer (1400) having a relatively low pattern density, thereby increasing the pattern density of the third conductive layer (1400) and improving the stability of the display device manufacturing process.

[0255] Figure 19 is a block diagram of an electronic device according to one embodiment of the present invention.

[0256] Referring to FIG. 19, an electronic device (1000) according to one embodiment may include a display module (110), a processor (120), a memory (130), and a power module (140).

[0257] The electronic device (1000) can output various information through the display module (110) within the operating system.

[0258] The processor (120) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In one embodiment, the processor (120) may be provided by being divided into two or more from a functional or structural standpoint. For example, the processor (120) may include a main processor in the form of a first driving chip that includes a central processing unit, and an auxiliary processor in the form of a second driving chip that includes a controller that receives an image signal from the main processor and processes the image signal to meet the interface specifications of the display module (110).

[0259] The memory (130) may include at least one of non-volatile memory and volatile memory. The memory (130) may store data information necessary for the operation of the processor (120) or the display module (110). When the processor (120) executes an application stored in the memory (130), an image data signal and / or an input control signal is transmitted to the display module (110), and the display module (110) may process the received signal and output image information through a display screen.

[0260] The power module (140) may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device (1000). Power conversion by the power conversion module may include, but is not limited to, DC-DC conversion, AC-DC conversion, and DC-AC conversion.

[0261] At least one of the components of the electronic device (1000) described above may be included in the display device according to the embodiments described above. In addition, some of the individual modules functionally included in one module may be included in the display device, and others may be provided separately from the display device. For example, the display device may include a display module (110) and an auxiliary processor among the processors (120), and the main processor among the processors (120), the memory (130), and the power module (140) may be provided in the form of other devices within the electronic device (1000) other than the display device. As another example, the power module (140) may be provided within the display device and supply power to the processor (120) and the memory (130) provided within the electronic device (1000) other than the display device, but is not limited to the above examples.

[0262] FIG. 20 is a schematic diagram of electronic devices according to various embodiments of the present invention.

[0263] The display device according to embodiments of the present invention is a device for displaying a moving image or a still image, and can be applied to various electronic devices. Referring to FIG. 20, various electronic devices to which the display device according to embodiments is applied may include not only image display electronic devices such as a smart phone (1_1a), a tablet PC (1_1b), a laptop / notebook computer (1_1c), a TV (1_1d), and a computer monitor (1_1e), but also wearable electronic devices including a display module such as smart glasses (1_2a), a head-mounted display (1_2b), and a smart watch (1_2c), and vehicle electronic devices (10_3) including a display module such as a CID (Center Information Display) and a room mirror display arranged on an automobile's instrument panel, center fascia, and dashboard. The electronic device (1000) according to embodiments of the present invention is not limited to the above-described devices.

[0264] The electronic device of FIG. 20 may include the components illustrated in FIG. 19. For example, a smartphone (1_1a) may include a display module (110), a processor (120), a memory (130), and a power module (140) illustrated in FIG. 19. The smartphone (1_1a) may further include a communication module and a battery device. Power provided from the battery device may be converted through the power module (140) and provided to the processor (120), the memory (130), and the display module (110). In one embodiment, the display device applied to the smartphone (1_1a) may include a display module (110) and further include a power module (140). The processor (120) and the memory (130) may be provided in the form of chips mounted on a motherboard, which is an external device, but are not limited thereto.

[0265] Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and variations of the embodiments are possible.

Claims

1. Substrate; A first pixel circuit disposed on the substrate and including a driving transistor and a storage capacitor; A light emitting diode electrically connected to the first pixel circuit; and A repair line is disposed on the substrate and extends in a first direction; The above first pixel circuit, A first pixel connection electrode electrically connected to the pixel electrode of the light-emitting diode; and Further comprising a repair bridge pattern disposed between the repair line and the first pixel connection electrode; A display device, wherein when viewed in a direction perpendicular to the substrate, the repair bridge pattern overlaps the repair line and the first pixel connection electrode.

2. In paragraph 1, The above first pixel circuit, A first conductive pattern disposed on the substrate and including a first electrode of the storage capacitor; A second conductive pattern disposed on the first conductive pattern to overlap with the first conductive pattern and including a second electrode of the storage capacitor; A third conductive pattern disposed on the second conductive pattern and including a lower gate electrode of the driving transistor; A first semiconductor pattern disposed on the third conductive pattern and including a semiconductor layer of the driving transistor; and A display device further comprising a fourth conductive pattern disposed on the first semiconductor pattern and including an upper gate electrode of the driving transistor.

3. In paragraph 2, The above repair line is arranged on the same layer as the first conductive pattern or the second conductive pattern, A display device in which the above repair bridge pattern is arranged on the same layer as the third conductive pattern.

4. In paragraph 2, A display device, wherein the first semiconductor pattern includes an oxide semiconductor material.

5. In paragraph 2, The above first pixel circuit, A fifth conductive pattern disposed on the fourth conductive pattern and on the same layer as the first pixel connection electrode; A display device further comprising a second semiconductor pattern disposed on the same layer as the first semiconductor pattern, connected to the fifth conductive pattern, and including a semiconductor layer of a light-emitting control transistor.

6. In paragraph 5, When viewed from a direction perpendicular to the above substrate, The first part of the first pixel connection electrode overlaps the second semiconductor pattern, A display device, wherein the second portion of the first pixel connection electrode overlaps the repair bridge pattern.

7. In paragraph 6, The first pixel circuit further includes a second pixel connection electrode disposed on the first pixel connection electrode and connecting the first pixel connection electrode and the light-emitting diode; A display device in which the first pixel connection electrode and the second pixel connection electrode electrically connect the second semiconductor pattern and the light-emitting diode.

8. In paragraph 1, Further comprising a plurality of voltage lines arranged on the substrate and extending in the first direction or in a second direction intersecting the first direction; The first pixel circuit further includes a dummy wiring that is arranged on the same layer as the repair bridge pattern and extends in the first direction; A display device, wherein the dummy wiring is electrically connected to at least one of the plurality of voltage lines.

9. In paragraph 8, The above plurality of voltage lines include a reference voltage line extending in the first direction, The first pixel circuit further includes a reference transistor connected between the driving transistor and the reference voltage line, The above dummy wiring is a display device electrically connected to the above reference voltage line.

10. In paragraph 9, The above reference voltage line includes an upper reference voltage line arranged on the same layer as the first pixel connection electrode, A display device in which the above dummy wiring is connected to the upper reference voltage line through a contact hole.

11. In paragraph 10, The above reference voltage line further includes a lower reference voltage line positioned lower than the upper reference voltage line, A display device, wherein the lower reference voltage line comprises a silicon semiconductor material.

12. In paragraph 8, The above plurality of voltage lines extend in the first direction and include a common voltage line electrically connected to the light emitting diode, The above dummy wiring is a display device electrically connected to the common voltage line.

13. In paragraph 8, The above plurality of voltage lines include a driving voltage line extending in the first direction, The first pixel circuit further includes a driving control transistor connected between the driving transistor and the driving voltage line, A display device in which the above dummy wiring is electrically connected to the above driving voltage line.

14. In paragraph 8, The above plurality of voltage lines include an initialization voltage line extending in the first direction, The above first pixel circuit, A light-emitting control transistor connected between the driving transistor and the light-emitting diode; and Further comprising an initialization transistor connected between the light emitting control transistor and the initialization voltage line; A display device in which the above dummy wiring is electrically connected to the above initialization voltage line.

15. Substrate; A first pixel circuit disposed on the substrate and including a first transistor and a storage capacitor; A light emitting diode electrically connected to the first pixel circuit; and A plurality of voltage lines are arranged on the substrate and extend in a first direction; The above first pixel circuit, A first conductive pattern including a lower gate electrode of the first transistor; and Further comprising a dummy wiring disposed on the same layer as the first challenge pattern and extending in the first direction; An electronic device wherein the dummy wiring is electrically connected to at least one of the plurality of voltage lines.

16. In paragraph 15, Further comprising a data line extending in a second direction intersecting the first direction and connected to the first pixel circuit; The above plurality of voltage lines include a reference voltage line extending in the first direction, The above first pixel circuit, a second transistor connected between the data line and the first transistor; and Further comprising a third transistor connected between the reference voltage line and the first transistor; An electronic device in which the above dummy wiring is electrically connected to the above reference voltage line.

17. In paragraph 15, The above plurality of voltage lines extend in the first direction and include a common voltage line electrically connected to the light emitting diode, An electronic device in which the above dummy wiring is electrically connected to the above common voltage line.

18. In paragraph 15, The above plurality of voltage lines include an initialization voltage line extending in the first direction, The first pixel circuit further includes a fourth transistor connected between the initialization voltage line and the light emitting diode; An electronic device wherein the above dummy wiring is electrically connected to the above initialization voltage line.

19. In paragraph 15, The above plurality of voltage lines include a driving voltage line extending in the first direction, The first pixel circuit further includes a fifth transistor connected between the driving voltage line and the first transistor; An electronic device in which the above dummy wiring is electrically connected to the above driving voltage line.

20. In paragraph 19, An electronic device wherein the semiconductor layer of the first transistor and the semiconductor layer of the fifth transistor are disposed on different layers.

Images