Systems and methods for cooling elements for semiconductor and multi-terminal devices

Abstract

The present disclosure provides systems and methods for cooling systems for semiconductor and multi-terminal devices. In an aspect, the present disclosure provides a method for dissipating heat from a semiconductor device using a cooling element comprising diamond or another suitable material. In another aspect, the present disclosure provides a method for dissipating heat from a multi-terminal device supplied in a die, the method including attaching a heat distribution layer to a first aide of said die wherein attaching the heat distribution layer comprises mechanical connection, thermal connection, and electrical connection.

Description

SYSTEMS AND METHODS FOR COOLING ELEMENTS FOR SEMICONDUCTORAND MULTI-TERMINAL DEVICESCROSS-REFERENCE

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 675,413, filed July 25, 2024, and U.S. Provisional Application No. 63 / 792,091, filed April 21, 2025, each of which is incorporated herein by reference in their entireties.BACKGROUND

[0002] Modem systems which require fast computation rates use very dense electrical circuits in multi-terminal devices which use great amounts of power to operate. Examples of such multi-terminal devices are a Graphics Processing Unit (GPU) or Central Processing Unit (CPU) of a computer system or Power Amplifier circuits for communication and / or RADAR tracking systems. Due to inefficiencies inherent in the circuits of these multi-terminal devices, they also generate large amounts of heat during operation. This heat, if not dissipated property, may negatively affect the circuit performance and circuit lifetime. In many cases, it is the removal of the heat from these circuits which is the limiting factor for the multi-terminal devices’ optimal performance.SUMMARY

[0003] The present disclosure provides systems and methods for cooling systems for semiconductor and multi-terminal devices. In an aspect, the present disclosure provides a method for dissipating heat from a semiconductor device using a cooling element comprising diamond or another suitable material. In another aspect, the present disclosure provides a method for dissipating heat from a multi-terminal device supplied in a die, the method comprising attaching a heat distribution layer to a first aide of said die wherein attaching the heat distribution layer comprises mechanical connection, thermal connection, and electrical connection.

[0004] Disclosed herein is a system for cooling a semiconductor device. The system can comprise a wafer comprising a first material having a thermal conductivity greater than about 1,000 Watts per meter-Kelvin (W / mK) at room temperature. The system can comprise an interfacial layer comprising a first cooling element. In some cases, wherein the first cooling element comprises a second material different from the first material. In some cases, the wafer is coupled to the semiconductor device via the interfacial material.

[0005] Provided herein is a method for cooling a semiconductor device. The method can comprise coupling a wafer to the semiconductor device via an interfacial layer. In some cases, the wafer comprises a first material having a thermal conductivity greater than about 1,000 Watts per meter-Kelvin (W / mK) at room temperature. In some cases, the interfacial layer comprises a first cooling element comprising a second material different from the first material.

[0006] Disclosed herein is a method for manufacturing a known good die (KGD). The method can comprise probing a wafer to create a plurality of electrical outputs on a first side of the wafer. The method can comprise cutting the wafer into one or more dies. In some cases, each of the one or more dies comprises an electrical output of the plurality of electrical outputs in both distal ends of a first side of the one or more dies. The method can comprise forming a plurality of vias in a heat dissipating layer (HDL). In some cases, a separation distance between at least some of the plurality of the plurality of vias is substantially the same as a separation distance between at least some of the plurality of electrical outputs on the one or more dies. The method can comprise lining up the plurality of vias in the HDL and the electrical outputs in the one or more dies. The method can comprise coupling the first side of the one or more dies to the HDL, thereby forming the KGD. The method can comprise coupling the KGD onto a carrier wafer.

[0007] Provided herein is a method for wafer-level packaging. The method can comprise placing a wafer mold over the known good die (KGD) described herein. The method can comprise removing the carrier wafer from the KGD, thereby creating a second wafer. The method can comprise coating the second wafer with a first polymer coat. The method can comprise curing the first polymer coat. The method can comprise depositing a redistribution layer (RDL) onto the second wafer. The method can comprise coating the second wafer with a second polymer coat. The method can comprise curing the second polymer coat. The method can comprise depositing an under-bump metal (UBM) layer onto the second wafer. The method can comprise flux printing solder balls onto the second wafer. The method can comprise probing the second wafer. The method can comprise cutting the second wafer into individually sized second wafer pieces for wafer-level packaging.

[0008] Provided herein is a wafer package created through wafer-level packaging. The wafer package can comprise a known good die (KGD) disposed within a wafer mold. The KGD comprise a die comprising a plurality of electrical outlets on a first side of the die. The KGD can comprise a heat dissipating layer (HDL) comprising a plurality of vias and coupled to the die. In some cases, a separation distance between at least some of the plurality of vias issubstantially the same as a separation distance between at least some of the plurality of electrical outputs on the die, such that the plurality of electrical outlets line up with the plurality of vias. The wafer package can comprise one or more thermal pads coupled to the HDL. The wafer package can comprise one or more thermal pads coupled to an external side of the wafer package. In some cases, the thermal pads on the HDL are electrically coupled to the one or more thermal pads on the external side of the wafer package via a plurality of vias in the wafer package.

[0009] Additional aspects and advantages of the present disclosure will become readily apparent from the following detailed description, wherein only illustrative embodiments of the present disclosure are shown and described. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.INCORPORATION BY REFERENCE

[0010] All publications, patents, and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference. To the extent publications and patents or patent applications incorporated by reference contradict the present disclosure contained in the specification, the specification is intended to supersede and / or take precedence over any such contradictory material.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The novel features of the present disclosure are set forth with particularity in the appended claims. A better understanding of the features and advantages of the present disclosure will be obtained by reference to the following detailed description that sets forth illustrative embodiments, in which the principles of the present disclosure are utilized, and the accompanying drawings of which:

[0012] FIGs. 1A-1C provide non-limiting examples of a cooling system for a semiconductor device in accordance with some embodiments disclosed herein. FIG. 1A provides a perspective view of a non-limiting example of a cooling system for a semiconductor device comprising a diamond wafer coupled to a cold plate in accordance with some embodiments disclosed herein. FIG. IB provides a non-limiting example of a cooling system for asemiconductor device comprising a diamond wafer not coupled to a cold plat in accordance with some embodiments disclosed herein. FIG. 1C provides a non-limiting example of a cooling system for a semiconductor device comprising a fluid-cooling element in accordance with some embodiments disclosed herein.

[0013] FIG. 2 provides a side view of a non-limiting example of a cooling system for a semiconductor device in accordance with some embodiments.

[0014] FIG. 3 provides a side view of a non-limiting example of a cooling system for a semiconductor device, in accordance with some embodiments.

[0015] FIG. 4 provides a side view of a non-limiting example of a cooling system for a semiconductor device, in accordance with some embodiments.

[0016] FIG. 5 provides a side view of a non-limiting example of a cooling system for a semiconductor device, in accordance with some embodiments.

[0017] FIG. 6A-6B provides a non-limiting example of Wafer-Level -Packaging (WLP), in accordance with some embodiments. FIG. 6A provides a side view of a non-limiting example of operations in WLP. FIG. 6B provides a side view of a non-limiting example of operations in WLP.

[0018] FIG. 7A-7B provides a non-limiting example of incorporating Heat Distribution Layers (HDL) into WLP, in accordance with some embodiments. FIG. 7A provides a side view of a non-limiting example of operations in WLP comprising HDL. FIG. 7B provides a side view of a non-limiting example of operations in WLP comprising HDL.DETAILED DESCRIPTION

[0019] Many current technologies rely on semiconductor devices and other compact circuitry which is capable of generating large amounts of heat during operation. Such semiconductor devices, particularly high-performance processors and integrated circuits may require advanced cooling capabilities to mitigate this heat generation to ensure optimal performance, reliability, and longevity. In recent years, the semiconductor industry has seen an emphasis on improving performance of semiconductor devices by increasing the transistor density while decreasing physical footprint. This, combined with an additional focus on faster signal processing, results in a higher number of operations performed, and a higher heat generation.

[0020] Systems which require active cooling for operation would also benefit from the heat transfer properties of strategically placed heat conducting surfaces or materials. Examples of systems that require active cooling are infrared sensor systems, which use active cooling devices for operation of infrared detector arrays, battery systems in electronicdevices / vehicles, and medical or laboratory equipment that require precise temperature control and stability for optimal performance, such as MRI scanners.

[0021] Some current approaches for cooling solutions may utilize materials such as aluminum or copper, which, while effective, create cooling plates that have limitations in thermal conductivity. In many cases, approaches for enhancing the thermal performance of these cooling plates has been directed to modifying the cooling plate or expanding the cooling plate into a heat extraction element that incorporates vapor chambers which can greatly increase the thermal conductivity and thermal performance of the cooling plates. Despite these enhancements, cooling for multi-terminal units and other such systems may still present many drawbacks and limitations. Such limitations may include thermal throttling from cooling elements which may not remove heat quickly enough from critical components. As a non-limiting example, throttling may be induced for cooling elements connected to high-power semiconductor devices, which can dissipate upwards of 1000 W in some cases.

[0022] Recognized herein is a need for systems and methods for advanced cooling elements which can more efficiently remove heat from dense electrical circuitry and high-power devices.

[0023] Proper cooling techniques may not only mitigate this higher heat generation but may also lead to increased performance by preventing thermal runaway and ensuring reliable operation of the device. Additionally, cooling can increase the lifespan of semiconductor devices by mitigating degradation of the device caused by higher temperatures.

[0024] In addition to the increased heat generation due to advances in semiconductor devices, many modern devices such as computers, smartphones, tablets, medical equipment, vehicle systems, gaming consoles, and numerous other digital devices may function at least in part using dense electrical circuits in multi-terminal devices. In many cases, the dense packaging of circuitry in these multi-terminal devices can be employed to deliver high performance from a small form factor. Achieving such high-performance from a small form factor can be a driving force in electronics innovation, mirroring the emphasis on transistor density in the semiconductor industry.

[0025] In many cases, the very dense electrical circuits in these multi-terminal devices can be prone to heat buildup, which limits performance and can lead to degradation of the circuits and multi-terminal devices comprising the dies. As innovation continues to drive the desire for higher performance from smaller form factors in multi-terminal devices, removing heat from such devices can be important.

[0026] In many cases, traditional cooling techniques may not be able to keep up with the heat generation of rapidly advancing semiconductor devices and multi-terminal devices, necessitating more efficient methods. Accordingly, recognized herein is the need for systems and methods for cooling elements for semiconductor and multi-terminal devices.Terms

[0027] The term “semiconductor device” as used herein, may generally refer to a large class of electronic components comprising one or more materials with conductivity falling between that of a conductor and an insulator, allowing the device to control the flow of electrical current. In some cases, semiconductor devices herein may comprise one or more transistors or diodes as described herein. Some non-limiting examples of semiconductor devices can include diodes, transistors, tunnel diodes, solar cells, Light Emitting Diodes (LEDs), capacitors, microprocessors, Central Processing Units (CPUs), general processing units (GPUs), Solid State Drives (SSDs), and any other such devices.

[0028] The term “multi-terminal device” as used herein generally refers to any electrical component or circuit element comprising two or more connection points (terminals) for interacting with other components or circuits. In some cases, multi-terminal devices herein comprise semiconductor devices as described herein. Some non-limiting examples of multiterminal devices can include, transistors, operational amplifiers (Op-Amps), integrated circuits, multi-emitter transistors, microprocessors, Central Processing Units (CPUs), general processing units (GPUs), Solid State Drives (SSDs), and any other such device.

[0029] The term “substrate,” as used herein generally refers to any substance upon which a structure (e.g., layered structure) may be deposited. The substrate may comprise a foundation for the fabrication of electronic devices, such as transistors, diodes, and integrated circuits. The substrate may comprise a solid material such as a semiconductor or an insulator.Substrate materials may comprise one or more of, for example, carbon, aluminum, gallium, silicon, germanium, arsenic, thallium, cadmium, tellurium, selenium, or alloy or allotrope thereof, or an oxide or nitride thereof. The substrate may be a carbon-containing substrate or a semiconductor-containing substrate. The substrate may include one or more chemical dopants, for example, nitrogen, phosphorous, boron or indium. Substrate materials may comprise one or more of, for example, diamond, synthetic diamond, silicon (Si), silicon dioxide (SiO2), silicon carbide (SiC), aluminum oxide (A12O3), sapphire, aluminum nitride (AIN), scandium aluminum nitride (ScAlN), germanium, gallium arsenide, gallium nitride (GaN), or indium phosphide (InP), indium nitride (InN), aluminum gallium nitride (AlGaN),indium gallium nitride (InGaN), indium aluminum nitride (InAlN), zinc oxide (ZnO), Cadmium Telluride (CdTe), for example. The substrate may include carbon-containing materials such as diamond, synthetic diamond, diamond-like carbon (DLC), diamond nanoparticles (e.g., nanodiamond), graphite, graphene, etc.

[0030] The substrate may include a material having a thermal conductivity (W / mK). Thermal conductivity, or the measurement of the ability of a material to conduct heat, may be measured and quantified as an average value. For example, a substrate may include a material having a thermal conductivity equal to or greater than about 1,000 W / mK (e.g., in at least a single dimension). The average thermal conductivity of such substrate may be greater than at least about 500 W / mK, 1,000 W / mK, 1,500 W / mK, 2,000 W / mK, 2,500 W / mK, 3,000 W / mK or greater. The average thermal conductivity may be within a range from about 500 W / mK to about 2,000 W / mK. The average thermal conductivity may be within a range from about 500 W / mK to about 3,000 W / mK. The average thermal conductivity may be within a range from about 1,500 W / mK to about 2,500 W / mK. Such materials may be “high-thermal conductivity” materials. The substrate may include a wide-bandgap semiconductor. The substrate may include a narrow-bandgap semiconductor. The substrate material may be single crystalline, poly crystalline, amorphous or a combination thereof. The substrate may comprise a buffer layer. The substrate may comprise a barrier layer. The substrate may comprise a buffer layer disposed adjacent to the barrier layer. An intermediate layer may be disposed between the buffer layer and the barrier layer. The buffer layer may comprise a wide-bandgap semiconductor. The buffer layer may comprise a Group III element and a Group V element or a Group II element and a Group VI element. The barrier layer may comprise a wide-bandgap semiconductor. The barrier layer may comprise a Group III element and a Group V element. The barrier layer may comprise a source region and a drain region. The buffer layer and the barrier layer may include a channel between the source region and the drain region.

[0031] The term “single crystal,” as used herein, generally refer to a material having one crystal or having a translational symmetry. The term “polycrystalline” generally refers to a material having more than one crystal domain or orientation. A polycrystalline material may exhibit more than one crystal structure under low energy electron diffraction (LEED) microscopy. The term “amorphous” generally refers to a material having no real or apparent crystalline form. An amorphous material may not exhibit any long-range crystal structure under LEED.

[0032] Active layers of a semiconductor device may be epitaxially grown on a substrate. In some cases, the substrate may be of the same family of materials as the active layers of the electronic device. Electronic materials for device fabrication may be realized by attaching the active layers to substrates comprising materials having crystalline structures and material combinations different from the active layer. Examples of ways to attach semiconductors to substrates having different crystal structures can include direct-bonding or direct growth using transition layer(s) to bridge different lattice structures. Alternatives to bonding and dieattachment may include the use of selective area deposition (SAD).

[0033] The substrate may have various functions, for example, (i) mechanical support; (ii) electrical conductivity that can be used to connect the active layers to the bottom of the chip; (iii) electrical isolation with low dielectric losses that can be used in high-frequency devices and surface waveguides where electric fields penetrate into the substrate; and (iv) high thermal conductivity with or without associated electrical conductivity.

[0034] The term “layered structure,” as used herein, generally refers to structures created from layers of materials of varying properties. A layered structure may comprise layers of the same or varying semiconductor properties. Individual layers may be single crystalline or polycrystalline. Individual layers may be amorphous. Electronic and optoelectronic devices manufactured out of layers of different semiconductor properties may be made by different growth techniques. In some cases, these growth techniques may allow for controlled growth of individual layers. In some case, the layers may be referred to as “epitaxial layers” or “epilayers.” Each layer may be of a thickness varying from sub-nanometer to tens of microns. Each layer may be of a thickness between about 1 nanometer (nm) and about 50 nm, between about 10 nm and about 100 nm, etc. Each layer may be greater than about 1 nm, about 2 nm, about 5nm, greater than about 10 nm, about 20 nm, greater than about 50 nm, greater than about 100 nm, greater than about 1 micron or greater. Each layer may be less than about 1 micron, less than about 100 nm, less than about 50 nm, less than about 20 nm, less than about 10 nm, less than about 5 nm, less than about 2 nm, less than about 1 nm, or less. Each layer may be atomically thin. Non-limiting examples of manufacturing techniques include molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition, organo-metallic vapor-phase epitaxy, and liquid phase epitaxy.

[0035] A substrate may comprise a thickness of at least about 1 micron, at least about 10 microns, at least about 50 microns, at least about 100 microns, at least 1 about millimeter or greater. A substrate may comprise a thickness of at least 1 millimeter of diamond. A substratemay comprise a thickness of diamond within a range from about 1 micron to about 1 millimeter, within a range from about 10 microns to about 1 millimeter, within a range from about 50 microns to about 1 millimeter or within a range from about 100 microns to about 500 microns. A substrate may comprise a thickness of about 100 microns, about 105 microns, about 110 microns, about 125 microns, about 150 microns, or greater.

[0036] Epitaxial layers may comprise one or more of, for example, boron, aluminum, gallium, indium, thallium, carbon, silicon, germanium, tin, lead, nitrogen, phosphorous, arsenic, antimony, bismuth, oxygen, sulfur, selenium, tellurium, beryllium, magnesium, calcium, zinc, mercury, cadmium, scandium, and alloys and allotropes thereof or an oxide or nitride thereof. Epitaxial layers may comprise a semiconductor comprising a bond between at least one Group III element and at least one Group V element. Epitaxial layers may comprise a semiconductor comprising a bond between at least one Group II element and at least one Group VI element. Epitaxial layers may comprise semiconductors comprising a bond between nitrogen and at least one Group III element (e.g., boron, aluminum, gallium, indium, thallium, scandium), semiconductors comprising a bond between carbon and at least one group IV element (e.g., carbon, silicon, germanium, tin, lead), and semiconductors comprising a bond between oxygen and at least one group II element (e.g., beryllium, magnesium, calcium, zinc, cadmium). Epitaxial layers may comprise one or more wide- bandgap semiconductors. Epitaxial layers may comprise one or more of, for example, GaN, AIN, InN, AlGaN, InGaN, InAlN, ZnO, SiC, InSb, HgCdTe, InGaAsP, or diamond. Any of the above materials may be single-crystalline, polycrystalline, or amorphous.

[0037] A substrate may comprise a comprise a two-dimensional electron gas layer (2DEG layer), which may be embedded within a layered structure. A 2DEG layer may be embedded within a buffer layer. A 2DEG layer may be proximate to an interface between a barrier layer and a buffer layer. A 2DEG layer may have a width of less than about 50 nm, less than about 10 nm, or less than about 5 nm. A 2DEG layer, for example, may be no further than about 150 nm, no further than about 250 nm, no further than about 500 nm, no further than about 750 nm, no further than about 1 micron, or no further than about 100 microns, from an interface between a layered structure and a carbon-containing substrate (e.g., diamond substrate).

[0038] The term "chip," as used herein generally refers to an active electronic or optoelectronic device, which may be disposed on a substrate. A chip may comprise one or more active layers disposed a substrate. The chip may comprise a layered structure. The chip may comprise one or more transistors (e.g., field-effect transistor, bipolar transistor) or diodes(e.g., infrared sensor array, metal-insulator-semiconductor diode). A transistor may be a high- electron-mobility transistor. The chip may comprise an integrated circuit, such as a monolithic microwave integrated circuit (MMIC). The chip may perform functions such as mixing, power amplification, low noise amplification, and switching. A diode may be an infrared sensor or metal insulator semiconductor diode used for temperature sensing. Diodes may be contained in a formation of diodes called a sensor array.

[0039] The term "transistor" or “diode,” as used herein, generally refers to an electrical device which can act as a switch or in the case of transistor, can act as a switch and / or an amplifier. A diode or transistor may be a part of a digital circuit. A digital circuit may comprise a plurality of diodes or transistors. A diode or transistor may comprise one or more contacts, a layered structure, and a substrate. A diode or transistor may be a part of a computing device. A transistor may be a portion of a logic circuit or a logic gate. A diode or transistor may be a semiconductor device. The term "field-effect transistor" (FET) as used herein, generally refers to a transistor which uses an electric field to control the operation of a device having the transistor. An electric field may be used to control the flow of current between two contacts or terminals in the device such as a source contact and a drain contact.

[0040] The term "high-electron-mobility transistor" (HEMT), as used herein, generally refers to a field-effect transistor comprising a heterojunction. A high-electron-mobility transistor may be alternatively referred to as a heterostructure field effect transistor. The term “heterojunction,” as used herein, may refer to the interface between any two solid-state materials of differing material properties. In some examples, these may include any two semiconductors, any two crystalline forms (e.g., amorphous, poly crystalline) of the same semiconductor, any two semiconductors comprising the same element but with varying amounts of those elements, any two semiconductors with varying dopant level, etc. The two materials may have unequal band gaps. The two materials may have a band offset. The two materials forming the heterojunction may be referred to as a "heterostructure." In some examples, an interface between a buffer layer and a barrier layer may form a heterojunction.

[0041] The term “heat extraction element,” “cold plate,” or “cooling plate” as used herein, generally refers to a system of one or more specialized heat exchangers configured to remove heat from electronic components through heat transfer to a cooling medium. In some cases, the heat extraction element comprises one or more cold plates, further comprising a number of internal channels through which a cooling medium may flow, carrying heat away from the cold plate. In some cases, the cold plate may comprise copper, aluminum, gold, silver, steel, graphite, tungsten, copper-tungsten alloy, other metal alloys, or any suitable material with ahigh thermal conductivity to facilitate efficient heat transfer. In some cases, the cooling medium may comprise one or more of air, water, coolant, glycol, water-glycol mixture, dielectric fluid, fluorocarbons, polyalphaolefins (PAO), or any other suitable cooling medium. In some cases, the cold plate may comprise cooling fins or a manifold structure to further facilitate the removal of heat from the system.

[0042] The term “Schottky contact,” as used herein, generally refers to a metalsemiconductor interface with a non-zero contact resistance, measured relative to the resistance of the semiconductor. The contact may comprise an energetic barrier between states of the semiconductor and states of the metal which barrier may be non-zero. The contact may be a rectifying contact, e.g., a Schottky barrier. In some examples, devices may include one or more dielectric or insulating material layers, for example, under a gate contact. Such devices may comprise Metal-Insulator-Semiconductor Field Effect Transistors (“MISFETs”).

[0043] The term “interface,” as used herein, generally refers to a surface forming a common boundary between two different materials, for example, materials having differing crystalline structures, differing material combinations, differing material properties. The term “interface” can refer to a location where two different materials come into contact with one another. The term “interface” can also refer to the atoms of a first material combining with the atoms of a second material at a location or at a boundary, for example, without the presence of atoms of a third material. An interface may be a surface forming a common boundary between semiconductor and diamond. An interface can be a location where diamond atoms contact atoms of a wide-bandgap semiconductor. A compound substrate of the present disclosure may include a single interface. In some examples, such compound substrate may not include more than one interface.

[0044] The term “etching,” as used herein, generally refers to a process of removing (e.g., via chemical or gas etchant) one or more layers from a wafer or substrate. A portion of the substrate may be protected from etching by the use of an “etch mask,” which may comprise material that resists etching. Etch mask materials may include, for example, silicon nitride, silicon dioxide, aluminum, titanium, nickel, or gold. Etching may include wet etching (e.g., using chemical etchants). Etching may include dry etching (e.g., using plasma or gas etchants), also known as plasma etching. Plasma etching may, for example, include microwave plasma etching, hydrogen plasma etching, reactive-ion etching (RIE), ion-assisted chemical vapor etching, inductively coupled plasma (ICP), transformer-coupled plasma (TCP) or capacitively coupled plasma (CCP). A plasma etcher, or etching tool, may be usedto plasma etch a substrate. An etching tool may produce a plasma source (e.g., etching species) from a gas (e.g., 02, fluorine-bearing gas) and an electric field (e.g., RF, microwave, DC).

[0045] An etching species may comprise positively charged or negatively charged ions. Etching quality may be influenced in part by parameters including selectivity, uniformity, directionality, plasma density and etching rate. Plasma density may be determined by plasma process parameters such as plasma etch power, process pressure and gas flow rate.

[0046] The term “intermediate layer,” as used herein, generally refers to a material layer disposed between two material layers, for example, between two layers of materials having similar or varying properties. Intermediate layers may comprise single crystalline, polycrystalline, or amorphous materials. Intermediate layers may comprise wide-bandgap semiconductors, as described herein.

[0047] Intermediate layers may comprise carbon-containing materials as described herein. Intermediate layers may comprise liquid metal thermal interfaces as described herein. Intermediate layers may comprise liquid metals as described herein. Individual layers surrounding an intermediate layer may comprise materials having different lattice-constants or different lattice structures. Individual layers surrounding an intermediate layer may comprise materials having different thermal conductivities and / or different sheet resistivities. An intermediate layer may comprise an interface or interface layer between two material layers. An intermediate layer may have a thickness from about sub-nanometer to tens of microns. An intermediate layer may have a thickness from about 20 nm to about 2,000 nm. An intermediate layer may have a thickness between about 1 nm and about 50 nm, between about 10 nm and about 100 nm, etc. An intermediate layer may have a thickness greater than about 1 nm, about 2 nm, about 5nm, greater than about 10 nm, about 20 nm, greater than about 50 nm, greater than about 100 nm, greater than about 1 micron or greater. An intermediate layer may have a thickness less than about 1 micron, less than about 100 nm, less than about 50 nm, less than about 20 nm, less than about 10 nm, less than about 5 nm, less than about 2 nm, less than about 1 nm, or less. An intermediate layer may have a thickness from about 1 nm to about 150 nm, about 150 nm or greater than 150 nm. An intermediate layer may be thinned by a method such as mechanical polishing or etching.

[0048] An intermediate layer may comprise an anchoring layer. An intermediate layer may comprise an immobilizing layer. An intermediate layer may comprise a tacking layer. An anchoring layer may assist in anchoring diamond seeds to a material layer, for example,anchoring a layer of diamond seeds to a semiconductor or dielectric-containing material layer.

[0049] An immobilizing layer may assist in immobilizing a layer of diamond seeds over a surface of a semiconductor-containing material layer. A tacking layer may assist in tacking a layer of diamond seeds to a surface of a semiconductor or dielectric-containing material layer. In some examples, the diamond seeds may be immobilized, anchored, or tacked to a semiconductor surface, in part, through Van der Waals bonding between the diamond seeds and the semiconductor surface. In some examples, the diamond seeds may be immobilized, anchored, or tacked to a dielectric or semiconductor surface, in part, through adhesion of the intermediate layer to the dielectric or semiconductor surface.

[0050] An intermediate layer may comprise a transition layer between two material layers or two substrates. In some examples, a transition layer may bridge a first lattice structure (e.g., first lattice constant) of a first material layer to a second lattice structure (e.g., second lattice constant) of a second material layer, for example, within a layered semiconductor structure. One or more transition layers may be used to accommodate for a change in the lattice constants and help absorb dislocations between two material layers or substrates.

[0051] An intermediate layer may comprise a nucleation layer. The term “nucleation layer” or “nucleating layer,” as used herein, generally refers to a material layer that assists in starting the growth or formation of another layer of material or stoichiometry. Nucleating layer materials can include semiconductors, for example, wide-bandgap semiconductors. Nucleating materials can include silicon, silicon nitride (SiN), silicon carbide (SiC) or other materials that may aid in the nucleation of synthetic diamond. Nucleating materials can include, for example, InGaN, InAlN, AIN, ScAlN or derivatives thereof. Nucleating layer materials can assist in preventing etching or damage to an underlying semiconductor material or substrate. Nucleating materials can be amorphous or polycrystalline. The presence of a nucleating layer may create multiple interfaces between a layered semiconductor structure and a substrate. Multiple interfaces can include, for example, (i) a first interface between a diamond substrate and a nucleating layer and (ii) a second interface between the nucleating layer and a layered semiconductor structure.

[0052] Nucleating layer(s) may be disposed between two material layers or substrates, such as two material layers having similar or varying properties. A nucleating layer may have similar properties to a material to which the nucleating layer assists in the growth of. Nucleating layers may be used in nucleating diamond on semiconductor-containing structures. Nucleating layers may be protective layers that protect such structures fromdamage. Such structures may include one or more nucleating layers disposed between a semiconductor-containing material and diamond. A nucleating layer may be an individual layer that is independent from a semiconductor-containing structure and may be disposed on a surface of such structure. In some cases, a nucleating layer may be nucleation material that is added to a final stage of growth of such structure (e.g., final stage of epitaxial growth), in which case the nucleation material may not be an independent layer but may be integrated into the structure near a surface (e.g., top surface). A diamond growth process can include a nucleation phase in which a nucleating layer and a set of diamond-growth conditions can enhance diamond nucleation on a host substrate. Diamond-growth conditions can include conditions within a vacuum chamber, for example, in the case of vapor deposition (e.g., CVD).

[0053] The term “liquid metal” as used herein, may generally refer to a metallic substance or alloy which remains in a liquid state at or near room temperature. In some cases, liquid metal, herein, may retain properties of both metals and liquid, exhibiting high electrical and thermal conductivity along with fluidity. In some cases, liquid metal, herein, may comprise one or more of gallium, indium, tin, zinc, bismuth, lead, mercury, or any combination therein.

[0054] The term “substrate feature” or “feature,” as used herein, may generally refer to a vertical interconnection access (“via”), channel, singulation trench, die street or street in a substrate, for example. A “via” or “through-substrate via” (or variations thereof) as used herein, may generally refer to an electrical connection disposed between layers in a substrate, such as a layered semiconductor-containing structure or a wafer. A via may couple a first layer of the substrate to a second layer of the substrate, a first device or circuit to second device or circuit, or to an antenna, or other component, for example. A via may couple a top or front side of a substrate to a bottom or back side of the substrate. A via may couple a via pad on a first side of the substrate to a metal layer on a second side of the substrate, for example, to provide electrical ground to a device disposed on or within the substrate or a layered structure.

[0055] A feature may comprise a hollow region within a substrate. A hollow region in a substrate, for example, may be generated at least in part by etching a portion of a semiconductor structure, for example, a layered structure. A hollow region may be generated at least in part by etching a portion of a structure that comprises substrate material. Etching substrate material may result in removal of the material. The hollow region may continue through more than one layer of the substrate, including more than one material.

[0056] A feature may also comprise a hollow region in a substrate, including one or more substrate layers, which may be plated with an electrically conductive material, such as a metal. Such feature may communicatively couple two or more layers of the substrate. A plating within a feature may have a thickness of less than or equal to about 4 microns, at least about 1 micron, at least about 4 microns, at least about 5 microns, at least about 6 microns, at least about 12 microns, at least about 15 microns, or greater. A plating within a feature may have a thickness within a range from about 1 micron to about 4 microns, from about 4 microns to about 6 microns, from about 6 microns to about 12 microns, from about 12 microns to about 15 microns, or greater.

[0057] A feature may comprise a portion of a semiconductor structure. A semiconductor structure may, for example, be a layered structure or a wafer. A feature may comprise, for example, a singulation feature (e.g., singulation trench or a die street). A feature may comprise an edge of a semiconductor structure, such as an edge of a die after dicing of a wafer. At least a portion of a feature may be cut away from the wafer during a dicing process. In some examples, after a feature is cut away, an edge of a die may be left with at least a portion of the feature. For example, an edge of a die may be left with at least a portion the feature comprising a material. A feature may comprise a semiconductor material. A feature may comprise silicon. A feature may comprise a material having an average value of thermal conductivity equal to or greater than about 1,000 W / mK. A feature may comprise a material having a plurality of crystals (e.g., crystal grains). Each of the plurality of crystal grains may have an average crystal grain diameter from about 10 nm to about 2,000 nm. In some examples, at least a portion of the plurality of crystal grains is disposed a distance of less than or equal to about 100 microns from a surface of a feature. At least a portion of the plurality of crystal grains may be disposed a distance of less than or equal to about 60 microns, less than or equal to about 25 microns, less than or equal to about 10 microns, less than or equal to about 5 microns, less than or equal to about 1,000 nm, less than or equal to about 100 nm, less than or equal to about 50 nm, less than or equal to about 25 nm or less, from a surface of a feature. A feature surface may, for example, be a surface or edge of the die after dicing a wafer. A feature surface may be a surface of a die street (e.g., before dicing of a wafer). A feature surface may be a surface of a via hole or hollow region. A feature surface may be a surface of a semiconductor material.

[0058] A feature may comprise an average feature size. An average feature size may be characterized by parameters including an average height, and average width or average diameter, an average aspect ratio and an average etch angle. A feature may be round orrectangular shaped. A feature height may be defined by a substrate thickness or layer thickness of a layer in the substrate. A feature may have a width or diameter of at least about 1 micron, at least about 10 microns, at least about 20 microns, at least about 30 microns, at least about 40 microns, at least about 50 microns, at least about 60 microns or greater. A feature may have a width or diameter of less than or equal to about 20 microns. A feature may have a width or diameter of less than or equal to about 40 microns. A feature may have a width or diameter within a range from about 1 micron to about 100 microns, within a range from about 10 microns to about 100 microns, within a range from about 20 microns to about 100 microns, within a range from about 30 microns to about 100 microns or within a range from about 40 microns to about 100 microns, within a range from about 60 microns to about 100 microns or greater. A feature may have a width or diameter within a range from about 10 microns to about 40 microns, within a range from about 10 microns to about 60 microns or greater. A feature may have a height varying from sub-nanometer to hundreds of microns. A feature may have a height less than or equal to about 600 microns. A feature may have a height less than or equal to about 150 microns. A feature may have a height of at least about 1 micron, at least about 25 microns, at least about 50 microns, at least about 100 microns or greater.

[0059] A feature may be characterized by an “aspect ratio” or “average aspect ratio.” In some examples, an aspect ratio (e.g., an average aspect ratio) may generally refer to a ratio between a height of a feature and a width or diameter of the feature (e.g., height-to-width aspect ratio). For example, a feature having a height of about 100 microns and a diameter or width of about 20 microns may have an aspect ratio of about 5: 1, 5 / 1 or 5. As another example, a feature having a height of about 50 microns and a width of about 40 microns may have an aspect ratio of about 1.25: 1 or 1.25. A feature may have an aspect ratio of at least about 0.25: 1. A feature may have an aspect ratio of at least about 1 : 1, at least about 1.25: 1, at least about 2: 1, at least about 3: 1, at least about 4: 1, at least about 5: 1, at least about 7: 1, at least about 10: 1 or greater.

[0060] In some examples, an aspect ratio may generally refer to a ratio between a first width or diameter of a feature and a second width or diameter of the feature (e.g., width-to- width aspect ratio). For example, an aspect ratio may refer to a ratio between a width or diameter of a feature on a first surface of a substrate and a width or diameter of the feature on a second surface of the substrate. In some examples, a feature may comprise a first width or diameter on a backside surface of a substrate and a second width or diameter on a frontside surface of the substrate. The backside surface, the frontside surface, or both, may comprise a materialhaving an average thermal conductivity equal to or greater than about 1,000 W / mK. The backside surface, the frontside surface, or both, may comprise diamond. The frontside surface may comprise an interface between diamond and another material different from diamond. The frontside surface may comprise another material different from diamond, for example, a semiconductor containing material.

[0061] A substrate may comprise one or more features that may be disposed proximate to a device or component of the substrate, such as a transistor. In some examples, such components may be disposed on a surface of the substrate. Components may also be disposed within a substrate, such as within epitaxial layers of a substrate. In some examples, a distance between a feature and a component may be defined by a distance between a surface or edge of the component and a surface of the feature (e.g., inner surface). A distance between a feature and a component may be, for example, less than or equal to about 200 micrometers (or microns, pm), less than or equal to about 100 microns, less than or equal to about 75 microns, less than or equal to about 60 microns, less than or equal to about 50 microns, less than or equal to about 30 microns, less than or equal to about 20 microns, less than or equal to about 15 microns, or less. A distance between a feature and a component may be within a range from about 30 microns to about 20 microns, from about 20 microns to about 10 microns, from about 10 microns to about 5 microns, or less.Cooling Elements

[0062] In some cases, the present disclosure provides a cooling element for semiconductor devices. In some cases, the cooling element comprises a heat sink made entirely, or in part, from diamond. This heat sink can alternatively be designed with fins or other structures to maximize surface area and enhance heat dissipation. In some cases, the cooling element can include a thermal plate constructed from diamond, which may be placed directly on the semiconductor device to facilitate efficient heat transfer.

[0063] Cooling elements can comprise layers of material which are thermally conductive but electrically insulative. Cooling elements may comprise silicon carbide (SiC). Cooling elements may comprise diamond. Cooling elements may comprise natural diamond. Cooling elements may comprise synthetic diamond. Cooling elements may comprise aluminum nitride (AIN). Cooling elements may comprise any other ceramic material which is thermally conductive but electrically insulative. Cooling elements may comprise any other polymeric material which is thermally conductive but electrically insulative. Cooling elements may comprise any other compound which is thermally conductive but electrically insulative.

[0064] Cooling elements may comprise epitaxially grown layers, sliced layers, laser exfoliated layers, or any combination thereof. Cooling elements may comprise portions which are single crystal, as described herein. Cooling elements may comprise portions which are polycrystalline, as described herein. Cooling elements may comprise portions which are amorphous, as described herein.

[0065] In some cases, a diamond chip or wafer may be used in the cooling element.

[0066] In some case, the cooling element may be wider than the semiconductor device in at least one dimension. In some cases, the cooling element may be larger (e.g., by at least 25%) in surface area than the semiconductor device. In some cases, the cooling element is at least 25% larger than a hot spot of the semiconductor device. In some cases, the cooling element can be one to several millimeters thick.

[0067] In some examples, the cooling element may be about 1% larger to about 50% larger than the semiconductor device and increments therein. In some examples, the cooling element may be about 1% larger in surface area than the semiconductor device. In some examples, the cooling element may be about 1% larger to about 10% larger than the semiconductor device and increments therein. In some examples, the cooling element may be about 10% larger in surface area than the semiconductor device. In some examples, the cooling element may be about 10% larger to about 15% larger than the semiconductor device and increments therein. In some examples, the cooling element may be about 15% larger in surface area than the semiconductor device. In some examples, the cooling element may be about 15% larger to about 20% larger than the semiconductor device and increments therein. In some examples, the cooling element may be about 20% larger in surface area than the semiconductor device. In some examples, the cooling element may be about 20% larger to about 25% larger than the semiconductor device and increments therein. In some examples, the cooling element may be about 25% larger in surface area than the semiconductor device. In some examples, the cooling element may be about 25% larger to about 30% larger than the semiconductor device and increments therein. In some examples, the cooling element may be about 30% larger in surface area than the semiconductor device. In some examples, the cooling element may be about 30% larger to about 35% larger than the semiconductor device and increments therein. In some examples, the cooling element may be about 35% larger in surface area than the semiconductor device. In some examples, the cooling element may be about 35% larger to about 50% larger than the semiconductor device and increments therein. In some examples, the cooling element may be about 50% larger than in surface area than the semiconductor device or greater.

[0068] In some examples, the cooling element may be about 1% larger to about 50% larger than a hotspot of the semiconductor device and increments therein. In some examples, the cooling element may be about 1% larger in surface area than a hotspot of the semiconductor device. In some examples, the cooling element may be about 1% larger to about 10% larger than a hotspot of the semiconductor device and increments therein. In some examples, the cooling element may be about 10% larger in surface area than a hotspot of the semiconductor device. In some examples, the cooling element may be about 10% larger to about 15% larger than a hotspot of the semiconductor device and increments therein. In some examples, the cooling element may be about 15% larger in surface area than a hotspot of the semiconductor device. In some examples, the cooling element may be about 15% larger to about 20% larger than a hotspot of the semiconductor device and increments therein. In some examples, the cooling element may be about 20% larger in surface area than a hotspot of the semiconductor device. In some examples, the cooling element may be about 20% larger to about 25% larger than a hotspot of the semiconductor device and increments therein. In some examples, the cooling element may be about 25% larger in surface area than a hotspot of the semiconductor device. In some examples, the cooling element may be about 25% larger to about 30% larger than a hotspot of the semiconductor device and increments therein. In some examples, the cooling element may be about 30% larger in surface area than a hotspot of the semiconductor device. In some examples, the cooling element may be about 30% larger to about 35% larger than a hotspot of the semiconductor device and increments therein. In some examples, the cooling element may be about 35% larger in surface area than a hotspot of the semiconductor device. In some examples, the cooling element may be about 35% larger to about 50% larger than a hotspot of the semiconductor device and increments therein. In some examples, the cooling element may be about 50% larger than in surface area than a hotspot of the semiconductor device or greater.

[0069] In some examples, the cooling element may be about 100 microns thick to about 5 mm thick and increments therein. In some examples, the cooling element may be about 100 microns thick. In some examples, the cooling element may be about 100 microns thick to about 250 microns thick and increments therein. In some examples, the cooling element may be about 250 microns thick. In some examples, the cooling element may be about 250 microns thick to about 500 microns thick and increments therein. In some examples, the cooling element may be about 500 microns thick. In some examples, the cooling element may be about 500 microns thick to about 1 mm thick and increments therein. In some examples, the cooling element may be about 1 mm thick. In some examples, the coolingelement may be about 1 mm thick to about 2.5 mm thick and increments therein, some examples, the cooling element may be about 2.5 mm thick. In some examples, the cooling element may be about 2.5 mm thick to about 5 mm thick and increments therein. In some examples, the cooling element may be about 5 mm thick or greater.

[0070] In some cases, the cooling element further comprises a heat extraction element. In some cases, the heat extraction element comprises one or more specialized heat exchangers configured to remove heat from electronic components through heat transfer to a cooling medium. In some cases, the heat extraction element comprises one or more cold plates, further comprising a number of internal channels through which a cooling medium may flow, carrying heat away from the cold plate. In some cases, the cold plate may comprise copper, aluminum, gold, silver, steel, metal alloys, or any suitable material with a high thermal conductivity to facilitate efficient heat transfer. In some cases, the cooling medium may comprise one or more of air, water, coolant, glycol, water-glycol mixture, dielectric fluid, fluorocarbons, polyalphaolefins (PAO), or any other suitable cooling medium. The cold plate may comprise microchannels to facilitate fluid cooling. The cold plate may comprise a vapor chamber. In some cases, the cold plate may comprise cooling fins or a manifold structure to further facilitate the removal of heat from the system.Intermediate Layers

[0071] In some cases, the semiconductor device is a layered structure as described herein. In some cases, the semiconductor device is a layered structure comprising silicon. In one nonlimiting example, the cooling element may be included on a silicon layer of a layered structure as described herein. In such an example, consideration of the expansion coefficients of the different materials may be important to mitigate buildup of stress in the system.

[0072] Diamond can have an extremely different expansion coefficient, about 1E-6 / K, compared to that of silicon, about 2.6E-6 / K. Mechanically combining a diamond layer and a silicon layer, such as in the creation of a cooling element described herein, may induce stress in the system under heating, as the components will expand at different rates. This buildup of stress can significantly impact performance and longevity of the system. As an example, a semiconductor during operation may experience large temperature fluctuations of up to 60°C or more in some cases. These fluctuations can cause a large buildup of stress between mechanically coupled layers comprising different expansion coefficients, such as diamond and silicon. To mitigate this buildup of stress, an intermediate layer as described herein may be included as an alternative to rigid mechanical coupling between layers.

[0073] In some cases, the intermediate layer comprises a liquid metal thermal interface as described herein. In some cases, the liquid metal thermal interface comprises one or more liquid metals as described herein. In some cases, the liquid metal thermal interface comprises a low shear modulus. In some cases, the liquid metal thermal interface comprises a moderate viscosity. In some cases, the liquid metal thermal interface comprises a high viscosity. In some cases, the liquid metal thermal interface comprises a moderate-to-high viscosity. In some cases, the liquid metal thermal interface comprises a liquid metal which does not corrode surrounding interfaces. In some cases, the liquid metal thermal interface comprises a liquid metal which flows easily enough to wet the interface between two layers, while not flowing out of the interface onto surrounding areas.

[0074] In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.01 GPa to about 10 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.01 GPa. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.01 GPa to about 0.1 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.1 GPa. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.1 GPa to about 0.25 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.25 GPa. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.25 GPa to about 0.5 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.5 GPa. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.5 GPa to about 0.75 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.75 GPa. In some cases, the liquid metal thermal interface comprises a shear modulus of about 0.75 GPa to about 1.0 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 1.0 GPa. In some cases, the liquid metal thermal interface comprises a shear modulus of about 1.0 GPa to about 1.25 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 1.25 GPa. In some cases, the liquid metal thermal interface comprises a shear modulus of about 1.25 GPa to about 1.5 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 1.5 GPa. In some cases, the liquid metal thermal interface comprises a shear modulus of about 1.5 GPa to about 1.75 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 1.75 GPa. In some cases, the liquid metal thermal interface comprises ashear modulus of about 01.75 GPa to about 2.0 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 2.0 GPa. In some cases, the liquid metal thermal interface comprises a shear modulus of about 2.0 GPa to about 10 GPa and increments therein. In some cases, the liquid metal thermal interface comprises a shear modulus of about 10 GPa.

[0075] . In some cases, the liquid metal thermal interface comprises a viscosity of about 0.01 mPa*s to about 10 mPa*s and increments therein. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.01 mPa*s. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.01 mPa*s to about 0.1 mPa*s and increments therein. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.1 mPa*s. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.1 mPa*s to about 0.25 mPa*s and increments therein. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.25 mPa*s. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.25 mPa*s to about 0.4 mPa*s and increments therein. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.4 mPa*s. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.4 mPa*s to about 0.5 mPa*s and increments therein. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.5 mPa*s. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.5 mPa*s to about 0.6 mPa*s and increments therein. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.6 mPa*s. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.6 mPa*s to about 0.75 mPa*s and increments therein. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.01 mPa*s. In some cases, the liquid metal thermal interface comprises a viscosity of about 0.75 mPa*s to about 1.0 mPa*s and increments therein. In some cases, the liquid metal thermal interface comprises a viscosity of about 1.0 mPa*s. In some cases, the liquid metal thermal interface comprises a viscosity of about 1.0 mPa*s to about 10 mPa*s and increments therein. In some cases, the liquid metal thermal interface comprises a viscosity of about 10 mPa*s.

[0076] In some cases, the low shear modulus and moderate, moderate-to-high, or high viscosity of the liquid metal thermal interface enables the interfacial coupling of two layers while mitigating the stress caused by different coefficients of thermal expansion. In one nonlimiting example, a liquid metal thermal interface may be formed between a diamond layer of a cooling element and a silicon layer of a semiconductor device, allowing for the transfer ofheat from the semiconductor device to the cooling element, while preventing mechanical stress as each layer expands at a different rate upon heating.

[0077] The term “liquid metal” as used herein, may generally refer to a metallic substance or alloy which remains in a liquid state at or near room temperature. In some cases, liquid metal, herein, may retain properties of both metals and liquid, exhibiting high electrical and thermal conductivity along with fluidity. In some cases, liquid metal, herein, may comprise one or more of gallium, indium, tin, zinc, bismuth, lead, mercury, or any combination therein.

[0078] In some cases, the intermediate layer as described herein comprises one or more low shear modulus solid materials. In some cases, the low shear modulus solid material comprises one or more of graphite, graphene, reinforced silicone, silver, silver-filled epoxy, filled epoxy, lead, indium, other soft metals, or any combination therein.

[0079] In some cases, the low shear modulus solid material comprises a shear modulus of about 0.01 GPa to about 10 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.01 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.01 GPa to about 0.1 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.1 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.1 GPa to about 0.25 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.25 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.25 GPa to about 0.5 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.5 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.5 GPa to about 0.75 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.75 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 0.75 GPa to about 1.0 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 1.0 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 1.0 GPa to about 1.25 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 1.25 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 1.25 GPa to about 1.5 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 1.5 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 1.5 GPa to about 1.75 GPa and increments therein. Insome cases, the low shear modulus solid material comprises a shear modulus of about 1.75 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 01.75 GPa to about 2.0 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 2.0 GPa. In some cases, the low shear modulus solid material comprises a shear modulus of about 2.0 GPa to about 10 GPa and increments therein. In some cases, the low shear modulus solid material comprises a shear modulus of about 10 GPa.Example Configurations of Cooling Elements

[0080] In some cases, a diamond-based cooling element is coupled to the semiconductor using an intermediate layer to maintain close thermal contact. Thereafter, the intermediate layer may also be applied between the diamond-based cooling element and a heat extraction element as described herein. In some cases, such a configuration of the diamond-based cooling element coupled to the semiconductor can reduce the temperature difference between the semiconductor and the cooling plate by at least about 50%.

[0081] In some cases, a layered structure as described herein may be formed using one or more intermediate layers to form a low shear modulus interfacial coupling. In some cases, this composite structure offers significant advantages in terms of thermal performance and environmental safety. For example, an example structure can leverage the superior thermal properties of diamond while benefiting from the structural advantages of a low-shear modulus or moderate-to-high viscosity intermediate layer. It will be appreciated that any material which can mitigate mechanical stress resulting from the differing expansion coefficients of two layers of a layered structure, such as diamond and silicon, can be used as an intermediate layer.

[0082] A non-limiting example of a cooling system for a semiconductor device 100 is provided in FIG. 1A. As illustrated, the cooling system 100 comprises a printed circuit board (PCB) 102. In one non-limiting example, the thermal conductivity of a PCB 102 can range between 0.2 to 0.5 watts per meter kelvin (W / mK). This example may suggest the material is not highly conductive to heat, which can limit heat dissipation in some cases. In some cases, a semiconductor device 104 can be coupled to the PCB 102. The thermal conductivity of a silicon semiconductor device can vary depending on factors such as the semiconductor material, doping, crystal orientation, and temperature. As a non-limiting example, at room temperature, the thermal conductivity of silicon can range from about 100 to 150 W / mK. This relatively high thermal conductivity may allow a silicon chip to efficiently dissipate heatgenerated during operation, which can be crucial for maintaining their performance and reliability. The semiconductor device 104 can be coupled to cooling element 106 using an intermediate layer as described herein. As a non-limiting example, a diamond-based cooling element 106 can have thermal conductivity between about 1,000 W / mK and about 2,600 W / mK (at room temperature), making it an ideal thermal conductor in some cases. In one non-limiting example, a diamond-based cooling element wafer 106 may have a thickness between about 1 mm and 2 mm for certain applications. In some cases, 106 is coupled to cold plate 108. In some cases, the cooling element 106 may be further coupled to a heat extraction element 108 as described herein. In some cases, the cooling element 106 may be coupled to the heat extraction element 108 using an intermediate layer as described herein. In some cases, the heat extraction element 108 may comprise one or more of copper having a thermal conductivity of about 390 W / mK, aluminum having a thermal conductivity of about 205 W / mK, graphite having a thermal conductivity of about 100 W / mK to about 700 W / mK, copper-tungsten alloy having a thermal conductivity of about 180 W / mK to about 220 W / mK, silicon carbide having a thermal conductivity of about 100 W / mK to about 500 W / mK, any other heat extraction element material listed herein, or any combination therein. In some cases, the heat extraction element 108 may comprise a material having a thermal conductivity greater than about 200 W / mK.

[0083] Another example of a cooling element for a semiconductor device 120 is provided in FIG. IB. In this non-limiting example, system lacks a heat extraction element 108. In some cases, a diamond-based cooling element 109 exchanges heat directly with a cooling medium, which may further reduce the thermal resistance between the semiconductor and the cooling element. As a non-limiting example, in some cases, the cooling medium can be water based, although other mechanisms such as fluorocarbon-based liquids, or synthetic oils, or cooled air, can also be employed. In some cases, non-corroding and phase transition fluids may also be used. In some cases, provided in FIG. 1C, a water-based heat extraction element 110 may be used in combination with a cooling medium to transfer heat away from cooling system 140. As a non-limiting example, although water itself has lower thermal conductivity compared to metals and graphite (around 0.6 W / mK), cooling can be achieved using water as a cooling medium due to the high specific heat capacity and flow rate of water.

[0084] In some cases, the cooling element may be configured to have various geometrical shapes to increase the surface area of the cooling element which comes in contact with the heat extraction element or cooling medium.

[0085] A non-limiting example of a portion of a cooling system for semiconductor devices 200 is provided in FIG. 2. In some cases, the cooling element 204 as described herein, can be of an adequate thickness and width to ensure efficient cooling of the semiconductor device.

[0086] In some cases, to ensure efficient heat dissipation, the semiconductor device 202 has a smaller surface area than that of the cooling element 204. In one example, the cooling element 204 is at least one millimeter thick and is wider (e.g., at least about 25%) than the semiconductor device 202. In another example, the cooling element 204 is larger (e.g., at least 25%) in surface area than a hot spot 203 of the semiconductor device 202.

[0087] In some cases, a hot spot 203 may comprise a localized area of a semiconductor device with a significantly higher temperature than surrounding regions. In some cases, a hot spot 203 may arise from various factors, such as, for example, a high density of integrated circuits, non-uniform current distribution, defects, or insufficient heat dissipation.

[0088] In some cases, the cooling element 204 features micro-channels to increase the surface area of the cooling element 204 and thereby facilitate heat exchange with the cooling medium. In some cases, the cooling element further comprises a vapor chamber. This vapor chamber may utilize the phase change of a working fluid to efficiently spread heat across the device. In some cases, the cooling element 204 may be fabricated using one or more advanced manufacturing techniques such as 3D printing, enabling the creation of intricate and highly efficient cooling structures that would be difficult to achieve with traditional manufacturing methods.

[0089] A further example of cooling elements for semiconductor devices is provided in FIG. 3, in accordance with some embodiments. The semiconductor device 302 can be disposed on top of a PCB 301. The cooling element 303 can be disposed onto the semiconductor device 302. In a non-limiting example, the cooling element 302 may be 250 microns to 2.5mm thick, and the area of the diamond cooling element is at least 1.15x the area of the semiconductor chip. There can be a heat extraction element 304 disposed on top of the cooling element 303. In a non-limiting example, the area of the heat extraction element 304 is at least 1.05x the area of the cooling element 303. There may be an intermediate layer between the semiconductor device 302 and the cooling element 303, and / or between the cooling element 303 and the heat extraction element 304. In some cases, this intermediate layer comprises a liquid metal thermal interface as described herein. In some cases, this intermediate layer comprises a low shear modulus material as described herein. In some cases, the intermediate layer comprises a liquid metal thermal interface and a low shear modulus material.

[0090] In one non-limiting example, the material types for the system 300 may comprise: 301 may be a standard PCB material, 302 may be a semiconductor material such as, but not limited to silicon, 303 may be diamond, and 304 may be a high thermal conductivity material such as, but not limited to, copper, aluminum, or diamond.

[0091] In the non-limiting example system 300, is important to note the overall thermal performance of the system may be improved despite increasing the thermal resistance of the system. This increase in linear thermal resistance may be, at least in part, due to the addition of the diamond into the system. The diamond, however, can successfully conduct the heat from the semiconductor over a broader area throughout the cooling element 303 and the heat extraction element 304, leading to overall superior thermal performance.

[0092] In some cases, such as in structure 400 provided in FIG. 4, a semiconductor device 402 can be disposed on top of a PCB 401. A diamond-based cooling element 403 can be disposed onto the semiconductor device. In some cases, the diamond-based cooling element may be 250 microns to 2.5mm thick, and the area of the diamond cooling element may be at least 1.15x the area of the semiconductor chip. There may be a heat extraction element 404 disposed on top of the cooling element 403. The area of the heat extraction element 404 may be at least 1.05x the area of the cooling element 403. There may be an intermediate layer between the semiconductor device 402 and the cooling element 403, and / or between the cooling element 403 and the heat extraction element 404. In some cases, this intermediate layer comprises a liquid metal thermal interface as described herein. In some cases, this intermediate layer can comprise a low shear modulus material as described herein. In some cases, the intermediate layer comprises a liquid metal thermal interface and a low shear modulus material. In one non-limiting example, 404 may be a cold plate as described herein, and may be attached to, or part of, a further heat extraction element 405. 405 may contain further heat dissipation elements such as liquids or gases, vapor chambers and / or heat pipes. 405 may comprise copper, aluminum, diamond, or other high conductivity materials. In combination with the diamond-based cooling element 403, the heat extraction unit 405 comprising the cold plate 404 may increase the capillary thermal conductivity limit, despite the thermal resistance depicted in 406. In some cases, in addition or alternatively to the cold plate, the diamond may have a vapor chamber, microchannels, or both.

[0093] In construction 500, provided in FIG. 5, the heat extraction element 505 can comprise diamond, leading to the thermal resistance 506. In some cases, the diamond can be part of the heat extraction element. In some cases, the diamond may be located in the coupled diamondbased cooling element. In some cases, the diamond-based cooling element may be part of theheat extraction element. In some cases, the diamond may be joined with the heat extraction element separately from the cooling element (e.g., by brazing) without an interfacial material.

[0094] As depicted in 400 and 500, the overall thermal performance of the system may be improved despite increasing the average linear thermal resistance of the system by introducing diamond with a thermal conductivity of about 1,000 W / m*K to about 2,600 W / m*K, as a layer in between the semiconductor chip and the heat extraction element, which may have a thermal conductivity of about 5000 W / m*K to about 10,000 W / m*K . The diamond, however, can successfully conduct the heat from the semiconductor device over a broader area throughout the diamond cooling element and the heat extraction element, leading to overall superior thermal performance.

[0095] For example, the addition of the diamond may increase the thermal resistance on the order of 10'3K / W to 10'5K / W depending on the size, thickness of the diamond plate, and the intermediary material.

[0096] Systems and methods herein can utilize a cooling element for passive cooling, which may lead to increased processing capabilities without energy expenditure on heat extraction. This is because the temperature of the hotspot 203 on a semiconductor device can restrict the operational intensity of a processor therein. By passively cooling the hotspot 203, the semiconductor device may operate at higher intensities, thereby processing more data in a shorter time. Additionally, the density with which semiconductor devices may be placed in a datacenter or High-Performance Computing (HPC) cluster may directly contribute to the datacenter or HPC cluster’s performance. Enhanced cooling for semiconductor devices as described herein, can allow for closer placement, thereby increasing datacenter or HPC cluster density, which in turn facilitates easier communication between semiconductor devices and boosts overall processing capacity.Heat Dissipating Layers

[0097] In some cases, a semiconductor device comprising integrated circuits may be formed. These semiconductor devices comprise the dense electrical circuitry of multi-terminal devices, as well as the transistors or diodes described herein of a semiconductor device. Such systems may commonly be referred to as dies. In many cases, these dies may be subject to both the emphasis on increasing transistor density in semiconductor devices, as well as miniaturization in circuitry of multi-terminal devices in order to increase efficiency. As such, removing heat from these devices may be increasingly important for at least the same reasons as above.

[0098] To remove heat from such devices, provided herein are methods and systems for incorporating Heat Dissipating Layers (HDLs) into the layered structures comprising the dies.

[0099] HDLs comprise layers of material which are thermally conductive but electrically insulative. HDLs may comprise silicon carbide (SiC). HDLs may comprise diamond. HDLs may comprise natural diamond. HDLs may comprise synthetic diamond. HDLs may comprise aluminum nitride (AIN). HDLs may comprise any other ceramic material which is thermally conductive but electrically insulative. HDLs may comprise any other polymeric material which is thermally conductive but electrically insulative. HDLs may comprise any other compound which is thermally conductive but electrically insulative.

[0100] HDLs may comprise epitaxially grown, sliced, or laser exfoliated layers, or any combination thereof. HDLs may comprise portions which are single crystal as described herein. HDLs may comprises portions which are polycrystalline as described herein. HDLs may comprise portions which are amorphous as described herein.

[0101] In some cases, HDLs may comprise one or more cooling elements as described herein.

[0102] In some cases, one or more HDLs may be incorporated into a layered structure, such as in a die, by acting as a substrate on which further layers of the layered structure may be epitaxially grown. In some cases, further layers of the layered structure comprise one or more epitaxial layers as described herein. In some cases, further layers of the layered structure comprise one or more intermediate layers as described herein. Examples of methods and systems for forming layered structures comprising HDLs, epitaxial layers, and intermediate layers are described in commonly owned United States Patent Publication No. 2024- 0170362-Al, which is incorporated by reference herein in its entirety.

[0103] In some cases, the one or more HDLs may be mechanically connected to the die. In some cases, the one or more HDLs may be thermally connected to the die. In some cases, the one or more HDLs may be mechanically connected to the die using an intermediate layer. In some cases, the one or more HDLs may be thermally connected to the die using an intermediate layer.

[0104] In some cases, the coefficient of thermal expansion of the one or more HDLs may differ from the coefficient of thermal expansion of the one or more further layers of the layered structure, producing a mismatch. In such cases, one or more intermediate layers as described herein, may be used to accommodate this mismatch in coefficients of thermal expansion. In some cases, the mismatch in coefficients of thermal expansion may be accommodated, at least in part, by the composition of the interconnect materials of the one ormore intermediate layers. In some cases, the mismatch in coefficients of thermal expansion may be accommodated, at least in part, by the height of the one or more intermediate layers. In some cases, the mismatch in coefficients of thermal expansion may be accommodated, at least in part, by sandwiching the one or more further layers of the layered structure between two HDL layers.

[0105] In some cases, one or more HDLs may be connected to one or multi-terminal devices or chips as described herein, on a first face not comprising electrical connections. In some cases, HDLs may be connected to one or more multi-terminal devices or chips as described herein, on a second face comprising electrical connections. In some cases, a first set of one or more HDLs may be connected to one or more multi-terminal devices or chips as described herein, on a first face comprising electrical connections, and a second set of one or more HDLs may be connected to one or more multi-terminal devices or chips as described herein, on a second face comprising electrical connections.

[0106] In some cases, HDLs may comprise additional features to create electrical connections, such as through-holes or vias. In some cases, these features may further comprise electrically conductive material. Examples of methods and systems for forming such additional features are described in commonly owned United States Patent Publication No. 2023-0420333-Al which is incorporated by reference herein in its entirety.

[0107] In some cases, electrical connections between HDLs and other layers, such as multiterminal devices or chips described herein, epitaxial layers described herein, or intermediate layers described herein, comprise metal bump adhesion processing. In some cases, the metal bump adhesion processing comprises Cu-Cu bumps. In some cases, the metal bump adhesion process comprises Ag-Ag bumps. In some cases, the metal bump adhesion process comprises Au-Au bumps. In some cases, the metal bump adhesion process comprises Al-Al bumps. In some cases, the metal bump adhesion process comprises metal alloy-metal alloy bumps. In some cases, the metal bump adhesion process comprises adhesion between bumps of an electrically conductive material. In some cases, electrical connections between HDLs and other layers, such as dies, multi-terminal devices or chips described herein, epitaxial layers described herein, or intermediate layers described herein, comprises any other type of adhesion process which electrically connects an electrical connection on the dies, multiterminal devices or chips, epitaxial layers, or intermediate layers to an electrical connection of the HDL. In some cases, there is a one-to-one correspondence between the electrical connections of the HDL and the electrical connections of the dies, multi-terminal devices or chips, epitaxial layers, or intermediate layers. In some cases, there is a one-to-onecorrespondence between the electrical connections of the HDL and the electrical connections of a Printed Circuit Board (PCB) on which the HDL is deployed. In some cases, there is a one-to-one correspondence between the electrical connections of the HDL and the electrical connections of a Re-Distribution Layer (RDL) on which the HDL is deployed. In some cases, there is a one-to-one correspondence between the electrical connections of the HDL and the electrical connections of a wafer of Wafer-Level Packaging (WLP) on which the HDL is deployed.

[0108] A layered structure comprising one or more HDLs and one or more dies can be referred to as a Heat Distribution Structure (HDS). In some cases, once a HDS has been formed, it may be deployed on a Printed Circuit Board (PCB) which is designed to receive the HDS. In some cases, the one or more dies of the HDS may be electrically connected to the other parts of the system architecture by the PCB.

[0109] In some cases, the one or more HDLs of a HDS may extend further in at least one dimension than the one or more dies of the HDS. In some cases, the one or more HDLs of a HDS which is layered along the Z direction may extend further in the X direction than the one or more dies of the HDS. In some cases, the one or more HDLs of a HDS which is layered along the Z direction may extend further in the Y direction than the one or more dies of the HDS. In some cases, the one or more HDLs of a HDS which is layered along the Z direction may extend further in the X and Y directions than the one or more dies of the HDS. In some cases, the extension of the one or more HDLs in the at least one dimension allows designers of circuitry and architecture where an HDS is deployed to incorporate one or more heat dispersive pads comprising the one or more HDLs of the HDS into the circuitry and architecture. In some cases, this allows for the one or more HDLs of the HDS to be connected to one or more heat sinks of the circuitry and architecture where an HDS is deployed. In some cases, this allows for the one or more HDLs of the HDS to be connected to one or more heat sinks of the PCB where an HDS is deployed. In some cases, this allows for the one or more HDLs of the HDS to be connected to one or more heat sinks of the RDL where an HDS is deployed. In some cases, this allows for the one or more HDLs of the HDS to be connected to one or more heat sinks of any sub-layer where an HDS is deployed.

[0110] An alternative to using a PCB for creating connections between the circuits of the multi-terminal device or chip and the system architecture is Wafer-Level Packaging (WLP). In some cases, one or more HDLs may be incorporated into WLP of dies to create an HDS. [OHl] Wafer-level packaging (WLP) may offer several benefits, including smaller, thinner packages for dies, improved electrical performance, and cost efficiency, making it suitablefor compact devices and high-performance applications. WLP can be achieved by packaging a multi-terminal device or chip as described herein, onto a wafer before the wafer is diced. Packaging may comprise mechanically connecting the multi-terminal device or chip to the wafer, as well as creating all necessary electrical connections between the multi-terminal device or chip and the wafer.

[0112] Non-limiting examples 600 of WLP are provided in FIGs. 6A-6B, in accordance with some embodiments. Incorporation of HDLs in WLP as described herein, may comprise Chip Scale Packaging (CSP) techniques. Incorporation of HDLs in WLP as described herein may comprise Wafer-Level Chip Scale Packaging (WLCSP). Incorporation of HDLs in WLP as described herein may comprise Fan-In WLCSP (FIWLCSP). Incorporation of HDLs in WLP as described herein may comprise Fan-Out WLCSP (FOWLCSP).

[0113] The non-limiting example of WLP may comprise the following operations 600: electrical connections of the wafer can be probed for continuity at 601, and then the backside of the wafer can be ground to reduce its thickness at 602 before sawing into individual dies at 603. In some cases, the WLP operations 600 comprise Known Good Die (KGD) pick and placement at 604, where components determined to be in operating condition may be placed onto a carrier wafer using adhesive or other means. In some cases, the method 600 further comprises encapsulating the dies on the carrier wafer with a protective mold compound at 605 to enable formation of new wafer structures. In some cases, this may be followed by removal of the carrier wafer and temporary adhesive, before cleaning the components at 606. In some cases, this may be followed by one or more photolithography processes, comprising a photoresist polymer coating, image development, and curing, whereby additional layers may be added to the layered structure.

[0114] In some cases, the non-limiting example of WLP further comprises additional operations. Method 600 can comprise sputtering one or more conductive metal layers comprising the Re-Distribution Layer (RDL) onto the layered structure, coating the metal layer with a photoresist and developing an image to pattern the RDL, stripping the undeveloped photoresist, and etching the un-protected metal layers to produce the patterned RDL at 608. In some cases, the method 600 can comprise an additional photolithography operation at 609, whereby the Under Bump Metallization (UBM) layer may be patterned onto the layered structure at 610. In some cases, the method 600 can comprise adding electrical connections to the UBM layer, applying solder balls to metallized portions of the layered structure, and melting and reforming the solder balls to form solder bumps at 611. In some cases, the continuity and performance of the electrical connections can be tested with a waferprobe, and identifying information can be engraved onto individual dies using a laser at 611. In some cases, following this, the wafer may again be sawed into dies and individually packaged at 612.

[0115] A non-limiting example of incorporating HDLs into WLP is provided in FIGs. 7A- 7B. In addition to the WLP steps of 600, the non-limiting example of incorporating HDLs into WLP, such as provided in FIG. 7, may comprise the operations 700: 1. Locate at 706 a HDL 704 to a first die surface, wherein the HDL can be a material that is thermally conductive and electrically insulative such as, but not limited to SiC, AIN, Diamond, or any other ceramic, polymeric, or other material that have sufficient thermal conductivity and electric insulation; 2. Place vias or through-holes in the HDL material at 705 that will be filled or partially filled with a conductive material. Conductive materials may be comprised of metals, such as Cu or Au or Ag, or other electrically conductive materials; 3. The HDL may mate directly to the electrical outputs on the first side of the die through a joining method, such as via Cu-Cu bump adhesion process. The mismatch in thermal coefficient of expansion (TCE) between the die and the HDL layers can be accommodated by both the composition of the interconnect materials, and the height of the interconnect; 6. An optional HDL layer may be placed on the second side of the die at 707. This optional layer can perform at least two functions: it may act as a second heat dispersive layer (HDL 2) close to the die, and may also help mitigate differences in thermal expansion between the die and the frontside HDL (HDL 1); 7. The above described HDL+Die or HDL1+Die+HDL2 structure may be referred to as the Heat Distribution Structure (HDS); 8. The process for placing the HDS may be incorporated into the standard die packaging process at 708; and 9. Vias and or thermally conductive structures 710 on the package may be formed in the package at 709 to connect to thermal pads on either or both HDL layers.

[0116] In some cases, the intermediary devices formed during the wafer-level packaging process may be integrated into the semiconductor devices described above, such that the intermediary devices can be used in conjunction with the cooling elements, cold plates, heat extraction elements, and other heat dispersion devices disclosed herein.Clauses

[0117] 1. A system for cooling a semiconductor device, the system comprising: a wafer comprising a first material having a thermal conductivity greater than about 1,000 Watts per meter-Kelvin (W / mK) at room temperature; and an interfacial layer comprising a first cooling element, wherein the first cooling element comprises a second material different from thefirst material; wherein the wafer is coupled to the semiconductor device via the interfacial material.

[0118] 2 The system of clause 1, wherein the first material comprises diamond.

[0119] 3 The system of clauses 1 or 2, further comprising a second cooling element coupled to the wafer, wherein the semiconductor device is coupled to the wafer on a first side and the second cooling element is coupled to the wafer on a second side.

[0120] 4. The system of clause 3, wherein the second cooling element comprises a cold plate.

[0121] 5. The system of clause 4, wherein the cold plate comprises silicon carbide, copper, aluminum, graphite, copper-tungsten alloy, or any combination thereof.

[0122] 6. The system of clause 4 or 5, wherein the cold plate comprises a third material having a thermal conductivity of at least about 200 W / mK.

[0123] 7. The system of clause 6, wherein the thermal conductivity of the third material is less than the thermal conductivity of the first material.

[0124] 8. The system of clause 3, wherein the second cooling element comprises one or more cooling fluids in a plate.

[0125] 9. The system of clause 8, wherein the one or more cooling fluids comprise one or more of water, fluorocarbon-based liquids, synthetic oils, cooled air, non-corroding and phase transition fluids, or any combination thereof.

[0126] 10. The system of any one of clauses 3 to 9, wherein the second cooling element comprises micro-channels to facilitate fluid cooling.

[0127] 11. The system of any one of clauses 3 to 10, wherein the second cooling element comprises a vapor chamber.

[0128] 12. The system of any one of clauses 3 to 11, wherein the second cooling element is coupled to the wafer via a second interfacial layer.

[0129] 13. The system of any one of clauses 1 to 12, wherein the wafer has a surface area equal to or greater than a surface area of the semiconductor device.

[0130] 14. The system of clause 13, wherein the surface area of the wafer is at least about 15% greater than the surface area of the semiconductor device.

[0131] 15. The system of clause 14, wherein the surface area of the wafer is at least about 25% greater than the surface area of the semiconductor device.

[0132] 16. The system of any one of clauses 3 to 15, wherein the second cooling element has a surface area equal to or greater than a surface area of the wafer.

[0133] 17. The system of any one of clauses 3 to 16, wherein the wafer comprises one or more geometrical shapes to increase a surface area of the wafer which comes in contact with the second cooling element.

[0134] 18. The system of any one of clauses 1 to 17, wherein the wafer is configured to decrease a temperature difference between the semiconductor device and the second cooling element by at least 50%.

[0135] 19. The system of any one of clauses 3 to 18, further comprising a third cooling element.

[0136] 20. The system of clause 19, wherein the third cooling element comprises the second cooling element.

[0137] 21. The system of clause 19 or 20, wherein the second cooling element is coupled to the third cooling element.

[0138] 22. The system of any one of clauses 19 to 21, wherein the third cooling element comprises copper, aluminum, diamond, other high conductivity materials, or any combination thereof.

[0139] 23. The system of any one of clauses 19 to 22, wherein the third cooling element comprises one or more heat dissipation elements comprising liquids, gases, vapor chambers, heat pipes, or any combination thereof.

[0140] 24. The system of any one of clauses 19 to 23, wherein the third cooling element has a thermal conductivity of at least about 3,000 W / mK.

[0141] 25. The system of clause 24, wherein the third cooling element has a thermal conductivity of from about 5,000 W / mK to about 10,000 W / mK.

[0142] 26. The system of any one of clauses 19 to 25, wherein the third cooling element has a surface area equal to or greater than a surface area of the wafer.

[0143] 27. The system of clause 26, wherein the surface area of the third cooling element is at least about 5% greater than the surface area of the wafer.

[0144] 28. The system of any one of clauses 1 to 27, wherein the wafer is at least about one millimeter (mm) thick.

[0145] 29. The system of clause 28, wherein the wafer is from about 1 mm thick to about 2 mm thick.

[0146] 30. The system of any one of clauses 1 to 27, wherein the wafer is from about 250 microns thick to about 2.5mm thick.

[0147] 31. The system of any one of clauses 1 to 30, wherein the wafer has a surface area equal to or greater than a hot spot of the semiconductor device.

[0148] 32. The system of clause 31, wherein the wafer’s surface area is 25% greater than the hot spot.

[0149] 33. The system of any one of clauses 1 to 32, wherein the interfacial layer is configured to reduce the thermal resistance between the semiconductor device and the wafer.

[0150] 34. The system of any one of clauses 1 to 33, wherein the interfacial layer comprises a cooling liquid.

[0151] 35. The system of any one of clauses 1 to 34, wherein the interfacial layer has a shear modulus of less than about 10 GigaPascals (GPa).

[0152] 36. The system of clause 35, wherein the interfacial layer has a shear modulus of less than about 2 GPa.

[0153] 37. The system of any one of clauses 1 to 36, wherein the interfacial layer has a viscosity of greater than about 0.5 milliPascal seconds (mPa*s).

[0154] 38. The system of any one of clauses 1 to 37, wherein the wafer comprises fins or other structures to maximize surface area and enhance heat dissipation.

[0155] 39. The system of any one of clauses 1 to 38, further comprising a printed circuit board (PCB).

[0156] 40. The system of any one of clauses 1 to 39, wherein a thermal performance of the semiconductor device is improved despite a higher average linear thermal resistance.

[0157] 41. The system of any one of clauses 1 to 40, wherein the semiconductor device comprises silicon or a silicon alloy.

[0158] 42. The system of any one of clauses 1 to 41, wherein the semiconductor device comprises a semiconductor chip.

[0159] 43. The system of clause 42, wherein the semiconductor chip is configured for use in a GPU located in a data center.

[0160] 44. The system of clause 42, wherein the semiconductor chip is configured for use in an individual computing device.

[0161] 45. A method for cooling a semiconductor device, the method comprising: coupling a wafer to the semiconductor device via an interfacial layer; wherein the wafer comprises a first material having a thermal conductivity greater than about 1,000 Watts per meter-Kelvin (W / mK) at room temperature; wherein the interfacial layer comprises a first cooling element comprising a second material different from the first material.

[0162] 46. The method of clause 45, wherein the first material comprises diamond.

[0163] 47. The method of any clause 45 or 46, further comprising coupling a second cooling element to the wafer such that semiconductor device is coupled to the wafer on a first side and the second cooling element is coupled to the wafer on a second side.

[0164] 48. The method of clause 47, wherein the second cooling element comprises a cold plate.

[0165] 49. The method of clause 48, wherein the cold plate comprises silicon carbide, copper, aluminum, graphite, copper-tungsten alloy, or any combination thereof.

[0166] 50. The method of clause 48 or 49, wherein the cold plate comprises a third material having a thermal conductivity of at least about 200 W / mK.

[0167] 51. The method of clause 50, wherein the thermal conductivity of the third material is less than the thermal conductivity of the first material.

[0168] 52. The method of clause 47, wherein the second cooling element comprises one or more cooling fluids in a plate.

[0169] 53. The method of clause 52, wherein the one or more cooling fluids comprise one or more of water, fluorocarbon-based liquids, synthetic oils, cooled air, non-corroding and phase transition fluids, or any combination thereof.

[0170] 54. The method of any one of clauses 47 to 53, wherein the second cooling element comprises micro-channels to facilitate fluid cooling.

[0171] 55. The method of any one of clauses 47 to 54, wherein the second cooling element comprises a vapor chamber.

[0172] 56. The method of any one of clauses 47 to 55, further comprising coupling the second cooling element to the wafer via a second interfacial layer.

[0173] 57. The method of any one of clauses 47 to 56, wherein the wafer has a surface area equal to or greater than a surface area of the semiconductor device.

[0174] 58. The method of clause 57, wherein the surface area of the wafer is at least about 15% greater than the surface area of the semiconductor device.

[0175] 59. The method of clause 58, wherein the surface area of the wafer is at least 25% greater than the surface area of the semiconductor device.

[0176] 60. The method of any one of clauses 47 to 59, wherein the second cooling element has a surface area equal to or greater than a surface area of the wafer.

[0177] 61. The method of any one of clauses 47 to 60, wherein the wafer comprises one or more geometrical shapes to increase a surface area of the wafer which comes in contact with the second cooling element.

[0178] 62. The method of any one of clauses 47 to 61, further comprising decreasing, via the wafer, a temperature difference between the semiconductor device and the second cooling element by at least 50%.

[0179] 63. The method of any one of clauses 47 to 62, further comprising coupling a third cooling element to the second cooling element.

[0180] 64. The method of clause 63, further comprising integrating the second cooling element into a third cooling element.

[0181] 65. The method of clauses 63 or 64, wherein the third cooling element comprises copper, aluminum, diamond, other high conductivity materials, or any combination thereof.

[0182] 66. The method of any one of clauses 63 to 65, wherein the third cooling element comprises one or more heat dissipation elements comprising liquids, gases, vapor chambers, heat pipes, or any combination thereof.

[0183] 67. The method of any one of clauses 63 to 66, wherein the third cooling element has a thermal conductivity of at least about 3,000 W / mK.

[0184] 68. The method of clause 67, wherein the third cooling element has a thermal conductivity of from about 5,000 W / mK to about 10,000 W / mK.

[0185] 69. The method of any one of clauses 63 to 68, wherein the third cooling element has a surface area equal to or greater than a surface area of the wafer.

[0186] 70. The method of clause 69, wherein the surface area of the third cooling element is at least about 5% greater than the surface area of the wafer.

[0187] 71. The method of any one of clauses 45 to 70, wherein the wafer is at least about one millimeter (mm) thick.

[0188] 72. The method of clause 71, wherein the wafer is from about 1 mm thick to about 2 mm thick.

[0189] 73. The method of any one of clauses 45 to 70, wherein the wafer is from about 250 microns thick to about 2.5mm thick.

[0190] 74. The method of any one of clauses 45 to 73, wherein the wafer has a surface area equal to or greater than a hot spot of the semiconductor device.

[0191] 75. The method of clause 74, wherein the wafer’s surface area is 25% greater than the hot spot.

[0192] 76. The method of any one of clauses 45 to 75, wherein the interfacial layer is configured to reduce the thermal resistance between the semiconductor device and the wafer.

[0193] 77. The method of any one of clauses 45 to 76, wherein the interfacial layer comprises a cooling liquid.

[0194] 78. The method of any one of clauses 45 to 77, wherein the interfacial layer has a shear modulus of less than about 45.5 GigaPascals (GPa).

[0195] 79. The method of clause 78, wherein the interfacial layer has a shear modulus of less than about 45 GPa.

[0196] 80. The method of any one of clauses 45 to 79, wherein the interfacial layer has a viscosity of greater than about 0.5 milliPascal seconds (mPa*s).

[0197] 81. The method of any one of clauses 45 to 80, wherein the wafer comprises fins or other structures to maximize surface area and enhance heat dissipation.

[0198] 82. The method of any one of clauses 45 to 81, further comprising coupling the semiconductor device to a printed circuit board (PCB).

[0199] 83. The method of any one of clauses 45 to 82, wherein a thermal performance of the semiconductor device is improved despite a higher average linear thermal resistance.

[0200] 84. The method of any one of clauses 45 to 83, wherein the semiconductor device comprises silicon or a silicon alloy.

[0201] 85. The method of any one of clauses 45 to 84, wherein the semiconductor device comprises a semiconductor chip.

[0202] 86. The method of clause 85, further comprising using the semiconductor chip in a GPU located in a data center.

[0203] 87. The method of clause 86, further comprising using the semiconductor chip in an individual computing device.

[0204] 88. A method for manufacturing a known good die (KGD), the method comprising: probing a wafer to create a plurality of electrical outputs on a first side of the wafer; cutting the wafer into one or more dies, wherein each of the one or more dies comprises an electrical output of the plurality of electrical outputs in both distal ends of a first side of the one or more dies; forming a plurality of vias in a heat dissipating layer (HDL), wherein a separation distance between at least some of the plurality of vias is substantially the same as a separation distance between at least some of the plurality of electrical outputs on the one or more dies; lining up the plurality of vias in the HDL and the electrical outputs in the one or more dies; coupling the first side of the one or more dies to the HDL, thereby forming the KGD; and coupling the KGD onto a carrier wafer.

[0205] 89. The method of clause 88, wherein coupling the first side of the one or more dies to the HDL comprises coupling via one or more of a mechanical connection, thermal connection, electrical connection, or any combination thereof.

[0206] 90. The method of clause 88 or 89, further comprising backgrinding the wafer after step (a).

[0207] 91. The method of any one of clauses 88 to 90, further comprising cutting the HDL into a plurality of smaller HDLs after step (d) such that each of the plurality of smaller HDLs have a via on both distal ends.

[0208] 92. The method of clause 91, wherein each of the plurality of the smaller HDLs has a length greater than a length of each of the one or more dies.

[0209] 93. The method of any one of clauses 88 to 92, further comprising coupling a second HDL to a second side of the one or more dies such that the one or more dies are sandwiched between the HDL and the second HDL.

[0210] 94. The method of clause 93, further comprising coupling the one or more dies to the HDL, the second HDL, or both via an intermediate layer.

[0211] 95. The method of clause 93 or 94, wherein coupling the second HDL to a second side of the one or more dies comprises coupling via one or more of a mechanical connection, thermal connection, electrical connection, or any combination thereof.

[0212] 96. The method of any one of clauses 88 to 95, wherein step (c) is executed before, after, or simultaneously to steps (a) and (b).

[0213] 97. The method of any one of clauses 88 to 96, wherein the KGD is coupled onto the carrier wafer with one or more adhesives.

[0214] 98. The method of any one of clauses 88 to 97, wherein the HDL comprises silicon carbide, diamond, aluminum nitride, ceramic materials which are thermally conductive and electrically insulative, polymeric materials which are thermally conductive and electrically insulative, or any combination thereof.

[0215] 99. The method of clause 98, wherein the diamond is natural, synthetic, or a combination thereof.

[0216] 100. The method of any one of clauses 88 to 99, wherein the HDL comprises an epitaxially grown material.

[0217] 101. The method of any one of clauses 88 to 100, wherein the HDL comprises a single-crystalline material, polycrystalline material, amorphous material, or any combination thereof.

[0218] 102. A method for wafer-level packaging, the method comprising: placing a wafer mold over the known good die (KGD) of any of the preceding clauses; removing the carrier wafer from the KGD, thereby creating a second wafer; coating the second wafer with a first polymer coat; curing the first polymer coat; depositing a redistribution layer (RDL) onto thesecond wafer; coating the second wafer with a second polymer coat; curing the second polymer coat; depositing an under bump metal (UBM) layer onto the second wafer; flux printing solder balls onto the second wafer; probing the second wafer; and cutting the second wafer into individually-sized second wafer pieces for wafer-level packaging.

[0219] 103. The method of clause 102, further comprising cleaning the second wafer formed after step (b).

[0220] 104. The method of clause 102 or 103, wherein the second wafer comprises a fanout wafer.

[0221] 105. The method of clause 102 or 103, wherein the second wafer comprises a fan-in wafer.

[0222] 106. The method of any one of clauses 102 to 105, wherein depositing the RDL comprises: sputtering an RDL seed layer onto the second wafer; resist-coating the RDL seed layer; developing the resist-coated RDL seed layer; patterning an RDL copper pattern plate onto the RDL seed layer; resist-stripping the RDL seed layer; and etching the RDL seed layer.

[0223] 107. The method of clause 106, wherein developing the resist-coated RDL seed layer comprises one or more of imaging, developing, or curing.

[0224] 108. The method of any one of clauses 102 to 107, wherein depositing the UBM layer comprises: sputtering a UBM seed layer onto the second wafer; resist-coating the UBM seed layer; developing the resist-coated UBM seed layer; patterning a UBM pattern plate onto the UBM seed layer; resist-stripping the UBM seed layer; and etching the UBM seed layer.

[0225] 109. The method of clause 108, wherein developing the resist-coated UBM seed layer comprises one or more of imaging, developing, or curing.

[0226] 110. The method of clause 108 or 109, wherein the UBM seed layer comprises one or more of copper, aluminum, gold, metal alloys, electrically conductive material, or any combination thereof.

[0227] 111. The method of any one of clauses 102 to 110, further comprising reflowing the solder balls after step (i).

[0228] 112. The method of any one of clauses 102 to 111, further comprising laser marking the second wafer after step (j).

[0229] 113. The method of any one of clauses 102 to 112, wherein the first polymer coat comprises a photoresist, parylene, polyimides, polytetrafluoroethylene (PTFE), epol02y, silicone, acrylate, conductive polymers, or any combination thereof.

[0230] 114. The method of any one of clauses 102 to 113, wherein curing the first polymer coat comprises one or more of imaging, developing, or curing.

[0231] 115. The method of any one of clauses 102 to 114, wherein the second polymer coat comprises a photoresist, parylene, polyimides, polytetrafluoroethylene (PTFE), epol02y, silicone, acrylate, conductive polymers, or any combination thereof.

[0232] 116. The method of any one of clauses 102 to 115, wherein curing the second polymer coat comprises one or more of imaging, developing, or curing.

[0233] 117. The method of any one of clauses 102 to 116, further comprising taping and reeling the individually sized second wafer pieces.

[0234] 118. The method of any one of clauses 102 to 117, further comprising: placing one or more thermal pads onto each heat dissipating layer (HDL) in the KGD; and placing one or more thermal pads onto an external side of the wafer level packaging, wherein the thermal pads on the each HDL are electrically connected to the one or more thermal pads on the external side of the wafer level packaging via a plurality of vias in the wafer packaging.

[0235] 119. The method of clause 118, wherein the vias in the wafer packaging comprise vias in any combination of layers in the wafer packaging or all layers in the wafer packaging.

[0236] 120. A wafer package created through wafer-level packaging, the wafer package comprising: a known good die (KGD) disposed within a wafer mold, the KGD comprising: a die comprising a plurality of electrical outlets on a first side of the die; a heat dissipating layer (HDL) comprising a plurality of vias and coupled to the die, wherein a separation distance between at least some of the plurality of vias is substantially the same as a separation distance between at least some of the plurality of electrical outputs on the die, such that the plurality of electrical outlets line up with the plurality of vias; one or more thermal pads coupled to the HDL; and one or more thermal pads coupled to an external side of the wafer package, wherein the thermal pads on the HDL are electrically coupled to the one or more thermal pads on the external side of the wafer package via a plurality of vias in the wafer package.

[0237] 121. The wafer package of clause 120, further comprising a redistribution layer (RDL) copper pattern plate coupled to the KGD on a first side of the RDL copper pattern plate.

[0238] 122. The wafer package of clause 121, further comprising a first side of an under bump metallization (UBM) pattern plate coupled to the RDL copper pattern plate on a second side of the RDL copper pattern plate, wherein the first side of the RDL copper pattern plate is opposite the second side of the RDL copper pattern plate.

[0239] 123. The wafer package of clause 122, further comprising solder elements coupled to a second side of the UBM pattern plate, wherein the first side of the UBM pattern plate is opposite the second side of the UBM pattern plate.

[0240] 124. The wafer package of any one of clauses 120 to 123, wherein the first side of the die is coupled to the HDL via one or more of a mechanical connection, thermal connection, electrical connection, or any combination thereof.

[0241] 125. The wafer package of any one of clauses 120 to 124, wherein the plurality of electrical outlets and the plurality of vias are proximate both distal ends of the die and the HDL, respectively.

[0242] 126. The wafer package of any one of clauses 120 to 125, wherein the HDL has a length greater than a length of the die.

[0243] 127. The wafer package of any one of clauses 120 to 126, further comprising a second HDL coupled to a second side of the die such that the die is sandwiched between the HDL and the second HDL.

[0244] 128. The wafer package of clause 127, wherein the HDL, the second HDL, or both are coupled to the die via an intermediate layer.

[0245] 129. The wafer package of clause 127 or 128, wherein the die is coupled to the second HDL via one or more of a mechanical connection, thermal connection, electrical connection, or any combination thereof.

[0246] 130. The wafer package of any one of clauses 127 to 129, further comprising one or more thermal pads coupled to the second HDL and electrically coupled to the one or more thermal pads coupled to the external side of the wafer package via the plurality of vias throughout the wafer package.

[0247] 131. The wafer package of clause 130, wherein the vias throughout the wafer package comprise via in any combination of layers in the wafer package or all layers in the wafer package.

[0248] 132. The wafer package of any one of clauses 120 to 131, wherein the HDL comprises silicon carbide, diamond, aluminum nitride, ceramic materials which are thermally conductive and electrically insulative, polymeric materials which are thermally conductive and electrically insulative, or any combination thereof.

[0249] 133. The wafer package of clause 132, wherein the diamond is natural, synthetic, or a combination thereof.

[0250] 134. The wafer package of any one of clauses 120 to 133, wherein the HDL comprises an epitaxially grown material.

[0251] 135. The wafer package of any one of clauses 120 to 134, wherein the HDL comprises a single-crystalline material, polycrystalline material, amorphous material, or any combination thereof.

[0252] 136. The wafer package of any one of clauses 120 to 135, wherein the wafer package comprises a fan-out wafer package.

[0253] 137. The wafer package of any one of clauses 120 to 135, wherein the wafer package comprises a fan-in wafer package.

[0254] 138. The system of any one of clauses 1 to 44, wherein the semiconductor device comprises the wafer package of any one of clauses 120 to 137.Definitions

[0255] Embodiments of the present disclosure may be understood by reference to the detailed figures and description set forth herein. Embodiments of the disclosure are discussed with reference to the Figures. However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes as the disclosure extends beyond these limited embodiments. For example, it should be appreciated that those skilled in the art will, in light of the teachings of the present disclosure, recognize a multiplicity of alternate and suitable approaches, depending upon the particular application, to implement the functionality of any given detail described herein, beyond the particular implementation choices in the following embodiments described and shown. That is, there are numerous modifications and variations of the disclosure that are too numerous to be listed but that all fit within the scope of the disclosure. Also, singular words should be read as plural and vice versa and masculine as feminine and vice versa, where appropriate, and alternative embodiments do not necessarily imply that the two are mutually exclusive. Also, compounds, materials, manufacturing techniques, uses, and applications as described herein, may vary and therefore, the embodiments presented herein must be read in a non-limiting manner.

[0256] It shall be understood that different aspects of the disclosure can be appreciated or modified individually, collectively, or in combination with each other. Where values are described as ranges, it will be understood that such disclosure includes the disclosure of all possible sub-ranges within such ranges, as well as specific numerical values that fall within such ranges irrespective of whether a specific numerical value or specific sub-range is expressly stated.

[0257] It shall be understood that while operations of a method described herein may be presented sequentially, this is for illustrative purposes. Operations of a method described herein may be completed contemporaneously, and in any order, without departing from the present disclosure.

[0258] Elements as shown in FIGs. 1-7B are not to scale, and may include, for example, magnified or exaggerated thicknesses and surface roughness.

[0259] It is also to be understood that the terminology used herein is used for the purpose of describing particular embodiments only and is not intended to limit the scope of the present disclosure. It must be noted that as used herein and in the appended claims, the singular forms “a,” “an,” and “the” include the plural reference unless the context clearly dictates otherwise. Thus, for example, a reference to “an element” is a reference to one or more elements and includes equivalents thereof known to those skilled in the art. It is to be further understood that the present disclosure is not limited to the particular methodology in the art. Similarly, for another example, a reference to “a step” or “a means” is a reference to one or more steps or means and may include sub steps and subservient means.

[0260] All conjunctions used are to be understood in the most inclusive sense possible. Thus, the word “or” should be understood as having the definition of a logical “or” rather than that of a logical “exclusive or” unless the context clearly necessitates otherwise. Structures described herein are to be understood also to refer to functional equivalents of such structures. Language that may be construed to express approximation should be so understood unless the context clearly dictates otherwise.

[0261] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Preferred methods, techniques, devices, and materials are described, although any methods, techniques, devices, or materials similar or equivalent to those described herein may be used in the practice or testing of the present disclosure.

[0262] Structures described herein are to be understood also to refer to functional equivalents of such structures. The present disclosure will now be described in detail with reference to embodiments thereof as illustrated in the accompanying drawings. From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the art, and which may be used instead of or in addition to features already described herein. Although Claims may have been formulated in this Application to particular combinations of features, it should be understood that the scope of the disclosure ofthe present disclosure also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalization thereof, whether or not it relates to the same disclosure as presently claimed in any Claim and whether or not it mitigates any or all of the same technical problems as does the present disclosure.

[0263] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination. References to “one embodiment,” “an embodiment,” “example embodiment,” “various embodiments,” etc., may indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “In some cases,” or “in an exemplary embodiment,” do not necessarily refer to the same embodiment, although they may. Additionally, the phrases like “one embodiment,” “an embodiment,” or “another embodiment” mean that a particular feature, structure, or characteristic described in conjunction with the embodiment can be included in at least one embodiment of the disclosure. The appearances of the phrase “In some cases” in various places in the specification do not necessarily all refer to the same embodiment. Although the processes are described herein in terms of some sequential operations, it should be appreciated that some of the operations described can be performed in a different order. Moreover, some operations can be performed in parallel rather than sequentially.

[0264] As is well known to those skilled in the art many careful considerations and compromises may be made when designing for the optimal manufacture of a commercial implementation any system, and in particular, the embodiments of the present disclosure.

[0265] A commercial implementation in accordance with the spirit and teachings of the present disclosure may be configured according to the particular application, whereby any aspect(s), feature(s), function(s), result(s), component(s), approach(es), or step(s) of the teachings related to any described embodiment of the present disclosure may be suitably omitted, included, adapted, mixed and matched, or improved and / or optimized by those skilled in the art, using their average skills and known techniques, to achieve the desired implementation that addresses the particular application.

[0266] Those skilled in the art will readily recognize, in light of and in accordance with the teachings of the present disclosure, that any of the foregoing steps may be suitably replaced; reordered, removed and additional steps may be inserted depending upon the particularapplication. Moreover, the prescribed method steps of the foregoing embodiments may be implemented using any physical and / or hardware system that those skilled in the art will readily know is suitable in light of the foregoing teachings. For any method steps described in the present application that can be carried out on a computing machine, a computer system can, when appropriately configured or designed, serve as a computer system in which those aspects of the disclosure may be embodied. Thus, the present disclosure is not limited to any particular tangible means of implementation.

[0267] Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs.

[0268] As used herein, the singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise. Any reference to “or” herein is intended to encompass “and / or” unless otherwise stated.

[0269] As used herein, the term “about” in some cases refers to an amount that is approximately the stated amount.

[0270] As used herein, the term “about” refers to an amount that is near the stated amount by 10%, 5%, or 1%, including increments therein.

[0271] As used herein, the term “about” in reference to a percentage refers to an amount that is greater or less the stated percentage by 10%, 5%, or 1%, including increments therein.

[0272] As used herein, the phrases “at least one,” “one or more,” and “and / or” are open- ended expressions that are both conjunctive and disjunctive in operation. For example, each of the expressions “at least one of A, B and C”, “at least one of A, B, or C”, “one or more of A, B, and C”, “one or more of A, B, or C” and “A, B, and / or C” means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B and C together.

[0273] While preferred embodiments of the present disclosure have been shown and described herein, such embodiments are provided by way of example only. It is not intended that the present disclosure be limited by the specific examples provided within the specification. While the present disclosure has been described with reference to the aforementioned specification, the descriptions and illustrations of the embodiments herein are not meant to be construed in a limiting sense. Numerous variations, changes, and substitutions may occur without departing from the present disclosure. Furthermore, it shall be understood that all aspects of the present disclosure are not limited to the specific depictions, configurations, or relative proportions set forth herein which depend upon a variety of conditions and variables. It should be understood that various alternatives to theembodiments of the present disclosure described herein may be employed in practicing the present disclosure. It is therefore contemplated that the present disclosure shall also cover any such alternatives, modifications, variations, or equivalents. It is intended that the following claims define the scope of the present disclosure and that systems, methods, and structures within the scope of these claims and their equivalents be covered thereby.

Claims

CLAIMSWHAT IS CLAIMED IS:

1. A system for cooling a semiconductor device, the system comprising: a. a wafer comprising a first material having a thermal conductivity greater than about 1,000 Watts per meter-Kelvin (W / mK) at room temperature; and b. an interfacial layer comprising a first cooling element, wherein the first cooling element comprises a second material different from the first material; c. wherein the wafer is coupled to the semiconductor device via the interfacial material.

2. The system of claim 1, wherein the first material comprises diamond.

3. The system of claims 1 or 2, further comprising a second cooling element coupled to the wafer, wherein the semiconductor device is coupled to the wafer on a first side and the second cooling element is coupled to the wafer on a second side.

4. The system of claim 3, wherein the second cooling element comprises a cold plate.

5. The system of claim 4, wherein the cold plate comprises silicon carbide, copper, aluminum, graphite, copper-tungsten alloy, or any combination thereof.

6. The system of claim 4 or 5, wherein the cold plate comprises a third material having a thermal conductivity of at least about 200 W / mK.

7. The system of claim 6, wherein the thermal conductivity of the third material is less than the thermal conductivity of the first material.

8. The system of claim 3, wherein the second cooling element comprises one or more cooling fluids in a plate.

9. The system of claim 8, wherein the one or more cooling fluids comprise one or more of water, fluorocarbon-based liquids, synthetic oils, cooled air, non-corroding and phase transition fluids, or any combination thereof.

10. The system of any one of claims 3 to 9, wherein the second cooling element comprises micro-channels to facilitate fluid cooling.

11. The system of any one of claims 3 to 10, wherein the second cooling element comprises a vapor chamber.

12. The system of any one of claims 3 to 11, wherein the second cooling element is coupled to the wafer via a second interfacial layer.

13. The system of any one of claims 1 to 12, wherein the wafer has a surface area equal to or greater than a surface area of the semiconductor device.

14. The system of claim 13, wherein the surface area of the wafer is at least about 15% greater than the surface area of the semiconductor device.

15. The system of claim 14, wherein the surface area of the wafer is at least about 25% greater than the surface area of the semiconductor device.

16. The system of any one of claims 3 to 15, wherein the second cooling element has a surface area equal to or greater than a surface area of the wafer.

17. The system of any one of claims 3 to 16, wherein the wafer comprises one or more geometrical shapes to increase a surface area of the wafer which comes in contact with the second cooling element.

18. The system of any one of claims 1 to 17, wherein the wafer is configured to decrease a temperature difference between the semiconductor device and the second cooling element by at least 50%.

19. The system of any one of claims 3 to 18, further comprising a third cooling element.

20. The system of claim 19, wherein the third cooling element comprises the second cooling element.

21. The system of claim 19 or 20, wherein the second cooling element is coupled to the third cooling element.

22. The system of any one of claims 19 to 21, wherein the third cooling element comprises copper, aluminum, diamond, other high conductivity materials, or any combination thereof.

23. The system of any one of claims 19 to 22, wherein the third cooling element comprises one or more heat dissipation elements comprising liquids, gases, vapor chambers, heat pipes, or any combination thereof.

24. The system of any one of claims 19 to 23, wherein the third cooling element has a thermal conductivity of at least about 3,000 W / mK.

25. The system of claim 24, wherein the third cooling element has a thermal conductivity of from about 5,000 W / mK to about 10,000 W / mK.

26. The system of any one of claims 19 to 25, wherein the third cooling element has a surface area equal to or greater than a surface area of the wafer.

27. The system of claim 26, wherein the surface area of the third cooling element is at least about 5% greater than the surface area of the wafer.

28. The system of any one of claims 1 to 27, wherein the wafer is at least about one millimeter (mm) thick.

29. The system of claim 28, wherein the wafer is from about 1 mm thick to about 2 mm thick.

30. The system of any one of claims 1 to 27, wherein the wafer is from about 250 microns thick to about 2.5mm thick.

31. The system of any one of claims 1 to 30, wherein the wafer has a surface area equal to or greater than a hot spot of the semiconductor device.

32. The system of claim 31, wherein the wafer’s surface area is 25% greater than the hot spot.

33. The system of any one of claims 1 to 32, wherein the interfacial layer is configured to reduce the thermal resistance between the semiconductor device and the wafer.

34. The system of any one of claims 1 to 33, wherein the interfacial layer comprises a cooling liquid.

35. The system of any one of claims 1 to 34, wherein the interfacial layer has a shear modulus of less than about 10 GigaPascals (GPa).

36. The system of claim 35, wherein the interfacial layer has a shear modulus of less than about 2 GPa.

37. The system of any one of claims 1 to 36, wherein the interfacial layer has a viscosity of greater than about 0.5 milliPascal seconds (mPa*s).

38. The system of any one of claims 1 to 37, wherein the wafer comprises fins or other structures to maximize surface area and enhance heat dissipation.

39. The system of any one of claims 1 to 38, further comprising a printed circuit board (PCB).

40. The system of any one of claims 1 to 39, wherein a thermal performance of the semiconductor device is improved despite a higher average linear thermal resistance.

41. The system of any one of claims 1 to 40, wherein the semiconductor device comprises silicon or a silicon alloy.

42. The system of any one of claims 1 to 41, wherein the semiconductor device comprises a semiconductor chip.

43. The system of claim 42, wherein the semiconductor chip is configured for use in a GPU located in a data center.

44. The system of claim 42, wherein the semiconductor chip is configured for use in an individual computing device.

45. A method for cooling a semiconductor device, the method comprising: a. coupling a wafer to the semiconductor device via an interfacial layer; b. wherein the wafer comprises a first material having a thermal conductivity greater than about 1,000 Watts per meter-Kelvin (W / mK) at room temperature; c. wherein the interfacial layer comprises a first cooling element comprising a second material different from the first material.

46. The method of claim 45, wherein the first material comprises diamond.

47. The method of any claim 45 or 46, further comprising coupling a second cooling element to the wafer such that semiconductor device is coupled to the wafer on a first side and the second cooling element is coupled to the wafer on a second side.

48. The method of claim 47, wherein the second cooling element comprises a cold plate.

49. The method of claim 48, wherein the cold plate comprises silicon carbide, copper, aluminum, graphite, copper-tungsten alloy, or any combination thereof.

50. The method of claim 48 or 49, wherein the cold plate comprises a third material having a thermal conductivity of at least about 200 W / mK.

51. The method of claim 50, wherein the thermal conductivity of the third material is less than the thermal conductivity of the first material.

52. The method of claim 47, wherein the second cooling element comprises one or more cooling fluids in a plate.

53. The method of claim 52, wherein the one or more cooling fluids comprise one or more of water, fluorocarbon-based liquids, synthetic oils, cooled air, non-corroding and phase transition fluids, or any combination thereof.

54. The method of any one of claims 47 to 53, wherein the second cooling element comprises micro-channels to facilitate fluid cooling.

55. The method of any one of claims 47 to 54, wherein the second cooling element comprises a vapor chamber.

56. The method of any one of claims 47 to 55, further comprising coupling the second cooling element to the wafer via a second interfacial layer.

57. The method of any one of claims 47 to 56, wherein the wafer has a surface area equal to or greater than a surface area of the semiconductor device.

58. The method of claim 57, wherein the surface area of the wafer is at least about 15% greater than the surface area of the semiconductor device.

59. The method of claim 58, wherein the surface area of the wafer is at least 25% greater than the surface area of the semiconductor device.

60. The method of any one of claims 47 to 59, wherein the second cooling element has a surface area equal to or greater than a surface area of the wafer.

61. The method of any one of claims 47 to 60, wherein the wafer comprises one or more geometrical shapes to increase a surface area of the wafer which comes in contact with the second cooling element.

62. The method of any one of claims 47 to 61, further comprising decreasing, via the wafer, a temperature difference between the semiconductor device and the second cooling element by at least 50%.

63. The method of any one of claims 47 to 62, further comprising coupling a third cooling element to the second cooling element.

64. The method of claim 63, further comprising integrating the second cooling element into a third cooling element.

65. The method of claims 63 or 64, wherein the third cooling element comprises copper, aluminum, diamond, other high conductivity materials, or any combination thereof.

66. The method of any one of claims 63 to 65, wherein the third cooling element comprises one or more heat dissipation elements comprising liquids, gases, vapor chambers, heat pipes, or any combination thereof.

67. The method of any one of claims 63 to 66, wherein the third cooling element has a thermal conductivity of at least about 3,000 W / mK.

68. The method of claim 67, wherein the third cooling element has a thermal conductivity of from about 5,000 W / mK to about 10,000 W / mK.

69. The method of any one of claims 63 to 68, wherein the third cooling element has a surface area equal to or greater than a surface area of the wafer.

70. The method of claim 69, wherein the surface area of the third cooling element is at least about 5% greater than the surface area of the wafer.

71. The method of any one of claims 45 to 70, wherein the wafer is at least about one millimeter (mm) thick.

72. The method of claim 71, wherein the wafer is from about 1 mm thick to about 2 mm thick.

73. The method of any one of claims 45 to 70, wherein the wafer is from about 250 microns thick to about 2.5mm thick.

74. The method of any one of claims 45 to 73, wherein the wafer has a surface area equal to or greater than a hot spot of the semiconductor device.

75. The method of claim 74, wherein the wafer’s surface area is 25% greater than the hot spot.

76. The method of any one of claims 45 to 75, wherein the interfacial layer is configured to reduce the thermal resistance between the semiconductor device and the wafer.

77. The method of any one of claims 45 to 76, wherein the interfacial layer comprises a cooling liquid.

78. The method of any one of claims 45 to 77, wherein the interfacial layer has a shear modulus of less than about 45.5 GigaPascals (GPa).

79. The method of claim 78, wherein the interfacial layer has a shear modulus of less than about 45 GPa.

80. The method of any one of claims 45 to 79, wherein the interfacial layer has a viscosity of greater than about 0.5 milliPascal seconds (mPa*s).

81. The method of any one of claims 45 to 80, wherein the wafer comprises fins or other structures to maximize surface area and enhance heat dissipation.

82. The method of any one of claims 45 to 81, further comprising coupling the semiconductor device to a printed circuit board (PCB).

83. The method of any one of claims 45 to 82, wherein a thermal performance of the semiconductor device is improved despite a higher average linear thermal resistance.

84. The method of any one of claims 45 to 83, wherein the semiconductor device comprises silicon or a silicon alloy.

85. The method of any one of claims 45 to 84, wherein the semiconductor device comprises a semiconductor chip.

86. The method of claim 85, further comprising using the semiconductor chip in a GPU located in a data center.

87. The method of claim 86, further comprising using the semiconductor chip in an individual computing device.

88. A method for manufacturing a known good die (KGD), the method comprising: a. probing a wafer to create a plurality of electrical outputs on a first side of the wafer; b. cutting the wafer into one or more dies, wherein each of the one or more dies comprises an electrical output of the plurality of electrical outputs in both distal ends of a first side of the one or more dies;c. forming a plurality of vias in a heat dissipating layer (HDL), wherein a separation distance between at least some of the plurality of vias is substantially the same as a separation distance between at least some of the plurality of electrical outputs on the one or more dies; d. lining up the plurality of vias in the HDL and the electrical outputs in the one or more dies; e. coupling the first side of the one or more dies to the HDL, thereby forming the KGD; and f. coupling the KGD onto a carrier wafer.

89. The method of claim 88, wherein coupling the first side of the one or more dies to the HDL comprises coupling via one or more of a mechanical connection, thermal connection, electrical connection, or any combination thereof.

90. The method of claim 88 or 89, further comprising backgrinding the wafer after step (a).

91. The method of any one of claims 88 to 90, further comprising cutting the HDL into a plurality of smaller HDLs after step (d) such that each of the plurality of smaller HDLs have a via on both distal ends.

92. The method of claim 91, wherein each of the plurality of the smaller HDLs has a length greater than a length of each of the one or more dies.

93. The method of any one of claims 88 to 92, further comprising coupling a second HDL to a second side of the one or more dies such that the one or more dies are sandwiched between the HDL and the second HDL.

94. The method of claim 93, further comprising coupling the one or more dies to the HDL, the second HDL, or both via an intermediate layer.

95. The method of claim 93 or 94, wherein coupling the second HDL to a second side of the one or more dies comprises coupling via one or more of a mechanical connection, thermal connection, electrical connection, or any combination thereof.

96. The method of any one of claims 88 to 95, wherein step (c) is executed before, after, or simultaneously to steps (a) and (b).

97. The method of any one of claims 88 to 96, wherein the KGD is coupled onto the carrier wafer with one or more adhesives.

98. The method of any one of claims 88 to 97, wherein the HDL comprises silicon carbide, diamond, aluminum nitride, ceramic materials which are thermally conductive and electrically insulative, polymeric materials which are thermally conductive and electrically insulative, or any combination thereof.

99. The method of claim 98, wherein the diamond is natural, synthetic, or a combination thereof.

100. The method of any one of claims 88 to 99, wherein the HDL comprises an epitaxially grown material.

101. The method of any one of claims 88 to 100, wherein the HDL comprises a single-crystalline material, polycrystalline material, amorphous material, or any combination thereof.

102. A method for wafer-level packaging, the method comprising: a. placing a wafer mold over the known good die (KGD) of any of the preceding claims; b. removing the carrier wafer from the KGD, thereby creating a second wafer; c. coating the second wafer with a first polymer coat; d. curing the first polymer coat; e. depositing a redistribution layer (RDL) onto the second wafer; f. coating the second wafer with a second polymer coat; g. curing the second polymer coat; h. depositing an under-bump metal (UBM) layer onto the second wafer; i. flux printing solder balls onto the second wafer; j . probing the second wafer; and k. cutting the second wafer into individually sized second wafer pieces for waferlevel packaging.

103. The method of claim 102, further comprising cleaning the second wafer formed after step (b).

104. The method of claim 102 or 103, wherein the second wafer comprises a fanout wafer.

105. The method of claim 102 or 103, wherein the second wafer comprises a fan-in wafer.

106. The method of any one of claims 102 to 105, wherein depositing the RDL comprises: a. sputtering an RDL seed layer onto the second wafer; b. resist-coating the RDL seed layer; c. developing the resist-coated RDL seed layer; d. patterning an RDL copper pattern plate onto the RDL seed layer; e. resist-stripping the RDL seed layer; and f. etching the RDL seed layer.

107. The method of claim 106, wherein developing the resist-coated RDL seed layer comprises one or more of imaging, developing, or curing.

108. The method of any one of claims 102 to 107, wherein depositing the UBM layer comprises: a. sputtering a UBM seed layer onto the second wafer; b. resist-coating the UBM seed layer; c. developing the resist-coated UBM seed layer; d. patterning a UBM pattern plate onto the UBM seed layer; e. resist-stripping the UBM seed layer; and f. etching the UBM seed layer.

109. The method of claim 108, wherein developing the resist-coated UBM seed layer comprises one or more of imaging, developing, or curing.

110. The method of claim 108 or 109, wherein the UBM seed layer comprises one or more of copper, aluminum, gold, metal alloys, electrically conductive material, or any combination thereof.

111. The method of any one of claims 102 to 110, further comprising reflowing the solder balls after step (i).

112. The method of any one of claims 102 to 111, further comprising laser marking the second wafer after step (j).

113. The method of any one of claims 102 to 112, wherein the first polymer coat comprises a photoresist, parylene, polyimides, polytetrafluoroethylene (PTFE), epol02y, silicone, acrylate, conductive polymers, or any combination thereof.

114. The method of any one of claims 102 to 113, wherein curing the first polymer coat comprises one or more of imaging, developing, or curing.

115. The method of any one of claims 102 to 114, wherein the second polymer coat comprises a photoresist, parylene, polyimides, polytetrafluoroethylene (PTFE), epol02y, silicone, acrylate, conductive polymers, or any combination thereof.

116. The method of any one of claims 102 to 115, wherein curing the second polymer coat comprises one or more of imaging, developing, or curing.

117. The method of any one of claims 102 to 116, further comprising taping and reeling the individually sized second wafer pieces.

118. The method of any one of claims 102 to 117, further comprising: a. placing one or more thermal pads onto each heat dissipating layer (HDL) in the KGD; and b. placing one or more thermal pads onto an external side of the wafer level packaging, wherein the thermal pads on the each HDL are electrically connected to the one or more thermal pads on the external side of the wafer level packaging via a plurality of vias in the wafer packaging.

119. The method of claim 118, wherein the vias in the wafer packaging comprise vias in any combination of layers in the wafer packaging or all layers in the wafer packaging.

120. A wafer package created through wafer-level packaging, the wafer package comprising: a. a known good die (KGD) disposed within a wafer mold, the KGD comprising: i. a die comprising a plurality of electrical outlets on a first side of the die; ii. a heat dissipating layer (HDL) comprising a plurality of vias and coupled to the die, wherein a separation distance between at least some of the plurality of vias is substantially the same as a separation distance between at least some of the plurality of electrical outputs on the die, such that the plurality of electrical outlets line up with the plurality of vias; b. one or more thermal pads coupled to the HDL; and c. one or more thermal pads coupled to an external side of the wafer package, wherein the thermal pads on the HDL are electrically coupled to the one or more thermal pads on the external side of the wafer package via a plurality of vias in the wafer package.

121. The wafer package of claim 120, further comprising a redistribution layer (RDL) copper pattern plate coupled to the KGD on a first side of the RDL copper pattern plate.

122. The wafer package of claim 121, further comprising a first side of an under bump metallization (UBM) pattern plate coupled to the RDL copper pattern plate on a second side of the RDL copper pattern plate, wherein the first side of the RDL copper pattern plate is opposite the second side of the RDL copper pattern plate.

123. The wafer package of claim 122, further comprising solder elements coupled to a second side of the UBM pattern plate, wherein the first side of the UBM pattern plate is opposite the second side of the UBM pattern plate.

124. The wafer package of any one of claims 120 to 123, wherein the first side of the die is coupled to the HDL via one or more of a mechanical connection, thermal connection, electrical connection, or any combination thereof.

125. The wafer package of any one of claims 120 to 124, wherein the plurality of electrical outlets and the plurality of vias are proximate both distal ends of the die and the HDL, respectively.

126. The wafer package of any one of claims 120 to 125, wherein the HDL has a length greater than a length of the die.

127. The wafer package of any one of claims 120 to 126, further comprising a second HDL coupled to a second side of the die such that the die is sandwiched between the HDL and the second HDL.

128. The wafer package of claim 127, wherein the HDL, the second HDL, or both are coupled to the die via an intermediate layer.

129. The wafer package of claim 127 or 128, wherein the die is coupled to the second HDL via one or more of a mechanical connection, thermal connection, electrical connection, or any combination thereof.

130. The wafer package of any one of claims 127 to 129, further comprising one or more thermal pads coupled to the second HDL and electrically coupled to the one or more thermal pads coupled to the external side of the wafer package via the plurality of vias throughout the wafer package.

131. The wafer package of claim 130, wherein the vias throughout the wafer package comprise via in any combination of layers in the wafer package or all layers in the wafer package.

132. The wafer package of any one of claims 120 to 131, wherein the HDL comprises silicon carbide, diamond, aluminum nitride, ceramic materials which are thermally conductive and electrically insulative, polymeric materials which are thermally conductive and electrically insulative, or any combination thereof.

133. The wafer package of claim 132, wherein the diamond is natural, synthetic, or a combination thereof.

134. The wafer package of any one of claims 120 to 133, wherein the HDL comprises an epitaxially grown material.

135. The wafer package of any one of claims 120 to 134, wherein the HDL comprises a single-crystalline material, polycrystalline material, amorphous material, or any combination thereof.

136. The wafer package of any one of claims 120 to 135, wherein the wafer package comprises a fan-out wafer package.

137. The wafer package of any one of claims 120 to 135, wherein the wafer package comprises a fan-in wafer package.

138. The system of any one of claims 1 to 44, wherein the semiconductor device comprises the wafer package of any one of claims 120 to 137.

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