Pixel driving circuit and driving method thereof, display substrate and display apparatus

Abstract

A pixel driving circuit, a driving method, a display substrate and a display apparatus. The pixel driving circuit comprises a signal input sub-circuit, a signal holding sub-circuit and a signal output sub-circuit; the signal input sub-circuit is configured to, under the control by signals of an input control signal terminal (EM1), a first power supply terminal (VDD), a first node (N1) and a third node (N3), input a first current signal of a current source signal terminal (IREF); the signal holding sub-circuit is configured to, under the control by signals of a control signal holding terminal (EM2) and a ground terminal (GND), provide a signal of the first node (N1) to a second node (N2) and provide a signal of the third node (N3) to a fourth node (N4); and the signal output sub-circuit is configured to, under the control by signals of the second node (N2), the fourth node (N4) and the first power supply terminal (VDD), output a second current signal to a signal output node (OUTN).

Description

Pixel driving circuit and its driving method, display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a pixel driving circuit and its driving method, a display substrate, and a display device. Background Technology

[0002] Augmented Reality (AR) products enhance the user's perception of the displayed world by overlaying virtual signals onto the user's field of vision. The main AR products on the market are AR glasses or head-up displays (HUDs). AR products require high brightness in outdoor scenes, generally exceeding 30,000 nits. Meanwhile, the transmittance of the accompanying waveguide technology is only 0.1% to 1%. Therefore, the brightness of the display screen typically needs to be in the range of 1 million to 10 million nits. Such high brightness is beyond the capabilities of Organic Light-Emitting Diodes (OLEDs), making Light-Emitting Diodes (LEDs) the mainstream choice for AR products.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a pixel driving circuit, including: a signal input sub-circuit, a signal holding sub-circuit, and a signal output sub-circuit;

[0006] The signal input sub-circuit is electrically connected to the input control signal terminal, the current source signal terminal, the first power supply terminal, the first node, and the third node, respectively, and is configured to input the first current signal of the current source signal terminal under the control of the signals of the input control signal terminal, the first power supply terminal, the first node, and the third node;

[0007] The signal holding sub-circuit is electrically connected to the holding control signal terminal, the first node, the second node, the third node, the fourth node and the ground terminal respectively, and is configured to provide the signal of the first node to the second node and the signal of the third node to the fourth node under the control of the signals of the holding control signal terminal and the ground terminal.

[0008] The signal output sub-circuit is electrically connected to the first power supply terminal, the second node, the fourth node and the signal output node respectively, and is configured to output a second current signal to the signal output node under the control of the signals of the second node, the fourth node and the first power supply terminal.

[0009] In an exemplary embodiment, the signal input sub-circuit includes: a first transistor, a third transistor, and a sixth transistor;

[0010] The control electrode of the first transistor is electrically connected to the input control signal terminal, the first electrode of the first transistor is electrically connected to the current source signal terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0011] The control electrode and the second electrode of the third transistor are electrically connected to the first node, and the first electrode of the third transistor is electrically connected to the first power supply terminal.

[0012] The control electrode and the second electrode of the sixth transistor are electrically connected to the third node, respectively, and the first electrode of the sixth transistor is electrically connected to the first node.

[0013] In an exemplary embodiment, the signal output sub-circuit includes a fourth transistor and a seventh transistor;

[0014] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node.

[0015] The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the signal output node.

[0016] In an exemplary embodiment, the signal input sub-circuit is also electrically connected to the node control signal terminal and is configured to provide the signal of the third node to the first node under the control of the signal at the node control signal terminal.

[0017] In an exemplary embodiment, the signal input sub-circuit includes: a first transistor, a third transistor, a sixth transistor, and an eighth transistor;

[0018] The control electrode of the first transistor is electrically connected to the input control signal terminal, the first electrode of the first transistor is electrically connected to the current source signal terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0019] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first power supply terminal, and the second electrode of the third transistor is electrically connected to the fifth node.

[0020] The control electrode and the second electrode of the sixth transistor are electrically connected to the third node, respectively, and the first electrode of the sixth transistor is electrically connected to the fifth node.

[0021] The control electrode of the eighth transistor is electrically connected to the node control signal terminal, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node.

[0022] In an exemplary embodiment, the signal output sub-circuit includes a fourth transistor and a seventh transistor;

[0023] The control electrode and the second electrode of the fourth transistor are electrically connected to the second node, and the first electrode of the fourth transistor is electrically connected to the first power supply terminal.

[0024] The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the signal output node.

[0025] In an exemplary embodiment, the signal holding sub-circuit includes: a second transistor, a fifth transistor, a first capacitor, and a second capacitor;

[0026] The control electrode of the second transistor is electrically connected to the holding control signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node.

[0027] The control electrode of the fifth transistor is electrically connected to the holding control signal terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0028] The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the ground terminal.

[0029] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the ground terminal.

[0030] In an exemplary embodiment, the signal input sub-circuit includes: a first transistor, a third transistor, and a sixth transistor; the signal holding sub-circuit includes: a second transistor, a fifth transistor, a first capacitor, and a second capacitor; and the signal output sub-circuit includes: a fourth transistor and a seventh transistor.

[0031] The control electrode of the first transistor is electrically connected to the input control signal terminal, the first electrode of the first transistor is electrically connected to the current source signal terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0032] The control electrode of the second transistor is electrically connected to the holding control signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node.

[0033] The control electrode and the second electrode of the third transistor are electrically connected to the first node, and the first electrode of the third transistor is electrically connected to the first power supply terminal.

[0034] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node.

[0035] The control electrode of the fifth transistor is electrically connected to the holding control signal terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0036] The control electrode and second electrode of the sixth transistor are electrically connected to the third node, respectively, and the first electrode of the sixth transistor is electrically connected to the first node.

[0037] The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the signal output node.

[0038] The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the ground terminal.

[0039] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the ground terminal.

[0040] At least one of the first to the seventh transistors is a P-type transistor.

[0041] In an exemplary embodiment, the signal input sub-circuit includes: a first transistor, a third transistor, a sixth transistor, and an eighth transistor; the signal holding sub-circuit includes: a second transistor, a fifth transistor, a first capacitor, and a second capacitor; and the signal output sub-circuit includes: a fourth transistor and a seventh transistor.

[0042] The control electrode of the first transistor is electrically connected to the input control signal terminal, the first electrode of the first transistor is electrically connected to the current source signal terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0043] The control electrode of the second transistor is electrically connected to the holding control signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node.

[0044] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first power supply terminal, and the second electrode of the third transistor is electrically connected to the fifth node.

[0045] The control electrode and the second electrode of the fourth transistor are electrically connected to the second node, and the first electrode of the fourth transistor is electrically connected to the first power supply terminal.

[0046] The control electrode of the fifth transistor is electrically connected to the holding control signal terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0047] The control electrode and the second electrode of the sixth transistor are electrically connected to the third node, respectively, and the first electrode of the sixth transistor is electrically connected to the fifth node.

[0048] The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the signal output node.

[0049] The control electrode of the eighth transistor is electrically connected to the node control signal terminal, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node.

[0050] The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the ground terminal.

[0051] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the ground terminal.

[0052] At least one of the first to eighth transistors is a P-type transistor.

[0053] In an exemplary embodiment, the pixel driving circuit is electrically connected to the light-emitting device group and is configured to drive the light-emitting device group to emit light. The pixel driving circuit further includes a duration control sub-circuit.

[0054] The light-emitting device group is electrically connected to the signal output node through the duration control sub-circuit, and the duration control sub-circuit is configured to provide the light-emitting device group with a second current signal output by the signal output node.

[0055] In an exemplary embodiment, the duration control sub-circuit includes: a ninth transistor, a tenth transistor, and a third capacitor;

[0056] The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the signal output sub-circuit, and the second electrode of the ninth transistor is electrically connected to the light-emitting device group.

[0057] The control electrode of the tenth transistor is electrically connected to the duration control signal terminal, the first electrode of the tenth transistor is electrically connected to the data signal terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node.

[0058] The first terminal of the third capacitor is electrically connected to the sixth node, and the second terminal of the third capacitor is electrically connected to the common voltage terminal.

[0059] At least one of the ninth and tenth transistors is a P-type transistor.

[0060] In an exemplary embodiment, the duration control sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor;

[0061] The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the signal output node, and the second electrode of the ninth transistor is electrically connected to the light-emitting device group.

[0062] The control electrode of the tenth transistor is electrically connected to the seventh node, the first electrode of the tenth transistor is electrically connected to the first power supply terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node.

[0063] The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the ground terminal, and the second electrode of the eleventh transistor is electrically connected to the sixth node.

[0064] The control electrode of the twelfth transistor is electrically connected to the sixth node, the first electrode of the twelfth transistor is electrically connected to the first power supply terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node.

[0065] The control electrode of the thirteenth transistor is electrically connected to the sixth node, the first electrode of the thirteenth transistor is electrically connected to the ground terminal, and the second electrode of the thirteenth transistor is electrically connected to the seventh node.

[0066] The control electrode of the fourteenth transistor is electrically connected to the duration control signal terminal, the first electrode of the fourteenth transistor is electrically connected to the first data signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the sixth node.

[0067] The control electrode of the fifteenth transistor is electrically connected to the duration control signal terminal, the first electrode of the fifteenth transistor is electrically connected to the second data signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the seventh node.

[0068] The tenth and eleventh transistors are of different transistor types, the twelfth and thirteenth transistors are of different transistor types, and at least one of the fourteenth and fifteenth transistors is an N-type transistor.

[0069] The signals at the first data signal terminal and the signals at the second data signal terminal are at least inverse signals for a portion of the time period.

[0070] In an exemplary embodiment, the duration control sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor;

[0071] The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the signal output node, and the second electrode of the ninth transistor is electrically connected to the light-emitting device group.

[0072] The control electrode of the tenth transistor is electrically connected to the seventh node, the first electrode of the tenth transistor is electrically connected to the high-frequency signal terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node.

[0073] The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the duration control signal terminal, and the second electrode of the eleventh transistor is electrically connected to the sixth node.

[0074] The control electrode of the twelfth transistor is electrically connected to the scan signal terminal, the first electrode of the twelfth transistor is electrically connected to the data signal terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node.

[0075] The first terminal of the third capacitor is electrically connected to the seventh node, and the second terminal of the third capacitor is electrically connected to the common voltage terminal.

[0076] The tenth and eleventh transistors have opposite transistor types;

[0077] At least one of the ninth and twelfth transistors is a P-type transistor.

[0078] In an exemplary embodiment, the device parameters of the third transistor are the same as those of the fourth transistor;

[0079] The device parameters include: mobility, unit gate oxide capacitance, and channel aspect ratio.

[0080] In an exemplary embodiment, the device parameters of the sixth transistor are the same as those of the seventh transistor;

[0081] The device parameters include: mobility, unit gate oxide capacitance, and channel aspect ratio.

[0082] In a second aspect, this disclosure also provides a display substrate, including: a plurality of light-emitting device groups and the above-mentioned pixel driving circuit, wherein the at least one pixel driving circuit is electrically connected to the light-emitting device groups and is configured to drive the light-emitting device groups to emit light;

[0083] The light-emitting device group includes at least one light-emitting device, and the light-emitting device group is electrically connected to the pixel driving circuit.

[0084] In an exemplary embodiment, the light-emitting device includes a first electrode and a second electrode;

[0085] When the light-emitting device group includes a light-emitting device, the first electrode of the light-emitting device is electrically connected to the signal output node or the node control sub-circuit, and the second electrode of the light-emitting device is electrically connected to the second power supply terminal.

[0086] When the light-emitting device group includes at least two light-emitting devices, the at least two light-emitting devices are connected in series, the first electrode of the first light-emitting device is electrically connected to the signal output node or the node control sub-circuit, and the second electrode of the last light-emitting device is electrically connected to the second power supply terminal.

[0087] In an exemplary embodiment, it further includes: multiple current source signal lines, multiple input control signal lines, and multiple hold control signal lines;

[0088] The current source signal terminals of pixel driving circuits located in the same column are connected to the same current source signal line;

[0089] At least one column of pixel driving circuits has its current source signal terminal connected to the same current source signal line;

[0090] The input control signal terminals of the pixel driving circuits located in the same row are connected to the same input control signal line;

[0091] The hold control signal terminals of the pixel driving circuits located in the same row are connected to the same hold control signal line.

[0092] In an exemplary embodiment, it further includes: a first data unit and a second data unit;

[0093] The first data unit is electrically connected to the input control signal line, and the second data unit is electrically connected to the hold control signal line;

[0094] The time when the first data unit provides an effective level signal to the input control signal line connected to the i-th row pixel driving circuit overlaps at least partially with the time when the second data unit provides an effective level signal to the hold control signal line connected to the i-th row pixel driving circuit. The time when the first data unit provides an effective level signal to the input control signal line connected to the i-th row pixel driving circuit is longer than the time when the second data unit provides an effective level signal to the hold control signal line connected to the i-th row pixel driving circuit, 1≤i≤N, where N is the total number of rows of the pixel driving circuit.

[0095] In an exemplary embodiment, the time during which the second data unit provides an effective level signal to the hold control signal line connected to the i-th row pixel driving circuit is within the time during which the first data unit provides an effective level signal to the input control signal line connected to the i-th row pixel driving circuit.

[0096] In an exemplary embodiment, the light-emitting device includes a micro light-emitting diode.

[0097] Thirdly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0098] In an exemplary embodiment, it includes: augmented reality glasses or a heads-up display.

[0099] Fourthly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0100] The signal input sub-circuit receives the first current signal from the current source signal terminal under the control of the input control signal terminal, the first power supply terminal, the first node, and the third node.

[0101] Under the control of the signal holding control terminal and the ground terminal, the signal holding sub-circuit provides the signal of the first node to the second node and the signal of the third node to the fourth node;

[0102] The signal output sub-circuit outputs a second current signal to the signal output node under the control of the signals from the second node, the fourth node, and the first power supply terminal.

[0103] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0104] Overview of the attached figures

[0105] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0106] Figure 1 is a schematic diagram of the pixel driving circuit;

[0107] Figure 2 is an equivalent circuit diagram of the pixel driving circuit;

[0108] Figure 3 shows another equivalent circuit diagram of the pixel driving circuit;

[0109] Figure 4 shows another equivalent circuit diagram of the pixel driving circuit;

[0110] Figure 5 is a timing diagram of the pixel driving circuit provided in Figure 4;

[0111] Figure 6 is a timing diagram of the pixel driving circuit provided in Figure 2;

[0112] Figure 7 is a timing diagram of the pixel driving circuit provided in Figure 3;

[0113] Figure 8 is another schematic diagram of the pixel driving circuit;

[0114] Figure 9 shows the equivalent circuit diagram of the pixel driving circuit.

[0115] Figure 10 shows the equivalent circuit diagram of the pixel driving circuit (II).

[0116] Figure 11 is the equivalent circuit diagram of the pixel driving circuit (Figure 3).

[0117] Figure 12 is the equivalent circuit diagram of the pixel driving circuit (Figure 4).

[0118] Figure 13 is the equivalent circuit diagram of the pixel driving circuit.

[0119] Figure 14 is the equivalent circuit diagram of the pixel driving circuit.

[0120] Figure 15 is a timing diagram of the pixel driving circuit provided in Figure 9;

[0121] Figure 16 is a timing diagram of the pixel driving circuit provided in Figure 10;

[0122] Figure 17 is a timing diagram of the pixel driving circuit provided in Figure 11;

[0123] Figure 18 is a timing diagram of the pixel driving circuit provided in Figure 12;

[0124] Figure 19 is a timing diagram of the pixel driving circuit provided in Figure 13;

[0125] Figure 20 is a timing diagram of the pixel driving circuit provided in Figure 14;

[0126] Figure 21 is a graph showing the error rates of Iref and Iout for the pixel driving circuit provided in Figure 4.

[0127] Figure 22 is a graph showing the error rates of Iref and Iout for the pixel driving circuit provided in Figure 2.

[0128] Figure 23 is a graph showing the error rates of Iref and Iout for the pixel driving circuit provided in Figure 3.

[0129] Figure 24 is a schematic diagram of the connection of the display substrate;

[0130] Figure 25 is a schematic diagram of the display substrate structure.

[0131] Detailed Explanation

[0132] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0133] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0134] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0135] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0136] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0137] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0138] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0139] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0140] The light-emitting devices in AR products are microLEDs. MicroLEDs can include micro light-emitting diodes (Micro LEDs) and mini light-emitting diodes (Mini LEDs), offering advantages such as small size and high brightness. They can be widely used in backlight modules of display devices. Displays using microLED backlights can achieve contrast levels comparable to organic light-emitting diode (OLED) displays, while retaining the technological advantages of liquid crystal displays (LCDs), thus enhancing the display effect and providing users with a superior visual experience. Furthermore, microLED displays are gradually becoming a hot topic in display panels, primarily used in AR / VR, TV, and outdoor displays.

[0141] AR products have high brightness requirements. To achieve high brightness, AR products require a large driving current. However, a large driving current results in a large voltage drop in the circuit, which reduces the brightness uniformity of the AR product and affects its display effect.

[0142] Therefore, this disclosure provides a pixel driving circuit. Figure 1 is a schematic diagram of the pixel driving circuit. As shown in Figure 1, the pixel driving circuit includes: a signal input sub-circuit, a signal holding sub-circuit, and a signal output sub-circuit.

[0143] As shown in Figure 1, the signal input sub-circuit is electrically connected to the input control signal terminal EM1, the current source signal terminal IREF, the first power supply terminal VDD, the first node N1, and the third node N3, respectively. It is configured to input the first current signal of the current source signal terminal IREF under the control of the signals of the input control signal terminal EM1, the first power supply terminal VDD, the first node N1, and the third node N3.

[0144] As shown in Figure 1, the signal holding sub-circuit is electrically connected to the holding control signal terminal EM2, the first node N1, the second node N2, the third node N3, the fourth node N4 and the ground terminal GND, respectively. It is configured to provide the signal of the first node N1 to the second node N2 and the signal of the third node N3 to the fourth node N4 under the control of the signals of the holding control signal terminal EM2 and the ground terminal GND.

[0145] As shown in Figure 1, the signal output sub-circuit is electrically connected to the first power supply terminal VDD, the second node N2, the fourth node N4 and the signal output node OUTN, respectively. It is configured to output a second current signal to the signal output node OUTN under the control of the signals of the second node N2, the fourth node N4 and the first power supply terminal VDD.

[0146] In an exemplary embodiment, the current value of the first current signal is equal to the current value of the second current signal.

[0147] In an exemplary embodiment, the pixel driving circuit is configured to drive a group of light-emitting devices. The group of light-emitting devices is electrically connected to the signal output node OUTN.

[0148] In an exemplary embodiment, the signal at the first current terminal VDD is a high-level signal.

[0149] This disclosure improves the brightness uniformity of AR products by coordinating the signal input sub-circuit, the signal holding sub-circuit, and the signal output sub-circuit to make the current value of the second current signal output by the pixel driving circuit equal to the current value of the signal at the current source signal terminal IREF.

[0150] Figure 2 shows an equivalent circuit diagram of the pixel driving circuit. As shown in Figure 2, the signal input sub-circuit includes: a first transistor M1, a third transistor M3, and a sixth transistor M6. Specifically, the control electrode of the first transistor M1 is electrically connected to the input control signal terminal EM1, the first electrode of the first transistor M1 is electrically connected to the current source signal terminal IREF, and the second electrode of the first transistor M1 is electrically connected to the third node N3. The control electrode and the second electrode of the third transistor M3 are respectively electrically connected to the first node N1, and the first electrode of the third transistor M3 is electrically connected to the first power supply terminal VDD. The control electrode and the second electrode of the sixth transistor M6 are respectively electrically connected to the third node N3, and the first electrode of the sixth transistor M6 is electrically connected to the first node N1.

[0151] As shown in Figure 2, the signal holding sub-circuit includes: a second transistor M2, a fifth transistor M5, a first capacitor C1, and a second capacitor C2. Specifically, the control electrode of the second transistor M2 is electrically connected to the holding control signal terminal EM2; the first electrode of the second transistor M2 is electrically connected to the first node N1; and the second electrode of the second transistor M2 is electrically connected to the second node N2. Similarly, the control electrode of the fifth transistor M5 is electrically connected to the holding control signal terminal EM2; the first electrode of the second transistor M2 is electrically connected to the third node N3; and the second electrode of the second transistor M2 is electrically connected to the fourth node N4. The first terminal of the first capacitor C1 is electrically connected to the second node N2; and the second terminal of the first capacitor C1 is electrically connected to the ground terminal GND. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4; and the second terminal of the second capacitor C2 is electrically connected to the ground terminal GND.

[0152] As shown in Figure 2, the signal output sub-circuit includes a fourth transistor M4 and a seventh transistor M7. The control electrode of the fourth transistor M4 is electrically connected to the second node N2, the first electrode of the fourth transistor M4 is electrically connected to the first power supply terminal VDD, and the second electrode of the fourth transistor M4 is electrically connected to the fifth node N5. Similarly, the control electrode of the seventh transistor M7 is electrically connected to the fourth node N4, the first electrode of the seventh transistor M7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor M7 is electrically connected to the signal output node OUTN.

[0153] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0154] For example, at least one of the first transistor M1 to the seventh transistor M7 can be a P-type transistor.

[0155] In an exemplary embodiment, at least one of the first transistors M1 to the seventh transistor M7 is a silicon-based complementary metal-oxide-semiconductor transistor.

[0156] In an exemplary embodiment, the device parameters of the third transistor M3 and the fourth transistor M4 are the same.

[0157] In an exemplary embodiment, the device parameters of the sixth transistor M6 are the same as those of the seventh transistor M7.

[0158] In an exemplary embodiment, the third transistor M3 and the fourth transistor M4 can form a current mirror pair, and the sixth transistor M6 and the seventh transistor M7 can also form a current mirror pair.

[0159] In an exemplary embodiment, as shown in FIG2, the second electrode of at least one of the first transistor M1 and the second transistor M2 can be the other electrode of the source electrode or the drain electrode; the first electrode of the third transistor M3 is the source electrode of the third transistor M3, and the second electrode of the third transistor M3 is the drain electrode of the third transistor M3; the first electrode of the fourth transistor M4 is the source electrode of the fourth transistor M4, and the second electrode of the fourth transistor M4 is the drain electrode of the fourth transistor M4; the first electrode of the fifth transistor M5 can be one of the source electrode or the drain electrode, and the second electrode of the fifth transistor M5 can be the other electrode of the source electrode or the drain electrode; the first electrode of the sixth transistor M6 can be the source electrode, and the second electrode of the sixth transistor M6 can be the drain electrode; the first electrode of the seventh transistor M7 can be the source electrode, and the second electrode of the seventh transistor M7 can be the drain electrode.

[0160] Figure 3 shows another equivalent circuit diagram of the pixel driving circuit. As shown in Figure 3, the signal input sub-circuit is also electrically connected to the node control signal terminal EM3 and is configured to provide the signal of the third node N3 to the first node N1 under the control of the signal of the node control signal terminal EM3.

[0161] In an exemplary embodiment, as shown in FIG3, the signal input sub-circuit includes: a first transistor M1, a third transistor M3, a sixth transistor M6, and an eighth transistor M8. The control electrode of the first transistor M1 is electrically connected to the input control signal terminal EM1, the first electrode of the first transistor M1 is electrically connected to the current source signal terminal IREF, and the second electrode of the first transistor M1 is electrically connected to the third node N3. The control electrode of the third transistor M3 is electrically connected to the first node N1, the first electrode of the third transistor M3 is electrically connected to the first power supply terminal VDD, and the second electrode of the third transistor M3 is electrically connected to the fifth node N5. The control electrode and the second electrode of the sixth transistor M6 are respectively electrically connected to the third node N3, and the first electrode of the sixth transistor M6 is electrically connected to the fifth node N5. The control electrode of the eighth transistor M8 is electrically connected to the node control signal terminal EM3, the first electrode of the eighth transistor M8 is electrically connected to the first node N1, and the second electrode of the eighth transistor M8 is electrically connected to the third node N3.

[0162] In an exemplary embodiment, as shown in FIG3, the signal holding sub-circuit includes: a second transistor M2, a fifth transistor M5, a first capacitor C1, and a second capacitor C2. The control electrode of the second transistor M2 is electrically connected to the holding control signal terminal EM2, the first electrode of the second transistor M2 is electrically connected to the first node N1, and the second electrode of the second transistor M2 is electrically connected to the second node N2. The control electrode of the fifth transistor M5 is electrically connected to the holding control signal terminal EM2, the first electrode of the fifth transistor M5 is electrically connected to the third node N3, and the second electrode of the fifth transistor M5 is electrically connected to the fourth node N4. The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the ground terminal GND. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the ground terminal GND.

[0163] In an exemplary embodiment, as shown in FIG3, the signal output sub-circuit includes a fourth transistor M4 and a seventh transistor M7. The control electrode and second electrode of the fourth transistor M4 are electrically connected to the second node N2, and the first electrode of the fourth transistor M4 is electrically connected to the first power supply terminal VDD. The control electrode of the seventh transistor M7 is electrically connected to the fourth node N4, the first electrode of the seventh transistor M7 is electrically connected to the second node N2, and the second electrode of the seventh transistor M7 is electrically connected to the signal output node OUTN.

[0164] In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0165] For example, at least one of the first transistor M1 to the eighth transistor M8 can be a P-type transistor.

[0166] In an exemplary embodiment, at least one of the first transistors M1 to the eighth transistor M8 is a silicon-based complementary metal-oxide-semiconductor transistor.

[0167] In an exemplary embodiment, the device parameters of the third transistor M3 and the fourth transistor M4 are the same.

[0168] In an exemplary embodiment, the device parameters of the sixth transistor M6 are the same as those of the seventh transistor M7.

[0169] In an exemplary embodiment, the third transistor M3 and the fourth transistor M4 can form a current mirror pair, and the sixth transistor M6 and the seventh transistor M7 can also form a current mirror pair.

[0170] In an exemplary embodiment, the pixel driving circuit provided in FIG3 can be referred to as a Wilson-type current mirror pixel driving circuit.

[0171] In an exemplary embodiment, as shown in FIG3, the first electrode of at least one of the first transistors M1 and M2 can be either the source electrode or the drain electrode, and the second electrode of at least one of the first transistors M1 and M2 can be either the source electrode or the drain electrode. The first electrode of the third transistor M3 is the source electrode of the third transistor M3, and the second electrode of the third transistor M3 is the drain electrode of the third transistor M3. The first electrode of the fourth transistor M4 is the source electrode of the fourth transistor M4, and the second electrode of the fourth transistor M4 is the drain electrode of the fourth transistor M4. The first electrode of the fifth transistor M5 can be either the source electrode or the drain electrode, and the second electrode of the fifth transistor M5 can be either the source electrode or the drain electrode. The first electrode of the sixth transistor M6 can be the source electrode, and the second electrode of the sixth transistor M6 can be the drain electrode. The first electrode of the seventh transistor M7 can be the source electrode, and the second electrode of the seventh transistor M7 can be the drain electrode. The first electrode of the eighth transistor M8 can be either the source electrode or the drain electrode, and the second electrode of the eighth transistor M8 can be either the source electrode or the drain electrode.

[0172] In an exemplary embodiment, Figure 4 is another equivalent circuit diagram of the pixel driving circuit. As shown in Figure 4, the signal input sub-circuit includes a first transistor M1 and a third transistor M3. The control electrode of the first transistor M1 is electrically connected to the input control signal terminal EM1, the first electrode of the first transistor M1 is electrically connected to the current source signal terminal IREF, and the second electrode of the first transistor M1 is electrically connected to the first node N1. The control electrode and the second electrode of the third transistor M3 are respectively electrically connected to the first node N1, and the first electrode of the third transistor M3 is electrically connected to the first power supply terminal VDD.

[0173] As shown in Figure 4, the signal holding sub-circuit includes a second transistor M2 and a first capacitor C1. The control terminal of the second transistor M2 is electrically connected to the holding control signal terminal EM2, the first terminal of the second transistor M2 is electrically connected to the first node N1, and the second terminal of the second transistor M2 is electrically connected to the second node N2. The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the ground terminal GND.

[0174] As shown in Figure 4, the signal output sub-circuit includes a fourth transistor M4. The control electrode of the fourth transistor M4 is electrically connected to the second node N2, the first electrode of the fourth transistor M4 is electrically connected to the first power supply terminal VDD, and the second electrode of the fourth transistor M4 is electrically connected to the signal output node OUTN.

[0175] The pixel driving circuit shown in Figure 4 can be called a current mirror pixel driving circuit. It can accurately copy the current value Iref of the first current signal at the current source signal terminal IREF to the signal output node OUTN, so that the current value Iout of the second current signal output by the signal output node OUTN is realized. This enables the light-emitting device group to be driven by the signal at the current source signal terminal. This disclosure can ensure that the second current signal output by the signal output node of at least one pixel driving circuit is the same by controlling the current source signal line, thereby ensuring the brightness uniformity of the AR product.

[0176] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0177] In an exemplary embodiment, the first transistor M1 to the fourth transistor M4 can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0178] For example, at least one of the first transistor M1 to the fourth transistor M4 can be a P-type transistor.

[0179] In an exemplary embodiment, at least one of the first transistors M1 to the fourth transistor M4 is a silicon-based complementary metal-oxide-semiconductor transistor.

[0180] In an exemplary embodiment, the device parameters of the third transistor M3 and the fourth transistor M4 are the same. These device parameters include: mobility, unit gate oxide capacitance, and the aspect ratio of the channel region.

[0181] In an exemplary embodiment, the third transistor M3 and the fourth transistor M4 can form a current mirror pair. The pixel driving circuit shown in Figure 3 can be a current mirror pixel driving circuit.

[0182] In an exemplary embodiment, as shown in FIG4, the first electrode of the third transistor M3 is the source electrode of the third transistor M3, and the second electrode of the third transistor M3 is the drain electrode of the third transistor M3. The first electrode of the fourth transistor M4 is the source electrode of the fourth transistor M4, and the second electrode of the fourth transistor M4 is the drain electrode of the fourth transistor M4. The first electrode of at least one of the first transistors M1 and M2 can be either the source electrode or the drain electrode, and the second electrode of at least one of the first transistors M1 and M2 can be either the source electrode or the drain electrode.

[0183] In an exemplary embodiment, the content displayed by the product includes multiple display frames.

[0184] Figure 5 is a timing diagram of the pixel driving circuit provided in Figure 4. The exemplary embodiments of this disclosure are described below using the operation of the exemplary pixel driving circuit in Figure 4. The pixel driving circuit provided in Figure 4 includes four transistors (first transistor M1 to fourth transistor M4) and one capacitor (first capacitor C1), all of which are P-type transistors.

[0185] In an exemplary embodiment, the operation of the pixel driving circuit in at least one display frame may include:

[0186] In the first stage P1, the initialization stage, the signal at the input control signal terminal EM1 is a low-level signal, while the signal at the control signal terminal EM2 remains a high-level signal. The first transistor M1 is turned on, and the second transistor M2 is turned off.

[0187] The first transistor M1 is turned on, and the signal at the current source signal terminal IREF is written into the first node N1. The third transistor M3 is turned on, and the first power supply terminal VDD, the third transistor M3, the first transistor M1, and the current source signal terminal IREF form a path. The signal flowing through the path is the first current signal, and the current value Iref of the first current signal is equal to the current value of the signal at the current source signal terminal IREF. During this stage, the voltage values ​​of the gate electrode and the drain electrode of the third transistor M3 are the same, and the third transistor M3 is in the constant current region. The current value Iref of the first current signal is equal to I... M3 =0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 I M3 V represents the current flowing through the third transistor, μ3 is the mobility of the third transistor, Cox3 is the capacitance per unit area of ​​the gate oxide layer of the third transistor, (W / L)3 is the aspect ratio of the channel region of the third transistor, and V GS3 V is the gate-source voltage difference of the third transistor. TH3 This is the threshold voltage of the third transistor.

[0188] In the second stage P2, the replication stage, the input control signal terminal EM1 and the holding control signal terminal EM2 are at a low level, and the first transistor M1 and the second transistor M2 are turned on.

[0189] The second transistor M2 is turned on, and the signal from the first node N1 is written to the second node N2. The fourth transistor M4 is then turned on. At this time, V... N1 =V N2 , where V N1 V is the voltage value of the signal at the first node N1. N2 The voltage value of the signal at the second node N2 is Vdd, meaning the gate electrode voltages of the third transistor M3 and the fourth transistor M4 are the same, and the source electrode voltages of both transistors M3 and M4 are Vdd, where Vdd is the voltage value of the signal at the first power supply terminal VDD. The voltage value of the signal at the signal output node OUTN is Vdd. N The following conditions must be met: V N -Vdd>V N2 -Vdd-V TH4 V TH4 The threshold voltage of the fourth transistor ensures that the fourth transistor M4 is in the constant current region. At this time, the current value Iout of the second current signal output by the signal output node OUTN satisfies the formula Iout = I M4 =0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 , among which, I M4 V is the current flowing through the fourth transistor, μ4 is the mobility of the fourth transistor, Cox4 is the capacitance per unit area of ​​the gate oxide layer of the fourth transistor, (W / L)4 is the aspect ratio of the channel region of the fourth transistor, and V GS4 V is the gate-source voltage difference of the fourth transistor. TH4 This is the threshold voltage of the fourth transistor.

[0190] Since the device parameters of the third transistor are the same as those of the fourth transistor (μ4 and μ3 are the same, Cox4 and Cox3 are the same, and (W / L)4 and (W / L)3 are the same), the gate voltage V of the third transistor M3 is... G3 and the gate electrode voltage V of the fourth transistor M4 G4 Equal, the source electrode voltage V of the third transistor S3 and the source electrode voltage V of the fourth transistor S4 Equal, the threshold voltage V of the third transistor TH3 and the threshold voltage V of the fourth transistor TH4 They are equal, according to the formula Iout = I M4=0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 and Iref=I M3 =0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 It can be seen that Iref = Iout, meaning that the current signal at the current source signal terminal IREF is copied to the signal output node OUTN.

[0191] In the third stage, P3, the holding stage, the signal at the input control signal terminal EM1 is a low-level signal, and the signal at the holding control signal terminal EM2 is a high-level signal. The first transistor M1 is turned on, and the second transistor M2 is turned off.

[0192] The first transistor M1 is turned on, and the signal at the first node N1 remains unchanged. The third transistor M3 remains on, and the second transistor M2 is turned off. The signal voltage value at the second node N2 is stored in the first capacitor C1 to maintain the stability of the signal at the second node N2. The fourth transistor M4 remains on, and the signal output node OUTN continuously outputs the second current signal. During this stage, at least one light-emitting device in the light-emitting device group emits light.

[0193] In the fourth stage, P4, the light-emitting and holding stage, the signals at the input control signal terminal EM1 and the holding control signal terminal EM2 are high-level signals. The first transistor M1 and the second transistor M2 are disconnected.

[0194] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, the fourth transistor M4 continues to conduct, the signal output node OUTN continuously outputs the second current signal, and at least one of the light-emitting devices in the light-emitting device group emits light.

[0195] As display technology continues to advance and transistor sizes shrink, the channel region of the transistor also shrinks, and the saturation current of the transistor becomes affected by the channel modulation effect. In the pixel driving circuit of Figure 3, the current values ​​Iref of the first current signal and Iout of the second current signal satisfy the following formula: Iref = I M3 =0.5*μ3Cox3*(W / L)3*(V GS3 -V TH3 ) 2 (1+λV DS3 Iout = I M4 =0.5*μ4Cox4*(W / L)4*(V GS4 -V TH4 ) 2 (1+λV DS4 )

[0196] As can be seen from the above formula, the current value Iref of the first current signal is also related to the source-drain voltage difference V of the third transistor. DS3 The current value Iout of the second current signal is also related to the source-drain voltage difference V of the fourth transistor. DS4 related,

[0197] Since the drain electrode of the third transistor M3 in the pixel driving circuit shown in Figure 4 is electrically connected to the DC source signal terminal, and the drain electrode of the fourth transistor M4 is electrically connected to the first electrode of the first light-emitting device in the light-emitting device group, the signal at the DC source signal terminal may be different from the signal at the first electrode of the first light-emitting device, thus causing V DS3 and V DS4 There is a gap, therefore, the pixel driving circuit shown in Figure 4 cannot reduce the influence of the channel modulation effect.

[0198] Figure 6 is a timing diagram of the pixel driving circuit provided in Figure 2. The exemplary embodiments of this disclosure are described below using the operation of the exemplary pixel driving circuit in Figure 2. The pixel driving circuit provided in Figure 2 includes seven transistors (first transistor M1 to seventh transistor M7) and two capacitors (first capacitor C1 and second capacitor C2), all of which are P-type transistors.

[0199] In an exemplary embodiment, the operation of the pixel driving circuit in at least one display frame may include:

[0200] In the first stage P1, the initialization stage, the signal at the input control signal terminal EM1 is a low-level signal, while the signal at the control signal terminal EM2 remains a high-level signal. The first transistor M1 is turned on, while the second transistor M2 and the fifth transistor M5 are turned off.

[0201] The first transistor M1 is turned on, and the signal at the current source signal terminal IREF is written into the third node N3. The sixth transistor M6 is turned on, and the signal at the third node N3 is written into the first node N1. The third transistor M3 is turned on, and the first power supply terminal VDD, the third transistor M3, the sixth transistor M6, the first transistor M1, and the current source signal terminal IREF form a path. The signal flowing through the path is the first current signal, and the current value Iref of the first current signal is equal to the current value of the signal at the current source signal terminal IREF. During this stage, the gate and drain voltages of either the third or sixth transistor are the same. Both the third transistor M3 and the sixth transistor M6 are in the constant current region, where the current value Iref of the first current signal is equal to I... M3 =I M6 =0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2=0.5*μ6*Cox6*(W / L)6*(V GS6 -V TH6 ) 2 I M3 V represents the current flowing through the third transistor, μ3 is the mobility of the third transistor, Cox3 is the capacitance per unit area of ​​the gate oxide layer of the third transistor, (W / L)3 is the aspect ratio of the channel region of the third transistor, and V GS3 V is the gate-source voltage difference of the third transistor. TH3 I is the threshold voltage of the third transistor. M6 I is the current flowing through the sixth transistor. M6 V represents the current flowing through the third transistor, μ6 is the mobility of the sixth transistor, Cox6 is the capacitance per unit area of ​​the gate oxide layer of the sixth transistor, (W / L)6 is the aspect ratio of the channel region of the sixth transistor, and V GS6 V is the gate-source voltage difference of the sixth transistor. TH6 This is the threshold voltage of the sixth transistor.

[0202] In the second stage P2, the replication stage, the input control signal terminal EM1 and the holding control signal terminal EM2 are at a low level, and the first transistor M1, the second transistor M2 and the fifth transistor M5 are turned on.

[0203] The second transistor M2 is turned on, and the signal from the first node N1 is written to the second node N2. The fourth transistor M4 is then turned on. At this time, V... N1 =V N2 , where V N1 V is the voltage value of the signal at the first node N1. N2 The voltage value of the signal at the second node N2 is given, the fifth transistor M5 is turned on, the signal at the third node N3 is written to the fourth node N4, the seventh transistor M7 is turned on, and at this time, V N3 =V N4 , where V N3 V is the voltage value of the signal at the third node N3. N4 Let N be the voltage value of the signal at the fourth node N4. At this time, the gate electrode voltages of the third transistor M3 and the fourth transistor M4 are the same, and the source electrode voltages of both the third transistor M3 and the fourth transistor M4 are Vdd, where Vdd is the voltage value of the signal at the first power supply terminal VDD. The current value Iout of the second current signal output by the signal output node OUTN satisfies the formula Iout = I M4 =I M7 =0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 =0.5*μ7*Cox7*(W / L)7*(V GS7 -VTH7 ) 2 , among which, I M4 V is the current flowing through the fourth transistor, μ4 is the mobility of the fourth transistor, Cox4 is the capacitance per unit area of ​​the gate oxide layer of the fourth transistor, (W / L)4 is the aspect ratio of the channel region of the fourth transistor, and V GS4 V is the gate-source voltage difference of the fourth transistor. TH4 I is the threshold voltage of the fourth transistor. M7 V is the current flowing through the seventh transistor, μ7 is the mobility of the seventh transistor, Cox7 is the capacitance per unit area of ​​the gate oxide layer of the seventh transistor, (W / L)7 is the width-to-length ratio of the channel region of the seventh transistor, and V GS7 V is the gate-source voltage difference of the seventh transistor. TH7 This is the threshold voltage of the seventh transistor.

[0204] The device parameters of the third transistor are the same as those of the fourth transistor; that is, μ4 is the same as μ3, Cox4 is the same as Cox3, and (W / L)4 is the same as (W / L)3. The gate voltage V of the third transistor M3 is... G3 and the gate electrode voltage V of the fourth transistor M4 G4 Equal, the source electrode voltage V of the third transistor M4 S3 and the source electrode voltage V of the fourth transistor M4 S4 Equal, the threshold voltage V of the third transistor TH3 and the threshold voltage V of the fourth transistor TH4 The gate-source voltage difference V of the third transistor M3 is equal. GS3 The gate-source voltage difference V with the fourth transistor GS4 Similarly, when (W / L)6 / (W / L)7 = (W / L)3 / (W / L)4, the gate-source voltage difference V of the sixth transistor M6... GS6 The gate-source voltage difference V with the seventh transistor M7 GS7 Similarly, the voltage values ​​of the signals at the first node N1 and the fifth node N5 are the same. Therefore, the source-drain voltage difference V of the third transistor is... DS3 The source-drain voltage difference V with the fourth transistor DS4 This eliminates the current replication error caused by the channel modulation effect in the pixel driving circuit, ensuring that the current value Iref of the first current signal is equal to the current value Iout of the second current signal, that is, the current signal at the current source signal terminal IREF can be accurately replicated to the signal output node OUTN.

[0205] In the third stage (P3), the holding stage, the signal at the input control signal terminal EM1 is a low-level signal, and the signal at the holding control signal terminal EM2 is a high-level signal. The first transistor M1 is turned on, while the second transistor M2 and the fifth transistor M5 are turned off.

[0206] The first transistor M1 is turned on, the signal at the third node N3 remains unchanged, the sixth transistor M6 is continuously turned on, the signal at the third node N3 is written into the first node N1, the third transistor M3 is continuously turned on, the second transistor M2 and the fifth transistor M5 are turned off, the signal voltage value at the second node N2 is stored in the first capacitor C1 to maintain the stability of the signal at the second node N2, the fourth transistor M4 is continuously turned on, the signal voltage value at the fourth node N4 is stored in the second capacitor C2 to maintain the stability of the signal at the fourth node N4, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal. During this stage, at least one light-emitting device in the light-emitting device group emits light.

[0207] In the fourth stage, P4, the light-emitting and holding stage, the signals at the input control signal terminal EM1 and the holding control signal terminal EM2 are high-level signals. The first transistor M1, the second transistor M2, and the fifth transistor M5 are disconnected.

[0208] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, the fourth transistor M4 continues to conduct, under the action of the second capacitor C2, the signal of the fourth node N4 remains unchanged, the seventh transistor M7 continues to conduct, the signal output node OUTN continuously outputs the second current signal, and at least one light-emitting device in the light-emitting device group emits light.

[0209] The sixth transistor M6 in the pixel driving circuit shown in Figure 2 shields the influence of the current source signal terminal on the drain electrode of the third transistor, and the seventh transistor M7 shields the influence of the first electrode of the first light-emitting device on the drain electrode of the fourth transistor, ensuring that the voltage of the drain electrode of the third transistor and the voltage of the drain electrode of the fourth transistor are the same. This enables the current signal at the current source signal terminal IREF to be accurately copied to the signal output node OUTN. The pixel driving circuit shown in Figure 2 eliminates the current copying error caused by the channel modulation effect in the pixel driving circuit.

[0210] Figure 7 is a timing diagram of the pixel driving circuit provided in Figure 3. The exemplary embodiments of this disclosure are described below using the operation of the exemplary pixel driving circuit in Figure 3. The pixel driving circuit provided in Figure 3 includes eight transistors (first transistor M1 to eighth transistor M8) and two capacitors (first capacitor C1 and second capacitor C2), all of which are P-type transistors.

[0211] In an exemplary embodiment, the operation of the pixel driving circuit in at least one display frame may include:

[0212] In the first stage P1, the initialization stage, the signals at the input control signal terminal EM1 and the node control signal terminal EM3 are low-level signals, while the signal at the control signal terminal EM2 remains high-level. The first transistor M1 and the eighth transistor M8 are turned on, while the second transistor M2 and the fifth transistor M5 are turned off.

[0213] The first transistor M1 is turned on, and the signal at the current source signal terminal IREF is written into the third node N3. The sixth transistor M6 is turned on, and the eighth transistor M8 is turned on. The signal at the third node N3 is written into the first node N1. The third transistor M3 is turned on, and the first power supply terminal VDD, the third transistor M3, the sixth transistor M6, the first transistor M1, and the current source signal terminal IREF form a path. The signal flowing through the path is the first current signal, and the current value Iref of the first current signal is equal to the current value of the signal at the current source signal terminal IREF. During this stage, the gate and drain voltages of either the third transistor or the sixth transistor are the same. Both the third transistor M3 and the sixth transistor M6 are in the constant current region, where the current value Iref of the first current signal is equal to I... M3 =I M6 =0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 *(1+λV DS3 )=0.5*μ6*Cox6*(W / L)6*(V GS6 -V TH6 ) 2 *(1+λV DS6 ), I M3 V represents the current flowing through the third transistor, μ3 is the mobility of the third transistor, Cox3 is the capacitance per unit area of ​​the gate oxide layer of the third transistor, (W / L)3 is the aspect ratio of the channel region of the third transistor, and V GS3 V is the gate-source voltage difference of the third transistor. DS3 V is the source-drain voltage difference of the third transistor. TH3 I is the threshold voltage of the third transistor. M6 V represents the current flowing through the sixth transistor, μ6 is the mobility of the sixth transistor, Cox6 is the capacitance per unit area of ​​the gate oxide layer of the sixth transistor, (W / L)6 is the aspect ratio of the channel region of the sixth transistor, and V GS6 V is the gate-source voltage difference of the sixth transistor. DS6 V is the source-drain voltage difference of the sixth transistor. TH6 This is the threshold voltage of the sixth transistor.

[0214] In the second stage P2, the replication stage, the input control signal terminal EM1 and the holding control signal terminal EM2 are low-level signals, the node control signal terminal EM3 is high-level signal, the first transistor M1, the second transistor M2 and the fifth transistor M5 are turned on, and the eighth transistor M8 is turned off.

[0215] The second transistor M2 is turned on, and the signal from the first node N1 is written to the second node N2. The fourth transistor M4 is then turned on. At this time, V... N1 =V N2 , where V N1 V is the voltage value of the signal at the first node N1. N2 The voltage value of the signal at the second node N2 is used to turn on the fifth transistor M5. The signal at the third node N3 is written to the fourth node N4, and the seventh transistor M7 is turned on. V N3 =V N4 At this time, V N3 V is the voltage value of the signal at the third node N3. N4 Let N be the voltage value of the signal at the fourth node N4. At this time, the gate electrode voltages of the third transistor M3 and the fourth transistor M4 are the same, and the source electrode voltages of the third transistor M3 and the fourth transistor M4 are both Vdd, where Vdd is the voltage value of the signal at the first power supply terminal. The current value Iout of the second current signal output by the signal output node OUTN satisfies the formula Iout = I M4 =I M7 =0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 *(1+λV DS4 )=0.5*μ7*Cox7*(W / L)7*(V GS7 -V TH7 ) 2 *(1+λV DS7 ), where I M4 V is the current flowing through the fourth transistor, μ4 is the mobility of the fourth transistor, Cox4 is the capacitance per unit area of ​​the gate oxide layer of the fourth transistor, (W / L)4 is the aspect ratio of the channel region of the fourth transistor, and V GS4 V is the gate-source voltage difference of the fourth transistor. DS4 V is the source-drain voltage difference of the fourth transistor. TH4 I is the threshold voltage of the fourth transistor. M7 V is the current flowing through the seventh transistor, μ7 is the mobility of the seventh transistor, Cox7 is the capacitance per unit area of ​​the gate oxide layer of the seventh transistor, (W / L)7 is the width-to-length ratio of the channel region of the seventh transistor, and V GS7 V is the gate-source voltage difference of the seventh transistor. DS7 V is the source-drain voltage difference of the seventh transistor.TH7 This is the threshold voltage of the seventh transistor.

[0216] The device parameters of the third transistor are the same as those of the fourth transistor; that is, μ4 is the same as μ3, Cox4 is the same as Cox3, and (W / L)4 is the same as (W / L)3. The gate voltage V of the third transistor M3 is... G3 and the gate electrode voltage V of the fourth transistor M4 G4 Equal, the source electrode voltage V of the third transistor M4 S3 and the source electrode voltage V of the fourth transistor M4 S4 Equal, the threshold voltage V of the third transistor TH3 and the threshold voltage V of the fourth transistor TH4 The gate-source voltage difference V of the third transistor M3 is equal. GS3 The gate-source voltage difference V with the fourth transistor GS4 Same. V DS3 =V GS7 +V GS4 -V GS6 When the gate-source voltage difference V of the sixth transistor M6 GS6 The gate-source voltage difference V with the seventh transistor M7 GS7 Same, has V DS3 =V GS4 =V DS4 According to the formula satisfied by the current values ​​of the first and second current signals, Iref / Iout=0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 *(1+λV DS3 ) / 0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 *(1+λV DS4 The pixel driving circuit provided in this disclosure eliminates the current replication error caused by the channel modulation effect in the pixel driving circuit, ensuring that the current value Iref of the first current signal is equal to the current value Iout of the second current signal, that is, the current signal of the current source signal terminal IREF can be accurately replicated to the signal output node OUTN.

[0217] In the third stage P3, the holding stage, the signal at the input control signal terminal EM1 is a low-level signal, while the signals at the holding control signal terminal EM2 and the node control signal terminal EM3 are high-level signals. The first transistor M1 is turned on, while the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are turned off.

[0218] The first transistor M1 is turned on, the signal at the third node N3 remains unchanged, the sixth transistor M6 is continuously turned on, the third transistor M3 is continuously turned on, the second transistor M2 and the fifth transistor M5 are turned off, the signal voltage value at the second node N2 is stored in the first capacitor C1 to maintain the stability of the signal at the second node N2, the fourth transistor M4 is continuously turned on, the signal voltage value at the fourth node N4 is stored in the second capacitor C2 to maintain the stability of the signal at the fourth node N4, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal. During this stage, at least one light-emitting device in the light-emitting device group emits light.

[0219] In the fourth stage, P4, the light-up holding stage, the input control signal terminal EM1, the holding control signal terminal EM2, and the node control signal terminal EM3 are all at a high level. The first transistor M1, the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are disconnected.

[0220] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, the fourth transistor M4 continues to conduct, under the action of the second capacitor C2, the signal of the fourth node N4 remains unchanged, the seventh transistor M7 continues to conduct, the signal output node OUTN continuously outputs the second current signal, and at least one light-emitting device in the light-emitting device group emits light.

[0221] In the pixel driving circuit shown in Figure 3, the sixth transistor M6 shields the influence of the current source signal terminal on the drain electrode of the third transistor, and the seventh transistor M7 shields the influence of the first electrode of the first light-emitting device on the drain electrode of the fourth transistor, ensuring that the voltage of the drain electrode of the third transistor and the voltage of the drain electrode of the fourth transistor are the same. This enables the current signal of the current source signal terminal IREF to be accurately copied to the signal output node OUTN, improving the reliability of the pixel driving circuit.

[0222] In an exemplary embodiment, as shown in Figures 2 to 4, the light-emitting device group includes at least one light-emitting device L, namely L1 to LK, where K is a positive integer greater than or equal to 1. Each light-emitting device includes a first electrode and a second electrode.

[0223] In an exemplary embodiment, when the light-emitting device group includes a light-emitting device, the first electrode of the light-emitting device is electrically connected to the signal output node OUTN, and the second electrode of the light-emitting device is electrically connected to the second power supply terminal VSS.

[0224] In an exemplary embodiment, when the light-emitting device group includes at least two light-emitting devices, the at least two light-emitting devices are arranged in series. The first electrode of the first light-emitting device is electrically connected to the signal output node OUTN, and the second electrode of the last light-emitting device is electrically connected to the second power supply terminal VSS.

[0225] In an exemplary embodiment, taking the pixel driving circuit shown in Figure 2 as an example, the power consumption of the light-emitting path (first power supply terminal, fourth transistor, and signal output node) of the pixel driving circuit is P = U * I = (Vdd - Vss) * Iout, where Iout is the current value of the second current signal, Vdd is the voltage value of the signal at the first power supply terminal VDD, and Vss is the voltage value of the signal at the second power supply terminal VSS. The power consumption of the fourth transistor M4 accounts for a percentage of P. M4 =V DS4 / (Vdd-Vss), V DS4 This represents the source-drain voltage difference of the fourth transistor. Therefore, the fourth transistor, M4, accounts for a relatively high proportion of power consumption. The light-emitting device group includes multiple light-emitting devices connected in series, which can increase the overall voltage of the light-emitting device group and reduce the power consumption of the fourth transistor in the pixel driving circuit.

[0226] In an exemplary embodiment, the light-emitting device may be a microLED.

[0227] Figure 8 shows another schematic diagram of the pixel driving circuit. As shown in Figure 8, the pixel driving circuit also includes a duration control sub-circuit. The light-emitting device group is electrically connected to the signal output node OUTN through the duration control sub-circuit, and the duration control sub-circuit is configured to provide the light-emitting device group with the second current signal output by the signal output node OUTN.

[0228] The duration control subcircuit in this disclosure can be configured to modulate the pulse width of the pixel driving circuit, thereby enabling precise control of the pixel driving circuit.

[0229] Figure 9 shows the equivalent circuit diagram of the pixel driving circuit (Figure 1), and Figure 10 shows the equivalent circuit diagram of the pixel driving circuit (Figure 2). As shown in Figures 9 and 10, the duration control sub-circuit may include: a ninth transistor M9, a tenth transistor M10, and a third capacitor C3. Specifically, the control electrode of the ninth transistor M9 is electrically connected to the sixth node N6, the first electrode of the ninth transistor M9 is electrically connected to the signal output node OUTN, and the second electrode of the ninth transistor M9 is electrically connected to the light-emitting device group; the control electrode of the tenth transistor M10 is electrically connected to the duration control signal terminal EM4, the first electrode of the tenth transistor M10 is electrically connected to the data signal terminal Data, and the second electrode of the tenth transistor M10 is electrically connected to the sixth node N6; the first terminal of the third capacitor C3 is electrically connected to the sixth node N6, and the second terminal of the third capacitor C3 is electrically connected to the common voltage terminal VCOM.

[0230] In an exemplary embodiment, at least one of the ninth transistor M9 and the tenth transistor M10 is a P-type transistor.

[0231] Figure 11 is the equivalent circuit diagram of the pixel driving circuit (Figure 3), and Figure 12 is the equivalent circuit diagram of the pixel driving circuit (Figure 4). As shown in Figures 11 and 12, in an exemplary embodiment, the duration control sub-circuit may include: the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15. Specifically, the control electrode of the ninth transistor M9 is electrically connected to the sixth node N6, the first electrode of the ninth transistor M9 is electrically connected to the signal output node OUTN, and the second electrode of the ninth transistor M9 is electrically connected to the light-emitting device group; the control electrode of the tenth transistor M10 is electrically connected to the seventh node N7, the first electrode of the tenth transistor M10 is electrically connected to the first power supply terminal VDD, and the second electrode of the tenth transistor M10 is electrically connected to the sixth node N6; the control electrode of the eleventh transistor M11 is electrically connected to the seventh node N7, the first electrode of the eleventh transistor M11 is electrically connected to the ground terminal GND, and the second electrode of the eleventh transistor M11 is electrically connected to the sixth node N6; the control electrode of the twelfth transistor M12 is electrically connected to the sixth node N6, and the first electrode of the twelfth transistor M12 is electrically connected to the first power supply terminal VDD. The connections are as follows: the second terminal of the twelfth transistor M12 is electrically connected to the seventh node N7; the control terminal of the thirteenth transistor M13 is electrically connected to the sixth node N6, the first terminal of the thirteenth transistor M13 is electrically connected to the ground terminal GND, and the second terminal of the thirteenth transistor M13 is electrically connected to the seventh node N7; the control terminal of the fourteenth transistor M14 is electrically connected to the duration control signal terminal EM4, the first terminal of the fourteenth transistor M14 is electrically connected to the first data signal terminal Data1, and the second terminal of the fourteenth transistor M14 is electrically connected to the sixth node N6; the control terminal of the fifteenth transistor M15 is electrically connected to the duration control signal terminal EM4, the first terminal of the fifteenth transistor M15 is electrically connected to the second data signal terminal Data2, and the second terminal of the fifteenth transistor M15 is electrically connected to the seventh node N7.

[0232] In an exemplary embodiment, the tenth transistor M10 and the eleventh transistor M11 are of different transistor types. For example, the tenth transistor M10 can be a P-type transistor, and the eleventh transistor M11 can be an N-type transistor.

[0233] In an exemplary embodiment, the twelfth transistor M12 and the thirteenth transistor M13 are of different transistor types. For example, the twelfth transistor M12 can be a P-type transistor, and the thirteenth transistor M13 can be an N-type transistor.

[0234] In an exemplary embodiment, at least one of the fourteenth transistor M14 and the fifteenth transistor M15 is an N-type transistor, and the ninth transistor M9 is a P-type transistor.

[0235] In an exemplary embodiment, the signal of the first data signal terminal Data1 and the signal of the second data signal terminal Data2 are at least partially opposite signals for a certain period of time.

[0236] In an exemplary embodiment, Figure 13 is an equivalent circuit diagram of the pixel driving circuit (Figure 5), and Figure 14 is an equivalent circuit diagram of the pixel driving circuit (Figure 6). As shown in Figures 13 and 14, the duration control sub-circuit may include: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a third capacitor C3. Specifically, the control electrode of the ninth transistor M9 is electrically connected to the sixth node N6, the first electrode of the ninth transistor M9 is electrically connected to the signal output node OUTN, and the second electrode of the ninth transistor M9 is electrically connected to the light-emitting device group; the control electrode of the tenth transistor M10 is electrically connected to the seventh node N7, the first electrode of the tenth transistor M10 is electrically connected to the high-frequency signal terminal Hf, and the second electrode of the tenth transistor M10 is electrically connected to the sixth node N6; the control electrode of the eleventh transistor M11 is electrically connected to the seventh node N7, the first electrode of the eleventh transistor M11 is electrically connected to the duration control signal terminal EM4, and the second electrode of the eleventh transistor M11 is electrically connected to the sixth node N6; the control electrode of the twelfth transistor M12 is electrically connected to the scan signal terminal Gate, the first electrode of the twelfth transistor M12 is electrically connected to the data signal terminal Data, and the second electrode of the twelfth transistor M12 is electrically connected to the seventh node N7; the first terminal of the third capacitor C3 is electrically connected to the seventh node N7, and the second terminal of the third capacitor C3 is electrically connected to the common voltage terminal VCOM.

[0237] In an exemplary embodiment, the tenth transistor M10 and the eleventh transistor M11 have opposite transistor types. For example, the tenth transistor M10 can be a P-type transistor, and the eleventh transistor M11 can be an N-type transistor.

[0238] In an exemplary embodiment, at least one of the ninth transistor M9 and the twelfth transistor M12 is a P-type transistor.

[0239] In the exemplary embodiments, the signal input sub-circuit, signal holding sub-circuit, and signal output sub-circuit in the pixel driving circuits provided in FIG. 9, 11, and 13 are described using the signal input sub-circuit, signal holding sub-circuit, and signal output sub-circuit in FIG. 2 as examples. The signal input sub-circuit, signal holding sub-circuit, and signal output sub-circuit in the pixel driving circuits provided in FIG. 10, 12, and 14 are described using the signal input sub-circuit, signal holding sub-circuit, and signal output sub-circuit in FIG. 3 as examples, and this disclosure does not impose any limitations on them.

[0240] Figure 15 is a timing diagram of the pixel driving circuit provided in Figure 9. The exemplary embodiments of this disclosure are described below using the working process of the exemplary pixel driving circuit in Figure 9. The pixel driving circuit provided in Figure 9 includes nine transistors (first transistor M1 to seventh transistor M7, ninth transistor M9, and tenth transistor M10) and three capacitors (first capacitor C1, second capacitor C2, and third capacitor C3). All nine transistors are P-type transistors.

[0241] At least one display frame includes multiple display subframes. Figure 15 illustrates an example where a display frame includes three display subframes S1 to S3.

[0242] In an exemplary embodiment, the operation of the pixel driving circuit in at least one display subframe may include:

[0243] In the first stage P1, the signal at the duration control signal terminal EM4 is a low-level signal, while the signals at the input control signal terminal EM1 and the hold control signal terminal EM2 are high-level signals. The tenth transistor M10 is turned on, while the first transistor M1, the second transistor M2, and the fifth transistor M5 are turned off.

[0244] When the tenth transistor M10 is turned on, the high-level signal of the data signal terminal Data is written to the sixth node N6. When the ninth transistor M9 is turned off, the voltage value of the signal at the sixth node N6 is stored in the third capacitor C3.

[0245] In the second stage P2, the current signal writing stage, the signals of the input control signal terminal EM1, the holding control signal terminal EM2, and the duration control signal terminal EM4 are low-level signals, and the first transistor M1, the second transistor M2, the fifth transistor M5, and the tenth transistor M10 are turned on.

[0246] The first transistor M1 is turned on, and the signal at the current source signal terminal IREF is written into the third node N3. The sixth transistor M6 is turned on, and the signal at the third node N3 is written into the first node N1. The third transistor M3 is turned on, and the first power supply terminal VDD, the third transistor M3, the sixth transistor M6, the first transistor M1, and the current source signal terminal IREF form a path. The signal flowing through the path is the first current signal, and the current value Iref of the first current signal is equal to the current value of the signal at the current source signal terminal IREF. During this stage, the gate and drain voltages of either the third or sixth transistor are the same. Both the third transistor M3 and the sixth transistor M6 are in the constant current region, where the current value Iref of the first current signal is equal to I... M3 =I M6 =0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2=0.5*μ6*Cox6*(W / L)6*(V GS6 -V TH6 ) 2 I M3 V represents the current flowing through the third transistor, μ3 is the mobility of the third transistor, Cox3 is the capacitance per unit area of ​​the gate oxide layer of the third transistor, (W / L)3 is the aspect ratio of the channel region of the third transistor, and V GS3 V is the gate-source voltage difference of the third transistor. TH3 I is the threshold voltage of the third transistor. M6 I is the current flowing through the sixth transistor. M6 V represents the current flowing through the third transistor, μ6 is the mobility of the sixth transistor, Cox6 is the capacitance per unit area of ​​the gate oxide layer of the sixth transistor, (W / L)6 is the aspect ratio of the channel region of the sixth transistor, and V GS6 V is the gate-source voltage difference of the sixth transistor. TH6 This is the threshold voltage of the sixth transistor.

[0247] The second transistor M2 is turned on, and the signal from the first node N1 is written to the second node N2. The fourth transistor M4 is then turned on. At this time, V... N1 =V N2 , where V N1 V is the voltage value of the signal at the first node N1. N2 The voltage value of the signal at the second node N2 is given, the fifth transistor M5 is turned on, the signal at the third node N3 is written to the fourth node N4, the seventh transistor M7 is turned on, and at this time, V N3 =V N4 , where V N3 V is the voltage value of the signal at the third node N3. N4 Let N be the voltage value of the signal at the fourth node N4. At this time, the gate electrode voltages of the third transistor M3 and the fourth transistor M4 are the same, and the source electrode voltages of both the third transistor M3 and the fourth transistor M4 are Vdd, where Vdd is the voltage value of the signal at the first power supply terminal VDD. The current value Iout of the second current signal output by the signal output node OUTN satisfies the formula Iout = I M4 =I M7 =0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 =0.5*μ7*Cox7*(W / L)7*(V GS7 -V TH7 ) 2 , among which, I M4V is the current flowing through the fourth transistor, μ4 is the mobility of the fourth transistor, Cox4 is the capacitance per unit area of ​​the gate oxide layer of the fourth transistor, (W / L)4 is the aspect ratio of the channel region of the fourth transistor, and V GS4 V is the gate-source voltage difference of the fourth transistor. TH4 I is the threshold voltage of the fourth transistor. M7 V is the current flowing through the seventh transistor, μ7 is the mobility of the seventh transistor, Cox7 is the capacitance per unit area of ​​the gate oxide layer of the seventh transistor, (W / L)7 is the width-to-length ratio of the channel region of the seventh transistor, and V GS7 V is the gate-source voltage difference of the seventh transistor. TH7 This is the threshold voltage of the seventh transistor.

[0248] The device parameters of the third transistor are the same as those of the fourth transistor; that is, μ4 is the same as μ3, Cox4 is the same as Cox3, and (W / L)4 is the same as (W / L)3. The gate voltage V of the third transistor M3 is... G3 and the gate electrode voltage V of the fourth transistor M4 G4 Equal, the source electrode voltage V of the third transistor M4 S3 and the source electrode voltage V of the fourth transistor M4 S4 Equal, the threshold voltage V of the third transistor TH3 and the threshold voltage V of the fourth transistor TH4 The gate-source voltage difference V of the third transistor M3 is equal. GS3 The gate-source voltage difference V with the fourth transistor GS4 Similarly, when (W / L)6 / (W / L)7 = (W / L)3 / (W / L)4, the gate-source voltage difference V of the sixth transistor M6... GS6 The gate-source voltage difference V with the seventh transistor M7 GS7 Similarly, the voltage values ​​of the signals at the first node N1 and the fifth node N5 are the same. Therefore, the source-drain voltage difference V of the third transistor is... DS3 The source-drain voltage difference V with the fourth transistor DS4 This eliminates the current replication error caused by the channel modulation effect in the pixel driving circuit, ensuring that the current value Iref of the first current signal is equal to the current value Iout of the second current signal, that is, the current signal at the current source signal terminal IREF can be accurately replicated to the signal output node OUTN.

[0249] The tenth transistor M10 remains on, and the high-level signal of the data signal terminal Data is continuously written to the sixth node N6. The ninth transistor M9 is off, and the voltage value of the signal at the sixth node N6 is stored in the third capacitor C3.

[0250] In the third stage, P3, the pulse signal writing stage, the signals at the input control signal terminal EM1 and the duration control signal terminal EM4 are low-level signals, while the signal at the control signal terminal EM2 remains high-level. The first transistor M1 and the tenth transistor M10 are turned on, while the second transistor M2 and the fifth transistor M5 are turned off.

[0251] The first transistor M1 is turned on, the signal at the third node N3 remains unchanged, the sixth transistor M6 is continuously turned on, the signal at the third node N3 is written into the first node N1, the third transistor M3 is continuously turned on, the second transistor M2 and the fifth transistor M5 are turned off, the signal voltage value at the second node N2 is stored in the first capacitor C1 to maintain the stability of the signal at the second node N2, the fourth transistor M4 is continuously turned on, the signal voltage value at the fourth node N4 is stored in the second capacitor C2 to maintain the stability of the signal at the fourth node N4, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal. During this stage, at least one light-emitting device in the light-emitting device group emits light.

[0252] The tenth transistor M10 is continuously turned on, and the data signal at the data signal terminal Data is written to the sixth node N6. The ninth transistor M9 is turned on or off, and the voltage value of the signal at the sixth node N6 is stored in the third capacitor C3.

[0253] In the fourth stage, P4, the light-up holding stage, the signals at the input control signal terminal EM1, the holding control signal terminal EM2, and the duration control signal terminal EM4 are high-level signals. The first transistor M1, the second transistor M2, the fifth transistor M5, and the tenth transistor M10 are disconnected.

[0254] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, and the fourth transistor M4 is turned on. Under the action of the second capacitor C2, the signal of the fourth node N4 remains unchanged, and the seventh transistor M7 continues to be turned on. The signal output node OUTN continuously outputs the second current signal. Under the action of the third capacitor C3, the signal of the sixth node N6 remains unchanged. The conduction state of the ninth transistor M9 depends on the data signal written at the data signal terminal. When the data signal written at the data signal terminal is a low-level signal, the ninth transistor M9 is turned on, and the second current signal is provided to the light-emitting device group. At least one light-emitting device in the light-emitting device group emits light. When the data signal written at the data signal terminal is a high-level signal, the ninth transistor M9 is turned off, the second current signal cannot be provided to the light-emitting device group, and the light-emitting device group does not emit light.

[0255] Figure 16 is a timing diagram of the pixel driving circuit provided in Figure 10. The exemplary embodiments of this disclosure are described below using the operation of the exemplary pixel driving circuit in Figure 10. The pixel driving circuit provided in Figure 9 includes ten transistors (first transistor M1 to eighth transistor M8, ninth transistor M9, and tenth transistor M10) and three capacitors (first capacitor C1, second capacitor C2, and third capacitor C3), all of which are P-type transistors.

[0256] At least one display frame includes multiple display subframes. Figure 16 illustrates an example where a display frame includes three display subframes S1 to S3.

[0257] In an exemplary embodiment, the operation of the pixel driving circuit in at least one display subframe may include:

[0258] In the first stage P1, the signal at the duration control signal terminal EM4 is a low-level signal, while the signals at the input control signal terminal EM1, the hold control signal terminal EM2, and the node control signal terminal EM3 are high-level signals. The tenth transistor M10 is turned on, while the first transistor M1, the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are turned off.

[0259] When the tenth transistor M10 is turned on, the high-level signal of the data signal terminal Data is written to the sixth node N6. When the ninth transistor M9 is turned off, the voltage value of the signal at the sixth node N6 is stored in the third capacitor C3.

[0260] In the second stage P2, the current signal writing stage, the signals of the input control signal terminal EM1, the holding control signal terminal EM2, the node control signal terminal EM3, and the duration control signal terminal EM4 are low-level signals, and the first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, and the tenth transistor M10 are turned on.

[0261] The first transistor M1 is turned on, and the signal at the current source signal terminal IREF is written into the third node N3. The sixth transistor M6 is turned on, and the eighth transistor M8 is turned on. The signal at the third node N3 is written into the first node N1. The third transistor M3 is turned on, and the first power supply terminal VDD, the third transistor M3, the sixth transistor M6, the first transistor M1, and the current source signal terminal IREF form a path. The signal flowing through the path is the first current signal, and the current value Iref of the first current signal is equal to the current value of the signal at the current source signal terminal IREF. During this stage, the gate and drain voltages of either the third transistor or the sixth transistor are the same. Both the third transistor M3 and the sixth transistor M6 are in the constant current region, where the current value Iref of the first current signal is equal to I... M3 =I M6 =0.5*μ3*Cox3*(W / L)3*(VGS3 -V TH3 ) 2 *(1+λV DS3 )=0.5*μ6*Cox6*(W / L)6*(V GS6 -V TH6 ) 2 *(1+λV DS6 ), I M3 V represents the current flowing through the third transistor, μ3 is the mobility of the third transistor, Cox3 is the capacitance per unit area of ​​the gate oxide layer of the third transistor, (W / L)3 is the aspect ratio of the channel region of the third transistor, and V GS3 V is the gate-source voltage difference of the third transistor. DS3 V is the source-drain voltage difference of the third transistor. TH3 I is the threshold voltage of the third transistor. M6 V represents the current flowing through the sixth transistor, μ6 is the mobility of the sixth transistor, Cox6 is the capacitance per unit area of ​​the gate oxide layer of the sixth transistor, (W / L)6 is the aspect ratio of the channel region of the sixth transistor, and V GS6 V is the gate-source voltage difference of the sixth transistor. DS6 V is the source-drain voltage difference of the sixth transistor. TH6 This is the threshold voltage of the sixth transistor.

[0262] The second transistor M2 is turned on, and the signal from the first node N1 is written to the second node N2. The fourth transistor M4 is then turned on. At this time, V... N1 =V N2 , where V N1 V is the voltage value of the signal at the first node N1. N2 The voltage value of the signal at the second node N2 is used to turn on the fifth transistor M5. The signal at the third node N3 is written to the fourth node N4, and the seventh transistor M7 is turned on. V N3 =V N4 At this time, V N3 V is the voltage value of the signal at the third node N3. N4 Let N be the voltage value of the signal at the fourth node N4. At this time, the gate electrode voltages of the third transistor M3 and the fourth transistor M4 are the same, and the source electrode voltages of the third transistor M3 and the fourth transistor M4 are both Vdd, where Vdd is the voltage value of the signal at the first power supply terminal. The current value Iout of the second current signal output by the signal output node OUTN satisfies the formula Iout = I M4 =I M7 =0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 *(1+λV DS4)=0.5*μ7*Cox7*(W / L)7*(V GS7 -V TH7 ) 2 *(1+λV DS7 ), where I M4 V is the current flowing through the fourth transistor, μ4 is the mobility of the fourth transistor, Cox4 is the capacitance per unit area of ​​the gate oxide layer of the fourth transistor, (W / L)4 is the aspect ratio of the channel region of the fourth transistor, and V GS4 V is the gate-source voltage difference of the fourth transistor. DS4 V is the source-drain voltage difference of the fourth transistor. TH4 I is the threshold voltage of the fourth transistor. M7 V is the current flowing through the seventh transistor, μ7 is the mobility of the seventh transistor, Cox7 is the capacitance per unit area of ​​the gate oxide layer of the seventh transistor, (W / L)7 is the width-to-length ratio of the channel region of the seventh transistor, and V GS7 V is the gate-source voltage difference of the seventh transistor. DS7 V is the source-drain voltage difference of the seventh transistor. TH7 This is the threshold voltage of the seventh transistor.

[0263] The device parameters of the third transistor are the same as those of the fourth transistor; that is, μ4 is the same as μ3, Cox4 is the same as Cox3, and (W / L)4 is the same as (W / L)3. The gate voltage V of the third transistor M3 is... G3 and the gate electrode voltage V of the fourth transistor M4 G4 Equal, the source electrode voltage V of the third transistor M4 S3 and the source electrode voltage V of the fourth transistor M4 S4 Equal, the threshold voltage V of the third transistor TH3 and the threshold voltage V of the fourth transistor TH4 The gate-source voltage difference V of the third transistor M3 is equal. GS3 The gate-source voltage difference V with the fourth transistor GS4 Same. V DS3 =V GS7 +V GS4 -V GS6 When the gate-source voltage difference V of the sixth transistor M6 GS6 The gate-source voltage difference V with the seventh transistor M7 GS7 Same, has V DS3 =V GS4 =V DS4 According to the formula satisfied by the current values ​​of the first and second current signals, Iref / Iout=0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2*(1+λV DS3 ) / 0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 *(1+λV DS4 The pixel driving circuit provided in this disclosure eliminates the current replication error caused by the channel modulation effect in the pixel driving circuit, ensuring that the current value Iref of the first current signal is equal to the current value Iout of the second current signal, that is, the current signal of the current source signal terminal IREF can be accurately replicated to the signal output node OUTN.

[0264] The tenth transistor M10 remains on, and the high-level signal of the data signal terminal Data is continuously written to the sixth node N6. The ninth transistor M9 is off, and the voltage value of the signal at the sixth node N6 is stored in the third capacitor C3.

[0265] In the third stage, P3, the pulse signal writing stage, the signals at the input control signal terminal EM1 and the duration control signal terminal EM4 are low-level signals, while the signals at the control signal terminal EM2 and the duration control signal terminal EM3 are high-level signals. The first transistor M1 and the tenth transistor M10 are turned on, while the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are turned off.

[0266] The first transistor M1 is turned on, the signal at the third node N3 remains unchanged, the sixth transistor M6 is continuously turned on, the first node N1 maintains the signal from the previous stage, the third transistor M3 is continuously turned on, the second transistor M2 and the fifth transistor M5 are turned off, the signal voltage value at the second node N2 is stored in the first capacitor C1 to maintain the stability of the signal at the second node N2, the fourth transistor M4 is continuously turned on, the signal voltage value at the fourth node N4 is stored in the second capacitor C2 to maintain the stability of the signal at the fourth node N4, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal. In this stage, at least one light-emitting device in the light-emitting device group emits light.

[0267] The tenth transistor M10 is continuously turned on, and the data signal at the data signal terminal Data is written to the sixth node N6. The ninth transistor M9 is turned on or off, and the voltage value of the signal at the sixth node N6 is stored in the third capacitor C3.

[0268] In the fourth stage, P4, the light-up holding stage, the signals at the input control signal terminal EM1, the holding control signal terminal EM2, the node control signal terminal EM3, and the duration control signal terminal EM4 are all high-level signals. The first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, and the tenth transistor M10 are disconnected.

[0269] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, and the fourth transistor M4 is turned on. Under the action of the second capacitor C2, the signal of the fourth node N4 remains unchanged, and the seventh transistor M7 continues to be turned on. The signal output node OUTN continuously outputs the second current signal. Under the action of the third capacitor C3, the signal of the sixth node N6 remains unchanged. The conduction state of the ninth transistor M9 depends on the data signal written at the data signal terminal. When the data signal written at the data signal terminal is a low-level signal, the ninth transistor M9 is turned on, and the second current signal is provided to the light-emitting device group. At least one light-emitting device in the light-emitting device group emits light. When the data signal written at the data signal terminal is a high-level signal, the ninth transistor M9 is turned off, the second current signal cannot be provided to the light-emitting device group, and the light-emitting device group does not emit light.

[0270] Figure 17 is a timing diagram of the pixel driving circuit provided in Figure 11. The exemplary embodiments of this disclosure are described below using the operation of the exemplary pixel driving circuit in Figure 11. The pixel driving circuit provided in Figure 11 includes: fourteen transistors (first transistor M1 to seventh transistor M7, ninth transistor M9 to fifteenth transistor M15) and three capacitors (first capacitor C1, second capacitor C2, and third capacitor C3). First transistors M1 to seventh transistor M7, ninth transistor M9, tenth transistor M10, and twelfth transistor M12 are P-type transistors, while eleventh transistor M11, thirteenth transistor M13, fourteenth transistor M14, and fifteenth transistor M15 are N-type transistors.

[0271] In an exemplary embodiment, the operation of the pixel driving circuit in at least one display frame may include:

[0272] In the first stage P1, the signals at the input control signal terminal EM1, the hold control signal terminal EM2, and the duration control signal terminal EM4 are all high-level signals. The fourteenth transistor M14 and the fifteenth transistor M15 are turned on, while the first transistor M1, the second transistor M2, and the fifth transistor M5 are turned off.

[0273] The fourteenth transistor M14 is turned on, and the high-level signal of the first data signal terminal Data1 is written to the sixth node N6. The ninth transistor M9 and the twelfth transistor M12 are turned off. The thirteenth transistor M13 is turned on, and the low-level signal of the ground terminal GND is written to the seventh node N7. The low-level signal of the second data signal terminal Data2 is written to the seventh node N7. The eleventh transistor M11 is turned off, and the tenth transistor M10 is turned on. The high-level signal of the first power supply terminal VDD is continuously written to the sixth node.

[0274] In the second stage P2, the current signal writing stage, the signals at the input control signal terminal EM1 and the holding control signal terminal EM2 are low-level signals, and the signal at the duration control signal terminal EM4 is high-level signal. The first transistor M1, the second transistor M2, the fifth transistor M5, the fourteenth transistor M14, and the fifteenth transistor M15 are turned on.

[0275] The first transistor M1 is turned on, and the signal at the current source signal terminal IREF is written into the third node N3. The sixth transistor M6 is turned on, and the signal at the third node N3 is written into the first node N1. The third transistor M3 is turned on, and the first power supply terminal VDD, the third transistor M3, the sixth transistor M6, the first transistor M1, and the current source signal terminal IREF form a path. The signal flowing through the path is the first current signal, and the current value Iref of the first current signal is equal to the current value of the signal at the current source signal terminal IREF. During this stage, the gate and drain voltages of either the third or sixth transistor are the same. Both the third transistor M3 and the sixth transistor M6 are in the constant current region, where the current value Iref of the first current signal is equal to I... M3 =I M6 =0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 =0.5*μ6*Cox6*(W / L)6*(V GS6 -V TH6 ) 2 I M3 V represents the current flowing through the third transistor, μ3 is the mobility of the third transistor, Cox3 is the capacitance per unit area of ​​the gate oxide layer of the third transistor, (W / L)3 is the aspect ratio of the channel region of the third transistor, and V GS3 V is the gate-source voltage difference of the third transistor. TH3 I is the threshold voltage of the third transistor. M6 I is the current flowing through the sixth transistor. M6 V represents the current flowing through the third transistor, μ6 is the mobility of the sixth transistor, Cox6 is the capacitance per unit area of ​​the gate oxide layer of the sixth transistor, (W / L)6 is the aspect ratio of the channel region of the sixth transistor, and V GS6 V is the gate-source voltage difference of the sixth transistor. TH6 This is the threshold voltage of the sixth transistor.

[0276] The second transistor M2 is turned on, and the signal from the first node N1 is written to the second node N2. The fourth transistor M4 is then turned on. At this time, V... N1 =V N2 , where V N1 V is the voltage value of the signal at the first node N1. N2The voltage value of the signal at the second node N2 is given, the fifth transistor M5 is turned on, the signal at the third node N3 is written to the fourth node N4, the seventh transistor M7 is turned on, and at this time, V N3 =V N4 , where V N3 V is the voltage value of the signal at the third node N3. N4 Let N be the voltage value of the signal at the fourth node N4. At this time, the gate electrode voltages of the third transistor M3 and the fourth transistor M4 are the same, and the source electrode voltages of both the third transistor M3 and the fourth transistor M4 are Vdd, where Vdd is the voltage value of the signal at the first power supply terminal VDD. The current value Iout of the second current signal output by the signal output node OUTN satisfies the formula Iout = I M4 =I M7 =0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 =0.5*μ7*Cox7*(W / L)7*(V GS7 -V TH7 ) 2 , among which, I M4 V is the current flowing through the fourth transistor, μ4 is the mobility of the fourth transistor, Cox4 is the capacitance per unit area of ​​the gate oxide layer of the fourth transistor, (W / L)4 is the aspect ratio of the channel region of the fourth transistor, and V GS4 V is the gate-source voltage difference of the fourth transistor. TH4 I is the threshold voltage of the fourth transistor. M7 V is the current flowing through the seventh transistor, μ7 is the mobility of the seventh transistor, Cox7 is the capacitance per unit area of ​​the gate oxide layer of the seventh transistor, (W / L)7 is the width-to-length ratio of the channel region of the seventh transistor, and V GS7 V is the gate-source voltage difference of the seventh transistor. TH7 This is the threshold voltage of the seventh transistor.

[0277] The device parameters of the third transistor are the same as those of the fourth transistor; that is, μ4 is the same as μ3, Cox4 is the same as Cox3, and (W / L)4 is the same as (W / L)3. The gate voltage V of the third transistor M3 is... G3 and the gate electrode voltage V of the fourth transistor M4 G4 Equal, the source electrode voltage V of the third transistor M4 S3 and the source electrode voltage V of the fourth transistor M4 S4 Equal, the threshold voltage V of the third transistor TH3 and the threshold voltage V of the fourth transistor TH4 The gate-source voltage difference V of the third transistor M3 is equal. GS3 The gate-source voltage difference V with the fourth transistorGS4 Similarly, when (W / L)6 / (W / L)7 = (W / L)3 / (W / L)4, the gate-source voltage difference V of the sixth transistor M6... GS6 The gate-source voltage difference V with the seventh transistor M7 GS7 Similarly, the voltage values ​​of the signals at the first node N1 and the fifth node N5 are the same. Therefore, the source-drain voltage difference V of the third transistor is... DS3 The source-drain voltage difference V with the fourth transistor DS4 Similarly, this eliminates the current replication error caused by the channel modulation effect in the pixel driving circuit, ensuring that the current value Iref of the first current signal is equal to the current value Iout of the second current signal, that is, the current signal at the current source signal terminal IREF can be accurately replicated to the signal output node OUTN. The fourteenth transistor M14 is continuously turned on, and the high-level signal of the first data signal terminal Data1 is continuously written to the sixth node N6. The ninth transistor M9 and the twelfth transistor M12 are turned off, the thirteenth transistor M13 is turned on, and the low-level signal of the ground terminal GND is written to the seventh node N7. The low-level signal of the second data signal terminal Data2 is continuously written to the seventh node N7. The eleventh transistor M11 is turned off, the tenth transistor M10 is turned on, and the high-level signal of the first power supply terminal VDD is continuously written to the sixth node N6.

[0278] In the third stage, P3, the pulse signal writing stage, the signal at the input control signal terminal EM1 is a low-level signal, while the signals at the control signal terminal EM2 and the duration control signal terminal EM4 are high-level signals. The first transistor M1, the fourteenth transistor M14, and the fifteenth transistor M15 are turned on, while the second transistor M2 and the fifth transistor M5 are turned off.

[0279] The first transistor M1 is turned on, the signal at the third node N3 remains unchanged, the sixth transistor M6 is continuously turned on, the signal at the third node N3 is written into the first node N1, the third transistor M3 is continuously turned on, the second transistor M2 and the fifth transistor M5 are turned off, the signal voltage value at the second node N2 is stored in the first capacitor C1 to maintain the stability of the signal at the second node N2, the fourth transistor M4 is continuously turned on, the signal voltage value at the fourth node N4 is stored in the second capacitor C2 to maintain the stability of the signal at the fourth node N4, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal. During this stage, at least one light-emitting device in the light-emitting device group emits light.

[0280] The fourteenth transistor M14 is continuously turned on, and the data signal of the first data signal terminal Data1 is written to the sixth node N6. The ninth transistor M9 is turned on or off depending on the signal of the sixth node N6. The fifteenth transistor M15 is continuously turned on, and the data signal of the second data signal terminal Data2 is written to the seventh node N7.

[0281] In the fourth stage, P4, the light-up holding stage, the signals at the input control signal terminal EM1 and the holding control signal terminal EM2 are high-level signals, while the signal at the duration control signal terminal EM4 is low-level. The first transistor M1, the second transistor M2, and the fifth transistor M5 are off, while the fourteenth transistor M14 and the fifteenth transistor M15 are on.

[0282] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, the fourth transistor M4 is turned on, the signal output node OUTN continuously outputs the second current signal, the signals of the sixth node N6 and the seventh node N7 remain unchanged, and the conduction state of the ninth transistor M9 depends on the data signals written to the first data signal terminal and the second data signal terminal. When the data signal written to the first data signal terminal is a low level signal and the data signal written to the second data signal terminal is a high level signal, the ninth transistor M9 is turned on, the second current signal is provided to the light-emitting device group, and at least one light-emitting device in the light-emitting device group emits light. When the data signal written to the first data signal terminal is a high level signal and the data signal written to the second data signal terminal is a low level signal, the ninth transistor M9 is turned off, the second current signal cannot be provided to the light-emitting device group, and at least one light-emitting device in the light-emitting device group does not emit light.

[0283] Figure 18 is a timing diagram of the pixel driving circuit provided in Figure 12. The exemplary embodiments of this disclosure are described below using the operation of the exemplary pixel driving circuit in Figure 12. The pixel driving circuit provided in Figure 11 includes: fifteen transistors (first transistor M1 to eighth transistor M8, ninth transistor M9 to fifteenth transistor M15) and three capacitors (first capacitor C1, second capacitor C2, and third capacitor C3). First transistors M1 to eighth transistors M8, ninth transistor M9, tenth transistor M10, and twelfth transistor M12 are P-type transistors, while eleventh transistor M11, thirteenth transistor M13, fourteenth transistor M14, and fifteenth transistor M15 are N-type transistors.

[0284] In an exemplary embodiment, the operation of the pixel driving circuit in at least one display frame may include:

[0285] In the first stage P1, the signals at the input control signal terminal EM1, the hold control signal terminal EM2, the node control signal terminal EM3, and the duration control signal terminal EM4 are all high-level signals. The fourteenth transistor M14 and the fifteenth transistor M15 are turned on, while the first transistor M1, the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are turned off.

[0286] The fourteenth transistor M14 is turned on, and the high-level signal of the first data signal terminal Data1 is written to the sixth node N6. The ninth transistor M9 and the twelfth transistor M12 are turned off. The thirteenth transistor M13 is turned on, and the low-level signal of the ground terminal GND is written to the seventh node N7. The low-level signal of the second data signal terminal Data2 is written to the seventh node N7. The eleventh transistor M11 is turned off, and the tenth transistor M10 is turned on. The high-level signal of the first power supply terminal VDD is continuously written to the sixth node.

[0287] In the second stage P2, the current signal writing stage, the signals of the input control signal terminal EM1, the holding control signal terminal EM2, and the node control signal terminal EM3 are low-level signals, and the signal of the duration control signal terminal EM4 is high-level signal. The first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, the fourteenth transistor M14, and the fifteenth transistor M15 are turned on.

[0288] The first transistor M1 is turned on, and the signal at the current source signal terminal IREF is written into the third node N3. The sixth transistor M6 is turned on, and the eighth transistor M8 is turned on. The signal at the third node N3 is written into the first node N1. The third transistor M3 is turned on, and the first power supply terminal VDD, the third transistor M3, the sixth transistor M6, the first transistor M1, and the current source signal terminal IREF form a path. The signal flowing through the path is the first current signal, and the current value Iref of the first current signal is equal to the current value of the signal at the current source signal terminal IREF. During this stage, the gate and drain voltages of either the third transistor or the sixth transistor are the same. Both the third transistor M3 and the sixth transistor M6 are in the constant current region, where the current value Iref of the first current signal is equal to I... M3 =I M6 =0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 *(1+λV DS3 )=0.5*μ6*Cox6*(W / L)6*(V GS6 -V TH6 ) 2 *(1+λV DS6 ), I M3 V represents the current flowing through the third transistor, μ3 is the mobility of the third transistor, Cox3 is the capacitance per unit area of ​​the gate oxide layer of the third transistor, (W / L)3 is the aspect ratio of the channel region of the third transistor, and V GS3 V is the gate-source voltage difference of the third transistor. DS3 V is the source-drain voltage difference of the third transistor. TH3 I is the threshold voltage of the third transistor. M6V represents the current flowing through the sixth transistor, μ6 is the mobility of the sixth transistor, Cox6 is the capacitance per unit area of ​​the gate oxide layer of the sixth transistor, (W / L)6 is the aspect ratio of the channel region of the sixth transistor, and V GS6 V is the gate-source voltage difference of the sixth transistor. DS6 V is the source-drain voltage difference of the sixth transistor. TH6 This is the threshold voltage of the sixth transistor.

[0289] The second transistor M2 is turned on, and the signal from the first node N1 is written to the second node N2. The fourth transistor M4 is then turned on. At this time, V... N1 =V N2 , where V N1 V is the voltage value of the signal at the first node N1. N2 The voltage value of the signal at the second node N2 is used to turn on the fifth transistor M5. The signal at the third node N3 is written to the fourth node N4, and the seventh transistor M7 is turned on. V N3 =V N4 At this time, V N3 V is the voltage value of the signal at the third node N3. N4 Let N be the voltage value of the signal at the fourth node N4. At this time, the gate electrode voltages of the third transistor M3 and the fourth transistor M4 are the same, and the source electrode voltages of the third transistor M3 and the fourth transistor M4 are both Vdd, where Vdd is the voltage value of the signal at the first power supply terminal. The current value Iout of the second current signal output by the signal output node OUTN satisfies the formula Iout = I M4 =I M7 =0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 *(1+λV DS4 )=0.5*μ7*Cox7*(W / L)7*(V GS7 -V TH7 ) 2 *(1+λV DS7 ), where I M4 V is the current flowing through the fourth transistor, μ4 is the mobility of the fourth transistor, Cox4 is the capacitance per unit area of ​​the gate oxide layer of the fourth transistor, (W / L)4 is the aspect ratio of the channel region of the fourth transistor, and V GS4 V is the gate-source voltage difference of the fourth transistor. DS4 V is the source-drain voltage difference of the fourth transistor. TH4 I is the threshold voltage of the fourth transistor. M7 V is the current flowing through the seventh transistor, μ7 is the mobility of the seventh transistor, Cox7 is the capacitance per unit area of ​​the gate oxide layer of the seventh transistor, (W / L)7 is the width-to-length ratio of the channel region of the seventh transistor, and VGS7 V is the gate-source voltage difference of the seventh transistor. DS7 V is the source-drain voltage difference of the seventh transistor. TH7 This is the threshold voltage of the seventh transistor.

[0290] The device parameters of the third transistor are the same as those of the fourth transistor; that is, μ4 is the same as μ3, Cox4 is the same as Cox3, and (W / L)4 is the same as (W / L)3. The gate voltage V of the third transistor M3 is... G3 and the gate electrode voltage V of the fourth transistor M4 G4 Equal, the source electrode voltage V of the third transistor M4 S3 and the source electrode voltage V of the fourth transistor M4 S4 Equal, the threshold voltage V of the third transistor TH3 and the threshold voltage V of the fourth transistor TH4 The gate-source voltage difference V of the third transistor M3 is equal. GS3 The gate-source voltage difference V with the fourth transistor GS4 Same. V DS3 =V GS7 +V GS4 -V GS6 When the gate-source voltage difference V of the sixth transistor M6 GS6 The gate-source voltage difference V with the seventh transistor M7 GS7 Same, has V DS3 =V GS4 =V DS4 According to the formula satisfied by the current values ​​of the first and second current signals, Iref / Iout=0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 *(1+λV DS3 ) / 0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 *(1+λV DS4 The pixel driving circuit provided in this disclosure eliminates the current replication error caused by the channel modulation effect in the pixel driving circuit, ensuring that the current value Iref of the first current signal is equal to the current value Iout of the second current signal, that is, the current signal of the current source signal terminal IREF can be accurately replicated to the signal output node OUTN.

[0291] The fourteenth transistor M14 is continuously turned on, and the high-level signal of the first data signal terminal Data1 is continuously written to the sixth node N6. The ninth transistor M9 and the twelfth transistor M12 are turned off, the thirteenth transistor M13 is turned on, and the low-level signal of the ground terminal GND is written to the seventh node N7. The low-level signal of the second data signal terminal Data2 is continuously written to the seventh node N7. The eleventh transistor M11 is turned off, the tenth transistor M10 is turned on, and the high-level signal of the first power supply terminal VDD is continuously written to the sixth node N6.

[0292] In the third stage, P3, the pulse signal writing stage, the signal at the input control signal terminal EM1 is a low-level signal, while the signals at the control signal terminal EM2, the node control signal terminal EM3, and the duration control signal terminal EM4 are kept at a high level. The first transistor M1, the fourteenth transistor M14, and the fifteenth transistor M15 are turned on, while the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are turned off.

[0293] The first transistor M1 is turned on, the signal at the third node N3 remains unchanged, the sixth transistor M6 is continuously turned on, the first node N1 maintains the signal from the previous stage, the third transistor M3 is continuously turned on, the second transistor M2 and the fifth transistor M5 are turned off, the signal voltage value at the second node N2 is stored in the first capacitor C1 to maintain the stability of the signal at the second node N2, the fourth transistor M4 is continuously turned on, the signal voltage value at the fourth node N4 is stored in the second capacitor C2 to maintain the stability of the signal at the fourth node N4, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal. In this stage, at least one light-emitting device in the light-emitting device group emits light.

[0294] The fourteenth transistor M14 is continuously turned on, and the data signal of the first data signal terminal Data1 is written to the sixth node N6. The ninth transistor M9 is turned on or off depending on the signal of the sixth node N6. The fifteenth transistor M15 is continuously turned on, and the data signal of the second data signal terminal Data2 is written to the seventh node N7.

[0295] In the fourth stage, P4, the light-up holding stage, the signals at the input control signal terminal EM1, the holding control signal terminal EM2, and the node control signal terminal EM3 are high-level signals, while the signal at the duration control signal terminal EM4 is low-level. The first transistor M1, the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are disconnected, while the fourteenth transistor M14 and the fifteenth transistor M15 are turned on.

[0296] Under the action of the first capacitor C1, the signal at the second node N2 remains unchanged, and the fourth transistor M4 is turned on. Under the action of the second capacitor C2, the signal at the fourth node N4 remains unchanged, and the seventh transistor M7 remains continuously turned on. The signal output node OUTN continuously outputs the second current signal. The signals at the sixth node N6 and the seventh node N7 remain unchanged. The conduction state of the ninth transistor M9 depends on the data signals written to the first and second data signal terminals. When the data signal written to the first data signal terminal is a low-level signal and the data signal written to the second data signal terminal is a high-level signal, the ninth transistor M9 is turned on, and the second current signal is provided to the light-emitting device group, causing at least one light-emitting device in the group to emit light. When the data signal written to the first data signal terminal is a high-level signal and the data signal written to the second data signal terminal is a low-level signal, the ninth transistor M9 is turned off, the second current signal cannot be provided to the light-emitting device group, and at least one light-emitting device in the group does not emit light.

[0297] Figure 19 is a timing diagram of the pixel driving circuit provided in Figure 13. The exemplary embodiments of this disclosure are described below using the operation of the exemplary pixel driving circuit in Figure 13. The pixel driving circuit provided in Figure 13 includes eleven transistors (first transistor M1 to seventh transistor M7, ninth transistor M9 to twelfth transistor M12) and three capacitors (first capacitor C1, second capacitor C2, and third capacitor C3). First transistors M1 to seventh transistor M7, ninth transistor M9, tenth transistor M10, and twelfth transistor M12 are P-type transistors, and eleventh transistor M11 is an N-type transistor.

[0298] In an exemplary embodiment, the operation of the pixel driving circuit in at least one display frame may include:

[0299] In the first stage P1, the input control signal terminal EM1, the hold control signal terminal EM2, and the scan signal terminal Gate are all at a high level. The first transistor M1, the second transistor M2, the fifth transistor M5, and the twelfth transistor M12 are disconnected.

[0300] With the twelfth transistor M12 disconnected, the data signal at the Data terminal cannot be written to the seventh node N7.

[0301] In the second stage P2, the current signal writing stage, the signals at the input control signal terminal EM1 and the holding control signal terminal EM2 are low-level signals, the signal at the scan signal terminal Gate is high-level signal, the first transistor M1 and the second transistor M2 are turned on, and the twelfth transistor M12 is turned off.

[0302] The first transistor M1 is turned on, and the signal at the current source signal terminal IREF is written into the third node N3. The sixth transistor M6 is turned on, and the signal at the third node N3 is written into the first node N1. The third transistor M3 is turned on, and the first power supply terminal VDD, the third transistor M3, the sixth transistor M6, the first transistor M1, and the current source signal terminal IREF form a path. The signal flowing through the path is the first current signal, and the current value Iref of the first current signal is equal to the current value of the signal at the current source signal terminal IREF. During this stage, the gate and drain voltages of either the third or sixth transistor are the same. Both the third transistor M3 and the sixth transistor M6 are in the constant current region, where the current value Iref of the first current signal is equal to I... M3 =I M6 =0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 =0.5*μ6*Cox6*(W / L)6*(V GS6 -V TH6 ) 2 I M3 V represents the current flowing through the third transistor, μ3 is the mobility of the third transistor, Cox3 is the capacitance per unit area of ​​the gate oxide layer of the third transistor, (W / L)3 is the aspect ratio of the channel region of the third transistor, and V GS3 V is the gate-source voltage difference of the third transistor. TH3 I is the threshold voltage of the third transistor. M6 I is the current flowing through the sixth transistor. M6 V represents the current flowing through the third transistor, μ6 is the mobility of the sixth transistor, Cox6 is the capacitance per unit area of ​​the gate oxide layer of the sixth transistor, (W / L)6 is the aspect ratio of the channel region of the sixth transistor, and V GS6 V is the gate-source voltage difference of the sixth transistor. TH6 This is the threshold voltage of the sixth transistor.

[0303] The second transistor M2 is turned on, and the signal from the first node N1 is written to the second node N2. The fourth transistor M4 is then turned on. At this time, V... N1 =V N2 , where V N1 V is the voltage value of the signal at the first node N1. N2 The voltage value of the signal at the second node N2 is given, the fifth transistor M5 is turned on, the signal at the third node N3 is written to the fourth node N4, the seventh transistor M7 is turned on, and at this time, V N3 =V N4 , where V N3 V is the voltage value of the signal at the third node N3. N4Let N be the voltage value of the signal at the fourth node N4. At this time, the gate electrode voltages of the third transistor M3 and the fourth transistor M4 are the same, and the source electrode voltages of both the third transistor M3 and the fourth transistor M4 are Vdd, where Vdd is the voltage value of the signal at the first power supply terminal VDD. The current value Iout of the second current signal output by the signal output node OUTN satisfies the formula Iout = I M4 =I M7 =0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 =0.5*μ7*Cox7*(W / L)7*(V GS7 -V TH7 ) 2 , among which, I M4 V is the current flowing through the fourth transistor, μ4 is the mobility of the fourth transistor, Cox4 is the capacitance per unit area of ​​the gate oxide layer of the fourth transistor, (W / L)4 is the aspect ratio of the channel region of the fourth transistor, and V GS4 V is the gate-source voltage difference of the fourth transistor. TH4 I is the threshold voltage of the fourth transistor. M7 V is the current flowing through the seventh transistor, μ7 is the mobility of the seventh transistor, Cox7 is the capacitance per unit area of ​​the gate oxide layer of the seventh transistor, (W / L)7 is the width-to-length ratio of the channel region of the seventh transistor, and V GS7 V is the gate-source voltage difference of the seventh transistor. TH7 This is the threshold voltage of the seventh transistor.

[0304] The device parameters of the third transistor are the same as those of the fourth transistor; that is, μ4 is the same as μ3, Cox4 is the same as Cox3, and (W / L)4 is the same as (W / L)3. The gate voltage V of the third transistor M3 is... G3 and the gate electrode voltage V of the fourth transistor M4 G4 Equal, the source electrode voltage V of the third transistor M4 S3 and the source electrode voltage V of the fourth transistor M4 S4 Equal, the threshold voltage V of the third transistor TH3 and the threshold voltage V of the fourth transistor TH4 The gate-source voltage difference V of the third transistor M3 is equal. GS3 The gate-source voltage difference V with the fourth transistor GS4 Similarly, when (W / L)6 / (W / L)7 = (W / L)3 / (W / L)4, the gate-source voltage difference V of the sixth transistor M6... GS6 The gate-source voltage difference V with the seventh transistor M7 GS7Similarly, the voltage values ​​of the signals at the first node N1 and the fifth node N5 are the same. Therefore, the source-drain voltage difference V of the third transistor is... DS3 The source-drain voltage difference V with the fourth transistor DS4 This eliminates the current replication error caused by the channel modulation effect in the pixel driving circuit, ensuring that the current value Iref of the first current signal is equal to the current value Iout of the second current signal, that is, the current signal at the current source signal terminal IREF can be accurately replicated to the signal output node OUTN.

[0305] With the twelfth transistor M12 disconnected, the data signal at the Data terminal cannot be written to the seventh node N7.

[0306] In the third stage, P3, the pulse signal writing stage, the signal at the input control signal terminal EM1 is a low-level signal, while the signals at the control signal terminal EM2 and the scan signal terminal Gate are kept at a high-level signal. The first transistor M1 is turned on, while the second transistor M2, the fifth transistor M5, and the twelfth transistor M12 are turned off.

[0307] The first transistor M1 is turned on, the signal at the third node N3 remains unchanged, the sixth transistor M6 is continuously turned on, the signal at the third node N3 is written into the first node N1, the third transistor M3 is continuously turned on, the second transistor M2 and the fifth transistor M5 are turned off, the signal voltage value at the second node N2 is stored in the first capacitor C1 to maintain the stability of the signal at the second node N2, the fourth transistor M4 is continuously turned on, the signal voltage value at the fourth node N4 is stored in the second capacitor C2 to maintain the stability of the signal at the fourth node N4, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal. During this stage, at least one light-emitting device in the light-emitting device group emits light.

[0308] With the twelfth transistor M12 disconnected, the data signal at the Data terminal cannot be written to the seventh node N7.

[0309] In the fourth stage (P4), the input control signal terminal EM1 and the hold control signal terminal EM2 are at a high level, while the scan signal terminal Gate is at a low level. The first transistor M1, the second transistor M2, and the fifth transistor M5 are off, and the twelfth transistor M12 is on.

[0310] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, the fourth transistor M4 is turned on, under the action of the second capacitor C2, the signal of the fourth node N4 remains unchanged, the seventh transistor M7 is continuously turned on, the signal output node OUTN continuously outputs the second current signal, the twelfth transistor M12 is turned on, the high-level signal of the data signal terminal Data is written to the seventh node N7, the eleventh transistor M11 is turned on, the low-level signal of the duration control signal terminal EM4 is written to the sixth node N6, the ninth transistor M9 is continuously turned on, and at least one light-emitting device in the light-emitting device group emits light.

[0311] In the fifth stage (P5), the light-emitting and holding stage, the signals at the input control signal terminal EM1 and the holding control signal terminal EM2 are high-level signals, while the signal at the scan signal terminal Gate is low-level. The first transistor M1 and the second transistor M2 are off, and the twelfth transistor M12 is on.

[0312] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, and the fourth transistor M4 is turned on. Under the action of the second capacitor C2, the signal of the fourth node N4 remains unchanged, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal, and the twelfth transistor M12 is turned on. The data at the data signal terminal Data is written to the seventh node N7. The conduction state of the ninth transistor M9 depends on the data signal written at the data signal terminal. When the data signal written at the data signal terminal is a low-level signal, the tenth transistor M10 is turned on, and the signal at the high-frequency signal terminal HF is written to the sixth node N6. The ninth transistor M9 is turned on and off at high frequency under the control of the signal at the high-frequency signal terminal. The second current signal is provided to the light-emitting device group for part of the time, and at least one light-emitting device in the light-emitting device group emits light. When the data signal written at the data signal terminal is a high-level signal, the eleventh transistor M11 is turned on, and the low-level signal at the duration control signal terminal EM4 is written to the sixth node N6. The ninth transistor M9 is continuously turned on, and at least one light-emitting device in the light-emitting device group emits light.

[0313] Figure 20 is a timing diagram of the pixel driving circuit provided in Figure 14. The exemplary embodiments of this disclosure are described below using the operation of the exemplary pixel driving circuit in Figure 14. The pixel driving circuit provided in Figure 14 includes: twelve transistors (first transistor M1 to twelfth transistor M12) and three capacitors (first capacitor C1, second capacitor C2, and third capacitor C3). First transistors M1 to tenth transistors M10 and twelfth transistor M12 are P-type transistors, and eleventh transistor M11 is an N-type transistor.

[0314] In an exemplary embodiment, the operation of the pixel driving circuit in at least one display frame may include:

[0315] In the first stage P1, the input control signal terminal EM1, the hold control signal terminal EM2, the node control signal terminal EM3, and the scan signal terminal Gate are all at high level. The first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, and the twelfth transistor M12 are disconnected.

[0316] With the twelfth transistor M12 disconnected, the data signal at the Data terminal cannot be written to the seventh node N7.

[0317] In the second stage P2, the current signal writing stage, the signals of the input control signal terminal EM1, the holding control signal terminal EM2, and the node control signal terminal EM3 are low-level signals, the signal of the scan signal terminal Gate is high-level signal, the first transistor M1, the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are turned on, and the twelfth transistor M12 is turned off.

[0318] The first transistor M1 is turned on, and the signal at the current source signal terminal IREF is written into the third node N3. The sixth transistor M6 is turned on, and the eighth transistor M8 is turned on. The signal at the third node N3 is written into the first node N1. The third transistor M3 is turned on, and the first power supply terminal VDD, the third transistor M3, the sixth transistor M6, the first transistor M1, and the current source signal terminal IREF form a path. The signal flowing through the path is the first current signal, and the current value Iref of the first current signal is equal to the current value of the signal at the current source signal terminal IREF. During this stage, the gate and drain voltages of either the third transistor or the sixth transistor are the same. Both the third transistor M3 and the sixth transistor M6 are in the constant current region, where the current value Iref of the first current signal is equal to I... M3 =I M6 =0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 *(1+λV DS3 )=0.5*μ6*Cox6*(W / L)6*(V GS6 -V TH6 ) 2 *(1+λV DS6 ), I M3 V represents the current flowing through the third transistor, μ3 is the mobility of the third transistor, Cox3 is the capacitance per unit area of ​​the gate oxide layer of the third transistor, (W / L)3 is the aspect ratio of the channel region of the third transistor, and V GS3 V is the gate-source voltage difference of the third transistor. DS3 V is the source-drain voltage difference of the third transistor. TH3 I is the threshold voltage of the third transistor. M6V represents the current flowing through the sixth transistor, μ6 is the mobility of the sixth transistor, Cox6 is the capacitance per unit area of ​​the gate oxide layer of the sixth transistor, (W / L)6 is the aspect ratio of the channel region of the sixth transistor, and V GS6 V is the gate-source voltage difference of the sixth transistor. DS6 V is the source-drain voltage difference of the sixth transistor. TH6 This is the threshold voltage of the sixth transistor.

[0319] The second transistor M2 is turned on, and the signal from the first node N1 is written to the second node N2. The fourth transistor M4 is then turned on. At this time, V... N1 =V N2 , where V N1 V is the voltage value of the signal at the first node N1. N2 The voltage value of the signal at the second node N2 is used to turn on the fifth transistor M5. The signal at the third node N3 is written to the fourth node N4, and the seventh transistor M7 is turned on. V N3 =V N4 At this time, V N3 V is the voltage value of the signal at the third node N3. N4 Let N be the voltage value of the signal at the fourth node N4. At this time, the gate electrode voltages of the third transistor M3 and the fourth transistor M4 are the same, and the source electrode voltages of the third transistor M3 and the fourth transistor M4 are both Vdd, where Vdd is the voltage value of the signal at the first power supply terminal. The current value Iout of the second current signal output by the signal output node OUTN satisfies the formula Iout = I M4 =I M7 =0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 *(1+λV DS4 )=0.5*μ7*Cox7*(W / L)7*(V GS7 -V TH7 ) 2 *(1+λV DS7 ), where I M4 V is the current flowing through the fourth transistor, μ4 is the mobility of the fourth transistor, Cox4 is the capacitance per unit area of ​​the gate oxide layer of the fourth transistor, (W / L)4 is the aspect ratio of the channel region of the fourth transistor, and V GS4 V is the gate-source voltage difference of the fourth transistor. DS4 V is the source-drain voltage difference of the fourth transistor. TH4 I is the threshold voltage of the fourth transistor. M7 V is the current flowing through the seventh transistor, μ7 is the mobility of the seventh transistor, Cox7 is the capacitance per unit area of ​​the gate oxide layer of the seventh transistor, (W / L)7 is the width-to-length ratio of the channel region of the seventh transistor, and VGS7 V is the gate-source voltage difference of the seventh transistor. DS7 V is the source-drain voltage difference of the seventh transistor. TH7 This is the threshold voltage of the seventh transistor.

[0320] The device parameters of the third transistor are the same as those of the fourth transistor; that is, μ4 is the same as μ3, Cox4 is the same as Cox3, and (W / L)4 is the same as (W / L)3. The gate voltage V of the third transistor M3 is... G3 and the gate electrode voltage V of the fourth transistor M4 G4 Equal, the source electrode voltage V of the third transistor M4 S3 and the source electrode voltage V of the fourth transistor M4 S4 Equal, the threshold voltage V of the third transistor TH3 and the threshold voltage V of the fourth transistor TH4 The gate-source voltage difference V of the third transistor M3 is equal. GS3 The gate-source voltage difference V with the fourth transistor GS4 Same. V DS3 =V GS7 +V GS4 -V GS6 When the gate-source voltage difference V of the sixth transistor M6 GS6 The gate-source voltage difference V with the seventh transistor M7 GS7 Same, has V DS3 =V GS4 =V DS4 According to the formula satisfied by the current values ​​of the first and second current signals, Iref / Iout=0.5*μ3*Cox3*(W / L)3*(V GS3 -V TH3 ) 2 *(1+λV DS3 ) / 0.5*μ4*Cox4*(W / L)4*(V GS4 -V TH4 ) 2 *(1+λV DS4 The pixel driving circuit provided in this disclosure eliminates the current replication error caused by the channel modulation effect in the pixel driving circuit, ensuring that the current value Iref of the first current signal is equal to the current value Iout of the second current signal, that is, the current signal of the current source signal terminal IREF can be accurately replicated to the signal output node OUTN.

[0321] With the twelfth transistor M12 disconnected, the data signal at the Data terminal cannot be written to the seventh node N7.

[0322] In the third stage, P3, the pulse signal writing stage, the signal at the input control signal terminal EM1 is a low-level signal, while the signals at the maintenance control signal terminal EM2, the duration control signal terminal EM3, and the scan signal terminal Gate are high-level signals. The first transistor M1 is turned on, while the second transistor M2, the fifth transistor M5, the eighth transistor M8, and the twelfth transistor M12 are turned off.

[0323] The first transistor M1 is turned on, the signal at the third node N3 remains unchanged, the sixth transistor M6 is continuously turned on, the first node N1 maintains the signal from the previous stage, the third transistor M3 is continuously turned on, the second transistor M2 and the fifth transistor M5 are turned off, the signal voltage value at the second node N2 is stored in the first capacitor C1 to maintain the stability of the signal at the second node N2, the fourth transistor M4 is continuously turned on, the signal voltage value at the fourth node N4 is stored in the second capacitor C2 to maintain the stability of the signal at the fourth node N4, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal. In this stage, at least one light-emitting device in the light-emitting device group emits light.

[0324] With the twelfth transistor M12 disconnected, the data signal at the Data terminal cannot be written to the seventh node N7.

[0325] In the fourth stage (P4), the input control signal terminal EM1, the hold control signal terminal EM2, and the node control signal terminal EM3 are all at high level, while the scan signal terminal Gate is at low level. The first transistor M1, the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are disconnected, while the twelfth transistor M12 is turned on.

[0326] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, the fourth transistor M4 is turned on, under the action of the second capacitor C2, the signal of the fourth node N4 remains unchanged, the seventh transistor M7 is continuously turned on, the signal output node OUTN continuously outputs the second current signal, the twelfth transistor M12 is turned on, the high-level signal of the data signal terminal Data is written to the seventh node N7, the eleventh transistor M11 is turned on, the low-level signal of the duration control signal terminal EM4 is written to the sixth node N6, the ninth transistor M9 is continuously turned on, and at least one light-emitting device in the light-emitting device group emits light.

[0327] In the fifth stage (P5), the light-up holding stage, the signals at the input control signal terminal EM1, the holding control signal terminal EM2, and the node control signal terminal EM3 are high-level signals, while the signal at the scan signal terminal Gate is low-level. The first transistor M1, the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are disconnected, while the twelfth transistor M12 is turned on.

[0328] Under the action of the first capacitor C1, the signal of the second node N2 remains unchanged, and the fourth transistor M4 is turned on. Under the action of the second capacitor C2, the signal of the fourth node N4 remains unchanged, and the seventh transistor M7 is continuously turned on. The signal output node OUTN continuously outputs the second current signal, and the twelfth transistor M12 is turned on. The data at the data signal terminal Data is written to the seventh node N7. The conduction state of the ninth transistor M9 depends on the data signal written at the data signal terminal. When the data signal written at the data signal terminal is a low-level signal, the tenth transistor M10 is turned on, and the signal at the high-frequency signal terminal HF is written to the sixth node N6. The ninth transistor M9 is turned on and off at high frequency under the control of the signal at the high-frequency signal terminal. The second current signal is provided to the light-emitting device group for part of the time, and at least one light-emitting device in the light-emitting device group emits light. When the data signal written at the data signal terminal is a high-level signal, the eleventh transistor M11 is turned on, and the low-level signal at the duration control signal terminal EM4 is written to the sixth node N6. The ninth transistor M9 is continuously turned on, and at least one light-emitting device in the light-emitting device group emits light.

[0329] Figure 21 is a graph showing the Iref and Iout error rates of the pixel driving circuit provided in Figure 4. As shown in Figure 21, for the pixel driving circuit provided in Figure 4, the Iout error rate is less than 5% when Iref is in the range of 10uA to 100uA, and the Iout error rate is larger when Iref is in the range of 1nA to 10uA.

[0330] Figure 22 is a graph showing the error rates of Iref and Iout for the pixel driving circuit provided in Figure 2. As shown in Figure 22, for the pixel driving circuit provided in Figure 2, when Iref is in the range of 1nA to 63uA, the error rate of Iout is ±0.5%; when Iref is in the range of 63uA to 100uA, the error rate of Iout is -2%, which is still less than ±5%.

[0331] Figure 23 is a graph showing the Iref and Iout error rates of the pixel driving circuit provided in Figure 3. As shown in Figure 23, for the pixel driving circuit provided in Figure 3, when Iref is in the range of 1nA to 60uA, the Iout error rate is ±0.5%; when Iref is in the range of 60uA to 100uA, the Iout error rate increases rapidly. The pixel driving circuit provided in Figure 3 can be optimized by adjusting the size or voltage of the device transistors, etc., and this disclosure does not impose any limitations on this.

[0332] As shown in Figures 21 to 23, the Iref error rate of the pixel driving circuit provided in Figures 2 and 3 of this disclosure in the range of 1nA to 60uA is less than the Iout error rate of the pixel driving circuit provided in Figure 4 in the range of 1nA to 60uA. Therefore, the arrangement of the sixth transistor and the seventh transistor can improve the performance of the pixel driving circuit, thereby improving the brightness uniformity of the AR product.

[0333] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit provided in any of the foregoing embodiments.

[0334] The driving method for a pixel driving circuit may include the following steps:

[0335] The signal input sub-circuit receives the first current signal from the current source signal terminal under the control of the input control signal terminal, the first power supply terminal, the first node, and the third node.

[0336] Under the control of the signal holding terminal and the ground terminal, the signal holding sub-circuit provides the signal of the first node to the second node and the signal of the third node to the fourth node.

[0337] The signal output sub-circuit, under the control of the signals from the second node, the fourth node, and the first power supply terminal, outputs a second current signal to the signal output node.

[0338] This disclosure also provides a display substrate, which may include: a plurality of light-emitting device groups and a pixel driving circuit provided in any of the foregoing embodiments, wherein at least one pixel driving circuit is electrically connected to the light-emitting device groups and is configured to drive the light-emitting device groups to emit light.

[0339] The light-emitting device group includes at least one light-emitting device, and the light-emitting device group is electrically connected to the pixel driving circuit.

[0340] In an exemplary embodiment, the light-emitting device includes a first electrode and a second electrode; when the light-emitting device group includes one light-emitting device, the first electrode of the light-emitting device is electrically connected to a signal output node or a node control sub-circuit, and the second electrode of the light-emitting device is electrically connected to a second power supply terminal; when the light-emitting device group includes at least two light-emitting devices, the at least two light-emitting devices are connected in series, the first electrode of the first light-emitting device is electrically connected to a signal output node or a node control sub-circuit, and the second electrode of the last light-emitting device is electrically connected to a second power supply terminal.

[0341] Figure 24 is a schematic diagram of the display substrate connection. As shown in Figure 24, the display substrate may include: multiple current source signal lines IREFL, multiple input control signal lines EML1, and multiple hold control signal lines EML2. Figure 24 is illustrated using N input control signal lines EML1-1 to EML1-N and N hold control signal lines EML2-1 to EML2-N as an example.

[0342] In an exemplary embodiment, as shown in FIG24, the current source signal terminals IREF of pixel driving circuits located in the same column are connected to the same current source signal line IREFL. Connecting the current source signal terminals IREF of pixel driving circuits located in the same column to the same current source signal line IREFL simplifies the structure of AR products and reduces manufacturing costs.

[0343] In an exemplary embodiment, the current source signal terminals IREF of at least one column of pixel driving circuits can be connected to the same current source signal line. That is, at least two of the M current source signal lines IREFL1 to IREFLM in Figure 24 are the same signal line. Connecting the current source signal terminals IREF of at least one column of pixel driving circuits to the same current source signal line can reduce the number of components in AR products and can help achieve high PPI in AR products.

[0344] In an exemplary embodiment, as shown in FIG24, the input control signal terminal EM1 of the pixel driving circuit in the same row is connected to the same input control signal line EML1.

[0345] In an exemplary embodiment, as shown in FIG24, the hold control signal terminal EM2 located in the same row of pixel driving circuits is connected to the same hold control signal line EML2.

[0346] In an exemplary embodiment, FIG25 is a schematic diagram of the display substrate. As shown in FIG25, the display substrate further includes a first data unit and a second data unit. The first data unit is electrically connected to the input control signal line EML1, and the second data unit is electrically connected to the hold control signal line EML2.

[0347] In an exemplary embodiment, the time during which the first data unit provides an effective level signal to the input control signal line connected to the i-th row pixel driving circuit overlaps at least partially with the time during which the second data unit provides an effective level signal to the hold control signal line connected to the i-th row pixel driving circuit, and the time during which the first data unit provides an effective level signal to the input control signal line connected to the i-th row pixel driving circuit is longer than the time during which the second data unit provides an effective level signal to the hold control signal line connected to the i-th row pixel driving circuit.

[0348] In an exemplary embodiment, the time during which the second data unit provides an effective level signal to the hold control signal line connected to the i-th row pixel driving circuit is within the time during which the first data unit provides an effective level signal to the input control signal line connected to the i-th row pixel driving circuit.

[0349] This disclosure also provides a display device, including: a display substrate provided in any of the foregoing embodiments.

[0350] In an exemplary embodiment, the display device is augmented reality glasses or a head-up display.

[0351] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0352] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0353] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit, comprising: Signal input sub-circuit, signal holding sub-circuit, and signal output sub-circuit; The signal input sub-circuit is electrically connected to the input control signal terminal, the current source signal terminal, the first power supply terminal, the first node, and the third node, respectively, and is configured to input the first current signal of the current source signal terminal under the control of the signals of the input control signal terminal, the first power supply terminal, the first node, and the third node; The signal holding sub-circuit is electrically connected to the holding control signal terminal, the first node, the second node, the third node, the fourth node and the ground terminal respectively, and is configured to provide the signal of the first node to the second node and the signal of the third node to the fourth node under the control of the signals of the holding control signal terminal and the ground terminal. The signal output sub-circuit is electrically connected to the first power supply terminal, the second node, the fourth node and the signal output node respectively, and is configured to output a second current signal to the signal output node under the control of the signals of the second node, the fourth node and the first power supply terminal.

2. The pixel driving circuit according to claim 1, wherein, The signal input sub-circuit includes: a first transistor, a third transistor, and a sixth transistor; The control electrode of the first transistor is electrically connected to the input control signal terminal, the first electrode of the first transistor is electrically connected to the current source signal terminal, and the second electrode of the first transistor is electrically connected to the third node. The control electrode and the second electrode of the third transistor are electrically connected to the first node, and the first electrode of the third transistor is electrically connected to the first power supply terminal. The control electrode and the second electrode of the sixth transistor are electrically connected to the third node, respectively, and the first electrode of the sixth transistor is electrically connected to the first node.

3. The pixel driving circuit according to claim 2, wherein, The signal output sub-circuit includes: a fourth transistor and a seventh transistor; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node. The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the signal output node.

4. The pixel driving circuit according to claim 1, wherein, The signal input sub-circuit is also electrically connected to the node control signal terminal and is configured to provide the signal of the third node to the first node under the control of the signal at the node control signal terminal.

5. The pixel driving circuit according to claim 4, wherein, The signal input sub-circuit includes: a first transistor, a third transistor, a sixth transistor, and an eighth transistor; The control electrode of the first transistor is electrically connected to the input control signal terminal, the first electrode of the first transistor is electrically connected to the current source signal terminal, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first power supply terminal, and the second electrode of the third transistor is electrically connected to the fifth node. The control electrode and the second electrode of the sixth transistor are electrically connected to the third node, respectively, and the first electrode of the sixth transistor is electrically connected to the fifth node. The control electrode of the eighth transistor is electrically connected to the node control signal terminal, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node.

6. The pixel driving circuit according to claim 5, wherein, The signal output sub-circuit includes: a fourth transistor and a seventh transistor; The control electrode and the second electrode of the fourth transistor are electrically connected to the second node, and the first electrode of the fourth transistor is electrically connected to the first power supply terminal. The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the signal output node.

7. The pixel driving circuit according to claim 1, wherein, The signal holding sub-circuit includes: a second transistor, a fifth transistor, a first capacitor, and a second capacitor; The control electrode of the second transistor is electrically connected to the holding control signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node. The control electrode of the fifth transistor is electrically connected to the holding control signal terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the ground terminal. The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the ground terminal.

8. The pixel driving circuit according to claim 1, wherein, The signal input sub-circuit includes: a first transistor, a third transistor, and a sixth transistor; the signal holding sub-circuit includes: a second transistor, a fifth transistor, a first capacitor, and a second capacitor; the signal output sub-circuit includes: a fourth transistor and a seventh transistor; The control electrode of the first transistor is electrically connected to the input control signal terminal, the first electrode of the first transistor is electrically connected to the current source signal terminal, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the holding control signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node. The control electrode and the second electrode of the third transistor are electrically connected to the first node, and the first electrode of the third transistor is electrically connected to the first power supply terminal. The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node. The control electrode of the fifth transistor is electrically connected to the holding control signal terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The control electrode and second electrode of the sixth transistor are electrically connected to the third node, respectively, and the first electrode of the sixth transistor is electrically connected to the first node. The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the signal output node. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the ground terminal. The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the ground terminal. At least one of the first to the seventh transistors is a P-type transistor.

9. The pixel driving circuit according to claim 1, wherein, The signal input sub-circuit includes: a first transistor, a third transistor, a sixth transistor, and an eighth transistor; the signal holding sub-circuit includes: a second transistor, a fifth transistor, a first capacitor, and a second capacitor; the signal output sub-circuit includes: a fourth transistor and a seventh transistor; The control electrode of the first transistor is electrically connected to the input control signal terminal, the first electrode of the first transistor is electrically connected to the current source signal terminal, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the hold control signal terminal, and the first electrode of the second transistor is electrically connected to the first node. Then, the second terminal of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first power supply terminal, and the second electrode of the third transistor is electrically connected to the fifth node. The control electrode and the second electrode of the fourth transistor are electrically connected to the second node, and the first electrode of the fourth transistor is electrically connected to the first power supply terminal. The control electrode of the fifth transistor is electrically connected to the holding control signal terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The control electrode and the second electrode of the sixth transistor are electrically connected to the third node, respectively, and the first electrode of the sixth transistor is electrically connected to the fifth node. The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the signal output node. The control electrode of the eighth transistor is electrically connected to the node control signal terminal, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the ground terminal. The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the ground terminal. At least one of the first to eighth transistors is a P-type transistor.

10. The pixel driving circuit according to any one of claims 1, 8, and 9, wherein, The pixel driving circuit is electrically connected to the light-emitting device group and is configured to drive the light-emitting device group to emit light. The pixel driving circuit also includes a duration control sub-circuit. The light-emitting device group is electrically connected to the signal output node through the duration control sub-circuit, and the duration control sub-circuit is configured to provide the light-emitting device group with a second current signal output by the signal output node.

11. The pixel driving circuit according to claim 10, wherein, The duration control sub-circuit includes: a ninth transistor, a tenth transistor, and a third capacitor; The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the signal output sub-circuit, and the second electrode of the ninth transistor is electrically connected to the light-emitting device group. The control electrode of the tenth transistor is electrically connected to the duration control signal terminal, the first electrode of the tenth transistor is electrically connected to the data signal terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node. The first terminal of the third capacitor is electrically connected to the sixth node, and the second terminal of the third capacitor is electrically connected to the common voltage terminal. At least one of the ninth and tenth transistors is a P-type transistor.

12. The pixel driving circuit according to claim 10, wherein, The duration control sub-circuit includes: the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor; The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the signal output node, and the second electrode of the ninth transistor is electrically connected to the light-emitting device group. The control electrode of the tenth transistor is electrically connected to the seventh node, the first electrode of the tenth transistor is electrically connected to the first power supply terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node. The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the ground terminal, and the second electrode of the eleventh transistor is electrically connected to the sixth node. The control electrode of the twelfth transistor is electrically connected to the sixth node, and the first electrode of the twelfth transistor is electrically connected to the first power supply terminal. Then, the second terminal of the twelfth transistor is electrically connected to the seventh node; The control electrode of the thirteenth transistor is electrically connected to the sixth node, the first electrode of the thirteenth transistor is electrically connected to the ground terminal, and the second electrode of the thirteenth transistor is electrically connected to the seventh node. The control electrode of the fourteenth transistor is electrically connected to the duration control signal terminal, the first electrode of the fourteenth transistor is electrically connected to the first data signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the sixth node. The control electrode of the fifteenth transistor is electrically connected to the duration control signal terminal, the first electrode of the fifteenth transistor is electrically connected to the second data signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the seventh node. The tenth and eleventh transistors are of different transistor types, the twelfth and thirteenth transistors are of different transistor types, and at least one of the fourteenth and fifteenth transistors is an N-type transistor. The signals at the first data signal terminal and the signals at the second data signal terminal are at least inverse signals for a portion of the time period.

13. The pixel driving circuit according to claim 10, wherein, The duration control sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor; The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the signal output node, and the second electrode of the ninth transistor is electrically connected to the light-emitting device group. The control electrode of the tenth transistor is electrically connected to the seventh node, the first electrode of the tenth transistor is electrically connected to the high-frequency signal terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node. The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the duration control signal terminal, and the second electrode of the eleventh transistor is electrically connected to the sixth node. The control electrode of the twelfth transistor is electrically connected to the scan signal terminal, the first electrode of the twelfth transistor is electrically connected to the data signal terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node. The first terminal of the third capacitor is electrically connected to the seventh node, and the second terminal of the third capacitor is electrically connected to the common voltage terminal. The tenth and eleventh transistors have opposite transistor types; At least one of the ninth and twelfth transistors is a P-type transistor.

14. The pixel driving circuit according to claim 8 or 9, wherein, The device parameters of the third transistor are the same as those of the fourth transistor; The device parameters include: mobility, unit gate oxide capacitance, and channel aspect ratio.

15. The pixel driving circuit according to claim 8 or 9, wherein, The device parameters of the sixth transistor are the same as those of the seventh transistor; The device parameters include: mobility, unit gate oxide capacitance, and channel aspect ratio.

16. A display substrate, comprising: A plurality of light-emitting device groups and a pixel driving circuit as described in any one of claims 1 to 15, wherein the at least one pixel driving circuit is electrically connected to the light-emitting device groups and is configured to drive the light-emitting device groups to emit light. The light-emitting device group includes at least one light-emitting device, and the light-emitting device group is electrically connected to the pixel driving circuit.

17. The display substrate according to claim 16, wherein, The light-emitting device includes a first electrode and a second electrode; When the light-emitting device group includes a light-emitting device, the first electrode of the light-emitting device is electrically connected to the signal output node or the node control sub-circuit, and the second electrode of the light-emitting device is electrically connected to the second power supply terminal. When the light-emitting device group includes at least two light-emitting devices, the at least two light-emitting devices are arranged in series, and the first light-emitting device emits light... The first electrode of the device is electrically connected to the signal output node or the node control sub-circuit, and the second electrode of the last light-emitting device is electrically connected to the second power supply terminal.

18. The display substrate according to claim 17, further comprising: Multiple current source signal lines, multiple input control signal lines, and multiple holding control signal lines; The current source signal terminals of pixel driving circuits located in the same column are connected to the same current source signal line; At least one column of pixel driving circuits has its current source signal terminal connected to the same current source signal line; The input control signal terminals of the pixel driving circuits located in the same row are connected to the same input control signal line; The hold control signal terminals of the pixel driving circuits located in the same row are connected to the same hold control signal line.

19. The display substrate according to claim 18, further comprising: a first data unit and a second data unit; The first data unit is electrically connected to the input control signal line, and the second data unit is electrically connected to the hold control signal line; The time when the first data unit provides an effective level signal to the input control signal line connected to the i-th row pixel driving circuit overlaps at least partially with the time when the second data unit provides an effective level signal to the hold control signal line connected to the i-th row pixel driving circuit. The time when the first data unit provides an effective level signal to the input control signal line connected to the i-th row pixel driving circuit is longer than the time when the second data unit provides an effective level signal to the hold control signal line connected to the i-th row pixel driving circuit, 1≤i≤N, where N is the total number of rows of the pixel driving circuit.

20. The display substrate according to claim 19, wherein, The time during which the second data unit provides an effective level signal to the hold control signal line connected to the i-th row pixel driving circuit is within the time during which the first data unit provides an effective level signal to the input control signal line connected to the i-th row pixel driving circuit.

21. The display substrate according to claim 16, wherein, Light-emitting devices include: micro light-emitting diodes.

22. A display device, comprising: The display substrate as described in any one of claims 16 to 21.

23. The display device according to claim 22, comprising: Augmented reality glasses or heads-up displays.

24. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as described in any one of claims 1 to 15, the method comprising: The signal input sub-circuit receives the first current signal from the current source signal terminal under the control of the input control signal terminal, the first power supply terminal, the first node, and the third node. Under the control of the signal holding control terminal and the ground terminal, the signal holding sub-circuit provides the signal of the first node to the second node and the signal of the third node to the fourth node; The signal output sub-circuit outputs a second current signal to the signal output node under the control of the signals from the second node, the fourth node, and the first power supply terminal.

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