Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a gate driving circuit, the gate driving circuit comprising a plurality of cascaded shift registers, wherein each shift register comprises a shift sub-circuit and an output sub-circuit. The display substrate further comprises a plurality of first cross-stage connection lines (NL1) located in a non-display area, wherein at least one first cross-stage connection line (NL1) is electrically connected to a first control signal terminal (G1) and a signal input terminal (IN) that are connected to a stage of shift register and a cascade signal output terminal (Carry) that is connected to the previous stage of shift register, respectively, and the orthographic projection of at least part of the at least one first cross-stage connection line (NL1) on a base (10) is at least partially located between the orthographic projections of two stages of shift registers connected to the first cross-stage connection line (NL1) on the base (10).

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a display substrate having a display area and a non-display area. The display substrate includes: a substrate and a gate driving circuit disposed on the substrate and located in the non-display area. The gate driving circuit includes: a plurality of cascaded shift registers, at least one shift register including: a shift sub-circuit and an output sub-circuit.

[0006] The shift sub-circuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the third power supply terminal, the cascaded signal output terminal, and the output sub-circuit, respectively. It is configured to provide a signal from the first power supply terminal or the second power supply terminal to the cascaded signal output terminal under the control of the signals from the signal input terminal, the first clock signal terminal, the second clock signal terminal, and the third power supply terminal, and to provide a signal from at least one of the signal input terminal, the second clock signal terminal, and the first power supply terminal to the output sub-circuit.

[0007] The output sub-circuit is also electrically connected to the first control signal terminal, the second control signal terminal, the third control signal terminal, the masking signal terminal, the first power supply terminal, the second power supply terminal, and the drive signal output terminal, respectively, and is configured to provide the first power supply terminal or the second power supply terminal signal to the drive signal output terminal under the control of the signal provided by the shift sub-circuit and the signals of the first control signal terminal, the second control signal terminal, the third control signal terminal, and the masking signal terminal;

[0008] The display substrate further includes: multiple first cross-level connection lines located in the non-display area;

[0009] At least one first cross-stage connection line is electrically connected to the first control signal terminal and signal input terminal of the first stage shift register and the cascaded signal output terminal of the previous stage shift register, respectively.

[0010] At least a portion of the orthographic projection of at least one first cross-stage connection line onto the substrate lies at least partially between the orthographic projections of the two shift registers connected by the first cross-stage connection line onto the substrate.

[0011] In an exemplary embodiment, it further includes: multiple second cross-level connection lines located in the non-display area; and a third node is provided in the shift sub-circuit;

[0012] The second cross-stage connection line is electrically connected to the second control signal terminal of the first-stage shift register and the third node in the shift sub-circuit of the first K-stage shift register, where K ≥ 2;

[0013] At least a portion of the orthographic projection of at least one second-stage crossover line onto the substrate overlaps at least a portion of the orthographic projection of at least one level shift register onto the substrate.

[0014] In an exemplary embodiment, it further includes: multiple third-level cross-connection lines located in the non-display area; and a fifth node is provided in the shift sub-circuit;

[0015] The third cross-stage connection line is electrically connected to the third control signal terminal of the first-stage shift register and the fifth node in the previous-stage shift register, respectively.

[0016] At least a portion of at least one third-level cross-connect line has its orthographic projection on the substrate located on the side of the orthographic projection of at least one level shift register on the substrate away from the display area.

[0017] In an exemplary embodiment, the gate drive circuit further includes: K virtual shift registers, each virtual shift register including a virtual shift sub-circuit and a virtual output sub-circuit, each virtual shift register including at least one virtual transistor and at least one virtual capacitor, the at least one virtual transistor including a first electrode and a second electrode, and the at least one virtual capacitor including a first plate and a second plate;

[0018] The shift sub-circuit of at least one shift register has the same circuit structure as the at least one virtual shift sub-circuit, and the output sub-circuit of at least one shift register has the same circuit structure as the at least one virtual shift sub-circuit.

[0019] At least one electrode of the first and second terminals of at least one virtual transistor is electrically connected to a first power supply terminal or a second power supply terminal, and at least one plate of the first and second terminals of at least one virtual capacitor is electrically connected to the first power supply terminal or the second power supply terminal.

[0020] In an exemplary embodiment, the cascaded signal output terminal of the k-th stage virtual shift register is electrically connected to the signal input terminal of the (k+1)-th stage virtual shift register, and the cascaded signal output terminal of the K-th stage shift register is electrically connected to the signal input terminal of the first stage shift register, where 1≤k≤K-1 and K≥2.

[0021] In an exemplary embodiment, the gate drive circuit further includes: K virtual shift registers, each virtual shift register including: a virtual shift sub-circuit and a virtual output sub-circuit;

[0022] The number of the first cross-stage connection lines is N+K-1, where N is the number of shift registers included in the gate drive circuit, and at least one first cross-stage connection line extends at least partially along the second direction;

[0023] For at least one level shift register, the shift sub-circuit includes: a first transistor, a ninth transistor, a tenth transistor, and a fourteenth transistor; the output sub-circuit includes: a twenty-second transistor; the second terminals of the ninth and tenth transistors are electrically connected to the cascaded signal output terminal, the first terminals of the first and fourteenth transistors are electrically connected to the signal input terminal, and the control terminal of the twenty-second transistor is electrically connected to the first control signal terminal. For at least one level virtual shift register, the virtual shift sub-circuit includes: a first virtual transistor, a ninth virtual transistor, a tenth virtual transistor, and a fourteenth virtual transistor; the virtual output sub-circuit includes: a twenty-second virtual transistor; the second terminals of the ninth and tenth virtual transistors are electrically connected to the cascaded signal output terminal, the first terminals of the first and fourteenth virtual transistors are electrically connected to the signal input terminal, and the control terminal of the twenty-second virtual transistor is connected to either the first or second power supply terminal.

[0024] The kth first cross-stage connection line is electrically connected to the second pole of the ninth virtual transistor and the second pole of the tenth virtual transistor in the kth stage virtual shift register, as well as the first pole of the first virtual transistor and the first pole of the fourteenth virtual transistor in the (k+1)th stage virtual shift register.

[0025] The first cross-stage connection line of the Kth stage is electrically connected to the second pole of the ninth virtual transistor and the second pole of the tenth virtual transistor located in the Kth stage virtual shift register, as well as the first pole of the first transistor, the first pole of the fourteenth transistor, and the control pole of the twenty-second transistor in the first stage shift register.

[0026] The r-th first cross-stage connection line is electrically connected to the second pole of the ninth transistor and the second pole of the tenth transistor of the rK-th stage shift register, as well as the first pole of the first transistor, the first pole of the fourteenth transistor, and the control pole of the twenty-second transistor of the r-K+1-th stage shift register, where K+1≤r≤N+K-1.

[0027] In an exemplary embodiment, it further includes: a driving structure layer disposed on the substrate, the gate driving circuit disposed on the driving structure layer, at least one level shift register including: at least one transistor and at least one capacitor, at least one level virtual shift register including: at least one virtual transistor and at least one virtual capacitor, at least one transistor or virtual transistor including: an active pattern, a control electrode, a first electrode and a second electrode, at least one capacitor or virtual capacitor including: a first electrode plate and a second electrode plate;

[0028] The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

[0029] The semiconductor layer includes at least: an active pattern of at least one transistor located in at least one level shift register and an active pattern of at least one virtual transistor located in at least one level virtual shift register;

[0030] The first conductive layer includes at least: a first plate of a control electrode of at least one transistor and at least one capacitor located in at least one level shift register, and a first plate of a control electrode of at least one virtual transistor and at least one virtual capacitor located in at least one level virtual shift register;

[0031] The second conductive layer includes at least: a second plate of at least one capacitor located in at least one level shift register and a second plate of at least one virtual capacitor located in at least one level virtual shift register;

[0032] The third conductive layer includes at least: a first and a second electrode of at least one transistor located in at least one level shift register, a first and a second electrode of at least one transistor located in at least one level shift register, and at least one first cross-level connection line.

[0033] In an exemplary embodiment, the gate drive circuit further includes: K virtual shift registers, each virtual shift register including: a virtual shift sub-circuit and a virtual output sub-circuit;

[0034] The number of the second cross-stage connection lines is N, where N is the number of shift registers included in the gate drive circuit;

[0035] For at least one level shift register, the shift sub-circuit further includes: a sixth transistor and a seventh transistor; the output sub-circuit further includes: a twenty-third transistor; the second terminal of the sixth transistor and the first terminal of the seventh transistor are electrically connected to the third node, respectively; the control terminal of the twenty-third transistor is electrically connected to the second control signal terminal. For at least one level virtual shift register, the virtual shift sub-circuit further includes: a sixth virtual transistor and a seventh virtual transistor; the virtual output sub-circuit further includes: a twenty-third virtual transistor; the second terminal of the sixth virtual transistor and the first terminal of the seventh virtual transistor are electrically connected to the third node, respectively; the control terminal of the twenty-third virtual transistor is electrically connected to the second control signal terminal.

[0036] The s-th second cross-stage connection line is electrically connected to the second pole of the sixth virtual transistor and the first pole of the seventh virtual transistor of the s-th stage virtual shift register, as well as the control pole of the twenty-third transistor of the s-th stage shift register, 1≤s≤K;

[0037] The t-th second cross-stage connection line is electrically connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor of the tK-th stage shift register, as well as the control terminal of the twenty-third transistor of the t-th stage shift register, where K+1≤t≤N.

[0038] In an exemplary embodiment, at least one second-level connecting line extends at least partially along the second direction, and the shape of the at least one second-level connecting line is a broken line, including K-1 bends;

[0039] The first end of the s-th second cross-stage connection line is electrically connected to the second pole of the sixth virtual transistor and the first pole of the seventh virtual transistor of the s-th stage virtual shift register, and the second end of the s-th second cross-stage connection line is electrically connected to the control pole of the twenty-third transistor of the s-th stage shift register.

[0040] The first end of the t-th second cross-stage connection line is electrically connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor of the tK-th stage shift register, and the second end of the t-th second cross-stage connection line is electrically connected to the control terminal of the twenty-third transistor of the t-th stage shift register.

[0041] In an exemplary embodiment, the line connecting the second end of the m-th second span-level connecting line and the first end of the (m+K)-th second span-level connecting line intersects at least one bend in the (m+1)-m to (m+K-1)-th second span-level connecting lines, where 1≤m≤N.

[0042] In an exemplary embodiment, it further includes: a driving structure layer disposed on the substrate, the gate driving circuit disposed on the driving structure layer, at least one level shift register including: at least one transistor and at least one capacitor, at least one level virtual shift register including: at least one virtual transistor and at least one virtual capacitor, at least one transistor or virtual transistor including: an active pattern, a control electrode, a first electrode and a second electrode, at least one capacitor or virtual capacitor including: a first electrode plate and a second electrode plate;

[0043] The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

[0044] The semiconductor layer includes at least: an active pattern of at least one transistor located in at least one level shift register and an active pattern of at least one virtual transistor located in at least one level virtual shift register;

[0045] The first conductive layer includes at least: a first plate of a control electrode of at least one transistor and at least one capacitor located in at least one level shift register, and a first plate of a control electrode of at least one virtual transistor and at least one virtual capacitor located in at least one level virtual shift register;

[0046] The second conductive layer includes at least: a second plate of at least one capacitor located in at least one level shift register and a second plate of at least one virtual capacitor located in at least one level virtual shift register;

[0047] The third conductive layer includes at least: a first electrode and a second electrode of at least one transistor located in at least one level shift register;

[0048] The fourth conductive layer includes at least one second cross-level connection line.

[0049] In an exemplary embodiment, at least one second cross-level connection line includes: a first connection portion and a second connection portion disposed in different layers and interconnected with each other; at least one of the first connection portion and the second connection portion extends at least partially along a second direction;

[0050] The first connection part of the second cross-stage connection line of the sth order is electrically connected to the second pole of the sixth virtual transistor and the first pole of the seventh virtual transistor of the sth stage virtual shift register, and the second connection part of the second cross-stage connection line of the sth order is electrically connected to the control pole of the twenty-third transistor of the sth stage shift register.

[0051] The first connection of the t-th second cross-stage connection line is electrically connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor of the tK-th stage shift register, and the second connection of the t-th second cross-stage connection line is electrically connected to the control terminal of the twenty-third transistor of the t-th stage shift register.

[0052] In an exemplary embodiment, the shape of the second connection portion of at least one second cross-level connection line is a broken line shape, and includes a bent portion;

[0053] The line connecting the end of the second connecting part of the mth second-level connecting line away from the first connecting part and the end of the first connecting part of the (m+K)th second-level connecting line away from the second connecting part intersects the bend of the second connecting part of the (m+1)th to (m+K-1)th second-level connecting lines, where 1≤m≤N.

[0054] In an exemplary embodiment, it further includes: a driving structure layer disposed on the substrate, the gate driving circuit disposed on the driving structure layer, at least one level shift register including: at least one transistor and at least one capacitor, at least one level virtual shift register including: at least one virtual transistor and at least one virtual capacitor, at least one transistor or virtual transistor including: an active pattern, a control electrode, a first electrode and a second electrode, at least one capacitor or virtual capacitor including: a first electrode plate and a second electrode plate;

[0055] The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0056] The semiconductor layer includes at least: an active pattern of at least one transistor located in at least one level shift register and an active pattern of at least one virtual transistor located in at least one level virtual shift register;

[0057] The first conductive layer includes at least: a first plate of a control electrode of at least one transistor and at least one capacitor located in at least one level shift register, and a first plate of a control electrode of at least one virtual transistor and at least one virtual capacitor located in at least one level virtual shift register;

[0058] The second conductive layer includes at least: a second plate of at least one capacitor located in at least one level shift register and a second plate of at least one virtual capacitor located in at least one level virtual shift register;

[0059] The third conductive layer includes at least: a first electrode and a second electrode of at least one transistor located in at least one level shift register;

[0060] The fourth conductive layer includes at least: a first connection portion of at least one second cross-level connection line;

[0061] The fifth conductive layer includes at least one second connection portion of at least one second cross-level connection line.

[0062] In an exemplary embodiment, the gate drive circuit further includes: K virtual shift registers, each virtual shift register including: a virtual shift sub-circuit and a virtual output sub-circuit;

[0063] The number of the third cross-stage connection lines is N+K-1, where N is the number of shift registers included in the gate drive circuit, and at least one third cross-stage connection line extends at least partially along the second direction;

[0064] For at least one level shift register, the shift sub-circuit further includes: a fourth transistor, and the output sub-circuit further includes: a twenty-fifth transistor, the second terminal of the fourth transistor is electrically connected to the fifth node, and the twenty-fifth transistor is electrically connected to the third control signal terminal; for at least one level virtual shift register, the virtual shift sub-circuit further includes: a fourth virtual transistor, and the virtual output sub-circuit further includes: a twenty-fifth virtual transistor, the second terminal of the fourth virtual transistor is electrically connected to the fifth node, and the control terminal of the twenty-fifth virtual transistor is electrically connected to the third control signal terminal;

[0065] The kth third cross-stage connection line is electrically connected to the second electrode of the fourth virtual transistor located in the kth stage virtual shift register and the control electrode of the twenty-fifth virtual transistor in the (k+1)th stage virtual shift register, respectively.

[0066] The third cross-stage connection line of the Kth stage is electrically connected to the second pole of the fourth virtual transistor located in the Kth stage virtual shift register and the control pole of the twenty-fifth transistor in the first stage shift register, respectively.

[0067] The r-th third cross-stage connection line is electrically connected to the second terminal of the fourth transistor of the rK-th stage shift register and the control terminal of the twenty-fifth transistor of the r-K+1-th stage shift register, respectively, where K+1≤r≤N+K-1.

[0068] In an exemplary embodiment, it further includes: a driving structure layer disposed on the substrate, the gate driving circuit disposed on the driving structure layer, at least one level shift register including: at least one transistor and at least one capacitor, at least one level virtual shift register including: at least one virtual transistor and at least one virtual capacitor, at least one transistor or virtual transistor including: an active pattern, a control electrode, a first electrode and a second electrode, at least one capacitor or virtual capacitor including: a first electrode plate and a second electrode plate;

[0069] The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0070] The semiconductor layer includes at least: an active pattern of at least one transistor located in at least one level shift register and an active pattern of at least one virtual transistor located in at least one level virtual shift register;

[0071] The first conductive layer includes at least: a first plate of a control electrode of at least one transistor and at least one capacitor located in at least one level shift register, and a first plate of a control electrode of at least one virtual transistor and at least one virtual capacitor located in at least one level virtual shift register;

[0072] The second conductive layer includes at least: a second plate of at least one capacitor located in at least one level shift register and a second plate of at least one virtual capacitor located in at least one level virtual shift register;

[0073] The third conductive layer includes at least: the first and second poles of at least one transistor located in at least one level shift register, the first and second poles of at least one transistor located in at least one level shift register, and at least one third cross-level connection line.

[0074] In an exemplary embodiment, it further includes: a first power signal line group disposed on the substrate and located in a non-display area, the first power signal line group including: a plurality of first power lines, at least one first power line extending at least partially along a second direction, and the plurality of first power lines arranged sequentially along a direction close to the display area;

[0075] At least one shift register includes: a fifth transistor, an eighth transistor, a ninth transistor, a thirteenth transistor, a nineteenth transistor, a twenty-fourth transistor, and a second capacitor;

[0076] The first power line is connected to the first terminal of the fifth transistor; the second power line is connected to the first terminal of the eighth transistor, the first terminal of the ninth transistor, the first terminal of the thirteenth transistor, and the second plate of the second capacitor; the third, fourth, and fifth power lines are connected to the first terminal of the nineteenth transistor; and the third power line is also connected to the first terminal of the twenty-fourth transistor.

[0077] The width of at least one of the fourth and fifth first power lines is greater than the width of at least one of the first, second, and third first power lines.

[0078] In an exemplary embodiment, it further includes: a second power signal line group disposed on the substrate and located in a non-display area; the second power signal line group includes: a plurality of second power lines; at least one second power line extends at least partially along a second direction, and the plurality of second power lines are arranged sequentially along a direction close to the display area;

[0079] At least one shift register includes: a third transistor, a tenth transistor, a twentieth transistor, a twenty-fifth transistor, and a fourth capacitor;

[0080] The first second power line is connected to the first terminal of the third transistor and the first terminal of the twenty-fifth transistor, the second second power line is connected to the first terminal of the tenth transistor, and the third second power line is connected to the first terminal of the twentieth transistor and the second plate of the fourth capacitor.

[0081] The orthographic projection of the first power line on the substrate is located between the orthographic projection of the first second power line on the substrate and the orthographic projection of the second second power line on the substrate. The orthographic projection of at least one of the signal lines among the second, third, fourth, and fifth power lines on the substrate is located between the orthographic projection of the second second power line on the substrate and the orthographic projection of the third second power line on the substrate.

[0082] The width of at least one signal line in the fourth and fifth first power lines is greater than the width of at least one signal line in the first and second second power lines;

[0083] The width of the third second power line is greater than the width of at least one of the following signal lines: the first first power line, the second first power line, the third first power line, the first second power line, the second second power line, and the third power line.

[0084] In an exemplary embodiment, it further includes: a clock signal line group and an initial signal line group disposed on the substrate and located in a non-display area. The clock signal line group includes: a first clock signal line and a second clock signal line. The initial signal line group includes: a first initial signal line and a second initial signal line. At least one of the first clock signal line, the second clock signal line, the first initial signal line and the second initial signal line extends at least partially along a second direction.

[0085] The orthographic projection of the clock signal line group on the substrate is located between the orthographic projection of the first second power line on the substrate and the orthographic projection of the first first power line on the substrate. The orthographic projection of the first initial signal line on the substrate is located on the side of the first second power line on the substrate away from the display area. The orthographic projection of the second initial signal line on the substrate is located between the orthographic projection of the first first power line on the substrate and the orthographic projection of the second second power line on the substrate.

[0086] In an exemplary embodiment, it further includes: a masking signal line and a third power line disposed on the substrate and located in a non-display area, wherein at least one of the masking signal line and the third power line extends at least partially along a second direction;

[0087] The orthographic projection of the masking signal line on the substrate is located between the orthographic projections of the second first power line and the third first power line on the substrate, and the orthographic projection of the third power line on the substrate is located between the orthographic projections of the first first power line and the second initial signal line on the substrate.

[0088] In an exemplary embodiment, the orthographic projection of the at least one second cross-level connection line on the substrate is located between the orthographic projection of the second first power line on the substrate and the orthographic projection of the masking signal line on the substrate.

[0089] In an exemplary embodiment, the orthographic projection of the at least one third cross-level connection line on the substrate is located on the side of the orthographic projection of the first initial signal line on the substrate that is away from the display area.

[0090] In an exemplary embodiment, the circuit further includes: multiple signal lines; the gate driving circuit further includes: at least one virtual shift register; and the display substrate further includes: a driving structure layer disposed on the substrate.

[0091] The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

[0092] The plurality of signal lines are disposed on the fourth conductive layer, and the orthographic projection of at least one of the signal lines on the substrate at least partially overlaps with the orthographic projections of at least one level shift register and at least one level virtual shift register on the substrate.

[0093] In an exemplary embodiment, the shift sub-circuit includes: a first transistor, a seventh transistor, a ninth transistor, a tenth transistor, and a fourteenth transistor; the output sub-circuit includes: an eighteenth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a twenty-sixth transistor; at least one transistor includes: an active pattern.

[0094] The length of the active pattern of the first transistor along the first direction is greater than the length of at least one of the active patterns of the third transistor, the seventh transistor, the fourteenth transistor, the eighteenth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, and the twenty-sixth transistor along the first direction.

[0095] The length of at least one of the active patterns of the ninth transistor and the tenth transistor along the first direction is greater than the length of at least one of the active patterns of the third transistor, the seventh transistor, the fourteenth transistor, the eighteenth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, and the twenty-sixth transistor along the first direction.

[0096] The length of at least one of the active patterns of the nineteenth transistor and the twentieth transistor along the first direction is greater than the length of at least one of the active patterns of the ninth transistor and the tenth transistor along the first direction.

[0097] In an exemplary embodiment, the output sub-circuit includes: a twenty-first transistor and a twenty-second transistor;

[0098] The 22nd transistor and the 21st transistor are arranged sequentially and adjacently along the direction close to the display area.

[0099] In an exemplary embodiment, the output sub-circuit includes: a twenty-second transistor, a twenty-fourth transistor, and a sixth capacitor, wherein the sixth capacitor is electrically connected to the drive signal output terminal;

[0100] The orthogonal projection of the sixth capacitor onto the substrate lies between the orthogonal projections of the twenty-fourth transistor onto the substrate and the orthogonal projections of the twentyth transistor onto the substrate.

[0101] Secondly, this disclosure also provides a display device, comprising: the aforementioned display substrate.

[0102] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0103] Overview of the attached figures

[0104] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0105] Figure 1 is a schematic diagram of a display device;

[0106] Figure 2A is a schematic diagram of a planar structure of a display substrate;

[0107] Figure 2B is a schematic diagram of a planar structure of a display substrate;

[0108] Figure 2C is a schematic diagram of a planar structure of a display substrate;

[0109] Figure 3 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0110] Figure 4 is a timing diagram of the pixel driving circuit provided in Figure 3;

[0111] Figure 5 is a schematic diagram of a shift register;

[0112] Figure 6 is a schematic diagram of the output sub-circuit;

[0113] Figure 7 shows the equivalent circuit diagram of the shift register;

[0114] Figure 8 is a timing diagram of the shift sub-circuit in the shift register provided in Figure 7;

[0115] Figure 9 shows the timing diagram of some shift registers;

[0116] Figure 10 is a schematic diagram of a display substrate;

[0117] Figure 11 is a schematic diagram of a gate drive circuit;

[0118] Figure 12 is another schematic diagram of the gate drive circuit;

[0119] Figure 13 is a schematic diagram of the structure of a first-level virtual shift register;

[0120] Figure 14 is another schematic diagram of the gate drive circuit;

[0121] Figure 15 is a schematic diagram of the second cross-level connection line;

[0122] Figure 16 is a schematic diagram of the second cross-level connection line;

[0123] Figure 17 is a cross-sectional view along the AA direction of Figures 15 and 16;

[0124] Figure 18 is another structural schematic diagram of the second cross-level connecting line;

[0125] Figure 19 is a cross-sectional view along direction AA in Figure 18;

[0126] Figure 20 is a schematic diagram of the structure of a display substrate including the second cross-level connection line provided in Figure 15;

[0127] Figure 21 is a schematic diagram showing the semiconductor layer pattern formed on the first and second display substrates;

[0128] Figure 22 is a schematic diagram of the first conductive layer pattern of the first display substrate and the second display substrate;

[0129] Figure 23 is a schematic diagram of the first and second display substrates after the first conductive layer pattern is formed;

[0130] Figure 24 is a schematic diagram of the patterns of the second conductive layer of the first display substrate and the second display substrate;

[0131] Figure 25 is a schematic diagram of the first and second display substrates after the second conductive layer pattern is formed.

[0132] Figure 26 is a schematic diagram of the first and second display substrates after the formation of the third insulating layer pattern;

[0133] Figure 27 is a schematic diagram of the pattern of the third conductive layer of the first display substrate and the second display substrate;

[0134] Figure 28 is a schematic diagram of the formation of the third conductive layer pattern on the first and second display substrates;

[0135] Figure 29 is a schematic diagram of the first and second display substrates after the fourth insulating layer pattern is formed;

[0136] Figure 30 is a schematic diagram of the pattern of the fourth insulating layer of the first display substrate;

[0137] Figure 31 is a schematic diagram of the first display substrate after the fourth insulating layer pattern has been formed;

[0138] Figure 32 is a schematic diagram of the fourth insulating layer pattern of the second display substrate;

[0139] Figure 33 is a schematic diagram of the second display substrate after the fourth insulating layer pattern is formed;

[0140] Figure 34 is a schematic diagram of the second display substrate after the first planarization layer pattern has been formed;

[0141] Figure 35 is a schematic diagram of the fifth conductive layer pattern of the second display substrate;

[0142] Figure 36 is a schematic diagram of the second display substrate after the fifth conductive layer pattern has been formed.

[0143] Detailed Explanation

[0144] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0145] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0146] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0147] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0148] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0149] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0150] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0151] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0152] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0153] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0154] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0155] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0156] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a gate driver, and a pixel array. The timing controller is connected to the data driver and the gate driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the gate driver is connected to multiple gate signal lines (G1 to Gm). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the gate signal lines and the data signal lines, respectively.

[0157] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages that will be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number.

[0158] In an exemplary embodiment, the gate driver can generate scan signals to be provided to gate signal lines G1, G2, G3, ... to Gm by receiving a clock signal, a gate start signal, etc., from a timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to the gate signal lines G1 to Gm. For example, the gate driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0159] Figure 2A is a schematic diagram of a planar structure of a display substrate (Figure 1), Figure 2B is a schematic diagram of a planar structure of a display substrate (Figure 22), and Figure 2C is a schematic diagram of a planar structure of a display substrate (Figure 23). As shown in Figures 2A to 2C, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a gate signal line and a data signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the gate signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0160] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light.

[0161] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0162] In an exemplary embodiment, a pixel unit may include three sub-pixels. These three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, etc., and this disclosure does not limit the specific arrangement. Figures 2A and 2B are illustrated using the example of a pixel unit comprising three sub-pixels. In Figure 2A, the three sub-pixels are arranged horizontally side-by-side, and in Figure 2B, the three sub-pixels are arranged in a triangular arrangement.

[0163] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a square, etc., and this disclosure does not limit the arrangement. Figure 2C illustrates an example where a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square.

[0164] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure, and this disclosure does not limit it in any way.

[0165] Figure 3 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 3, the pixel driving circuit may include seven transistors (first transistor M1 to seventh transistor M7) and one capacitor C. Specifically, the gate electrode of the first transistor M1 is electrically connected to the first reset signal line Reset1, the first terminal of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first transistor M1 is electrically connected to either the first node N1 or the third node N3. The gate electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2, the first terminal of the second transistor M2 is electrically connected to the first node N1, and the second terminal of the second transistor M2 is electrically connected to the third node N3. The gate electrode of the third transistor M3 is electrically connected to the first node N1, the first terminal of the third transistor M3 is electrically connected to the second node N2, and the second terminal of the third transistor M3 is electrically connected to the third node N3. The gate electrode of the fourth transistor M4 is electrically connected to the first scan signal line Gate1, and the first terminal of the fourth transistor M4 is electrically connected to the data signal line Data. The second terminal of the fourth transistor M4 is electrically connected to the second node N2; the gate electrode of the fifth transistor M5 is electrically connected to the light-emitting signal line EM, the first terminal of the fifth transistor M5 is electrically connected to the high-level power supply line VDD, and the second terminal of the fifth transistor M5 is electrically connected to the second node N2; the gate electrode of the sixth transistor M6 is electrically connected to the light-emitting signal line EM, the first terminal of the sixth transistor M6 is electrically connected to the third node N3, and the second terminal of the sixth transistor M6 is electrically connected to the fourth node N4; the gate electrode of the seventh transistor M7 is electrically connected to the second reset signal line Reset2, the first terminal of the seventh transistor M7 is electrically connected to the second initial signal line INIT2, and the second terminal of the seventh transistor M7 is electrically connected to the fourth node N4; the first plate of capacitor C is electrically connected to the first node N1, and the second plate of capacitor C is electrically connected to the high-level power supply line VDD. Figure 3 illustrates this using the example of the second terminal of the first transistor M1 being electrically connected to the first node N1.

[0166] In an exemplary embodiment, the signal of the second reset signal line Reset2 may be the same as the signal of the first scan signal line Gate1, or it may also be the same as the signal of the first reset signal line Reset1.

[0167] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), or oxide thin-film transistors (OPTs), or a combination of both. The active pattern of the LTPS is made of low-temperature polysilicon (LTPS), while the active pattern of the OPT is made of oxide. LTPS TFTs have advantages such as high mobility and fast charging, while OPTs have advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate to form an LTPO display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0168] In an exemplary embodiment, at least one of the first transistor M1 and the second transistor M2 has a transistor type opposite to that of at least one of the third transistor M3 to the seventh transistor M7. For example, the first transistor M1 and the second transistor M2 can be N-type transistors, and the third transistor M3 to the seventh transistor M7 can be P-type transistors; alternatively, the second transistor M2 can be an N-type transistor, and the first transistor M1 and the third transistor M3 to the seventh transistor M7 can be P-type transistors.

[0169] In an exemplary embodiment, the N-type transistor can be an oxide transistor, and the P-type transistor can be a low-temperature polysilicon transistor.

[0170] In an exemplary embodiment, the voltage value of the signal on the first initial signal line INIT1 is constant and is a DC signal; the voltage value of the signal on the first initial signal line INIT1 can be -3V.

[0171] In an exemplary embodiment, the voltage value of the signal on the second initial signal line INIT2 is constant and is a DC signal; the voltage value of the signal on the second initial signal line INIT2 can be 0V.

[0172] In an exemplary embodiment, the light-emitting device L can be electrically connected to the fourth node N4 and the low-level power line VSS, respectively.

[0173] In an exemplary embodiment, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0174] Figure 4 is a timing diagram of the pixel driving circuit shown in Figure 3. The following describes an exemplary embodiment of this disclosure through the operation of the pixel driving circuit in the display stage as illustrated in Figure 3. Figure 4 is illustrated with the example of the second transistor M2 being an N-type transistor, the first transistor M1, the third transistor M3 to the seventh transistor M7 being P-type transistors, and the signal of the second reset signal line Reset2 being the same as the signal of the first reset signal line Reset1. The pixel driving circuit in Figure 3 includes the first transistor M1 to the seventh transistor M7, a capacitor C, and nine signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, first reset signal line Reset1, second reset signal line Reset2, first initial signal line INIT1, second initial signal line INIT2, light emission signal line EM, and high-level power supply line VDD).

[0175] Referring to Figures 3 and 4, the operation of the pixel driving circuit can include:

[0176] In the first stage P1, called the initialization stage, the signals of the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals, the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written to the first node N1 or the third node N3 through the turned-on first transistor M1 to initialize (reset) the first node N1 or the third node N3, clearing its internal pre-stored voltage and completing the initialization. The seventh transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written to the fourth node N4 through the turned-on seventh transistor M7 to initialize (reset) the first electrode of the light-emitting device L, clearing its internal pre-stored voltage and completing the initialization.

[0177] The second stage, P2, is called the data writing stage or threshold compensation stage. The first scan signal line, Gate1, is low, and the second scan signal line, Gate2, is high. The data signal line, Data, outputs a data voltage. During this stage, since the first node, N1, is low, the third transistor, M3, is turned on. With the first scan signal line, Gate1, low, the fourth transistor, M4, is turned on. With the second scan signal line, Gate2, high, the second transistor, M2, is turned on. The data voltage output from Data is supplied to the first node, N1, via the turned-on fourth transistor, M4, N2, M3, and M2. The difference between the data voltage output from Data and the threshold voltage of the third transistor, M3, is charged into capacitor C until the voltage at the first node, N1, is Vd - |Vth|, where Vd is the data voltage output from Data and Vth is the threshold voltage of the third transistor, M3.

[0178] The third stage, P3, is called the light-emitting stage. The signal on the light-emitting signal line EM is a low-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output by the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, driving the light-emitting device L to emit light.

[0179] During the pixel driving circuit operation, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor M3 is:

[0180] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0181] Where I is the driving current flowing through the third transistor M3, which is also the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0182] In an exemplary embodiment, the light-emitting device L may include any one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode, and an inorganic light-emitting diode. For example, the light-emitting device may be a micrometer-scale light-emitting device, such as a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (Mini LED), or a micro organic light-emitting diode (Micro OLED), etc., and this disclosure does not limit this. For example, taking an organic light-emitting diode (OLED) as an example, the light-emitting device L may include a first electrode (e.g., as an anode), an organic light-emitting layer, and a second electrode (e.g., as a cathode) stacked together.

[0183] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together, and the emissive layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.

[0184] In an exemplary embodiment, the gate driver includes at least one gate driving circuit. The number of gate driving circuits depends on the gate signal lines. Taking a display substrate including the pixel driving circuit shown in FIG3 as an example, the gate driving circuit includes: a first scan driving circuit, a second scan driving circuit, and a light-emitting driving circuit. The first scan driving circuit is electrically connected to a first scan signal line, a first reset signal line, and a second reset signal line. The second scan driving circuit is electrically connected to a second scan signal line. The light-emitting driving circuit is electrically connected to a light-emitting signal line.

[0185] In an exemplary embodiment, any gate drive circuit in the gate driver may include a plurality of cascaded shift registers.

[0186] When a display product shows an image, the gate driving circuit generates a driving signal. Under the control of this driving signal, the pixel driving circuit initializes and writes data to achieve the display. The display refreshes the screen in every frame, meaning that the pixel driving circuit needs to be initialized and data written in each display frame. However, for some special screen displays (e.g., always-on display, static screens, or screens with infrequent updates), the pixel driving circuit does not need initialization and data writing in at least some display frames. A low-leakage pixel driving circuit can maintain the original brightness. Regardless of the type of image being displayed, the gate driving circuit of the display product generates a driving signal in every frame, repeatedly initializing and writing data to the pixel driving circuit, resulting in higher power consumption.

[0187] This disclosure provides a shift register. Figure 5 is a schematic diagram of the structure of a shift register. As shown in Figure 5, the shift register provided in this disclosure may include a shift sub-circuit and an output sub-circuit. The shift sub-circuit is electrically connected to a signal input terminal IN, a first clock signal terminal CK, a second clock signal terminal CB, a first power supply terminal VGH, a second power supply terminal VGL, a third power supply terminal NCX, a cascaded signal output terminal Carry, and an output sub-circuit. It is configured to, under the control of the signals from the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB, and the third power supply terminal NCX, provide a signal from either the first power supply terminal VGH or the second power supply terminal VGL to the cascaded signal output terminal Carry, and provide a signal from at least one of the signal input terminals IN, the second clock signal terminal CB, and the first power supply terminal VGH to the output sub-circuit. The output sub-circuit is also electrically connected to the first control signal terminal G1, the second control signal terminal G2, the third control signal terminal G3, the masking signal terminal MS, the first power supply terminal VGH, the second power supply terminal VGL, and the drive signal output terminal OUT, respectively. It is configured to provide the first power supply terminal VGH or the second power supply terminal VGL signal to the drive signal output terminal OUT under the control of the signal provided by the shift sub-circuit and the signals of the first control signal terminal G1, the second control signal terminal G2, the third control signal terminal G3, and the masking signal terminal MS.

[0188] This disclosure achieves the output of cascade signals for other stage shift registers by setting a shift sub-circuit to output cascade signal to the cascade signal output terminal, and setting an output sub-circuit to output drive signal for pixel drive circuit to the drive signal output terminal. This enables the cascade signal and drive signal to be output by different sub-circuits, and allows control over whether to output drive signal to pixel drive circuit while ensuring normal output of cascade signal.

[0189] The shift register provided in this embodiment, through the cooperation of the shift sub-circuit and the output sub-circuit, can lock the control signal of the corresponding masking signal terminal in the output sub-circuit under the control of the signals of the first control signal terminal, the second control signal terminal, and the third control signal terminal, according to the refresh rate requirements of the display area. This enables control of the signal output by the drive signal output terminal, allowing different refresh rates to be achieved in different areas of the display panel. That is, high and low refresh rates can coexist within the same frame. Furthermore, this embodiment is not limited to achieving different refresh rates in a fixed area of ​​the display panel, but can achieve dynamic refresh in any area, thereby reducing the power consumption of the display panel.

[0190] In an exemplary embodiment, the shift sub-circuit is provided with a first node N1 to an eighth node N8.

[0191] Figure 6 is a schematic diagram of the output sub-circuit. As shown in Figure 6, in an exemplary embodiment, the output sub-circuit may include: a first node control sub-circuit, a second node control sub-circuit, a third node control sub-circuit, a fourth node control sub-circuit, and an output control sub-circuit.

[0192] As shown in Figure 6, the first node control sub-circuit is electrically connected to the first node N1, the sixth node N6, the ninth node N9 and the tenth node N10 respectively, and is configured to provide the first node N1 or the sixth node N6 signal to the ninth node N9 under the control of the signals of the sixth node N6 and the tenth node N10.

[0193] As shown in Figure 6, the second node control sub-circuit is electrically connected to the first control signal terminal G1, the second control signal terminal G2, the third control signal terminal G3, the masking signal terminal MS, the second power supply terminal VGL, and the tenth node N10, respectively. It is configured to provide the masking signal terminal MS or the second power supply terminal VGL signal to the tenth node N10 under the control of the signals of the first control signal terminal G1, the second control signal terminal G2, and the third control signal terminal G3.

[0194] As shown in Figure 6, the third node control sub-circuit is electrically connected to the fourth node N4, the tenth node N10, and the eleventh node N11, respectively, and is configured to provide the signal of the fourth node N4 to the eleventh node N11 under the control of the signal of the tenth node N10.

[0195] As shown in Figure 6, the fourth node control sub-circuit is electrically connected to the drive signal output terminal OUT, the first power supply terminal VGH, the ninth node N9, and the eleventh node N11, respectively. It is configured to provide the first power supply terminal VGH signal to the eleventh node N11 under the control of the signals of the ninth node N9 and the drive signal output terminal OUT.

[0196] As shown in Figure 6, the output control sub-circuit is electrically connected to the first power supply terminal VGH, the second power supply terminal VGL, the drive signal output terminal OUT, the ninth node N9, and the eleventh node N11, respectively. It is configured to provide the first power supply terminal VGH or the second power supply terminal VGL signal to the drive signal output terminal OUT under the control of the signals of the ninth node N9 and the eleventh node N11.

[0197] Figure 7 is an equivalent circuit diagram of the shift register provided in the embodiment of this disclosure. Figure 7 is illustrated using the nth stage shift register as an example. Carry(n) refers to the cascaded signal output terminal of the nth stage shift register, and OUT(n) refers to the drive signal output terminal of the nth stage shift register.

[0198] In an exemplary embodiment, as shown in FIG7, the first node control sub-circuit may include a seventeenth transistor T17 and an eighteenth transistor T18. The control electrode and first electrode of the seventeenth transistor T17 are electrically connected to the sixth node N6, and the second electrode of the seventeenth transistor T17 is electrically connected to the ninth node N9. The control electrode of the eighteenth transistor T18 is electrically connected to the tenth node N10, the first electrode of the eighteenth transistor T18 is electrically connected to the first node N1, and the second electrode of the eighteenth transistor T18 is electrically connected to the ninth node N9.

[0199] Figure 7 shows an exemplary structure of the first node control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the first node control sub-circuit is not limited to this.

[0200] In an exemplary embodiment, as shown in FIG7, the second node control sub-circuit may include: a twenty-second transistor T22, a twenty-third transistor T23, and a twenty-fifth transistor T25. Specifically, the control electrode of the twenty-second transistor T22 is electrically connected to the first control signal terminal G1, the first electrode of the twenty-second transistor T22 is electrically connected to the tenth node N10, and the second electrode of the twenty-second transistor T22 is electrically connected to the second electrode of the twenty-third transistor T23; the control electrode of the twenty-third transistor T23 is electrically connected to the second control signal terminal G2, and the first electrode of the twenty-third transistor T23 is electrically connected to the masking signal terminal MS; the control electrode of the twenty-fifth transistor T25 is electrically connected to the third control signal terminal G3, the first electrode of the twenty-fifth transistor T25 is electrically connected to the second power supply terminal VGL, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the tenth node N10.

[0201] In an exemplary embodiment, the twenty-second transistor T22 and the twenty-third transistor T23 can be referred to as latching units. When the signals of the first control signal terminal G1 and the second control signal terminal G2 are both at valid levels, the twenty-second transistor T22 and the twenty-third transistor T23 are turned on. The signal of the masking signal terminal MS is written to the tenth node N10 and the fifth capacitor C5, thereby controlling whether the twentieth transistor T21 is turned on. Whether the twenty-first transistor T21 is turned on determines whether the signal of the fourth node N4 is written to the eleventh node N11. The signal of the eleventh node N11 determines whether the nineteenth transistor T19 is turned on, and whether the nineteenth transistor T19 is turned on determines whether the signal of the first power supply terminal VGH is written to the drive signal output terminal OUT.

[0202] Figure 7 shows an exemplary structure of the second node control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the second node control sub-circuit is not limited to this.

[0203] In an exemplary embodiment, the third node control sub-circuit includes: two twenty-first transistors T21 and a fifth capacitor C5. The control electrode of the first twenty-first transistor T21 is electrically connected to the tenth node N10, the first electrode of the first twenty-first transistor T21 is electrically connected to the fourth node N4, and the second electrode of the first twenty-first transistor T21 is electrically connected to the first electrode of the second twenty-first transistor T21; the control electrode of the second twenty-first transistor T21 is electrically connected to the tenth node N10, and the second electrode of the second twenty-first transistor T21 is electrically connected to the eleventh node N11; the first plate of the fifth capacitor C5 is electrically connected to the tenth node N10, and the second plate of the fifth capacitor C5 is electrically connected to the eleventh node N11.

[0204] Alternatively, in an exemplary embodiment, the third node control sub-circuit includes a twenty-first transistor T21 and a fifth capacitor C5, wherein the twenty-first transistor T21 is a dual-gate transistor. The control electrode of the twenty-first transistor T21 is electrically connected to the tenth node N10, the first electrode of the twenty-first transistor T21 is electrically connected to the fourth node N4, and the second electrode of the twenty-first transistor T21 is electrically connected to the eleventh node N11; the first plate of the fifth capacitor C5 is electrically connected to the tenth node N10, and the second plate of the fifth capacitor C5 is electrically connected to the eleventh node N11. Figure 7 illustrates an example where the third node control sub-circuit includes the twenty-first transistor T21 and the fifth capacitor C5, wherein the twenty-first transistor T21 is a dual-gate transistor.

[0205] The third node control sub-circuit in this disclosure includes two twenty-first transistors T21, or a twenty-first transistor T21 that is a dual-gate transistor, which can prevent the leakage current of the fourth node N4 from affecting the eleventh node N11 and can ensure the stability of the output signal of the drive signal output terminal OUT.

[0206] Figure 7 shows an exemplary structure of the third node control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the third node control sub-circuit is not limited to this.

[0207] In an exemplary embodiment, as shown in FIG7, the fourth node control sub-circuit may include: a twenty-fourth transistor T24 and a twenty-sixth transistor T26. The control electrode of the twenty-fourth transistor T24 is electrically connected to the ninth node N9, the first electrode of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal VGH, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the second electrode of the twenty-sixth transistor T26. The control electrode of the twenty-sixth transistor T26 is electrically connected to the drive signal output terminal OUT, and the first electrode of the twenty-sixth transistor T26 is electrically connected to the eleventh node N11.

[0208] In an exemplary embodiment, the fourth node control sub-circuit can be referred to as a stabilizing unit. When the signals at the ninth node N9 and the drive output signal terminal are low-level signals, i.e., when the shift register outputs a low-level signal, the twenty-fourth transistor T24 and the twenty-sixth transistor T26 are turned on, the high-level signal at the first power supply terminal VGH is written to the eleventh node N11, and the nineteenth transistor T19 is turned off. The configuration of the fourth node control sub-circuit can prevent the nineteenth transistor T19 from being accidentally turned on and causing leakage, avoid the erroneous output of the drive output signal terminal of the shift register, and improve the reliability of the shift register.

[0209] The configuration of the twenty-sixth transistor T26 in this disclosure can avoid the influence of the signal of the first power supply terminal VGH on the eleventh node N11 when the twenty-fourth transistor T24 leaks current, thus ensuring the stability of the eleventh node N11 and ensuring the normal operation of the nineteenth transistor T19.

[0210] Figure 7 shows an exemplary structure of the fourth node control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the fourth node control sub-circuit is not limited to this.

[0211] In an exemplary embodiment, as shown in FIG7, the output control sub-circuit may include: a nineteenth transistor T19, a twentieth transistor T20, a sixth capacitor C6, and a seventh capacitor C7. Specifically, the control electrode of the nineteenth transistor T19 is electrically connected to the eleventh node N11, the first electrode of the nineteenth transistor T19 is electrically connected to the first power supply terminal VGH, and the second electrode of the nineteenth transistor T19 is electrically connected to the drive signal output terminal OUT; the control electrode of the twentieth transistor T20 is electrically connected to the ninth node N9, the first electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL, and the second electrode of the twentieth transistor T20 is electrically connected to the drive signal output terminal OUT; the first plate of the sixth capacitor C6 is electrically connected to the ninth node N9, and the second plate of the sixth capacitor C6 is electrically connected to the drive signal output terminal OUT; the first plate of the seventh capacitor C7 is electrically connected to the eleventh node N11, and the second plate of the seventh capacitor C7 is electrically connected to the first power supply terminal VGH.

[0212] In this disclosure, the setting of the sixth capacitor C6 can improve the stability of the output signal of the drive signal output terminal OUT, and the setting of the seventh capacitor C7 can further ensure the stability of the signal of the eleventh node N11.

[0213] Figure 7 shows an exemplary structure of the output control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the output control sub-circuit is not limited to this.

[0214] In exemplary embodiments, the shift sub-circuit can be a circuit structure of 10T3C, 10T4C, 12T3C, 12T4C, 13T3C, 13T4C, 16T3C, or 16T4C, and this disclosure does not limit it in any way. Figure 7 is illustrated using 16T4C as an example.

[0215] In an exemplary embodiment, as shown in FIG7, the shift sub-circuit may include: a first transistor T1 to a sixteenth transistor T16 and a first capacitor C1 to a fourth capacitor C4. The control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first terminal of the first transistor T1 is electrically connected to the signal input terminal IN, and the second terminal of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first terminal of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second terminal of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first terminal of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second terminal of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the sixth node N6. The connections are as follows: the first terminal of the fourth transistor T4 is electrically connected to the second clock signal terminal CB, and the second terminal of the fourth transistor T4 is electrically connected to the fifth node N5; the control terminal of the fifth transistor T5 is electrically connected to the second node N2, and the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VGH; the second terminal of the fifth transistor T5 is electrically connected to the fifth node N5; the control terminal of the sixth transistor T6 is electrically connected to the eighth node N8, and the first terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal CB; the second terminal of the sixth transistor T6 is electrically connected to the third node N3; the control terminal of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and the first terminal of the seventh transistor T7 is electrically connected to the third node N3. The second terminal of the seventh transistor T7 is electrically connected to the fourth node N4; the control terminal of the eighth transistor T8 is electrically connected to the first node N1, the first terminal of the eighth transistor T8 is electrically connected to the first power supply terminal VGH, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the control terminal of the ninth transistor T9 is electrically connected to the fourth node N4, the first terminal of the ninth transistor T9 is electrically connected to the first power supply terminal VGH, and the second terminal of the ninth transistor T9 is electrically connected to the cascaded signal output terminal Carry; the control terminal of the tenth transistor T10 is electrically connected to the seventh node N7, the first terminal of the tenth transistor T10 is electrically connected to the second power supply terminal VGL, and the second terminal of the tenth transistor T10 is electrically connected to the cascaded signal output terminal Carry. Carry is electrically connected; the control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal VGL, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, and the second electrode of the eleventh transistor T11 is electrically connected to the eighth node N8; the control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VGL, the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, and the second electrode of the twelfth transistor T12 is electrically connected to the seventh node N7; the control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal NCX, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VGH, and the second electrode of the thirteenth transistor T13 is electrically connected to the first node N1;The control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK; the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN; the second electrode of the fourteenth transistor T14 is electrically connected to the first electrode of the fifteenth transistor T15; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL; the second electrode of the fifteenth transistor T15 is electrically connected to the sixth node N6; the first electrode of the control electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6; the second electrode of the sixteenth transistor T16 is electrically connected to the seventh node N7; the first plate of the first capacitor C1 is electrically connected to the eighth node N8; the second plate of the first capacitor C1 is electrically connected to the third node N3; the first plate of the second capacitor C2 is electrically connected to the fourth node N4; the second plate of the second capacitor C2 is electrically connected to the first power supply terminal VGH; the first plate of the third capacitor C3 is electrically connected to the sixth node N6; the second plate of the third capacitor C3 is electrically connected to the fifth node N5; the first plate of the fourth capacitor C4 is electrically connected to the cascaded signal output terminal Carry; the second plate of the fourth capacitor C4 is electrically connected to the second power supply terminal VGL. ;

[0216] In an exemplary embodiment, the first capacitor C1 can ensure the stability of the signal at the third node N3, the second capacitor C2 can ensure the stability of the signal at the fourth node N4, the third capacitor C3 can ensure the stability of the signal at the fifth node N5, and the fourth capacitor C4 can ensure the stability of the cascaded signal output terminal Carry.

[0217] In an exemplary embodiment, when the shift sub-circuit is a 10T3C circuit structure, the shift sub-circuit includes: a first transistor T1 to a tenth transistor T10 and a first capacitor C1 to a third capacitor C3.

[0218] In an exemplary embodiment, when the shift sub-circuit is a 10T4C circuit structure, the shift sub-circuit includes: a first transistor T1 to a tenth transistor T10 and a first capacitor C1 to a fourth capacitor C4.

[0219] In an exemplary embodiment, when the shift sub-circuit is a 12T3C circuit structure, the shift sub-circuit includes: a first transistor T1 to a twelfth transistor T12 and a first capacitor C1 to a third capacitor C3.

[0220] In an exemplary embodiment, when the shift sub-circuit is a 12T4C circuit structure, the shift sub-circuit includes: a first transistor T1 to a twelfth transistor T12 and a first capacitor C1 to a fourth capacitor C4.

[0221] In an exemplary embodiment, when the shift sub-circuit is a 13T3C circuit structure, the shift sub-circuit includes: a first transistor T1 to a thirteenth transistor T13 and a first capacitor C1 to a third capacitor C3.

[0222] In an exemplary embodiment, when the shift sub-circuit is a 13T4C circuit structure, the shift sub-circuit includes: a first transistor T1 to a thirteenth transistor T13 and a first capacitor C1 to a fourth capacitor C4.

[0223] In an exemplary embodiment, when the shift sub-circuit is a 16T3C circuit structure, the shift sub-circuit includes: a first transistor T1 to a sixteenth transistor T16 and a first capacitor C1 to a third capacitor C3.

[0224] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0225] In an exemplary embodiment, at least one of the first transistor T1 to the twenty-sixth transistor T26 may be a P-type transistor.

[0226] In an exemplary embodiment, the signal at the masking signal terminal MS can be a low-level signal or a high-level signal. When the signal at the masking signal terminal MS is a low-level signal, it can be -20V to -5V; when the signal at the masking signal terminal MS is a high-level signal, it can be 5V to 20V.

[0227] In an exemplary embodiment, the signal at either the first clock signal terminal CK or the second clock signal terminal CB is a square wave signal that repeats between high and low voltages. Exemplarily, the signal at the first clock signal terminal CK and the second clock signal terminal CB may have the same period and may be configured as phase-shifted signals. Here, the signal at the second clock signal terminal CB may be phase-shifted by half a cycle compared to the signal at the first clock signal terminal CK. The high-voltage period in each cycle of the signal at either the first clock signal terminal CK or the second clock signal terminal CB may be set to be longer than the low-voltage period.

[0228] In an exemplary embodiment, the signal at the first power supply terminal VGH can be a high-level signal, for example, 5V to 10V; the signal at the second power supply terminal VGL can be a low-level signal, for example, -10V to -5V.

[0229] In an exemplary embodiment, the third power supply terminal NCX is a low-level signal during the power-on initialization phase to prevent the ninth transistor T9 and the tenth transistor T10 of the last-stage control shift register from conducting simultaneously due to output signal delay, or it is a low-level signal during the abnormal power-off phase to prevent the ninth transistor T9 and the tenth transistor T10 from conducting simultaneously. The third power supply terminal NCX continuously provides a high-level signal during the normal display phase, that is, during the normal display phase, the thirteenth transistor T13 is turned off.

[0230] In an exemplary embodiment, any one of the first capacitors C1 to the seventh capacitor C7 can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, any one of the first capacitors C1 to the seventh capacitor C7 can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of any one of the first capacitors C1 to the seventh capacitor C7 includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0231] In an exemplary embodiment, the drive signal output from the shift register's drive signal output terminal is primarily used to control at least one transistor (e.g., a second transistor M2) in the pixel driving circuit of the display substrate. When the display substrate is in a refresh frame, the drive signal output terminal outputs a high-level signal for a period of time, and a low-level signal for the remaining time periods within a frame, controlling the second transistor M2 to conduct and thus refreshing the data voltage. When the display substrate is not in a refresh frame, the drive signal output terminal continuously outputs a low-level signal, and the second transistor M2 cannot conduct.

[0232] In an exemplary embodiment, the first control signal terminal G1 and the signal input terminal IN of at least one shift register are electrically connected to the cascaded signal output terminal Carry of the previous shift register. The electrical connection between the first control signal terminal G1 of at least one shift register and the cascaded signal output terminal Carry of the previous shift register in this disclosure allows the signal at the masking signal terminal MS to be written in advance, ensuring a more thorough writing process.

[0233] In an exemplary embodiment, the second control signal terminal G2 connected to at least one shift register is electrically connected to the third node N3 in the shift sub-circuit of the upper two shift registers. In this disclosure, since the second clock signal terminal CB provides a signal to the third node N3 when the sixth transistor T6 is turned on, the signal of the second control signal terminal G2 connected to at least one shift register (which is also the signal of the third node N3 in the shift sub-circuit of the upper two shift registers) can be considered a periodically changing clock signal.

[0234] In an exemplary embodiment, the third control signal terminal G3 connected to at least one level shift register is electrically connected to the fifth node N5 in the shift sub-circuit of the previous level shift register. The electrical connection between the third control signal terminal G3 connected to at least one level shift register and the fifth node N5 in the shift sub-circuit of the previous level shift register in this disclosure allows for the reset of the signal at the tenth node N10, ensuring a more thorough reset of the tenth node N10.

[0235] Figure 8 is a timing diagram of the shift sub-circuit in the shift register provided in Figure 7. Figure 7 is an example where the first transistor T1 to the sixteenth transistor T16 are all P-type transistors. During the operation of the shift register, the eleventh transistor T11, the twelfth transistor T12, and the fifteenth transistor T15 are continuously turned on, while the thirteenth transistor T13 is continuously turned off.

[0236] As shown in Figure 8, the operation of a shift sub-circuit provided in an exemplary embodiment may include the following stages:

[0237] In the first stage A1, i.e., the input stage, the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals, while the signal at the first clock signal terminal CK is low-level. The first transistor T1, the third transistor T3, and the fourteenth transistor T14 are turned on, while the seventh transistor T7 is turned off.

[0238] The first transistor T1, which is turned on, transmits the high-level signal from the signal input terminal IN to the first node N1, making the signal at the first node N1 high. The twelfth transistor T12, which is turned on, transmits the high-level signal from the first node N1 to the seventh node N7. The fourteenth and fifteenth transistors T14 and T15, which are turned on, transmit the high-level signal from the signal input terminal IN to the sixth node N6. The second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the sixteenth transistor T16 are turned off. Meanwhile, the third transistor T3 and the eleventh transistor T11, which are turned on, transmit the low-level signal from the second power supply terminal VGL to the second node N2 and the eighth node N8. The fifth transistor T5 and the sixth transistor T6 are turned on, making the signal at the fifth node N5 high. The signal at the third node N3 is also high. Because the seventh transistor T7 is turned off, the signal at the fourth node N4 remains low. The ninth transistor T9 is turned off, and the signal at the cascaded output terminal Carry remains low. In the first stage A1, the signals of the first node N1, the third node N3, the fifth node N5, the sixth node N6 and the seventh node N7 are high-level signals, the second node N2, the fourth node N4 and the eighth node N8 are low-level signals, and the signal of the cascaded output signal terminal Carry is a low-level signal.

[0239] In the second stage A2, i.e., the output stage, the signal at the second clock signal terminal CB is a low-level signal, while the signals at the signal input terminal IN and the first clock signal terminal CK are high-level signals. The first transistor T1, the third transistor T3, and the fourteenth transistor T14 are off, and the seventh transistor T7 is on.

[0240] Under the action of the first capacitor C1, the signals at the second node N2 and the eighth node N8 remain at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on. The low-level signal at the second clock signal terminal CB is transmitted to the third node N3 and the fourth node N4 through the turned-on sixth transistor T6 and seventh transistor T7. The signal at the first power supply terminal VGH is written to the fifth node N5, and the ninth transistor T9 is turned on. The high-level signal at the first power supply terminal VGH is transmitted to the cascaded output signal terminal Carry through the turned-on ninth transistor T9. Under the action of the third capacitor C3, the sixth node N6 maintains the high-level signal of the previous stage, the first node N1 and the seventh node N7 maintain the high-level signal of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. Therefore, in this stage, the signals at the first node N1, the fifth node N5, the sixth node N6, and the seventh node N7 are high-level signals, the second node N2, the third node N3, the fourth node N4, and the eighth node N8 are low-level signals, and the signal at the cascaded output signal terminal Carry is a high-level signal.

[0241] In the third stage A3, the signal at the first clock signal terminal CK is low, while the signals at the signal input terminal IN and the second clock signal terminal CB are high. The first transistor T1, the third transistor T3, and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0242] Under the influence of the second capacitor C2, the fourth node N4 maintains the low-level signal from the previous stage, and the ninth transistor T remains on. The high-level signal of the first power supply terminal VGH is transmitted to the cascaded output signal terminal Carry through the on-circuit ninth transistor T9. The on-circuit first transistor T1 and twelfth transistor T12 transmit the high-level signal of the signal input terminal IN to the first node N1 and the seventh node N7. The on-circuit fourteenth transistor T14 and fifteenth transistor T15 transmit the high-level signal of the signal input terminal IN to the sixth node N6. The second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the sixteenth transistor T16 are off. In addition, the on-circuit third transistor T3 and eleventh transistor T11 transmit the low-level signal of the second power supply terminal VGL to the second node N2 and the eighth node N8. The fifth transistor T5 and the sixth transistor T6 are on, and the high-level signal of the second clock signal terminal CB is written to the third node N3. The high-level signal of the first power supply terminal VGH is written to the fifth node N5. In this stage, the signals of the first node N1, the third node N3, the fifth node N5, the sixth node N6 and the seventh node N7 are high-level signals, the signals of the second node N2, the fourth node N4 and the eighth node N8 are low-level signals, and the signal of the cascaded output signal terminal Carry is a high-level signal.

[0243] In stage A4, the signals at the signal input terminal IN and the second clock signal terminal CB are low, while the signal at the first clock signal terminal CK is high. The first transistor T1, the third transistor T3, and the fourteenth transistor T14 are off, while the seventh transistor T7 is on.

[0244] Under the action of the first capacitor C1, the signals at the second node N2 and the eighth node N8 remain at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on. The low-level signal at the second clock signal terminal CB is transmitted to the third node N3 and the fourth node N4 through the turned-on sixth transistor T6 and seventh transistor T7. The signal at the first power supply terminal VGH is written to the fifth node N5, and the ninth transistor T9 is turned on. The high-level signal at the first power supply terminal VGH is transmitted to the cascaded output signal terminal Carry through the turned-on ninth transistor T9. Under the action of the third capacitor C3, the sixth node N6 maintains the high-level signal of the previous stage, the first node N1 and the seventh node N7 maintain the high-level signal of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. Therefore, in this stage, the signals at the first node N1, the fifth node N5, the sixth node N6, and the seventh node N7 are high-level signals, the second node N2, the third node N3, the fourth node N4, and the eighth node N8 are low-level signals, and the signal at the cascaded output signal terminal Carry is a high-level signal.

[0245] In stage A5, the signal at the second clock signal terminal CB is high, while the signals at the signal input terminal IN and the first clock signal terminal CK are low. The first transistor T1, the third transistor T3, and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0246] The first transistor T1 and the twelfth transistor T12 transmit the low-level signal of the signal input terminal IN to the first node N1 and the seventh node N7. The fourteenth transistor T14 and the fifteenth transistor T15 transmit the low-level signal of the signal input terminal IN to the sixth node N6. The second transistor T2, the fourth transistor T4, the eighth transistor T8 / the tenth transistor T10, and the sixteenth transistor T16 are turned on. The sixth transistor T6 transmits the high-level signal of the second clock signal terminal CB to the third node N3. The fourth transistor T4 transmits the high-level signal of the second clock signal terminal CB to the fifth node N5. The sixteenth transistor T16 continuously transmits the low-level signal of the sixth node N6 to the seventh node N7. The second transistor T2 transmits the low-level signal of the first clock signal terminal CK to the second node N2. The signal of the second node N2 is a low-level signal. The second node N2 and the eighth node N8 continue to maintain the low-level signal of the previous stage. The fifth transistor T5 and the sixth transistor T6 are turned on, and the high-level signal of the first power supply terminal VGH is written to the fifth node N5. The signal at the second clock signal terminal CB is high, and the seventh transistor T7 is off. Additionally, the high-level signal at the first power supply terminal VGH is transmitted to the fourth node N4 via the conducting eighth transistor T8, while the ninth transistor T9 is off. The low-level signal at the second power supply terminal VGL is transmitted to the cascaded output signal terminal Carry via the conducting tenth transistor T10, causing the signal at Carry to become low. During this stage, the signals at the first node N1, second node N2, sixth node N6, seventh node N7, and eighth node N8 are low, while the signals at the third node N3, fourth node N4, and fifth node N5 are high, and the signal at the cascaded output signal terminal Carry is low.

[0247] In an exemplary embodiment, when at least one level shift register is in operation, the signal of the fifth node N5 of the previous level shift register is continuously high, that is, the signal of the third control signal terminal G3 of at least one level shift register is high. Therefore, the twenty-fifth transistor T25 in this level shift register is continuously disconnected.

[0248] In an exemplary embodiment, when the signal at the cascaded signal output terminal Carry in the shift register is low, the signals at the first node N1 and the sixth node N6 are low, and the signal at the fourth node N4 is high. The seventeenth transistor T17 is turned on, and the low-level signal at the sixth node N6 is transmitted to the ninth node N9 through the turned-on seventeenth transistor T17. The twentieth transistor T20 and the twenty-fourth transistor T24 are turned on, and the low level of the second power supply terminal VGL is written to the drive signal output terminal OUT. At this time, the twenty-sixth transistor T26 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the eleventh node N11 through the turned-on twenty-fourth transistor T24 and the twenty-sixth transistor T26. The nineteenth transistor T19 is turned on. At this time, regardless of whether the signals at the first control signal terminal G1 and the second control signal terminal G2 are high or low, the signal at the drive signal output terminal OUT of the shift register remains low. That is, when the signal at the cascaded signal output terminal CARRY in the shift register provided in this disclosure is low, the signal at the drive signal output terminal OUT is also low and outputs a low-level signal.

[0249] In an exemplary embodiment, when the Carry signal at the cascaded signal output terminal of the shift register is high, the signals of the first node N1 and the sixth node N6 are high, and the signal of the fourth node N4 is low. When the signal of the sixth node N6 is high, the seventeenth transistor T17 is off, and the signals of the ninth node N9 and the eleventh node N11 both depend on the signal of the tenth node N10.

[0250] When the signals at the first control signal terminal G1 and the second control signal terminal G2 are low-level signals, the twenty-second transistor T22 and the twenty-third transistor T23 are turned on, and the signal at the masking signal terminal MS is written into the tenth node N10 and the fifth capacitor C5. If the signal at the masking signal terminal MS is low, the signal at the tenth node N10 is low, the eighteenth transistor T18 is turned on, the high-level signal at the first node N1 is written to the ninth node N9, the twentieth transistor T20 and the twenty-fourth transistor T24 are turned off, the twenty-first transistor T21 is turned on, the low-level signal at the fourth node N4 is written to the eleventh node N11, the nineteenth transistor T19 is turned on, and the high-level signal at the first power supply terminal VGH is written to the drive signal output terminal OUT. If the signal at the masking signal terminal MS is high, the signal at the tenth node N10 is high, the eighteenth transistor T18 is turned off, the high-level signal at the first node N1 cannot be written to the ninth node N9, the ninth node N9 is floating, the twenty-first transistor T21 is turned off, the low-level signal at the fourth node N4 cannot be written to the eleventh node N11, and the high-level signal at the first power supply terminal VGH cannot be written to the drive signal output terminal OUT. At this time, the shift register has no output.

[0251] In an exemplary embodiment, since the signal of the second control signal terminal G2 connected to at least one shift register (which is also the signal of the third node N3 in the shift sub-circuit of the upper two shift registers) can be regarded as a periodically changing clock signal, the conduction time of the twenty-second transistor T22 and the twenty-third transistor T23 is the time when the clock signal of the second clock signal terminal of the upper two shift registers is a low-level signal. When the twenty-second transistor T22 and the twenty-third transistor T23 are conducting and the signal of the masking signal terminal MS is a high-level signal, when the twenty-third transistor T23 is turned off, the signal of the masking signal terminal MS cannot be written to the tenth node N10. At this time, under the action of the fifth capacitor C5, the signal of the tenth node N10 remains a high-level signal, the eighteenth transistor T18 and the twenty-first transistor T21 are turned off, the first node N1 and the sixth node N6 will not affect the ninth node N9. At this time, the ninth node N9 remains a low-level signal, the twentieth transistor T20 is conducting, and the drive signal output terminal OUT outputs a low-level signal.

[0252] Figure 9 is a timing diagram of a portion of the shift registers. The following description, using the shift register shown in Figure 7 as an example and referring to the signal timing diagram in Figure 9, illustrates the working principle of the shift registers provided in this embodiment of the present disclosure for controlling different refresh rates in different areas of the display panel. Figure 9 is an example of the first four stages of shift registers.

[0253] In an exemplary embodiment, as shown in FIG9, the display substrate may include: a first clock signal line CLK1 and a second clock signal line CLK2, at least the first clock signal terminal of the shift register is electrically connected to one of the first clock signal lines CLK1 and CLK2, at least the first clock signal terminal of the shift register is electrically connected to the other of the first clock signal lines CLK1 and CLK2, the first clock signal terminals of adjacent shift registers are connected to different clock signal lines, and the second clock signal terminals of adjacent shift registers are connected to different clock signal lines.

[0254] The signal timing diagram shown in Figure 9 only takes the first four stages of shift registers as an example. For example, when the areas corresponding to the first and second rows of sub-pixels in the display substrate are high refresh rate areas, and the third and fourth rows of sub-pixels are low refresh rate areas, when the signal of the cascaded signal output terminal Carry(1) of the first stage shift register and the signal of the third node of the upper two stage shift registers are both low level signals (at time t11), the twenty-second transistor T22 and the twenty-third transistor T23 are both turned on, that is, at time t1, the low level signal of the masking signal terminal MS is latched in the fifth capacitor C5. When the cascaded signal output terminal Carry(1) of the first stage shift register outputs a high level (at time t12), under the action of the fifth capacitor C5, The tenth node N10 maintains the low level signal of the masking signal terminal MS at time t11, then the twenty-first transistor T21 and the nineteenth transistor T19 are turned on. At time t12, the drive signal output terminal OUT(1) of the first stage shift register outputs the high level signal of the first power supply terminal VGH, realizing the high refresh rate of the first row of sub-pixels in the display area. The duration of the high level signal of the first power supply terminal VGH output by the drive signal output terminal OUT(1) of the first stage shift register can be set according to actual needs.

[0255] As shown in Figure 9, when the signal at the cascaded signal output terminal Carry(2) of the second-stage shift register and the signal at the third node of the two upper-stage shift registers are both low-level signals (at time t21), the twenty-second transistor T22 and the twenty-third transistor T23 are both turned on, that is, at time t21, the low-level signal of the masking signal terminal MS is latched in the fifth capacitor C5; when the cascaded signal output terminal Carry(2) of the second-stage shift register outputs a high level (at time t22), under the action of the fifth capacitor C5, the tenth node N10 maintains the low-level signal of the masking signal terminal MS at time t21, then the twenty-first transistor T21 and the nineteenth transistor T19 are turned on, then at time t22, the drive signal output terminal OUT(2) of the second-stage shift register outputs a high-level signal of the first power supply terminal VGH, realizing the high refresh rate of the second row of sub-pixels in the display area.

[0256] As shown in Figure 9, when the signal of Carry(3) at the cascaded signal output terminal of the third-stage shift register and the signal of the third node of the first-stage shift register are both low-level signals (at time t31), the twenty-second transistor T22 and the twenty-third transistor T23 are both turned on, that is, at time t31, the high-level signal of the masking signal terminal MS is latched in the fifth capacitor C5; when Carry(3) at the cascaded signal output terminal of the third-stage shift register outputs a high level (at time t32), under the action of the fifth capacitor C5, the tenth node N10 maintains the high-level signal of the masking signal terminal MS at time t31, then the twenty-first transistor T21 is turned off, and the drive signal output terminal OUT(3) of the third-stage shift register cannot output the high-level signal of the first power supply terminal VGH, thus realizing the low refresh rate of the third row of sub-pixels in the display area;

[0257] As shown in Figure 9, when the signal at the cascaded signal output terminal Carry(4) of the fourth-stage shift register and the signal at the third node of the second-stage shift register are both low-level signals (at time t41), the twenty-second transistor T22 and the twenty-third transistor T23 are both turned on. That is, at time t41, the high-level signal of the masking signal terminal MS is latched in the fifth capacitor C5. When the cascaded signal output terminal Carry(4) of the fourth-stage shift register outputs a high level (at time t42), under the action of the fifth capacitor C5, the tenth node N10 maintains the high-level signal of the masking signal terminal MS at time t41. Then the twenty-first transistor T21 is turned off, and the drive signal output terminal OUT(4) of the fourth-stage shift register cannot output the high-level signal of the first power supply terminal VGH, thus realizing the low refresh rate of the third row of sub-pixels in the display area.

[0258] Therefore, when a low refresh rate is required in a certain area of ​​the display substrate, a high-level signal is supplied through the masking signal terminal MS, and a low-level signal is continuously output from the drive signal output terminal, so that some transistors in the corresponding pixel drive circuit in the display substrate are turned off. As a result, the data voltage in the display substrate is not charged, and the state of the previous frame is maintained, thereby achieving a low refresh rate in that area.

[0259] This disclosure also provides a method for driving a shift register, configured to drive the shift register provided in any of the foregoing embodiments. The method for driving the shift register may include:

[0260] Under the control of the signals at the signal input terminal, the first clock signal terminal, the second clock signal terminal, and the third power supply terminal, the shift sub-circuit provides the signal from the first power supply terminal or the second power supply terminal to the cascaded signal output terminal, and provides the signal from at least one of the signal input terminal, the second clock signal terminal, and the first power supply terminal to the output sub-circuit.

[0261] Under the control of the signals provided by the shift sub-circuit and the signals from the first control signal terminal, the second control signal terminal, the third control signal terminal, and the masking signal terminal, the output sub-circuit provides the first power supply terminal or the second power supply terminal signal to the drive signal output terminal.

[0262] This disclosure also provides a display device, including a display substrate having a display area and a non-display area, and including: a gate driving circuit located in the non-display area, the gate driving circuit including: a plurality of cascaded shift registers provided in any of the foregoing embodiments.

[0263] In an exemplary embodiment, the display device further includes: a plurality of pixel driving circuits, wherein the driving signal output terminal of at least one shift register in the gate driving circuit provides a driving signal to the pixel driving circuit.

[0264] In an exemplary embodiment, FIG10 is a schematic diagram of a display substrate, FIG11 is a schematic diagram of one gate driving circuit, FIG12 is a schematic diagram of another gate driving circuit, and FIG13 is a schematic diagram of a first-stage virtual shift register. As shown in FIG10 to FIG13, the display substrate includes: a plurality of first cross-stage connection lines NL1 located in the non-display area. At least one first cross-stage connection line NL1 is electrically connected to a first control signal terminal and a signal input terminal connected to a first-stage shift register and a cascaded signal output terminal connected to the previous stage shift register, respectively; at least a portion of the orthographic projection of at least one first cross-stage connection line NL1 on the substrate is located between the orthographic projections on the substrate of the two stage shift registers connected to the first cross-stage connection line NL1.

[0265] In an exemplary embodiment, as shown in Figures 10 to 13, the display substrate further includes: multiple second cross-level connection lines NL2 located in the non-display area; a third node is provided in the shift sub-circuit; the second cross-level connection lines NL2 are electrically connected to the second control signal terminal connected to the first-level shift register and the third node in the shift sub-circuit of the first K-level shift register, respectively, where K ≥ 2.

[0266] In an exemplary embodiment, at least a portion of the orthographic projection of at least one second cross-level connection line onto the substrate at least partially overlaps with the orthographic projection of at least one level shift register onto the substrate.

[0267] In an exemplary embodiment, as shown in Figures 10 to 13, the display substrate further includes: multiple third cross-level connection lines NL3 located in the non-display area; a fifth node is provided in the shift sub-circuit; the third cross-level connection lines NL3 are electrically connected to the third control signal terminal connected to the first-level shift register and the fifth node in the previous-level shift register, respectively.

[0268] In an exemplary embodiment, at least a portion of the orthographic projection of at least one third cross-level connection line onto the substrate is located on the side of the orthographic projection of at least one level shift register onto the substrate that is away from the display area.

[0269] In an exemplary embodiment, as shown in FIG10, at least one shift register includes: a first transistor T1 to a twenty-sixth transistor T26, and at least one transistor includes: an active pattern.

[0270] In an exemplary embodiment, the length of the active pattern of the first transistor T1 along the first direction D1 is greater than the length of at least one of the active patterns of the third transistor T3, the seventh transistor T7, the fourteenth transistor T14, the eighteenth transistor T18, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, and the twenty-sixth transistor T26 along the first direction D1.

[0271] In an exemplary embodiment, at least one of the active patterns of the ninth transistor T9 and the tenth transistor T10 has a length along the first direction D1 greater than the length along the first direction D1 of at least one of the active patterns of the third transistor T3, the seventh transistor T7, the fourteenth transistor T14, the eighteenth transistor T18, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, and the twenty-sixth transistor T26.

[0272] In an exemplary embodiment, the length of at least one of the active patterns of the nineteenth transistor T19 and the twentieth transistor T20 along the first direction D1 is greater than the length of at least one of the active patterns of the ninth transistor T9 and the tenth transistor T10 along the first direction D1.

[0273] The active pattern of the ninth transistor T9 and the active pattern of the tenth transistor T10 along the first direction D1 are relatively long, which can increase the output capability of the shift sub-circuit. The active pattern of the nineteenth transistor T19 and the active pattern of the twentieth transistor T20 along the first direction D1 are also relatively long, which can increase the output capability of the output sub-circuit.

[0274] In an exemplary embodiment, as shown in FIG10, the twenty-first transistor T21 and the twenty-second transistor T22 are arranged along the first direction D1 and are adjacent to each other. That is, the arrangement of the twenty-first transistor T21 and the twenty-second transistor T22 along the first direction D1 and their adjacent arrangement makes the distance between the first electrode of the twenty-second transistor T22 and the control electrode of the twenty-first transistor T21 smaller. By shortening the distance between the first electrode of the twenty-second transistor T22 and the control electrode of the twenty-first transistor T21, this disclosure can ensure the switching stability of the twenty-first transistor T21.

[0275] In an exemplary embodiment, as shown in FIG10, at least one shift register further includes a sixth capacitor C6, which is electrically connected to the drive signal output terminal. The orthogonal projection of the sixth capacitor C6 onto the substrate lies between the orthogonal projections of the twenty-fourth transistor T24 and the twentieth transistor T20 onto the substrate.

[0276] In an exemplary embodiment, as shown in Figures 11 to 13, the gate drive circuit further includes K virtual shift registers. Each virtual shift register includes a virtual shift sub-circuit and a virtual output sub-circuit. Each virtual shift register includes at least one virtual transistor and at least one virtual capacitor. The at least one virtual transistor includes a first electrode and a second electrode, and the at least one virtual capacitor includes a first plate and a second plate.

[0277] In an exemplary embodiment, the shift sub-circuit of at least one shift register has the same circuit structure as the at least one virtual shift sub-circuit, and the output sub-circuit of at least one shift register has the same circuit structure as the at least one virtual shift sub-circuit.

[0278] In an exemplary embodiment, at least one electrode of the first and second poles of at least one virtual transistor is electrically connected to a first power supply terminal or a second power supply terminal, and at least one plate of the first and second plates of at least one virtual capacitor is electrically connected to the first power supply terminal or the second power supply terminal.

[0279] For example, at least one virtual shift register includes: a first virtual transistor DT1 to a twenty-sixth virtual transistor DT26, and a first virtual capacitor DC1 to a seventh virtual capacitor DC7. Figures 11 and 12 are illustrated with K=2 as an example.

[0280] As shown in Figure 13, the structure and connection method of the first to sixteenth transistors and the first to fourth capacitors in at least one shift register are the same as those of the first virtual transistor DT1 to sixteenth virtual transistor DT16 and the first virtual capacitor DC1 to fourth virtual capacitor DC4 in at least one virtual shift register.

[0281] As shown in Figure 13, the structure of at least one shift register, including transistors seventeen to twenty-six and capacitors fifth to seventh, is at least partially identical to that of at least one virtual shift register, including virtual transistors seventeen to twenty-six and virtual capacitors DT26 and capacitors DC5 to DC7. One of the first and second electrodes of at least one of the transistors DT26 to DC5, and one of the first and second plates of at least one capacitor DC7, are electrically connected to either a first or second power supply terminal. This connection ensures that the output sub-circuit in the virtual shift register does not output, and all traces are short-circuited, preventing the output sub-circuit from being in a floating state and further improving the reliability of the display device.

[0282] The virtual shift register configuration in this disclosure ensures the display uniformity of the display substrate in the display device.

[0283] As shown in Figures 11 and 12, the cascaded signal output terminal of the k-th stage virtual shift register is electrically connected to the signal input terminal of the (k+1)-th stage virtual shift register, and the cascaded signal output terminal of the K-th stage shift register is electrically connected to the signal input terminal of the first stage shift register, where 1 ≤ k ≤ K-1 and K ≥ 2. For example, when K = 2, the cascaded signal output terminal of the first stage virtual shift register is electrically connected to the signal input terminal of the second stage virtual shift register, and the cascaded signal output terminal of the second stage shift register is electrically connected to the signal input terminal of the first stage shift register.

[0284] In an exemplary embodiment, as shown in FIG12, the display substrate may further include: a first power line signal group disposed on the substrate and located in a non-display area. The first power signal line group includes: a plurality of first power lines VGH, at least one of the first power lines extending at least partially along a second direction, and the plurality of first power lines being arranged sequentially along the direction close to the display area.

[0285] In an exemplary embodiment, as shown in FIG12, the display substrate may further include a second power line signal group disposed on the substrate and located in a non-display area. The second power signal line group includes a plurality of second power lines VGL, at least one of the second power lines VGL extending at least partially along a second direction D2, and the plurality of second power lines being arranged sequentially along a direction close to the display area.

[0286] In an exemplary embodiment, as shown in FIG12, the display substrate may further include: an initial signal line group disposed on the substrate and located in the non-display area. The initial signal line group includes: a first initial signal line STV1 and a second initial signal line STV2, wherein at least one of the first initial signal line STV1 and the second initial signal line STV2 extends along a second direction D2.

[0287] In an exemplary embodiment, as shown in FIG12, the display substrate may further include a clock signal line group disposed on the substrate and located in a non-display area. The clock signal line group includes a first clock signal line CLK1 and a second clock signal line CLK2, at least a portion of at least one of the first clock signal line CLK1 and the second clock signal line CLK2 extending along a second direction D2.

[0288] In an exemplary embodiment, as shown in FIG12, the display substrate may further include a masking signal line MSL disposed on the substrate and located in a non-display area. At least a portion of the masking signal line MSL extends along a second direction D2.

[0289] In an exemplary embodiment, as shown in FIG12, the display substrate may further include a third power line NCXL disposed on the substrate and located in a non-display area. At least a portion of the third power line NCXL extends along a second direction D2.

[0290] In an exemplary embodiment, as shown in FIG12, the first clock signal terminal of at least one level shift register and at least one level virtual shift register is electrically connected to one of the first clock signal lines CLK1 and CLK2; the second clock signal terminal of at least one level shift register and at least one level virtual shift register is electrically connected to the other of the first clock signal lines CLK1 and CLK2; the masking signal terminal of at least one level shift register and at least one level virtual shift register is electrically connected to the masking signal line MSL; the first power supply terminal of at least one level shift register and at least one level virtual shift register is electrically connected to the first power supply line; and the second power supply terminal of at least one level shift register and at least one level virtual shift register is electrically connected to the second power supply line.

[0291] In an exemplary embodiment, as shown in FIG12, at least one of the first initial signal line STV1, the second initial signal line STV2, the masking signal line MSL, the first clock signal line CLK1, the second clock signal line CLK2, the plurality of first power lines VGH, the plurality of second power lines VGL, and the third power line NCXL extends at least partially along the second direction D2.

[0292] In an exemplary embodiment, as shown in FIG12, the first initial signal line STV1, the first second power line VGL-1, the first clock signal line CLK1, the second clock signal line CLK2, the first first power line VGH-1, the third power line NCXL, the second initial signal line STV2, the second second power line VGL-2, the second first power line VGH-2, the masking signal line MSL, the third first power line VGH-3, the fourth first power line VGH-4, the fifth first power line VGH-5, and the third second power line VGL-3 are arranged sequentially along the direction close to the display area.

[0293] In an exemplary embodiment, referring to Figures 10 and 12, at least one shift register includes: first transistors T1 to twenty-sixth transistors T26, and first capacitors C1 to seventh capacitors C7. A first second power line VGL-1 is connected to the first terminal of the third transistor T3 and the first terminal of the twenty-fifth transistor T25, respectively. A second second power line VGL-2 is connected to the first terminal of the tenth transistor T10. A third second power line VGL-3 is connected to the first terminal of the twentieth transistor T20 and the second terminal of the fourth capacitor C4, respectively. A first first power line VGH-1 is connected to the first terminal of the fifth transistor T5; a second first power line VGH-2 is connected to the first terminals of the eighth transistor T8, the ninth transistor T9, the thirteenth transistor T13, and the second terminal of the second capacitor C2; a third first power line VGH-3, a fourth first power line VGH-4, and a fifth first power line VGH-5 are connected to the first terminal of the nineteenth transistor T19, and the third first power line VGH-3 is also connected to the first terminal of the twenty-fourth transistor T24.

[0294] In an exemplary embodiment, as shown in FIG12, the width of at least one of the fourth first power line VGH-4 and the fifth first power line VGH-5 is greater than the width of at least one of the first first power line VGH-1, the second first power line VGH-2, the third first power line VGH-3, the first second power line VGL-1, the second second power line VGL-2 and the third power line NCXL.

[0295] In an exemplary embodiment, as shown in FIG12, the width of the third second power line VGL-3 is greater than the width of at least one of the first first power line VGH-1, the second first power line VGH-2, the third first power line VGH-3, the first second power line VGL-1, the second second power line VGL-2, and the third power line NCXL.

[0296] In an exemplary embodiment, the display device may include: a substrate and a driving structure layer disposed on the substrate. The gate driving circuit, a first initial signal line, a second initial signal line, a masking signal line, a first clock signal line, a second clock signal line, multiple first power lines, multiple second power lines, and a third power line are disposed on the driving structure layer. At least one level of shift register includes: multiple transistors and multiple capacitors. At least one level of virtual shift register includes: multiple virtual transistors and multiple virtual capacitors. At least one transistor or virtual transistor includes: an active pattern, a control electrode, a first electrode, and a second electrode. At least one capacitor or virtual capacitor includes: a first electrode plate and a second electrode plate.

[0297] The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer.

[0298] In an exemplary embodiment, the semiconductor layer includes at least: an active pattern of at least one transistor located in at least one level shift register and an active pattern of at least one virtual transistor located in at least one level virtual shift register.

[0299] In an exemplary embodiment, the first conductive layer includes at least: a first plate located at the control electrode of at least one transistor of at least one level shift register and at least one capacitor, and a first plate located at the control electrode of at least one virtual transistor of at least one level virtual shift register and at least one virtual capacitor.

[0300] In an exemplary embodiment, the second conductive layer includes at least: a second plate of at least one capacitor located in at least one level shift register and a second plate of at least one virtual capacitor located in at least one level virtual shift register.

[0301] In an exemplary embodiment, the third conductive layer includes at least: a first pole and a second pole of at least one transistor located in at least one level shift register.

[0302] In an exemplary embodiment, the fourth conductive layer includes at least: a first initial signal line, a second initial signal line, a masking signal line, a first clock signal line, a second clock signal line, a first power line, a second power line, and a third power line.

[0303] In an exemplary embodiment, FIG14 is another schematic diagram of the gate drive circuit. FIG14 is illustrated with K=2 as an example. As shown in FIG12 and FIG14, the number of first cross-level interconnects NL1 in the display substrate is N+K-1. For at least one level shift register, the shift sub-circuit includes: a first transistor, a ninth transistor, a tenth transistor, and a fourteenth transistor; the output sub-circuit includes: a twenty-second transistor; the second terminals 94 of the ninth transistor and 104 of the tenth transistor are electrically connected to the cascaded signal output terminal, respectively; the first terminals 13 of the first transistor and 143 of the fourteenth transistor are electrically connected to the signal input terminal, respectively; and the control terminal 222 of the twenty-second transistor is electrically connected to the first control signal terminal. For at least one level virtual shift register, the virtual shift sub-circuit includes: a first virtual transistor, a ninth virtual transistor, a tenth virtual transistor, and a fourteenth virtual transistor; the virtual output sub-circuit includes: a twenty-second virtual transistor; the second terminals DT94 of the ninth virtual transistor and DT104 of the tenth virtual transistor are electrically connected to the cascaded signal output terminal, respectively; the first terminals DT13 of the first virtual transistor and DT143 of the fourteenth virtual transistor are electrically connected to the signal input terminal, respectively; and the control terminal of the twenty-second virtual transistor DT222 is connected to the first power supply terminal or the second power supply terminal.

[0304] In an exemplary embodiment, the kth first cross-stage connection line is electrically connected to the second poles DT94 and DT104 of the ninth virtual transistor and the tenth virtual transistor in the kth stage virtual shift register, respectively, as well as the first poles DT13 and DT143 of the first virtual transistor and the fourteenth virtual transistor in the (k+1)th stage virtual shift register; the Kth first cross-stage connection line is electrically connected to the second poles DT94 and DT104 of the ninth virtual transistor and the tenth virtual transistor in the kth stage virtual shift register, respectively, as well as the first poles DT13 of the first transistor, DT143 of the fourteenth transistor, and the control pole 222 of the twenty-second transistor in the first stage shift register. For example, when K=2, the first first cross-stage connection line NL1(1) is electrically connected to the second poles DT94 and DT104 of the ninth virtual transistor and the tenth virtual transistor in the first stage virtual shift register, respectively, as well as the first poles DT13 and DT143 of the first virtual transistor and the fourteenth virtual transistor in the second stage virtual shift register. The second first cross-stage connection line NL1(2) is electrically connected to the second poles DT94 and DT104 of the ninth virtual transistor and the tenth virtual transistor in the second stage virtual shift register, respectively, as well as the first poles T13, T143 of the first transistor, and the control pole 222 of the twenty-second transistor in the first stage shift register.

[0305] In an exemplary embodiment, the r-th first cross-stage connection line is electrically connected to the second pole 94 of the ninth transistor and the second pole 104 of the tenth transistor of the rK-th stage shift register, and the first pole 13 of the first transistor, the first pole 143 of the fourteenth transistor, and the control pole 222 of the twenty-second transistor of the r-K+1-th stage shift register, respectively, where K+1≤r≤N+K-1. In an exemplary embodiment, the third first cross-stage connection line NL1(3) is electrically connected to the second pole 94 of the ninth transistor and the second pole 104 of the tenth transistor of the first stage shift register, and the first pole 13 of the first transistor, the first pole 143 of the fourteenth transistor, and the control pole 222 of the twenty-second transistor of the second stage shift register, respectively. The fourth first cross-stage connection line NL1(4) is electrically connected to the second pole 94 of the ninth transistor and the second pole 104 of the tenth transistor of the second stage shift register, and the first pole 13 of the first transistor, the first pole 143 of the fourteenth transistor, and the control pole 222 of the twenty-second transistor of the third stage shift register, and so on.

[0306] The first cross-stage connection line in this disclosure is directly electrically connected to the control electrode of the twenty-second transistor of at least one level shift register, which can shorten the length of the first cross-stage connection line, reduce the load on the first cross-stage connection line, and enable the twenty-second transistor connected to the first cross-stage connection line to respond to the control of the cascaded signal more quickly.

[0307] In an exemplary embodiment, as shown in Figures 11 and 14, at least a portion of at least one first cross-level connection line NL1 is located between the shift registers connected by the first cross-level connection line. Exemplarily, at least a portion of the first first cross-level connection line NL1(1) is located between the first virtual shift register and the second virtual shift register, at least a portion of the second first cross-level connection line NL1(2) is located between the second virtual shift register and the first shift register, at least a portion of the third first cross-level connection line NL1(3) is located between the first shift register and the second shift register, and so on.

[0308] In an exemplary embodiment, at least one first cross-level connection line is located in the third conductive layer.

[0309] In an exemplary embodiment, as shown in Figures 11 and 14, the display device may further include: N+K-1 third cross-stage connection lines NL3; in at least one level of shift register, the second terminal 44 of the fourth transistor is electrically connected to the fifth node, and the control terminal of the twenty-fifth transistor is electrically connected to the third control signal terminal; for at least one level of virtual shift register, the virtual shift sub-circuit further includes: a fourth virtual transistor; the virtual output sub-circuit further includes: a twenty-fifth virtual transistor; the second terminal DT44 of the fourth virtual transistor is electrically connected to the fifth node, and the control terminal DT252 of the twenty-fifth virtual transistor is electrically connected to the third control signal terminal.

[0310] In an exemplary embodiment, the kth third-stage cross-stage connection line is electrically connected to the second terminal of the fourth virtual transistor in the kth-stage virtual shift register and the control terminal of the twenty-fifth virtual transistor in the (k+1)th-stage virtual shift register, respectively. The Kth third-stage cross-stage connection line is electrically connected to the second terminal of the fourth virtual transistor in the Kth-stage virtual shift register and the control terminal of the twenty-fifth transistor in the first-stage shift register, respectively. For example, when K=2, the first third-stage cross-stage connection line NL3(1) is electrically connected to the second terminal DT44 of the fourth virtual transistor in the first-stage virtual shift register and the control terminal DT252 of the twenty-fifth virtual transistor in the second-stage virtual shift register, respectively. The second third-stage cross-stage connection line NL3(2) is electrically connected to the second terminal DT44 of the fourth virtual transistor in the second-stage virtual shift register and the control terminal 252 of the twenty-fifth transistor in the first-stage shift register, respectively.

[0311] In an exemplary embodiment, the r-th third cross-stage connection line is electrically connected to the second terminal of the fourth transistor of the rK-th stage shift register and the control terminal of the twenty-fifth transistor of the r-K+1-th stage shift register, respectively, where K+1≤r≤N+K-1. For example, when K=2, the third cross-stage connection line NL3(3) is electrically connected to the second terminal 44 of the fourth transistor of the first stage shift register and the control terminal 252 of the twenty-fifth transistor of the second stage shift register, respectively, and the fourth cross-stage connection line NL3(4) is electrically connected to the second terminal 44 of the fourth transistor of the second stage shift register and the control terminal 252 of the twenty-fifth transistor of the third stage shift register, and so on.

[0312] In an exemplary embodiment, as shown in Figures 11 and 14, at least one third cross-level connection line NL3 is located in the third conductive layer.

[0313] In an exemplary embodiment, as shown in Figures 11 and 14, at least one third cross-level connecting line NL3 extends at least partially along a second direction D2, which intersects with a first direction D1.

[0314] In an exemplary embodiment, as shown in FIG12, the orthographic projection of at least one third cross-level connection line NL3 on the substrate is located on the side of the orthographic projection of the first initial signal line STV1 on the substrate away from the display area.

[0315] In an exemplary embodiment, as shown in FIG12, the display device further includes: N second cross-stage connection lines NL2. For at least one level shift register, the shift sub-circuit further includes: a sixth transistor and a seventh transistor, and the output sub-circuit further includes: a twenty-third transistor, the second terminal of the sixth transistor and the first terminal of the seventh transistor being electrically connected to the third node, and the control terminal of the twenty-third transistor being electrically connected to the second control signal terminal. For at least one level virtual shift register, the virtual shift sub-circuit further includes: a sixth virtual transistor and a seventh virtual transistor, and the virtual output sub-circuit further includes: a twenty-third virtual transistor, the second terminal of the sixth virtual transistor and the first terminal of the seventh virtual transistor being electrically connected to the third node, and the control terminal of the twenty-third virtual transistor being electrically connected to the second control signal terminal.

[0316] In an exemplary embodiment, the s-th second cross-stage connection line is electrically connected to the second terminal of the sixth virtual transistor and the first terminal of the seventh virtual transistor of the s-th stage virtual shift register, and the control terminal of the twenty-third transistor of the s-th stage shift register, respectively, where 1≤s≤K. For example, when K=2, the first second cross-stage connection line NL2(1) is electrically connected to the second terminal DT64 of the sixth virtual transistor and the first terminal DT73 of the seventh virtual transistor of the first stage virtual shift register, and the control terminal 232 of the twenty-third transistor of the first stage shift register, respectively. The second second cross-stage connection line NL(2) is electrically connected to the second terminal DT64 of the sixth virtual transistor and the first terminal DT73 of the seventh virtual transistor of the second stage virtual shift register, and the control terminal 232 of the twenty-third transistor of the second stage shift register, respectively.

[0317] In an exemplary embodiment, the t-th second cross-stage connection line is electrically connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor of the tK-th stage shift register, and the control terminal of the twenty-third transistor of the t-th stage shift register, respectively, where K+1≤t≤N. For example, when K=2, the third second cross-stage connection line NL(3) is electrically connected to the second terminal 64 of the sixth transistor and the first terminal 73 of the seventh transistor of the first stage shift register, and the control terminal 232 of the twenty-third transistor of the third stage shift register, respectively. The fourth second cross-stage connection line NL(4) is electrically connected to the second terminal 64 of the sixth transistor and the first terminal 73 of the seventh transistor of the second stage shift register, and the control terminal 232 of the twenty-third transistor of the fourth stage shift register, respectively.

[0318] In an exemplary embodiment, as shown in FIG12, at least one second cross-level connecting line NL2 extends at least partially along a second direction D2, which intersects with a first direction D1.

[0319] In an exemplary embodiment, as shown in FIG12, the orthographic projection of at least one second cross-level connection line NL2 on the substrate is located between the orthographic projection of the second first power line VGH-2 on the substrate and the orthographic projection of the masking signal line MSL on the substrate.

[0320] In an exemplary embodiment, Figure 15 is a schematic diagram of the second cross-level connection line (Figure 15), Figure 16 is a schematic diagram of the second cross-level connection line (Figure 16), and Figure 17 is a cross-sectional view of Figures 15 and 16 along the AA direction. Figure 15 is illustrated with K=2 as an example, and Figure 16 is illustrated with K=3 as an example. As shown in Figures 15 and 16, at least one second cross-level connection line NL2 is located in the fourth conductive layer.

[0321] In an exemplary embodiment, as shown in Figures 15 and 16, at least one second-level connecting line extends at least partially along the second direction and is in the shape of a broken line, and the at least one second-level connecting line includes K-1 bends NC.

[0322] In an exemplary embodiment, the first end of the s-th second cross-stage connection line is electrically connected to the second pole of the sixth virtual transistor and the first pole of the seventh virtual transistor of the s-th stage virtual shift register, and the second end of the s-th second cross-stage connection line is electrically connected to the control pole of the twenty-third transistor of the s-th stage shift register.

[0323] In an exemplary embodiment, the first end of the t-th second cross-stage connection line is connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor of the tK-th stage shift register, and the second end of the t-th second cross-stage connection line is electrically connected to the control terminal of the twenty-third transistor of the t-th stage shift register.

[0324] In an exemplary embodiment, as shown in Figures 15 and 16, the line connecting the second end of the m-th second-level connecting line and the first end of the (m+K)-th second-level connecting line intersects at least one bend in the (m+1)-m+K-1-th second-level connecting lines. For example, when K=2, the line connecting the second end of the first second-level connecting line NL(1) and the first end of the third second-level connecting line NL(3) intersects the bend in the second second-level connecting line NL(2), the line connecting the second end of the second second-level connecting line NL(2) and the first end of the fourth second-level connecting line NL(4) intersects the bend in the third second-level connecting line NL(3), and so on.

[0325] In this disclosure, at least one second-level connection line includes K-1 bends, and the line connecting the second end of the m-th second-level connection line and the first end of the (m+K)-th second-level connection line intersects with at least one bend of the (m+1)-m+K-1 second-level connection lines. This allows the second-level connection line to bend near the control electrode of the 23rd transistor, preventing interference between adjacent second-level connection lines and improving the reliability of the display device.

[0326] In an exemplary embodiment, at least one level shift register includes: a second connection line L2, a third connection electrode E3 and a fourth connection electrode E4. The second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor of the at least one level shift register are connected to the fourth connection electrode E4 through the second connection line L2. The control electrode 232 of the twenty-third transistor of the at least one level shift register is electrically connected to the third connection electrode E3.

[0327] In an exemplary embodiment, the second connecting line L2 is located in the first conductive layer, and the third connecting electrode E3 and the fourth connecting electrode E4 are located in the third conductive layer.

[0328] In an exemplary embodiment, as shown in FIG17, the display device further includes: a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, and a first planarization layer 105 disposed on a substrate 100. The first insulating layer 101 is located between the semiconductor layer and the first conductive layer; the second insulating layer 102 is located between the first and second conductive layers; the third insulating layer 103 is located between the second and third conductive layers; the fourth insulating layer 104 is located between the third and fourth conductive layers; and the first planarization layer 105 is located on the side of the fourth conductive layer away from the substrate.

[0329] In an exemplary embodiment, FIG18 is another structural schematic diagram of the second cross-level connecting line, and FIG19 is a cross-sectional view of FIG18 along the AA direction. As shown in FIG18 and FIG19, at least one second cross-level connecting line NL2 includes: a first connecting portion NL2A and a second connecting portion NL2B that are disposed in different layers and interconnected with each other; the first connecting portion NL2A and the second connecting portion NL2B extend at least partially along the second direction D2.

[0330] In an exemplary embodiment, the first connection portion NL2A of the s-th second cross-stage connection line is electrically connected to the second pole of the sixth virtual transistor and the first pole of the seventh virtual transistor of the s-th stage virtual shift register, and the second connection portion NL2BA of the s-th second cross-stage connection line is electrically connected to the control pole of the twenty-third transistor of the s-th stage shift register. Exemplarily, when K=2, the first connection portion NL2A of the first second cross-stage connection line NL2(1) is electrically connected to the second pole DT64 of the sixth virtual transistor and the first pole DT73 of the seventh virtual transistor of the first stage virtual shift register, the second connection portion NL2B of the first second cross-stage connection line NL2(1) is electrically connected to the control pole 232 of the twenty-third transistor of the first stage shift register, the first connection portion NL2A of the second second cross-stage connection line NL2(2) is electrically connected to the second pole DT64 of the sixth virtual transistor and the first pole DT73 of the seventh virtual transistor of the second stage virtual shift register, and the second connection portion NL2B of the second second cross-stage connection line NL2(2) is electrically connected to the control pole 232 of the twenty-third transistor of the second stage shift register.

[0331] In an exemplary embodiment, the first connection portion NL2A of the t-th second cross-stage connection line is electrically connected to the second terminal 64 of the sixth transistor and the first terminal 73 of the seventh transistor of the tK-th stage shift register, and the second connection portion NL2B of the t-th second cross-stage connection line is electrically connected to the control terminal 232 of the twenty-third transistor of the t-th stage shift register. For example, when K=2, the first connection portion NL2A of the third second cross-stage connection line NL2(3) is electrically connected to the second terminal 64 of the sixth transistor and the first terminal 73 of the seventh transistor of the first stage shift register, the second connection portion NL2B of the third second cross-stage connection line NL2(3) is electrically connected to the control terminal 232 of the twenty-third transistor of the third stage shift register, the first connection portion NL2A of the fourth second cross-stage connection line NL2(4) is electrically connected to the second terminal 64 of the sixth transistor and the first terminal 73 of the seventh transistor of the second stage shift register, the second connection portion NL2B of the fourth second cross-stage connection line NL2(4) is electrically connected to the control terminal 232 of the twenty-third transistor of the fourth stage shift register, and so on.

[0332] In an exemplary embodiment, as shown in FIG18, the second connecting portion NL2B of at least one second cross-level connecting line NL2 is shaped as a broken line and includes a bent portion NC.

[0333] In an exemplary embodiment, as shown in FIG18, the line connecting the end of the second connecting portion of the m-th second-level connecting line away from the first connecting portion and the end of the first connecting portion of the (m+K)-th second-level connecting line away from the second connecting portion intersects the bend of the second connecting portion of the (m+1)-m+K-1-th second-level connecting lines. For example, the line connecting the end of the second connecting portion NLB of the first second-level connecting line NL2(1) away from the first connecting portion NLA and the end of the first connecting portion NLA of the third second-level connecting line NL2(3) away from the second connecting portion NLB intersects the bend NC of the second connecting portion NLB of the second second-level connecting line NL2(3), and so on.

[0334] This application includes at least one second cross-level connection line NL2 comprising: a first connection portion NL2A and a second connection portion NL2B that are disposed in different layers and interconnected with each other. This can reduce the length of the second cross-level connection line in the fourth conductive layer and reduce the risk of electrostatic discharge caused by the long length of the second cross-level connection line in the fourth conductive layer.

[0335] In an exemplary embodiment, the driving structure layer further includes: a fifth conductive layer located on the side of the fourth conductive layer away from the substrate; the first connection portion NL2A may be located on the fourth conductive layer, and the second connection portion NL2B may be located on the fifth conductive layer.

[0336] In an exemplary embodiment, at least one level shift register includes: a second connection line L2, a third connection electrode E3, a fourth connection electrode E4, and a seventh connection electrode E7. The second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor of the at least one level shift register are connected to the fourth connection electrode E4 through the second connection line L2. The control electrode 232 of the twenty-third transistor of the at least one level shift register is electrically connected to the seventh connection electrode E7 through the third connection electrode E3.

[0337] In an exemplary embodiment, the second connecting line L2 is located in the first conductive layer, the third connecting electrode E3 and the fourth connecting electrode E4 are located in the third conductive layer, and the seventh connecting electrode E7 is located in the fourth conductive layer.

[0338] In an exemplary embodiment, as shown in FIG18, the display device further includes: a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a first planarization layer 105, and a second planarization layer 106 disposed on a substrate 100. The first insulating layer 101 is located between the semiconductor layer and the first conductive layer; the second insulating layer 102 is located between the first and second conductive layers; the third insulating layer 103 is located between the second and third conductive layers; the fourth insulating layer 104 is located between the third and fourth conductive layers; the first planarization layer 105 is located between the fourth and fifth conductive layers; and the second planarization layer 106 is located on the side of the fifth conductive layer away from the substrate.

[0339] Figure 20 is a schematic diagram of the structure of a display substrate including the second cross-level connection line shown in Figure 15. As shown in Figure 20, the orthographic projection of at least one second cross-level connection line NL2 on the substrate is located between the orthographic projection of the second first power line VGH-2 on the substrate and the orthographic projection of the masking signal line MSL on the substrate.

[0340] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer located on the side of the driving circuit layer away from the substrate. The light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit via a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode.

[0341] In an exemplary embodiment, the display substrate may further include an encapsulation structure layer located on the side of the light-emitting structure layer away from the substrate. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0342] In an exemplary embodiment, the display substrate may further include a touch structure layer located on the side of the encapsulation structure layer away from the substrate. The touch structure layer may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protective layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes via vias.

[0343] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with gate driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure is not limited thereto.

[0344] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0345] This disclosure uses a first display substrate and a second display substrate as examples to illustrate the fabrication process of the display substrate. The second cross-level connection line of the first display substrate is the second cross-level connection line provided in FIG15, and the second cross-level connection line of the second display substrate is the second cross-level connection line provided in FIG18.

[0346] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film using a patterning process to form a semiconductor layer pattern. As shown in FIG21, FIG21 is a schematic diagram of the first display substrate and the second display substrate after forming a semiconductor layer pattern.

[0347] In an exemplary embodiment, as shown in FIG21, the semiconductor layer pattern may include at least: the active pattern 11 of the first transistor to the active pattern 261 of the twenty-sixth transistor located in at least one level shift register.

[0348] In an exemplary embodiment, as shown in FIG21, the active pattern 21 of the second transistor and the active pattern 111 of the eleventh transistor are integrated into one structure; the active patterns 81 of the eighth transistor, 121 of the twelfth transistor, 131 of the thirteenth transistor, 161 of the sixteenth transistor, and 171 of the seventeenth transistor are integrated into one structure; the active patterns 91 of the ninth transistor and 101 of the tenth transistor are integrated into one structure; the active patterns 191 of the nineteenth transistor and 201 of the twentieth transistor are integrated into one structure; the active patterns 211 of the twenty-first transistor, 241 of the twenty-fourth transistor, and 261 of the twenty-sixth transistor are integrated into one structure; and the active patterns 221 of the twenty-second transistor and 231 of the twenty-third transistor are integrated into one structure. The active patterns 11 of the first transistor, 31 of the third transistor, 41 of the fourth transistor, 51 of the fifth transistor, 61 of the sixth transistor, 71 of the seventh transistor, 141 of the fourteenth transistor, 151 of the fifteenth transistor, 181 of the eighteenth transistor, and 251 of the twenty-fifth transistor can be set individually.

[0349] In an exemplary embodiment, as shown in FIG21, the active pattern 11 of the first transistor and the active pattern 141 of the fourteenth transistor are arranged along a first direction D1, and the active pattern 11 of the first transistor is located on the side of the active pattern 141 of the fourteenth transistor closer to the display area. The active pattern 11 of the first transistor and the active pattern 31 of the third transistor are arranged along a second direction D2, and the active pattern 31 of the third transistor of the current stage shift register is located on the side of the active pattern 11 of the first transistor closer to the next stage shift register. The active patterns 141 of the fourteenth transistor and the active pattern 151 of the fifteenth transistor are arranged along the first direction D1, and the active pattern 151 of the fifteenth transistor of the current stage shift register is located on the side of the active pattern 141 of the fourteenth transistor closer to the next stage shift register. The integrated structure of the active pattern 21 of the second transistor and the active pattern 111 of the eleventh transistor is located on the side of the active pattern 31 of the third transistor closer to the display area. The active pattern 41 of the fourth transistor in this stage shift register is located on the side of the integrated structure of the active patterns 21 and 111 of the second and eleventh transistors, near the next stage shift register. The active pattern 251 of the twenty-fifth transistor in this stage shift register is located on the side of the active pattern 41 of the fourth transistor, near the next stage shift register. The active patterns 51 of the fifth transistor and 61 of the sixth transistor are located on the side of the integrated structure of the active patterns 21 and 111 of the second and eleventh transistors, near the display area, and the active pattern 51 of the fifth transistor in this stage shift register is located on the side of the active pattern 61 of the sixth transistor, near the next stage shift register. The active pattern 71 of the seventh transistor is located on the side of the active pattern 61 of the sixth transistor, near the display area. The integrated structure of the active pattern 81 of the eighth transistor, the active pattern 121 of the twelfth transistor, the active pattern 131 of the thirteenth transistor, the active pattern 161 of the sixteenth transistor, and the active pattern 171 of the seventeenth transistor is located on the side of the active pattern 51 of the fifth transistor, the active pattern 41 of the fourth transistor, and the active pattern 251 of the twenty-fifth transistor near the display area, respectively. The active patterns 41 of the fourth transistor and 161 of the sixteenth transistor are arranged along the first direction D1, and the active patterns 251 of the twenty-fifth transistor and 171 of the seventeenth transistor are also arranged along the first direction D1. The active patterns 81 of the eighth transistor, 131 of the thirteenth transistor, 121 of the twelfth transistor, 161 of the sixteenth transistor, and 171 of the seventeenth transistor are arranged sequentially along the second direction D2. The active pattern 181 of the eighteenth transistor is located on the side of the integrated structure of the active pattern 81 of the eighth transistor, the active pattern 121 of the twelfth transistor, the active pattern 131 of the thirteenth transistor, the active pattern 161 of the sixteenth transistor, and the active pattern 171 of the seventeenth transistor, close to the display area.The integrated structure of the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor is located on the side of the integrated structure of the active pattern 81 of the eighth transistor, the active pattern 121 of the twelfth transistor, the active pattern 131 of the thirteenth transistor, the active pattern 161 of the sixteenth transistor, and the active pattern 171 of the seventeenth transistor closer to the display area. The active patterns 91 of the ninth transistor and 101 of the tenth transistor are arranged along the second direction D2, and the active pattern 101 of the tenth transistor of this stage shift register is located on the side of the active pattern 91 of the ninth transistor closer to the display area. The integrated structure of the active pattern 221 of the twenty-second transistor and the active pattern 231 of the twenty-third transistor is located on the side of the integrated structure of the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor closer to the display area. The active patterns 221 of the twenty-second transistor and 231 of the twenty-third transistor are arranged along the second direction D2, and the active pattern 221 of the twenty-second transistor in this stage shift register is located on the side of the active pattern 231 of the twenty-third transistor closer to the next stage shift register. The integrated structure of the active patterns 211 of the twenty-first transistor, 241 of the twenty-fourth transistor, and 261 of the twenty-sixth transistor is located on the side of the integrated structure of the active patterns 221 of the twenty-second transistor and 231 of the twenty-third transistor closer to the display area. The active patterns 211 of the twenty-first transistor, 261 of the twenty-sixth transistor, and 241 of the twenty-fourth transistor are arranged sequentially along the second direction D2, and the active pattern 241 of the twenty-fourth transistor in this stage shift register is located on the side of the active pattern 261 of the twenty-sixth transistor closer to the display area. The integrated structure of the active pattern 191 of the nineteenth transistor and the active pattern 201 of the twentieth transistor is located on the side of the integrated structure of the active pattern 211 of the twenty-first transistor, the active pattern 241 of the twenty-fourth transistor, and the active pattern 261 of the twenty-sixth transistor closer to the display area. The active patterns 191 of the nineteenth transistor and 201 of the twentieth transistor are arranged along the second direction D2, and the active pattern 201 of the twentieth transistor of this stage shift register is located on the side of the active pattern 191 of the nineteenth transistor closer to the next stage shift register.

[0350] In an exemplary embodiment, the active pattern of the first transistor is along the width of the first direction D1.

[0351] In an exemplary embodiment, any one of the active patterns of the first transistor 11, the second transistor 21, the third transistor 31, the fifth transistor 51, the seventh transistor 71, the ninth transistor 91, the tenth transistor 101, the eleventh transistor 111, the fourteenth transistor 141, the fifteenth transistor 151, the eighteenth transistor 181, the nineteenth transistor 191, the twentieth transistor 201, the twenty-first transistor 211, the twenty-second transistor 221, the twenty-third transistor 231, the twenty-fourth transistor 241, and the twenty-sixth transistor 261 is strip-shaped and extends along the second direction D2.

[0352] In an exemplary embodiment, any one of the active patterns of the fourth transistor 41, the sixth transistor 61, the sixteenth transistor 161, the seventeenth transistor 171, and the twenty-fifth transistor 251 is strip-shaped and extends along the first direction D1. The active patterns of the sixteenth transistor 161 and the seventeenth transistor 171 are in an "n" shape with openings facing the display area.

[0353] In an exemplary embodiment, the length of the active pattern 11 of the first transistor along the first direction D1 is greater than the length of at least one of the active patterns of the third transistor 31, the seventh transistor 71, the fourteenth transistor 141, the eighteenth transistor 181, the twenty-first transistor 211, the twenty-second transistor 221, the twenty-third transistor 231, the twenty-fourth transistor 241, and the twenty-sixth transistor 261 along the first direction D1.

[0354] In an exemplary embodiment, at least one of the active patterns 91 of the ninth transistor and 101 of the tenth transistor has a length along the first direction D1 greater than the length along the first direction D1 of at least one of the active patterns 31 of the third transistor, 71 of the seventh transistor, 141 of the fourteenth transistor, 181 of the eighteenth transistor, 211 of the twenty-first transistor, 221 of the twenty-second transistor, 231 of the twenty-third transistor, 241 of the twenty-fourth transistor, and 261 of the twenty-sixth transistor.

[0355] In an exemplary embodiment, the length of at least one active pattern of the nineteenth transistor's active pattern 191 and the twentieth transistor's active pattern 201 along the first direction D1 is greater than the length of at least one active pattern of the ninth transistor's active pattern 91 and the tenth transistor's active pattern 101 along the first direction D1.

[0356] In an exemplary embodiment, the length of at least one of the active patterns 91 of the ninth transistor and 101 of the tenth transistor along the first direction D1 is greater than the length of at least one of the active patterns 31 of the third transistor, 71 of the seventh transistor, 141 of the fourteenth transistor, 181 of the eighteenth transistor, 211 of the twenty-first transistor, 221 of the twenty-second transistor, 231 of the twenty-third transistor, 241 of the twenty-fourth transistor, and 261 of the twenty-sixth transistor along the first direction D1, which can increase the driving capability of the ninth and tenth transistors.

[0357] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 21-2 of the active pattern 21 of the second transistor can serve as the first region 111-1 of the active pattern 111 of the eleventh transistor, the first region 81-1 of the active pattern 81 of the eighth transistor can serve as the first region 131-1 of the active pattern 131 of the thirteenth transistor, the second region 91-2 of the active pattern 91 of the ninth transistor can serve as the second region 101-2 of the active pattern 101 of the tenth transistor, the first region 121-1 of the active pattern 121 of the twelfth transistor can serve as the second region 131-2 of the active pattern 131 of the thirteenth transistor, and the second region 121-2 of the active pattern 121 of the twelfth transistor can serve as the second region 161-2 of the active pattern 161 of the sixteenth transistor. The first region 161-1 of the active pattern 161 of the sixteenth transistor can be used as the first region 171-1 of the active pattern 171 of the seventeenth transistor; the second region 191-2 of the active pattern 191 of the nineteenth transistor can be used as the second region 201-2 of the active pattern of the twentieth transistor; the second region 221-2 of the active pattern 221 of the twenty-second transistor can be used as the second region 231-2 of the active pattern 231 of the twenty-third transistor; the second region 211-2 of the active pattern 211 of the twenty-first transistor can be used as the first region 261-1 of the active pattern 261 of the twenty-sixth transistor; and the second region 241-2 of the active pattern of the twenty-fourth transistor can be used as the second region 261-2 of the active pattern 261 of the twenty-sixth transistor.The active pattern 11 of the first transistor has a first region 11-1 and a second region 11-2. The active pattern 21 of the second transistor has a first region 21-1. The active pattern 31 of the third transistor has a first region 31-1 and a second region 31-2. The active pattern 41 of the fourth transistor has a first region 41-1 and a second region 41-2. The active pattern 51 of the fifth transistor has a first region 51-1 and a second region 51-2. The active pattern 61 of the sixth transistor has a first region 61-1 and a second region 61-2. The active pattern 71 of the seventh transistor has a first region 71-1 and a second region 71-2. The active pattern 81 of the eighth transistor has a second region 81-2. The active pattern 91 of the ninth transistor has a first region 91-1. The active pattern 101 of the tenth transistor has a first region 101-1. The active pattern 111 of the eleventh transistor has a second region 111-2. The active pattern 111 of the fourteenth transistor has a first region 101-1. The active pattern 111 of the eleventh transistor has a second region 111-2. The first region 141-1 and the second region 141-2 of pattern 141, the first region 151-1 and the second region 151-2 of the active pattern 151 of the fifteenth transistor, the second region 171-2 of the active pattern 171 of the seventeenth transistor, the first region 181-1 and the second region 181-2 of the active pattern 181 of the eighteenth transistor, the first region 191-1 of the active pattern 191 of the nineteenth transistor, the first region 201-1 of the active pattern 201 of the twentieth transistor, the first region 211-1 of the active pattern 211 of the twenty-first transistor, the first region 221-1 of the active pattern 221 of the twenty-second transistor, the first region 231-1 of the active pattern 231 of the twenty-third transistor, the first region 241-1 of the active pattern of the twenty-fourth transistor, and the first region 251-1 and the second region 251-1 of the active pattern of the twenty-fifth transistor are set separately.

[0358] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first insulating film and a first conductive film on a substrate having the aforementioned pattern formed; patterning the first conductive film using a patterning process to form a first insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 22 and 23. Figure 22 is a schematic diagram of the first conductive layer pattern of the first display substrate and the second display substrate, and Figure 23 is a schematic diagram of the first display substrate and the second display substrate after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0359] In an exemplary embodiment, as shown in Figures 22 and 23, the first conductive layer pattern may include at least: the control electrode 12 of the first transistor to the control electrode 262 of the twenty-sixth transistor located in each stage of the shift register, the first plate C1-1 of the first capacitor to the first plate C7-1 of the seventh capacitor, the first connecting line L1 and the second connecting line L2.

[0360] In an exemplary embodiment, the gate electrode 12 of the first transistor, the control electrode 32 of the third transistor, and the control electrode 142 of the fourteenth transistor are integrally formed, and the shape of this integrally formed structure can be an "n" shape with the opening facing the display area. The gate electrode 12 of the first transistor and the control electrode 142 of the fourteenth transistor are arranged along a first direction D1 and are strip-shaped extending along the first direction D1. The control electrode 32 of the third transistor is connected to one end of the control electrode 142 of the fourteenth transistor and is zigzag-shaped.

[0361] In an exemplary embodiment, the gate electrode 22 of the second transistor and the gate electrode 82 of the eighth transistor are integrally formed. The gate electrode 22 of the second transistor can be shaped like an "n" with its opening facing the display area, and the gate electrode 82 of the eighth transistor can be shaped like a broken line and extends at least partially along the first direction D1.

[0362] In an exemplary embodiment, the control electrode 42 of the fourth transistor, the control electrode 162 of the sixteenth transistor, the control electrode 172 of the seventeenth transistor, and the first plate C3-1 of the third capacitor are integrally formed. The shape of the third capacitor C3-1 can be rectangular. The control electrodes 42 and 172 of the fourth transistor and the seventeenth transistor of the current stage shift register are located on the side of the third capacitor C3-1 closer to the next stage shift register. The control electrodes 42 and 172 of the fourth transistor and the seventeenth transistor are strip-shaped and extend along the second direction D2. The control electrode 162 of the sixteenth transistor is located on the side of the first plate C31 of the third capacitor closer to the display area. The shape of the control electrode 162 of the sixteenth transistor is "┐".

[0363] In an exemplary embodiment, the control electrode 52 of the fifth transistor is provided separately. The shape of the control electrode 52 of the fifth transistor may be "└".

[0364] In an exemplary embodiment, the control electrode 62 of the sixth transistor and the first plate C1-1 of the first capacitor are integrally formed. The control electrode 62 of the sixth transistor is located on the side of the first plate C11 of the first capacitor closer to the display area. The first plate C11 of the first capacitor can be shaped like a "┌", and the control electrode 62 of the sixth transistor is strip-shaped, extending at least partially along the second direction D2. The integral structure of the control electrode 62 of the sixth transistor and the first plate C11 of the first capacitor can also be shaped like an "n".

[0365] In an exemplary embodiment, the control electrode 72 of the seventh transistor is provided separately. The shape of the control electrode 72 of the seventh transistor may be "└".

[0366] In an exemplary embodiment, the control electrode 92 of the ninth transistor is provided separately. The control electrode 92 of the ninth transistor may be zigzag-shaped and extends at least partially along the first direction D1.

[0367] In an exemplary embodiment, the control electrode 102 of the tenth transistor is provided separately. The control electrode 102 of the tenth transistor may be in the shape of a comb, with the back of the comb located on the side of the plurality of comb teeth away from the display area, the back of the comb extending along the second direction D2, and at least one comb tooth extending along the first direction D1.

[0368] In an exemplary embodiment, the control electrode 112 of the eleventh transistor and the control electrode 152 of the fifteenth transistor are an integral structure. The integral structure of the control electrode 112 of the eleventh transistor and the control electrode 152 of the fifteenth transistor is strip-shaped and extends along the first direction D1.

[0369] In an exemplary embodiment, the control electrode 122 of the twelfth transistor is provided separately. The control electrode 122 of the twelfth transistor may be strip-shaped and at least partially extend along the first direction D1.

[0370] In an exemplary embodiment, the control electrode 132 of the thirteenth transistor is provided separately. The control electrode 132 of the thirteenth transistor is strip-shaped and extends along the first direction D1.

[0371] In an exemplary embodiment, the control electrode 182 of the eighteenth transistor, the control electrode 212 of the twenty-first transistor, and the first plate C5-1 of the fifth capacitor are integrated into a single structure. The control electrode 182 of the eighteenth transistor in this stage shift register is located on the side of the first plate C5-1 of the fifth capacitor closer to the next stage shift register, and the control electrode 212 of the twenty-first transistor is located on the side of the first plate C5-1 of the fifth capacitor closer to the display area. The control electrode 182 of the eighteenth transistor can be shaped like a "┘", the control electrode 212 of the twenty-first transistor can be shaped like an "n" with its opening facing the display area, and the first plate C5-1 of the fifth capacitor can be rectangular. The two gate structures of the control electrode 212 of the twenty-first transistor are straddling the active structure of the twenty-first transistor, making the twenty-first transistor a dual-gate transistor.

[0372] In an exemplary embodiment, the control electrode 192 of the nineteenth transistor and the first plate C7-1 of the seventh capacitor are integrally formed. The control electrode 192 of the nineteenth transistor is comb-shaped, with multiple comb teeth located on the side of the comb back closest to the display area. The comb back extends along the second direction D2, and at least one comb tooth extends along the first direction D1. The first plate C7-1 of the seventh capacitor may be rectangular in shape and located on the side of the comb back furthest from the display area.

[0373] In an exemplary embodiment, the control electrode 202 of the twentieth transistor, the control electrode 242 of the twenty-fourth transistor, and the first electrode C6-1 of the sixth capacitor are integrally formed. The control electrode 202 of the twentieth transistor is comb-shaped, with multiple comb teeth located on the back of the comb near the display area. The back of the comb extends along the second direction D2, and at least one comb tooth extends along the first direction D1. The control electrode 242 of the twenty-fourth transistor and the first electrode C6-1 of the sixth capacitor are located on the back of the comb away from the display area. The first electrode C6-1 of the sixth capacitor can be rectangular. The control electrode 242 of the twenty-fourth transistor is strip-shaped, extending along the first direction D1. The end of the control electrode 242 of the twenty-fourth transistor is connected to the middle of the back of the comb of the control electrode 202 of the twentieth transistor, and the first electrode C6-1 of the sixth capacitor is connected to the end of the back of the comb of the control electrode 202 of the twentieth transistor.

[0374] In an exemplary embodiment, the control electrode 222 of the twenty-second transistor is provided separately. The control electrode 222 of the twenty-second transistor is a strip-shaped electrode extending along the first direction D1.

[0375] In an exemplary embodiment, the control electrode 232 of the twenty-third transistor is provided separately. The shape of the control electrode 232 of the twenty-third transistor may be "└".

[0376] In an exemplary embodiment, the control electrode 242 of the 24th transistor and the control electrode 262 of the 26th transistor are integrally formed. The control electrode 242 of the 24th transistor is located on the side of the control electrode 262 of the 26th transistor away from the display area. The integral structure of the control electrode 242 of the 24th transistor and the control electrode 262 of the 26th transistor has a "comb-like" shape, with the comb teeth located on the back of the comb closer to the display area.

[0377] In an exemplary embodiment, the control electrode 252 of the twenty-fifth transistor is provided separately. The control electrode 252 of the twenty-fifth transistor is shaped like an inverted "n".

[0378] In an exemplary embodiment, the control electrode 262 of the twenty-sixth transistor is provided separately. The control electrode 262 of the twenty-sixth transistor is a strip-shaped electrode extending along the first direction D1.

[0379] In an exemplary embodiment, the first plate C2-1 of the second capacitor is disposed separately. The main body of the first plate C2-1 of the second capacitor may be rectangular in shape, and the first plate C2-1 of the second capacitor further includes a connecting portion located on the side of the main body of the first plate C2-1 of the second capacitor away from the display area.

[0380] In an exemplary embodiment, the first plate C4-1 of the fourth capacitor is provided separately. The first plate C4-1 of the fourth capacitor may be rectangular in shape.

[0381] In an exemplary embodiment, the first connecting line L1 is provided separately and is in the shape of a strip extending along the first direction D1.

[0382] In an exemplary embodiment, the second connecting line L2 is provided separately. The second connecting line L2 is zigzag in shape and extends at least partially along the first direction D1. The second connecting line L2 at least partially surrounds the side of the first plate C2-1 of the second capacitor.

[0383] In an exemplary embodiment, the control electrode 12 of the first transistor (which is also the control electrode 32 of the third transistor and the control electrode 142 of the fourteenth transistor) spans the active patterns of the first transistor, the third transistor, and the fourteenth transistor; the control electrode 22 of the second transistor (which is also the control electrode 82 of the eighth transistor) spans the active patterns of the second transistor and the eighth transistor; and the control electrode 42 of the fourth transistor (which is also the control electrode 162 of the sixteenth transistor and the control electrode 172 of the seventeenth transistor) spans the fourth transistor. On the active patterns of the sixteenth and seventeenth transistors, the control electrode 52 of the fifth transistor is connected across the active pattern of the fifth transistor; the control electrode 62 of the sixth transistor (which is also the first plate C1-1 of the first capacitor) is connected across the active pattern of the sixth transistor; the control electrode 72 of the seventh transistor is connected across the active pattern of the seventh transistor; the control electrode 92 of the ninth transistor is connected across the active pattern of the ninth transistor; the control electrode 102 of the tenth transistor is connected across the active pattern of the tenth transistor; and the control electrode 112 of the eleventh transistor (which is also the control electrode 15 of the fifteenth transistor) is connected across the active pattern of the eleventh transistor. 2) The control electrode 122 of the 12th transistor is connected across the active patterns of the 11th and 15th transistors. The control electrode 132 of the 13th transistor is connected across the active pattern of the 13th transistor. The control electrode 182 of the 18th transistor (which is also the control electrode 201 of the 21st transistor and the first plate C5-1 of the fifth capacitor) is connected across the active patterns of the 18th and 21st transistors. The control electrode 192 of the 19th transistor (which is also the first plate C7-1 of the seventh capacitor) is connected across the active pattern of the 19th transistor. On the case, the control electrode 202 of the twentieth transistor (which is also the control electrode 242 of the twenty-fourth transistor and the first plate C6-1 of the sixth capacitor) is positioned across the active pattern of the twentieth transistor and the active pattern of the twenty-fourth transistor, the control electrode 222 of the twenty-second transistor is positioned across the active pattern of the twenty-second transistor, the control electrode 232 of the twenty-third transistor is positioned across the active pattern of the twenty-third transistor, and the control electrode 252 of the twenty-fifth transistor is positioned across the active pattern of the twenty-fifth transistor. That is to say, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0384] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform a conductor-enhancing process on the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor to the twenty-sixth transistor, while the semiconductor layer in the region not shielded by the first conductive layer is conductor-enhanced. That is, the first and second regions of the active pattern of any one of the first to the twenty-sixth transistors are conductor-enhanced. As shown in FIG23, the second region of the active pattern of the twenty-second transistor in this disclosure after conductor-enhancing (which is also the second region of the active pattern of the twenty-third transistor) serves as the second electrode 224 of the twenty-second transistor (which is also the second electrode 234 of the twenty-third transistor), and the second region of the active pattern of the twenty-fourth transistor (which is also the second region of the active pattern of the twenty-sixth transistor) serves as the second electrode 244 of the twenty-fourth transistor (which is also the second electrode 264 of the twenty-sixth transistor).

[0385] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second insulating film and a second conductive film on a substrate having the aforementioned pattern, and patterning the second conductive film using a patterning process to form a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern located on the second insulating layer pattern, as shown in Figures 24 and 25. Figure 24 is a schematic diagram of the second conductive layer patterns of the first display substrate and the second display substrate, and Figure 25 is a schematic diagram of the first display substrate and the second display substrate after the second conductive layer pattern has been formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0386] In an exemplary embodiment, as shown in Figures 24 and 25, the second conductive layer pattern may include at least the second plate C1-2 of the first capacitor to the second plate C7-2 of the seventh capacitor in each stage of the shift register.

[0387] In an exemplary embodiment, the orthographic projection of the second plate C1-2 of the first capacitor onto the substrate at least partially overlaps with the orthographic projection of the first plate of the first capacitor onto the substrate. The area of ​​the second plate C1-2 of the first capacitor is larger than the area of ​​the first plate of the first capacitor. The shape of the second plate C1-2 of the first capacitor is the same as the shape of the first plate of the first capacitor.

[0388] In an exemplary embodiment, the orthographic projection of the second plate C2-2 of the second capacitor onto the substrate at least partially overlaps with the orthographic projection of the first plate of the second capacitor onto the substrate. The orthographic projection of the second plate C2-2 onto the substrate at least partially overlaps with the orthographic projection of the main body portion of the first plate of the second capacitor onto the substrate, but does not overlap with the orthographic projection of the connecting portion of the first plate of the second capacitor onto the substrate. The area of ​​the second plate C2-2 is larger than the area of ​​the main body portion of the first plate of the second capacitor. The shape of the second plate C2-2 is the same as the shape of the first plate of the second capacitor.

[0389] In an exemplary embodiment, the orthographic projection of the second plate C3-2 of the third capacitor onto the substrate at least partially overlaps with the orthographic projection of the first plate of the third capacitor onto the substrate. The second plate C3-2 of the third capacitor has a recess H that exposes the first plate of the third capacitor, and the area of ​​the second plate C3-2 is smaller than the area of ​​the first plate of the third capacitor. The shape of the second plate C3-2 of the third capacitor is the same as the shape of the first plate of the third capacitor.

[0390] In an exemplary embodiment, the orthographic projection of the second plate C4-2 of the fourth capacitor onto the substrate at least partially overlaps with the orthographic projection of the first plate of the fourth capacitor onto the substrate. The area of ​​the second plate C4-2 of the fourth capacitor is smaller than the area of ​​the first plate of the fourth capacitor.

[0391] In an exemplary embodiment, the orthographic projection of the second plate C5-2 of the fifth capacitor onto the substrate at least partially overlaps with the orthographic projection of the first plate of the fifth capacitor onto the substrate. The shape of the second plate C5-2 of the fifth capacitor is the same as the shape of the first plate of the fifth capacitor, and the area of ​​the second plate C5-2 of the fifth capacitor is larger than the area of ​​the first plate of the fifth capacitor.

[0392] In an exemplary embodiment, the orthographic projection of the second plate C6-2 of the sixth capacitor onto the substrate at least partially overlaps with the orthographic projection of the first plate of the sixth capacitor onto the substrate. The shape of the second plate C6-2 of the sixth capacitor is the same as the shape of the first plate of the sixth capacitor, and the area of ​​the second plate C6-2 of the sixth capacitor is larger than the area of ​​the first plate of the sixth capacitor.

[0393] In an exemplary embodiment, the orthographic projection of the second plate C7-2 of the seventh capacitor onto the substrate at least partially overlaps with the orthographic projection of the first plate of the seventh capacitor onto the substrate. The shape of the second plate C7-2 of the seventh capacitor is the same as the shape of the first plate of the seventh capacitor, and the area of ​​the second plate C7-2 of the seventh capacitor is larger than the area of ​​the first plate of the seventh capacitor.

[0394] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the third insulating film using a patterning process to form a third insulating layer pattern covering the aforementioned structure. The third insulating layer has a plurality of via patterns, as shown in FIG26. FIG26 is a schematic diagram of the first display substrate and the second display substrate after the third insulating layer pattern has been formed.

[0395] In an exemplary embodiment, as shown in FIG26, the third insulating layer pattern may include at least: the first via V1 to the sixty-ninth via V69 located in each stage of the shift register.

[0396] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the orthographic projection of the first region of the active pattern of the first transistor onto the substrate. The first insulating layer and the second insulating layer within the first via V1 are etched away, exposing the surface of the first region of the active pattern of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor (which is also the first electrode of the fourteenth transistor) to be connected to the first region of the active pattern of the first transistor through the via.

[0397] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the orthographic projection of the second region of the active pattern of the first transistor onto the substrate. The first and second insulating layers within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor to be connected to the second region of the active pattern of the first transistor through the via.

[0398] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the second transistor onto the substrate. The first and second insulating layers within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the second transistor. The third via V3 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first region of the active pattern of the second transistor through the via.

[0399] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the second region of the active pattern of the second transistor (which is also the first region of the active pattern of the eleventh transistor) onto the substrate. The first and second insulating layers within the fourth via V4 are etched away, exposing the surface of the second region of the active pattern of the second transistor (which is also the first region of the active pattern of the eleventh transistor). The fourth via V4 is configured to allow the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to be connected to the second region of the active pattern of the second transistor (which is also the first region of the active pattern of the eleventh transistor) through the via.

[0400] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the orthographic projection of the first region of the active pattern of the third transistor onto the substrate. The first and second insulating layers within the fifth via V5 are etched away, exposing the surface of the first region of the active pattern of the third transistor. The fifth via V5 is configured to allow the first electrode of the subsequently formed third transistor to be connected to the first region of the active pattern of the third transistor through the via.

[0401] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the second region of the active pattern of the third transistor onto the substrate. The first and second insulating layers within the sixth via V6 are etched away, exposing the surface of the second region of the active pattern of the third transistor. The sixth via V6 is configured to allow the second terminal of the subsequently formed second transistor (which is also the second terminal of the third transistor and the first terminal of the eleventh transistor) to be connected to the second region of the active pattern of the third transistor through the via.

[0402] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The first and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The seventh via V7 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0403] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the fourth transistor onto the substrate. The first and second insulating layers within the eighth via V8 are etched away, exposing the surface of the second region of the active pattern of the fourth transistor. The eighth via V8 is configured to allow the second electrode of the subsequently formed fourth transistor to be connected to the second region of the active pattern of the fourth transistor through the via.

[0404] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The first and second insulating layers within the ninth via V9 are etched away, exposing the surface of the second region of the active pattern of the fifth transistor. The ninth via V9 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0405] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the fifth transistor onto the substrate. The first and second insulating layers within the tenth via V10 are etched away, exposing the surface of the second region of the active pattern of the fifth transistor. The tenth via V10 is configured to allow the second electrode of the subsequently formed fifth transistor to be connected to the second region of the active pattern of the fifth transistor through the via.

[0406] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the sixth transistor onto the substrate. The first and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the first region of the active pattern of the sixth transistor. The eleventh via V11 is configured to allow the first electrode of the subsequently formed sixth transistor to be connected to the first region of the active pattern of the sixth transistor through the via.

[0407] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the orthographic projection of the second region of the active pattern of the sixth transistor onto the substrate. The first and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the second region of the active pattern of the sixth transistor. The twelfth via V12 is configured to allow the second terminal of the subsequently formed sixth transistor (which is also the first terminal of the seventh transistor) to be connected to the second region of the active pattern of the sixth transistor through the via.

[0408] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The first and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first region of the active pattern of the seventh transistor. The thirteenth via V13 is configured to allow the second terminal of the subsequently formed sixth transistor (which is also the first terminal of the seventh transistor) to be connected to the first region of the active pattern of the seventh transistor through the via.

[0409] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the orthographic projection of the second region of the active pattern of the seventh transistor onto the substrate. The first and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the second region of the active pattern of the seventh transistor. The fourteenth via V14 is configured to allow the second terminal of the subsequently formed seventh transistor (which is also the second terminal of the eighth transistor) to be connected to the second region of the active pattern of the seventh transistor through the via.

[0410] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the first region of the active pattern of the eighth transistor (the first region of the active pattern of the thirteenth transistor) onto the substrate. The first and second insulating layers within the fifteenth via V15 are etched away, exposing the surface of the first region of the active pattern of the eighth transistor (the first region of the active pattern of the thirteenth transistor). The fifteenth via V15 is configured to allow the first electrode of the subsequently formed eighth transistor (which is also the first electrode of the ninth transistor and the first electrode of the thirteenth transistor) to be connected to the first region of the active pattern of the eighth transistor (the first region of the active pattern of the thirteenth transistor) through the via.

[0411] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate lies within the orthographic projection of the second region of the active pattern of the eighth transistor onto the substrate. The first and second insulating layers within the sixteenth via V16 are etched away, exposing the surface of the second region of the active pattern of the eighth transistor. The sixteenth via V16 is configured to allow the second terminal of the subsequently formed seventh transistor (which is also the second terminal of the eighth transistor) to be connected to the second region of the active pattern of the eighth transistor through the via.

[0412] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the orthographic projection of the first region of the active pattern of the ninth transistor onto the substrate. The first and second insulating layers within the seventeenth via V17 are etched away, exposing the surface of the first region of the active pattern of the ninth transistor. The seventeenth via V17 is configured to allow the first electrode of the subsequently formed eighth transistor (which is also the first electrode of the ninth transistor and the first electrode of the thirteenth transistor) to be connected to the first region of the active pattern of the ninth transistor through the via.

[0413] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate lies within the range of the orthographic projection of the second region of the active pattern of the ninth transistor (which is also the second region of the active pattern of the tenth transistor) onto the substrate. The first and second insulating layers within the eighteenth via V18 are etched away, exposing the surface of the second region of the active pattern of the ninth transistor (which is also the second region of the active pattern of the tenth transistor). The eighteenth via V18 is configured to allow the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to be connected to the second region of the active pattern of the ninth transistor (which is also the second region of the active pattern of the tenth transistor) through the via.

[0414] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 onto the substrate is within the orthographic projection range of the first region of the active pattern of the tenth transistor onto the substrate. The first and second insulating layers within the nineteenth via V19 are etched away, exposing the surface of the first region of the active pattern of the tenth transistor. The nineteenth via V19 is configured to allow the first electrode of the subsequently formed tenth transistor to be connected to the first region of the active pattern of the tenth transistor through the via.

[0415] In an exemplary embodiment, the orthographic projection of the 20th via V20 onto the substrate is within the orthographic projection of the second region of the active pattern of the 11th transistor onto the substrate. The first and second insulating layers within the 20th via V20 are etched away, exposing the surface of the second region of the active pattern of the 11th transistor. The 20th via V20 is configured to allow the second electrode of the subsequently formed 11th transistor to be connected to the second region of the active pattern of the 11th transistor through the via.

[0416] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 onto the substrate lies within the orthographic projection of the first region of the active pattern of the twelfth transistor (which is also the second region of the active pattern of the thirteenth transistor) onto the substrate. The first and second insulating layers within the twenty-first via V21 are etched away, exposing the surface of the first region of the active pattern of the twelfth transistor (which is also the second region of the active pattern of the thirteenth transistor). The twenty-first via V21 is configured to allow the first electrode of the subsequently formed twelfth transistor (which is also the second electrode of the thirteenth transistor and the first electrode of the eighteenth transistor) to be connected to the first region of the active pattern of the twelfth transistor (which is also the second region of the active pattern of the thirteenth transistor) through the via.

[0417] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate lies within the range of the orthographic projection of the second region of the active pattern of the 12th transistor (which is also the second region of the active pattern of the 16th transistor) onto the substrate. The first and second insulating layers within the 22nd via V22 are etched away, exposing the surface of the second region of the active pattern of the 12th transistor (which is also the second region of the active pattern of the 16th transistor). The 22nd via V22 is configured to allow the second electrode of the subsequently formed 12th transistor (which is also the second electrode of the 16th transistor) to be connected to the second region of the active pattern of the 12th transistor (which is also the second region of the active pattern of the 16th transistor) through the via.

[0418] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate is within the orthographic projection of the first region of the active pattern of the 14th transistor onto the substrate. The first and second insulating layers within the 23rd via V23 are etched away, exposing the surface of the first region of the active pattern of the 14th transistor. The 23rd via V23 is configured to allow the first electrode of the subsequently formed first transistor (which is also the first electrode of the 14th transistor) to be connected to the first region of the active pattern of the 14th transistor through the via.

[0419] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate is within the orthographic projection of the second region of the active pattern of the 14th transistor onto the substrate. The first and second insulating layers within the 24th via V24 are etched away, exposing the surface of the second region of the active pattern of the 14th transistor. The 24th via V24 is configured to allow the second terminal of the subsequently formed 14th transistor (which is also the first terminal of the 15th transistor) to be connected to the second region of the active pattern of the 14th transistor through the via.

[0420] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate is within the orthographic projection of the first region of the active pattern of the 15th transistor onto the substrate. The first and second insulating layers within the 25th via V25 are etched away, exposing the surface of the first region of the active pattern of the 15th transistor. The 25th via V25 is configured to allow the second terminal of the subsequently formed 14th transistor (which is also the first terminal of the 15th transistor) to be connected to the first region of the active pattern of the 15th transistor through the via.

[0421] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate is within the orthographic projection of the second region of the active pattern of the 15th transistor onto the substrate. The first and second insulating layers within the 26th via V26 are etched away, exposing the surface of the second region of the active pattern of the 15th transistor. The 26th via V26 is configured to allow the second electrode of the subsequently formed 15th transistor to be connected to the second region of the active pattern of the 15th transistor through the via.

[0422] In an exemplary embodiment, the orthographic projection of the 27th via V27 onto the substrate lies within the orthographic projection of the first region of the active pattern of the 16th transistor (which is also the first region of the active pattern of the 17th transistor) onto the substrate. The first and second insulating layers within the 27th via V27 are etched away, exposing the surface of the first region of the active pattern of the 16th transistor (which is also the first region of the active pattern of the 17th transistor). The 27th via V27 is configured to allow the first electrode of the subsequently formed 16th transistor (which is also the first electrode of the 17th transistor) to be connected to the first region of the active pattern of the 16th transistor (which is also the first region of the active pattern of the 17th transistor) through the via.

[0423] In an exemplary embodiment, the orthographic projection of the 28th via V28 onto the substrate is within the orthographic projection of the second region of the active pattern of the 17th transistor onto the substrate. The first and second insulating layers within the 28th via V28 are etched away, exposing the surface of the second region of the active pattern of the 17th transistor. The 28th via V28 is configured to allow the second terminal of the subsequently formed 17th transistor (which is also the second terminal of the 18th transistor) to be connected to the second region of the active pattern of the 17th transistor through the via.

[0424] In an exemplary embodiment, the orthographic projection of the 29th via V29 onto the substrate is within the orthographic projection of the first region of the active pattern of the 18th transistor onto the substrate. The first and second insulating layers within the 29th via V29 are etched away, exposing the surface of the first region of the active pattern of the 18th transistor. The 29th via V29 is configured to allow the first terminal of the subsequently formed 12th transistor (which is also the second terminal of the 13th transistor and the first terminal of the 18th transistor) to be connected to the first region of the active pattern of the 18th transistor through the via.

[0425] In an exemplary embodiment, the orthographic projection of the thirtieth via V30 onto the substrate is within the orthographic projection of the second region of the active pattern of the eighteenth transistor onto the substrate. The first and second insulating layers within the thirtieth via V30 are etched away, exposing the surface of the second region of the active pattern of the eighteenth transistor. The thirtieth via V30 is configured to allow the second terminal of the subsequently formed seventeenth transistor (which is also the second terminal of the eighteenth transistor) to be connected to the second region of the active pattern of the eighteenth transistor through the via.

[0426] In an exemplary embodiment, the orthographic projection of the 31st via V31 onto the substrate is within the orthographic projection of the first region of the active pattern of the 19th transistor onto the substrate. The first and second insulating layers within the 31st via V31 are etched away, exposing the surface of the first region of the active pattern of the 19th transistor. The 31st via V31 is configured to allow the first electrode of the subsequently formed 19th transistor to be connected to the first region of the active pattern of the 19th transistor through the via.

[0427] In an exemplary embodiment, the orthographic projection of the 32nd via V32 onto the substrate lies within the range of the orthographic projection of the second region of the active pattern of the 19th transistor (which is also the second region of the active pattern of the 20th transistor) onto the substrate. The first and second insulating layers within the 32nd via V32 are etched away, exposing the surface of the second region of the active pattern of the 19th transistor (which is also the second region of the active pattern of the 20th transistor). The 32nd via V32 is configured to allow the second electrode of the subsequently formed 19th transistor (which is also the second electrode of the 20th transistor) to be connected to the second region of the active pattern of the 19th transistor (which is also the second region of the active pattern of the 20th transistor) through the via.

[0428] In an exemplary embodiment, the orthographic projection of the 33rd via V33 onto the substrate is within the orthographic projection of the first region of the active pattern of the 20th transistor onto the substrate. The first and second insulating layers within the 33rd via V33 are etched away, exposing the surface of the first region of the active pattern of the 20th transistor. The 33rd via V33 is configured to allow the first electrode of the subsequently formed 20th transistor to be connected to the first region of the active pattern of the 20th transistor through the via.

[0429] In an exemplary embodiment, the orthographic projection of the 34th via V34 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the 21st transistor onto the substrate. The first and second insulating layers within the 34th via V34 are etched away, exposing the surface of the first region of the active pattern of the 21st transistor. The 34th via V34 is configured to allow the first electrode of the subsequently formed 21st transistor to be connected to the first region of the active pattern of the 21st transistor through the via.

[0430] In an exemplary embodiment, the orthographic projection of the 35th via V35 onto the substrate lies within the orthographic projection of the second region of the active pattern of the 21st transistor (the first region of the active pattern of the 26th transistor) onto the substrate. The first and second insulating layers within the 35th via V35 are etched away, exposing the surface of the second region of the active pattern of the 21st transistor (the first region of the active pattern of the 26th transistor). The 35th via V35 is configured to allow the second electrode of the subsequently formed 21st transistor (which is also the second electrode of the 26th transistor) to be connected to the second region of the active pattern of the 21st transistor (the first region of the active pattern of the 26th transistor) through the via.

[0431] In an exemplary embodiment, the orthographic projection of the 36th via V36 onto the substrate is within the orthographic projection of the first region of the active pattern of the 22nd transistor onto the substrate. The first and second insulating layers within the 36th via V36 are etched away, exposing the surface of the first region of the active pattern of the 22nd transistor. The 36th via V36 is configured to allow the first electrode of the subsequently formed 22nd transistor to be connected to the first region of the active pattern of the 22nd transistor through the via.

[0432] In an exemplary embodiment, the orthographic projection of the 37th via V37 onto the substrate is within the orthographic projection of the first region of the active pattern of the 23rd transistor onto the substrate. The first and second insulating layers within the 37th via V37 are etched away, exposing the surface of the first region of the active pattern of the 23rd transistor. The 37th via V37 is configured to allow the first electrode of the subsequently formed 23rd transistor to be connected to the first region of the active pattern of the 23rd transistor through the via.

[0433] In an exemplary embodiment, the orthographic projection of the 38th via V38 onto the substrate is within the orthographic projection of the first region of the active pattern of the 24th transistor onto the substrate. The first and second insulating layers within the 38th via V38 are etched away, exposing the surface of the first region of the active pattern of the 24th transistor. The 38th via V38 is configured to allow the first electrode of the subsequently formed 24th transistor to be connected to the first region of the active pattern of the 24th transistor through the via.

[0434] In an exemplary embodiment, the orthographic projection of the 39th via V39 onto the substrate is within the orthographic projection of the first region of the active pattern of the 25th transistor onto the substrate. The first and second insulating layers within the 39th via V39 are etched away, exposing the surface of the first region of the active pattern of the 25th transistor. The 39th via V39 is configured to allow the first electrode of the subsequently formed 25th transistor to be connected to the first region of the active pattern of the 25th transistor through the via.

[0435] In an exemplary embodiment, the orthographic projection of the 40th via V40 onto the substrate lies within the orthographic projection of the second region of the active pattern of the 25th transistor onto the substrate. The first and second insulating layers within the 40th via V40 are etched away, exposing the surface of the second region of the active pattern of the 25th transistor. The 40th via V40 is configured to allow the second electrode of the subsequently formed 25th transistor to be connected to the second region of the active pattern of the 25th transistor through the via.

[0436] In an exemplary embodiment, the orthographic projection of the forty-first via V41 onto the substrate lies within the range of the orthographic projection of the gate electrode of the first transistor (which is also the gate electrode of the third transistor and the gate electrode of the fourteenth transistor) onto the substrate. The second insulating layer within the forty-first via V41 is etched away, exposing the surface of the gate electrode of the first transistor (which is also the gate electrode of the third transistor and the gate electrode of the fourteenth transistor). The forty-first via V41 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the gate electrode of the first transistor (which is also the gate electrode of the third transistor and the gate electrode of the fourteenth transistor) through the via.

[0437] In an exemplary embodiment, the orthographic projection of the forty-second via V42 onto the substrate lies within the orthographic projection of the gate electrode of the second transistor (which is also the gate electrode of the eighth transistor) onto the substrate. The second insulating layer within the forty-second via V42 is etched away, exposing the surface of the gate electrode of the second transistor (which is also the gate electrode of the eighth transistor). The forty-second via V42 is configured to allow the second electrode of the subsequently formed first transistor and the first electrode of the twelfth transistor (which is also the second electrode of the thirteenth transistor and the first electrode of the eighteenth transistor) to be connected to the gate electrode of the second transistor (which is also the gate electrode of the eighth transistor) through the via.

[0438] In an exemplary embodiment, the orthogonal projection of the forty-third via V43 onto the substrate lies within the range of the orthogonal projection of the gate electrode of the fourth transistor (which is also the gate electrode of the sixteenth transistor, the gate electrode of the seventeenth transistor, and the first plate of the third capacitor) onto the substrate. The second insulating layer within the forty-third via V43 is etched away, exposing the surface of the gate electrode of the fourth transistor (which is also the gate electrode of the sixteenth transistor, the gate electrode of the seventeenth transistor, and the first plate of the third capacitor). The forty-third via V43 is configured to allow the second electrode of the subsequently formed fifteenth transistor to be connected to the gate electrode of the fourth transistor (which is also the gate electrode of the sixteenth transistor, the gate electrode of the seventeenth transistor, and the first plate of the third capacitor) through the via.

[0439] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 onto the substrate is within the range of the orthographic projection of the gate electrode of the fifth transistor onto the substrate. The second insulating layer within the forty-fourth via V44 is etched away, exposing the surface of the gate electrode of the fifth transistor. The forty-fourth via V44 is configured to allow the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to be connected to the gate electrode of the fifth transistor through the via.

[0440] In an exemplary embodiment, the orthographic projection of the forty-fifth via V45 onto the substrate is within the range of the orthographic projection of the gate electrode of the sixth transistor (the first plate of the first capacitor) onto the substrate. The second insulating layer within the forty-fifth via V45 is etched away, exposing the surface of the gate electrode of the sixth transistor (the first plate of the first capacitor). The forty-fifth via V45 is configured to allow the second electrode of the subsequently formed eleventh transistor to be connected to the gate electrode of the sixth transistor (the first plate of the first capacitor) through the via.

[0441] In an exemplary embodiment, the orthographic projection of the forty-sixth via V46 onto the substrate is within the range of the orthographic projection of the gate electrode of the seventh transistor onto the substrate. The second insulating layer within the forty-sixth via V46 is etched away, exposing the surface of the gate electrode of the seventh transistor. The forty-sixth via V46 is configured to allow the first electrode of the sixth transistor to be connected to the gate electrode of the seventh transistor through the via.

[0442] In an exemplary embodiment, the orthographic projection of the forty-seventh via V47 onto the substrate is within the range of the orthographic projection of the gate electrode of the ninth transistor onto the substrate. The second insulating layer within the forty-seventh via V47 is etched away, exposing the surface of the gate electrode of the ninth transistor. The forty-seventh via V47 is configured to allow the second electrode of the subsequently formed seventh transistor (which is also the second electrode of the eighth transistor) and the first electrode of the twenty-first transistor to be connected to the gate electrode of the ninth transistor through the via.

[0443] In an exemplary embodiment, the orthographic projection of the forty-eighth via V48 on the substrate is within the range of the orthographic projection of the first plate of the second capacitor on the substrate. The second insulating layer within the forty-eighth via V48 is etched away, exposing the surface of the first plate of the second capacitor. The forty-eighth via V48 is configured to allow the second electrode of the subsequently formed seventh transistor (which is also the second electrode of the eighth transistor) to be connected to the first plate of the second capacitor through the via.

[0444] In an exemplary embodiment, the orthographic projection of the forty-ninth via V49 onto the substrate is within the range of the orthographic projection of the gate electrode of the tenth transistor onto the substrate. The second insulating layer within the forty-ninth via V49 is etched away, exposing the surface of the gate electrode of the tenth transistor. The forty-ninth via V49 is configured to allow the second electrode of the subsequently formed twelfth transistor (which is also the second electrode of the sixteenth transistor) to be connected to the gate electrode of the tenth transistor through the via.

[0445] In an exemplary embodiment, the orthographic projection of the fiftieth via V50 onto the substrate lies within the range of the orthographic projection of the gate electrode of the eleventh transistor (which is also the gate electrode of the fifteenth transistor) onto the substrate. The second insulating layer within the fiftieth via V50 is etched away, exposing the surface of the gate electrode of the eleventh transistor (which is also the gate electrode of the fifteenth transistor). The fiftieth via V50 is configured to allow the first electrode of a subsequently formed third transistor to be connected to the gate electrode of the eleventh transistor (which is also the gate electrode of the fifteenth transistor) through the via.

[0446] In an exemplary embodiment, the orthographic projection of the 51st via V51 onto the substrate is within the range of the orthographic projection of the gate electrode of the 12th transistor onto the substrate. The second insulating layer within the 51st via V51 is etched away, exposing the surface of the gate electrode of the 12th transistor. The 51st via V51 is configured to allow the first electrode of a subsequently formed third transistor to be connected to the gate electrode of the 12th transistor through the via.

[0447] In an exemplary embodiment, the orthographic projection of the 52nd via V52 onto the substrate is within the range of the orthographic projection of the gate electrode of the 13th transistor onto the substrate. The second insulating layer within the 52nd via V52 is etched away, exposing the surface of the gate electrode of the 13th transistor. The 52nd via V52 is configured to allow the subsequently formed first connection electrode E1 to be connected to the gate electrode of the 13th transistor through the via.

[0448] In an exemplary embodiment, the orthographic projection of the 53rd via V53 onto the substrate lies within the range of the orthographic projection of the gate electrode of the 18th transistor (the gate electrode of the 21st transistor and the first plate of the 5th capacitor) onto the substrate. The second insulating layer within the 53rd via V53 is etched away, exposing the surface of the gate electrode of the 18th transistor (the gate electrode of the 21st transistor and the first plate of the 5th capacitor). The 53rd via V53 is configured to allow the first electrode of the subsequently formed 22nd transistor and the second electrode of the 25th transistor to be connected to the gate electrode of the 18th transistor (the gate electrode of the 21st transistor and the first plate of the 5th capacitor) through the via.

[0449] In an exemplary embodiment, the orthographic projection of the 54th via V54 onto the substrate lies within the orthographic projection of the gate electrode of the 19th transistor (which is also the first plate of the 7th capacitor) onto the substrate. The second insulating layer within the 54th via V54 is etched away, exposing the surface of the gate electrode of the 19th transistor (which is also the first plate of the 7th capacitor) (which is also the first plate of the 4th capacitor). The 54th via V54 is configured to allow the second electrode of the subsequently formed 21st transistor (which is also the first electrode of the 26th transistor) to be connected to the gate electrode of the 19th transistor through the via.

[0450] In an exemplary embodiment, the orthographic projection of the 55th via V55 onto the substrate lies within the orthographic projection of the gate electrode of the 20th transistor (which is also the control electrode of the 24th transistor and the first plate of the 6th capacitor) onto the substrate. The second insulating layer within the 55th via V55 is etched away, exposing the surface of the gate electrode of the 20th transistor. The 55th via V55 is configured to allow a subsequently formed second connection electrode to be connected to the gate electrode of the 20th transistor (which is also the control electrode of the 24th transistor and the first plate of the 6th capacitor) through the via.

[0451] In an exemplary embodiment, the orthographic projection of the 56th via V56 onto the substrate is within the range of the orthographic projection of the gate electrode of the 22nd transistor onto the substrate. The second insulating layer within the 56th via V56 is etched away, exposing the surface of the gate electrode of the 22nd transistor. The 56th via V56 is configured to allow a subsequently formed first cross-stage interconnect to be connected to the gate electrode of the 22nd transistor through the via.

[0452] In an exemplary embodiment, the orthographic projection of the 57th via V57 on the substrate is within the range of the orthographic projection of the gate electrode of the 23rd transistor on the substrate. The 57th via V57 exposes the surface of the gate electrode of the 23rd transistor. The 57th via V57 is configured to allow a subsequently formed third connection electrode to be connected to the gate electrode of the 23rd transistor through the via.

[0453] In an exemplary embodiment, the orthographic projection of the 58th via V58 onto the substrate is within the range of the orthographic projection of the gate electrode of the 25th transistor onto the substrate. The second insulating layer within the 58th via V58 is etched away, exposing the surface of the gate electrode of the 25th transistor. The 58th via V58 is configured to allow a third cross-stage connection line subsequently formed to connect to the second electrode of the fourth transistor of the (n-1)th stage shift register to the gate electrode of the 25th transistor through the via.

[0454] In an exemplary embodiment, the orthographic projection of the 59th via V59 onto the substrate is within the range of the orthographic projection of the gate electrode of the 26th transistor onto the substrate. The second insulating layer within the 59th via V59 is etched away, exposing the surface of the gate electrode of the 26th transistor. The 59th via V59 is configured to allow the second electrode of the subsequently formed 19th transistor (which is also the second electrode of the 20th transistor) to be connected to the gate electrode of the 26th transistor through the via.

[0455] In an exemplary embodiment, the orthographic projection of the sixtieth via V60 on the substrate is within the range of the orthographic projection of the first plate of the fourth capacitor on the substrate. The second insulating layer within the sixtieth via V60 is etched away, exposing the surface of the first plate of the fourth capacitor. The sixtieth via V60 is configured to allow a subsequently formed first cross-stage connection line to be connected to the first plate of the fourth capacitor through the via.

[0456] In an exemplary embodiment, the orthographic projection of the sixty-first via V61 on the substrate is within the range of the orthographic projection of the first connection line on the substrate. The second insulating layer within the sixty-first via V61 is etched away, exposing the surface of the first connection line. The sixty-first via V61 is configured to allow the second electrode of the subsequently formed seventeenth transistor (which is also the second electrode of the eighteenth transistor) and the second connection electrode to be connected to the first connection line through the via.

[0457] In an exemplary embodiment, the orthographic projection of the sixty-second via V62 on the substrate is within the range of the orthographic projection of the second connection line on the substrate. The second insulating layer within the sixty-second via V62 is etched away, exposing the surface of the second connection line. The sixty-second via V62 is configured to allow the subsequently formed fourth connection electrode and the second electrode of the sixth transistor (which is also the first electrode of the seventh transistor) to be connected to the second connection line through the via.

[0458] In an exemplary embodiment, the orthographic projection of the sixty-third via V63 on the substrate is within the range of the orthographic projection of the second plate of the first capacitor on the substrate. The sixty-third via V63 exposes the surface of the second plate of the first capacitor. The sixty-third via V63 is configured to allow the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to be connected to the second plate of the first capacitor through the via.

[0459] In an exemplary embodiment, the orthographic projection of the sixty-fourth via V64 on the substrate is within the range of the orthographic projection of the second plate of the second capacitor on the substrate. The sixty-fourth via V64 exposes the surface of the second plate of the second capacitor. The sixty-fourth via V64 is configured to allow the subsequently formed fifth connection electrode to be connected to the second plate of the second capacitor through the via.

[0460] In an exemplary embodiment, the orthographic projection of the sixty-fifth via V65 on the substrate is within the range of the orthographic projection of the second plate of the third capacitor on the substrate. The sixty-fifth via V65 exposes the surface of the second plate of the third capacitor. The sixty-fifth via V65 is configured to allow the second electrode of the subsequently formed fourth transistor to be connected to the second plate of the third capacitor through the via.

[0461] In an exemplary embodiment, the orthographic projection of the sixty-sixth via V66 onto the substrate is within the range of the orthographic projection of the second plate of the seventh capacitor onto the substrate. The sixty-sixth via V66 exposes the surface of the second plate of the seventh capacitor. The sixty-sixth via V66 is configured to allow the first electrode of the subsequently formed nineteenth transistor to be connected to the second plate of the seventh capacitor through the via.

[0462] In an exemplary embodiment, the orthographic projection of the sixty-seventh via V67 onto the substrate is within the range of the orthographic projection of the second plate of the fifth capacitor onto the substrate. The sixty-seventh via V67 exposes the surface of the second plate of the fifth capacitor. The sixty-seventh via V67 is configured to allow the second electrode of the subsequently formed twenty-first transistor (which is also the first electrode of the twenty-sixth transistor) to be connected to the second plate of the fifth capacitor through the via.

[0463] In an exemplary embodiment, the orthographic projection of the sixty-eighth via V68 onto the substrate is within the range of the orthographic projection of the second plate of the sixth capacitor onto the substrate. The sixty-eighth via V68 exposes the surface of the second plate of the sixth capacitor. The sixty-eighth via V68 is configured to allow the second electrode of the subsequently formed nineteenth transistor (which is also the second electrode of the twentieth transistor) to be connected to the second plate of the sixth capacitor through the via.

[0464] In an exemplary embodiment, the orthographic projection of the sixty-ninth via V69 on the substrate is within the range of the orthographic projection of the second plate of the fourth capacitor on the substrate. The sixty-ninth via V69 exposes the surface of the second plate of the fourth capacitor. The sixty-ninth via V69 is configured to allow the subsequently formed sixth connection electrode to be connected to the second plate of the fourth capacitor through the via.

[0465] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fifth insulating layer, as shown in Figures 27 and 28. Figure 27 is a schematic diagram of the third conductive layer pattern of the first display substrate and the second display substrate, and Figure 28 is a schematic diagram of the first display substrate and the second display substrate after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0466] In an exemplary embodiment, as shown in Figures 27 and 28, the third conductive layer pattern may include at least: the first electrode 13 and the second electrode 14 of the first transistor to the first electrode 163 and the second electrode 164 of the sixteenth transistor, the first electrode 183 and the second electrode 184 of the eighteenth transistor, the first electrode 193 and the second electrode 194 of the nineteenth transistor, the first electrode 203 and the second electrode 204 of the twentieth transistor, the first electrode 213 and the second electrode 214 of the twenty-first transistor, the first electrode 223 of the twenty-second transistor, the first electrode 233 of the twenty-third transistor, the first electrode 243 of the twenty-fourth transistor, the first electrode 253 and the second electrode 254 of the twenty-fifth transistor, and the first electrode 263 of the second sixth transistor, the first connecting electrode E1 to the sixth connecting electrode E6, and the third cross-stage connecting line NL3 and the cascaded output connecting line NL1.

[0467] In an exemplary embodiment, the first electrode 13 of the first transistor and the first electrode 143 of the fourteenth transistor are integrally formed. The first electrode 13 of the first transistor (which is also the first electrode 143 of the fourteenth transistor) is strip-shaped, extending along the first direction D1. The first electrode 13 of the first transistor (which is also the first electrode 143 of the fourteenth transistor) is connected to the first region of the active pattern of the first transistor through a first via, and to the first region of the active pattern of the fourteenth transistor through a twenty-third via.

[0468] In an exemplary embodiment, the second electrode 14 of the first transistor is provided separately. The shape of the second electrode 14 of the first transistor may be "┐". The second electrode 14 of the first transistor is connected to the second region of the active pattern of the first transistor through a second via, and is connected to the control electrode of the second transistor (which is also the control electrode of the eighth transistor) through a forty-second via.

[0469] In an exemplary embodiment, the first electrode 23 of the second transistor is provided separately. The first electrode 23 of the second transistor is strip-shaped and extends along the second direction D2. The first electrode 23 of the second transistor is connected to the first region of the active pattern of the second transistor through a third via, and is connected to the gate electrode of the first transistor (which is also the gate electrode of the third transistor and the gate electrode of the fourteenth transistor) through a forty-first via.

[0470] In an exemplary embodiment, the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 113 of the eleventh transistor are integrally formed. This integral structure is zigzag-shaped and extends at least partially along the first direction D1. The second electrode 24 of the second transistor (which is also the second electrode 34 of the third transistor and the first electrode 113 of the eleventh transistor) is connected to the second region of the active pattern of the second transistor (which is also the first region of the active pattern of the eleventh transistor) through a fourth via, to the second region of the active pattern of the third transistor through a sixth via, and to the control electrode of the fifth transistor through a forty-fourth via.

[0471] In an exemplary embodiment, the first electrode 33 of the third transistor is provided separately. The shape of the first electrode 33 of the third transistor may be "└". The first electrode 33 of the third transistor is connected to the first region of the active pattern of the third transistor through the fifth via, connected to the control electrode of the eleventh transistor (which is also the control electrode of the fifteenth transistor) through the fiftieth via, and connected to the gate electrode of the twelfth transistor through the fifty-first via.

[0472] In an exemplary embodiment, the first electrode 43 of the fourth transistor is provided separately. The first electrode 43 of the fourth transistor is block-shaped. The first electrode 43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through a seventh via.

[0473] In an exemplary embodiment, the second electrode 44 of the fourth transistor is separately provided. The second electrode 44 of the fourth transistor is connected to the second region of the active pattern of the fourth transistor through an eighth via, connected to the second region of the active pattern of the fifth transistor through a tenth via, and connected to the second plate of the third capacitor through a sixty-fifth via.

[0474] In an exemplary embodiment, the first electrode 53 of the fifth transistor is separately disposed, and the first electrode 53 of the fifth transistor is strip-shaped and extends along the second direction D2. The first electrode 53 of the fifth transistor is connected to the first region of the active pattern of the fifth transistor through a ninth via.

[0475] In an exemplary embodiment, the second electrode 54 of the fifth transistor is separately disposed, and the second electrode 54 of the fifth transistor is strip-shaped and extends along the first direction D1. The second electrode 54 of the fifth transistor is connected to the second region of the active pattern of the fifth transistor through a tenth via.

[0476] In an exemplary embodiment, the first electrode 63 of the sixth transistor is provided separately. The first electrode 63 of the sixth transistor is in the shape of an "I". The first electrode 63 of the sixth transistor is connected to the first region of the active pattern of the sixth transistor through an eleventh via, and is connected to the control electrode of the seventh transistor through a forty-sixth via.

[0477] In an exemplary embodiment, the second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor are an integral structure. The integral structure of the second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor has a zigzag shape and extends at least partially along the first direction D1. The second electrode 64 of the sixth transistor (which is also the first electrode 73 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor through the twelfth via, to the first region of the active pattern of the seventh transistor through the thirteenth via, to the second connecting line through the sixty-second via, and to the second plate of the first capacitor through the sixty-third via.

[0478] In an exemplary embodiment, the second electrode 74 of the seventh transistor and the second electrode 84 of the eighth transistor are an integral structure. The integral structure of the second electrode 74 of the seventh transistor and the second electrode 84 of the eighth transistor has a zigzag shape and extends at least partially along the second direction D2. The second electrode 74 of the seventh transistor (which is also the first electrode 84 of the eighth transistor) is connected to the second region of the active pattern of the seventh transistor through the fourteenth via, to the second region of the active pattern of the eighth transistor through the sixteenth transistor, to the control electrode of the ninth transistor through the forty-seventh via, and to the first plate of the second capacitor through the forty-eighth via.

[0479] In an exemplary embodiment, the first electrode 83 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 133 of the thirteenth transistor are integrally formed. The first electrode 83 of the eighth transistor (which is also the first electrode 93 of the ninth transistor and the first electrode 133 of the thirteenth transistor) is connected to the first region of the active pattern of the eighth transistor (which is also the first region of the active pattern of the thirteenth transistor) through the fifteenth via, and is connected to the first region of the active pattern of the ninth transistor through the seventeenth via.

[0480] In an exemplary embodiment, the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor are an integral structure. The integral structure of the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor is shaped like an "E". The second electrode 94 of the ninth transistor (which is also the second electrode 104 of the tenth transistor) is connected to the second region of the active pattern of the ninth transistor (which is also the second region of the active pattern of the tenth transistor) through an eighteenth via.

[0481] In an exemplary embodiment, the first electrode 103 of the tenth transistor can be provided separately. The first electrode 103 of the tenth transistor is strip-shaped and extends along the first direction D1. The first electrode 103 of the tenth transistor is connected to the first region of the active pattern of the tenth transistor through the nineteenth via.

[0482] In an exemplary embodiment, the second electrode 114 of the eleventh transistor can be provided separately. The second electrode 114 of the eleventh transistor is shaped like a broken line and extends at least partially along the second direction D2. The second electrode 114 of the eleventh transistor is connected to the second region of the active pattern of the eleventh transistor through the twentieth via, and is connected to the control electrode of the sixth transistor (which is also the first plate of the first capacitor) through the forty-fifth via.

[0483] In an exemplary embodiment, the first electrode 123 of the twelfth transistor, the second electrode 134 of the thirteenth transistor, and the first electrode 183 of the eighteenth transistor are integrally formed. The integral structure of the first electrode 123 of the twelfth transistor, the second electrode 134 of the thirteenth transistor, and the first electrode 183 of the eighteenth transistor has a zigzag shape and extends at least partially along the second direction D2. The first electrode 123 of the twelfth transistor (which is also the second electrode 134 of the thirteenth transistor and the first electrode 183 of the eighteenth transistor) is connected to the first region of the active pattern of the twelfth transistor (which is also the second region of the active pattern of the thirteenth transistor) through a twenty-first via, to the first region of the active pattern of the eighteenth transistor through a twenty-ninth via, and to the control electrode of the second transistor (which is also the control electrode of the eighth transistor) through a forty-second via.

[0484] In an exemplary embodiment, the second electrode 124 of the twelfth transistor and the first electrode 164 of the sixteenth transistor are integrally formed. The integral structure of the second electrode 124 of the twelfth transistor and the first electrode 164 of the sixteenth transistor is shaped like a "┌". The second electrode 124 of the twelfth transistor (which is also the second electrode 164 of the sixteenth transistor) is connected to the second region of the active pattern of the twelfth transistor (which is also the second region of the active pattern of the sixteenth transistor) through the twenty-second via, and is connected to the control electrode of the tenth transistor through the forty-ninth via.

[0485] In an exemplary embodiment, the second electrode 144 of the fourteenth transistor and the first electrode 153 of the fifteenth transistor are an integral structure. The integral structure of the second electrode 144 of the fourteenth transistor and the first electrode 153 of the fifteenth transistor is a strip extending along the second direction D2. The second electrode 144 of the fourteenth transistor (which is also the first electrode 153 of the fifteenth transistor) is connected to the second region of the active pattern of the fourteenth transistor through a twenty-fourth via, and is connected to the first region of the active pattern of the fifteenth transistor through a twenty-fifth via.

[0486] In an exemplary embodiment, the second electrode 154 of the fifteenth transistor can be provided separately. The second electrode 154 of the fifteenth transistor is strip-shaped and extends along the second direction D2. The second electrode 154 of the fifteenth transistor is connected to the second region of the active pattern of the fifteenth transistor through the twenty-sixth via, and is connected to the control electrode of the fourth transistor (which is also the control electrode of the sixteenth transistor, the control electrode of the seventeenth transistor, and the first plate of the third capacitor) through the forty-third via.

[0487] In an exemplary embodiment, the first electrode 163 of the sixteenth transistor and the first electrode 173 of the seventeenth transistor are an integral structure. The integral structure of the first electrode 163 of the sixteenth transistor and the first electrode 173 of the seventeenth transistor is shaped like a "┐". The first electrode 163 of the sixteenth transistor (which is also the first electrode 173 of the seventeenth transistor) is connected to the first region of the active pattern of the sixteenth transistor (which is also the first region of the active pattern of the seventeenth transistor) through the twenty-seventh via, and is connected to the control electrode of the fourth transistor (which is also the control electrode of the sixteenth transistor, the control electrode of the seventeenth transistor, and the first plate of the third capacitor) through the forty-third via.

[0488] In an exemplary embodiment, the second electrode 174 of the seventeenth transistor and the second electrode 184 of the eighteenth transistor are an integral structure. The integral structure of the second electrode 174 of the seventeenth transistor and the second electrode 184 of the eighteenth transistor is strip-shaped, extending along the first direction D1. The second electrode 174 of the seventeenth transistor (which is also the second electrode 184 of the eighteenth transistor) is connected to the second region of the active pattern of the seventeenth transistor through the twenty-eighth via, connected to the second region of the active pattern of the eighteenth transistor through the thirtieth via, and connected to the first connection line through the sixty-first via.

[0489] In an exemplary embodiment, the first electrode 193 of the nineteenth transistor can be provided separately. The first electrode 193 of the nineteenth transistor is strip-shaped and extends along the first direction D1. The first electrode 193 of the nineteenth transistor is connected to the first region of the active pattern of the nineteenth transistor through the thirty-first via and to the second electrode plate of the seventh capacitor through the sixty-sixth via.

[0490] In an exemplary embodiment, the second electrode 194 of the nineteenth transistor and the second electrode 204 of the twentieth transistor are integrally formed. The integral structure of the second electrode 194 of the nineteenth transistor and the second electrode 204 of the twentieth transistor can be comb-shaped, with multiple comb teeth located on the side of the comb back away from the display area. The comb back extends along a second direction D2, and at least one comb tooth extends along a first direction D1. The second electrode 194 of the nineteenth transistor (also the second electrode 204 of the twentieth transistor) is connected to the second region of the active pattern of the nineteenth transistor (also the second region of the active pattern of the twentieth transistor) through a thirty-second via, to the gate electrode of the twenty-sixth transistor through a fifty-ninth via, and to the second plate of the sixth capacitor through a sixty-eighth via.

[0491] In an exemplary embodiment, the first electrode 203 of the twentieth transistor can be provided separately. The first electrode 203 of the twentieth transistor is strip-shaped and extends along the first direction D1. The first electrode 203 of the twentieth transistor is connected to the first region of the active pattern of the twentieth transistor through a thirty-third via.

[0492] In an exemplary embodiment, the first electrode 213 of the twenty-first transistor can be provided separately. The first electrode 213 of the twenty-first transistor can be shaped like a "┘". The first electrode 213 of the twenty-first transistor is connected to the first region of the active pattern of the twenty-first transistor through the thirty-fourth via, and is connected to the gate electrode of the ninth transistor through the forty-seventh via.

[0493] In an exemplary embodiment, the second electrode 214 of the twenty-first transistor and the first electrode 263 of the twenty-sixth transistor are integrally formed. The integral structure of the second electrode 214 of the twenty-first transistor and the first electrode 263 of the twenty-sixth transistor may be in the shape of a broken line and extends at least partially along the second direction D2. The second electrode 214 of the twenty-first transistor (which is also the first electrode 263 of the twenty-sixth transistor) is connected to the second region of the active pattern of the twenty-first transistor (the first region of the active pattern of the twenty-sixth transistor) through the thirty-fifth via, to the control electrode of the nineteenth transistor through the fifty-fourth via, and to the second plate of the fifth capacitor through the sixty-seventh via.

[0494] In an exemplary embodiment, the first electrode 223 of the twenty-second transistor can be provided separately. The first electrode 223 of the twenty-second transistor is strip-shaped and extends along the second direction D2. The first electrode 223 of the twenty-second transistor is connected to the first region of the active pattern of the twenty-second transistor through a thirty-seventh via, and connected to the gate electrode of the eighteenth transistor (the gate electrode of the twenty-first transistor and the first plate of the fifth capacitor) through a fifty-third via. In this disclosure, the first electrode 223 of the twenty-second transistor is directly connected to the gate electrode of the eighteenth transistor (the gate electrode of the twenty-first transistor and the first plate of the fifth capacitor) through vias, which can reduce the adverse effects of jumps.

[0495] In an exemplary embodiment, the first electrode 233 of the twenty-third transistor can be provided separately. The first electrode 233 of the twenty-third transistor is strip-shaped and extends along the first direction D1. The first electrode 233 of the twenty-third transistor is connected to the first region of the active pattern of the twenty-third transistor through the thirty-sixth via.

[0496] In an exemplary embodiment, the first electrode 243 of the twenty-fourth transistor can be provided separately. The first electrode 243 of the twenty-fourth transistor is strip-shaped and extends along the first direction D1. The first electrode 243 of the twenty-fourth transistor is connected to the first region of the active pattern of the twenty-fourth transistor through the thirty-eighth via.

[0497] In an exemplary embodiment, the first electrode 253 of the twenty-fifth transistor can be provided separately. The first electrode 253 of the twenty-fifth transistor is strip-shaped and extends along the first direction D1. The first electrode 253 of the twenty-fifth transistor is connected to the first region of the active pattern of the twenty-fifth transistor through the thirty-ninth via, and is connected to the gate electrode of the eighteenth transistor (the gate electrode of the twenty-first transistor and the first plate of the fifth capacitor) through the fifty-third via.

[0498] In an exemplary embodiment, the second electrode 254 of the twenty-fifth transistor can be provided separately. The second electrode 254 of the twenty-fifth transistor is strip-shaped and extends along the first direction D1. The second electrode 254 of the twenty-fifth transistor is connected to the second region of the active pattern of the twenty-fifth transistor through the fortieth via.

[0499] In an exemplary embodiment, the first connection electrode E1 is strip-shaped and extends at least partially along the second direction D2. The first connection electrode E1 is connected to the gate electrode of the thirteenth transistor through a fifty-second via.

[0500] In an exemplary embodiment, the second connection electrode E2 is strip-shaped and extends at least partially along the first direction D1. The second connection electrode L2 is connected to the control electrode of the twentieth transistor (which is also the control electrode of the twentieth transistor and the first electrode plate of the sixth transistor) through the fifty-fifth via, and is connected to the first connection line through the sixty-first via.

[0501] In an exemplary embodiment, the third connection electrode E3 is shaped like a "┌". The third connection electrode L3 is connected to the control electrode of the twenty-third transistor through the fifty-seventh via.

[0502] In an exemplary embodiment, the fourth connecting electrode E4 is strip-shaped and extends at least partially along the first direction D1. The fourth connecting electrode L4 is connected to the second connecting line through a sixty-second via.

[0503] In an exemplary embodiment, the fifth connecting electrode E5 is strip-shaped and extends at least partially along the first direction D1. The fifth connecting electrode E5 is connected to the second plate of the second capacitor through a sixty-fourth via.

[0504] In an exemplary embodiment, the sixth connecting electrode E6 is strip-shaped and extends at least partially along the first direction D1. The sixth connecting electrode E6 is connected to the second plate of the fourth capacitor through a sixty-ninth via.

[0505] In an exemplary embodiment, the k-th first cross-stage connection line is electrically connected to the second terminals of the ninth and tenth virtual transistors of the k-th stage virtual shift register, and the first terminals of the first and fourteenth virtual transistors of the (k+1)-th stage virtual shift register. The K-th first cross-stage connection line is electrically connected to the second terminals of the ninth and tenth virtual transistors of the k-th stage virtual shift register, and the first terminals of the first transistor, fourteenth transistor, and twenty-second transistor of the first stage shift register. The r-th first cross-stage connection line is electrically connected to the second terminals of the ninth and tenth transistors of the rK-th stage shift register, and the first terminals of the first transistor, fourteenth transistor, and twenty-second transistor of the (r-K+1)-th stage shift register, where K+1≤r≤N+K-1.

[0506] In an exemplary embodiment, the Kth first cross-stage connection line is connected to the control electrode of the 22nd transistor of the first-stage shift register through the 56th via of the first-stage shift register, and is electrically connected to the first plate of the fourth capacitor of the first-stage shift register through the 60th via of the first-stage shift register.

[0507] The first cross-stage connection line of the rth stage is electrically connected to the second terminals of the ninth and tenth transistors of the rKth stage shift register through the fifty-sixth via of the rKth stage shift register, and is electrically connected to the first terminal of the first transistor, the first terminal of the fourteenth transistor, and the control terminal of the twenty-second transistor of the r-K+1th stage shift register through the sixtieth via of the rKth stage shift register, where K+1≤r≤N+K-1.

[0508] In an exemplary embodiment, the kth third cross-stage connection line is electrically connected to the second terminal of the fourth virtual transistor in the kth stage virtual shift register and the control terminal of the twenty-fifth virtual transistor in the (k+1)th stage virtual shift register, respectively; the Kth third cross-stage connection line is electrically connected to the second terminal of the fourth virtual transistor in the kth stage virtual shift register and the control terminal of the twenty-fifth transistor in the first stage shift register, respectively; the rth third cross-stage connection line is electrically connected to the second terminal of the fourth transistor in the rKth stage shift register and the control terminal of the twenty-fifth transistor in the (r-K+1)th stage shift register, respectively, where K+1≤r≤N+K-1.

[0509] In an exemplary embodiment, the kth third cross-stage connection line is electrically connected to the control electrode of the 25th transistor of the kth stage virtual shift register through the 58th via of the kth stage virtual shift register, the kth third cross-stage connection line is electrically connected to the control electrode of the 25th transistor of the first stage shift register through the 58th via of the first stage shift register, and the rth third cross-stage connection line is electrically connected to the control electrode of the 25th transistor of the (r-K+1)th stage shift register through the 58th via of the (r-K+1)th stage shift register.

[0510] In an exemplary embodiment, in at least one level shift register, the second electrode 64 of the sixth transistor (which is also the first electrode 73 of the seventh transistor) is electrically connected to the fourth connection electrode E4 via a second connection line.

[0511] In an exemplary embodiment, in at least one level shift register, the second electrode 174 of the seventeenth transistor (which is also the second electrode 184 of the eighteenth transistor) is connected in sequence to the control electrode of the twentieth transistor (which is also the control electrode of the twenty-fourth transistor and the first plate of the sixth capacitor) via a first connection line and a second connection electrode.

[0512] (6) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer pattern covering the aforementioned structure. The fourth insulating layer has a plurality of via patterns, as shown in FIG29. FIG29 is a schematic diagram of the first display substrate and the second display substrate after the fourth insulating layer pattern has been formed.

[0513] In an exemplary embodiment, as shown in FIG29, the fourth insulating layer pattern may include at least: the seventieth via V70 to the eighty-third via V83 located in at least one level shift register.

[0514] In an exemplary embodiment, the orthographic projection of the 70th via V70 on the substrate is within the range of the orthographic projection of the first electrode of the third transistor on the substrate. The 70th via V70 exposes the surface of the first electrode of the third transistor. The 70th via V70 is configured to allow a subsequently formed first second power line to be connected to the first electrode of the third transistor through the via.

[0515] In an exemplary embodiment, the orthographic projection of the seventy-first via V71 onto the substrate is within the range of the orthographic projection of the first electrode of the twenty-fifth transistor onto the substrate. The seventy-first via V71 exposes the surface of the first electrode of the twenty-fifth transistor. The seventy-first via V71 is configured to allow a subsequently formed first second power line to be connected to the first electrode of the twenty-fifth transistor through the via.

[0516] In an exemplary embodiment, the orthographic projection of the seventy-second via V72 on the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate. The seventy-second via V72 exposes the surface of the first electrode of the fifth transistor. The seventy-second via V72 is configured to allow a subsequently formed first power line to be connected to the first electrode of the fifth transistor through the via.

[0517] In an exemplary embodiment, the orthographic projection of the 73rd via V73 onto the substrate lies within the range of the orthographic projection of the first connection electrode onto the substrate. The 73rd via V73 exposes the surface of the first connection electrode and is configured to allow a subsequently formed third power line to be connected to the first connection electrode through this via. The third power line is electrically connected to the control electrode of the 13th transistor through the first connection electrode.

[0518] In an exemplary embodiment, the orthographic projection of the seventy-fourth via V74 onto the substrate lies within the range of the orthographic projection of the first pole of the eighth transistor (which is also the first pole of the ninth transistor and the first pole of the thirteenth transistor) onto the substrate. The seventy-fourth via V74 exposes the surface of the first pole of the eighth transistor (which is also the first pole of the ninth transistor and the first pole of the thirteenth transistor). The seventy-fourth via V74 is configured to allow a subsequently formed second first power line to be connected to the first pole of the eighth transistor (which is also the first pole of the ninth transistor and the first pole of the thirteenth transistor) through the via.

[0519] In an exemplary embodiment, the orthographic projection of the 75th via V75 onto the substrate lies within the range of the orthographic projection of the fifth connecting electrode onto the substrate. The 75th via V75 exposes the surface of the fifth connecting electrode and is configured to allow a subsequently formed second first power line to be connected to the fifth connecting electrode through this via. The second first power line is electrically connected to the second plate of the second capacitor through the fifth connecting electrode.

[0520] In an exemplary embodiment, the orthographic projection of the seventy-sixth via V76 on the substrate is within the range of the orthographic projection of the first electrode of the tenth transistor on the substrate. The seventy-sixth via V76 exposes the surface of the first electrode of the tenth transistor. The seventy-sixth via V76 is configured to allow a subsequently formed second power line to be connected to the first electrode of the tenth transistor through the via.

[0521] In an exemplary embodiment, the orthographic projection of the seventy-seventh via V77 on the substrate is within the range of the orthographic projection of the fourth connecting electrode on the substrate. The seventy-seventh via V77 exposes the surface of the fourth connecting electrode. The seventy-seventh via V77 is configured to allow the subsequently formed nth second cross-level connecting line to be connected to the fourth connecting electrode through the via.

[0522] In an exemplary embodiment, the orthographic projection of the seventy-eighth via V78 on the substrate is within the range of the orthographic projection of the third connecting electrode on the substrate. The seventy-eighth via V78 exposes the surface of the third connecting electrode. The seventy-eighth via V78 is configured to allow the subsequently formed (n-2)th second cross-stage connecting line to be connected to the third connecting electrode through the via.

[0523] In an exemplary embodiment, the orthographic projection of the seventy-ninth via V79 on the substrate is within the range of the orthographic projection of the first electrode of the twenty-third transistor on the substrate. The seventy-ninth via V79 exposes the surface of the first electrode of the twenty-third transistor. The seventy-ninth via V79 is configured to allow a subsequently formed masking signal line to be connected to the first electrode of the twenty-third transistor through the via.

[0524] In an exemplary embodiment, the orthographic projection of the 80th via V80 onto the substrate is within the range of the orthographic projection of the first electrode of the 19th transistor onto the substrate. The 80th via V80 exposes the surface of the first electrode of the 19th transistor. The 80th via V80 is configured to allow the subsequently formed third, fourth, and fifth first power lines to be connected to the first electrode of the 19th transistor through the via.

[0525] In an exemplary embodiment, the orthogonal projection of the eighty-first via V81 onto the substrate is within the range of the orthogonal projection of the first electrode of the twenty-fourth transistor onto the substrate. The eighty-first via V81 exposes the surface of the first electrode of the twenty-fourth transistor. The eighty-first via V81 is configured to allow a subsequently formed third first power line to be connected to the first electrode of the twenty-fourth transistor through the via.

[0526] In an exemplary embodiment, the orthogonal projection of the 82nd via V82 on the substrate is within the range of the orthogonal projection of the first electrode of the 20th transistor on the substrate. The 82nd via V82 exposes the surface of the first electrode of the 20th transistor. The 82nd via V82 is configured to allow a subsequently formed third second power line to be connected to the first electrode of the 20th transistor through the via.

[0527] In an exemplary embodiment, the orthographic projection of the 83rd via V83 onto the substrate lies within the range of the orthographic projection of the sixth connecting electrode onto the substrate. The 83rd via V83 exposes the surface of the sixth connecting electrode and is configured to allow a subsequently formed third second power line to connect to the sixth connecting electrode through this via. The third second power line is connected to the second plate of the fourth capacitor through the sixth connecting electrode.

[0528] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer disposed on a fourth insulating layer, as shown in Figures 30 to 33. Figure 30 is a schematic diagram of the fourth insulating layer pattern of the first display substrate, Figure 31 is a schematic diagram of the first display substrate after the fourth insulating layer pattern is formed, Figure 32 is a schematic diagram of the fourth insulating layer pattern of the second display substrate, and Figure 33 is a schematic diagram of the second display substrate after the fourth insulating layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0529] In an exemplary embodiment, as shown in Figures 30 to 33, the fourth conductive layer pattern may include at least: a first initial signal line STV1, a second initial signal line STV2, a masking signal line MSL, a first clock signal line CLK1, a second clock signal line CLK2, a first first power line VGH-1, a second first power line VGH-2, a third first power line VGH-3, a fourth first power line VGH-4, a fifth first power line VGH-5, a first second power line VGL-1, a second second power line VGL-2, a third second power line VGL-3, and a third power line NCXL.

[0530] In an exemplary embodiment, at least one of the following signal lines extends at least partially along the second direction D2: first initial signal line STV1, second initial signal line STV2, masking signal line MSL, first clock signal line CLK1, second clock signal line CLK2, first first power line VGH-1, second first power line VGH-2, third first power line VGH-3, fourth first power line VGH-4, fifth first power line VGH-5, first second power line VGL-1, second second power line VGL-2, third second power line VGL-3, and third power line NCXL.

[0531] In an exemplary embodiment, the first initial signal line STV1, the first second power line VGL-1, the first clock signal line CLK1, the second clock signal line CLK2, the first first power line VGH-1, the third power line NCXL, the second initial signal line STV2, the second second power line VGL-2, the second first power line VGH-2, the masking signal line MSL, the third first power line VGH-3, the fourth first power line VGH-4, the fifth first power line VGH-5, and the third second power line VGL-3 are arranged sequentially along the direction closer to the display area.

[0532] In an exemplary embodiment, the orthographic projection of at least one third cross-level connection line on the substrate is located on the side of the orthographic projection of the first initial signal line on the substrate that is away from the display area.

[0533] In an exemplary embodiment, the first second power line VGL-1 is connected to the first terminal of the third transistor through the seventieth via and to the first terminal of the twenty-fifth transistor through the seventy-first via.

[0534] In an exemplary embodiment, the second power line VGL-2 is connected to the first terminal of the tenth transistor via the seventy-sixth via.

[0535] In an exemplary embodiment, the third second power line VGL-3 is connected to the first electrode of the twentieth transistor via the eighty-second via, and also connected to the sixth connection electrode via the eighty-third via. The third second power line VGL-3 is connected to the second plate of the fourth capacitor via the sixth connection electrode.

[0536] In an exemplary embodiment, the first power line VGH-1 is connected to the first terminal of the fifth transistor through the seventy-second via.

[0537] In an exemplary embodiment, the second first power line VGH-2 is connected to the first electrode of the eighth transistor (which is also the first electrode of the ninth and thirteenth transistors) through the seventy-fourth via, and to the fifth connection electrode through the seventy-fifth via. The second first power line VGH-2 is electrically connected to the second plate of the second capacitor through the fifth connection electrode.

[0538] In an exemplary embodiment, the third first power line VGH-3, the fourth first power line VGH-4, and the fifth first power line VGH-5 are connected to the first terminal of the nineteenth transistor through the eightieth via, and the third first power line VGH-3 is also connected to the first terminal of the twenty-fourth transistor through the eighty-first via.

[0539] In an exemplary embodiment, the masking signal line MSL is connected to the first terminal of the twenty-third transistor via the seventy-ninth via.

[0540] In an exemplary embodiment, the third power line NCXL is connected to the first connection electrode via the seventy-third via. The third power line is electrically connected to the control electrode of the thirteenth transistor via the first connection electrode.

[0541] In an exemplary embodiment, as shown in Figures 30 and 31, the fourth conductive layer pattern in the first display substrate further includes at least a plurality of second cross-level interconnect lines NL2.

[0542] In an exemplary embodiment, at least one second cross-level connection line NL2 extends at least partially along the second direction D2.

[0543] In an exemplary embodiment, at least one of the second-level connecting lines is in the shape of a broken line and includes multiple bends.

[0544] In an exemplary embodiment, the first end of the s-th second cross-level connection line is electrically connected to the fourth connection electrode of the s-th virtual shift register through the seventy-seventh via of the s-th virtual shift register, and the second end of the s-th second cross-level connection line is electrically connected to the third connection electrode of the s-th shift register through the seventy-eighth via of the s-th shift register.

[0545] In an exemplary embodiment, the first end of the t-th second cross-stage connection line is electrically connected to the fourth connection electrode of the tK-th stage shift register through the seventy-seventh via of the tK-th stage shift register, and the second end of the t-th second cross-stage connection line is electrically connected to the third connection electrode of the t-th stage shift register through the seventy-eighth via of the t-th stage shift register.

[0546] In an exemplary embodiment, the line connecting the second end of the m-th second span-level connecting line and the first end of the (m+K)-th second span-level connecting line intersects at least one bend in the (m+1)-m to (m+K-1)-th second span-level connecting lines, where 1≤m≤N.

[0547] In an exemplary embodiment, the orthographic projection of at least one second cross-level connection line NL2 on the substrate lies between the orthographic projection of the second first power line VGH-2 on the substrate and the orthographic projection of the masking signal line MSL on the substrate.

[0548] In an exemplary embodiment, as shown in Figures 32 and 33, the fourth conductive layer pattern on the second display substrate further includes at least: a first connection portion NL2A of a plurality of second cross-level connection lines NL2 and a seventh connection electrode E7 located in at least one shift register.

[0549] In an exemplary embodiment, at least one first connection portion NL2A of a second cross-level connection line NL2 extends at least partially along the second direction D2.

[0550] In an exemplary embodiment, the first connection portion of the s-th second cross-level connection line is connected to the fourth connection electrode of the s-th level virtual shift register through the seventy-seventh via of the s-th level virtual shift register.

[0551] In an exemplary embodiment, the first connection portion of the tth second cross-level connection line is connected to the fourth connection electrode of the tKth level shift register through the seventy-seventh via of the tKth level shift register.

[0552] In an exemplary embodiment, the seventh connecting electrode E7 is strip-shaped and extends along the second direction D2.

[0553] In an exemplary embodiment, the seventh connection electrode E7 of the nth stage shift register is electrically connected to the third connection electrode of the nth stage shift register through the seventy-eighth via.

[0554] In an exemplary embodiment, the orthographic projection of the first connection portion NL2A of at least one second cross-level connection line NL2 onto the substrate is located on the side of the orthographic projection of the fifth capacitor of at least one level shift register onto the substrate away from the display area.

[0555] In an exemplary embodiment, the arrangement of the first connecting line, the second connecting line, and the first connecting electrode to the seventh connecting electrode can reduce the via depth in the display substrate and improve the reliability of the display substrate.

[0556] In an exemplary embodiment, the width of at least one of the fourth first power line VGH-4 and the fifth first power line VGH-5 is greater than the width of at least one of the first first power line VGH-1, the second first power line VGH-2, the third first power line VGH-3, the first second power line VGL-1, the second second power line VGL-2, and the third power line NCXL.

[0557] In an exemplary embodiment, the width of the third second power line VGL-3 is greater than the width of at least one of the first first power line VGH-1, the second first power line VGH-2, the third first power line VGH-3, the first second power line VGL-1, the second second power line VGL-2, and the third power line NCXL.

[0558] In an exemplary embodiment, the first initial signal line STV1, the second initial signal line STV2, the masking signal line MSL, the first clock signal line CLK1, the second clock signal line CLK2, the first first power line VGH-1, the second first power line VGH-2, the third first power line VGH-3, the fourth first power line VGH-4, the fifth first power line VGH-5, the first second power line VGL-1, the second second power line VGL-2, the third second power line VGL-3, and the third power line NCXL can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the shift register but also reduces the parasitic capacitance between signal lines. This disclosure does not limit the scope of the invention.

[0559] (8) Forming a first planarization layer. In an exemplary embodiment, forming a first planarization layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, coating a first planarization film, and patterning the fifth insulating film and the first planarization film using a patterning process to form a fifth insulating layer pattern covering the aforementioned structure and a first planarization layer pattern covering the fifth insulating layer pattern. The fifth insulating layer and the first planarization layer have multiple via patterns. As shown in FIG34, FIG34 is a schematic diagram of the second display substrate after the first planarization layer pattern is formed.

[0560] In an exemplary embodiment, the first flattening layer pattern may include at least: an eighty-fourth via V84 and an eighty-fifth via V85 of at least one shift register.

[0561] In an exemplary embodiment, the orthographic projection of the 84th via V84 on the substrate is within the range of the orthographic projection of the 7th connection electrode on the substrate. The fifth insulating layer within the 84th via V84 is etched to expose the surface of the 7th connection electrode. The 84th via V84 in the nth stage shift register is configured to allow the second connection portion of at least one subsequently formed second cross-stage connection line to be connected to the 7th connection electrode through the via.

[0562] In an exemplary embodiment, the orthographic projection of the 85th via V85 onto the substrate lies within the orthographic projection of the first connection portion of at least one second cross-level connection line onto the substrate. The fifth insulating layer within the 85th via V85 is etched to expose the surface of the first connection portion of at least one second cross-level connection line. The 85th via V85 is configured to allow the second connection portions of at least one subsequently formed second cross-level connection line to be connected through the first connection portion of at least one second cross-level connection line.

[0563] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer pattern disposed on a fifth insulating layer, as shown in Figures 35 and 36. Figure 35 is a schematic diagram of the fifth conductive layer pattern of the second display substrate, and Figure 36 is a schematic diagram of the second display substrate after the fifth conductive layer pattern is formed. In an exemplary embodiment, the fifth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0564] In an exemplary embodiment, as shown in Figures 35 and 36, the fifth conductive layer pattern may include at least: a second connection portion NL2B of the second cross-level connection line NL2.

[0565] In an exemplary embodiment, the second connecting portion NL2B of the second cross-level connecting line NL2 extends at least partially along the second direction D2, and the shape of the second connecting portion NL2B of the second cross-level connecting line NL2 is a zigzag shape, including a bend.

[0566] In an exemplary embodiment, the second connection portion of the s-th second cross-level connection line is connected to the seventh connection electrode of the s-th level shift register through the eighty-fourth via of the s-th level shift register, and is connected to the first connection portion of the s-th second cross-level connection line th...

Claims

A display substrate having a display area and a non-display area, the display substrate comprising: The substrate and a gate driving circuit disposed on the substrate and located in the non-display area, the gate driving circuit including: a plurality of cascaded shift registers, at least one shift register including: a shift sub-circuit and an output sub-circuit; The shift sub-circuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the third power supply terminal, the cascaded signal output terminal, and the output sub-circuit, respectively. It is configured to provide a signal from the first power supply terminal or the second power supply terminal to the cascaded signal output terminal under the control of the signals from the signal input terminal, the first clock signal terminal, the second clock signal terminal, and the third power supply terminal, and to provide a signal from at least one of the signal input terminal, the second clock signal terminal, and the first power supply terminal to the output sub-circuit. The output sub-circuit is also electrically connected to the first control signal terminal, the second control signal terminal, the third control signal terminal, the masking signal terminal, the first power supply terminal, the second power supply terminal, and the drive signal output terminal, respectively, and is configured to provide the first power supply terminal or the second power supply terminal signal to the drive signal output terminal under the control of the signal provided by the shift sub-circuit and the signals of the first control signal terminal, the second control signal terminal, the third control signal terminal, and the masking signal terminal; The display substrate further includes: multiple first cross-level connection lines located in the non-display area; At least one first cross-stage connection line is electrically connected to the first control signal terminal and signal input terminal of the first stage shift register and the cascaded signal output terminal of the previous stage shift register, respectively. At least a portion of the orthographic projection of at least one first cross-stage connection line onto the substrate lies at least partially between the orthographic projections of the two shift registers connected by the first cross-stage connection line onto the substrate. The display substrate according to claim 1 further includes: Multiple second-level connection lines located in the non-display area; a third node is provided in the shift sub-circuit; The second cross-stage connection line is electrically connected to the second control signal terminal of the first-stage shift register and the third node in the shift sub-circuit of the first K-stage shift register, where K ≥ 2; At least a portion of the orthographic projection of at least one second-stage crossover line onto the substrate overlaps at least a portion of the orthographic projection of at least one level shift register onto the substrate. The display substrate according to claim 1 further includes: Multiple third-level cross-connection lines located in the non-display area; a fifth node is provided in the shift sub-circuit; The third cross-stage connection line is electrically connected to the third control signal terminal of the first-stage shift register and the fifth node in the previous-stage shift register, respectively. At least a portion of at least one third-level cross-connect line has its orthographic projection on the substrate located on the side of the orthographic projection of at least one level shift register on the substrate away from the display area. The display substrate according to claim 1, wherein, The gate drive circuit further includes: K virtual shift registers, each virtual shift register including: a virtual shift sub-circuit and a virtual output sub-circuit, each virtual shift register including: at least one virtual transistor and at least one virtual capacitor, each virtual transistor including: a first electrode and a second electrode, and each virtual capacitor including: a first plate and a second plate; The shift sub-circuit of at least one shift register has the same circuit structure as the at least one virtual shift sub-circuit, and the output sub-circuit of at least one shift register has the same circuit structure as the at least one virtual shift sub-circuit. At least one electrode of the first and second terminals of at least one virtual transistor is electrically connected to a first power supply terminal or a second power supply terminal, and at least one plate of the first and second terminals of at least one virtual capacitor is electrically connected to the first power supply terminal or the second power supply terminal. The display substrate according to claim 4, wherein, The cascaded signal output of the k-th stage virtual shift register is electrically connected to the signal input of the (k+1)-th stage virtual shift register, and the cascaded signal output of the K-th stage shift register is electrically connected to the signal input of the first stage shift register, where 1≤k≤K-1 and K≥2. The display substrate according to claim 1, wherein, The gate drive circuit further includes: K virtual shift registers, each virtual shift register including: a virtual shift sub-circuit and a virtual output sub-circuit; The number of the first cross-stage connection lines is N+K-1, where N is the number of shift registers included in the gate drive circuit, and at least one first cross-stage connection line extends at least partially along the second direction; For at least one level shift register, the shift sub-circuit includes: a first transistor, a ninth transistor, a tenth transistor, and a fourteenth transistor; the output sub-circuit includes: a twenty-second transistor; the second terminals of the ninth and tenth transistors are electrically connected to the cascaded signal output terminal, the first terminals of the first and fourteenth transistors are electrically connected to the signal input terminal, and the control terminal of the twenty-second transistor is electrically connected to the first control signal terminal. For at least one level virtual shift register, the virtual shift sub-circuit includes: a first virtual transistor, a ninth virtual transistor, a tenth virtual transistor, and a fourteenth virtual transistor; the virtual output sub-circuit includes: a twenty-second virtual transistor; the second terminals of the ninth and tenth virtual transistors are electrically connected to the cascaded signal output terminal, the first terminals of the first and fourteenth virtual transistors are electrically connected to the signal input terminal, and the control terminal of the twenty-second virtual transistor is connected to either the first or second power supply terminal. The kth first cross-stage connection line is electrically connected to the second pole of the ninth virtual transistor and the second pole of the tenth virtual transistor in the kth stage virtual shift register, as well as the first pole of the first virtual transistor and the first pole of the fourteenth virtual transistor in the (k+1)th stage virtual shift register. The first cross-stage connection line of the Kth stage is electrically connected to the second pole of the ninth virtual transistor and the second pole of the tenth virtual transistor located in the Kth stage virtual shift register, as well as the first pole of the first transistor, the first pole of the fourteenth transistor, and the control pole of the twenty-second transistor in the first stage shift register. The r-th first cross-stage connection line is electrically connected to the second pole of the ninth transistor and the second pole of the tenth transistor of the rK-th stage shift register, as well as the first pole of the first transistor, the first pole of the fourteenth transistor, and the control pole of the twenty-second transistor of the r-K+1-th stage shift register, where K+1≤r≤N+K-1. The display substrate according to claim 6 further includes: The driving structure layer is disposed on the substrate, the gate driving circuit is disposed on the driving structure layer, at least one level shift register includes at least one transistor and at least one capacitor, at least one level virtual shift register includes at least one virtual transistor and at least one virtual capacitor, at least one transistor or virtual transistor includes an active pattern, a control electrode, a first electrode and a second electrode, at least one capacitor or virtual capacitor includes a first electrode plate and a second electrode plate; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; The semiconductor layer includes at least: an active pattern of at least one transistor located in at least one level shift register and an active pattern of at least one virtual transistor located in at least one level virtual shift register; The first conductive layer includes at least: a first plate of a control electrode of at least one transistor and at least one capacitor located in at least one level shift register, and a first plate of a control electrode of at least one virtual transistor and at least one virtual capacitor located in at least one level virtual shift register; The second conductive layer includes at least: a second plate of at least one capacitor located in at least one level shift register and a second plate of at least one virtual capacitor located in at least one level virtual shift register; The third conductive layer includes at least: a first electrode and a second electrode of at least one transistor located in at least one level of the shift register, and at least one first crossbar. Level connection cable. The display substrate according to claim 2, wherein, The gate drive circuit further includes: K virtual shift registers, each virtual shift register including: a virtual shift sub-circuit and a virtual output sub-circuit; The number of the second cross-stage connection lines is N, where N is the number of shift registers included in the gate drive circuit; For at least one level shift register, the shift sub-circuit further includes: a sixth transistor and a seventh transistor; the output sub-circuit further includes: a twenty-third transistor; the second terminal of the sixth transistor and the first terminal of the seventh transistor are electrically connected to the third node, respectively; the control terminal of the twenty-third transistor is electrically connected to the second control signal terminal. For at least one level virtual shift register, the virtual shift sub-circuit further includes: a sixth virtual transistor and a seventh virtual transistor; the virtual output sub-circuit further includes: a twenty-third virtual transistor; the second terminal of the sixth virtual transistor and the first terminal of the seventh virtual transistor are electrically connected to the third node, respectively; the control terminal of the twenty-third virtual transistor is electrically connected to the second control signal terminal. The s-th second cross-stage connection line is electrically connected to the second pole of the sixth virtual transistor and the first pole of the seventh virtual transistor of the s-th stage virtual shift register, as well as the control pole of the twenty-third transistor of the s-th stage shift register, 1≤s≤K; The t-th second cross-stage connection line is electrically connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor of the tK-th stage shift register, as well as the control terminal of the twenty-third transistor of the t-th stage shift register, where K+1≤t≤N. The display substrate according to claim 8, wherein, At least one second-level connecting line extends at least partially along the second direction, and the shape of the at least one second-level connecting line is a broken line, including K-1 bends; The first end of the s-th second cross-stage connection line is electrically connected to the second pole of the sixth virtual transistor and the first pole of the seventh virtual transistor of the s-th stage virtual shift register, and the second end of the s-th second cross-stage connection line is electrically connected to the control pole of the twenty-third transistor of the s-th stage shift register. The first end of the t-th second cross-stage connection line is electrically connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor of the tK-th stage shift register, and the second end of the t-th second cross-stage connection line is electrically connected to the control terminal of the twenty-third transistor of the t-th stage shift register. The display substrate according to claim 9, wherein, The line connecting the second end of the m-th second-span connecting line and the first end of the (m+K)-th second-span connecting line intersects at least one bend in the (m+1)-m to (m+K-1)-th second-span connecting lines, where 1≤m≤N. The display substrate according to claim 9 or 10 further comprises: The driving structure layer is disposed on the substrate, the gate driving circuit is disposed on the driving structure layer, at least one level shift register includes at least one transistor and at least one capacitor, at least one level virtual shift register includes at least one virtual transistor and at least one virtual capacitor, at least one transistor or virtual transistor includes an active pattern, a control electrode, a first electrode and a second electrode, at least one capacitor or virtual capacitor includes a first electrode plate and a second electrode plate; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; The semiconductor layer includes at least: an active pattern of at least one transistor located in at least one level shift register and an active pattern of at least one virtual transistor located in at least one level virtual shift register; The first conductive layer includes at least: a first plate of a control electrode of at least one transistor and at least one capacitor located in at least one level shift register, and a first plate of a control electrode of at least one virtual transistor and at least one virtual capacitor located in at least one level virtual shift register; The second conductive layer includes at least: a second plate of at least one capacitor located in at least one level shift register and a second plate of at least one virtual capacitor located in at least one level virtual shift register; The third conductive layer includes at least: the first electrode of at least one transistor located in at least one level shift register and the second electrode of the first level shift register. Two poles, the first and second poles of at least one transistor located in at least one level shift register; The fourth conductive layer includes at least one second cross-level connection line. The display substrate according to claim 8, wherein, At least one second cross-level connection line includes: a first connection portion and a second connection portion disposed in different layers and interconnected with each other; at least one of the first connection portion and the second connection portion extends at least partially along a second direction; The first connection part of the second cross-stage connection line of the sth order is electrically connected to the second pole of the sixth virtual transistor and the first pole of the seventh virtual transistor of the sth stage virtual shift register, and the second connection part of the second cross-stage connection line of the sth order is electrically connected to the control pole of the twenty-third transistor of the sth stage shift register. The first connection of the t-th second cross-stage connection line is electrically connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor of the tK-th stage shift register, and the second connection of the t-th second cross-stage connection line is electrically connected to the control terminal of the twenty-third transistor of the t-th stage shift register. The display substrate according to claim 12, wherein, The second connecting portion of at least one second-level connecting line is zigzag-shaped and includes a bend. The line connecting the end of the second connecting part of the mth second-level connecting line away from the first connecting part and the end of the first connecting part of the (m+K)th second-level connecting line away from the second connecting part intersects the bend of the second connecting part of the (m+1)th to (m+K-1)th second-level connecting lines, where 1≤m≤N. The display substrate according to claim 12 or 13 further comprises: The driving structure layer is disposed on the substrate, the gate driving circuit is disposed on the driving structure layer, at least one level shift register includes at least one transistor and at least one capacitor, at least one level virtual shift register includes at least one virtual transistor and at least one virtual capacitor, at least one transistor or virtual transistor includes an active pattern, a control electrode, a first electrode and a second electrode, at least one capacitor or virtual capacitor includes a first electrode plate and a second electrode plate; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; The semiconductor layer includes at least: an active pattern of at least one transistor located in at least one level shift register and an active pattern of at least one virtual transistor located in at least one level virtual shift register; The first conductive layer includes at least: a first plate of a control electrode of at least one transistor and at least one capacitor located in at least one level shift register, and a first plate of a control electrode of at least one virtual transistor and at least one virtual capacitor located in at least one level virtual shift register; The second conductive layer includes at least: a second plate of at least one capacitor located in at least one level shift register and a second plate of at least one virtual capacitor located in at least one level virtual shift register; The third conductive layer includes at least: a first electrode and a second electrode of at least one transistor located in at least one level shift register; The fourth conductive layer includes at least: a first connection portion of at least one second cross-level connection line; The fifth conductive layer includes at least one second connection portion of at least one second cross-level connection line. The display substrate according to claim 3, wherein, The gate drive circuit further includes: K virtual shift registers, each virtual shift register including: a virtual shift sub-circuit and a virtual output sub-circuit; The number of the third cross-stage connection lines is N+K-1, where N is the number of shift registers included in the gate drive circuit, and at least one third cross-stage connection line extends at least partially along the second direction; For at least one shift register, the shift sub-circuit further includes: a fourth transistor; the output sub-circuit further includes: a twenty-fifth transistor; the second terminal of the fourth transistor is electrically connected to the fifth node; and the twenty-fifth transistor is connected to the third control signal... For at least one virtual shift register, the virtual shift sub-circuit further includes: a fourth virtual transistor; the virtual output sub-circuit further includes: a twenty-fifth virtual transistor; the second terminal of the fourth virtual transistor is electrically connected to the fifth node; and the control terminal of the twenty-fifth virtual transistor is electrically connected to the third control signal terminal. The kth third cross-stage connection line is electrically connected to the second electrode of the fourth virtual transistor located in the kth stage virtual shift register and the control electrode of the twenty-fifth virtual transistor in the (k+1)th stage virtual shift register, respectively. The third cross-stage connection line of the Kth stage is electrically connected to the second pole of the fourth virtual transistor located in the Kth stage virtual shift register and the control pole of the twenty-fifth transistor in the first stage shift register, respectively. The r-th third cross-stage connection line is electrically connected to the second terminal of the fourth transistor of the rK-th stage shift register and the control terminal of the twenty-fifth transistor of the r-K+1-th stage shift register, respectively, where K+1≤r≤N+K-1. The display substrate according to claim 15 further comprises: The driving structure layer is disposed on the substrate, the gate driving circuit is disposed on the driving structure layer, at least one level shift register includes at least one transistor and at least one capacitor, at least one level virtual shift register includes at least one virtual transistor and at least one virtual capacitor, at least one transistor or virtual transistor includes an active pattern, a control electrode, a first electrode and a second electrode, at least one capacitor or virtual capacitor includes a first electrode plate and a second electrode plate; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; The semiconductor layer includes at least: an active pattern of at least one transistor located in at least one level shift register and an active pattern of at least one virtual transistor located in at least one level virtual shift register; The first conductive layer includes at least: a first plate of a control electrode of at least one transistor and at least one capacitor located in at least one level shift register, and a first plate of a control electrode of at least one virtual transistor and at least one virtual capacitor located in at least one level virtual shift register; The second conductive layer includes at least: a second plate of at least one capacitor located in at least one level shift register and a second plate of at least one virtual capacitor located in at least one level virtual shift register; The third conductive layer includes at least: the first and second poles of at least one transistor located in at least one level shift register, the first and second poles of at least one transistor located in at least one level shift register, and at least one third cross-level connection line. The display substrate according to claim 1 further includes: A first power signal line group is disposed on the substrate and located in the non-display area. The first power signal line group includes: multiple first power lines, at least one first power line extending at least partially along a second direction, and multiple first power lines arranged sequentially along the direction close to the display area. At least one shift register includes: a fifth transistor, an eighth transistor, a ninth transistor, a thirteenth transistor, a nineteenth transistor, a twenty-fourth transistor, and a second capacitor; The first power line is connected to the first terminal of the fifth transistor; the second power line is connected to the first terminal of the eighth transistor, the first terminal of the ninth transistor, the first terminal of the thirteenth transistor, and the second plate of the second capacitor; the third, fourth, and fifth power lines are connected to the first terminal of the nineteenth transistor; and the third power line is also connected to the first terminal of the twenty-fourth transistor. The width of at least one of the fourth and fifth first power lines is greater than the width of at least one of the first, second, and third first power lines. The display substrate according to claim 17 further comprises: A second power signal line group is mounted on the substrate and located in the non-display area; The second power signal line group includes: multiple second power lines; at least one second power line extends at least partially along a second direction, and the multiple second power lines are arranged sequentially along the direction close to the display area; At least one shift register includes: a third transistor, a tenth transistor, a twentieth transistor, a twenty-fifth transistor, and a fourth capacitor; The first second power line is connected to the first terminal of the third transistor and the first terminal of the twenty-fifth transistor, the second second power line is connected to the first terminal of the tenth transistor, and the third second power line is connected to the first terminal of the twentieth transistor and the second plate of the fourth capacitor. The orthographic projection of the first power line on the substrate is located between the orthographic projection of the first second power line on the substrate and the orthographic projection of the second second power line on the substrate. The orthographic projection of at least one of the signal lines among the second, third, fourth, and fifth power lines on the substrate is located between the orthographic projection of the second second power line on the substrate and the orthographic projection of the third second power line on the substrate. The width of at least one signal line in the fourth and fifth first power lines is greater than the width of at least one signal line in the first and second second power lines; The width of the third second power line is greater than the width of at least one of the following signal lines: the first first power line, the second first power line, the third first power line, the first second power line, the second second power line, and the third power line. The display substrate according to claim 17 further comprises: A clock signal line group and an initial signal line group are disposed on the substrate and located in the non-display area. The clock signal line group includes a first clock signal line and a second clock signal line. The initial signal line group includes a first initial signal line and a second initial signal line. At least one of the first clock signal line, the second clock signal line, the first initial signal line and the second initial signal line extends at least partially along a second direction. The orthographic projection of the clock signal line group on the substrate is located between the orthographic projection of the first second power line on the substrate and the orthographic projection of the first first power line on the substrate. The orthographic projection of the first initial signal line on the substrate is located on the side of the first second power line on the substrate away from the display area. The orthographic projection of the second initial signal line on the substrate is located between the orthographic projection of the first first power line on the substrate and the orthographic projection of the second second power line on the substrate. The display substrate according to claim 17 further comprises: A masking signal line and a third power line are disposed on a substrate and located in a non-display area, wherein at least one of the masking signal lines and the third power line extends at least partially along a second direction; The orthographic projection of the masking signal line on the substrate is located between the orthographic projections of the second first power line and the third first power line on the substrate, and the orthographic projection of the third power line on the substrate is located between the orthographic projections of the first first power line and the second initial signal line on the substrate. The display substrate according to claim 20, wherein, The orthographic projection of the at least one second cross-level connection line on the substrate is located between the orthographic projection of the second first power line on the substrate and the orthographic projection of the masking signal line on the substrate. The display substrate according to claim 19, wherein, The orthographic projection of the at least one third cross-level connection line on the substrate is located on the side of the orthographic projection of the first initial signal line on the substrate that is far from the display area. The display substrate according to claim 1 further includes: The gate driving circuit includes multiple signal lines and at least one virtual shift register. The display substrate also includes a driving structure layer disposed on the substrate. The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; The plurality of signal lines are disposed on the fourth conductive layer, and the orthographic projection of at least one of the signal lines on the substrate at least partially overlaps with the orthographic projections of at least one level shift register and at least one level virtual shift register on the substrate. The display substrate according to claim 1, wherein, The shift sub-circuit includes: a first transistor, a seventh transistor, a ninth transistor, a tenth transistor, and a fourteenth transistor; the output sub-circuit includes: an eighteenth transistor. The transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, and the twenty-sixth transistor, wherein at least one transistor includes: an active pattern; The length of the active pattern of the first transistor along the first direction is greater than the length of at least one of the active patterns of the third transistor, the seventh transistor, the fourteenth transistor, the eighteenth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, and the twenty-sixth transistor along the first direction. The length of at least one of the active patterns of the ninth transistor and the tenth transistor along the first direction is greater than the length of at least one of the active patterns of the third transistor, the seventh transistor, the fourteenth transistor, the eighteenth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, and the twenty-sixth transistor along the first direction. The length of at least one of the active patterns of the nineteenth transistor and the twentieth transistor along the first direction is greater than the length of at least one of the active patterns of the ninth transistor and the tenth transistor along the first direction. The display substrate according to claim 1, wherein, The output sub-circuit includes: a twenty-first transistor and a twenty-second transistor; The 22nd transistor and the 21st transistor are arranged sequentially and adjacently along the direction close to the display area. The display substrate according to claim 1, wherein, The output sub-circuit includes: a twenty-second transistor, a twenty-fourth transistor, and a sixth capacitor, wherein the sixth capacitor is electrically connected to the drive signal output terminal; The orthogonal projection of the sixth capacitor onto the substrate lies between the orthogonal projections of the twenty-fourth transistor onto the substrate and the orthogonal projections of the twentyth transistor onto the substrate. A display device, comprising: The display substrate as described in any one of claims 1 to 26.

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