Display substrate and preparation method therefor

Abstract

A display substrate and a preparation method therefor. The display substrate comprises a base and a transistor device arranged on the base. The transistor device comprises: a gate electrode (11), a gate insulating layer (21), and an active layer (12) that are sequentially stacked on the base (10). A recess structure (1) is provided on the side of the gate insulating layer (21) away from the base (10), at least part of the active layer (12) is arranged in the recess structure (1), and at least two boundaries of the active layer (12) are spaced from the corresponding boundaries of the recess structure (1) by a predetermined distance.

Description

Display substrate and preparation method thereof TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular, to a display substrate and a preparation method thereof. BACKGROUND

[0002] In recent years, thin film transistor flat panel displays have been widely used in watches, mobile phones, tablet computers, desktop computers, vehicle displays, industrial Internet of Things displays, televisions and other fields of social production and life. With the expansion of the application field of flat panel displays, display technologies with excellent image quality, high smoothness, high touch performance, high refresh rate and high touch frequency have become the highest point of display industry.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising a substrate and a transistor device disposed on the substrate, the transistor device comprising: a gate electrode, a gate insulating layer and an active layer disposed on the substrate;

[0006] The gate insulating layer is provided with a groove structure away from the substrate, the active layer is located within the range of the orthographic projection of the groove structure on the substrate, and at least two boundaries of the active layer have a preset interval with the corresponding boundaries of the groove structure.

[0007] In an exemplary embodiment, the gate insulating layer comprises a first region and a second region, the second region being all regions except the first region, and the second region being located at least one side of the first region;

[0008] The groove structure is located in the first region, and the thickness of the gate insulating layer in the first region is less than the thickness of the gate insulating layer in the second region.

[0009] In an exemplary embodiment, the orthographic projection of the groove structure on the substrate is located within the range of the orthographic projection of the gate electrode on the substrate.

[0010] In an exemplary embodiment, the active layer comprises a first active layer and a second active layer, and the second active layer is disposed away from the substrate from the first active layer;

[0011] The orthographic projection of the second active layer on the substrate is located within the range of the orthographic projection of the first active layer on the substrate.

[0012] In an exemplary embodiment, the first active layer has a thickness greater than a thickness of the second active layer, and the second active layer has a conductivity greater than a conductivity of the first active layer.

[0013] In an exemplary embodiment, a distance between a surface of the first active layer away from the substrate and a surface of the gate electrode away from the substrate is less than or equal to a distance between a surface of the gate insulating layer in the second region away from the substrate and a surface of the gate electrode away from the substrate.

[0014] A distance between a surface of the second active layer away from the substrate and a surface of the gate electrode away from the substrate is greater than a distance between a surface of the gate insulating layer in the second region away from the substrate and a surface of the gate electrode away from the substrate.

[0015] In an exemplary embodiment, further comprising: a first electrode and a second electrode disposed on a side of the active layer away from the substrate, the first electrode and the second electrode being connected to the active layer, respectively.

[0016] At least a portion of a projection of the second active layer on the substrate is within a range of a projection of the first electrode on the substrate, and at least a portion of a projection of the second active layer on the substrate is within a range of a projection of the second electrode on the substrate.

[0017] In an exemplary embodiment, at least one of the first electrode and the second electrode is partially filled in the recess structure and covers a sidewall of the active layer.

[0018] At least one of the first electrode and the second electrode has a projection on the substrate at least partially overlapping a projection of the gate insulating layer in the second region on the substrate.

[0019] In an exemplary embodiment, the gate insulating layer is a single-layer structure.

[0020] The gate insulating layer in the first region has a thickness in a range of 2000 angstroms to 3500 angstroms.

[0021] A distance between a surface of the gate insulating layer in the second region away from the substrate and a surface of the gate electrode away from the substrate is in a range of 3800 angstroms to 4200 angstroms.

[0022] In an exemplary embodiment, the gate insulating layer comprises: a first gate insulating layer and a second gate insulating layer sequentially stacked on the substrate.

[0023] The second gate insulating layer is provided with a via hole exposing the first gate insulating layer, and the via hole of the second gate insulating layer and the first gate insulating layer form the groove structure.

[0024] A normal projection of the active layer on the substrate is within a range of a normal projection of the via hole on the substrate.

[0025] In an example embodiment, a thickness of the first gate insulating layer is in a range of 2000 angstroms to 3500 angstroms.

[0026] A distance between a surface of the second gate insulating layer away from the substrate and a surface of the gate electrode away from the substrate is in a range of 3800 angstroms to 4200 angstroms.

[0027] In an example embodiment, a material of the first gate insulating layer is different from a material of the second gate insulating layer.

[0028] The material of the first gate insulating layer includes one of silicon oxide and silicon nitride, and the material of the second gate insulating layer includes the other of silicon oxide and silicon nitride.

[0029] In an example embodiment, a material of the active layer includes metal oxide.

[0030] The material of the first gate insulating layer includes silicon oxide, and the material of the second gate insulating layer includes silicon nitride.

[0031] In an example embodiment, a material of the active layer includes amorphous silicon.

[0032] The material of the first gate insulating layer includes silicon nitride, and the material of the second gate insulating layer includes silicon oxide.

[0033] In an example embodiment, a thickness of the gate electrode is in a range of 2000 angstroms to 5000 angstroms.

[0034] A thickness of at least one of the first electrode and the second electrode is in a range of 2000 angstroms to 5000 angstroms.

[0035] A thickness of the active layer is in a range of 1700 angstroms to 2200 angstroms.

[0036] In an example embodiment, a minimum width of at least one of the first electrode and the second electrode along an arrangement direction of the first electrode and the second electrode is in a range of 2.5 micrometers to 3.5 micrometers.

[0037] In an example embodiment, the first electrode surrounds at least one side of the second electrode, a projection of the first electrode on the substrate covers at least part of a sidewall of the active layer, and a projection of the second electrode on the substrate at least partially overlaps with a projection of a middle part of the active layer on the substrate.

[0038] A distance between a projection of a boundary of the recess structure on the substrate and a projection of a boundary of the active layer on the substrate is smaller than a distance between a projection of a boundary of the first electrode close to the second electrode on the substrate and a projection of a boundary of the active layer on the substrate.

[0039] A distance between a projection of a boundary of the first electrode close to the second electrode on the substrate and a projection of a boundary of the active layer on the substrate is greater than a distance between a projection of a boundary of the first electrode away from the second electrode on the substrate and a projection of a boundary of the gate electrode on the substrate.

[0040] In an example embodiment, the display substrate further comprises a passivation layer.

[0041] The passivation layer is located on a side of the first electrode and the second electrode away from the substrate.

[0042] In a second aspect, the disclosure also provides a method for manufacturing a display substrate configured to manufacture the display substrate described above, the method comprising:

[0043] forming a gate electrode of a transistor device on a substrate;

[0044] forming a gate insulating layer of the transistor device on the gate electrode, the gate insulating layer being provided with a recess structure, and the recess structure being located on a side of the gate insulating layer away from the substrate;

[0045] forming an active layer of the transistor device in the recess structure of the gate insulating layer, at least two boundaries of the active layer having a preset interval with corresponding boundaries of the recess structure.

[0046] In an example embodiment, the forming the gate insulating layer of the transistor device on the gate electrode comprises:

[0047] coating a gate insulating film on the gate electrode, and forming the gate insulating layer of the transistor device by forming a recess structure on the gate insulating film through a patterning process.

[0048] In an example embodiment, the forming the gate insulating layer of the transistor device on the gate electrode comprises:

[0049] sequentially coating a first gate insulating film and a second gate insulating film on the gate electrode,

[0050] The via is formed by a patterning process on the second gate insulating film, the gate insulating layer of the transistor device is formed, and the groove structure is formed by the via and the first gate insulating film.

[0051] In an example embodiment, the active layer includes a first active layer and a second active layer, and the active layer of the transistor device formed in the groove structure of the gate insulating layer includes:

[0052] A semiconductor film is deposited on the gate insulating layer;

[0053] The semiconductor film is treated by a hydrogenation process to form the first active layer and a third active layer;

[0054] A source-drain metal film is deposited on the third active layer, and the source-drain metal film and the third active layer are treated by a patterning process to form the second active layer, a first electrode and a second electrode.

[0055] In an example embodiment, the display substrate further includes:

[0056] A passivation layer is formed on the first electrode and the second electrode.

[0057] Other aspects can be apparent after reading and understanding the accompanying drawings and detailed description.

[0058] SUMMARY

[0059] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and together with the embodiments of the present disclosure, are used to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0060] FIG. 1 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0061] FIG. 2 is a structural schematic diagram of part of the film layers according to FIG. 1;

[0062] FIG. 3 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0063] FIG. 4 is a structural schematic diagram of part of the film layers according to FIG. 3;

[0064] FIG. 5 is a top view of a transistor device according to FIG. 1 and FIG. 3;

[0065] FIG. 6 is a curve diagram of the thickness of the gate insulating layer and the normalized coefficient of Ion;

[0066] FIG. 7 is a curve diagram of the voltage Vg of the gate electrode and the current Id flowing through the source electrode under different thicknesses of the gate insulating layer;

[0067] FIG. 8 is a top view of a transistor device;

[0068] Fig. 9 is a sectional view of Fig. 8 along A-A;

[0069] Fig. 10 is a sectional view of Fig. 8 along B-B;

[0070] Fig. 11 is a schematic view showing one structure of a display substrate;

[0071] Fig. 12 is a schematic view showing another structure of a display substrate;

[0072] Fig. 13 is a schematic view of Fig. 11 after forming a gate electrode;

[0073] Fig. 14 is a schematic view of Fig. 11 after forming a gate insulating layer;

[0074] Fig. 15 is a schematic view of Fig. 11 after forming an original semiconductor layer;

[0075] Fig. 16 is a schematic view of Fig. 11 after forming a first electrode and a second electrode;

[0076] Fig. 17 is a schematic view of Fig. 11 after forming a passivation layer;

[0077] Fig. 18 is a schematic view of Fig. 12 after forming a gate insulating layer;

[0078] Fig. 19 is a schematic view of Fig. 12 after forming an original semiconductor layer;

[0079] Fig. 20 is a schematic view of Fig. 12 after forming a first electrode and a second electrode;

[0080] Fig. 21 is a schematic view of Fig. 12 after forming a passivation layer.

[0081] DETAILED DESCRIPTION

[0082] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. One skilled in the art can easily understand that the means and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

[0083] The scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted as needed. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings. The drawings described in this disclosure are only schematic diagrams, and one embodiment of the disclosure is not limited to the shapes or values shown in the drawings.

[0084] The ordinal numbers "first", "second", "third" and the like in this specification are used to avoid confusion among components, and are not intended to be limiting in terms of number.

[0085] In this specification, in order to facilitate the description and simplify the description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the positional relationship of the components with reference to the drawings, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0086] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication between two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0087] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0088] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0089] In the present specification, "electrically connected" includes a case where components are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between the components to be connected. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0090] In the present specification, "parallel" means a state where two straight lines form an angle of -10° or more and 10° or less, and thus, a state where the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where two straight lines form an angle of 80° or more and 100° or less, and thus, a state where the angle is 85° or more and 95° or less is also included.

[0091] In the present specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be sometimes interchanged with "a conductive film". Similarly, "an insulating film" can be sometimes interchanged with "an insulating layer".

[0092] In the present specification, "disposed in the same layer" means structures of two (or more) kinds that are patterned by one patterning process, and the materials thereof can be the same or different. For example, the materials of precursors for forming the structures disposed in the same layer are the same, and the materials finally formed can be the same or different.

[0093] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, an arc edge, and deformation, and the like.

[0094] A transistor is limited in an on-current by a semiconductor property of the transistor, i.e., a carrier mobility, and thus it is difficult to further improve the on-current, which limits improvement in a refresh rate of a display product.

[0095] To address this, the present disclosure provides a transistor device.

[0096] FIG. 1 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure, FIG. 2 is a structural schematic diagram of part of a film layer according to FIG. 1, FIG. 3 is a structural schematic diagram of a display substrate according to another embodiment of the present disclosure, and FIG. 4 is a structural schematic diagram of part of a film layer according to FIG. 3. As shown in FIGS. 1 to 4, the display substrate according to an embodiment of the present disclosure can include a substrate and a transistor device disposed on the substrate. The transistor device can include a gate electrode 11, a gate insulating layer 21, and an active layer 12, which are sequentially stacked on the substrate 10. The second direction Y in FIGS. 1 to 4 is the direction in which the gate electrode, the gate insulating layer, and the active layer are stacked, and the first direction X can be the extension direction of the active layer. The first direction X intersects the second direction Y.

[0097] As shown in FIGS. 1 to 4, the gate insulating layer 21 is provided with a groove structure 1 on the side away from the substrate 10, and at least part of the active layer 12 is disposed in the groove structure 1. At least two boundaries of the active layer 12 have a predetermined spacing from the corresponding boundaries of the groove structure. That is, the orthogonal projection of the active layer 12 on the substrate 10 is within the orthogonal projection of the groove structure 1 on the substrate 10. The width of the longitudinal cross-section of the active layer 12 falls entirely within the groove structure 1.

[0098] In an exemplary embodiment, the substrate 10 can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass, conductive foil, and the like. The flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0099] In an exemplary embodiment, the transistor device according to the present disclosure is a bottom-gate structure.

[0100] In an exemplary embodiment, the gate electrode 11 can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The gate electrode can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, and the like. Exemplarily, the gate electrode can be made of Al / Mo or MoNb / Cu.

[0101] In an exemplary embodiment, the gate insulating layer 21 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer.

[0102] In example embodiments, the material of the active layer can include one or more of amorphous silicon (a-Si), low temperature polysilicon (LTPS), metal oxide. Among them, the metal oxide layer can be an oxide including indium and tin, an oxide including tungsten and indium, an oxide including tungsten and indium and zinc, an oxide including titanium and indium, an oxide including titanium and indium and tin, an oxide including indium and zinc, an oxide including silicon and indium and tin, or an oxide including indium or gallium and zinc.

[0103] In some embodiments, the material of the active layer can be M1OaNb, where M1 is a single metal or a combination of multiple metals, a > 0, and b ≥ 0, O represents an oxygen element, and N represents a nitrogen element, that is, the material of the active layer is a metal oxide material or a metal oxynitride material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), In-free OS, rare earth doped oxide (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0104] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or a combination thereof. In one example, the material of the channel region CH1 / CH2 / CH3 includes indium gallium zinc oxide (IGZO). The material of the active layer can be in an amorphous, partially crystalline, single crystalline, or polycrystalline state, and can be a single layer or a multi-layer structure.

[0105] In example embodiments, the transistor device further includes a first electrode 13 and a second electrode 14 located on a side of the active layer 12 away from the substrate 10, and the first electrode 13 and the second electrode 14 are respectively connected to the active layer 12. In example embodiments, the first electrode 13 can be one of a source electrode and a drain electrode, and the second electrode 14 can be the other of the source electrode and the drain electrode.

[0106] In the example embodiments, the first electrode 13 and the second electrode 14 can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), niobium (Nb), neodymium (Nd), nickel (Ni), and molybdenum (Mo), or an alloy material composed of at least two of the above-mentioned metals, such as an aluminum neodymium alloy (AlNd), a titanium aluminum alloy (TiAl), a molybdenum nickel titanium alloy (Mo-Ni-Ti, MTD), or a molybdenum niobium alloy (MoNb), and can also be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the first electrode 13 and the second electrode 14 can adopt Mo / Al / Mo, MoNb / Cu, MTD / Cu / MTD, Cu / MTD.

[0107] In the example embodiments, the on-current Ion of the transistor satisfies the following formula, Ion = (W / L) * C * [(V gs -V th )*V ds -0.5*(V ds ) 2 ]

[0108] wherein W is the width of the channel region of the active layer, L is the length of the channel region of the active layer, C is the parasitic capacitance between the channel region of the active layer and the gate electrode, V gs is the voltage difference between the gate electrode and the source electrode of the transistor, V ds is the voltage difference between the drain electrode and the source electrode of the transistor, and V th is the threshold voltage of the transistor. As can be seen from the above formula, the on-current Ion of the transistor depends on the parameters C, W, L, V gs , V th , and V ds .

[0109] The present disclosure reduces the thickness of the gate insulating layer that overlaps with the active layer by providing a recess structure on the side of the gate insulating layer away from the substrate, arranging at least part of the active layer in the recess structure, and arranging at least two boundaries of the active layer to have a preset interval with the corresponding boundaries of the recess structure, increases the capacitance value of the parasitic capacitance between the channel region of the active layer and the gate electrode, increases the on-current of the transistor device, and thus can improve the refresh frequency of the display product.

[0110] In the example embodiments, as shown in FIGS. 2 and 4, the gate insulating layer 21 includes a first region R1 and a second region R2, the second region R2 being all regions except the first region R1, and the second region R2 being arranged around at least one side of the first region R1.

[0111] In an example embodiment, as shown in FIGS. 2 and 4, the recess structure 1 is located in the first region R1, and the thickness H1 of the gate insulating layer 21 located in the first region R1 is less than the thickness H2 of the gate insulating layer 21 located in the second region R2.

[0112] In an example embodiment, FIG. 5 is a top view of the transistor device provided in FIGS. 1 and 3. As shown in FIG. 5, the orthographic projection of the recess structure 1 on the substrate 10 is located within the orthographic projection of the gate electrode 11 on the substrate 10.

[0113] In an example embodiment, the shape of the recess structure in the cross section parallel to the substrate direction can be circular, square, rectangular, or other shapes, and the present disclosure does not make any limitation thereto. FIG. 5 is an example of the shape of the recess structure in the cross section parallel to the substrate direction being square.

[0114] In an example embodiment, as shown in FIGS. 1, 3, and 5, the active layer 12 can include a first active layer 121 and a second active layer 122. The second active layer 122 is disposed on the side of the first active layer 121 away from the substrate 10.

[0115] In an example embodiment, as shown in FIG. 5, the orthographic projection of the second active layer 122 on the substrate 10 can be located within the orthographic projection of the first active layer 121 on the substrate 10.

[0116] In an example embodiment, the thickness of the first active layer 121 is greater than the thickness of the second active layer 122.

[0117] In an example embodiment, the electrical conductivity of the second active layer 122 is greater than the electrical conductivity of the first active layer 121.

[0118] In an example embodiment, the first active layer 121 can be an amorphous silicon layer or a metal oxide layer.

[0119] In an example embodiment, the second active layer 122 is an N-type semiconductor layer. For example, the second active layer 122 is an N-type doped amorphous silicon layer or a metal oxide layer.

[0120] In an example embodiment, as shown in FIGS. 1 and 3, the distance L1 between the surface of the first active layer 121 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is less than or equal to the distance L2 between the surface of the gate insulating layer 21 located in the second region away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10. FIGS. 1 and 3 are examples in which the distance L1 between the surface of the first active layer 121 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is equal to the distance L2 between the surface of the gate insulating layer 21 located in the second region away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10.

[0121] In an example embodiment, as shown in FIG. 1 and FIG. 3, the distance L3 between the surface of the second active layer 122 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is greater than the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10.

[0122] In an example embodiment, as shown in FIG. 1 and FIG. 3, the orthographic projection of at least part of the second active layer 122 on the substrate 10 is within the orthographic projection of the first electrode 13 on the substrate 10, i.e. the first electrode 13 covers at least part of the second active layer.

[0123] In an example embodiment, as shown in FIG. 1 and FIG. 3, the orthographic projection of at least part of the second active layer 122 on the substrate 10 is within the orthographic projection of the second electrode 14 on the substrate 10, i.e. the second electrode 14 covers at least part of the second active layer.

[0124] In an example embodiment, as shown in FIG. 1, FIG. 3 and FIG. 5, at least one of the first electrode 13 and the second electrode 14 is partially filled in the groove structure 1 and covers the sidewall of the active layer 12.

[0125] In an example embodiment, as shown in FIG. 1, FIG. 3 and FIG. 5, the orthographic projection of at least one of the first electrode 13 and the second electrode 14 on the substrate 10 at least partially overlaps with the orthographic projection of the gate insulating layer 21 in the second region on the substrate 10. The at least partial overlap between the orthographic projection of at least one of the first electrode 13 and the second electrode 14 on the substrate 10 and the orthographic projection of the gate insulating layer 21 in the second region on the substrate 10 can ensure that the first electrode and the second electrode can sufficiently contact the active layer 12.

[0126] In an example embodiment, as shown in FIG. 1 and FIG. 2, the gate insulating layer 21 can be a single-layer structure.

[0127] In an example embodiment, as shown in FIG. 2, the thickness H1 of the gate insulating layer 21 in the first region R1 is within the range of 2000 angstroms to 3500 angstroms. Exemplarily, the thickness H1 of the gate insulating layer 21 in the first region R1 can be 2000 angstroms.

[0128] In an example embodiment, when the gate insulating layer 21 is a single-layer structure, the material of the gate insulating layer 21 can include silicon oxide or silicon nitride.

[0129] In an example embodiment, as shown in FIG. 2, the distance H between the surface of the gate insulating layer 21 in the second region R2 and the surface of the gate electrode 11 away from the substrate 10 is in the range of 3800-4200 angstroms. Exemplarily, the distance H between the surface of the gate insulating layer 21 in the second region R2 and the surface of the gate electrode 11 away from the substrate 10 can be 4000 angstroms.

[0130] In an example embodiment, when the gate insulating layer is a single layer structure, the thickness of the gate insulating layer is the thickness of the gate insulating layer in the second region. The thickness of the gate insulating layer is in the range of 3800-4200 angstroms.

[0131] In an example embodiment, the distance H between the surface of the gate insulating layer 21 in the second region R2 and the surface of the gate electrode 11 away from the substrate 10 can be controlled by the etching time of the gate insulating layer.

[0132] In an example embodiment, as shown in FIG. 3 and FIG. 4, the gate insulating layer 21 can include a first gate insulating layer 22 and a second gate insulating layer 23 which are sequentially stacked on the substrate 10.

[0133] In an example embodiment, as shown in FIG. 4, the second gate insulating layer 23 is provided with a via V which exposes the first gate insulating layer 22, and the via V of the second gate insulating layer 23 and the first gate insulating layer 22 form a groove structure 1.

[0134] In an example embodiment, as shown in FIG. 4, the orthographic projection of the active layer 12 on the substrate 10 is within the orthographic projection of the via V on the substrate 10.

[0135] In an example embodiment, as shown in FIG. 4, the thickness H2 of the first gate insulating layer 22 is in the range of 2000-3500 angstroms. Exemplarily, the thickness H3 of the first gate insulating layer 22 can be 2000 angstroms. In an example embodiment, the thinner the thickness of the first gate insulating layer, the more obvious the effect of improving the on-state current of the transistor device.

[0136] In an example embodiment, as shown in FIG. 3, the distance H between the surface of the second gate insulating layer 23 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is in the range of 3800-4200 angstroms.

[0137] In an example embodiment, when the gate insulating layer is a double layer structure, the thickness of the gate insulating layer is equal to the sum of the thickness of the first gate insulating layer and the thickness of the second gate insulating layer. The thickness of the gate insulating layer is in the range of 3800-4200 angstroms.

[0138] In the example embodiment, the first gate insulating layer 22 and the second gate insulating layer 23 are made of different materials. The material of the first gate insulating layer 22 includes one of silicon oxide and silicon nitride, and the material of the second gate insulating layer 23 includes the other of silicon oxide and silicon nitride.

[0139] In the example embodiment, the first gate insulating layer 22 and the second gate insulating layer 23 are made of different materials, and the first gate insulating layer 22 and the second gate insulating layer 23 require different dry etching gases. When forming the gate insulating layer, only the etching gas for the second gate insulating layer is used, and the etching gas for the first gate insulating layer is not used. In this way, the second gate insulating layer can be etched, and the first gate insulating layer is completely retained, thereby avoiding changes in transistor characteristics caused by etching amount fluctuations.

[0140] In the example embodiment, the active layer 12 is made of a metal oxide. The first gate insulating layer 22 is made of silicon oxide, and the second gate insulating layer 23 is made of silicon nitride.

[0141] In the example embodiment, the active layer 12 is made of amorphous silicon. The first gate insulating layer 22 is made of silicon nitride, and the second gate insulating layer 23 is made of silicon oxide.

[0142] FIG. 6 is a graph of the gate insulating layer thickness and the Ion normalization coefficient. As shown in FIG. 6, the smaller the gate insulating layer thickness, the greater the improvement in the on-current Ion of the transistor.

[0143] FIG. 7 is a graph of the voltage Vg of the gate electrode and the current Id flowing through the source electrode under different gate insulating layer thicknesses. As shown in FIG. 7, S1 is a graph of the voltage of the gate electrode and the current flowing through the source electrode when the gate insulating layer thickness is 3500 angstroms, and S2 is a graph of the voltage of the gate electrode and the current flowing through the source electrode when the gate insulating layer thickness is 4000 angstroms. As shown in FIG. 7, the smaller the gate insulating layer thickness, the greater the improvement in the on-current Ion of the transistor.

[0144] The smaller the gate insulating layer thickness, the greater the increase in the failure rate of the load of the display product and the short circuit between the data line and the gate line.

[0145] The present disclosure can improve the on-current of the transistor while reducing the failure rate of the load of the display product and the short circuit between the data line and the gate line when the thickness of the gate insulating layer is in the range of 3800 angstroms to 4200 angstroms.

[0146] In the example embodiment, the thickness of the gate electrode 11 is in the range of 2000 angstroms to 5000 angstroms. The thickness of the gate electrode 11 depends on the resolution and refresh frequency of the display product, and the present disclosure does not make any limitation thereon.

[0147] In an exemplary embodiment, the thickness of at least one of the first electrode 13 and the second electrode 14 is in the range of 2000 angstroms to 5000 angstroms. The thickness of at least one of the first electrode 13 and the second electrode 14 depends on the resolution and refresh frequency of the display product, and the present disclosure does not make any limitation in this regard.

[0148] In an exemplary embodiment, the thickness of the active layer 12 is in the range of 1700 angstroms to 2200 angstroms.

[0149] The subsequent process flow is shown in FIG. 2. Thus, the overall Ion value of the TFT can be adjusted by adjusting the thickness of the GI1 deposition. As can be seen from the above formula, the Ion value ratio is proportional to the GI thinning value and the initial GI value ratio, i.e., Ion / Ionref=GIref / GI. FIG. 4 shows the relationship between the Ion normalization coefficient and GI using a-Si as an example. In theory, the thinner the GI, the greater the Ion improvement, but GI thinning will cause an increase in the gate parasitic capacitance and source / drain parasitic capacitance of the TFT, and the DGS defect rate will also increase, so in general industrial production, the commonly used value of the thickness of GI1 is 2000 angstroms to 3500 angstroms.

[0150] In an exemplary embodiment, the thickness of the gate electrode of the transistor is determined by the product characteristics of the product, wherein the product characteristics include: resolution and refresh frequency.

[0151] In an exemplary embodiment, the thickness of the first electrode and the second electrode of the transistor is determined by the product characteristics of the product.

[0152] In an exemplary embodiment, the thickness of the gate insulating layer can be 4000 angstroms.

[0153] In an exemplary embodiment, the thickness of the first gate insulating layer can be between 2000 angstroms and 3500 angstroms. The thinner the thickness of the first gate insulating layer, the more obvious the improvement effect on the on-current of the transistor device.

[0154] FIG. 8 is a top view of a transistor device, FIG. 9 is a sectional view of FIG. 8 along A-A, and FIG. 10 is a sectional view of FIG. 8 along B-B. As shown in FIGS. 8 to 10, the first electrode 13 can surround at least one side of the second electrode 14, and the orthographic projection of the first electrode 13 on the substrate 10 covers the sidewall of the active layer 12, and the orthographic projection of the second electrode 14 on the substrate 10 at least partially overlaps with the orthographic projection of the middle part of the active layer 12 on the substrate 10. That is, the first electrode 13 in FIG. 8 at least partially surrounds the second electrode 14. FIG. 5 is described by taking the first electrode and the second electrode as strips as an example, and FIG. 8 is described by taking the first electrode 13 at least partially surrounding the second electrode 14 as an example.

[0155] In the example embodiment, as shown in FIGS. 5 and 8, the minimum width W of at least one of the first electrode 13 and the second electrode 14 along the arrangement direction of the first electrode 13 and the second electrode 14 is in the range of 2.5 microns to 3.5 microns.

[0156] In the example embodiment, as shown in FIGS. 5 and 8, the distance W2 between the orthographic projection of the boundary of the recess structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is less than the distance W3 between the orthographic projection of the boundary of the first electrode 13 close to the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10.

[0157] In the example embodiment, as shown in FIGS. 5 and 8, the distance W3 between the orthographic projection of the boundary of the first electrode 13 close to the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 on the substrate 10.

[0158] In the example embodiment, the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 on the substrate 10 satisfies the overlap error between the film layer where the gate electrode is located and the film layer where the first electrode 13 and the second electrode 14 are located, i.e., the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 on the substrate 10 is greater than or equal to the overlap error between the film layer where the gate electrode 11 is located and the film layer where the first electrode 13 and the second electrode 14 are located.

[0159] In the example embodiment, the distance W2 between the orthographic projection of the boundary of the recess structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 satisfies the overlap error between the film layer where the active layer is located and the film layer where the gate insulating layer is located, i.e., the distance W1 between the orthographic projection of the boundary of the recess structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than or equal to the overlap error between the film layer where the active layer is located and the film layer where the gate insulating layer is located.

[0160] In the example embodiment, the distance W3 between the orthographic projection of the boundary of the first electrode 13 close to the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than or equal to the overlap error between the film layer where the active layer is located and the film layer where the first electrode and the second electrode are located plus 1 micron, so as to ensure the overlap area between one of the first electrode and the second electrode and the active layer, which can improve the reliability of the transistor device.

[0161] In the example embodiment, the distance W4 between the first electrode 13 and the second electrode 14 along the first electrode and second electrode arrangement direction is determined by the resolution of the exposure machine used in the process of forming the first electrode and the second electrode, the process type, and the product model, and the present disclosure does not make any limitation thereto.

[0162] In the example embodiment, FIG. 11 is a schematic structural diagram of a display substrate, and FIG. 12 is another schematic structural diagram of a display substrate. As shown in FIGS. 11 and 12, the transistor device further comprises a passivation layer 31. The passivation layer 31 is located on the side of the first electrode 13 and the second electrode 14 of the transistor away from the substrate 10. In the example embodiment, the passivation layer can protect the metal film layer where the first electrode and the second electrode of the transistor are located, can avoid the metal film layer where the first electrode and the second electrode of the transistor are located from being corroded, and can improve the reliability of the transistor device.

[0163] In the example embodiment, the passivation layer 31 can be any one or more of silicon oxide compound (SiOx), silicon nitride compound (SiNx), and silicon oxynitride compound (SiON), and can be a single layer, multiple layers, or a composite layer.

[0164] The “patterning process” in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, and the like for metal materials, inorganic materials, or transparent conductive materials, and includes coating organic materials, mask exposure, development, and the like for organic materials. The deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can use any one or more of spraying, spin coating, and inkjet printing, and the etching can use any one or more of dry etching and wet etching, and the present disclosure does not make any limitation. The “thin film” refers to a thin film of a certain material made on a substrate by deposition, coating, or other processes. If the “thin film” does not need to be patterned during the entire manufacturing process, the “thin film” can also be referred to as a “layer”. If the “thin film” needs to be patterned during the entire manufacturing process, it is referred to as a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one “pattern”. The “A and B are arranged in the same layer” in the present disclosure means that A and B are formed at the same time by the same patterning process. The “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the example embodiment of the present disclosure, “the orthographic projection of B is within the orthographic projection of A” or “the orthographic projection of A contains the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0165] The preparation process of the transistor device provided in FIG. 11 is exemplarily described below.

[0166] (1) Forming the gate electrode. In an exemplary embodiment, forming the gate electrode comprises: depositing a first metal thin film on the substrate, patterning the first metal thin film by a patterning process, and forming the gate electrode 11. As shown in FIG. 13, FIG. 13 is a schematic diagram of the structure after forming the gate electrode of FIG. 11.

[0167] (2) Forming the gate insulating layer. In an exemplary embodiment, forming the gate insulating layer comprises: depositing a gate insulating thin film on the substrate with the gate electrode formed thereon, patterning the gate insulating thin film by a patterning process, and forming the gate insulating layer 21 with the groove structure 1 arranged thereon. As shown in FIG. 14, FIG. 14 is a schematic diagram of the structure after forming the gate insulating layer of FIG. 11.

[0168] In an exemplary embodiment, the gate insulating thin film is deposited on the substrate with the gate electrode formed thereon by a chemical vapor deposition process.

[0169] (3) Forming the original semiconductor layer. In an exemplary embodiment, forming the original semiconductor layer comprises: depositing a semiconductor thin film on the substrate with the gate insulating layer formed thereon, doping the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process, thereby forming the original semiconductor layer comprising the first active layer 121 and the third active layer 123. As shown in FIG. 15, FIG. 15 is a schematic diagram of the structure after forming the original semiconductor layer of FIG. 11.

[0170] In an exemplary embodiment, the third active layer 123 is an N-type semiconductor layer.

[0171] In an exemplary embodiment, the third active layer 123 is an N-type semiconductor layer.

[0172] (4) Forming the first electrode and the second electrode. In an exemplary embodiment, forming the first electrode and the second electrode comprises: depositing a second metal thin film on the substrate with the original semiconductor layer formed thereon, and patterning the second metal thin film and the third active layer by a patterning process, respectively, thereby forming the first electrode 13, the fourth electrode 14, and the second active layer 122. As shown in FIG. 16, FIG. 16 is a schematic diagram of the structure after forming the first electrode and the second electrode of FIG. 11.

[0173] In an exemplary embodiment, the active layer comprises the first active layer 121 and the second active layer 122.

[0174] (5) Forming the passivation layer. In an exemplary embodiment, forming the passivation layer comprises: depositing a passivation layer on the substrate with the first electrode and the second electrode formed thereon. As shown in FIG. 17, FIG. 17 is a schematic diagram of the structure after forming the passivation layer of FIG. 11.

[0175] The preparation process of the transistor device provided by FIG. 12 is exemplarily illustrated below.

[0176] (1) Forming a gate electrode. In an example embodiment, forming the gate electrode includes depositing a first metal thin film on the substrate, patterning the first metal thin film by a patterning process, and forming the gate electrode. The schematic diagram after forming the gate electrode in FIG. 12 is the same as that in FIG. 9.

[0177] (2) Forming a gate insulating layer. In an example embodiment, forming the gate insulating layer includes sequentially depositing a first gate insulating thin film and a second gate insulating thin film on the substrate on which the gate electrode is formed, patterning the second gate insulating thin film by a patterning process, and forming the gate insulating layer 21 including the first gate insulating layer 22 and the second gate insulating layer 23. As shown in FIG. 18, the schematic diagram after forming the gate insulating layer in FIG. 12 is the same as that in FIG. 18.

[0178] In an example embodiment, the second gate insulating layer 23 is provided with a via V exposing the first gate insulating layer 22. The via V and the first gate insulating layer 22 constitute a groove structure.

[0179] In an example embodiment, the first gate insulating thin film and the second gate insulating thin film are sequentially deposited on the substrate on which the gate electrode is formed by a chemical vapor deposition process.

[0180] (3) Forming a raw semiconductor layer. In an example embodiment, forming the raw semiconductor layer includes depositing a semiconductor thin film on the substrate on which the gate insulating layer is formed, N-type doping the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form the raw semiconductor layer including the first active layer 121 and the third active layer 123. As shown in FIG. 19, the schematic diagram after forming the raw semiconductor layer in FIG. 12 is the same as that in FIG. 19.

[0181] In an example embodiment, the third active layer 123 is an N-type semiconductor layer.

[0182] In an example embodiment, the third active layer 123 is an N-type semiconductor layer.

[0183] (4) Forming a first electrode and a second electrode. In an example embodiment, forming the first electrode and the second electrode includes depositing a second metal thin film on the substrate on which the raw semiconductor layer is formed, and patterning the second metal thin film and the third active layer by a patterning process, respectively, to form the first electrode 13, the fourth electrode 14, and the second active layer 122. As shown in FIG. 20, the schematic diagram after forming the first electrode and the second electrode in FIG. 12 is the same as that in FIG. 20.

[0184] In an example embodiment, the active layer includes the first active layer 121 and the second active layer 122.

[0185] (5) Forming a passivation layer. In an example embodiment, forming the passivation layer includes depositing the passivation layer on the substrate on which the first electrode and the second electrode are formed. As shown in FIG. 21, which is a schematic diagram of the transistor device after the passivation layer is formed in FIG. 12.

[0186] The embodiments of the present disclosure also provide a method for manufacturing a transistor device, configured to manufacture the transistor device provided by any one of the preceding embodiments. The method for manufacturing the transistor device includes:

[0187] Step 100, forming a gate electrode of the transistor device on a substrate.

[0188] Step 200, forming a gate insulating layer of the transistor device on the gate electrode, the gate insulating layer being provided with a groove structure, and the groove structure being located on a side of the gate insulating layer away from the substrate.

[0189] Step 300, forming an active layer of the transistor device in the groove structure of the gate insulating layer.

[0190] In the example embodiment, the active layer includes a first active layer and a second active layer. Step 300 includes: depositing a semiconductor thin film on the gate insulating layer; treating the semiconductor thin film by a hydrogenation process to form the first active layer and a third active layer;

[0191] In the example embodiment, step 200 can include: coating a gate insulating film on the gate electrode, and opening a groove on the gate insulating film by a patterning process to form the gate insulating layer of the transistor device.

[0192] In the example embodiment, step 200 can include: coating a first gate insulating film and a second gate insulating film on the gate electrode in sequence, opening a via on the second gate insulating film by a patterning process to form the gate insulating layer provided with the groove structure composed of the via and the first gate insulating film.

[0193] In the example embodiment, the active layer includes a first active layer and a second active layer. Step 300 includes: depositing a semiconductor thin film on the gate insulating layer; treating the semiconductor thin film by a hydrogenation process to form the first active layer and a third active layer;

[0194] depositing a source-drain metal thin film on the third active layer, and treating the source-drain metal thin film and the third active layer by a patterning process to form the second active layer, the first electrode and the second electrode.

[0195] In the example embodiment, the method for manufacturing the transistor device further includes:

[0196] Step 400, forming a passivation layer on the first electrode and the second electrode.

[0197] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0198] For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of layers or microstructures are exaggerated. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intervening element can also be present.

[0199] Although the embodiments disclosed by the present disclosure are as above, the content described is only the embodiments adopted for the convenience of understanding the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate comprising a base and a transistor device disposed on the base, the transistor device comprising: A gate electrode, a gate insulating layer and an active layer are disposed on the substrate; The gate insulating layer is provided with a groove structure on a side away from the substrate, a normal projection of the active layer on the substrate is located within a normal projection of the groove structure on the substrate, and at least two boundaries of the active layer have a preset interval with corresponding boundaries of the groove structure. 2.The display substrate of claim 1, wherein, The gate insulating layer comprises a first region and a second region, the second region being all regions except the first region, and the second region being located on at least one side of the first region; The groove structure is located in the first region, and a thickness of the gate insulating layer in the first region is less than a thickness of the gate insulating layer in the second region. 3.The display substrate of claim 1, wherein, A normal projection of the groove structure on the substrate is located within a normal projection of the gate electrode on the substrate. 4.The display substrate of claim 2, wherein, The active layer comprises a first active layer and a second active layer, and the second active layer is disposed on a side of the first active layer away from the substrate; A normal projection of the second active layer on the substrate is located within a normal projection of the first active layer on the substrate. 5.The display substrate of claim 4, wherein, A thickness of the first active layer is greater than a thickness of the second active layer, and a conductivity of the second active layer is greater than a conductivity of the first active layer. 6.The display substrate of claim 4, wherein, A distance between a surface of the first active layer away from the substrate and a surface of the gate electrode away from the substrate is less than or equal to a distance between a surface of the gate insulating layer in the second region away from the substrate and a surface of the gate electrode away from the substrate; A distance between a surface of the second active layer away from the substrate and a surface of the gate electrode away from the substrate is greater than a distance between a surface of the gate insulating layer in the second region away from the substrate and a surface of the gate electrode away from the substrate. 7.The display substrate of claim 4, further comprising: A first electrode and a second electrode are disposed on a side of the active layer away from the substrate, and the first electrode and the second electrode are connected with the active layer respectively; At least part of a normal projection of the second active layer on the substrate is located within a normal projection of the first electrode on the substrate, and at least part of a normal projection of the second active layer on the substrate is located within a normal projection of the second electrode on the substrate. 8.The display substrate of claim 7, wherein, At least part of at least one of the first electrode and the second electrode fills in the groove structure and covers a sidewall of the active layer; A normal projection of at least one of the first electrode and the second electrode on the substrate at least partially overlaps with a normal projection of the gate insulating layer in the second region on the substrate. 9.The display substrate of claim 2, wherein, The gate insulating layer is a single-layer structure; A thickness of the gate insulating layer in the first region is in a range of 2000 angstroms to 3500 angstroms; A distance between a surface of the gate insulating layer in the second region away from the substrate and a surface of the gate electrode away from the substrate is in a range of 3800 angstroms to 4200 angstroms. 10.The display substrate of claim 2, wherein, The gate insulating layer comprises a first gate insulating layer and a second gate insulating layer which are sequentially stacked on the substrate; The second gate insulating layer is provided with a via hole exposing the first gate insulating layer, and the via hole of the second gate insulating layer and the first gate insulating layer constitute the groove structure. A normal projection of the active layer on the substrate is located within a normal projection of the via on the substrate. 11.The display substrate of claim 10, wherein, A thickness of the first gate insulating layer is in a range of 2000 angstroms to 3500 angstroms; A distance between a surface of the second gate insulating layer away from the substrate and a surface of the gate electrode away from the substrate is in a range of 3800 angstroms to 4200 angstroms. 12.The display substrate of claim 10, wherein, The first gate insulating layer and the second gate insulating layer are made of different materials. The first gate insulating layer is made of one of silicon oxide and silicon nitride, and the second gate insulating layer is made of the other one of silicon oxide and silicon nitride. 13.The display substrate of claim 12, wherein, The active layer is made of metal oxide. The first gate insulating layer is made of silicon oxide, and the second gate insulating layer is made of silicon nitride. 14.The display substrate of claim 12, wherein, The active layer is made of amorphous silicon. The first gate insulating layer is made of silicon nitride, and the second gate insulating layer is made of silicon oxide. 15.The display substrate of claim 7, wherein, A thickness of the gate electrode is in a range of 2000 angstroms to 5000 angstroms. A thickness of at least one of the first electrode and the second electrode is in a range of 2000 angstroms to 5000 angstroms. A thickness of the active layer is in a range of 1700 angstroms to 2200 angstroms. 16.The display substrate of claim 7, wherein, A minimum width of at least one of the first electrode and the second electrode along a direction in which the first electrode and the second electrode are arranged is in a range of 2.5 micrometers to 3.5 micrometers. 17.The display substrate of claim 7, wherein, The first electrode surrounds at least one side of the second electrode, a normal projection of the first electrode on the substrate covers at least a part of a sidewall of the active layer, and a normal projection of the second electrode on the substrate at least partially overlaps with a normal projection of a middle part of the active layer on the substrate. A distance between a normal projection of a boundary of the recess structure on the substrate and a normal projection of a boundary of the active layer on the substrate is less than a distance between a normal projection of a boundary of the first electrode close to the second electrode on the substrate and a normal projection of a boundary of the active layer on the substrate. A distance between a normal projection of a boundary of the first electrode close to the second electrode on the substrate and a normal projection of a boundary of the active layer on the substrate is greater than a distance between a normal projection of a boundary of the first electrode away from the second electrode on the substrate and a normal projection of a boundary of the gate electrode on the substrate.

18. The display substrate of claim 7, further comprising: A passivation layer; The passivation layer is located on a side of the first electrode and the second electrode away from the substrate.

19. A method for manufacturing a display substrate configured to manufacture the display substrate of any one of claims 1 to 18, the method comprising: forming a gate electrode of a transistor device on a substrate; forming a gate insulating layer of the transistor device on the gate electrode, the gate insulating layer being provided with a recess structure, and the recess structure being located on a side of the gate insulating layer away from the substrate; forming an active layer of the transistor device within the recess structure of the gate insulating layer, at least two boundaries of the active layer having a preset interval with corresponding boundaries of the recess structure.

20. The method of claim 19, wherein, The forming a gate insulating layer of a transistor device on a gate electrode comprises: A gate insulating film is coated on the gate electrode, and a recess structure is formed on the gate insulating film by a patterning process to form a gate insulating layer of the transistor device.

21. The method of claim 19, wherein, The forming of the gate insulating layer of the transistor device on the gate electrode comprises: A first gate insulating film and a second gate insulating film are sequentially coated on the gate electrode, A via hole is formed on the second gate insulating film by a patterning process to form a gate insulating layer of the transistor device, and the recess structure is formed by the via hole and the first gate insulating film.

22. The method of claim 19, wherein, The active layer comprises a first active layer and a second active layer, and the forming of the active layer of the transistor device in the recess structure of the gate insulating layer comprises: A semiconductor film is deposited on the gate insulating layer; The semiconductor film is treated by a hydrogenation process to form a first active layer and a third active layer; A source-drain metal film is deposited on the third active layer, and the source-drain metal film and the third active layer are treated by a patterning process to form a second active layer, a first electrode and a second electrode.

23. The method of claim 19, further comprising: A passivation layer is formed on the first electrode and the second electrode.

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