Display substrate and display device

Abstract

A display substrate and a display device comprising same. The display substrate comprises: a base substrate (10), and a display area (AA) and a non-display area (NA) that are arranged on one side of the base substrate (10). The display area (AA) comprises a plurality of sub-pixels (PX), and each sub-pixel (PX) comprises a thin film transistor (T) and a pixel electrode (EP). The pixel electrode (EP) is connected to the drain (D) of the thin film transistor (T); and the pixel electrode (EP), and the source (S) and the drain (D) of the thin film transistor (T) are arranged in the same layer, i.e., a first conductive layer (11). The active layer (12) of the thin film transistor (T) is separately in direct contact with the source (S) and the drain (D), and the pixel electrode (EP) is used for driving target particles (LZ) to move.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Electronic paper usually adopts electrophoresis display (EPD) as a display panel. Electronic paper display not only has the advantages of comfortable reading, ultra-thin and light, bendable, and the like, like paper, but also can refresh the display content, and has lower power consumption than liquid crystal display.

[0003] SUMMARY

[0004] The present disclosure provides a display substrate, comprising: a substrate substrate, and a display area and a non-display area arranged on one side of the substrate substrate, the display area comprising a plurality of sub-pixels;

[0005] The sub-pixel comprises a thin film transistor and a pixel electrode, the pixel electrode is connected with the drain of the thin film transistor, the pixel electrode, the source and the drain of the thin film transistor are arranged in the same layer on a first conductive layer, the active layer of the thin film transistor is directly connected with the source and the drain, and the pixel electrode is used to drive the movement of target particles.

[0006] In some embodiments, the first conductive layer is located on the side of the active layer away from the substrate substrate;

[0007] The active layer comprises a first channel region and a first connection region, in the orthographic projection on the substrate substrate, the first channel region has an overlap with the gate of the thin film transistor and has no overlap with the first conductive layer, and the first connection region has an overlap with the source and the drain, respectively; and

[0008] The surface of the source and the drain close to the substrate substrate is in contact with the surface of the first connection region away from the substrate substrate.

[0009] In some embodiments, the orthographic projection of the first conductive layer on the substrate substrate is located in the orthographic projection area of the active layer on the substrate substrate.

[0010] In some embodiments, the gate is located on the side of the first conductive layer away from the substrate substrate;

[0011] The active layer further comprises a first conductive region connected between the first channel region and the first connection region, the first conductive region has no overlap with the gate and the first conductive layer in the orthogonal projection on the substrate, and the first conductive region is located between the gate and the source and between the gate and the drain.

[0012] In some embodiments, the first conductive layer is located between the active layer and the substrate;

[0013] The active layer comprises a second channel region and a second connection region, the second channel region has no overlap with the first conductive layer in the orthogonal projection on the substrate, the second connection region has overlap with the source and the drain respectively, and the second channel region and the second connection region are both completely covered by the gate; and

[0014] The surface of the source and the drain facing away from the substrate is in contact with the surface of the second connection region close to the substrate.

[0015] In some embodiments, the first conductive layer is located in the same layer as the active layer.

[0016] In some embodiments, the active layer comprises a third channel region and a second conductive region connected to each other, the third channel region has overlap with the gate, the second conductive region comprises a base material and conductive ions doped in the base material, the base material is the same material as the third channel region, and the first conductive layer is located in the second conductive region.

[0017] In some embodiments, the display area further comprises a data line connected to the source, and the data line is located in the same layer as the pixel electrode.

[0018] In some embodiments, the sub-pixel further comprises a first common electrode located in the same layer as the gate, and the first common electrode has overlap with the pixel electrode in the orthogonal projection on the substrate.

[0019] In some embodiments, the first common electrode is located on the side of the pixel electrode facing away from the substrate, the orthogonal projection of the first common electrode on the substrate is located in the area of the orthogonal projection of the pixel electrode on the substrate, and the ratio of the area of the orthogonal projection of the first common electrode on the substrate to the area of the orthogonal projection of the pixel electrode on the substrate is less than or equal to one half.

[0020] In some embodiments, the pixel further comprises a second common electrode, the second common electrode is disposed out of layer with the gate electrode, the second common electrode has an overlapping area with the pixel electrode in the orthographic projection on the substrate, and the second common electrode is located on the side of the pixel electrode close to the substrate.

[0021] In some embodiments, the orthographic projection of the second common electrode on the substrate covers the substrate entirely.

[0022] In some embodiments, the gate electrode has no overlapping area with the source electrode and the drain electrode in the orthographic projection on the substrate.

[0023] In some embodiments, the gate electrode is located on a second conductive layer, the second conductive layer is located on the side of the active layer away from the substrate; and

[0024] The display substrate further comprises a first gate insulating layer disposed between the second conductive layer and the active layer, the first gate insulating layer covers at least the channel region of the thin film transistor.

[0025] In some embodiments, the orthographic projection patterns of the second conductive layer and the first gate insulating layer on the substrate are the same.

[0026] In some embodiments, the first conductive layer comprises a first transfer pattern, the second conductive layer comprises a second transfer pattern, and the first transfer pattern and the second transfer pattern are connected through a via disposed in the first gate insulating layer.

[0027] In some embodiments, the display substrate further comprises:

[0028] A first passivation layer disposed on the side of the second conductive layer away from the substrate, the first passivation layer at least partially covers the second conductive layer, and the via in the first gate insulating layer and the via in the first passivation layer are in communication with each other.

[0029] In some embodiments, the gate electrode is located on a third conductive layer, the third conductive layer is located on the side of the active layer close to the substrate; and

[0030] The display substrate further comprises a second passivation layer disposed on the side of the active layer away from the substrate, the second passivation layer covers at least the channel region of the thin film transistor.

[0031] The display device includes a counter substrate, an electrophoretic solution, and the display substrate as described in any of the embodiments, the electrophoretic solution is located between the counter substrate and the display substrate, the electrophoretic solution includes target particles, and the pixel electrode is located on the side of the substrate close to the electrophoretic solution.

[0032] In some embodiments, the counter substrate includes:

[0033] a counter substrate, and a counter electrode disposed on the side of the counter substrate close to the electrophoretic solution, the counter electrode and the pixel electrode are used to form an electric field for driving the target particles to move.

[0034] The above description is only a summary of the technical solutions of the present disclosure, in order to enable more clear understanding of the technical means of the present disclosure, and in order to enable the above and other purposes, features and advantages of the present disclosure to be more obvious and easy to understand, the following will be described in detail.

[0035] Brief Description of Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or related art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0037] FIG. 1 exemplarily shows a structural schematic diagram of a first display substrate;

[0038] FIG. 2 exemplarily shows a structural schematic diagram of a second display substrate;

[0039] FIG. 3 exemplarily shows a structural schematic diagram of a third display substrate;

[0040] FIG. 4 exemplarily shows a structural schematic diagram of a fourth display substrate;

[0041] FIG. 5 exemplarily shows a structural schematic diagram of a fifth display substrate;

[0042] FIG. 6 exemplarily shows a structural schematic diagram of a sixth display substrate;

[0043] FIG. 7 exemplarily shows a structural schematic diagram of a seventh display substrate;

[0044] FIG. 8 exemplarily shows a structural schematic diagram of an eighth display substrate;

[0045] FIG. 9 schematically shows a preparation flow of a first display substrate;

[0046] FIG. 10 schematically shows a preparation flow of a second display substrate;

[0047] FIG. 11 schematically shows a preparation flow of a third display substrate;

[0048] FIG. 12 schematically shows a preparation flow of a fourth display substrate;

[0049] FIG. 13 schematically shows a preparation flow of a fifth display substrate;

[0050] FIG. 14 schematically shows a preparation flow of a sixth display substrate;

[0051] FIG. 15 schematically shows a preparation flow of a seventh display substrate;

[0052] FIG. 16 schematically shows a preparation flow of an eighth display substrate;

[0053] FIG. 17 schematically shows a cross-sectional structure of a display device;

[0054] FIG. 18 schematically shows a planar structure of a display device.

[0055] DETAILED DESCRIPTION

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0057] The present disclosure provides a display substrate, as shown in any one of FIGS. 1 to 8, the display substrate comprising: a substrate 10, and a display area AA and a non-display area NA disposed on one side of the substrate 10, the display area AA comprising a plurality of sub-pixels PX.

[0058] For example, as shown in any one of FIGS. 1 to 8, the display area AA comprises scan lines GL extending along a row direction f1 and data lines DL extending along a column direction f2, the scan lines GL and the data lines DL intersecting each other to form the plurality of sub-pixels PX. The plurality of sub-pixels PX are arranged in an array along the row direction f1 and the column direction f2, for example.

[0059] For example, the non-display area NA is located at the periphery of the display area AA.

[0060] As shown in any one of FIGS. 1 to 8, the sub-pixel PX includes a thin film transistor T and a pixel electrode EP connected with the drain D of the thin film transistor T, the pixel electrode EP, the source S and the drain D of the thin film transistor T are arranged in the same layer in the first conductive layer 11, the active layer 12 of the thin film transistor T is directly connected with the source S and the drain D respectively, and the pixel electrode EP is used to drive the target particles to move.

[0061] In the present disclosure, the active layer 12 is directly connected with the source S and the drain D respectively, which means that the connection between the active layer 12 and the source S and the drain D is not through a via. The active layer 12 and the source S or the drain D can be arranged in the same layer and directly connected (as shown in FIGS. 6 or 7), or can be arranged in different layers and directly overlapped (as shown in FIGS. 1 to 5 and 8).

[0062] In the present disclosure, since the pixel electrode EP, the source S and the drain D are arranged in the same layer, the pixel electrode EP, the source S and the drain D can be prepared and formed by using one mask plate in the same patterning process, so as to reduce the number of mask plates, simplify the preparation process and reduce the cost. In addition, since the active layer 12 of the thin film transistor T is directly connected with the source S and the drain D respectively, that is, the connection between the active layer 12 and the source S and the drain D is not through a via, so as to save the mask plate required for the punching process, simplify the preparation process and reduce the cost.

[0063] It should be noted that in FIGS. 1 to 8, a is a schematic diagram of the planar structure of the display substrate, and b is a schematic diagram of the cross-sectional structure of the display substrate.

[0064] Exemplarily, the target particles can be electrophoretic particles, such as two-color particles, three-color particles or four-color particles, etc.; or can be liquid crystal molecules.

[0065] In the present disclosure, the movement of the target particles can refer to the up-down movement (such as movement along the direction perpendicular to the substrate 10) or the left-right movement (such as movement along the direction parallel to the substrate 10) between the two substrates or polar plates, or can refer to the up-down, left-right or front-back deflection of the target particles between the two substrates or polar plates.

[0066] Exemplarily, the pixel electrode EP, the source S and the drain D of the thin film transistor T are arranged in the same layer and have the same material.

[0067] Exemplarily, as shown in any one of FIGS. 1 to 8, the data line DL is connected with the source S, the data line DL and the pixel electrode EP are arranged in the same layer and have the same material, and are both located in the first conductive layer 11.

[0068] Exemplarily, as shown in any one of FIGS. 1 to 8, the data line DL and the source S are in an integrated structure, and the pixel electrode EP and the drain D are in an integrated structure.

[0069] Exemplarily, as shown in any one of FIGS. 1 to 8, the gate G of the thin film transistor T is connected with the scan line GL, and the gate G and the scan line GL are, for example, provided in the same layer and in an integrated structure.

[0070] In a specific implementation, the positional relationship between the first conductive layer 11 and the active layer 12 can have various implementation manners, which are exemplarily described below.

[0071] In a first implementation manner, as shown in any one of FIGS. 1 to 4 and 8, the first conductive layer 11 is located on a side of the active layer 12 away from the substrate 10.

[0072] Exemplarily, as shown in any one of FIGS. 1 to 4 and 8, the active layer 12 includes a first channel region CH1 and a first connection region LJ1, in a projection of the active layer 12 on the substrate 10, the first channel region CH1 has an overlap with the gate G and has no overlap with the first conductive layer 11, and the first connection region LJ1 has an overlap with the source S and the drain D, respectively; and the source S and the drain D are in contact with each other at surfaces of the source S and the drain D close to the substrate 10 and surfaces of the source S and the drain D away from the substrate 10.

[0073] Exemplarily, as shown in any one of FIGS. 1 to 4 and 8, a projection of the first conductive layer 11 on the substrate 10 is located in a projection region of the active layer 12 on the substrate 10.

[0074] In a specific implementation, an SDT process can be used, that is, exposure and development are performed through one gray mask, and then etching is performed to form the first conductive layer 11 and the active layer 12, so that the mask can be further saved, and the process complexity and cost can be reduced.

[0075] Exemplarily, as shown in FIG. 2, the gate G is located on a side of the first conductive layer 11 away from the substrate 10, in this case, the active layer 12 can further include a first conductorization region CD1, the first conductorization region CD1 is connected between the first channel region CH1 and the first connection region LJ1, and in a projection of the active layer 12 on the substrate 10, the first conductorization region CD1 has no overlap with the gate G and the first conductive layer 11, and the first conductorization region CD1 is located between the gate G and the source S and between the gate G and the drain D.

[0076] In a specific implementation, after the gate G is formed, the gate G can be used as a mask to conduct conductorization on the semiconductor material in the first conductorization region CD1 by using a self-alignment process. For example, the conductorization process can use a dry etching device to introduce plasma (such as helium plasma) into the semiconductor material, and can also use an ion implantation device to implant external ions (such as boron ions, phosphorus ions, etc.) into the semiconductor material.

[0077] Exemplarily, as shown in FIG. 2, in the direction in which the source electrode S points to the drain electrode D (i.e. the row direction f1), the first channel region CH1 completely overlaps with the orthogonal projection of the gate electrode G on the substrate base plate 10.

[0078] In the second implementation manner, as shown in FIG. 5, the first conductive layer 11 is located between the active layer 12 and the substrate base plate 10.

[0079] Exemplarily, as shown in FIG. 5, the active layer 12 includes a second channel region CH2 and a second junction region LJ2, in the orthogonal projection on the substrate base plate 10, the second channel region CH2 does not overlap with the first conductive layer 11, the second junction region LJ2 respectively overlaps with the source electrode S and the drain electrode D, and the second channel region CH2 and the second junction region LJ2 are both completely covered by the gate electrode G; and the surface of the source electrode S and the drain electrode D away from the substrate base plate 10 and the surface of the second junction region LJ2 close to the substrate base plate 10 are in contact with each other.

[0080] Since the SDT process needs to avoid the active layer 12 from being corroded by the etching liquid in the process of etching the first conductive layer 11, the material selection of the first conductive layer 11 is limited. In the second implementation manner, the first conductive layer 11 and the active layer 12 do not need to adopt the SDT process, so that the process complexity can be reduced, and the material selection range of the first conductive layer 11 can be expanded.

[0081] In the third implementation manner, as shown in FIG. 6 or FIG. 7, the first conductive layer 11 is arranged in the same layer as the active layer 12.

[0082] Exemplarily, as shown in FIG. 6 or FIG. 7, the active layer 12 includes a third channel region CH3 and a second conductorization region CD2 connected with each other, the third channel region CH3 overlaps with the gate electrode G, the second conductorization region CD2 includes a base material and conductive ions doped in the base material, the base material is the same as the material of the third channel region CH3, and the first conductive layer 11 is located in the second conductorization region CD2. That is, the pixel electrode EP, the source electrode S and the drain electrode D are all located in the second conductorization region CD2.

[0083] Exemplarily, as shown in FIG. 6 or FIG. 7, the gate electrode G is located on the side of the first conductive layer 11 and the active layer 12 away from the substrate base plate 10, in this case, the semiconductor material of the second conductorization region CD2 in the active layer 12 can be conductivized by using a self-alignment process after the gate electrode G is formed, taking the gate electrode G as a mask plate. The conductivization process may, for example, introduce plasma (such as helium plasma) into the semiconductor material by using a dry etching device, or inject external ions (such as boron ions, phosphorus ions, etc.) into the semiconductor material by using an ion implantation device.

[0084] In the third implementation, since the first conductive layer 11 is arranged in the same layer as the active layer 12, i.e., the first conductive layer 11 is a conductorized active layer 12, wiring space can be saved. In addition, the first conductive layer 11 and the active layer 12 do not need to use the SDT process, so the process complexity can be reduced.

[0085] In the second implementation, as shown in FIG. 5, the gate G has a large overlap with the source S and the drain D, respectively, which results in a large parasitic capacitance between the gate G and the source S and the drain D. In the first implementation and the third implementation, the overlap between the gate G and the source S and the drain D is small (as shown in FIGS. 1, 3, 4, and 8) or has no overlap (as shown in FIGS. 2, 6, and 7), so there is no parasitic capacitance or the parasitic capacitance is small between the gate G and the source S and the drain D, thereby reducing power consumption.

[0086] It should be noted that the positional relationship between the first conductive layer 11 and the active layer 12 is not limited to the above three implementations, and the above implementations are only exemplary.

[0087] Exemplarily, the sub-pixel PX further includes a common electrode EC, and the common electrode EC and the pixel electrode EP have a mutual overlap in the orthographic projection on the substrate 10 to form a storage capacitor. In specific implementation, the positional relationship between the common electrode EC and the pixel electrode EP has various implementations, which are exemplarily described below.

[0088] In the first implementation, as shown in any one of FIGS. 1 to 5 and 8, the sub-pixel PX further includes a first common electrode EC1, the first common electrode EC1 is arranged in the same layer as the gate G and has the same material, and the first common electrode EC1 and the pixel electrode EP have an overlap in the orthographic projection on the substrate 10. In this implementation, the common electrode EC is the first common electrode EC1.

[0089] Since the first common electrode EC1 is arranged in the same layer as the gate G and has the same material, the first common electrode EC1 and the gate G can be formed synchronously by using one mask plate in one patterning process, thereby further saving the mask plate and reducing the process complexity and cost.

[0090] Exemplarily, as shown in any one of FIGS. 1 to 5, the first common electrode EC1 arranged in the same layer as the gate G is located on the side of the pixel electrode EP away from the substrate 10, the orthographic projection of the first common electrode EC1 on the substrate 10 is located in the orthographic projection area of the pixel electrode EP on the substrate 10, and the ratio of the orthographic projection area of the first common electrode EC1 on the substrate 10 to the orthographic projection area of the pixel electrode EP on the substrate 10 is less than or equal to one half.

[0091] In a specific implementation, the first common electrode EC1 arranged in the same layer as the gate electrode G can also be located on the side of the pixel electrode EP close to the substrate 10 (as shown in FIG. 8). In this way, the first common electrode EC1 does not block the pixel electrode EP, and the contact area of the pixel electrode EP with the target particles can be increased, thereby increasing the opening area.

[0092] In the second implementation, as shown in FIG. 6 or FIG. 7, the sub-pixel PX further includes a second common electrode EC2 arranged in a layer different from the gate electrode G, the second common electrode EC2 has an overlapping projection on the substrate 10 with the pixel electrode EP, and the second common electrode EC2 is located on the side of the pixel electrode EP close to the substrate 10. In this implementation, the common electrode EC is the second common electrode EC2.

[0093] In this way, the second common electrode EC2 is located on the side of the pixel electrode EP close to the substrate 10, and does not block the pixel electrode EP. The contact area of the pixel electrode EP with the target particles can be increased, thereby increasing the opening area.

[0094] For example, as shown in FIG. 6 or FIG. 7, the entire projection of the second common electrode EC2 on the substrate 10 covers the substrate 10. In this way, the second common electrode EC2 does not need to be patterned, thereby further saving the mask plate.

[0095] It should be noted that the positional relationship between the common electrode EC and the pixel electrode EP is not limited to the above two implementations, and the above implementations are only exemplary.

[0096] In a specific implementation, the positional relationship between the gate electrode G and the active layer 12 has various implementations, which are exemplarily described below.

[0097] In the first implementation, as shown in any one of FIGS. 1 to 7, the gate electrode G is located on the second conductive layer 14, and the second conductive layer 14 is located on the side of the active layer 12 away from the substrate 10. The display substrate further includes a first gate insulating layer 13 arranged between the second conductive layer 14 and the active layer 12, and the first gate insulating layer 13 covers at least the channel region CH1 / CH2 / CH3 of the thin film transistor T. In this implementation, the thin film transistor T is a top gate structure.

[0098] Since the channel region CH1 / CH2 / CH3 is covered and protected by the first gate insulating layer 13, the characteristic stability of the thin film transistor T can be improved.

[0099] For example, as shown in FIGS. 4, 5 or 7, the projection pattern of the second conductive layer 14 and the first gate insulating layer 13 on the substrate 10 is the same.

[0100] In a specific implementation, after the second conductive layer 14 is prepared, the first gate insulating layer 13 can be etched directly using the second conductive layer 14 as a mask plate, thereby further saving a mask plate.

[0101] Exemplarily, as shown in FIG. 1, the first conductive layer 11 includes a first transfer pattern PT1, and the second conductive layer 14 includes a second transfer pattern PT2. The first transfer pattern PT1 and the second transfer pattern PT2 are connected through a via provided in the first gate insulating layer 13. In this way, through the via connection between the first transfer pattern PT1 and the second transfer pattern PT2, the connection between different layers can be realized, thereby simplifying the wiring design and being conducive to saving wiring space.

[0102] Exemplarily, as shown in FIG. 3 or FIG. 6, the display substrate further includes a first passivation layer PVX1 provided on a side of the second conductive layer 14 away from the substrate 10, and the first passivation layer PVX1 at least partially covers the second conductive layer 14, thereby protecting the second conductive layer 14 and improving the stability of the display substrate.

[0103] Exemplarily, as shown in FIG. 3 or FIG. 6, the via in the first gate insulating layer 13 and the via in the first passivation layer PVX1 are in communication with each other.

[0104] In the second implementation, as shown in FIG. 8, the gate G is located on a third conductive layer 81, and the third conductive layer 81 is located on a side of the active layer 12 close to the substrate 10. The display substrate further includes a second passivation layer PVX2 provided on a side of the active layer 12 away from the substrate 10, and the second passivation layer PVX2 at least covers the channel region CH1 / CH2 / CH3 of the thin film transistor T. In this implementation, the thin film transistor T is in a bottom gate structure.

[0105] Since the channel region CH1 / CH2 / CH3 is covered and protected by the second passivation layer PVX2, the characteristic stability of the thin film transistor T can be improved.

[0106] In the present disclosure, the thin film transistor T refers to an element including at least three terminals of a gate G, a drain D, and a source S. The thin film transistor T has a channel region CH1 / CH2 / CH3 between the drain D (a drain D terminal, a drain region, or a drain D) and the source S (a source S terminal, a source region, or a source S), and a current can flow through the drain D, the channel region CH1 / CH2 / CH3, and the source S. In the present disclosure, the channel region CH1 / CH2 / CH3 refers to a region through which a current mainly flows.

[0107] In the present disclosure, the functions of the "source S" and the "drain D" are sometimes exchanged with each other in the case of using a thin film transistor T with opposite polarity or in the case of changing the current direction in the circuit operation. Therefore, in the present disclosure, the "source S" and the "drain D" can be exchanged with each other.

[0108] Exemplarily, the material of the active layer 12 includes an oxide semiconductor material such as IGZO, and can also include amorphous silicon or low-temperature polysilicon, etc., which are not limited in the present disclosure.

[0109] In some embodiments, the channel region CH1 / CH2 / CH3 of the thin film transistor T includes a semiconductor material M1OaNb, where M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents an oxygen element, and N represents a nitrogen element, that is, the semiconductor material is a metal oxide material or a metal oxynitride material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), In-free OS, rare earth doped oxide (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the channel CH can be in an amorphous, partially crystalline, single crystalline, or polycrystalline state, and can also be a single layer or a multi-layer structure.

[0110] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or a combination thereof. In one example, the material of the channel region CH1 / CH2 / CH3 includes indium gallium zinc oxide (IGZO).

[0111] Exemplarily, the first conductive layer 11 can be made of a metal material such as aluminum or copper, and can also be made of a transparent conductive material such as ITO, IZO, IGZO, IGO, ZTO, etc. Using a metal oxide can improve the oxidation resistance of the first conductive layer 11, and meet the requirements of the trace resistance of small-size display substrates (such as electronic price tags, etc.).

[0112] Exemplarily, the second conductive layer 14 and the third conductive layer 81 can adopt metal materials such as aluminum, copper, etc., and can also adopt transparent conductive materials such as ITO, IZO, IGZO, IGO, ZTO, etc. metal oxides. Adopting metal oxides can improve the oxidation resistance of the second conductive layer 14 and the third conductive layer 81, and meet the requirements of small-size display substrates (such as electronic price tags, etc.) on the resistance of the trace.

[0113] In the case of adopting metal materials and existing bare surfaces on the surface away from the substrate 10 of the first conductive layer 11, the second conductive layer 14 or the third conductive layer 81, etc., a protective layer can be coated on the surface of the display substrate away from the substrate 10 of the display substrate, for preventing the oxidation of the metal material in the conductive layer, and the material of the protective layer is, for example, polyimide, etc.

[0114] The display substrate provided by the present disclosure will be exemplarily described below in combination with FIGS. 1-8.

[0115] In a first example, as shown in FIG. 1, the display substrate includes a substrate 10, and an active layer 12, a first conductive layer 11, a first gate insulating layer 13 and a second conductive layer 14 which are sequentially stacked on one side of the substrate 10, the active layer 12 being arranged close to the substrate 10. The display substrate is of a top gate structure.

[0116] The active layer 12 includes a first channel region CH1 and a first connection region LJ1, and the first connection region LJ1 is in contact with the source S and the drain D away from the surface of the substrate 10. The first conductive layer 11 includes a pixel electrode EP, a source S, a drain D and a data line DL. The second conductive layer 14 includes a gate G, a scan line GL connected to the gate G and a first common electrode EC1.

[0117] Referring to FIG. 9, the display substrate provided by the first example can be prepared according to the following steps:

[0118] Step 01: providing a substrate 10;

[0119] Step 02: using an SDT process, exposing and developing through a gray mask, and etching to form a first conductive layer 11 and an active layer 12 on one side of the substrate 10, to obtain a display substrate as shown in FIG. 9a. The orthographic projection of the first conductive layer 11 formed in this way on the substrate 10 is located within the orthographic projection area of the active layer 12 on the substrate 10.

[0120] Step 03: Using a single patterning process, a first gate insulating layer 13 is formed on the side of the first conductive layer 11 facing away from the substrate 10 through a mask, resulting in the display substrate shown in Figure 9b. For example, vias can be formed on the first gate insulating layer 13 so that the first transition pattern PT1 located on the first conductive layer 11 and the second transition pattern PT2 located on the second conductive layer 14 are connected through the vias provided in the first gate insulating layer 13.

[0121] Step 04: Using a single patterning process, a second conductive layer 14 is formed on the side of the first gate insulating layer 13 facing away from the substrate 10 through a mask, to obtain the display substrate shown in Figure 9c.

[0122] In the first example, a three-mask array can be used to form the display substrate. Since the first channel region CH1 is covered and protected by the first gate insulating layer 13, the characteristic stability of the thin-film transistor T can be improved. In addition, the first transition pattern PT1 located on the first conductive layer 11 and the second transition pattern PT2 located on the second conductive layer 14 can be connected by vias provided in the first gate insulating layer 13, which simplifies the wiring design and helps save wiring space.

[0123] In the second example, as shown in Figure 2, the display substrate includes a substrate 10, and an active layer 12, a first conductive layer 11, a first gate insulating layer 13, and a second conductive layer 14 sequentially stacked on one side of the substrate 10. The active layer 12 is disposed close to the substrate 10. This display substrate has a top gate structure.

[0124] The active layer 12 includes a first channel region CH1, a first conductive region CD1, and a first connection region LJ1, with the first conductive region CD1 connected between the first channel region CH1 and the first connection region LJ1. In the orthographic projection onto the substrate 10, the first conductive region CD1 does not overlap with the gate G or the first conductive layer 11, and is located between the gate G and the source S, and between the gate G and the drain D. The surface of the first connection region LJ1 facing away from the substrate 10 is in contact with the surfaces of the source S and the drain D near the substrate 10. The first conductive layer 11 includes a pixel electrode EP, a source S, a drain D, and a data line DL. The second conductive layer 14 includes a gate G, a scan line GL connected to the gate G, and a first common electrode EC1.

[0125] Referring to Figure 10, the display substrate provided in the second example can be prepared according to the following steps:

[0126] Step 11: Provide substrate 10;

[0127] Step 12: Using the SDT process, exposure and development are performed through a grayscale mask to sequentially etch and form a first conductive layer 11 and an active layer 12 on one side of the substrate 10, resulting in the display substrate shown in Figure 10a. The orthographic projection of the first conductive layer 11 on the substrate 10 is located within the orthographic projection area of ​​the active layer 12 on the substrate 10.

[0128] Step 13: Using a single patterning process, a first gate insulating layer 13 is formed on the side of the first conductive layer 11 facing away from the substrate 10 through a mask, resulting in the display substrate shown in Figure 10b. For example, vias can be formed on the first gate insulating layer 13 so that the first transition pattern PT1 located on the first conductive layer 11 and the second transition pattern PT2 located on the second conductive layer 14 are connected through the vias provided in the first gate insulating layer 13.

[0129] Step 14: Using a single patterning process, a second conductive layer 14 is formed on the side of the first gate insulating layer 13 facing away from the substrate 10 through a mask. In the orthographic projection of the second conductive layer 14 onto the substrate 10, the gate G has no overlap with the source S and the drain D, and there are gaps between them. Then, using the gate G as a mask, a self-aligned process is used to conduct the semiconductor material at the gaps, resulting in the display substrate shown in Figure 10c. The semiconductor region after conduction is the first conductor region CD1. As shown in Figure 10c, in the direction from the source S to the drain D (i.e., in the row direction f1), the first channel region CH1 completely overlaps with the orthographic projection of the gate G onto the substrate 10.

[0130] In the second example, a three-mask array can be used to form the display substrate. Since the first channel region CH1 is covered and protected by the first gate insulating layer 13, the characteristic stability of the thin-film transistor T can be improved. Furthermore, the first transition pattern PT1 located in the first conductive layer 11 and the second transition pattern PT2 located in the second conductive layer 14 can be connected through vias provided in the first gate insulating layer 13, simplifying wiring design and saving wiring space. The gate G does not overlap with the source S and drain D, thereby reducing the parasitic capacitance between the gate G and the source S and drain D, which helps to reduce power consumption.

[0131] In the third example, as shown in Figure 3, the display substrate includes a substrate 10, and an active layer 12, a first conductive layer 11, a first gate insulating layer 13, a second conductive layer 14, and a first passivation layer PVX1 sequentially stacked on one side of the substrate 10. The active layer 12 is disposed close to the substrate 10. This display substrate has a top-gate structure.

[0132] The active layer 12 includes a first channel region CH1 and a first connection region LJ1. The surface of the first connection region LJ1 facing away from the substrate 10 is in contact with the surfaces of the source electrode S and the drain electrode D near the substrate 10. The first conductive layer 11 includes a pixel electrode EP, a source electrode S, a drain electrode D, and a data line DL. The second conductive layer 14 includes a gate electrode G, a scan line GL connected to the gate electrode G, and a first common electrode EC1.

[0133] Referring to Figure 11, the display substrate provided in the third example can be prepared according to the following steps:

[0134] Step 21: Provide substrate 10;

[0135] Step 22: Using the SDT process, exposure and development are performed through a grayscale mask to sequentially etch and form a first conductive layer 11 and an active layer 12 on one side of the substrate 10, resulting in the display substrate shown in Figure 11a. The orthographic projection of the first conductive layer 11 on the substrate 10 is located within the orthographic projection area of ​​the active layer 12 on the substrate 10.

[0136] Step 23: Cover the entire side of the first conductive layer 11 away from the substrate 10 with the material of the first gate insulating layer 13. Then, use a single patterning process to form the second conductive layer 14 on the side of the first gate insulating layer 13 away from the substrate 10 through a mask, to obtain the display substrate shown in Figure 11b.

[0137] Step 24: Using a single patterning process, a first passivation layer PVX1 is formed on the side of the second conductive layer 14 facing away from the substrate 10 through a mask, resulting in the display substrate shown in Figure 11c. Specifically, vias can be formed on the first passivation layer PVX1 to remove the insulating layer on the bonding terminals located in the non-display area NA. For example, if the bonding terminals are located on the second conductive layer 14, the first passivation layer PVX1 on the bonding terminals needs to be removed. If the bonding terminals are located on the first conductive layer 11, the first passivation layer PVX1 and the first gate insulating layer 13 on the bonding terminals need to be removed. Therefore, the vias in the first gate insulating layer 13 are interconnected with the vias in the first passivation layer PVX1.

[0138] In the third example, a three-mask array can be used to form the display substrate. Since the first channel region CH1 is covered and protected by the first gate insulating layer 13, the characteristic stability of the thin-film transistor T can be improved. Because the first passivation layer PVX1 at least partially covers the second conductive layer 14, the second conductive layer 14 can be protected, thereby improving the stability of the display substrate.

[0139] Furthermore, the pattern located in the first conductive layer 11 and the pattern located in the second conductive layer 14 cannot be connected through vias provided in the first gate insulating layer 13, which may increase the difficulty of wiring design. To reduce the difficulty of wiring design, a conductive layer can be added to the side of the first passivation layer PVX1 facing away from the substrate 10, so that the pattern in the conductive layer can be connected to the pattern in the second conductive layer 14 or the first conductive layer 11 through vias, thereby realizing the bridging between different layers.

[0140] The display substrate prepared according to the steps shown in Figure 11 has an overlap between the gate G and the source S and the drain D, respectively. Therefore, there is a parasitic capacitance between the gate G and the source S and the drain D.

[0141] To reduce parasitic capacitance between the gate G and the source S and drain D, in a specific implementation, a second conductive layer 14 can be formed in step 24 such that, in the orthographic projection on the substrate 10, the gate G does not overlap with the source S and drain D, and gaps exist between them. After step 24 and before step 25, using the gate G as a mask, a self-aligned process is used to conduct the active layer 12 at the gaps, thereby forming a first conductive region CD1 between the first channel region CH1 and the first connection region LJ1. In this way, the gate G does not overlap with the source S and drain D, thereby reducing the parasitic capacitance between the gate G and the source S and drain D, which is beneficial for reducing power consumption.

[0142] In the fourth example, as shown in Figure 4, the display substrate includes a substrate 10, and an active layer 12, a first conductive layer 11, a first gate insulating layer 13, and a second conductive layer 14 sequentially stacked on one side of the substrate 10. The active layer 12 is disposed close to the substrate 10. This display substrate has a top gate structure.

[0143] The active layer 12 includes a first channel region CH1 and a first connection region LJ1. The surface of the first connection region LJ1 facing away from the substrate 10 is in contact with the surfaces of the source electrode S and the drain electrode D near the substrate 10. The first conductive layer 11 includes a pixel electrode EP, a source electrode S, a drain electrode D, and a data line DL. The second conductive layer 14 includes a gate electrode G, a scan line GL connected to the gate electrode G, and a first common electrode EC1.

[0144] Referring to Figure 12, the display substrate provided in the fourth example can be prepared according to the following steps:

[0145] Step 31: Provide substrate 10;

[0146] Step 32: Using the SDT process, exposure and development are performed through a grayscale mask to sequentially etch and form a first conductive layer 11 and an active layer 12 on one side of the substrate 10, resulting in the display substrate shown in Figure 12a. The orthographic projection of the first conductive layer 11 on the substrate 10 is located within the orthographic projection area of ​​the active layer 12 on the substrate 10.

[0147] Step 33: Cover the entire side of the first conductive layer 11 away from the substrate 10 with the material of the first gate insulating layer 13. Then, using a single patterning process, form the second conductive layer 14 on the side of the first gate insulating layer 13 away from the substrate 10 through a mask. Then, using the second conductive layer 14 as a mask, etch the material of the first gate insulating layer 13 to form a first gate insulating layer 13 with the same pattern as the second conductive layer 14, resulting in the display substrate shown in Figure 12b.

[0148] In the fourth example, a two-mask fabrication process can be used, reducing the number of masks required, simplifying the process, and lowering costs. Since the first channel region CH1 is covered and protected by the first gate insulating layer 13, the characteristic stability of the thin-film transistor T can be improved.

[0149] When the second conductive layer 14 is made of a metallic material, polyimide can be coated on the surface of the second conductive layer 14 facing away from the substrate 10, for example, to prevent oxidation of the metallic material in the conductive layer and to protect the second conductive layer 14 from oxidation.

[0150] In the fifth example, as shown in Figure 5, the display substrate includes a substrate 10, and a first conductive layer 11, an active layer 12, a first gate insulating layer 13, and a second conductive layer 14 sequentially stacked on one side of the substrate 10, with the active layer 12 disposed close to the substrate 10. This display substrate has a top-gate structure.

[0151] The active layer 12 includes a second channel region CH2 and a second connection region LJ2, both of which are completely covered by the gate G. Furthermore, the surfaces of the source S and drain D facing away from the substrate 10 are in contact with the surface of the second connection region LJ2 near the substrate 10. The first conductive layer 11 includes a pixel electrode EP, a source S, a drain D, and a data line DL. The second conductive layer 14 includes a gate G, a scan line GL connected to the gate G, and a first common electrode EC1.

[0152] Referring to Figure 13, the display substrate provided in the fifth example can be prepared according to the following steps:

[0153] Step 41: Provide substrate 10;

[0154] Step 42: Using a single patterning process, a first conductive layer 11 is formed on one side of the substrate 10 through a mask, resulting in a display substrate as shown in Figure 13a.

[0155] Step 43: Using a single patterning process, an active layer 12 is formed on the side of the first conductive layer 11 away from the substrate 10 through a mask, resulting in the display substrate shown in Figure 13b.

[0156] Step 44: Cover the entire side of the active layer 12 away from the substrate 10 with the material of the first gate insulating layer 13. Then, using a single patterning process, form the second conductive layer 14 on the side of the first gate insulating layer 13 material away from the substrate 10 through a mask. Then, using the second conductive layer 14 as a mask, etch the first gate insulating layer 13 material to form a first gate insulating layer 13 with the same pattern as the second conductive layer 14, resulting in the display substrate shown in Figure 13c.

[0157] In the fifth example, a three-mask process can be used to fabricate the display substrate. Since the second channel region CH2 is covered and protected by the first gate insulating layer 13, the characteristic stability of the thin-film transistor T can be improved. Because the first conductive layer 11 and the active layer 12 do not require SDT (Surface Mount Technology) processing, the process complexity can be reduced, and the range of materials that can be selected for the first conductive layer 11 can be expanded.

[0158] When the second conductive layer 14 is made of a metallic material, polyimide can be coated on the surface of the second conductive layer 14 facing away from the substrate 10, for example, to prevent oxidation of the metallic material in the conductive layer and to protect the second conductive layer 14 from oxidation.

[0159] In the sixth example, as shown in Figure 6, the display substrate includes a substrate 10, and a second common electrode EC2, a buffer layer, an active layer 12 (including a first conductive layer 11), a first gate insulating layer 13, a second conductive layer 14, and a first passivation layer PVX1, which are sequentially stacked on one side of the substrate 10. The second common electrode EC2 is disposed close to the substrate 10. This display substrate has a top gate structure.

[0160] The active layer 12 includes an interconnected third channel region CH3 and a second conductive region CD2. The third channel region CH3 overlaps with the gate G. The second conductive region CD2 includes a substrate and conductive ions doped in the substrate. The substrate is made of the same material as the third channel region CH3. The first conductive layer 11 is located within the second conductive region CD2. The second conductive region CD2 includes a pixel electrode EP, a source electrode S, a drain electrode D, and a data line DL. The second conductive layer 14 includes a gate G and a scan line GL connected to the gate G.

[0161] Referring to Figure 14, the display substrate provided in the sixth example can be prepared according to the following steps:

[0162] Step 50: Provide substrate 10;

[0163] Step 51: A second common electrode EC2 and a buffer layer are sequentially formed on one side of the substrate 10, covering the entire surface of the substrate 10. Then, using a single patterning process, an active layer 12 is formed on the side of the buffer layer opposite to the substrate 10 through a mask, resulting in the display substrate shown in Figure 14a.

[0164] Step 52: The material of the first gate insulating layer 13 is fully covered on the side of the active layer 12 facing away from the substrate 10. Then, using a single patterning process, a second conductive layer 14 is formed on the side of the first gate insulating layer 13 material facing away from the substrate 10 through a mask. Then, using the second conductive layer 14 as a mask, a self-aligned process is used to conduct the semiconductor material of the second conductive region CD2 in the active layer 12, resulting in the display substrate shown in Figure 14b.

[0165] Step 53: Using a single patterning process, a first passivation layer PVX1 is formed on the side of the second conductive layer 14 facing away from the substrate 10 through a mask, resulting in the display substrate shown in Figure 14c. Specifically, vias can be formed on the first passivation layer PVX1 to remove the insulating layer on the bonding terminals located in the non-display area NA. For example, if the bonding terminals are located on the second conductive layer 14, the first passivation layer PVX1 on the bonding terminals needs to be removed. If the bonding terminals are located on the active layer 12, the first passivation layer PVX1 and the first gate insulating layer 13 on the bonding terminals need to be removed. Therefore, the vias in the first gate insulating layer 13 are interconnected with the vias in the first passivation layer PVX1.

[0166] In the sixth example, a three-mask formation can be used to form the display substrate. Since the third channel region CH3 is covered and protected by the first gate insulating layer 13, the characteristic stability of the thin-film transistor T can be improved. Because the first passivation layer PVX1 at least partially covers the second conductive layer 14, the second conductive layer 14 can be protected, thereby improving the stability of the display substrate.

[0167] Since the gate G does not overlap with the source S and drain D respectively, the parasitic capacitance between the gate G and the source S and drain D can be reduced, which helps to reduce power consumption.

[0168] Since the first conductive layer 11 and the active layer 12 are disposed on the same layer, that is, the first conductive layer 11 is a conductive active layer 12, wiring space can be saved. The first conductive layer 11 and the active layer 12 do not need to use SDT process, thus reducing process complexity.

[0169] Since the second common electrode EC2 is located on the side of the pixel electrode EP closest to the substrate 10, it will not block the pixel electrode EP, thereby increasing the contact area between the pixel electrode EP and the target particles, and thus increasing the opening area.

[0170] In the sixth example, the pattern located in the first conductive layer 11 and the pattern located in the second conductive layer 14 cannot be connected through vias provided in the first gate insulating layer 13, which may increase the difficulty of wiring design. To reduce the difficulty of wiring design, a conductive layer can also be added to the side of the first passivation layer PVX1 away from the substrate 10, so that the pattern in the conductive layer can be connected to the pattern in the second conductive layer 14, the active layer 12 or the second common electrode EC2 through vias, thereby realizing the bridging between different layers.

[0171] In the seventh example, as shown in Figure 7, the display substrate includes a substrate 10, and a second common electrode EC2, a buffer layer, an active layer 12 (including a first conductive layer 11), a first gate insulating layer 13, a second conductive layer 14, and a first passivation layer PVX1, which are sequentially stacked on one side of the substrate 10. The second common electrode EC2 is disposed close to the substrate 10. This display substrate has a top gate structure.

[0172] The active layer 12 includes an interconnected third channel region CH3 and a second conductive region CD2. The third channel region CH3 overlaps with the gate G. The second conductive region CD2 includes a substrate and conductive ions doped in the substrate. The substrate is made of the same material as the third channel region CH3. The first conductive layer 11 is located within the second conductive region CD2. The second conductive region CD2 includes a pixel electrode EP, a source electrode S, a drain electrode D, and a data line DL. The second conductive layer 14 includes a gate G and a scan line GL connected to the gate G.

[0173] Referring to Figure 15, the display substrate provided in the seventh example can be prepared according to the following steps:

[0174] Step 60: Provide substrate 10;

[0175] Step 61: A second common electrode EC2 and a buffer layer are sequentially formed on one side of the substrate 10, covering the entire surface of the substrate 10. Then, using a single patterning process, an active layer 12 is formed on the side of the buffer layer opposite to the substrate 10 through a mask, resulting in the display substrate shown in Figure 15a.

[0176] Step 62: The material of the first gate insulating layer 13 is fully covered on the side of the active layer 12 facing away from the substrate 10. Then, using a single patterning process and a mask, a second conductive layer 14 is formed on the side of the first gate insulating layer 13 material facing away from the substrate 10. Next, using the second conductive layer 14 as a mask, the first gate insulating layer 13 material is etched to form a first gate insulating layer 13 with the same pattern as the second conductive layer 14. Then, using the second conductive layer 14 as a mask again, a self-aligned process is used to conduct the semiconductor material in the second conductive region CD2 of the active layer 12, resulting in the display substrate shown in Figure 15b.

[0177] Step 63: Using a single patterning process, a first passivation layer PVX1 is formed on the side of the second conductive layer 14 facing away from the substrate 10 through a mask, resulting in the display substrate shown in Figure 15c. Specifically, vias can be formed on the first passivation layer PVX1 to remove the first passivation layer PVX1 located on the bonding terminals of the non-display area NA.

[0178] In this example, the conductor formation process can be performed simultaneously with the dry etching process of the first gate insulating layer 13 or the film formation process of the first passivation layer PVX1, thereby simplifying the process. For example, the active layer 12 can be subjected to He / H plasma treatment during the etching of the first gate insulating layer 13, or the active layer 12 can be subjected to He / H plasma treatment during the film formation process of the first passivation layer PVX1 after the etching of the first gate insulating layer 13 is completed.

[0179] In the seventh example, a display substrate can be formed using three photomasks. Since the third channel region CH3 is covered and protected by the first gate insulating layer 13, the characteristic stability of the thin-film transistor T can be improved. Because the first passivation layer PVX1 at least partially covers the second conductive layer 14, the second conductive layer 14 can be protected, thereby improving the stability of the display substrate.

[0180] Since the gate G does not overlap with the source S and drain D respectively, the parasitic capacitance between the gate G and the source S and drain D can be reduced, which helps to reduce power consumption.

[0181] Since the first conductive layer 11 and the active layer 12 are disposed on the same layer, that is, the first conductive layer 11 is a conductive active layer 12, wiring space can be saved. The first conductive layer 11 and the active layer 12 do not need to use SDT process, thus reducing process complexity.

[0182] Since the second common electrode EC2 is located on the side of the pixel electrode EP closest to the substrate 10, it will not block the pixel electrode EP, thereby increasing the contact area between the pixel electrode EP and the target particles, and thus increasing the opening area.

[0183] In the seventh example, the pattern located in the first conductive layer 11 and the pattern located in the second conductive layer 14 cannot be connected through vias provided in the first gate insulating layer 13, which may increase the difficulty of wiring design. To reduce the difficulty of wiring design, a conductive layer can also be added to the side of the first passivation layer PVX1 away from the substrate 10, so that the pattern in the conductive layer can be connected to the pattern in the second conductive layer 14, the active layer 12 or the second common electrode EC2 through vias, thereby realizing the bridging between different layers.

[0184] In the eighth example, as shown in Figure 8, the display substrate includes a substrate 10, and a third conductive layer 81, a second gate insulating layer 82, an active layer 12, a first conductive layer 11, and a second passivation layer PVX2 sequentially stacked on one side of the substrate 10. The third conductive layer 81 is disposed close to the substrate 10. This display substrate has a bottom gate structure.

[0185] The third conductive layer 81 includes a gate G, a scan line GL connected to the gate G, and a first common electrode EC1. The active layer 12 includes a first channel region CH1 and a first connection region LJ1. The surface of the first connection region LJ1 facing away from the substrate 10 is in contact with the surfaces of the source electrode S and the drain electrode D near the substrate 10. The first conductive layer 11 includes a pixel electrode EP, a source electrode S, a drain electrode D, and a data line DL.

[0186] Referring to Figure 16, the display substrate provided in the eighth example can be prepared according to the following steps:

[0187] Step 71: Provide substrate 10;

[0188] Step 72: Using a single patterning process, a third conductive layer 81 is formed on one side of the substrate 10 through a mask, resulting in the display substrate shown in Figure 16a.

[0189] Step 73: A second gate insulating layer 82 is formed on the entire surface of the third conductive layer 81 facing away from the substrate 10. Then, using an SDT process, exposure and development are performed through a grayscale mask. On the side of the second gate insulating layer 82 facing away from the substrate 10, a first conductive layer 11 and an active layer 12 are sequentially etched to obtain the display substrate shown in Figure 16b. The orthographic projection of the first conductive layer 11 onto the substrate 10 thus formed lies within the orthographic projection area of ​​the active layer 12 onto the substrate 10.

[0190] Step 74: Using a single patterning process, a second passivation layer PVX2 is formed on the side of the first conductive layer 11 away from the substrate 10 through a mask, to obtain the display substrate shown in Figure 16c.

[0191] In the eighth example, a three-mask array can be used to form the display substrate. Since the first channel region CH1 is covered and protected by the second passivation layer PVX2, the characteristic stability of the thin-film transistor T can be improved. Because the first common electrode EC1 is located on the side of the pixel electrode EP closest to the substrate 10, it does not obstruct the pixel electrode EP, thus increasing the contact area between the pixel electrode EP and the target particles, thereby increasing the opening area.

[0192] In the eighth example, the pattern located in the third conductive layer 81 cannot be connected to the pattern located in the first conductive layer 11 through a via disposed in the second gate insulating layer 82, which may increase the difficulty of wiring design. To reduce the difficulty of wiring design, a conductive layer can also be added to the side of the second passivation layer PVX2 away from the substrate 10, so that the pattern in the conductive layer can be connected to the pattern in the first conductive layer 11, the active layer 12 or the third conductive layer 81 through a via, thereby realizing the bridging between different layers.

[0193] This disclosure provides a display device, as shown in FIG17. The display device includes a counter substrate 171, an electrophoretic solution 172, and a display substrate 173 as provided in any embodiment. The electrophoretic solution 172 is located between the counter substrate 171 and the display substrate 173. The electrophoretic solution 172 includes target particles LZ. The pixel electrode EP is located on the side of the substrate 10 near the electrophoretic solution 172.

[0194] Those skilled in the art will understand that the display device provided in this disclosure has the advantages of the display substrate 173 described above.

[0195] The display devices disclosed herein can be: electronic paper, electronic price tags, electronic name tags, display modules, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, in-vehicle display devices, smartwatches, fitness wristbands, personal digital assistants, and any other products or components with display functions.

[0196] For example, the counter substrate 171 includes: a counter substrate 1711, and a counter electrode 1712 disposed on the side of the counter substrate 1711 near the electrophoretic solution 172. The counter electrode 1712 and the pixel electrode EP are used to form an electric field that drives the target particle LZ to move.

[0197] For example, the electrophoresis solution 172 can be an electronic paper membrane.

[0198] For example, as shown in FIG18, the display device may further include a driver chip IC bonded to the non-display area NA of the display substrate 173, and the driver chip IC is connected to the driver circuit board 182 via the flexible circuit board 181.

[0199] During the display process, the driver chip IC can be activated by the driver circuit board 182. The driver chip IC inputs the scan signal to the scan line GL and the data signal to the data line DL, turns on the thin film transistor T, and the pixel electrode EP of the sub-pixel PX obtains the voltage required for the image. It forms a voltage difference with the upper counter electrode 1712, thereby separating the white particles and black particles in the electrophoresis solution 172, and thus forming different display grayscale states.

[0200] In this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0201] In this disclosure, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0202] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0203] In this disclosure, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly specified. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," both including the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0204] The use of “for” or “configured to” in this disclosure implies an open and inclusive language that does not preclude applicability to or configuration to devices for performing additional tasks or steps.

[0205] As used in this disclosure, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0206] As used in this disclosure, "parallel," "perpendicular," "equal," and "flush" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, within 10° or 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, within 10° or 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein an acceptable deviation range for approximate flush may be, for example, a distance between the flushes being less than or equal to 5% of either one's dimension.

[0207] It should be understood that when a layer or element is referred to as being disposed on one side of another layer or substrate, it may be that the layer or element is directly disposed on the other layer or substrate, or it may be that there is an intermediate layer between the layer or element and the other layer or substrate.

[0208] This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown in this disclosure, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0209] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

A display substrate, comprising: A substrate, and a display area and a non-display area disposed on one side of the substrate, the display area comprising a plurality of sub-pixels; The sub-pixel comprises a thin film transistor and a pixel electrode, the pixel electrode is connected with the drain of the thin film transistor, the pixel electrode, the source and the drain of the thin film transistor are disposed in the same layer of a first conductive layer, the active layer of the thin film transistor is directly connected with the source and the drain respectively, and the pixel electrode is used to drive the movement of target particles. The display substrate according to claim 1, wherein The first conductive layer is located on the side of the active layer away from the substrate. The active layer comprises a first channel region and a first connection region, in the orthographic projection on the substrate, the first channel region overlaps with the gate of the thin film transistor and does not overlap with the first conductive layer, and the first connection region overlaps with the source and the drain respectively; and The surface of the source and the drain close to the substrate is in contact with the surface of the first connection region away from the substrate. The display substrate according to claim 2, wherein The orthographic projection of the first conductive layer on the substrate is located in the orthographic projection area of the active layer on the substrate. The display substrate according to claim 2, wherein The gate is located on the side of the first conductive layer away from the substrate. The active layer further comprises a first conductorization region, the first conductorization region is connected between the first channel region and the first connection region, in the orthographic projection on the substrate, the first conductorization region does not overlap with the gate and the first conductive layer, and the first conductorization region is located between the gate and the source and between the gate and the drain. The display substrate according to claim 1, wherein The first conductive layer is located between the active layer and the substrate. The active layer comprises a second channel region and a second connection region, in the orthographic projection on the substrate, the second channel region does not overlap with the first conductive layer, the second connection region overlaps with the source and the drain respectively, and the second channel region and the second connection region are completely covered by the gate; and The surface of the source and the drain away from the substrate is in contact with the surface of the second connection region close to the substrate. The display substrate according to claim 1, wherein The first conductive layer is disposed in the same layer as the active layer. The display substrate according to claim 6, wherein The active layer comprises a third channel region and a second conductorization region connected with each other, the third channel region overlaps with the gate, the second conductorization region comprises a base material and conductive ions doped in the base material, the base material is the same material as the third channel region, and the first conductive layer is located in the second conductorization region. The display substrate according to claim 1, wherein The display area further comprises a data line, the data line is connected with the source, and the data line is disposed in the same layer as the pixel electrode. The display substrate according to claim 1, wherein The sub-pixel further comprises a first common electrode, the first common electrode is disposed in the same layer as the gate, and the orthographic projection of the first common electrode and the pixel electrode on the substrate overlaps. The display substrate according to claim 9, wherein The first common electrode is located on a side of the pixel electrode facing away from the substrate, a projection of the first common electrode on the substrate is located within a projection area of the pixel electrode on the substrate, and a ratio of a projection area of the first common electrode on the substrate to a projection area of the pixel electrode on the substrate is less than or equal to one half. The display substrate according to claim 1, wherein The pixel further includes a second common electrode, the second common electrode is located on a side of the pixel electrode close to the substrate, and a projection of the second common electrode on the substrate overlaps with a projection of the pixel electrode on the substrate. The display substrate according to claim 11, wherein The second common electrode entirely covers the substrate in a projection on the substrate. The display substrate according to claim 4 or 7, wherein The gate electrode does not overlap with the source electrode and the drain electrode in a projection on the substrate. The display substrate according to any one of claims 1 to 12, wherein The gate electrode is located on a second conductive layer, the second conductive layer is located on a side of the active layer facing away from the substrate. The display substrate further includes a first gate insulating layer located between the second conductive layer and the active layer, the first gate insulating layer at least covers a channel region of the thin film transistor. The second conductive layer and the first gate insulating layer have the same pattern in a projection on the substrate. The display substrate according to claim 14, wherein The first conductive layer includes a first transfer pattern, the second conductive layer includes a second transfer pattern, and the first transfer pattern and the second transfer pattern are connected through a via in the first gate insulating layer. The display substrate according to claim 14, wherein The display substrate further includes: The display substrate according to claim 14, wherein A first passivation layer located on a side of the second conductive layer facing away from the substrate, the first passivation layer at least partially covers the second conductive layer, and a via in the first gate insulating layer and a via in the first passivation layer are in communication with each other. The gate electrode is located on a third conductive layer, the third conductive layer is located on a side of the active layer close to the substrate. The display substrate according to any one of claims 1 to 12, wherein The display substrate further includes a second passivation layer located on a side of the active layer facing away from the substrate, the second passivation layer at least covers a channel region of the thin film transistor. The display substrate as claimed in any one of claims 1 to 18, an electrophoretic solution located between the counter substrate and the display substrate, the electrophoretic solution including target particles, and the pixel electrode is located on a side of the substrate close to the electrophoretic solution. The counter substrate includes: A display device comprising: A counter substrate and a counter electrode located on a side of the counter substrate close to the electrophoretic solution, the counter electrode and the pixel electrode are used to form an electric field for driving the target particles to move. The display device according to claim 19, wherein ​ ​

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