Shift register unit, driving circuit, and display device

Abstract

Provided are a shift register unit, a driving circuit, and a display device. The shift register unit comprises a first sub-shift register unit and a second sub-shift register unit; in the first sub-shift register unit, a first reset circuit (01) and a first control circuit (03) are connected to a first control node (OFF<N>), and the first control circuit (03) is connected between the first control node (OFF<N>) and a first reset signal end (VGL1); the first reset circuit (01) and the first control circuit (03) respectively respond to a first control signal and a second control signal, and use a first reset signal (VGL1) from the first reset signal end (VGL1) to reset a first node (Q<N>); in the second sub-shift register unit, a second reset circuit (02) is connected to a second control node (OFF<N+1>), the second control node (OFF<N+1>) is connected to the first control node (OFF<N>), and the second reset circuit (02) is configured to reset, in response to a third control signal, a third node (Q<N+1>) by using the first reset signal (VGL1) that is transmitted to the second control node (OFF<N+1>) by means of the first control node (OFF<N>).

Description

Shift register unit, drive circuit and display device Technical Field

[0001] This disclosure relates to a shift register unit, a driving circuit, and a display device. Background Technology

[0002] In the field of display technology, pixel arrays typically consist of multiple rows of gate lines and multiple columns of intersecting data lines. Driving the gate lines can be achieved through attached integrated driver circuits. In recent years, with the continuous improvement of amorphous silicon thin-film technology, it has become possible to directly integrate the gate line driving circuit onto the thin-film transistor array substrate to form a GOA (Gate driver on Array) for driving the gate lines.

[0003] For example, a GOA consisting of multiple cascaded shift register units can be used to provide switching voltage signals to multiple rows of gate lines in the pixel array, thereby controlling the multiple rows of gate lines to open sequentially, and providing data signals to the pixel units of the corresponding rows in the pixel array through data lines to form the grayscale voltage required for each grayscale level of the displayed image, and thus displaying each frame of the image.

[0004] Summary of the Invention

[0005] At least one embodiment of this disclosure provides a shift register unit, which includes: a first sub-shift register unit and a second sub-shift register unit. The first sub-shift register unit includes: a first input circuit, a first output reset circuit, a first reset circuit, a first output circuit, and a first control circuit; the first input circuit is configured to input a first input signal to a first node in response to a first input control signal; the first output reset circuit is configured to reset a first output terminal under the control of a second node; the first output circuit is configured to output a first clock signal to the first output terminal under the control of the first node; the first reset circuit and the first control circuit are connected to a first control node, and the first control circuit is connected between the first control node and a first reset signal terminal; the first reset circuit and the first control circuit are configured to respond to the first control signal and the second control signal respectively using a first clock signal from the first reset signal terminal. A reset signal resets the first node; the second sub-shift register unit includes: a second input circuit, a second output reset circuit, a second reset circuit, and a second output circuit; the second input circuit is configured to input the first input signal to the third node in response to a second input control signal; the second output reset circuit is configured to reset the second output terminal under the control of the fourth node; the second output circuit is configured to output a second clock signal to the second output terminal under the control of the fourth node; the second reset circuit is connected to a second control node, the second control node is connected to the first control node, and the second reset circuit is configured to reset the third node in response to a third control signal using the first reset signal transmitted from the first control node to the second control node.

[0006] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first reset circuit includes a first reset sub-circuit, the control terminal of the first reset sub-circuit is connected to the second node, the first terminal of the first reset sub-circuit is connected to the first node, the second terminal of the first reset sub-circuit is connected to the first control node, and the first reset sub-circuit is configured to reset the first node under the control of the second node using the first reset signal from the first control node, wherein the first control signal includes the signal of the second node; the second reset circuit includes a second reset sub-circuit, the control terminal of the second reset sub-circuit is connected to the fourth node, the first terminal of the second reset sub-circuit is connected to the third node, the second terminal of the second reset sub-circuit is connected to the second control node, and the second reset sub-circuit is configured to reset the third node under the control of the fourth node using the first reset signal transmitted from the first control node to the second control node.

[0007] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first reset circuit further includes a third reset sub-circuit. The driving terminal of the third reset sub-circuit is connected to a first reset control terminal to receive a first reset control signal. The first control signal includes the first reset control signal. A first terminal of the third reset sub-circuit is connected to the first node, and a second terminal of the third reset sub-circuit is connected to the first control node. The third reset sub-circuit is configured to reset the first node in response to the first reset control signal using the first reset signal from the first reset signal terminal. The second reset circuit further includes a fourth reset sub-circuit. The control terminal of the fourth reset sub-circuit is connected to a second reset control terminal to receive a second reset control signal. The third control signal includes the second reset control signal. A first terminal of the fourth reset sub-circuit is connected to the third node, and a second terminal of the fourth reset sub-circuit is connected to the third control node. The fourth reset sub-circuit is configured to reset the third node in response to the second reset control signal using the first reset signal transmitted from the first control node to the second control node.

[0008] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first control circuit includes a first control sub-circuit, the control terminal of the first control sub-circuit is connected to an auxiliary control terminal to receive an auxiliary control signal, the second control signal includes the auxiliary control signal, the first terminal of the first control circuit is connected to the first control node, and the second terminal of the first control circuit is connected to the first reset signal terminal.

[0009] For example, in at least one embodiment of the shift register unit provided in this disclosure, the control terminal of the first control sub-circuit is connected to the first terminal of the first control sub-circuit, and the signal of the first control node serves as the auxiliary control signal.

[0010] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first control circuit includes a second control sub-circuit and a third control sub-circuit; the control terminal of the second control sub-circuit is connected to the second node, the first terminal of the second control sub-circuit is connected to the first control node, and the second terminal of the second control sub-circuit is connected to the first reset signal terminal; the control terminal of the third control sub-circuit is connected to the first reset control terminal, the first terminal of the third control sub-circuit is connected to the first control node, and the second terminal of the third control sub-circuit is connected to the first reset signal terminal; the second control signal includes the signal of the second node and the first reset control signal.

[0011] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first sub-shift register unit further includes a first initial reset circuit, which is connected to an initial reset control terminal to receive an initial reset control signal and is configured to reset the first node in response to the initial reset control signal; the second sub-shift register unit further includes a second initial reset circuit, which is configured to reset the third node in response to the initial reset control signal, wherein the control terminal of the second initial reset circuit is connected to the initial reset control terminal to receive the initial reset control signal, the first terminal of the second initial reset circuit is connected to the third node, and the second terminal of the second initial reset circuit is connected to the second control node.

[0012] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first sub-shift register unit further includes a first initial reset circuit, which is connected to an initial reset control terminal to receive an initial reset control signal and is configured to reset the first node in response to the initial reset control signal; the second sub-shift register unit further includes a second initial reset circuit, which is configured to reset the third node in response to the initial reset control signal, wherein the control terminal of the second initial reset circuit is connected to the initial reset control terminal to receive the initial reset control signal, the first terminal of the second initial reset circuit is connected to the third node, and the second terminal of the second initial reset circuit is connected to the second control node; the initial reset control terminal is multiplexed as the auxiliary control terminal.

[0013] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first sub-shift register unit further includes a leakage current protection charging circuit. The control terminal of the leakage current protection charging circuit is connected to the first node. The first terminal of the leakage current protection charging circuit is connected to a leakage current protection charging signal terminal to receive a leakage current protection charging signal. The second terminal of the leakage current protection charging circuit is connected to the first control node. The leakage current protection charging circuit is configured to input the leakage current protection charging signal to the first control node under the control of the first node.

[0014] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first sub-shift register unit further includes a second node control circuit, which includes a second node charging circuit and a second node reset circuit. The second node charging circuit is connected to a second node charging control terminal to receive a second node charging control signal, and to a second node charging signal terminal to receive a second node charging signal. It is also connected to the second node. The second node charging circuit is configured to charge the second node using the second node charging signal in response to the second node charging control signal. The second node reset circuit is connected to the first node and the second node, and is connected to the first reset signal terminal to receive the first reset signal and / or to the second reset signal terminal to receive a second reset signal. The second node reset circuit is configured to reset the second node using the first reset signal and the second reset signal under the control of the potential of the first node. The level of the second reset signal is lower than the level of the first reset signal, or the level of the second reset signal is equal to the level of the first reset signal.

[0015] For example, in at least one embodiment of the shift register unit provided in this disclosure, the fourth node is connected to the second node.

[0016] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first reset sub-circuit includes a first reset transistor, the gate of the first reset transistor is connected to the second node, the first terminal of the first reset transistor is connected to the first node, and the second terminal of the first reset transistor is connected to the first control node; the second reset sub-circuit includes a second reset transistor, the gate of the second reset transistor is connected to the fourth node, the first terminal of the second reset transistor is connected to the third node, and the second terminal of the second reset transistor is connected to the second control node.

[0017] For example, in at least one embodiment of the shift register unit provided in this disclosure, the third reset sub-circuit includes a third reset transistor, the gate of which is connected to the first reset control terminal, the first terminal of which is connected to the first node, and the second terminal of which is connected to the first control node; the fourth reset sub-circuit includes a fourth reset transistor, the gate of which is connected to the second reset control terminal to receive the second reset control signal, the first terminal of which is connected to the third node, and the second terminal of which is connected to the second control node.

[0018] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first control sub-circuit includes a first control transistor, the gate of the first control transistor is connected to the auxiliary control terminal, the first electrode of the first control transistor is connected to the first control node, and the second electrode of the first control transistor is connected to the first reset signal terminal.

[0019] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first control sub-circuit includes a first control transistor, the gate of the first control transistor is connected to the first terminal of the first control transistor, the first terminal of the first control transistor is connected to the first control node, and the second terminal of the first control transistor is connected to the first reset signal terminal.

[0020] For example, in at least one embodiment of the shift register unit provided in this disclosure, the second control sub-circuit includes a second control transistor, the gate of the second control transistor is connected to the second node, the first terminal of the second control transistor is connected to the first control node, and the second terminal of the second control transistor is connected to the first reset signal terminal; the third control sub-circuit includes a third control transistor, the gate of the third control transistor is connected to the first reset control terminal, the first terminal of the third control transistor is connected to the first control node, and the second terminal of the third control transistor is connected to the first reset signal terminal.

[0021] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first initial reset circuit includes a first initial transistor and a second initial transistor; the gates of the first initial transistor and the second initial transistor are both connected to the initial reset control terminal; the first terminal of the first initial transistor is connected to the first node; the second terminal of the first initial transistor is connected to the first terminal of the second initial transistor; and the second terminal of the second initial transistor is connected to the first reset signal terminal. The second initial reset circuit includes a third initial transistor; the gate of the third initial transistor is connected to the initial reset control terminal; the first terminal of the third initial transistor is connected to the third node; and the second terminal of the third initial transistor is connected to the second control node.

[0022] For example, in the shift register unit provided in at least one embodiment of this disclosure, when the initial reset control terminal is multiplexed as the auxiliary control terminal, the second initial transistor is multiplexed as the first control transistor, the gate of the first control transistor is connected to the initial reset control terminal, the second terminal of the first initial transistor is connected to the first terminal of the first control transistor, and both the second terminal of the first initial transistor and the first terminal of the first control transistor are connected to the first control node.

[0023] For example, in at least one embodiment of the shift register unit provided in this disclosure, the leakage current protection charging circuit includes a leakage current protection charging transistor, the gate of the leakage current protection charging transistor is connected to the first node, the first terminal of the leakage current protection charging transistor is connected to the leakage current protection charging signal terminal, and the second terminal of the leakage current protection charging transistor is connected to the first control node.

[0024] For example, in at least one embodiment of the shift register unit provided in this disclosure, the second node charging circuit includes a first charging transistor and a second charging transistor; the second node charging signal terminal is connected to the second node charging control terminal, the first electrode of the first charging transistor is connected to the second node charging signal terminal, and the second electrode of the first charging transistor is connected to the gate of the second charging transistor; the first electrode of the second charging transistor is connected to the second node charging signal terminal, and the second electrode of the second charging transistor is connected to the second node.

[0025] For example, in at least one embodiment of the shift register unit provided in this disclosure, the second node reset circuit includes a first transistor and a second transistor; the gate of the first transistor and the gate of the second transistor are both connected to the first node, the first terminal of the first transistor is connected to the gate of the second charging transistor and the second terminal of the first charging transistor, and the second terminal of the first transistor is connected to the first reset signal terminal or the second reset signal terminal; the first terminal of the second transistor is connected to the second node and the second terminal of the second charging transistor, and the second terminal of the second transistor is connected to the first reset signal terminal.

[0026] For example, in at least one embodiment of the shift register unit provided in this disclosure, the driving terminal of the first input circuit is connected to the first input control signal terminal to receive the first input control signal, the first terminal of the first input circuit is connected to the first input signal terminal to receive the first input signal, and the second terminal of the first input circuit is connected to the first node to charge the first node using the first input signal; the driving terminal of the second input circuit is connected to the first input control signal terminal to receive the first input control signal, the first terminal of the second input circuit is connected to the first input signal terminal to receive the first input signal, and the second terminal of the second input circuit is connected to the third node to charge the third node using the first input signal.

[0027] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first input circuit includes a first input transistor, the gate of which is connected to the first input control signal terminal to receive the first input control signal, the first terminal of which is connected to the first input signal terminal to receive the first input signal, and the second terminal of which is connected to the first node to charge the first node using the first input signal; the second input circuit includes a second input transistor, the gate of which is connected to the first input control signal terminal to receive the first input control signal, the first terminal of which is connected to the first input signal terminal to receive the first input signal, and the second terminal of which is connected to the third node to charge the third node using the first input signal.

[0028] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first input circuit is also connected to the first control node, and the first terminal of the second input circuit is connected to the first control node to be connected to the first input signal terminal via the first control node, and the second input circuit charges the third node using the first input signal received via the first control node.

[0029] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first input circuit includes a first input transistor, the gate of which is connected to the first input control signal terminal to receive the first input control signal, the first terminal of which is connected to the first input signal terminal to receive the first input signal, the second terminal of which is connected to the first node to charge the first node using the first input signal, and the second terminal of which is also connected to the first control node; the second input circuit includes a second input transistor, the gate of which is connected to the first input control signal terminal to receive the first input control signal, the first terminal of which is connected to the first control node to be connected to the first input signal terminal via the first control node, the second input transistor charging the third node using the first input signal received via the first control node, and the second terminal of which is connected to the third node to charge the third node using the first input signal.

[0030] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first output circuit includes a first output transistor and a first capacitor; the gate of the first output transistor is connected to the first node, the first terminal of the first output transistor is connected to a first clock signal terminal to receive the first clock signal, and the second terminal of the first output transistor is connected to the first output terminal; the first terminal of the first capacitor is connected to the gate of the first output transistor, and the second terminal of the first capacitor is connected to the second terminal of the first output transistor; the second output circuit includes a second output transistor and a second capacitor; the gate of the second output transistor is connected to the third node, the first terminal of the second output transistor is connected to a second clock signal terminal to receive the second clock signal, and the second terminal of the second output transistor is connected to the second output terminal; the first terminal of the second capacitor is connected to the gate of the second output transistor, and the second terminal of the second capacitor is connected to the second terminal of the second output transistor.

[0031] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first output reset circuit includes a first output reset transistor, the gate of which is connected to the second node, the first electrode of which is connected to the first output terminal, and the second electrode of which is connected to the first reset signal terminal to receive the first reset signal; the second output reset circuit includes a second output reset transistor, the gate of which is connected to the fourth node, the first electrode of which is connected to the second output terminal, and the second electrode of which is connected to the second reset signal terminal to receive the second reset signal and configured to reset the second output terminal using the second reset signal; the level of the second reset signal is lower than the level of the first reset signal.

[0032] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first sub-shift register further includes a third output reset circuit and a third output circuit; the third output reset circuit is configured to reset the third output terminal under the control of the second node; the third output circuit is configured to output a third clock signal to the third output terminal under the control of the first node.

[0033] For example, in at least one embodiment of the shift register unit provided in this disclosure, the third output reset circuit includes a third output reset transistor, the gate of which is connected to the second node, the first terminal of which is connected to the third output terminal, and the second terminal of which is connected to a second reset signal terminal to receive a second reset signal and configured to reset the third output terminal using the second reset signal; the level of the second reset signal is lower than the level of the first reset signal; the third output circuit includes a third output transistor and a third capacitor; the gate of which is connected to the first node, the first terminal of which is connected to a third clock signal terminal to receive the third clock signal, and the second terminal of which is connected to the third output terminal; the first terminal of which is connected to the gate of which is the third output transistor, and the second terminal of which is connected to the second terminal of which is the third output transistor.

[0034] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first sub-shift register unit further includes an auxiliary reset circuit. The control terminal of the auxiliary reset circuit is connected to a first input control terminal to receive the first input control signal. The first terminal of the auxiliary reset circuit is connected to the second node, and the second terminal of the auxiliary reset circuit is connected to the first reset signal terminal to receive the first reset signal. The auxiliary reset circuit is configured to reset the second node using the first reset signal in response to the first input control signal.

[0035] For example, in at least one embodiment of the shift register unit provided in this disclosure, the auxiliary reset circuit includes an auxiliary reset transistor, the gate of which is connected to the first input control terminal, the first terminal of which is connected to the second node, and the second terminal of which is connected to the first reset signal terminal. At least one embodiment of this disclosure provides a shift register unit comprising: an input circuit, a first output reset circuit, a first reset circuit, a first output circuit, and a first control circuit. The input circuit is configured to charge the first node in response to an input control signal; the first output reset circuit is configured to reset the first output terminal under the control of the second node; the first output circuit is configured to output a first clock signal to the first output terminal under the control of the first node; the first reset circuit and the first control circuit are connected to a first control node, and the first control circuit is connected between the first control node and the first reset signal terminal; the first reset circuit and the first control circuit are configured to reset the first node using a first reset signal from the first reset signal terminal in response to a first control signal and a second control signal, respectively.

[0036] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first reset circuit includes a first reset sub-circuit, the control terminal of the first reset sub-circuit is connected to the second node, the first terminal of the first reset sub-circuit is connected to the first node, the second terminal of the first reset sub-circuit is connected to the first control node, and the first reset sub-circuit is configured to reset the first node using the first reset signal from the first control node under the control of the second node, wherein the first control signal includes the signal of the second node.

[0037] For example, in the shift register unit provided in at least one embodiment of this disclosure, the first reset circuit further includes a second reset sub-circuit. The driving terminal of the second reset sub-circuit is connected to the first reset control terminal to receive a first reset control signal. The first control signal includes the first reset control signal. The first terminal of the second reset sub-circuit is connected to the first node, and the second terminal of the second reset sub-circuit is connected to the first control node.

[0038] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first control circuit includes a first control sub-circuit, the control terminal of the first control sub-circuit is connected to an auxiliary control terminal to receive an auxiliary control signal, the second control signal includes the auxiliary control signal, the first terminal of the first control circuit is connected to the first control node, and the second terminal of the first control circuit is connected to the first reset signal terminal.

[0039] For example, in at least one embodiment of the shift register unit provided in this disclosure, the control terminal of the first control sub-circuit is connected to the first terminal of the first control sub-circuit, and the signal of the first control node serves as the auxiliary control signal.

[0040] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first control circuit includes a second control sub-circuit and a third control sub-circuit; the control terminal of the second control sub-circuit is connected to the second node, the first terminal of the second control sub-circuit is connected to the first control node, and the second terminal of the second control sub-circuit is connected to the first reset signal terminal; the control terminal of the third control sub-circuit is connected to the first reset control terminal, the first terminal of the third control sub-circuit is connected to the first control node, and the second terminal of the third control sub-circuit is connected to the first reset signal terminal; the second control signal includes the signal of the second node and the first reset control signal.

[0041] For example, at least one embodiment of the shift register unit provided in this disclosure further includes: a first initial reset circuit, which is connected to an initial reset control terminal to receive an initial reset control signal and is configured to reset the first node in response to the initial reset control signal.

[0042] For example, in at least one embodiment of the shift register unit provided in this disclosure, the initial reset control terminal is multiplexed as the auxiliary control terminal.

[0043] For example, at least one embodiment of the shift register unit provided in this disclosure further includes a leakage current protection charging circuit. The control terminal of the leakage current protection charging circuit is connected to the first node, the first terminal of the leakage current protection charging circuit is connected to a leakage current protection charging signal terminal to receive a leakage current protection charging signal, the second terminal of the leakage current protection charging circuit is connected to the first control node, and the leakage current protection charging circuit is configured to input the leakage current protection charging signal to the first control node under the control of the first node.

[0044] For example, at least one embodiment of the shift register unit provided in this disclosure further includes a second node control circuit, which includes a second node charging circuit and a second node reset circuit. The second node charging circuit is connected to a second node charging control terminal to receive a second node charging control signal, and to a second node charging signal terminal to receive a second node charging signal. It is also connected to the second node. The second node charging circuit is configured to charge the second node using the second node charging signal in response to the second node charging control signal. The second node reset circuit is connected to the first node and the second node, and to a first reset signal terminal to receive the first reset signal. The second node reset circuit is configured to reset the second node using the first reset signal under the control of the potential of the first node.

[0045] For example, at least one embodiment of the shift register unit provided in this disclosure further includes an auxiliary reset circuit, wherein the control terminal of the auxiliary reset circuit is connected to the input control terminal to receive the input control signal, the first terminal of the auxiliary reset circuit is connected to the second node, the second terminal of the auxiliary reset circuit is connected to the first reset signal terminal to receive the first reset signal, and the auxiliary reset circuit is configured to reset the second node using the first reset signal in response to the first input control signal.

[0046] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first reset sub-circuit includes a first reset transistor, the gate of the first reset transistor is connected to the second node, the first terminal of the second reset transistor is connected to the first node, and the second terminal of the first reset transistor is connected to the first control node.

[0047] For example, in at least one embodiment of the shift register unit provided in this disclosure, the second reset sub-circuit includes a second reset transistor, the gate of the second reset transistor is connected to the first reset control terminal, the first terminal of the second reset transistor is connected to the first node, and the second terminal of the second reset transistor is connected to the first control node.

[0048] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first control sub-circuit includes a first control transistor, the gate of the first control transistor is connected to the auxiliary control terminal, the first electrode of the first control transistor is connected to the first control node, and the second electrode of the first control transistor is connected to the first reset signal terminal.

[0049] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first control sub-circuit includes a first control transistor, the gate of the first control transistor is connected to the first terminal of the first control transistor, the first terminal of the first control transistor is connected to the first control node, and the second terminal of the first control transistor is connected to the first reset signal terminal.

[0050] For example, in at least one embodiment of the shift register unit provided in this disclosure, the second control sub-circuit includes a second control transistor, the gate of the second control transistor is connected to the second node, the first terminal of the second control transistor is connected to the first control node, and the second terminal of the second control transistor is connected to the first reset signal terminal; the third control sub-circuit includes a third control transistor, the gate of the third control transistor is connected to the first reset control terminal, the first terminal of the third control transistor is connected to the first control node, and the second terminal of the third control transistor is connected to the first reset signal terminal.

[0051] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first initial reset circuit includes a first initial transistor and a second initial transistor; the gates of the first initial transistor and the second initial transistor are both connected to the initial reset control terminal, the first terminal of the first initial transistor is connected to the first node, the second terminal of the first initial transistor is connected to the first terminal of the second initial transistor, and the second terminal of the second initial transistor is connected to the first reset signal terminal.

[0052] For example, in the shift register unit provided in at least one embodiment of this disclosure, when the initial reset control terminal is multiplexed as the auxiliary control terminal, the second initial transistor is multiplexed as the first control transistor, the gate of the first control transistor is connected to the initial reset control terminal, the second terminal of the first initial transistor is connected to the first terminal of the first control transistor, and both the second terminal of the first initial transistor and the first terminal of the first control transistor are connected to the first control node.

[0053] For example, in at least one embodiment of the shift register unit provided in this disclosure, the second node charging circuit includes a first charging transistor and a second charging transistor; the second node charging signal terminal is connected to the second node charging control terminal, the first electrode of the first charging transistor is connected to the second node charging signal terminal, and the second electrode of the first charging transistor is connected to the gate of the second charging transistor; the first electrode of the second charging transistor is connected to the second node charging signal terminal, and the second electrode of the second charging transistor is connected to the second node.

[0054] For example, in at least one embodiment of the shift register unit provided in this disclosure, the second node reset circuit includes a first transistor and a second transistor; the gate of the first transistor and the gate of the second transistor are both connected to the first node, the first terminal of the first transistor is connected to the gate of the second charging transistor and the second terminal of the first charging transistor, and the second terminal of the first transistor is connected to the first reset signal terminal; the first terminal of the second transistor is connected to the second node and the second terminal of the second charging transistor, and the second terminal of the second transistor is connected to the first reset signal terminal.

[0055] For example, in at least one embodiment of the shift register unit provided in this disclosure, the leakage current protection charging circuit includes a leakage current protection charging transistor, the gate of the leakage current protection charging transistor is connected to the first node, the first terminal of the leakage current protection charging transistor is connected to the leakage current protection charging signal terminal, and the second terminal of the leakage current protection charging transistor is connected to the first control node.

[0056] For example, in at least one embodiment of the shift register unit provided in this disclosure, the auxiliary reset circuit includes an auxiliary reset transistor, the gate of the auxiliary reset transistor is connected to the input control terminal, the first terminal of the auxiliary reset transistor is connected to the second node, and the second terminal of the auxiliary reset transistor is connected to the first reset signal terminal.

[0057] For example, in at least one embodiment of the shift register unit provided in this disclosure, the shift register unit further includes a second output reset circuit and a second output circuit; the second output reset circuit is configured to reset the second output terminal under the control of the second node; the second output circuit is configured to output a second clock signal to the second output terminal under the control of the first node.

[0058] For example, in at least one embodiment of the shift register unit provided in this disclosure, the second output reset circuit includes a second output reset transistor, the gate of which is connected to the second node, the first terminal of which is connected to the second output terminal, and the second terminal of which is connected to a first reset signal terminal to receive a first reset signal and configured to reset the second output terminal using the first reset signal; the second output circuit includes a second output transistor and a second capacitor; the gate of which is connected to the first node, the first terminal of which is connected to a second clock signal terminal to receive the second clock signal, and the second terminal of which is connected to the second output terminal; the first terminal of which is connected to the gate of which is the second output transistor, and the second terminal of which is connected to the second terminal of which is the second output transistor.

[0059] For example, in the shift register unit provided in at least one embodiment of this disclosure, a first auxiliary transistor is connected between the gate of the first output transistor and the gate of the second output transistor; the gate of the first auxiliary transistor is connected to a first auxiliary control terminal, the first terminal of the first auxiliary transistor is connected to the gate of the first output transistor, and the second terminal of the first auxiliary transistor is connected to the gate of the second output transistor.

[0060] For example, in at least one embodiment of the shift register unit provided in this disclosure, a second auxiliary transistor is connected between the first node and the first reset circuit; the gate of the second auxiliary transistor is connected to a second auxiliary control terminal, the first terminal of the second auxiliary transistor is connected to the first reset circuit, and the second terminal of the second auxiliary transistor is connected to the first node. At least one embodiment of the present disclosure provides a shift register unit, which includes: a first sub-shift register unit and a second sub-shift register unit. The first sub-shift register unit includes: a first input circuit, a first output reset circuit, and a first output circuit; the first input circuit is configured to input a first input signal to a first node in response to a first input control signal; the first output reset circuit is configured to reset a first output terminal under the control of a second node; the first output circuit is configured to output a first clock signal to the first output terminal under the control of the first node; the second sub-shift register unit includes: a second input circuit, a second output reset circuit, and a second output circuit; the second input circuit is configured to input the first input signal to a third node in response to a second input control signal; the second output reset circuit is configured to reset a second output terminal under the control of a fourth node; the second output circuit is configured to output a second clock signal to the second output terminal under the control of the fourth node; the fourth node is connected to the second node, and the second output reset circuit is configured to reset the second output terminal under the control transmitted via the second node to the fourth node.

[0061] For example, in at least one embodiment of the shift register unit provided in this disclosure, the first sub-shift register unit further includes a second node control circuit, which includes a second node charging circuit and a second node reset circuit. The second node charging circuit is connected to a second node charging control terminal to receive a second node charging control signal, and to a second node charging signal terminal to receive a second node charging signal. It is also connected to the second node. The second node charging circuit is configured to charge the second node using the second node charging signal in response to the second node charging control signal. The second node reset circuit is connected to the first node and the second node, and is connected to the first reset signal terminal to receive the first reset signal and / or to the second reset signal terminal to receive a second reset signal. The second node reset circuit is configured to reset the second node using the first reset signal and the second reset signal under the control of the potential of the first node. The level of the second reset signal is lower than the level of the first reset signal, or the level of the second reset signal is equal to the level of the first reset signal.

[0062] For example, in at least one embodiment of the shift register unit provided in this disclosure, the second sub-shift register unit does not have a second node control circuit. At least one embodiment of this disclosure provides a shift register unit comprising: an input circuit, a first output reset circuit, a first reset circuit, and a first output circuit. The input circuit is configured to charge a first node in response to an input control signal; the first output reset circuit is configured to reset a first output terminal under the control of a second node; the first output circuit is configured to output a first clock signal to the first output terminal under the control of the first node; the control terminal of the first reset circuit is connected to the second node, the first terminal of the first reset circuit is connected to the first node, and the second terminal of the second reset circuit is connected to the first output terminal.

[0063] For example, at least one embodiment of the shift register unit provided in this disclosure further includes a second reset circuit, wherein the control terminal of the second reset circuit is connected to the first reset control terminal to receive a first reset control signal, the first terminal of the second reset circuit is connected to the first node, and the second terminal of the second reset circuit is connected to the first output terminal.

[0064] For example, at least one embodiment of the shift register unit provided in this disclosure further includes an initial reset circuit, wherein the control terminal of the initial reset circuit is connected to an initial reset control terminal to receive an initial reset control signal, the first terminal of the initial reset circuit is connected to the first node, and the second terminal of the initial reset circuit is connected to the first output terminal.

[0065] At least one embodiment of this disclosure provides a driving circuit, which includes a plurality of cascaded shift register units, wherein the shift register units are any type of shift register units provided in the embodiments of this disclosure.

[0066] For example, in the driving circuit provided in at least one embodiment of this disclosure, except for the first-stage shift register unit, the first input terminal of each of the other shift register units is connected to the first output terminal of the previous-stage shift register unit; except for the last-stage shift register unit, the initial reset control terminal of each of the other shift register units is connected to the first output terminal of the next-stage shift register unit.

[0067] At least one embodiment of this disclosure provides a display device, which includes any of the driving circuits provided in the embodiments of this disclosure. Attached Figure Description

[0068] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0069] Figure 1 is a circuit diagram of a shift register unit provided in an embodiment of this disclosure;

[0070] Figure 2 is a signal timing diagram corresponding to the shift register unit shown in Figure 1 when it is working;

[0071] Figure 3 is a circuit diagram of another shift register unit provided in an embodiment of this disclosure;

[0072] Figure 4 is a signal timing diagram corresponding to the shift register unit shown in Figure 3 when it is working;

[0073] Figure 5 is a circuit diagram of another shift register unit provided in an embodiment of this disclosure;

[0074] Figure 6 is a signal timing diagram corresponding to the shift register unit shown in Figure 5 when it is working;

[0075] Figure 7 is a circuit diagram of another shift register unit provided in an embodiment of this disclosure;

[0076] Figure 8 is a signal timing diagram corresponding to the shift register unit shown in Figure 7 when it is working;

[0077] Figure 9 is a circuit diagram of another shift register unit provided in an embodiment of this disclosure;

[0078] Figure 10 is a signal timing diagram corresponding to the shift register unit shown in Figure 9 when it is working;

[0079] Figure 11 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0080] Figure 12 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0081] Figure 13 is a circuit diagram of another shift register unit provided in an embodiment of this disclosure;

[0082] Figure 14 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0083] Figure 15 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0084] Figure 16 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0085] Figure 17 is a signal timing diagram corresponding to the shift register unit shown in Figure 16 when it is working;

[0086] Figure 18 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0087] Figure 19 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0088] Figure 20 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0089] Figure 21 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0090] Figure 22 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0091] Figure 23 is a circuit diagram of another shift register unit provided in an embodiment of the present disclosure;

[0092] Figure 24 is a signal timing diagram corresponding to the shift register unit shown in Figure 23 during operation; and

[0093] Figure 25 is a schematic block diagram of a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. The embodiments described below are some, but not all, embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0095] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0096] In describing the connection relationships of components and nodes in a shift register unit or driver circuit, unless otherwise specified, the term "connection" refers to an electrical connection, meaning that the two connected components are electrically connected, i.e., they can form a current through each other. Unless otherwise specified, the two components that can form a current through each other can be directly connected by a wire, or they can be connected by other switching elements (such as transistors), and when the switching elements are turned on, they form a current through the switching elements.

[0097] In this disclosure, the direct connection of components such as nodes, signal terminals, transistor electrodes, and capacitor electrodes in a circuit via wires means that no other electronic components besides wires are provided between the directly connected components. These electronic components include, but are not limited to, switching elements such as transistors and capacitors.

[0098] In this embodiment of the disclosure, CR <n-2>G1 represents both the first input control terminal and the first input control signal. <n>VGL1 represents both the first output terminal and the first output signal, while CR represents both the first reset signal terminal and the first reset signal.<N+4> The symbols TRST and GVDD2 can represent both auxiliary control terminals and auxiliary control signals, respectively. TRST can represent both initial reset control terminals and initial reset control signals. GVDD2 can represent both leakage current protection charging signal terminals and leakage current charging signals. GVDD1 can represent both second node charging control terminals and second node charging control signals. Similarly, other reference numerals in the figures can represent both signal terminals and signals provided by those terminals, and will not be listed individually here.

[0099] In display panel technology, to achieve low cost and narrow bezels, GOA (Gate driver on Array) technology can be used. This involves integrating the gate driving circuitry onto the display panel using thin-film transistor technology, thereby achieving advantages such as narrow bezels and reduced assembly costs. The display panel can be a liquid crystal display (LCD) panel or an organic light-emitting diode (OLED) display panel. The pixels of the display panel include light-emitting devices, which can be of various types and selected according to actual needs. For example, the light-emitting device can be OLED, quantum dot light-emitting diodes (QLED), or micro light-emitting diodes (Micro LED), etc.

[0100] In the display field, especially in OLED displays, oxides are currently widely used in medium and large-sized OLED displays due to their good uniformity. However, because the gate driving circuit needs to consider functions such as leakage protection, the circuit becomes overly complex and has a low yield rate. Furthermore, the gate driving circuit contains too many semiconductor components, occupying too much bezel space, which is not conducive to realizing narrow bezel display panels.

[0101] At least one embodiment of this disclosure provides a shift register unit, which includes: a first sub-shift register unit and a second sub-shift register unit; the first sub-shift register unit includes: a first input circuit, a first output reset circuit, a first reset circuit, a first output circuit, and a first control circuit; the first input circuit is configured to input a first input signal to a first node in response to a first input control signal; the first output reset circuit is configured to reset a first output terminal under the control of a second node; the first output circuit is configured to output a first clock signal to the first output terminal under the control of the first node; the first reset circuit and the first control circuit are connected to a first control node, and the first control circuit is connected between the first control node and a first reset signal terminal; the first reset circuit and the first control circuit are respectively configured to respond to a first input control signal. The control signal and the second control signal reset the first node using the first reset signal from the first reset signal terminal; the second sub-shift register unit includes: a second input circuit, a second output reset circuit, a second reset circuit, and a second output circuit; the second input circuit is configured to input the first input signal to the third node in response to the second input control signal; the second output reset circuit is configured to reset the second output terminal under the control of the fourth node; the second output circuit is configured to output a second clock signal to the second output terminal under the control of the fourth node; the second reset circuit is connected to the second control node, the second control node is connected to the first control node, and the second reset circuit is configured to reset the third node in response to the third control signal using the first reset signal transmitted from the first control node to the second control node.

[0102] According to the shift register unit provided in this embodiment, a first control circuit is connected between a first control node and a first reset signal terminal. The first reset signal reaches the first control node via the first control circuit and is then transmitted to the first node via the first reset circuit, thereby resetting the first node. During the operation of the shift register unit, direct connection between the first control node and the first reset signal terminal via wires can be avoided, thus maintaining the potential of the first control node using the first control circuit. Therefore, when a high potential is written to the first control node, on the one hand, it can prevent the first node from discharging through the first control node, thereby maintaining the potential of the first node; on the other hand, it can prevent leakage of transistors directly electrically connected to the first control node.

[0103] Furthermore, according to the shift register unit provided in the embodiments of this disclosure, by connecting the second control node of the second sub-shift register to the first control node of the first sub-shift register, the first reset signal can be transmitted to the second control node via the first control node and then to the third node via the third reset circuit of the second sub-shift register, thereby realizing the reset of the third node using the first reset signal from the first control node. The first sub-shift register and the second sub-shift register output signals respectively. For example, these two output signals are usually transmitted to two adjacent rows of sub-pixels in the display area. Thus, in the shift register unit provided in this embodiment, the first sub-shift register and the second sub-shift register that provide output signals to two adjacent rows of sub-pixels in the display area can be reset using the first reset signal from the first control node of the first sub-shift register. That is, the first sub-shift register and the second sub-shift register share the first reset signal from the first control node. There is no need to set up a separate reset circuit for the second sub-shift register, which simplifies the structure of the second sub-shift register. This not only reduces the manufacturing difficulty of the gate control circuit using this shift register unit, but also helps to reduce the space occupied by the gate control circuit, thereby reducing the bezel size of the display substrate using this shift register unit.

[0104] For example, FIG1 is a circuit diagram of a shift register unit provided in an embodiment of the present disclosure; FIG2 is a signal timing diagram corresponding to the shift register unit shown in FIG1 when it is working.

[0105] As shown in Figure 1, the shift register unit includes a first sub-shift register unit and a second sub-shift register unit. The first sub-shift register unit includes a first input circuit 110a, a first output reset circuit 121a, a first reset circuit 01, a first output circuit 131a, and a first control circuit 03.

[0106] The first input circuit 110a is configured to respond to the first input control signal CR <n-2>The first input signal is input to the first node Q. <n>, for the first node Q <n>Charging is performed. For example, the drive terminal of the first input circuit 110a is connected to the first input control signal terminal CR. <n-2>Connect to receive the first input control signal CR <n-2>The first terminal of the first input circuit 110a is connected to the first input signal terminal to receive the first input signal, and the second terminal of the first input circuit 110a is connected to the first node Q. <n>Connection to utilize the first input signal to the first node Q <n>Charge it.

[0107] The first output reset circuit 121a is configured at the second node QB <n>Under the control of the first output terminal G1 <n>Perform a reset, that is, at the second node QB <n>Under the control of the signal, the first output terminal G1 <n>Perform a reset; the first output circuit 131a is configured to perform a reset at the first node Q. <n>Under the control of the first clock signal CLKE1, the first clock signal is output to the first output terminal G1. <n>, as the first output signal.

[0108] The first reset circuit 01 and the first control circuit 03 are connected to the first control node OFF. <n>The first control circuit 03 is connected to the first control node OFF. <n>Between the first reset signal terminal VGL1; the first reset circuit 01 and the first control circuit 03 are configured to respond to the first control signal and the second control signal respectively by using the first reset signal VGL1 from the first reset signal terminal VGL1 to control the first node Q. <n>Perform a reset.

[0109] Since the first control circuit 03 is connected to the first control node OFF <n>Between the first reset signal VGL1 terminal and the first reset signal VGL1 terminal, the first reset signal VGL1 from the first reset signal VGL1 terminal can be transmitted to the first control node OFF via the first control circuit 03. <n>Then, it is transmitted to the first node Q via the first reset circuit 01. <n>For the first node Q <n>Perform a reset. This will prevent the first control section from turning off. <n>The first control node is directly connected to the first reset signal terminal via a wire, thereby enabling the first control circuit 03 to maintain the first control node OFF. <n>The potential. Thus, when a high potential is written to the first control node, on the one hand, it can prevent the first node's Q... <n>OFF via the first control node <n>Discharge to maintain the first node Q <n>On the one hand, the potential can prevent the first control node from being OFF. <n>The transistor with direct electrical connection is leaking current.

[0110] As shown in Figure 1, the second sub-shift register unit includes: a second input circuit 110b, a second output reset circuit 121b, a second reset circuit 02, and a second output circuit 131b.

[0111] The second input circuit 110b is configured to respond to the second input control signal CR <n-2>The first input signal is input to the third node Q.<N+1> To the third node Q<N+1> Charging is performed. For example, the drive terminal of the second input circuit 110b is connected to the first input control signal terminal CR. <n-2>Connect to receive the first input control signal CR <n-2>The first terminal of the second input circuit 110b is connected to the first input signal terminal to receive the first input signal, and the second terminal of the second input circuit 110b is connected to the third node Q.<N+1> Connection to utilize the first input signal to the third node Q<N+1> Charge it.

[0112] Here, we assume that the first input control signal and the second input control signal are the same signal CR. <n-2>For example, in other embodiments, the first input control signal and the second input control signal may be different signals that are controlled independently.

[0113] As shown in Figure 1, the second output reset circuit 121b is configured at the fourth node QB.<N+1> Under the control of the second output terminal G1<N+1> Perform a reset, specifically at the fourth node QB.<N+1> Under the control of the signal, the second output terminal G1<N+1> Perform a reset; the second output circuit 131b is configured at the fourth node QB<N+1> Under the control of the signal, the second clock signal CLKE2 is output to the second output terminal G1.<N+1> The second reset circuit 02 is OFF with the second control node.<N+1> Connection, second control node OFF<N+1> OFF with the first control node <n>The connection, the second reset circuit 02 is configured to respond to the third control signal via the first control node OFF. <n>Transmitted to the second control node OFF<N+1> The first reset signal VGL1 is applied to the third node Q.<N+1> Perform a reset.

[0114] For example, the second control node OFF<N+1> OFF with the first control node <n>Direct connection via wires. That is, the second control node is OFF.<N+1> OFF with the first control node <n>The conductive path includes paths that are only connected via wires. In paths that are only connected via wires, the second control node is OFF.<N+1> OFF with the first control node <n>There are no other circuit elements besides wires between them, and the circuit elements include, but are not limited to, transistors and capacitors.

[0115] For example, the first clock signal CLKE1 output by the first sub-shift register and the second clock signal CLKE2 output by the second sub-shift register are respectively transmitted to two adjacent rows of sub-pixels in the display area. According to the shift register unit provided in this embodiment, the second control node of the second sub-shift register is turned OFF.<N+1> OFF with the first control node of the first sub-shift register <n>The connection, the first reset signal VGL1 can be transmitted via the first control node OFF. <n>Transmitted to the second control node OFF<N+1> Then, it is transmitted to the third node Q via the second reset circuit 02 of the second sub-shift register.<N+1> This enables the use of the OFF signal from the first control node. <n>The first reset signal VGL1 is given to the third node Q.<N+1> A reset is performed. Therefore, the shift register unit provided in this embodiment can utilize the first control node OFF from the first sub-shift register. <n>The first reset signal VGL1 resets the first sub-shift register and the second sub-shift register, which provide output signals to two adjacent sub-pixels in the display area. In other words, the first sub-shift register and the second sub-shift register share the first reset signal from the first control node. There is no need to set up a separate reset circuit for the second sub-shift register, which simplifies the structure of the second sub-shift register. This not only reduces the manufacturing difficulty but also greatly helps to reduce the space occupied by the gate control circuit, thereby helping to reduce the bezel size of the display substrate.

[0116] N is a positive integer greater than or equal to 2, representing the number of pixel rows in the display area being scanned sequentially, or, in the case of multiple cascaded shift register units, the order of the sub-shift registers in the shift register unit that provides a one-to-one correspondence between the pixel rows of the display area and the grid scan signals. The first sub-shift register unit of the first-stage shift register unit, which receives the initial input signal, has an index of 1. For the Nth-stage shift register unit, the first sub-shift register unit outputs the first output signal G1. <n>The second output signal is CR <n>First output signal G1 <n>CR serves as the first input control signal for the next-stage shift register unit. <n-2>The second output signal CR <n>This serves as the raster scan signal for the Nth row of pixels in the display area.

[0117] Here, Figure 1 uses a shift register that provides signals to the pixels in rows N and N+1 as an example for illustration, i.e., the output terminal G1 <n>and G1<N+1> These are used to provide signals to the pixels in the Nth and N+1th rows, respectively. The first input control signal CR... <n-2>This is the output signal for row N-2. Of course, the first input control signal can also be the output signal for other rows, such as rows N-1, N-3, N-4, N-5, N-6, etc. Similarly, the auxiliary control signal CR...<N+4> This is the output signal for the (N+4)th row. Of course, the auxiliary control signal can also be the output signal for other rows, such as the output signals for rows N+3, N+4, N+5, N+6, N+7, etc. For example, as shown in Figure 1, the first reset circuit 01 includes a first reset sub-circuit 1a. For example, in Figure 1, the first reset sub-circuit 1a serves as the first reset circuit 01. The control terminal of the first reset sub-circuit 1a is connected to the second node QB. <n>Connection, the first terminal of the first reset sub-circuit 1a is connected to the first node Q <n>The second terminal of the first reset sub-circuit 1a is connected to the first control node OFF. <n>The first reset sub-circuit 1a is configured at the second node QB. <n>Under the control of the first control node OFF <n>The first reset signal VGL1 is applied to the first node Q. <n>To perform a reset, the aforementioned first control signal includes the second node QB. <n>The signal. The second reset circuit 02 includes a second reset sub-circuit 1b, for example, in Figure 1, the second reset sub-circuit 1b serves as the second reset circuit 02. The control terminal of the second reset sub-circuit 1b is connected to the fourth node QB.<N+1> The connection is made between the first terminal of the second reset sub-circuit 1b and the third node Q.<N+1> The second terminal of the second reset sub-circuit 1b is connected to the second control node OFF.<N+1> The second reset sub-circuit 1b is configured at the fourth node QB.<N+1> Under the control of the signal via the first control node OFF <n>Transmitted to the second control node OFF<N+1> The first reset signal VGL1 is applied to the third node Q.<N+1> Perform a reset.

[0118] For example, as shown in Figure 1, the first control circuit 03 includes a first control sub-circuit 3a. For example, in Figure 1, the first control sub-circuit 3a serves as the first control circuit 03. Of course, in other embodiments, the first control circuit may also include other sub-circuits. Referring to Figure 1, the control terminal and auxiliary control terminal CR of the first control sub-circuit 3a...<N+4> Connect to receive auxiliary control signal CR<N+4> The aforementioned second control signal includes the auxiliary control signal CR.<N+4> The first terminal of the first control circuit 03 is OFF with the first control node. <n>The second terminal of the first control circuit 03 is connected to the first reset signal terminal VGL1. Therefore, the first control sub-circuit 3a can respond to the auxiliary control signal CR.<N+4> When the circuit is turned on, the first reset sub-circuit 1a can be activated at the second node QB. <n>Under the control of the signal, it is turned on, so that the first reset signal VGL1 from the first reset signal terminal VGL1 can be transmitted via the first control sub-circuit 3a and the first control node OFF. <n>And the first reset circuit 1a transmits to the first node Q <n>, for the first node Q <n>Perform a reset.

[0119] For example, as shown in Figure 1, the first sub-shift register unit further includes a first initial reset circuit 170a. The first initial reset circuit 170a is connected to the initial reset control terminal TRST to receive the initial reset control signal TRST, and is configured to respond to the initial reset control signal TRST to the first node Q. <n>An initial reset is performed. The second sub-shift register unit also includes a second initial reset circuit 170b, which is configured to respond to the initial reset control signal TRST on the third node Q.<N+1> To perform a reset, for example, the control terminal of the second initial reset circuit 170b is also connected to the initial reset control terminal TRST to receive the initial reset control signal TRST. The first terminal of the second initial reset circuit 170b is connected to the third node Q.<N+1> Connection. The second terminal of the second initial reset circuit 170b is connected to the second control node OFF.<N+1> Connection. Thus, the second terminal of the second initial reset circuit 170b is connected to OFF.<N+1> Point connections can be made using the first control node OFF. <n>Transmitted to the second control node OFF<N+1> The initial reset signal TRST is applied to the third node Q.<N+1> The initial reset can be performed without setting up an initial reset circuit in the second sub-shift register unit, which simplifies the structure of the second sub-shift register unit, reduces the manufacturing difficulty of the gate control circuit using the shift register unit, and helps to reduce the space occupied by the gate control circuit, thereby reducing the bezel size of the display substrate using the shift register unit.

[0120] For example, multiple cascaded shift register units 100 described above can be used to form a driving circuit. When this driving circuit is used to drive the display substrate or display panel, for example, when the power is turned on, the first initial reset circuit 170a and the second initial reset circuit 170b in each shift register unit can simultaneously respond to the same initial reset control signal TRST, and adjust the first node Q in their respective circuits. <n>and the third node Q<N+1> The potential of the first node Q is reset or pulled down. <n>and the third node Q<N+1> The potential of the first node Q remains low during power-on, thus effectively preventing issues caused by the first node Q during non-output phases. <n>and the third node Q<N+1> The problem of multiple outputs caused by potential drift.

[0121] For example, as shown in Figure 1, the first sub-shift register unit also includes a leakage current protection charging circuit 150, the control terminal of which is connected to the first node Q. <n>The first terminal of the leakage protection charging circuit 150 is connected to the leakage protection charging signal terminal GVDD2 to receive the leakage protection charging signal GVDD2, and the second terminal of the leakage protection charging circuit 150 is connected to the first control node OFF. <n>The connection, the leakage protection charging circuit 150 is configured to connect at the first node Q. <n>OFF the first control node under the control of the signal. <n>Input the leakage current protection charging signal GVDD2. For example, the leakage current protection charging signal GVDD2 is a high-level signal, meaning its potential is not lower than that of the first node Q. <n>The potential when it is at a high potential (referred to as the high potential of the first node). Thus, the first control node can be OFF via the leakage protection charging circuit 150. <n>Write the leakage protection charging signal GVDD2 to turn the first control node OFF. <n>The potential is high. At this time, on the one hand, it can prevent the first node Q from being... <n>OFF via the first control node <n>Discharging maintains the potential of the first node. On the other hand, it increases the potential of the first (or second) terminal of the transistor connected to the first control node, making the gate-source voltage of the transistor negative. This allows the transistor to be turned off more completely, preventing leakage and thus preventing it from OFF with the first control node. <n>Transistor leakage in directly electrically connected transistors can, for example, prevent leakage in transistors in the first reset sub-circuit 1a and the first control sub-circuit 3a.

[0122] For example, as shown in Figure 1, the first sub-shift register unit further includes a second node control circuit 160. The second node control circuit 160 includes a second node charging circuit 161 and a second node reset circuit 162. The second node charging circuit 161 is connected to the second node charging control terminal GVDD1 to receive the second node charging control signal GVDD1, and to the second node charging signal terminal GVDD1 to receive the second node charging signal GVDD1, and is also connected to the second node QB... <n>The connection is such that the second node charging circuit 161 is configured to charge the second node QB in response to the second node charging control signal GVDD1. <n>Charging is then performed. For example, assuming the second node charging control signal and the second node charging control signal are the same signal GVDD1, the control terminal of the second node charging circuit 161 is connected to its first terminal; that is, both are connected to the same signal terminal to receive the same signal GVDD1. Of course, in other embodiments, the control terminal of the second node charging circuit 161 and its first terminal may not be electrically connected, and the second node charging control signal and the second node charging control signal may be different signals that are controlled independently.

[0123] For example, referring to Figure 1, the second node reset circuit 162 and the first node Q <n>Second node QB <n>The second node reset circuit 162 is configured to connect to the first reset signal terminal VGL1 to receive the first reset signal VGL1 and / or connect to the second reset signal terminal VGL2 to receive the second reset signal VGL2. The second node reset circuit 162 is configured to connect to the first node Q. <n>Under the control of the potential, the second node QB is controlled by the first reset signal VGL1 and the second reset signal VGL2. <n>A reset is performed; the level of the second reset signal VGL2 is lower than the level of the first reset signal VGL1, or the level of the second reset signal VGL2 is equal to the level of the first reset signal VGL1. For example, in at least one embodiment, the first reset signal terminal VGL1 and the second reset signal terminal VGL2 may also be the same reset signal terminal.

[0124] For example, as shown in Figure 1, the fourth node QB<N+1> With the second node QB <n>Connections. For example, the fourth node QB.<N+1> With the second node QB <n>The second output reset circuit 121b is configured to connect directly via the second node QB. <n>The reset of the second output terminal G1 <N+1> is controlled by the signal transmitted to the fourth node QB <N+1>. Thus, the second sub-shift register does not have a design of the second node control circuit similar to the first sub-shift register, i.e. the structure of the second sub-shift register is simplified.

[0125] For example, as shown in Fig. 1, the first input circuit 110a is also connected to the first control node OFF <n>The first end of the second input circuit 110b is connected to the first control node OFF <n>connect to via the first control node OFF <n>is connected to the first input signal terminal. Thus, the second input circuit 110b is able to use the signal inputted from the first input signal terminal via the first control node OFF <n>The received first input signal charges the third node Q<N+1>, without the need to additionally connect the second input circuit 110b of the second sub-shift register unit to the first input signal terminal, from the point of view of spatial wiring, only the first end of the second input circuit 110b needs to be connected to the first control node OFF <n>The connection saves the length of the wiring, thereby avoiding unnecessary wiring cross-connection and reducing the wiring difficulty, which is very important for the layout of the gate drive circuit using multiple cascaded shift register units, especially in the case of driving a high PPI display substrate, which can greatly reduce the wiring difficulty, is easy to implement in process, and improves the yield of the display substrate.

[0126] For example, as shown in FIG. 1, in at least one embodiment, the first sub-shift register unit further includes an auxiliary reset circuit 180, a control end of the auxiliary reset circuit 180 is connected with the first input control end to receive a first input control signal CR <n-2>, a first end of the auxiliary reset circuit 180 is connected to the second node QB <n>The second end of the connection, the auxiliary reset circuit 180 is connected with the first reset signal end VGL1 to receive the first reset signal VGL1, and the auxiliary reset circuit 180 is configured to respond to the first input control signal CR <n-2>The second node QB is reset by the first reset signal VGL1 <n>The reset is performed. Thus, when the first input control signal is an ON signal such as a high potential, the auxiliary reset circuit 180 is turned on, and thereby the second node QB <n>the potential of the first node Q <n>the potential of the first node QB becomes high potential, and the process plays an auxiliary role, and is beneficial to the first node QB <n>the potential of the second node QB becomes a high potential, and the input ability of the first input circuit is enhanced.

[0127] Of course, in other embodiments, the auxiliary reset circuit 180 can also be removed.

[0128] The specific structure of the shift register unit shown in Fig. 1 will be described below.

[0129] For example, as shown in Fig. 1, the first reset sub-circuit 1a includes a first reset transistor M8, a gate of the first reset transistor M8 being connected to the second node QB <n>connects, a first electrode of the first reset transistor M8 and the first node Q <n>connects, a second electrode of the first reset transistor M8 and the first control node OFF <n>Connection. The second reset sub-circuit 1b includes a second reset transistor M22, a gate of the second reset transistor M22 is connected with the fourth node QB<N+1>, a first pole of the second reset transistor M22 is connected with the third node Q<N+1>, and a second pole of the second reset transistor M22 is connected with the second control node OFF<N+1>.

[0130] For example, as shown in FIG. 1, the first control sub-circuit 3a includes a first control transistor M40, a gate of the first control transistor M40 is connected with the auxiliary control end CR<N+4>, a first pole of the first control transistor M40 is connected with the first control node OFF <n>The second electrode of the first control transistor M40 is connected with the first reset signal terminal VGL1.

[0131] For example, as shown in FIG. 1, the first initial reset circuit 170a includes a first initial transistor M3. The gate of the first initial transistor M3 is connected with the initial reset control terminal TRST, the first electrode of the first initial transistor M3 is connected with the first node Q <n>connects, a second electrode of the first initial transistor M3 and the first control node OFF <n>The first initial transistor M3, the first control transistor M40, and the first reset transistor M8 are connected to the first control node OFF. That is, the second electrode of the first initial transistor M3, the first electrode of the first control transistor M40, and the second electrode of the first reset transistor M8 are connected to the first control node OFF <n>.

[0132] For example, as shown in FIG. 1, the second initial reset circuit 170b includes a third initial transistor M20, a gate of the third initial transistor M20 is connected with the initial reset control terminal TRST, a first pole of the third initial transistor M20 is connected with the third node Q <n>The electrical connection.

[0133] For example, the leakage prevention charging circuit 150 includes a leakage prevention charging transistor whose gate is connected to the first node Q <n>The first electrode of the leakage-proof charging transistor is connected with the leakage-proof charging signal terminal GVDD2, and the second electrode of the leakage-proof charging transistor is connected with the first control node OFF <n>Connection. That is, in at least one embodiment, the leakage prevention charging transistor can simply be a transistor.

[0134] For example, in the embodiment shown in FIG. 1, the leakage prevention charging transistor includes a first leakage prevention charging transistor M51 and a second leakage prevention charging transistor M52. The gate of the first leakage prevention charging transistor M51 and the gate of the second leakage prevention charging transistor M52 are both coupled to the first node Q <n>The first electrode of the first leakage-preventing charging transistor M51 is connected with the leakage-preventing charging signal terminal GVDD2, the second electrode of the first leakage-preventing charging transistor M51 is connected with the first electrode of the second leakage-preventing charging transistor M52, the second electrode of the second leakage-preventing charging transistor M52 is connected with the first control node OFF <n>connected. That is, the first leakage prevention charging transistor M51 and the second leakage prevention charging transistor M52 are connected in series between the leakage prevention charging signal terminal GVDD2 and the first node Q <n>between.

[0135] For example, as shown in FIG. 1, the second node charging circuit 161 includes a first charging transistor M101 and a second charging transistor M11. A second node charging signal terminal GVDD1 is connected with a second node charging control terminal GVDD1, a first electrode of the first charging transistor M101 is connected with the second node charging signal terminal GVDD1, that is, the first electrode of the first charging transistor M101 is connected with the gate electrode of the first charging transistor M101. A second electrode of the first charging transistor M101 is connected with the gate electrode of the second charging transistor M11. A first electrode of the second charging transistor M11 is connected with the second node charging signal terminal GVDD1, and a second electrode of the second charging transistor M11 is connected with the second node QB <n>Connection.

[0136] In the embodiment shown in FIG. 1, the second node charging signal and the second node charging control signal are the same signal GVDD1. For example, the second node charging control signal GVDD1 is a constant high high-level signal.

[0137] Of course, in other embodiments, the second node charging signal terminal GVDD1 can not be connected with the second node charging control terminal GVDD1, and the second node charging signal and the second node charging control signal can be different signals independently controlled. In this case, the first electrode of the first charging transistor M101 is not connected with the gate of the first charging transistor M101.

[0138] For example, in some embodiments, as shown in FIG. 1, the second node charging circuit 161 can further include a third charging transistor M102. The third charging transistor M102 is connected in series with the first charging transistor M101, and the second electrode of the first charging transistor M101 is connected with the gate of the second charging transistor M11 via the third charging transistor M102. The gate of the third charging transistor M102 is also connected with the second node charging control terminal GVDD1, the first electrode of the third charging transistor M102 is connected with the second electrode of the first charging transistor M101, and the second electrode of the third charging transistor M102 is connected with the gate of the second charging transistor M11.

[0139] In some embodiments, the second node charging circuit 161 can only have the above-mentioned first charging transistor M101, but does not include the third charging transistor M102.

[0140] For example, as shown in FIG. 1, the second node reset circuit 162 includes a first transistor M12 and a second transistor M13. The gate of the first transistor M12 and the gate of the second transistor M13 are both connected with the first node Q <n>The first electrode of the first transistor M12 is connected with the gate electrode of the second charging transistor M11 and the second electrode of the first charging transistor M101, and the second electrode of the first transistor M12 is connected with the first reset signal terminal VGL1. The first electrode of the second transistor M13 is connected with the second node QB <n>The second electrode of the second charging transistor M11 is connected to the second electrode of the second transistor M13, and the second electrode of the second transistor M13 is connected to the first reset signal terminal VGL1.

[0141] Alternatively, in another embodiment, the second electrode of the first transistor M12 is connected to the second reset signal terminal VGL2, and the second reset signal terminal VGL2 provides a second reset signal VGL2 having a lower potential than the first reset signal VGL1 provided by the first reset signal terminal VGL1, so as to provide the second node Q <n>A first reset signal VGL1 is provided at the first node Q <n>When the potential of the first input circuit 110a is a low potential, the second electrode of the first transistor M12 receives a lower potential, so that the first transistor M12 is turned off more completely, preventing current leakage of the first transistor M12.

[0142] For example, as shown in FIG. 1, the first input circuit 110a includes a first input transistor M1. The gate of the first input transistor M1 is connected to a first input control signal terminal CR <n-2>connects to receive a first input control signal CR <n-2>The first electrode of the first input transistor Ml is connected to the first input signal terminal to receive a first input signal.

[0143] For example, the first input signal can be an alternating current signal (denoted as STV in the present application) or a direct current signal (denoted as GVDDn in the present application, where n is a positive integer). The second electrode of the first input transistor Ml is connected to the first node Q <n>connecting to utilize the first input signal to the first node Q <n>Charging is performed. For example, the first electrode of the first input transistor Ml is connected to the gate of the first input transistor Ml, so that the first input control signal CR <n-2>The first input signal is multiplexed as the first input control signal CR. Of course, in other embodiments, the first pole of the first input transistor Ml can not be connected to the gate of the first input transistor Ml, and the first input control signal CR <n-2>signals that are different from the first input signal and are independently controlled, respectively.

[0144] For example, as shown in FIG. 1, the first input circuit 110a further includes a third input transistor M2. The third input transistor M2 is connected in series between the second electrode of the first input transistor M1 and the first node Q <n>between the first input transistor Ml and the second input transistor M2, the second electrode of the first input transistor Ml is connected to the first node Q via the third input transistor M2 <n>Connection. The gate of the third input transistor M2 is also connected to the first input control signal terminal CR <n-2>connected, the first electrode of the third input transistor M2 is connected with the second electrode of the first input transistor Ml, and the second electrode of the third input transistor M2 is connected with the first node Q <n>Connection.

[0145] For example, in another embodiment, different from FIG. 1, the gate of the first input transistor M1 is connected with the first pole of the first input transistor M1 and with the first input control signal end CR <n-2>connects to receive a first input control signal CR <n-2>, a second electrode of the first input transistor M1 is directly connected to the first node Q <n>connected to the first input control signal CR <n-2>As the first input signal, that is, not including the third input transistor M2.

[0146] For example, as shown in FIG. 1, the second input circuit 110b includes a second input transistor M19, a gate of the second input transistor M19 being connected to the first input control signal terminal CR <n-2>connects to receive a first input control signal CR <n-2>, a first electrode of the second input transistor M19 and the first control node OFF <n>connect to via the first control node OFF <n>connected to the first input signal terminal, the second input transistor M19 uses the first control node OFF <n>The received first input signal charges the third node Q<N+1>, and the second electrode of the second input transistor M19 is connected to the third node Q<N+1> to charge the third node Q<N+1> with the first input signal, without the first electrode of the second input transistor M19 being additionally connected to the first input signal terminal. From the point of view of spatial wiring, only the first terminal of the second input circuit 110b needs to be connected to the first control node OFF <n>Connect, save the length of wiring, thereby avoid unnecessary wiring cross, reduce the wiring difficulty.

[0147] For example, in another embodiment, different from FIG. 1, the second input circuit 110b includes a second input transistor M19, and the gate of the second input transistor M19 is also connected with the first input control signal end CR <n-2>connects to receive a first input control signal CR <n-2>, the first electrode of the second input transistor M19 is connected to the first input signal terminal to receive the first input signal without being connected to the first control node OFF <n>The connection, the second electrode of the second input transistor M19 is connected with the third node Q

[0148] For example, as shown in FIG. 1, the first output circuit 131a includes a first output transistor M17 and a first capacitor C1. The gate of the first output transistor M17 is connected with the first node Q <n>The first end of the first output transistor M17 is connected to the first clock signal CLKE1 terminal to receive the first clock signal CLKE1, and the second end of the first output transistor M17 is connected to the first output terminal G1 <n>The first pole of the first capacitor C1 is connected with the gate of the first output transistor M17, and the second pole of the first capacitor C1 is connected with the second pole of the first output transistor M17.

[0149] For example, as shown in FIG. 1, the second output circuit 131b includes a second output transistor M23 and a second capacitor C2. The gate of the second output transistor M23 is connected with the third node Q

[0150] For example, as shown in FIG. 1, the first output reset circuit 121a includes a first output reset transistor M18, the gate of the first output reset transistor M18 is connected with the second node QB <n>connects the first electrode of the first output reset transistor M18 to the first output terminal G1 <n>The second electrode of the first output reset transistor M18 is connected to the first reset signal terminal VGL1 to receive the first reset signal VGL1.

[0151] For example, as shown in FIG. 1, the second output reset circuit 121b includes a second output reset transistor M24, a gate of the second output reset transistor M24 is connected to the fourth node QB

[0152] For example, as shown in FIG. 1, the auxiliary reset circuit 180 includes an auxiliary reset transistor M14, a gate of the auxiliary reset transistor M14 is connected to the first input control terminal, a first electrode of the auxiliary reset transistor M14 is connected to the second node QB <n>The second electrode of the connection auxiliary reset transistor M14 is connected with the first reset signal terminal VGL1.

[0153] The working principle of the shift register unit shown in FIG. 1 is described below in combination with the signal timing diagram shown in FIG. 2. In the four stages of the first stage T1, the second stage T2, the third stage T3 and the fourth stage T4 shown in FIG. 2, the shift register unit performs the following operations.

[0154] For example, the above-mentioned transistors are all N-type transistors. The following description is also taken as an example of N-type transistors, but embodiments of the present disclosure are not limited to this case, for example, at least part of these transistors can be replaced by P-type transistors.

[0155] In the first stage T1, the first input control signal CR <n-2>To turn on the signal, for example, to be a high potential, so that the first input transistor Ml, the second input transistor M2, the auxiliary reset transistor M14, and the second input transistor M19 are turned on. Thus, the first input signal is written to the first node Q by the first input circuit 110a <n>to the first node Q <n>Charging, the first input signal is a high level signal (for example, here the first input signal and the first input control signal are the same signal as an example), the first node Q <n>Write high potential; the first reset signal VGL1 is written into the second node QB through the auxiliary reset transistor M14 <n>, to the second node QB <n>Write low. Since the second node QB <n>For low potential, both the first reset transistor M8 and the first output reset transistor M18 are turned off. The first input signal is written to the third node Q<N+1> via the second input transistor M19 to charge the third node Q<N+1>, that is, the second electrode of the second input transistor M19 is connected to the third node Q<N+1> to charge the third node Q<N+1> with the first input signal, without the first electrode of the second input transistor M19 being additionally connected to the first input signal terminal, from the perspective of spatial wiring, only the first terminal of the second input circuit 110b needs to be connected to the first control node OFF <n>Connect, save the length of wiring, thus avoid unnecessary wiring cross, reduce the wiring difficulty.

[0156] And, in the first stage T1, the auxiliary control signal CR<N+4> is low to make the first control transistor M40 off, the initial reset control signal TRST is low to make the first initial transistor M3 off, at this time, in response to the first node Q <n>high potential, the first leakage-preventing charging transistor M51 and the second leakage-preventing charging transistor M52 are turned on, and the first control node OFF <n>The anti-leakage charging signal GVDD2 written into is a high potential signal to increase the voltage of the first control node OFF <n>the potential of the second electrode of the first initial transistor M3, the first electrode of the first control transistor M40, and the second electrode of the first reset transistor M8, so that the gate-source voltage of the first initial transistor M3, the first control transistor M40, and the first reset transistor M8 are all negative, so that the first initial transistor M3, the first control transistor M40, and the first reset transistor M8 are all turned off more thoroughly, preventing leakage of these transistors. The anti-leakage charging signal GVDD2 passes through the first control node OFF <n>The signal is transmitted to the second control node OFF < N + 1 >, thereby increasing the potential of the second electrode of the second reset transistor M22 connected to the second control node OFF < N + 1 >, thereby making the gate-source voltage of the second reset transistor M22 negative, thereby making the second reset transistor M22 turn off more completely, preventing the second reset transistor M22 from leaking.

[0157] And in the first stage T1, since the fourth node QB < N + 1 > and the second node QB <n>The electrical connection, thus, is written to the second node QB <n>The low level of the first input control signal CR is also written to the fourth node QB<N+1>, in response to the low level of the fourth node QB<N+1>, the second output reset transistor M24 is turned off.

[0158] In the second phase T2, the third phase T3 and the fourth phase T4 after the first phase T1, the first input control signal CR <n-2>The hold as off signal is for example a low potential, to keep the first input transistor Ml, the second input transistor M2, the auxiliary reset transistor M14 and the second input transistor M19 turned off.

[0159] In the second phase T2, the first output transistor M17 is turned on in response to the first node Q <n>The first clock signal CLKE1 is turned on by the high potential of the first clock signal CLKE1, and the first clock signal CLKE1 is output from the first output terminal Gl through the first output transistor M17 <n>output, as a first output signal, at the first output terminal G1 <n>the signal of the first node Q is high, so that the first node Q is brought to a high potential due to the bootstrap action of the first capacitor C1 <n>the potential of the first node Q is further raised, so that in the second phase T2 the first node Q <n>the potential at the first node Q is higher than the potential at the second node P in the first phase T1 <n>potential. In this process, the first leakage prevention charging transistor M51 and the second leakage prevention charging transistor M52 are kept on, continuously maintaining the first control node OFF <n>For high potential, to ensure the first node Q <n>the potential of the first control node OFF <n>, any one of the first initial transistor M3, the first control transistor M40, and the first reset transistor M8 leaks current, i.e., the first node Q <n>high potential.

[0160] In the second stage T2, the second output transistor M23 is turned on in response to the high potential of the third node Q<N+1>, and the second clock signal CLKE2 is output from the second output terminal Gl<N+1> as the second output signal through the second output transistor M23 at a time lagged from the time when the first clock signal CLKE1 changes from the low potential to the high potential, and the second clock signal CLKE2 changes from the low potential to the high potential. At this time, the signal of the second output terminal Gl<N+1> is the high potential, and thus the potential of the third node Q<N+1> is further increased due to the bootstrap action of the second capacitor C2. Thus, in the second stage T2, the potential of the third node Q<N+1> is higher than that of the first node Q<N> in the first stage Tl. <n>The time at which the potential of the third node Q<N+1> is further raised lags behind the time at which the potential of the second node Q<N> is further raised. The potential of the third node Q<N+1> is further raised at the time at which the potential of the second node Q<N> is further raised, and the potential of the third node Q<N+1> in the second stage T2 is higher than the potential of the third node Q<N+1> in the first stage T1. Thus, a time difference is provided between the signals outputted by the first sub-shift register unit and the second sub-shift register unit which provide the scanning signals to the two rows of pixels, respectively. The time lag does not exceed the time at which the second stage T2 ends, for example, so as to be controlled.

[0161] In the third stage T3, the first clock signal CLKE1 becomes low potential, and the first clock signal CLKE1 is outputted from the first output terminal G1 to the first node Q<N> through the first output transistor M17. <n>output, at this time, the first output terminal G1 <n>the signal of the first node Q is low, so that the first node Q is pulled up to the high potential due to the bootstrap action of the first capacitor C1 <n>the second clock signal CLKE2 becomes low potential at a time lagging the time when the first clock signal CLKE1 becomes low potential by the above-mentioned time lag, and the second clock signal CLKE2 is output from the second output terminal G1<N+1> through the second output transistor M23, at this time, the signal of the second output terminal G1<N+1> is low potential, so that the potential of the third node Q<N+1> is lowered due to the bootstrap action of the second capacitor C2, and becomes a signal of a level of sub-high.

[0162] In the fourth stage T4, the auxiliary control signal CR<N+4> becomes high potential, so that the first control transistor M40 is turned on, and the first reset signal VGL1 is transmitted to the first node Q <n>To give the first node Q <n>Reset. Since the first node is on Q <n>The second node QB is charged to a high potential by the first charging transistor M101, the third charging transistor M102, and the second charging transistor M11 <n>Thus, the first reset transistor M8 and the second reset transistor M22 are caused to respond to the second node QB <n>turns on, and the first reset signal VGL1 is written into the first node Q through the first reset transistor M8 <n>To further address the first node Q <n>a reset is performed; and a first reset signal VGL1 is passed through the first control node OFF <n>to the second control node OFF <N+1>, which in turn is transmitted via the second reset transistor M22 to the third node Q <N+1>, to reset the third node Q <N+1>, i.e. to the low state, due to the first control node OFF <n>OFF with the second control node<N+1> Electrical connection, capable of utilizing the first control node OFF <n>The first reset signal VGL1 transmitted to the second control node OFF<N+1> resets the third node Q<N+1>.

[0163] The first charging transistor M101, the third charging transistor M102, the second charging transistor M11, the first transistor M12 and the second transistor M13 constitute a Darlington inverter. The reason for using this Darlington inverter is that the width-length ratio (W / L) of the first charging transistor M101, the third charging transistor M102 and the first transistor M12 is smaller, at least smaller than that of the second transistor M13, and the leakage current of the first transistor M12 is smaller when the first transistor M1 is negatively biased; if the second charging transistor M11 and the second transistor M13 are directly used to constitute an inverter, the width-length ratio of the second transistor M13 is larger, and the leakage current of the second transistor M13 is larger when the second transistor M13 is negatively biased.

[0164] And in the fourth stage T4, the second node QB <n>to the fourth node QB <N+1>, so that the first output reset transistor M18 and the second output reset transistor M24 are respectively turned on in response to the second node QB <n>turns on by the high level of the second reset signal VGL2 and the high level of the fourth node QB<N+1>, and writes the second reset signal VGL2 into the first output terminal G1 through the first output reset transistor M18 <n>, the second reset signal VGL2 is written into the second output terminal G1<N+1> through the second output reset transistor M24, and the first node Q <n>the potential of the third node Q < N + 1 > is kept at a low potential due to the bootstrap action of the second capacitor C2, to ensure that the first output terminal G1 <n>both the first output end G1<N+1> and the second output end G1<N+2> do not output high potential.

[0165] For example, there is also an initialization stage (not shown in FIG. 2) before the first stage T1. In the initialization stage, the initial reset control signal TRST input by the initial reset control end TRST is a high-level signal, and the auxiliary control signal CR<N+4> input by the auxiliary control end CR<N+4> is also a high-level signal, so that the first initial transistor M3, the third initial transistor M20 and the first control transistor M40 are all turned on, so that the first node Q <n>and a first reset signal terminal VGL1 are electrically connected, the first reset signal VGL1 is written into the first node Q<N> via the first control transistor M40 and the first initial transistor M3, the potential of the first node Q<N> is pulled down to a low level, and a reset operation of the first node Q <n>an initial reset of the first control node OFF <n>The first reset signal VGL1 is electrically connected to the first control node OFF via a first resistor R1. <n>The signal transmitted to the second control node OFF<N+1> is further transmitted to the third node Q<N+1> via the third initial transistor M20, thereby achieving initial reset of the third node Q<N+1>. Thus, the first output transistor M17 and the second output transistor M23 are turned off in response to the low level of the first node Q<N> and the low level of the third node Q<N+1>, respectively, so that even if the first clock signal terminal CLKE1 or the second clock signal terminal CLKE2 inputs a high level at this stage, the first output terminal G1 <n>The high level signal cannot be outputted from the first output terminal G1<N+1> either. It should be noted that during the initialization stage, other transistors not mentioned are kept in the off state (i.e. turned off).

[0166] For example, the initial reset control signal TRST can be an on signal (e.g. high level signal) only during the initialization stage, and an off signal (e.g. low level signal) during other time periods.

[0167] For example, in the embodiment shown in Fig. 1, the auxiliary control signal terminal is independently controlled, denoted as CR<N+4>; in other embodiments, the auxiliary control signal terminal can be the same signal terminal as the initial reset control terminal TRST.

[0168] It should be noted that the high and low levels of the signal timing diagram shown in Fig. 2 are only illustrative, and do not represent the actual potential values.

[0169] Fig. 3 is a circuit schematic diagram of a shift register unit according to an embodiment of the present disclosure; and Fig. 4 is a signal timing diagram corresponding to the operation of the shift register unit shown in Fig. 3. The embodiment shown in Fig. 3 is different from the embodiment shown in Fig. 1 in that the timing diagram shown in Fig. 4 is the same as the timing diagram shown in Fig. 2.

[0170] For example, as shown in Fig. 3, the first reset circuit 01 further comprises a third reset sub-circuit 2a. The driving terminal of the third reset sub-circuit 2a is connected to the first reset control terminal CR<N+4> to receive the first reset control signal CR<N+4>, and the first control signal comprises the first reset control signal CR<N+4>. Here, the auxiliary control signal terminal and the first reset control terminal are the same signal terminal, both denoted as CR<N+4>, and of course, in other embodiments, the two can be different signals independently controlled. The first terminal of the third reset sub-circuit 2a is connected to the first node Q <n>connects, a second end of the third reset sub-circuit 2a and the first control node OFF <n>The connection, the third reset sub-circuit 2a is configured to utilize the first reset signal VGL1 from the first reset signal end VGL1 to the first node Q <n>A reset is performed to set the first node Q <n>On the basis of the reset, the first node Q is reset by the third reset sub-circuit 2a <n>a further reset.

[0171] For example, as shown in FIG. 3, the second reset circuit 02 further comprises a fourth reset sub-circuit 2b. The control terminal of the fourth reset sub-circuit 2b is connected with the second reset control terminal CR<N+4> to receive the second reset control signal CR<N+4>, and the third control signal comprises the second reset control signal. For example, here, the second reset control signal terminal and the first reset control signal terminal are the same signal terminal, both of which are represented by CR<N+4>. Of course, in other embodiments, the two can be different signals that are independently controlled; the first terminal of the fourth reset sub-circuit 2b is connected with the third node Q<N+1>, and the second terminal of the fourth reset sub-circuit 2b is connected with the second control node OFF<N+1>. The fourth reset sub-circuit 2b is configured to respond to the second reset control signal CR<N+4> to utilize the first control node OFF <n>The first reset signal VGL1 transmitted to the second control node OFF<N+1> resets the third node Q<N+1>, so as to realize further reset of the third node Q<N+1> on the basis of reset of the third node Q<N+1> via the second reset sub-circuit 1b.

[0172] For example, with reference to FIG. 3, the third reset sub-circuit 2a comprises a third reset transistor M6, a gate of the third reset transistor M6 is connected with the first reset control end CR<N+4>, a first pole of the third reset transistor M6 is connected with the first node Q <n>connects, a second electrode of the third reset transistor M6 and the first control node OFF <n>The connection; the fourth reset sub-circuit 2b includes a fourth reset transistor M21, the gate of the fourth reset transistor M21 is connected with the second reset control end CR

[0173] The unmentioned features of the circuit structure of the shift register shown in Fig. 3 are the same as those shown in Fig. 1, and can be referred to the previous description.

[0174] Referring to Fig. 3 and Fig. 4, the working process of the shift register unit shown in Fig. 3 has the following differences from the working process of the embodiment shown in Fig. 1.

[0175] In the first stage T1, the first control node OFF <n>The anti-leakage charging signal GVDD2 written into is a high potential signal to increase the voltage of the first control node OFF <n>the first initial transistor M3, the first control transistor M40, the first reset transistor M8, and the third reset transistor M6 are all turned off thoroughly, and leakage of the transistors is prevented. The other working processes of the first stage T1 are the same as those of the first stage of the embodiment shown in FIG. 1, and reference can be made to the previous description.

[0176] In the second stage T2, the first output transistor M17 is turned on in response to the first node Q <n>The first clock signal CLKE1 is turned on by the high potential of the first clock signal CLKE1, and the first clock signal CLKE1 is output from the first output terminal Gl through the first output transistor M17 <n>output, as a first output signal, at the first output terminal G1 <n>the signal of the first node Q is high, so that the first node Q is pulled up to the high potential due to the bootstrap action of the first capacitor C1 <n>the potential of the first node Q is further raised, so that in the second phase T2 the first node Q <n>the potential at the first node Q <n>potential. In this process, the first leakage prevention charging transistor M51 and the second leakage prevention charging transistor M52 are kept on, continuously maintaining the first control node OFF <n>For high potential, to ensure the first node Q <n>the potential of the first control node OFF <n>and the first initial transistor M3, the first control transistor M40, the first reset transistor M8, and the third reset transistor M6, i.e., the first node Q can be held in the second phase T2 <n>The other operation processes of the second stage T2 are the same as those of the second stage of the embodiment shown in Fig. 1, and reference can be made to the previous description.

[0177] The other operation processes of the third stage T3 are the same as those of the third stage of the embodiment shown in Fig. 1, and reference can be made to the previous description.

[0178] In the fourth stage T4, the auxiliary control signal CR<N+4> becomes high potential, the first control transistor M40 and the third reset transistor M6 are both turned on, and the first reset signal VGL1 is transmitted to the first node Q <n>To give the first node Q <n>Reset. As with the embodiment shown in Fig. 3, the first reset signal VGL1 is also written to the first node Q by the first reset transistor M8 <n>To further address the first node Q <n>The reset is performed. The other working processes of the fourth stage T4 are the same as those of the second stage of the embodiment shown in Fig. 1, and reference can be made to the previous description.

[0179] For the embodiment shown in Figs. 3-4, for example, there is also an initialization stage (not shown in Fig. 4) before the first stage T1. In the initialization stage, the initial reset control signal TRST input by the initial reset control end TRST is a high-level signal, and the auxiliary control signal CR<N+4> input by the auxiliary control end CR<N+4> is also a high-level signal, so that the first initial transistor M3, the third initial transistor M20, the first control transistor M40, the third reset transistor M6 and the fourth reset transistor M21 are all turned on, so that the first node Q <n>and a first reset signal terminal VGL1 are electrically connected, the first reset signal VGL1 is written into the first node Q<N> via the first control transistor M40 and the first initial transistor M3, or written into the first node Q<N> via the first control transistor M40 and the third reset transistor M6, the potential of the first node Q<N> is pulled down to a low level, and a reset operation of the first node Q <n>an initial reset of the first control node OFF <n>The first reset signal VGL1 is electrically connected to the first control node OFF via a first resistor R1. <n>The low level of the first node Q<N> is transmitted to the second control node OFF<N+1> and then transmitted to the third node Q<N+1> via the third initial transistor M20 and the fourth reset transistor M21, so as to realize the initial reset of the third node Q<N+1>. Thus, the first output transistor M17 and the second output transistor M23 are turned off in response to the low level of the first node Q<N> and the low level of the third node Q<N+1> respectively, so that even if the first clock signal terminal CLKE1 or the second clock signal terminal CLKE2 inputs a high level at this stage, the first output terminal G1 <n>The high level cannot be output by the first output end G1<N+1> either. It should be noted that during the initialization stage, the transistors not mentioned by him are kept in the off state (i.e. the off state).

[0180] For example, the initial reset control signal TRST can be an on signal such as a high level signal only during the initialization stage, and an off signal such as a low level signal during other periods.

[0181] Figure 5 is a circuit schematic diagram of a shift register unit according to an embodiment of the present disclosure; and Figure 6 is a signal timing diagram corresponding to the operation of the shift register unit shown in Figure 5. The shift register unit shown in Figures 5-6 is different from the embodiment shown in Figures 3-4 in the following aspects.

[0182] In the shift register unit shown in Figure 5, the first sub-shift register further comprises a third output reset circuit 122a and a third output circuit 132a. The third output reset circuit 122a is configured to output a low level to the second node QB <n>under control of the signal of the first output terminal CR <n>The third output circuit 132a is configured to reset the first node Q <n>The third clock signal CLKD1 is output to the third output terminal CR under the control of the signal of the third clock signal output control signal CLKD1 <n>.

[0183] For example, the first end of the first output circuit 131a and the first end of the third output circuit 132a are connected to the same clock signal terminal, and the first clock signal CLKE1 and the third clock signal CLKD1 are the same signal. Of course, in other embodiments, the first clock signal CLKE1 and the third clock signal CLKD1 can also be different signals.

[0184] For example, the third output reset circuit 122a includes a third output reset transistor M18, a gate of the third output reset transistor M18 is connected to the second node QB <n>connects the first electrode of the third output reset transistor M18 to the third output terminal CR <n>The second electrode of the third output reset transistor M18 is connected with the second reset signal terminal VGL2 to receive the second reset signal VGL2 and is configured to reset the third output terminal CR <n>The reset is performed. For example, the level of the second reset signal VGL2 is lower than the level of the first reset signal VGL1, so that in the second stage T2, the second electrode of the third output reset transistor M18 receives a lower potential, so that the third output reset transistor M18 is turned off more thoroughly, preventing the third output reset transistor M18 from leaking. For example, in other embodiments, the second electrode of the third output reset transistor M18 can also be connected to the first reset signal end VGL1 to receive the first reset signal VGL1.

[0185] For example, the third output circuit 132a includes a third output transistor M15 and a third capacitor C3; the gate of the third output transistor M15 is connected to the first node Q <n>The first electrode of the third output transistor M15 is connected with the third clock signal CLKD1 terminal to receive the third clock signal CLKD1, and the second electrode of the third output transistor M15 is connected with the third output end CR <n>The first pole of the third capacitor C3 is connected with the gate of the third output transistor M15, and the second pole of the third capacitor C3 is connected with the second pole of the third output transistor M15.

[0186] Referring to FIGS. 5-6, the working process of the shift register shown in FIGS. 5-6 is different from that of the embodiment shown in FIGS. 5-6 in that, on the basis of the working process shown in FIGS. 3-4, in the second stage T2, the third output transistor M15 is turned on in response to the first node Q <n>The third clock signal CLKD1 is turned on by the high potential of the third clock signal CLKD1, and the third clock signal CLKD1 is output from the third output terminal CR <n>output, as a third output signal, at the third output terminal CR <n>the signal of the third node Q is high, so that the first node Q is made high due to the bootstrap action of the third capacitor C3 <n>the potential of the first node Q is further raised, so that in the second phase T2 the first node Q <n>the potential at the first node Q is higher than the potential at the second node P in the first phase T1 <n>the potential of the first control node OFF. The other working process and principle of the shift register shown in FIGS. 5-6 are the same as those shown in FIGS. 3-4, and reference can be made to the previous description.

[0187] FIG. 7 is a circuit schematic diagram of another shift register unit according to an embodiment of the present disclosure; and FIG. 8 is a signal timing diagram corresponding to the working of the shift register unit shown in FIG. 7. The shift register unit shown in FIGS. 7-8 is different from the embodiment shown in FIGS. 5-6 in the following aspects.

[0188] In the shift register unit shown in FIG. 7, the control end of the first control sub-circuit 3a is connected with the first end of the first control sub-circuit 3a, and the first control node OFF <n>signal as the auxiliary control signal CR<N+4>. In this way, the control terminal of the first control sub-circuit 3a does not need to be externally connected to any control signal terminal, and the first control node OFF <n>discharge, which is favorable to maintain the potential of the first control node OFF<N>, thereby preventing the first node Q <n>The point discharge can avoid the interference of the control process caused by the connection of the control end of the first control sub-circuit 3a to other existing control signal ends, simplify the circuit connection of the shift register and the control method.

[0189] Specifically, for example, the first control sub-circuit 3a includes a first control transistor M40, the gate of the first control transistor M40 is connected with the first pole of the first control transistor M40, the first pole of the first control transistor M40 is connected with the first control node OFF <n>The second electrode of the first control transistor M40 is connected to the first reset signal terminal VGL1.

[0190] Referring to FIGS. 7-8, the operation of the shift register shown in FIGS. 7-8 differs from the operation of the embodiment shown in FIGS. 5-6 as follows.

[0191] In the first phase T1 to the third phase T3, since both the first reset transistor M8 and the third reset transistor M6 are turned off, even when the first control node OFF <n>The first control transistor M40 is turned on for a high potential, and the first node Q <n>The point will also not pass through the first control node OFF <n>discharged through the first control transistor M40. In the fourth stage T4, the auxiliary control signal CR<N+4> becomes a high potential, thereby causing the third reset transistor M6 to be turned on, at which time the first control transistor M40 is also turned on, and the first reset signal VGL1 is transmitted to the first node Q through the first control transistor M40 and the third reset transistor M6 <n>To give the first node Q <n>Reset. Since the first node is on Q <n>The second node QB is charged to a high potential by the first charging transistor M101, the third charging transistor M102, and the second charging transistor M11 <n>Thus, the first reset transistor M8 and the second reset transistor M22 are caused to respond to the second node QB <n>turned on by the high potential of the first reset signal VGL1, and the first reset signal VGL1 is written into the first node Q through the first reset transistor M8 <n>To further address the first node Q <n>a reset is performed; and a first reset signal VGL1 is passed through the first control node OFF <n>to the second control node OFF <N+1>, which in turn is transmitted via the second reset transistor M22 to the third node Q <N+1>, to reset the third node Q <N+1>, i.e. to the low state, due to the first control node OFF <n>OFF with the second control node<N+1> Electrical connection, capable of utilizing the first control node OFF <n>The first reset signal VGL1 transmitted to the second control node OFF<N+1> resets the third node Q<N+1>.

[0192] The other working processes and principles of the shift register shown in FIGS. 7-8 are the same as those shown in FIGS. 5-6, and reference can be made to the previous description.

[0193] FIG. 9 is a circuit schematic diagram of another shift register unit according to an embodiment of the present disclosure, and FIG. 10 is a signal timing diagram corresponding to the working of the shift register unit shown in FIG. 9. The shift register unit shown in FIGS. 9-10 is different from the embodiment shown in FIGS. 5-6 in the following aspects.

[0194] In the shift register unit shown in FIG. 9, the first control circuit 03 includes a second control sub-circuit 1c and a third control sub-circuit 2c. The control end of the second control sub-circuit 1c is connected to the second node QB <n>connects, a first end of the second control sub-circuit 1c with the first control node OFF <n>The second end of the second control sub-circuit 1c is connected with the first reset signal terminal VGL1; the control end of the third control sub-circuit 2c is connected with the first reset control terminal CR<N+4>, and the first end of the third control sub-circuit 2c is connected with the first control node OFF <n>The second end of the third control sub-circuit 2c is connected with the first reset signal terminal VGL1; the second control signal includes a second node QB <n>a signal of the first reset control signal CR<N+4>.

[0195] For example, the second control sub-circuit 1c includes a second control transistor M9, a gate of the second control transistor M9 is connected with the second node QB <n>connects, a first electrode of the second control transistor M9 and the first control node OFF <n>The second control terminal of the third control transistor M7 is connected with the first reset control terminal CR<N+4>, and the first control terminal of the third control transistor M7 is connected with the first control node OFF. The third control sub-circuit 2c further includes a fourth control transistor M8, and the gate of the fourth control transistor M8 is connected with the first reset control terminal CR<N+4>. The first control terminal of the fourth control transistor M8 is connected with the first control node OFF, and the second control terminal of the fourth control transistor M8 is connected with the first reset signal terminal VGL1, for example, directly connected with the first reset signal terminal VGL1 through a wire. <n>The second electrode of the third control transistor M7 is connected with the first reset signal terminal VGL1, for example, directly connected with the first reset signal terminal VGL1 through a wire.

[0196] For example, the shift register unit shown in FIG. 9 does not include the above-mentioned first control circuit 3a, i.e., does not include the above-mentioned first control transistor M40.

[0197] In at least one embodiment, for example, as shown in FIG. 9, the first initial reset circuit 170a can include a plurality of transistors, for example, including a first initial transistor M3 and a second initial transistor M41. The gate of the first initial transistor M3 and the gate of the second initial transistor M41 are both connected with the initial reset control terminal TRST, the first electrode of the first initial transistor M3 is connected with the first node Q <n>The second terminal of the first initial transistor M3 is connected to the first terminal of the second initial transistor M41, and the second terminal of the second initial transistor M41 is connected to the first reset signal terminal VGL1; the second initial reset circuit 170b includes a third initial transistor M20, the gate of the third initial transistor M20 is connected to the initial reset control terminal TRST, and the first terminal of the third initial transistor M20 is connected to the third node Q.<N+1> Connection, the second terminal of the third initial transistor M20 is OFF with the second control node.<N+1> connect.

[0198] The operation of the shift register shown in Figure 9-10 differs from that of the embodiment shown in Figure 7-8 in the following ways. Referring to Figure 9-10, in the first stage T1, the first node Q is... <n>Charging such that the first node Q <n>The process of the potential of the first node Q being a high potential is the same as in the previous embodiment, and the second reset control signal CR<N+4> is a low potential to make the third reset transistor M6 and the third control transistor M7 both off, and the fourth reset transistor M21 is also off; the initial reset control signal TRST is a low potential to make the first initial transistor M3 and the second initial transistor M41 both off, at this time, since the first node Q is a high potential in response to the first node Q <n>high potential, the first leakage-preventing charging transistor M51 and the second leakage-preventing charging transistor M52 are turned on, and the first control node OFF <n>The anti-leakage charging signal GVDD2 written into is a high potential signal to increase the voltage of the first control node OFF <n>the second electrode of the third reset transistor M6, the second electrode of the first reset transistor M8, the first electrode of the second control transistor M9, and the first electrode of the third control transistor M7, so that the gate-source voltages of the third reset transistor M6, the first reset transistor M8, the second control transistor M9, and the third control transistor M7 are all negative, so that the third reset transistor M6, the first reset transistor M8, the second control transistor M9, and the third control transistor M7 are all turned off more thoroughly, preventing leakage of these transistors. The anti-leakage charging signal GVDD2 passes through the first control node OFF <n>The signal is transmitted to the second control node OFF < N + 1 >, thereby increasing the potential of the second electrode of the second reset transistor M22 connected to the second control node OFF < N + 1 >, so that the gate-source voltage of the second reset transistor M22 is negative, thereby making the second reset transistor M22 turn off more completely, preventing the second reset transistor M22 from leaking.

[0199] In the second stage T2, the first output transistor M17 responds to the first node Q <n>The first clock signal CLKE1 is turned on by the high potential of the first clock signal CLKE1, and the first clock signal CLKE1 is output from the first output terminal Gl through the first output transistor M17 <n>output, as a first output signal, at the first output terminal G1 <n>the signal of the first node Q is high, so that the first node Q is brought to a high potential due to the bootstrap action of the first capacitor C1 <n>the potential of the first node Q is further raised, so that the first node Q <n>the potential at the first node Q is higher than the potential at the second node P in the first phase T1 <n>potential. In this process, the first leakage prevention charging transistor M51 and the second leakage prevention charging transistor M52 are kept on, continuously maintaining the first control node OFF <n>For high potential, to ensure the first node Q <n>the potential of the first control node OFF <n>, any one of the first reset transistor M8, the second control transistor M9, the third reset transistor M6, and the third control transistor M7 leaks current, i.e., the first node Q <n>The other operation processes of the second stage T2 are the same as those of the second stage of the embodiment shown in Fig. 1, and reference can be made to the previous description.

[0200] The other operation processes of the third stage T3 are the same as those of the third stage of the previous embodiment, and reference can be made to the previous description.

[0201] In the fourth stage T4, the auxiliary control signal CR<N+4> becomes high potential, so that the third reset transistor M6 and the third control transistor M7 are both turned on, and the first reset signal VGL1 is transmitted to the first node Q <n>To give the first node Q <n>Reset. Since the first node is on Q <n>The second node QB is charged to a high potential by the first charging transistor M101, the third charging transistor M102, and the second charging transistor M11 <n>Thus, the first reset transistor M8 and the second control transistor M9 are made to respond to the second node QB <n>turned on by the high potential of the first reset signal VGL1, and the first reset signal VGL1 is written into the first node Q through the first reset transistor M8 and the second control transistor M9 <n>To further address the first node Q <n>Reset is performed. Also, the second reset transistor M22 is responsive to the second node QB <n>turned on by the high potential of the first reset signal VGL1 via the first control node OFF <n>to the second control node OFF <N+1>, which in turn is transmitted via the second reset transistor M22 to the third node Q <N+1>, to reset the third node Q <N+1>, i.e. to the low state, due to the first control node OFF <n>OFF with the second control node<N+1> Electrical connection, capable of utilizing the first control node OFF <n>The first reset signal VGL1 transmitted to the second control node OFF<N+1> resets the third node Q<N+1>. Meanwhile, since the fourth reset transistor M21 is also turned on in response to the high level of the auxiliary control signal CR<N+4>, the first reset signal VGL1 transmitted to the second control node OFF<N+1> can also be transmitted to the third node Q<N+1> via the fourth reset transistor M21 to further reset the third node Q<N+1>. The other working processes of the fourth stage T4 are the same as those of the fourth stage of the previous embodiments, and reference can be made to the previous description.

[0202] For the embodiment shown in FIGS. 9-10, for example, there is also an initialization stage (not shown in FIG. 10) before the first stage T1. In the initialization stage, the initial reset control signal TRST input to the initial reset control end TRST is a high level signal, so that the first initial transistor M3, the second initial transistor M41 and the third initial transistor M20 are all turned on; the second reset control signal CR<N+4> input to the second reset control end CR<N+4> is also a high signal, so that the third reset transistor M6, the third control transistor M7 and the fourth reset transistor M21 are all turned on, so that the first node Q <n>and a first reset signal terminal VGL1 are electrically connected, the first reset signal VGL1 is written into the first node Q<N> via the first initial transistor M3 and the second initial transistor M41, and is written into the first node Q<N> via the third reset transistor M6 and the third control transistor M7, the potential of the first node Q<N> is pulled down to a low level, and the first node Q <n>an initial reset of the first control node OFF <n>The first reset signal VGL1 is electrically connected to the first control node OFF via a first resistor R1. <n>The low level of the first node Q<N> is transmitted to the second control node OFF<N+1> and then transmitted to the third node Q<N+1> via the third initial transistor M20 and the fourth reset transistor M21, so as to realize the initial reset of the third node Q<N+1>. Thus, the first output transistor M17 and the second output transistor M23 are turned off in response to the low level of the first node Q<N> and the low level of the third node Q<N+1> respectively, so that even if the first clock signal terminal CLKE1 or the second clock signal terminal CLKE2 inputs a high level at this stage, the first output terminal G1 <n>The high level cannot be outputted by the first output terminal G1<N+1> either. It should be noted that during the initialization stage, the transistors not mentioned by him are kept in the off state (i.e. the off state).

[0203] For example, the initial reset control signal TRST can be an open signal such as a high level signal only in the initialization stage, and a closed signal such as a low level signal in other periods.

[0204] For example, the initial reset control signal TRST can be an open signal such as a high level signal only in the initialization stage, and a closed signal such as a low level signal in other periods.

[0205] The other working processes and principles of the shift register shown in FIGS. 9-10 are the same as those shown in FIGS. 7-8, and reference can be made to the previous description.

[0206] FIG. 11 is a circuit schematic diagram of another shift register unit provided by an embodiment of the present disclosure. The shift register unit shown in FIG. 11 is different from the embodiment shown in FIG. 9 in the following aspects.

[0207] In the shift register unit shown in FIG. 11, the initial reset control terminal TRST is multiplexed as an auxiliary control terminal. The second initial transistor M41 is multiplexed as the first control transistor, i.e. in FIG. 11, the first control transistor and the second initial transistor are the same transistor, which are both denoted by the reference sign M41. The gate of the second initial transistor M41 is connected with the initial reset control terminal TRST, and the first pole of the first initial transistor M3 is connected with the first node Q <n>The second terminal of the first initial transistor M3 is connected to the first terminal of the second initial transistor M41, and both the second terminal of the first initial transistor M3 and the first terminal of the second initial transistor M41 are connected to the first control node OFF <n>connected, e.g. directly with a wire, to the first control node OFF <n>Connection. That is, the shift register unit shown in Fig. 11 connects the second electrode of the first initial transistor M3 and the first electrode of the second initial transistor to the first control node OFF on the basis of the shift register unit shown in Fig. 9 <n>.

[0208] The operation timing chart of the shift register unit shown in Fig. 11 can be the same as that shown in Fig. 10, and the operation of the shift register unit shown in Fig. 11 is different from that of the embodiment shown in Figs. 9-10 in the following points.

[0209] Referring to Fig. 11, in the first stage T1, the first node Q <n>After being charged, in response to the first node Q <n>high potential, the first leakage-preventing charging transistor M51 and the second leakage-preventing charging transistor M52 are turned on, and the first control node OFF <n>The anti-leakage charging signal GVDD2 written into is a high potential signal, so that, in addition to improving the connection to the first control node OFF <n>the potential of the second electrode of the third reset transistor M6, the second electrode of the first reset transistor M8, the first electrode of the second control transistor M9, and the first electrode of the third control transistor M7, in addition to the potential of the first electrode of the third reset transistor M6, the second electrode of the first reset transistor M8, the first electrode of the second control transistor M9, and the first electrode of the third control transistor M7 <n>The first initial transistor M3 and the second initial transistor M41 are turned off more thoroughly, and the first initial transistor M3 and the second initial transistor M41 are further prevented from leaking current.

[0210] In the second stage T2, the first output transistor M17 is turned on in response to the first node Q <n>The first clock signal CLKE1 is turned on by the high potential of the first clock signal CLKE1, and the first clock signal CLKE1 is output from the first output terminal Gl through the first output transistor M17 <n>output, as a first output signal, at the first output terminal G1 <n>the signal of the first node Q is high, so that the first node Q is pulled up to the high potential due to the bootstrap action of the first capacitor C1 <n>the potential of the first node Q is further raised, so that in the second phase T2 the first node Q <n>the potential at the first node Q <n>potential. In this process, the first leakage prevention charging transistor M51 and the second leakage prevention charging transistor M52 are kept on, continuously maintaining the first control node OFF <n>For high potential, initial reset control signal and TRST, to ensure the first node Q <n>the potential of the first control node OFF <n>, any one of the first initial transistor M3, the second initial transistor M41 (i.e., the first control transistor), the first reset transistor M8, the third reset transistor M6, the third control transistor M7, and the second control transistor M9 leaks current, thereby being able to hold the first node Q <n>The other operation processes of the second stage T2 are the same as those of the second stage of the previous embodiment, and reference can be made to the previous description.

[0211] The other operation processes of the third stage T3 are the same as those of the third stage of the embodiment shown in FIGS. 9-10, and reference can be made to the previous description.

[0212] In the fourth stage T4, the auxiliary control signal CR<N+4> becomes high potential, so that the third reset transistor M6 and the third control transistor M7 are both turned on, and the first reset signal VGL1 is transmitted to the first node Q <n>To give the first node Q <n>Reset; the initial reset control signal TRST can be an off signal, for example, a low potential, so that the first initial transistor M3 and the second initial transistor M41 (i.e., the first control transistor) are both turned off, and the first node Q <n>The reset is performed. For example, in other embodiments, in the fourth stage T4, the initial reset control signal TRST can also be an on signal, for example, a high potential, so that the first initial transistor M3 and the second initial transistor M41 (i.e., the first control transistor) are both turned on, and the first reset signal VGL1 can also be transmitted to the first node Q through the first initial transistor M3 and the second initial transistor M41 (i.e., the first control transistor) <n>To give the first node Q <n>Reset.

[0213] The other working processes of the fourth stage T4 are the same as those of the fourth stage of the embodiment shown in FIGS. 9-10, and reference can be made to the previous description.

[0214] For the embodiment shown in FIG. 11, for example, there is also an initialization stage before the first stage T1, and the working process of the initialization stage is the same as that of the fourth stage of the embodiment shown in FIGS. 9-10, and reference can be made to the previous description.

[0215] FIG. 12 is a circuit schematic diagram of another shift register unit provided by an embodiment of the present disclosure. The shift register unit shown in FIG. 12 is different from the embodiment shown in FIG. 7 in the following aspects.

[0216] Referring to FIG. 12, on the basis of the embodiment shown in FIG. 7, some of the transistors in the shift register adopt a double-gate structure. For example, the first output transistor M17, the first output reset transistor M18, the second output transistor M23, and the second output reset transistor M24 adopt a double-gate structure and respectively include a bottom gate and a top gate, so as to enhance the output capability of the above-mentioned transistors adopting a double-gate structure and reduce the size of the transistors. For example, the width-length ratio of the above-mentioned transistors adopting a double-gate structure is 300 / 6, of course, the width-length ratio here is only exemplary and is not limited to this value.

[0217] In any embodiment of the present disclosure, the first output transistor M17, the first output reset transistor M18, the second output transistor M23, and the second output reset transistor M24 can adopt a double-gate structure. Of course, in any embodiment of the present disclosure, other transistors can also be designed as a double-gate structure including a bottom gate and a top gate according to actual needs.

[0218] The other features of the shift register unit shown in FIG. 12 are the same as those of the embodiment shown in FIG. 7, and reference can be made to the previous description.

[0219] FIG. 13 is a circuit schematic diagram of another shift register unit provided by an embodiment of the present disclosure. The shift register unit shown in FIG. 13 is different from the embodiment shown in FIG. 11 in the following aspects.

[0220] Referring to FIG. 13, on the basis of the embodiment shown in FIG. 11, some of the transistors in the shift register adopt a double-gate structure. For example, the first output transistor M17, the first output reset transistor M18, the second output transistor M23, and the second output reset transistor M24 adopt a double-gate structure and respectively include a bottom gate and a top gate, so as to enhance the output capability of the above-mentioned transistors adopting a double-gate structure and reduce the size of the transistors. For example, the width-length ratio of the above-mentioned transistors adopting a double-gate structure is 300 / 6, of course, the width-length ratio here is only exemplary and is not limited to this value.

[0221] In any embodiment of the present disclosure, the first output transistor M17, the first output reset transistor M18, the second output transistor M23 and the second output reset transistor M24 can all be designed as double-gate structures. Of course, in any embodiment of the present disclosure, other transistors can also be designed as double-gate structures including bottom gate and top gate according to actual needs.

[0222] The other features of the shift register unit shown in FIG. 13 are the same as those of the embodiment shown in FIG. 11. Please refer to the previous description.

[0223] FIG. 14 is a circuit schematic diagram of another shift register unit according to an embodiment of the present disclosure. The shift register unit shown in FIG. 14 is different from the embodiment shown in FIG. 11 in the following aspects.

[0224] Referring to FIG. 14, on the basis of the embodiment shown in FIG. 11, the first input signal end adopts a direct current signal GVDD3 as the first input signal CR <n-2>For example, further, the first input control signal end and the second input control signal end can each provide a direct current signal GVDD3, that is, the first input control signal and the second input control signal are each the direct current signal GVDD3, and the gate of the first input transistor M1, the gate of the second input transistor M2 and the gate of the second input transistor M19 are each input with the direct current signal GVDD3. Since the direct current signal GVDD3 is a constant power current, using the direct current signal GVDD3 as the first input signal and / or the first and second input control signals can make the input current capacity of the first input circuit 110a and the second input circuit 110b stronger.

[0225] The other features of the shift register unit shown in FIG. 14 are the same as those of the embodiment shown in FIG. 11, and reference can be made to the previous description.

[0226] FIG. 15 is a circuit schematic diagram of another shift register unit according to an embodiment of the present disclosure. The shift register unit shown in FIG. 15 is different from the embodiment shown in FIG. 14 in the following aspects.

[0227] Referring to FIG. 15, since the first input signal end uses the direct current signal GVDD3 as the first input signal CR <n-2>For example, further, the first input control signal terminal and the second input control signal terminal can each provide a direct current signal GVDD3. Using the direct current signal GVDD3 as the first input signal and / or the first and second input control signals can make the input current of the first input circuit 110a and the second input circuit 110b have stronger capability, and thus the first input circuit 110a can only have one transistor, i.e., the first input transistor M1, and the second input transistor M2 in FIG. 14 is removed.

[0228] The first input control signal and the second input control signal are each a direct current signal GVDD3, and the gate of the first input transistor M1 and the gate of the second input transistor M19 are each input with the direct current signal GVDD3.

[0229] The shift register unit shown in FIG. 15 has other features same as the embodiment shown in FIG. 14, and reference can be made to the previous description.

[0230] The shift register unit provided by at least one embodiment of the present disclosure includes an input circuit, a first output reset circuit, a first reset circuit, a first output circuit, and a first control circuit. The input circuit is configured to charge a first node in response to an input control signal; the first output reset circuit is configured to reset a first output terminal under the control of a signal of a second node; the first output circuit is configured to output a first clock signal to the first output terminal under the control of a signal of the first node; the first reset circuit and the first control circuit are connected to a first control node, and the first control circuit is connected between the first control node and a first reset signal terminal; and the first reset circuit and the first control circuit are configured to reset the first node with a first reset signal from the first reset signal terminal in response to a first control signal and a second control signal, respectively.

[0231] For example, FIG. 16 is a circuit schematic diagram of another shift register unit provided by an embodiment of the present disclosure, and FIG. 17 is a signal timing diagram corresponding to the operation of the shift register unit shown in FIG. 16. Referring to FIG. 16, the shift register unit includes an input circuit 110, a first output reset circuit 120, a first reset circuit 01, a first output circuit 130, and a first control circuit 03. The input circuit 110 is configured to charge a first node Q <n>Charging is performed. In the driving circuit of the shift register unit provided in the embodiments of the present disclosure including a plurality of cascades, the first stage input control signal STV is the initial driving signal. The first output reset circuit 120 is configured to reset the second node QB <n>under control of a signal of the first output circuit 130. The first output circuit 130 is configured to reset the first output terminal GOUT at the first node Q <n>The first clock signal CLKD1 is output to the first output terminal GOUT under the control of the signal of the first control circuit 03. The first reset circuit 01 and the first control circuit 03 are connected to the first control node OFF <n>, the first control circuit 03 is connected to the first control node OFF <n>between the first reset signal terminal VGL1. The first reset circuit 01 and the first control circuit 03 are configured to utilize the first reset signal VGL1 from the first reset signal terminal VGL1 to the first node Q <n>Reset is performed.

[0232] According to the shift register unit provided by the embodiment of the present disclosure, the first control circuit 03 is connected to the first control node OFF <n>between the first reset signal end VGL1, the first reset signal VGL1 reaches the first control node OFF via the first control circuit 03 <n>, and then transmitted to the first node Q via the first reset circuit 01 <n>Thus, the first node Q <n>The reset is performed during the operation of the shift register unit, and the first control node OFF <n>The first reset signal terminal VGL1 is directly connected through a wire, so that the first control node OFF can be held by the first control circuit 03 <n>the potential of the first control node OFF <n>When the high potential is written, on the one hand, the first node Q <n>By the first control node OFF <n>discharge to maintain the first node Q <n>the potential of the first control node OFF <n>Transistor leakage due to direct electrical connection.

[0233] For example, as shown in FIG. 16, the first reset circuit 01 includes a first reset sub-circuit 1a, a control end of the first reset sub-circuit 1a being connected with the second node QB <n>connects a first end of the first reset sub-circuit 1a to the first node Q <n>connects, a second end of the first reset sub-circuit 1a and the first control node OFF <n>The connection, the first reset sub-circuit 1a is configured to connect the second node QB <n>under control of a signal of the first control node OFF <n>a first reset signal VGL1 to a first node Q <n>The first control signal includes the second node QB <n>signal.

[0234] For example, as shown in FIG. 16, the first control circuit 03 includes a first control sub-circuit 3a. For example, in FIG. 16, the first control sub-circuit 3a is taken as the first control circuit 03, and of course, in other embodiments, the first control circuit 03 can also include other sub-circuits. Referring to FIG. 16, the control end of the first control sub-circuit 3a is connected with the auxiliary control end STD to receive the auxiliary control signal STD, and the second control signal includes the auxiliary control signal STD, the first end of the first control circuit 03 is connected with the first control node OFF <n>The second end of the first control circuit 03 is connected with the first reset signal end VGL1.

[0235] Thus, the first control sub-circuit 3a can be turned on in response to the auxiliary control signal STD, and the first reset sub-circuit 1a can be turned on in response to the second node QB <n>under the control of the signal of the first reset signal terminal VGL1, so that the first reset signal VGL1 from the first reset signal terminal VGL1 can pass through the first control sub-circuit 3a, the first control node OFF <n>and the first reset sub-circuit 1a transmits to the first node Q <n>to the first node Q <n>A reset is performed.

[0236] For example, as shown in FIG. 16, the shift register unit further includes a first initial reset circuit 170. The first initial reset circuit 170 is connected with the initial reset control terminal TRST to receive an initial reset control signal TRST, and is configured to perform an initial reset on the first node Q <n>Reset is performed. A plurality of cascaded shift register units 100 described above can be used to form a driving circuit. When the driving circuit is used to drive a display substrate or a display panel, for example, at power-on, the first initial reset circuit 170 in each stage of the shift register unit can respond to an initial reset control signal TRST to reset the first node Q <n>the potential of the first node Q <n>The potential of the first node Q <n>multiple output problems caused by potential drift of the shift register unit.

[0237] For example, referring to FIG. 16, the shift register unit further includes a leakage prevention charging circuit 150. A control terminal of the leakage prevention charging circuit 150 is connected to the first node Q <n>The first end of the leakage prevention charging circuit 150 is connected with the leakage prevention charging signal terminal GVDD2 to receive the leakage prevention charging signal GVDD2, and the second end of the leakage prevention charging circuit 150 is connected with the first control node OFF <n>The connection, the leakage-proof charging circuit 150 is configured to be connected to the first node Q <n>under control of the signal of the first control node OFF <n>An input leakage-prevention charging signal GVDD2 is input. For example, the leakage-prevention charging signal GVDD2 is a high-level signal, for example, the potential of the leakage-prevention charging signal GVDD2 is not lower than the first node Q <n>the potential of the first node. Thus, the first control node OFF <n>The write prevention current charging signal GVDD2 is written so as to make the first control node OFF <n>the potential of the first node Q is a high potential. At this time, on one hand, it is possible to prevent the first node Q <n>By the first control node OFF <n>discharging, on the other hand, the potential of the first node, and, on the other hand, increasing the potential of the first electrode (or of the second electrode) of the transistor connected to the first control node, so as to make the gate-source voltage of the transistor negative, thus making the transistor turn off more completely, preventing the leakage current of the transistor, i.e. preventing the current flowing from the first node to the second node when the first control node is OFF <n>The transistor leakage of the direct electrical connection, for example, can prevent the transistor leakage in the first reset sub-circuit 1a and the first control sub-circuit 3a.

[0238] For example, as shown in FIG. 16, the shift register unit further includes a second node control circuit 160. The second node control circuit 160 includes a second node charging circuit 161 and a second node reset circuit 162. The second node charging circuit 161 is connected with the second node charging control end GVDD1 to receive a second node charging control signal GVDD1, with the second node charging signal end GVDD1 to receive a second node charging signal GVDD1, and with the second node QB <n>connected, the second node charging circuit 161 is configured to charge the second node QB with the second node charging signal GVDD1 in response to the second node charging control signal GVDD1 <n>The second node charging is performed. For example, taking the second node charging control signal and the second node charging control signal as the same signal GVDD1 as an example, for example, the control end of the second node charging circuit 161 is connected with the first end of the second node charging circuit 161, that is, the two are connected to the same signal end to receive the same signal GVDD1. Of course, in other embodiments, the control end of the second node charging circuit 161 can not be electrically connected with the first end of the second node charging circuit 161, and the second node charging control signal and the second node charging control signal can be different signals and are independently controlled respectively.

[0239] For example, referring to FIG. 16, the second node reset circuit 162 is connected with the first node Q <n>and a second node QB <n>is connected to the first reset signal terminal VGL1 to receive the first reset signal VGL1, and the second node reset circuit 162 is configured to be connected to the first node Q <n>the second node QB with the first reset signal VGL1 under the control of the potential of the first node QB <n>A reset is performed.

[0240] For example, as shown in Fig. 16, the first input circuit 110 is also connected to the first control node OFF <n>Connection. Of course, in other embodiments, the first input circuit 110 can also not be connected to the first control node OFF <n>Connection.

[0241] For example, referring to FIG. 16, the shift register unit further comprises an auxiliary reset circuit 180. A control end of the auxiliary reset circuit 180 is connected with the input control end to receive the input control signal STV, and a first end of the auxiliary reset circuit 180 is connected with the second node QB <n>The second end of the connection, the auxiliary reset circuit 180 is connected with the first reset signal end VGL1 to receive the first reset signal VGL1, and the auxiliary reset circuit 180 is configured to input the first reset signal VGL1 to the second node QB in response to the first input control signal STV <n>to utilize the first reset signal VGL1 to the second node QB <n>The reset is performed. Thus, when the first input control signal is an ON signal such as a high potential, the auxiliary reset circuit 180 is turned on, and thereby the second node QB <n>the potential of the first node Q <n>the potential of the first node QB becomes high potential, and the process of the potential of the first node QB becoming high potential is assisted, and the first node QB <n>The potential of the second node QB becomes a high potential, and the input ability of the first input circuit is enhanced.

[0242] Of course, in other embodiments, the auxiliary reset circuit 180 can also be removed.

[0243] The specific structure of the shift register unit shown in Fig. 16 will be described below.

[0244] For example, as shown in Fig. 16, the first reset sub-circuit 1a includes a first reset transistor M8, a gate of the first reset transistor M8 being connected to the second node QB <n>connects, a first electrode of the second reset transistor and the first node Q <n>connects, a second electrode of the first reset transistor M8 and the first control node OFF <n>Connection.

[0245] For example, as shown in FIG. 16, the first control sub-circuit 3a includes a first control transistor M40, a gate of the first control transistor M40 is connected with the auxiliary control end STD, a first electrode of the first control transistor M40 is connected with the first control node OFF <n>The second electrode of the first control transistor M40 is connected with the first reset signal terminal VGL1.

[0246] For example, as shown in FIG. 16, the second node charging circuit 161 includes a first charging transistor M101 and a second charging transistor M11. The second node charging signal terminal GVDD1 is connected with the second node charging control terminal GVDD1. The first electrode of the first charging transistor M101 is connected with the second node charging signal terminal GVDD1, that is, the first electrode of the first charging transistor M101 is connected with the gate electrode of the first charging transistor M101. The second electrode of the first charging transistor M101 is connected with the gate electrode of the second charging transistor M11. The first electrode of the second charging transistor M11 is connected with the second node charging signal terminal GVDD1, and the second electrode of the second charging transistor M11 is connected with the second node QB <n>Connection.

[0247] In the embodiment shown in FIG. 16, the second node charging signal and the second node charging control signal are the same signal GVDD1. For example, the second node charging control signal GVDD1 is a constant high high-level signal.

[0248] Of course, in other embodiments, the second node charging signal terminal GVDD1 can not be connected with the second node charging control terminal GVDD1, and the second node charging signal and the second node charging control signal can be different signals independently controlled. In this case, the first electrode of the first charging transistor M101 is not connected with the gate of the first charging transistor M101.

[0249] For example, in some embodiments, as shown in FIG. 16, the second node charging circuit 161 can further include a third charging transistor M102. The third charging transistor M102 is connected in series with the first charging transistor M101, and the second electrode of the first charging transistor M101 is connected with the gate of the second charging transistor M11 via the third charging transistor M102. The gate of the third charging transistor M102 is also connected with the second node charging control terminal GVDD1, the first electrode of the third charging transistor M102 is connected with the second electrode of the first charging transistor M101, and the second electrode of the third charging transistor M102 is connected with the gate of the second charging transistor M11.

[0250] In some embodiments, the second node charging circuit 161 can only have the above-mentioned first charging transistor M101, but does not include the third charging transistor M102.

[0251] For example, as shown in FIG. 16, the second node reset circuit 162 includes a first transistor M12 and a second transistor M13. The gate of the first transistor M12 and the gate of the second transistor M13 are both connected with the first node Q <n>The first electrode of the first transistor M12 is connected with the gate electrode of the second charging transistor and the second electrode of the first charging transistor M101, the second electrode of the first transistor M12 is connected with the second reset signal terminal VGL2, the first electrode of the second transistor M13 is connected with the second node QB <n>The second electrode of the second charging transistor M11 is connected with the second electrode of the second transistor M13, and the second electrode of the second transistor M13 is connected with the first reset signal terminal VGL1.

[0252] For example, the potential of the second reset signal VGL2 provided by the second reset signal terminal VGL2 is lower than the potential of the first reset signal VGL1 provided by the first reset signal terminal VGL1, the second electrode of the first transistor M12 is connected with the second reset signal terminal VGL2, thereby, the voltage of the first node Q <n>When the potential of the first node Q is a low potential, the second electrode of the first transistor M12 receives a lower potential, so that the first transistor M12 is turned off more completely, preventing current leakage of the first transistor M12.

[0253] Alternatively, in another embodiment, for example, the second electrode of the first transistor M12 can also be connected to the first reset signal terminal VGL1.

[0254] For example, as shown in FIG. 16, the input circuit 110 includes a first input transistor M1. The gate of the first input transistor M1 is connected to the input control signal terminal STV to receive the input control signal STV, and the first electrode of the first input transistor M1 is connected to the input signal terminal STV to receive the input signal STV. For example, the input signal STV can be an alternating current signal or a direct current signal. The second electrode of the first input transistor M1 is connected to the first node Q <n>The connection is to utilize the input signal STV on the first node Q <n>The charging is performed. For example, the first electrode of the first input transistor M1 is connected to the gate of the first input transistor M1, so that the input control signal STV is multiplexed as the input signal STV. Of course, in other embodiments, the first electrode of the first input transistor M1 can not be connected to the gate of the first input transistor M1, and the input control signal STV and the input signal STV are different, independently controlled signals, respectively.

[0255] For example, as shown in FIG. 16, the input circuit 110 further includes a second input transistor M2. The second input transistor M2 is connected in series between the second electrode of the first input transistor M1 and the first node Q <n>between the first and second input transistors M1, M2, the second electrode of the first input transistor M1 is coupled to the first node Q via the second input transistor M2 <n>Connection. The gate of the second input transistor M2 is also connected to the input control signal terminal STV, the first pole of the second input transistor M2 is connected to the second pole of the first input transistor M1, and the second pole of the second input transistor M2 is connected to the first node Q <n>Connection.

[0256] For example, in another embodiment, different from FIG. 16 is that the gate of the first input transistor M1 is connected with the first pole of the first input transistor M1 and connected with the input control signal end STV to receive the input control signal STV, the second pole of the first input transistor M1 is directly connected with the first node Q <n>is connected to input the control signal STV as the input signal STV, that is, the second input transistor M2 is removed.

[0257] For example, as shown in Fig. 16, the first output circuit 130 includes a first output transistor M15 and a first capacitor Cl. The gate of the first output transistor M15 is connected to the first node Q <n>The first pole of the first output transistor M15 is connected with the first clock signal CLKD1 terminal to receive the first clock signal CLKD1, and the second pole of the first output transistor M15 is connected with the first output end GOUT; the first pole of the first capacitor C1 is connected with the gate of the first output transistor M15, and the second pole of the first capacitor C1 is connected with the second pole of the first output transistor M15.

[0258] For example, as shown in FIG. 16, the first output reset circuit 120 includes a first output reset transistor M16, the gate of the first output reset transistor M16 is connected with the second node QB <n>The first electrode of the first output reset transistor M16 is connected with the first output terminal GOUT, and the second electrode of the first output reset transistor M16 is connected with the first reset signal terminal VGL1 to receive the first reset signal VGL1.

[0259] For example, in another embodiment, different from FIG. 16, the second electrode of the first output reset transistor M16 is connected with the second reset signal VGL2 terminal to receive the second reset signal VGL2, and is configured to reset the first output terminal GOUT by using the second reset signal VGL2. For example, the level of the second reset signal VGL2 is lower than the level of the first reset signal VGL1. Thus, the first output terminal GOUT can be provided with a lower low level as a reset signal, so that when the output signal is low in the non-output stage, the potential of the first output terminal GOUT is further pulled down, and the effect of output noise reduction can be achieved.

[0260] For example, the auxiliary reset circuit 180 includes an auxiliary reset transistor M14, the gate electrode of the auxiliary reset transistor M14 is connected with the input control terminal STV, the first electrode of the auxiliary reset transistor M14 is connected with the second node QB <n>The second electrode of the connection auxiliary reset transistor M14 is connected with the first reset signal terminal VGL1.

[0261] For example, the leakage prevention charging circuit 150 includes a leakage prevention charging transistor M5, the gate electrode of the leakage prevention charging transistor is connected with the first node Q <n>The first electrode of the leakage-proof charging transistor is connected with the leakage-proof charging signal terminal GVDD2, and the second electrode of the leakage-proof charging transistor is connected with the first control node OFF <n>Connection. That is, in at least one embodiment, the leakage prevention charging transistor can simply be a transistor.

[0262] For example, in the embodiment shown in FIG. 16, the leakage prevention charging transistor includes a first leakage prevention charging transistor M51 and a second leakage prevention charging transistor M52. The gate of the first leakage prevention charging transistor M51 and the gate of the second leakage prevention charging transistor M52 are both connected to the first node Q <n>The first electrode of the first leakage-preventing charging transistor M51 is connected with the leakage-preventing charging signal terminal GVDD2, the second electrode of the first leakage-preventing charging transistor M51 is connected with the first electrode of the second leakage-preventing charging transistor M52, the second electrode of the second leakage-preventing charging transistor M52 is connected with the first control node OFF <n>connected. That is, the first leakage prevention charging transistor M51 and the second leakage prevention charging transistor M52 are connected in series between the leakage prevention charging signal terminal GVDD2 and the first node Q <n>between.

[0263] For example, in another embodiment provided shift register unit, different from that shown in Figure 16, the shift register unit also includes a second output reset circuit and a second output circuit (can refer to similar to the design of the second output reset circuit and the second output circuit in Figure 5); the second output reset circuit is configured to reset the second node QB <n>The second output terminal is reset under the control of the signal; the second output circuit is configured to be at the first node Q. <n>The second clock signal is output to the second output terminal under the control of a signal.

[0264] For example, the first terminal of the first output circuit 130 and the first terminal of the second output circuit are connected, and the first clock signal CLKD1 and the second clock signal are the same signal.

[0265] For example, as shown in FIG. 1, the first initial reset circuit 170 includes a first initial transistor M3. The gate of the first initial transistor M3 is connected with the initial reset control terminal TRST, the first pole of the first initial transistor M3 is connected with the first node Q <n>connects, a second electrode of the first initial transistor M3 and the first control node OFF <n>The first initial transistor M3, the first control transistor M40, and the first reset transistor M8 are connected to the first control node OFF. That is, the second electrode of the first initial transistor M3, the first electrode of the first control transistor M40, and the second electrode of the first reset transistor M8 are connected to the first control node OFF <n>.

[0266] The operation principle of the shift register unit shown in FIG. 16 will be described below with reference to a signal timing chart shown in FIG. 17. In four stages of a first stage T1, a second stage T2, a third stage T3, and a fourth stage T4 shown in FIG. 17, the shift register unit operates as follows.

[0267] For example, each of the above-described transistors is an N-type transistor. The following description will be given by way of example using an N-type transistor, but embodiments of the present disclosure are not limited to this case, and for example, at least part of these transistors can be replaced with a P-type transistor.

[0268] In the first stage T1, the input control signal STV is an ON signal such as a high potential, so that the first input transistor M1, the second input transistor M2, and the auxiliary reset transistor M14 are turned on. Thus, the input signal STV is written to the first node Q1 through the input circuit 110 <n>to the first node Q <n>When charging, the input signal STV is a high level signal (for example, here, the input signal STV is taken as an example of being the same signal as the input control signal), and the first node Q <n>Write high potential; the first reset signal VGL1 is written into the second node QB through the auxiliary reset transistor M14 <n>, to the second node QB <n>Write low. Since the second node QB <n>For a low potential, the first reset transistor M8 is turned off and the first output reset transistor M16 is also turned off.

[0269] And, in the first stage T1, the auxiliary control signal STD is at a low potential to turn off the first control transistor M40, and the initial reset control signal TRST is at a low potential to turn off the first initial transistor M3, at this time, in response to the first node Q <n>high potential, the first leakage-preventing charging transistor M51 and the second leakage-preventing charging transistor M52 are turned on, and the first control node OFF <n>The anti-leakage charging signal GVDD2 written into is a high potential signal to increase the voltage of the first control node OFF <n>The potential of the second electrode of the first initial transistor M3, the first electrode of the first control transistor M40, and the second electrode of the first reset transistor M8 is set to a low potential, so that the gate-source voltage of the first initial transistor M3, the first control transistor M40, and the first reset transistor M8 is all negative, so that the first initial transistor M3, the first control transistor M40, and the first reset transistor M8 are all turned off more completely, preventing leakage of these transistors.

[0270] In the second stage T2, the third stage T3, and the fourth stage T4 after the first stage T1, the input control signal STV remains as an off signal, for example, a low potential, so that the first input transistor M1, the second input transistor M2, and the auxiliary reset transistor M14 remain turned off.

[0271] In the second stage T2, the first output transistor M15 is turned on in response to the first node Q <n>The first clock signal CLKD1 is at a high potential, and the first output transistor M15 outputs the first clock signal CLKD1 from the first output terminal GOUT as a first output signal. At this time, the signal of the first output terminal GOUT is at a high potential, and thus the first node Q <n>the potential of the first node Q is further raised, so that in the second phase T2 the first node Q <n>the potential at the first node Q is higher than the potential at the second node P in the first phase T1 <n>potential. In this process, the first leakage prevention charging transistor M51 and the second leakage prevention charging transistor M52 are kept on, continuously maintaining the first control node OFF <n>For high potential, to ensure the first node Q <n>the potential of the first control node OFF <n>and the first initial transistor M3, the first control transistor M40, and the first reset transistor M8, i.e., the first node Q can be maintained in the T2 phase <n>a high potential.

[0272] In the third stage T3, the first clock signal CLKD1 becomes a low potential, and the first clock signal CLKD1 is output from the first output terminal GOUT through the first output transistor M15. At this time, the signal of the first output terminal GOUT is a low potential, and thus the first node Q <n>The potential of the first node Q1 decreases to a signal of the second highest level.

[0273] In the fourth stage T4, the auxiliary control signal STD becomes a high potential to turn on the first control transistor M40, and the first reset signal VGL1 is transmitted to the first node Q1 via the first control transistor M40 <n>To give the first node Q <n>Reset. Since the first node is on Q <n>The second node QB is charged to a high potential by the first charging transistor M101, the third charging transistor M102, and the second charging transistor M11 <n>Thus, the first reset transistor M8 is made to respond to the second node QB <n>turned on by the high potential of the first node Q, and the first reset signal VGL1 is written into the first node Q through the first reset transistor M8 <n>To further address the first node Q <n>Reset is performed.

[0274] The first charging transistor M101, the third charging transistor M102, the second charging transistor M11, the first transistor M12 and the second transistor M13 constitute a Darlington inverter. The reason for using this Darlington inverter is that the width-length ratio (W / L) of the first charging transistor M101, the third charging transistor M102 and the first transistor M12 is smaller, at least smaller than that of the second transistor M13, and the leakage current of the first transistor M12 is smaller when the first transistor M1 is negatively biased; if the second charging transistor M11 and the second transistor M13 are directly used to form an inverter, the width-length ratio of the second transistor M13 is larger, and the leakage current of the second transistor M13 is larger when the second transistor M13 is negatively biased.

[0275] And in the fourth stage T4, the first output reset transistor M16 is responsive to the second node QB <n>The first reset signal VGL1 is input to the first output terminal GOUT through the first output reset transistor M16, and the first node Q is brought to a high potential by the bootstrap action of the first capacitor C1 <n>The potential of the first node Q is kept at a low potential to ensure that the first output terminal GOUT does not output a high potential in the non-output stage.

[0276] For example, there is also an initialization stage (not shown in Fig. 17) before the first stage T1. In the initialization stage, the initial reset control signal TRST input at the initial reset control terminal TRST is a high-level signal, and the auxiliary control signal STD input at the auxiliary control terminal STD is also a high-level signal, so that the first initial transistor M3 and the first control transistor M40 are both turned on, so that the first node Q <n>and a first reset signal terminal VGL1 are electrically connected, the first reset signal VGL1 is written into the first node Q<N> via the first control transistor M40 and the first initial transistor M3, the potential of the first node Q<N> is pulled down to a low level, and a reset operation of the first node Q <n>initialization phase, so even if the first clock signal terminal CLKD1 inputs a high level, the first output terminal GOUT and the first output terminal G1<N+1> cannot output this high level. It should be noted that during the initialization phase, the transistors not mentioned by him are kept in the off state (i.e., the off state).

[0277] For example, the initial reset control signal TRST can be an on signal such as a high level signal only in the initialization phase, and an off signal such as a low level signal in other periods.

[0278] For example, in the embodiment shown in FIG. 16, the auxiliary control signal terminal STD is independently controlled. In other embodiments, the auxiliary control signal terminal can be the same signal terminal as the initial reset control terminal TRST.

[0279] It should be noted that the high and low potentials of the signal timing diagram shown in FIG. 2 are only illustrative and do not represent the actual potential values.

[0280] FIG. 18 is a circuit schematic diagram of another shift register unit according to an embodiment of the present disclosure. The signal timing diagram of the shift register unit shown in FIG. 18 during operation can be the same as the timing diagram shown in FIG. 17. The embodiment shown in FIG. 3 is different from the embodiment shown in FIG. 1 in the following aspects.

[0281] For example, as shown in FIG. 18, the first reset circuit 01 further includes a third reset sub-circuit 2a. The driving terminal of the second reset sub-circuit 2a is connected to the first reset control terminal STD to receive the first reset control signal STD. The first control signal includes the first reset control signal STD, and the above-mentioned first control signal includes the first reset control signal STD. Here, the auxiliary control signal terminal and the first reset control terminal are the same signal terminal, both of which are represented by STD. Of course, in other embodiments, the two can be different and independently controlled signals. The first terminal of the second reset sub-circuit 2a is connected to the first node Q <n>connection, the second end of the second reset sub-circuit 2a is connected with the first control node OFF <n>Connection. The second reset sub-circuit 2a is configured to utilize the first reset signal VGL1 from the first reset signal terminal VGL1 to reset the first node Q <n>A reset is performed to set the first node Q <n>On the basis of the reset, the first node Q is reset by the second reset sub-circuit 2a <n>further reset.

[0282] For example, as shown in FIG. 18, the second reset sub-circuit 2a includes a second reset transistor M6, a gate of the second reset transistor M6 is connected with the first reset control end STD, a first electrode of the second reset transistor M6 is connected with the first node Q <n>connects, a second electrode of the second reset transistor M6 and the first control node OFF <n>is connected, so that the second pole of the second reset transistor M6 is connected with the first pole of the first control transistor M40.

[0283] The features of the circuit structure of the shift register shown in Fig. 18 which are not mentioned are identical with those of the embodiment shown in Fig. 16 and can be referred to the previous description.

[0284] With reference to Fig. 18 and Fig. 17, the working process of the shift register unit shown in Fig. 18 differs from the working process of the embodiment shown in Fig. 16 in the following.

[0285] In the first phase T1, the first control node OFF <n>The anti-leakage charging signal GVDD2 written into is a high potential signal to increase the voltage of the first control node OFF <n>the first initial transistor M3, the first control transistor M40, the first reset transistor M8, and the second reset transistor M6 are all turned off thoroughly, and leakage of the transistors is prevented. The other working processes of the first stage T1 are the same as those of the first stage of the embodiment shown in FIG. 1, and reference can be made to the previous description.

[0286] In the second stage T2, the first output transistor M15 is turned on in response to the first node Q <n>The first clock signal CLKD1 is turned on by the high potential of the first clock signal CLKD1, and the first clock signal CLKD1 is output from the first output terminal Gl through the first output transistor Ml 7 <n>output, as a first output signal, at the first output terminal G1 <n>the signal of the first node Q is high, so that the first node Q is brought to a high potential due to the bootstrap action of the first capacitor C1 <n>the potential of the first node Q is further raised, so that in the second phase T2 the first node Q <n>the potential at the first node Q is higher than the potential at the second node P in the first phase T1 <n>potential. In this process, the first leakage prevention charging transistor M51 and the second leakage prevention charging transistor M52 are kept on, continuously maintaining the first control node OFF <n>For high potential, to ensure the first node Q <n>the potential of the first control node OFF <n>and the first initial transistor M3, the first control transistor M40, the first reset transistor M8, and the second reset transistor M6, i.e., the first node Q can be held in the T2 phase <n>The other operation processes of the second stage T2 are the same as those of the second stage of the embodiment shown in Fig. 1, and the previous description can be referred to.

[0287] The other operation processes of the third stage T3 are the same as those of the third stage of the embodiment shown in Fig. 16, and the previous description can be referred to.

[0288] In the fourth stage T4, the auxiliary control signal STD becomes high potential, the first control transistor M40 and the second reset transistor M6 are turned on, and the first reset signal VGL1 is transmitted to the first node Q <n>To give the first node Q <n>Reset. As with the embodiment shown in Fig. 16, the first reset signal VGL1 is also written to the first node Q by the first reset transistor M8 <n>To further address the first node Q <n>The reset is performed. The other working processes of the fourth stage T4 are the same as those of the second stage of the embodiment shown in Fig. 16, and reference can be made to the previous description.

[0289] For the embodiment shown in Fig. 18, for example, there is also an initialization stage (not shown in Fig. 17) before the first stage Tl. In the initialization stage, the initial reset control signal TRST input to the initial reset control end TRST is a high-level signal, and the auxiliary control signal STD input to the auxiliary control end STD is also a high-level signal, so that the first initial transistor M3, the third initial transistor M20, the first control transistor M40 and the second reset transistor M6 are all turned on, so that the first node Q <n>and a first reset signal terminal VGL1 are electrically connected, the first reset signal VGL1 is written into the first node Q<N> via the first control transistor M40 and the first initial transistor M3, or written into the first node Q<N> via the first control transistor M40 and the second reset transistor M6, the potential of the first node Q<N> is pulled down to a low level, and a reset operation of the first node Q <n>initial reset. Thus, the first output transistor M15 is turned off in response to the low level of the first node Q<N> and the third node Q<N+1>, so that the first output terminal GOUT cannot output the high level even if the first clock signal terminal CLKD1 inputs the high level in this stage. It should be noted that in the initialization stage, the unmentioned transistors all remain in the off state (i.e., the off state).

[0290] For example, the initial reset control signal TRST can be an on signal (e.g., a high level signal) only in the initialization stage and an off signal (e.g., a low level signal) in other periods.

[0291] The other working processes and principles of the shift register shown in FIG. 18 are the same as those shown in FIG. 16, and reference can be made to the previous description.

[0292] FIG. 19 is a circuit schematic diagram of another shift register unit provided by an embodiment of the present disclosure. The signal timing diagram of the shift register unit shown in FIG. 19 can be the same as that shown in FIG. 17. The shift register unit shown in FIG. 19 is different from the embodiment shown in FIG. 18 in the following aspects.

[0293] In the shift register unit shown in FIG. 19, the control terminal of the first control sub-circuit 3a is connected with the first terminal of the first control sub-circuit 3a, and the first control node OFF <n>signal as the auxiliary control signal STD. In this way, the control end of the first control sub-circuit 3a does not need to be externally connected to any control signal end, and the first control node OFF <n>discharge, which is favorable to maintain the potential of the first control node OFF<N>, thereby preventing the first node Q <n>The point discharge can avoid the interference of the control process caused by connecting the control end of the first control sub-circuit 3a to other existing control signal ends, simplify the circuit connection of the shift register and the control method.

[0294] Specifically, for example, as shown in FIG. 19, the first control sub-circuit 3a includes a first control transistor M40, the gate of the first control transistor M40 is connected with the first pole of the first control transistor M40, the first pole of the first control transistor M40 is connected with the first control node OFF <n>The second electrode of the first control transistor M40 is connected to the first reset signal terminal VGL1.

[0295] Referring to FIGS. 19 and 17, the operation of the shift register shown in FIG. 19 differs from that of the embodiment shown in FIG. 18 as follows.

[0296] In the first to third periods T1 to T3, since both the first reset transistor M8 and the second reset transistor M6 are turned off, the first control node OFF <n>The first control transistor M40 is turned on for a high potential, and the first node Q <n>The point will also not pass through the first control node OFF <n>discharged through the first control transistor M40. In the fourth stage T4, the auxiliary control signal CR<N+4> becomes a high potential, thereby causing the second reset transistor M6 to be turned on, at which time the first control transistor M40 is also turned on, and the first reset signal VGL1 is transmitted to the first node Q through the first control transistor M40 and the second reset transistor M6 <n>To give the first node Q <n>Reset. Since the first node is on Q <n>The second node QB is charged to a high potential by the first charging transistor M101, the third charging transistor M102, and the second charging transistor M11 <n>Thus, the first reset transistor M8 is made to respond to the second node QB <n>turned on by the high potential of the first node Q, and the first reset signal VGL1 is written into the first node Q through the first reset transistor M8 <n>To further address the first node Q <n>Reset is performed.

[0297] The other working process and principle of the shift register shown in FIG. 19 are the same as those shown in FIG. 18, and reference can be made to the previous description.

[0298] FIG. 20 is a circuit schematic diagram of another shift register unit provided by an embodiment of the present disclosure. The signal timing diagram of the shift register unit shown in FIG. 20 when working can be the same as that shown in FIG. 17. The shift register unit shown in FIG. 20 is different from the embodiment shown in FIG. 18 in the following aspects.

[0299] In the shift register unit shown in FIG. 20, the first control circuit 03 includes a second control sub-circuit 1c and a third control sub-circuit 2c. The control end of the second control sub-circuit 1c is connected to the second node QB <n>connects, a first end of the second control sub-circuit 1c with the first control node OFF <n>The second end of the second control sub-circuit 1c is connected with the first reset signal end VGL1; the control end of the third control sub-circuit 2c is connected with the first reset control end STD, and the first end of the third control sub-circuit 2c is connected with the first control node OFF <n>The second end of the third control sub-circuit 2c is connected with the first reset signal terminal VGL1; the second control signal includes a second node QB <n>a signal of the first reset control signal STD.

[0300] For example, as shown in Fig. 20, the second control sub-circuit 1c includes a second control transistor M9, a gate of the second control transistor M9 being connected to the second node QB <n>connects, a first electrode of the second control transistor M9 and the first control node OFF <n>The second electrode of the second control transistor M9 is connected with the first reset signal terminal VGL1, for example, directly connected with the first reset signal terminal VGL1 through a wire. The third control sub-circuit 2c includes a third control transistor M7, the gate of the third control transistor M7 is connected with the first reset control terminal STD, the first electrode of the third control transistor M7 is connected with the first control node OFF <n>The second electrode of the third control transistor M7 is connected with the first reset signal terminal VGL1, for example, directly connected with the first reset signal terminal VGL1 through a wire.

[0301] In at least one embodiment, for example, as shown in FIG. 20, the first initial reset circuit 170a can include a plurality of transistors, for example, including a first initial transistor M3 and a second initial transistor M41. The gate of the first initial transistor M3 and the gate of the second initial transistor M41 are both connected with the initial reset control terminal TRST, the first electrode of the first initial transistor M3 is connected with the first node Q <n>The second electrode of the first initial transistor M3 is connected with the first electrode of the second initial transistor M41, and the second electrode of the second initial transistor M41 is connected with the first reset signal terminal VGL1.

[0302] In the shift register unit shown in Fig. 20, the initial reset control terminal TRST is multiplexed as an auxiliary control terminal. The second initial transistor M41 is multiplexed as the first control transistor, i.e., in Fig. 20, the first control transistor and the second initial transistor are the same transistor, both of which are denoted by the reference numeral M41. The gate of the second initial transistor M41 is connected with the initial reset control terminal TRST, and the first electrode of the first initial transistor M3 is connected with the first node Q <n>The second terminal of the first initial transistor M3 is connected to the first terminal of the second initial transistor M41, and both the second terminal of the first initial transistor M3 and the first terminal of the second initial transistor M41 are connected to the first control node OFF <n>connected, e.g. directly with a wire, to the first control node OFF <n>Connection. That is, in the shift register unit shown in Fig. 20, the second electrode of the first initial transistor M3 and the first electrode of the second initial transistor are connected to the first control node OFF <n>.

[0303] In another embodiment, the shift register unit is provided, on the basis of Fig. 20, that the second electrode of the first initial transistor M3 and the first electrode of the second initial transistor M4 are not connected to the first control node OFF <n>, other features being the same as the shift register cell shown in Fig. 20.

[0304] The working timing diagram of the shift register cell shown in Fig. 20 can be the same as the timing diagram shown in Fig. 17, and the working process of the shift register cell shown in Fig. 20 has the following differences from the working process of the embodiment shown in Fig. 18.

[0305] Referring to Fig. 20, in the first stage T1, the first node Q <n>After being charged, in response to the first node Q <n>high potential, the first leakage-preventing charging transistor M51 and the second leakage-preventing charging transistor M52 are turned on, and the first control node OFF <n>The anti-leakage charge signal GVDD2 written into is a high potential signal, so that, in addition to improving the connection to the first control node OFF <n>the potential of the second electrode of the second reset transistor M6, the second electrode of the first reset transistor M8, the first electrode of the second control transistor M9, and the first electrode of the third control transistor M7, in addition to the potential of the first electrode of the second reset transistor M6, the second electrode of the first reset transistor M8, the first electrode of the second control transistor M9, and the first electrode of the third control transistor M7 <n>The first initial transistor M3 and the second initial transistor M41 are turned off more thoroughly, and the first initial transistor M3 and the second initial transistor M41 are further prevented from leaking current.

[0306] In the second stage T2, the first output transistor M17 is turned on in response to the first node Q <n>The first clock signal CLKD1 is at a high potential, and the first output transistor M15 outputs the first clock signal CLKD1 from the first output terminal GOUT as the first output signal. At this time, the first output terminal G1 <n>the signal of the first node Q is high, so that the first node Q is pulled up to the high potential due to the bootstrap action of the first capacitor C1 <n>the potential of the first node Q is further raised, so that in the second phase T2 the first node Q <n>the potential at the first node Q is higher than the potential at the second node P in the first phase T1 <n>potential. In this process, the first leakage-preventing charging transistor M51 and the second leakage-preventing charging transistor M52 are kept on, continuously maintaining the first control node OFF <n>For high potential, initial reset control signal and TRST, to ensure the first node Q <n>the potential of the first control node OFF <n>and the first initial transistor M3, the second initial transistor M41 (i.e., the first control transistor), the first reset transistor M8, the second reset transistor M6, the third control transistor M7, and the second control transistor M9 leak current, thereby being able to hold the first node Q <n>The other operation processes of the second stage T2 are the same as those of the second stage of the previous embodiment, and reference can be made to the previous description.

[0307] The other operation processes of the third stage T3 are the same as those of the third stage of the embodiment shown in FIG. 18, and reference can be made to the previous description.

[0308] In the fourth stage T4, the auxiliary control signal STD becomes high potential, so that the second reset transistor M6 and the third control transistor M7 are both turned on, and the first reset signal VGL1 is transmitted to the first node Q <n>To give the first node Q <n>Reset; the initial reset control signal TRST can be an off signal, for example, a low potential, so that the first initial transistor M3 and the second initial transistor M41 (i.e., the first control transistor) are both turned off, and the first node Q <n>The reset is performed. For example, in other embodiments, in the fourth stage T4, the initial reset control signal TRST can also be an on signal, for example, a high potential, so that the first initial transistor M3 and the second initial transistor M41 (i.e., the first control transistor) are both turned on, and the first reset signal VGL1 can also be transmitted to the first node Q through the first initial transistor M3 and the second initial transistor M41 (i.e., the first control transistor) <n>To give the first node Q <n>Reset.

[0309] The other working processes of the fourth stage T4 are the same as those of the fourth stage of the embodiment shown in FIG. 18, and reference can be made to the previous description.

[0310] For the embodiment shown in FIG. 20, for example, there is also an initialization stage before the first stage T1, and the working process of the initialization stage is the same as that of the fourth stage of the embodiment shown in FIG. 18, and reference can be made to the previous description.

[0311] FIG. 21 is a circuit schematic diagram of another shift register unit provided by an embodiment of the present disclosure. The signal timing diagram of the shift register unit when working in FIG. 20 can be the same as that shown in FIG. 17. The shift register unit shown in FIG. 20 is different from the embodiment shown in FIG. 18 in the following aspects.

[0312] For example, referring to FIG. 21, the shift register unit further includes a second output reset circuit 120a and a second output circuit 130a; the second output reset circuit 120a is configured to reset the second node QB <n>under control of a signal of the first output terminal G1 <n>performing a reset; the second output circuit 130a is configured to output a signal at the first node Q <n>the second clock signal CLKE1 is output to the second output terminal G1 under control of the signal of the second clock signal control signal CLKE1 <n>.

[0313] For example, referring to FIG. 21, the second output reset circuit 120a includes a second output reset transistor M20, a gate of the second output reset transistor M20 is connected with the second node, a first pole of the second output reset transistor M20 is connected with the second output end G1 <n>The second output reset transistor M20 is connected between the second output terminal G1 and the second reset signal terminal VGL2, and the second output reset transistor M20 is connected to the second reset signal terminal VGL2 to receive the second reset signal VGL2 and configured to reset the second output terminal G1 by the second reset signal VGL2. <n>Reset is performed. The second output circuit 130a includes a second output transistor M17 and a second capacitor C2; the gate of the second output transistor M17 is connected to the first node Q <n>The first electrode of the second output transistor M17 is connected to the second clock signal terminal CLKE1 to receive the second clock signal CLKE1, and the second electrode of the second output transistor M17 is connected to the second output terminal G1 <n>The first pole of the second capacitor C2 is connected to the gate of the second output transistor M17, and the second pole of the second capacitor C2 is connected to the second pole of the second output transistor M17.

[0314] For example, referring to FIG. 21, a first auxiliary transistor M01 is connected between the gate of the first output transistor M15 and the gate of the second output transistor M17. The gate of the first auxiliary transistor M01 is connected to a first auxiliary control terminal GVDD3 to receive a first auxiliary control signal GVDD3, the first pole of the first auxiliary transistor M01 is connected to the gate of the first output transistor M15, the second pole of the first auxiliary transistor M01 is connected to the gate of the second output transistor M17, and the first auxiliary control signal GVDD13 is a constant high potential. Thus, in the second phase T2, that is, when the first node Q <n>After the charging and before the output of the high potential clock signal, when the voltage of the gate of the second output transistor M17 is greater than the voltage of the first auxiliary control signal GVDD3, the first auxiliary transistor M01 is turned off, so the gate voltage of the second output transistor M17 is kept stable without being disturbed by other signals, thereby preventing the second output transistor M17 from leaking by setting the first auxiliary transistor M01, to prevent the output signal from being unstable or inaccurate.

[0315] For example, referring to FIG. 21, the first node Q <n>A second auxiliary transistor M02 is connected with the first reset circuit 01. A gate of the second auxiliary transistor M02 is connected with a second auxiliary control terminal GVDD3 to receive a second auxiliary control signal GVDD3. For example, the second auxiliary control terminal and the first auxiliary control terminal are the same control terminal, and both are represented by GVDD3. For example, the plurality of auxiliary control terminals described below can all be the same signal terminal, and all are represented by GVDD3. Of course, in other embodiments, each auxiliary control terminal can be an independent and different signal terminal, and the present disclosure does not limit this.

[0316] For example, a first pole of the second auxiliary transistor M02 is connected with the first reset circuit 01, and a second pole of the second auxiliary transistor M02 is connected with the first node Q <n>With connection. For example, the first pole of the second auxiliary transistor M02 is connected with the first end of the first reset sub-circuit 1a; for example, the first pole of the second auxiliary transistor M02 is connected with the first pole of the first reset transistor M8. Thus, in the second stage T2, that is, in the process of charging the first node Q <n>After charging and before outputting the high potential clock signal, when the voltage at the gate of the first output transistor M15 is greater than the voltage of the first auxiliary control signal GVDD3, the second auxiliary transistor M02 is turned off, so the gate voltage of the first output transistor M15 remains stable without being disturbed by other signals, thereby preventing the first output transistor M15 from leaking and preventing the output signal from being unstable or inaccurate by setting the second auxiliary transistor M02.

[0317] For example, referring to FIG. 21, the shift register unit further includes other multiple output circuits, such as third to fifth output circuits 130b-130d. Of course, the number of output circuits is not limited to five, and can be less than five or more than five. For example, an auxiliary transistor is connected between the gates of two adjacent output circuits, and the first and second poles of the auxiliary transistor are connected to the gates of the two adjacent output circuits, respectively.

[0318] The shift register unit provided by at least one embodiment of the present disclosure includes a first sub-shift register unit and a second sub-shift register unit. The first sub-shift register unit includes a first input circuit, a first output reset circuit, and a first output circuit. The first input circuit is configured to input a first input signal to a first node in response to a first input control signal. The first output reset circuit is configured to reset a first output terminal under the control of a signal at a second node. The first output circuit is configured to output a first clock signal to the first output terminal under the control of a signal at the first node. The second sub-shift register unit includes a second input circuit, a second output reset circuit, and a second output circuit. The second input circuit is configured to input the first input signal to a third node in response to a second input control signal. The second output reset circuit is configured to reset a second output terminal under the control of a signal at a fourth node. The second output circuit is configured to output a second clock signal to the second output terminal under the control of a signal at the fourth node. The fourth node is connected to the second node, and the second output reset circuit is configured to reset the second output terminal under the control of a signal transmitted from the second node to the fourth node.

[0319] For example, FIG. 22 is a circuit schematic diagram of another shift register unit provided by an embodiment of the present disclosure. Referring to FIG. 22, the shift register unit has the following differences from the embodiment shown in FIG. 11.

[0320] Referring to FIG. 22, the fourth node QB <n>The connection, the second output reset circuit 121b is configured to reset the second node QB <n>The second output end G1<N+1> is reset under the control of the signal transmitted to the fourth node QB<N+1>. Thus, by making the first sub-shift register unit and the second sub-shift register unit share the Darlington inverter, the Darlington inverter does not need to be additionally arranged for the second sub-shift register unit, the reset of the second output end G1<N+1> of the second sub-shift register unit is realized, the structure of the shift register unit is simplified, the space is saved, and the size of the frame area of the display panel provided with the shift register unit in the frame area is reduced.

[0321] For example, in FIG. 22, the fourth node QB<N+1> is directly connected with the second node QB <n>The connection between the fourth node QB<N+1> and the second node QB <n>There are no other electronic elements between the two nodes QB<N> and QB<N+1>, including but not limited to switching elements (e.g. transistors), inductors, etc. In this way, the structure of the shift register unit can be simplified, and its control method can be simplified.

[0322] Alternatively, in other embodiments, the fourth node QB<N+1> is connected to the second node QB <n>between the fourth node QB<N+1> and the second node QB<N> can be electrically connected with other electronic elements, for example, switching elements (for example, transistors), such that the fourth node QB<N+1> and the second node QB<N> are electrically connected with each other through the switching elements. <n>The electronic component is electrically connected via the electronic component.

[0323] For example, as shown in FIG. 22, the first sub-shift register unit further includes a second node control circuit 160. The second node control circuit 160 includes a second node charging circuit 161 and a second node resetting circuit 162. The second node charging circuit 161 is connected with the second node charging control end GVDD1 to receive a second node charging control signal GVDD1, with the second node charging signal end GVDD1 to receive a second node charging signal GVDD1, and with the second node QB <n>connected, the second node charging circuit 161 is configured to charge the second node QB with the second node charging signal GVDD1 in response to the second node charging control signal GVDD1 <n>The second node charging is performed. For example, here taking the second node charging control signal and the second node charging control signal as the same signal GVDD1 as an example, for example, the control end of the second node charging circuit 161 is connected with the first end of the second node charging circuit 161, that is, the two are connected to the same signal end to receive the same signal GVDD1. Of course, in other embodiments, the control end of the second node charging circuit 161 can not be electrically connected with the first end of the second node charging circuit 161, and the second node charging control signal and the second node charging control signal can be different signals and are independently controlled respectively.

[0324] For example, referring to FIG. 22, the second node reset circuit 162 is connected with the first node Q <n>and a second node QB <n>is connected to the first reset signal terminal VGL1 to receive the first reset signal VGL1 and / or is connected to the second reset signal terminal VGL2 to receive the second reset signal VGL2, and the second node reset circuit 162 is configured to reset the first node Q <n>the second node QB with the first reset signal VGL1 and the second reset signal VGL2 under control of the potential of the first node QA <n>The second reset signal VGL2 has a level lower than that of the first reset signal VGL1, or the level of the second reset signal VGL2 is equal to that of the first reset signal VGL1. For example, in at least one embodiment, the first reset signal terminal VGL1 and the second reset signal terminal VGL2 can also be the same reset signal terminal.

[0325] For example, as shown in FIG. 22, the fourth node QB <n>Connection. For example, the fourth node QB <N+1> is connected to the second node QB <n>directly connected by a wire. The second output reset circuit 121b is configured to reset the second node QB <n>The second output G1<N+1> is reset under the control of the signal transmitted to the fourth node QB<N+1>. Thus, the second sub-shift register does not have a second node control circuit similar to the design of the first sub-shift register, i.e., the structure of the second sub-shift register is simplified.

[0326] For example, other features of the embodiment shown in FIG. 22 that are not mentioned are the same as those shown in FIG. 11, and reference can be made to the previous description.

[0327] For example, in one embodiment, the second sub-shift register unit has the same structure as the first sub-shift register unit except that the second node control circuit is not provided.

[0328] The shift register unit provided by at least one embodiment of the present disclosure includes an input circuit, a first output reset circuit, a first reset circuit, and a first output circuit. The input circuit is configured to charge a first node in response to an input control signal; the first output reset circuit is configured to reset a first output end under the control of a signal of a second node; the first output circuit is configured to output a first clock signal to the first output end under the control of a signal of the first node; a control end of the first reset circuit is connected with the second node, a first end of the first reset circuit is connected with the first node, and a second end of the second reset circuit is connected with the first output end.

[0329] Exemplarily, FIG. 23 is a circuit schematic diagram of another shift register unit provided by an embodiment of the present disclosure. The shift register unit includes an input circuit 110, a first output reset circuit 120, a first reset circuit 01, and a first output circuit 130. The input circuit 110 is configured to charge a first node Q <n>charging; the first output reset circuit 120 is configured to reset the second node QB <n>under control of a signal of the first output terminal CR <n>performing a reset; the first output circuit 130 is configured to output a first signal at the first node Q <n>the first clock signal CLKD1 is output to the first output terminal CR under control of a signal of the first control signal line CTR1 <n>; control end of the first reset circuit 01 and the second node QB <n>connects, a first end of the first reset circuit 01 and the first node Q <n>Connection, second end of first reset circuit 01 with first output end CR <n>Connection. Thereby, on the one hand, it is possible to employ the first output CR <n>The output signal is protected from leakage current, when the first output terminal CR <n>When the output signal is high, the first reset circuit 01 has a high level at the first output terminal CR <n>The first or second pole of the connected transistor can be written to a high potential, so that the gate-source voltage of the transistor is negative, thereby making the transistor turn off more completely, preventing the transistor from leaking; on the other hand, when the first output end CR <n>When the output signal is at a low potential, the first reset circuit 01 can be used to set the second node QB <n>under control of the signal of the first output terminal CR <n>The output signal is coupled to the first node Q <n>Reset is performed.

[0330] For example, referring to FIG. 23, the shift register unit further includes a second reset circuit 02. A control terminal of the second reset circuit 02 is connected with the first reset control terminal STD to receive the first reset control signal STD, and a first terminal of the second reset circuit 02 is connected with the first node Q <n>Connection, second end of second reset circuit 02 with first output CR <n>Connection. Thus, on the one hand, when the first output end CR <n>When the output signal is high, the first output terminal CR <n>The output signal is prevented from electric leakage, and the second reset circuit 02 is connected to the first output terminal CR <n>The first or second pole of the connected transistor can be written to a high potential, so that the gate-source voltage of the transistor is negative, thereby making the transistor turn off more completely, preventing the transistor from leaking; on the other hand, when the first output end CR <n>When the output signal is at a low potential, the first output terminal CR of the second reset circuit 02 can be reset in response to the first reset control signal STD <n>The output signal is coupled to the first node Q <n>A reset is performed.

[0331] For example, referring to FIG. 23, the shift register unit further comprises an initial reset circuit 03, a control end of the initial reset circuit 03 being connected with the initial reset control end TRST to receive an initial reset control signal TRST, a first end of the initial reset circuit 03 being connected with the first node Q <n>Connection, second end of initial reset circuit 03 with first output CR <n>Connection. Thus, on the one hand, when the first output end CR <n>When the output signal is high, the first output terminal CR <n>The output signal is prevented from electric leakage, and the initial reset circuit 03 is connected to the first output terminal CR <n>The first or second pole of the connected transistor can be written to a high potential, so that the gate-source voltage of the transistor is negative, so that the transistor is turned off more completely, preventing the transistor from leaking; on the other hand, when the first output end CR <n>When the output signal is low, in the initial stage, the first output terminal CR of the initial reset circuit 03 can be used to respond to the initial reset control terminal TRST <n>The output signal is coupled to the first node Q <n>A reset is performed.

[0332] Specifically, for example, referring to FIG. 23, the first reset circuit 01 includes a first reset transistor M8, a gate of the first reset transistor M8 being connected to the second node QB <n>connects, a first electrode of the first reset transistor M8 and the first node Q <n>connects the second electrode of the first reset transistor M8 and the first output terminal CR <n>Connection.

[0333] For example, with reference to FIG. 23, the second reset sub-circuit 2a includes a second reset transistor M6, a gate of the second reset transistor M6 is connected with the first reset control end STD, a first electrode of the second reset transistor M6 is connected with the first node Q <n>connection, the second electrode of the second reset transistor M6 and the first output terminal CR <n>Connection.

[0334] For example, referring to FIG. 23, the initial reset circuit 03 includes an initial transistor M3. The gate of the initial transistor M3 is connected to the initial reset control terminal TRST, the first electrode of the initial transistor M3 is connected to the first node Q <n>connects the second terminal of the initial transistor M3 and the first output terminal CR <n>Connection.

[0335] In comparison with the shift register unit shown in Fig. 18, the shift register unit shown in Fig. 23 removes the anti-leakage charging circuit 150 in Fig. 18, since the first output terminal CR <n>The high potential output prevents leakage of the transistor, so that an additional leakage prevention charging circuit is not needed, which is conducive to simplifying the structure of the shift register unit; and the first control circuit is also removed.

[0336] For example, the shift register unit shown in FIG. 23 can further include a plurality of output circuits, for example, further including a second output circuit 130a, which has the same design as the second output circuit 130a in the previous embodiments, and reference can be made to the previous description.

[0337] The other structures of the shift register unit shown in FIG. 23 that are not mentioned can refer to the same structures in FIG. 18.

[0338] The working principle of the shift register unit shown in FIG. 23 will be described below in combination with the signal timing diagram shown in FIG. 24. In the four stages of the first stage T1, the second stage T2, the third stage T3, and the fourth stage T4 shown in FIG. 24, the shift register unit performs the following operations.

[0339] For example, the above-mentioned transistors are all N-type transistors. The following description will also take N-type transistors as an example, but the embodiments of the present disclosure are not limited to this case, for example, at least part of these transistors can be replaced by P-type transistors.

[0340] In the first stage T1, the input control signal STV is an on signal, for example, a high potential, so that the first input transistor M1 and the auxiliary reset transistor M14 are turned on. Thus, the input signal STV is written to the first node Q <n>to the first node Q <n>When charging, the input signal STV is a high level signal (for example, here, the input signal STV is taken as an example of being the same signal as the input control signal), and the first node Q <n>Write high potential; the first reset signal VGL1 is written into the second node QB through the auxiliary reset transistor M14 <n>, to the second node QB <n>Write low. Since the second node QB <n>For a low potential, the first reset transistor M8 is turned off and the first output reset transistor M16 is also turned off.

[0341] In the first phase T1, the auxiliary control signal STD is at a low potential to turn off the second reset transistor M6, and the initial reset control signal TRST is at a low potential to turn off the first initial transistor M3.

[0342] In the second phase T2, the third phase T3 and the fourth phase T4, which follow the first phase T1, the input control signal STV remains at an off signal, for example at a low potential, to keep the first input transistor M1 and the auxiliary reset transistor M14 turned off.

[0343] In the second phase T2, the first reset transistor M8, the second reset transistor M6 and the initial transistor M3 remain turned off. The first output transistor M15 is turned on in response to the first node Q <n>The first clock signal CLKD1 is at a high potential, and the first output transistor M15 outputs the first clock signal CLKD1 from the first output terminal GOUT as a first output signal. At this time, the signal output from the first output terminal GOUT is at a high potential, and thus the first node Q <n>the potential of the first node Q is further raised, so that in the second phase T2 the first node Q <n>the potential at the first node Q is higher than the potential at the second node P in the first phase T1 <n>the potential of the first node Q. In this process, the second electrode of the first reset transistor M8, the second electrode of the second reset transistor M6 and the second electrode of the initial transistor M3 are outputted with the high potential signal from the first output terminal GOUT, so that the gate-source voltage of these transistors is negative, thereby making these transistors be turned off more completely, preventing these transistors from leaking, and being beneficial to guarantee the first node Q <n>the potential of the first node Q will not be leaked through any one of the first reset transistor M8, the second reset transistor M6, and the first initial transistor M3, i.e., the first node Q can be maintained in the second stage T2 <n>The high potential signal outputted by the first output terminal GOUT is used to prevent the transistors from leaking, and no additional leakage prevention circuit is needed to input a leakage prevention signal to the first electrode or the second electrode of the transistors, thus simplifying the structure of the shift register unit.

[0344] In the third stage T3, the first clock signal CLKD1 becomes low potential, and the first clock signal CLKD1 is outputted from the first output terminal GOUT through the first output transistor M15. At this time, the signal of the first output terminal GOUT is low potential, so that the first node Q <n>The potential of the first node Q is lowered to a signal of the second highest level.

[0345] In the fourth stage T4, the auxiliary control signal STD is changed to a high potential to turn on the second reset transistor M6, the first clock signal CLKD1 is still at a low potential, and the first clock signal CLKD1 is output from the first output terminal GOUT through the first output transistor M15. The low potential signal output from the first output terminal GOUT through the second reset transistor M6 is transmitted to the first node Q <n>To give the first node Q <n>reset, thereby causing the first node to be in Q <n>is low. Since the first node is at Q <n>For a low potential, both the first transistor M12 and the second transistor M13 are turned off, so the second node QB to which a high potential is applied can be written with the second node charging signal GVDD1 through the first charging transistor M101, the third charging transistor M102, and the second charging transistor M11 <n>Thus, the first reset transistor M8 is made to respond to the second node QB <n>turns on, and a low potential signal output from the first output terminal GOUT is written into the first node Q through the first reset transistor M8 <n>, to further the first node Q <n>A reset is performed.

[0346] Thus, it is achieved that when the first output end CR <n>When the output signal is at a low potential, the first reset circuit 01 and the second reset circuit 02 respond to the first reset control signal STD to set the first output terminal CR <n>The output signal is coupled to the first node Q <n>A reset is performed.

[0347] And, in the fourth stage T4, the first output reset transistor M16 is responsive to the second node QB <n>turned on by the high potential of the first node Q, and the first reset signal VGL1 is input to the first output terminal GOUT through the first output reset transistor M16. The first node Q is pulled up to the high potential by the first capacitor C1, and the first output terminal GOUT is pulled down to the low potential by the first output reset transistor M16. Thus, the first output terminal GOUT is reset to the low potential. <n>The potential of the first node Q is kept at a low potential to ensure that the first output terminal GOUT does not output a high potential in the non-output stage.

[0348] The signals GVDD1 and GVDD2 in FIG. 23 are both constant high potential signals, and details can be referred to the related descriptions in previous embodiments.

[0349] For example, there is an initialization stage (not shown in FIG. 24) before the first stage T1. In the initialization stage, the initial reset control signal TRST input by the initial reset control terminal TRST is a high level signal, and the auxiliary control signal STD input by the auxiliary control terminal STD is also a high level, so that the first initial transistor M3 is turned on, and the first node Q <n>and a first output terminal CR <n>The first clock signal end CLKD1 inputs a low potential signal, and the first clock signal CLKD1 is output from the first output end GOUT through the first output transistor M15. The low potential signal output from the first output end GOUT is written into the first node Q <n>initial reset. It is to be noted that during the initialization phase, the transistors not mentioned remain in the off state (i.e. turned off).

[0350] For example, the initial reset control signal TRST can be an on signal (e.g. high level signal) only during the initialization phase, and an off signal (e.g. low level signal) during other time periods.

[0351] It is to be noted that the high and low levels of the signal timing diagram shown in Fig. 24 are only illustrative, and do not represent the actual potential values.

[0352] The operation of the other unmentioned structures of the shift register shown in Fig. 25 during each phase and the principles thereof are the same as those of the same components shown in Fig. 18, and reference can be made to the previous description.

[0353] At least one embodiment of the present disclosure provides a driving circuit comprising a plurality of cascaded shift register units, which can employ any shift register unit provided by the embodiments of the present disclosure. The driving circuit can be directly integrated on an array substrate of a display device using a process of the same manufacturing process as thin film transistors, to realize a row-by-row scanning driving function.

[0354] For example, the driving circuit can further comprise a timing controller. The timing controller is configured to provide clock signals (CLKD1, CLKE1, etc.) to each stage of shift register units, and can also be configured to provide a first input control signal CR <n-2>, an auxiliary control signal CR<N+4> / STD, an input control signal STV, a trigger signal STV, a reset signal RST, and an initial reset control signal TRST, etc.

[0355] The technical effects of the driving circuit 10 provided by the embodiments of the present disclosure can be referred to the corresponding descriptions about the shift register unit in the above embodiments, which will not be repeated here.

[0356] At least one embodiment of the present disclosure provides a display device 100, as shown in FIG. 25, which includes any driving circuit 10 provided in the above embodiments.

[0357] It should be noted that the display device in the present embodiment can be any product or component with display function, such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. The display device 1 can further include a display panel and other conventional components, and the embodiments of the present disclosure do not limit this.

[0358] The technical effects of the driving circuit 10 provided by the embodiments of the present disclosure can be referred to the corresponding descriptions about the shift register unit in the above embodiments, which will not be repeated here.

[0359] The following points should be noted:

[0360] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0361] (2) For the sake of clarity, the thickness of the layers or regions is exaggerated or reduced in the drawings used to describe the embodiments of the present disclosure, that is, these drawings are not drawn according to the actual proportion.

[0362] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0363] The above only describes exemplary embodiments of the present disclosure, and is not intended to limit the protection scope of the present disclosure, and the protection scope of the present disclosure is determined according to the scope defined by the claims. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A shift register unit comprising: The first sub-shift register unit and the second sub-shift register unit, The first sub-shift register unit comprises a first input circuit, a first output reset circuit, a first reset circuit, a first output circuit and a first control circuit; the first input circuit is configured to input a first input signal to a first node in response to a first input control signal; the first output reset circuit is configured to reset a first output end under the control of a second node; the first output circuit is configured to output a first clock signal to the first output end under the control of the first node; The first reset circuit and the first control circuit are connected to a first control node, and the first control circuit is connected between the first control node and a first reset signal end; the first reset circuit and the first control circuit are configured to reset the first node by the first reset signal from the first reset signal end in response to a first control signal and a second control signal respectively; The second sub-shift register unit comprises a second input circuit, a second output reset circuit, a second reset circuit and a second output circuit; the second input circuit is configured to input the first input signal to a third node in response to a second input control signal; the second output reset circuit is configured to reset a second output end under the control of a fourth node; the second output circuit is configured to output a second clock signal to the second output end under the control of the fourth node; The second reset circuit is connected to a second control node, the second control node is connected to the first control node, and the second reset circuit is configured to reset the third node by the first reset signal transmitted to the second control node through the first control node in response to a third control signal.

2. The shift register cell of claim 1, wherein, The first reset circuit comprises a first reset sub-circuit, a control end of the first reset sub-circuit is connected to the second node, a first end of the first reset sub-circuit is connected to the first node, a second end of the first reset sub-circuit is connected to the first control node, and the first reset sub-circuit is configured to reset the first node by the first reset signal from the first control node under the control of the second node, and the first control signal comprises a signal of the second node; The second reset circuit comprises a second reset sub-circuit, a control end of the second reset sub-circuit is connected to the fourth node, a first end of the second reset sub-circuit is connected to the third node, a second end of the second reset sub-circuit is connected to the second control node, and the second reset sub-circuit is configured to reset the third node by the first reset signal transmitted to the second control node through the first control node under the control of the fourth node. ​ 3. The shift register cell of claim 2, wherein, The first reset circuit further comprises a third reset sub-circuit, a driving end of the third reset sub-circuit is connected with the first reset control end to receive the first reset control signal, the first control signal comprises the first reset control signal, a first end of the third reset sub-circuit is connected with the first node, and a second end of the third reset sub-circuit is connected with the first control node, and the third reset sub-circuit is configured to reset the first node by using the first reset signal from the first reset signal end in response to the first reset control signal. The second reset circuit further comprises a fourth reset sub-circuit, a control end of the fourth reset sub-circuit is connected with the second reset control end to receive the second reset control signal, the third control signal comprises the second reset control signal, a first end of the fourth reset sub-circuit is connected with the third node, and a second end of the fourth reset sub-circuit is connected with the third control node, and the fourth reset sub-circuit is configured to reset the third node by using the first reset signal transmitted to the second control node via the first control node in response to the second reset control signal.

4. The shift register cell of claim 2 or 3, wherein, The first control circuit comprises a first control sub-circuit, a control end of the first control sub-circuit is connected with the auxiliary control end to receive the auxiliary control signal, the second control signal comprises the auxiliary control signal, a first end of the first control circuit is connected with the first control node, and a second end of the first control circuit is connected with the first reset signal end.

5. The shift register cell of claim 4, wherein, The control end of the first control sub-circuit is connected with the first end of the first control sub-circuit, and a signal of the first control node is taken as the auxiliary control signal.

6. The shift register cell of claim 4, wherein, The first control circuit comprises a second control sub-circuit and a third control sub-circuit. A control end of the second control sub-circuit is connected with the second node, a first end of the second control sub-circuit is connected with the first control node, and a second end of the second control sub-circuit is connected with the The first reset signal end; A control end of the third control sub-circuit is connected with the first reset control end, a first end of the third control sub-circuit is connected with the first control node, and a second end of the third control sub-circuit is connected with the first reset signal end; The second control signal comprises a signal of the second node and the first reset control signal.

7. The shift register cell of any one of claims 1-6, wherein, The first sub-shift register unit further comprises: A first initial reset circuit connected with an initial reset control end to receive an initial reset control signal and configured to reset the first node in response to the initial reset control signal; The second sub-shift register unit further comprises: A second initial reset circuit configured to reset the third node in response to the initial reset control signal, wherein a control end of the second initial reset circuit is connected with the initial reset control end to receive the initial reset control signal, a first end of the second initial reset circuit is connected with the third node, and a second end of the second initial reset circuit is connected with the second control node.

8. The shift register cell of claim 4 or 6, wherein, The first sub-shift register unit further comprises: A first initial reset circuit is connected to the initial reset control terminal to receive an initial reset control signal and is configured to reset the first node in response to the initial reset control signal; The second sub-shift register unit further comprises: A second initial reset circuit is configured to reset the third node in response to the initial reset control signal, wherein a control terminal of the second initial reset circuit is connected to the initial reset control terminal to receive the initial reset control signal, a first terminal of the second initial reset circuit is connected to the third node, and a second terminal of the second initial reset circuit is connected to the second control node. The initial reset control terminal is multiplexed as the auxiliary control terminal.

9. The shift register cell of any one of claims 1-8, wherein, The first sub-shift register unit further comprises an anti-leakage charging circuit, a control terminal of the anti-leakage charging circuit is connected to the first node, a first terminal of the anti-leakage charging circuit is connected to an anti-leakage charging signal terminal to receive an anti-leakage charging signal, a second terminal of the anti-leakage charging circuit is connected to the first control node, and the anti-leakage charging circuit is configured to input the anti-leakage charging signal to the first control node under the control of the first node.

10. The shift register cell of any one of claims 1-9, wherein, The first sub-shift register unit further comprises: A second node control circuit comprises a second node charging circuit and a second node reset circuit, wherein The second node charging circuit is connected to a second node charging control terminal to receive a second node charging control signal, is connected to a second node charging signal terminal to receive a second node charging signal, and is connected to the second node, and the second node charging circuit is configured to charge the second node with the second node charging signal in response to the second node charging control signal; The second node reset circuit is connected to the first node and the second node, and is connected to the first reset signal terminal to receive the first reset signal and / or is connected to a second reset signal terminal to receive a second reset signal, and the second node reset circuit is configured to reset the second node with the first reset signal and the second reset signal under the control of the potential of the first node; The level of the second reset signal is lower than the level of the first reset signal, or the level of the second reset signal is equal to the level of the first reset signal.

11. The shift register cell of claim 10, wherein, The fourth node is connected to the second node.

12. The shift register cell of claim 2, wherein, The first reset sub-circuit comprises a first reset transistor, a gate of the first reset transistor is connected to the second node, a first pole of the first reset transistor is connected to the first node, and a second pole of the first reset transistor is connected to the first control node; The second reset sub-circuit comprises a second reset transistor, a gate of the second reset transistor is connected to the fourth node, a first pole of the second reset transistor is connected to the third node, and a second pole of the second reset transistor is connected to the second control node.

13. The shift register cell of claim 3, wherein, The third reset sub-circuit comprises a third reset transistor, a gate of the third reset transistor is connected with the first reset control end, a first pole of the third reset transistor is connected with the first node, and a second pole of the third reset transistor is connected with the first control node. The fourth reset sub-circuit comprises a fourth reset transistor, a gate of the fourth reset transistor is connected with the second reset control end to receive the second reset control signal, a first pole of the fourth reset transistor is connected with the third node, and a second pole of the fourth reset transistor is connected with the second control node. The first control sub-circuit comprises a first control transistor, a gate of the first control transistor is connected with the auxiliary control end, a first pole of the first control transistor is connected with the first control node, and a second pole of the first control transistor is connected with the first reset signal end.

14. The shift register cell of claim 4, wherein, The first control sub-circuit comprises a first control transistor, a gate of the first control transistor is connected with a first pole of the first control transistor, the first pole of the first control transistor is connected with the first control node, and a second pole of the first control transistor is connected with the first reset signal end.

15. The shift register cell of claim 5, wherein, The second control sub-circuit comprises a second control transistor, a gate of the second control transistor is connected with the second node, a first pole of the second control transistor is connected with the first control node, and a second pole of the second control transistor is connected with the first reset signal end.

16. The shift register cell of claim 6, wherein, The third control sub-circuit comprises a third control transistor, a gate of the third control transistor is connected with the first reset control end, a first pole of the third control transistor is connected with the first control node, and a second pole of the third control transistor is connected with the first reset signal end. The first initial reset circuit comprises a first initial transistor and a second initial transistor.

17. The shift register cell of claim 7 or 8, wherein, A gate of the first initial transistor and a gate of the second initial transistor are both connected with the initial reset control end, a first pole of the first initial transistor is connected with the first node, a second pole of the first initial transistor is connected with a first pole of the second initial transistor, and a second pole of the second initial transistor is connected with the first reset signal end. The second initial reset circuit comprises a third initial transistor, a gate of the third initial transistor is connected with the initial reset control end, a first pole of the third initial transistor is connected with the third node, and a second pole of the third initial transistor is connected with the second control node. In the case that the initial reset control end is multiplexed as the auxiliary control end, the second initial transistor is multiplexed as the first control transistor, a gate of the first control transistor is connected with the initial reset control end, a second pole of the first initial transistor is connected with a first pole of the first control transistor, and the second pole of the first initial transistor and the first pole of the first control transistor are both connected with the first control node.

18. The shift register cell of claim 17, wherein, ​ 19. The shift register cell of claim 9, wherein, The leakage-proof charging circuit comprises a leakage-proof charging transistor, a gate of the leakage-proof charging transistor is connected with the first node, a first pole of the leakage-proof charging transistor is connected with the leakage-proof charging signal end, and a second pole of the leakage-proof charging transistor is connected with the first control node.

20. The shift register cell of claim 10, wherein, The second node charging circuit comprises a first charging transistor and a second charging transistor; The second node charging signal end is connected with the second node charging control end, a first pole of the first charging transistor is connected with the second node charging signal end, and a second pole of the first charging transistor is connected with a gate of the second charging transistor; A first pole of the second charging transistor is connected with the second node charging signal end, and a second pole of the second charging transistor is connected with the second node.

21. The shift register cell of claim 10 or 20, wherein, The second node reset circuit comprises a first transistor and a second transistor; A gate of the first transistor and a gate of the second transistor are both connected with the first node, a first pole of the first transistor is connected with the gate of the second charging transistor and the second pole of the first charging transistor, and a second pole of the first transistor is connected with the first reset signal end or the second reset signal end; A first pole of the second transistor is connected with the second node and the second pole of the second charging transistor, and a second pole of the second transistor is connected with the first reset signal end.

22. The shift register cell of any of claims 1-21, wherein, The driving end of the first input circuit is connected with the first input control signal end to receive the first input control signal, a first end of the first input circuit is connected with the first input signal end to receive the first input signal, and a second end of the first input circuit is connected with the first node to charge the first node by using the first input signal; The driving end of the second input circuit is connected with the first input control signal end to receive the first input control signal, a first end of the second input circuit is connected with the first input signal end to receive the first input signal, and a second end of the second input circuit is connected with the third node to charge the third node by using the first input signal. The first input circuit comprises a first input transistor, a gate of the first input transistor is connected with the first input control signal end to receive the first input control signal, a first pole of the first input transistor is connected with the first input signal end to receive the first input signal, and a second pole of the first input transistor is connected with the first node to charge the first node by using the first input signal; 23. The shift register cell of claim 22, wherein, The second input circuit comprises a second input transistor, a gate of the second input transistor is connected with the first input control signal end to receive the first input control signal, a first pole of the second input transistor is connected with the first input signal end to receive the first input signal, and a second pole of the second input transistor is connected with the third node to charge the third node by using the first input signal. The first input circuit is further connected with the first control node, and 24. The shift register cell of claim 22, wherein, ​ The first end of the second input circuit is connected with the first control node to be connected with the first input signal end via the first control node, and the second input circuit charges the third node by using the first input signal received via the first control node.

25. The shift register cell of claim 24, wherein, The first input circuit comprises a first input transistor, a gate of the first input transistor is connected with the first input control signal end to receive the first input control signal, a first pole of the first input transistor is connected with a first input signal end to receive a first input signal, a second pole of the first input transistor is connected with the first node to charge the first node by using the first input signal, and the second pole of the first input transistor is also connected with the first control node; The second input circuit comprises a second input transistor, a gate of the second input transistor is connected with the first input control signal end to receive the first input control signal, a first pole of the second input transistor is connected with the first control node to be connected with the first input signal end via the first control node, the second input transistor charges the third node by using the first input signal received via the first control node, a second pole of the second input transistor is connected with the third node to charge the third node by using the first input signal. The first output circuit comprises a first output transistor and a first capacitor; 26. The shift register cell of any one of claims 1-25, wherein, A gate of the first output transistor is connected with the first node, a first pole of the first output transistor is connected with a first clock signal end to receive the first clock signal, and a second pole of the first output transistor is connected with the first output end; A first pole of the first capacitor is connected with the gate of the first output transistor, and a second pole of the first capacitor is connected with the second pole of the first output transistor; The second output circuit comprises a second output transistor and a second capacitor; A gate of the second output transistor is connected with the third node, a first pole of the second output transistor is connected with a second clock signal end to receive the second clock signal, and a second pole of the second output transistor is connected with the second output end; A first pole of the second capacitor is connected with the gate of the second output transistor, and a second pole of the second capacitor is connected with the second pole of the second output transistor. The first output reset circuit comprises a first output reset transistor, a gate of the first output reset transistor is connected with the second node, a first pole of the first output reset transistor is connected with the first output end, and a second pole of the first output reset transistor is connected with the first reset signal end to receive the first reset signal; 27. The shift register cell of any of claims 1-26, wherein, ​ The second output reset circuit includes a second output reset transistor, a gate of the second output reset transistor is connected with the fourth node, a first pole of the second output reset transistor is connected with the second output end, and a second pole of the second output reset transistor is connected with a second reset signal end to receive a second reset signal and is configured to reset the second output end by using the second reset signal. The second reset signal has a lower level than the first reset signal.

28. The shift register cell of any of claims 1-27, wherein, The first sub-shift register further includes a third output reset circuit and a third output circuit. The third output reset circuit is configured to reset a third output end under the control of a second node. The third output circuit is configured to output a third clock signal to the third output end under the control of the first node.

29. The shift register cell of claim 28, wherein, The third output reset circuit includes a third output reset transistor, a gate of the third output reset transistor is connected with the second node, a first pole of the third output reset transistor is connected with the third output end, and a second pole of the third output reset transistor is connected with a second reset signal end to receive a second reset signal and is configured to reset the third output end by using the second reset signal. The second reset signal has a lower level than the first reset signal. The third output circuit includes a third output transistor and a third capacitor. A gate of the third output transistor is connected with the first node, a first pole of the third output transistor is connected with a third clock signal end to receive the third clock signal, and a second pole of the third output transistor is connected with the third output end. A first pole of the third capacitor is connected with the gate of the third output transistor, and a second pole of the third capacitor is connected with the second pole of the third output transistor.

30. The shift register cell of any one of claims 1-29, wherein, The first sub-shift register unit further includes an auxiliary reset circuit, a control end of the auxiliary reset circuit is connected with a first input control end to receive the first input control signal, a first end of the auxiliary reset circuit is connected with the second node, and a second end of the auxiliary reset circuit is connected with the first reset signal end to receive the first reset signal, and the auxiliary reset circuit is configured to reset the second node by using the first reset signal in response to the first input control signal.

31. The shift register cell of claim 30, wherein, The auxiliary reset circuit includes an auxiliary reset transistor, a gate of the auxiliary reset transistor is connected with the first input control end, a first pole of the auxiliary reset transistor is connected with the second node, and a second pole of the auxiliary reset transistor is connected with the first reset signal end.

32. A shift register unit comprising: The first sub-shift register unit and the second sub-shift register unit, The first sub-shift register unit includes a first input circuit, a first output reset circuit and a first output circuit, the first input circuit is configured to input a first input signal to a first node in response to a first input control signal, the first output reset circuit is configured to reset a second output end under the control of a second node, and the first output circuit is configured to output a second clock signal to the second output end under the control of the first node. resetting the first output end; the first output circuit is configured to output a first clock signal to the first output end under the control of the first node; the second sub-shift register unit comprises: a second input circuit, a second output reset circuit and a second output circuit; the second input circuit is configured to input the first input signal to a third node in response to a second input control signal; the second output reset circuit is configured to reset a second output end under the control of the fourth node; and the second output circuit is configured to output a second clock signal to the second output end under the control of the fourth node. The fourth node is connected with the second node, and the second output reset circuit is configured to reset the second output end under the control transmitted from the second node to the fourth node.

33. The shift register cell of claim 32, wherein, The first sub-shift register unit further comprises: a second node control circuit comprising a second node charging circuit and a second node reset circuit, wherein the second node charging circuit is connected with a second node charging control end to receive a second node charging control signal, connected with a second node charging signal end to receive a second node charging signal, and connected with the second node, and the second node charging circuit is configured to charge the second node with the second node charging signal in response to the second node charging control signal; the second node reset circuit is connected with the first node and the second node, and connected with the first reset signal end to receive the first reset signal and / or connected with a second reset signal end to receive a second reset signal, and the second node reset circuit is configured to reset the second node with the first reset signal and the second reset signal under the control of the potential of the first node; the level of the second reset signal is lower than the level of the first reset signal, or the level of the second reset signal is equal to the level of the first reset signal.

34. The shift register cell of claim 33, wherein, The second sub-shift register unit does not set the second node control circuit.

35. A shift register unit comprising: an input circuit, a first output reset circuit, a first reset circuit and a first output circuit; the input circuit is configured to charge the first node in response to an input control signal; the first output reset circuit is configured to reset the first output end under the control of the second node; the first output circuit is configured to output a first clock signal to the first output end under the control of the first node; the control end of the first reset circuit is connected with the second node, the first end of the first reset circuit is connected with the first node, and the second end of the first reset circuit is connected with the first output end.

36. The shift register unit of claim 35, further comprising: a second reset circuit, wherein the control end of the second reset circuit is connected with the first reset control end to receive a first reset control signal, the first end of the second reset circuit is connected with the first node, and the second end of the second reset circuit is connected with the first output end.

37. The shift register unit of claim 35 or 36, further comprising: ​ An initial reset circuit, wherein a control terminal of the initial reset circuit is connected with the initial reset control terminal to receive an initial reset control signal, a first terminal of the initial reset circuit is connected with the first node, and a second terminal of the initial reset circuit is connected with the first output terminal.

38. A driving circuit comprising a plurality of cascaded shift register units as claimed in any one of claims 1 to 37.

39. The driving circuit as claimed in claim 38, wherein the first input terminal of each shift register unit except the first stage shift register unit is connected with the first output terminal of the previous stage shift register unit; and the initial reset control terminal of each shift register unit except the last stage shift register unit is connected with the first output terminal of the next stage shift register unit.

40. A display device comprising the driving circuit as claimed in claim 38 or 39. ​

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