Driving circuit, display device, and driving method

Abstract

A driving circuit, a display device (100), and a driving method. The driving circuit may comprise a pulse signal generation circuit. By using the pulse signal generation circuit and a plurality of thin-film transistors, the driving circuit can output signals to control at least two light-emitting diodes to emit light respectively. The driving circuit contains a small number of electronic components, and occupies a small area on a display panel (150), so that a bezel of the display device (100) is narrower. A system-on-chip can be used for implementing part of a compensation function for adjusting display performance of the display panel (150). A random access memory in a timing control module may have more storage space to store a plurality of sets of compensation parameters, so that a time interval for switching the display panel (150) between different display modes is shorter, and the switching efficiency is higher.

Description

Drive circuit, display device and driving method

[0001] This application claims priority to Chinese Patent Application No. 202411029473.4, filed on July 29, 2024, entitled "Driving Circuit, Display Device and Driving Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of terminal device hardware, and more specifically, to a driving circuit, a display device, and a driving method. Background Technology

[0003] With the continuous development of display and driving technologies, multiple light-emitting diodes (LEDs) can be placed in the same pixel circuit to achieve different display modes on the display panel, enriching the user experience. More LEDs mean that the driving circuit used to drive the pixel circuit needs to contain more electronic components, making the driving circuit more complex. At the same time, the driving circuit also occupies a larger area of ​​the display panel's bezel.

[0004] How to minimize the area occupied by the drive circuit while achieving the same driving function is a problem worth considering. Summary of the Invention

[0005] This application provides a driving circuit and a display device. The driving circuit may include a pulse signal generation circuit, which can output a signal to drive at least two light-emitting diodes. This driving circuit contains fewer electronic components, occupies less area on the display panel, and results in a narrower bezel for the display device. This application also provides a driving method where a system-on-a-chip can perform processing operations corresponding to compensation functions for adjusting the display effect of the display panel. The random access memory in the timing control module can have more storage space to store multiple sets of compensation parameters for adjusting the display effect of the display panel, resulting in higher efficiency in switching between different display modes.

[0006] In a first aspect, a driving circuit is provided, comprising: a pulse signal generating circuit, a constant-level input terminal, a first control signal input line, a second control signal input line, a first signal output line, a second signal output line, a third signal output line, a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, and a fourth thin-film transistor. The first signal output line is electrically connected to the pulse signal generating circuit; the second signal output line is electrically connected to the pulse signal generating circuit via the first thin-film transistor, and the second signal output line is also electrically connected to the constant-level input terminal via the fourth thin-film transistor; the third signal output line is electrically connected to the pulse signal generating circuit via the second thin-film transistor. The third signal output line is also electrically connected to the constant-level input terminal via a third thin-film transistor; the first control signal input line is electrically connected to the first thin-film transistor to control the pulse signal generation circuit and the first signal output line to be turned on or off; the first control signal input line is also electrically connected to the second thin-film transistor to control the constant-level input terminal and the second signal output circuit to be turned on or off; the second control signal input line is electrically connected to the third thin-film transistor to control the pulse signal generation circuit and the second signal output line to be turned on or off; the second control signal input line is also electrically connected to the fourth thin-film transistor to control the constant-level input terminal and the first signal output circuit to be turned on or off.

[0007] In some scenarios, the driving circuit in the above scheme can also be called a light-emitting pulse output selector.

[0008] In some examples, the first signal output line can be directly electrically connected to the pulse signal generation circuit, and the first signal output line can be used to output a pulse signal.

[0009] In some examples, a constant-level input can be used to input a high-level or low-level signal to the driver circuit.

[0010] One possibility is that the pulse signals and high-level (or low-level) signals output by the driving circuit can be used to control the connection or disconnection of thin-film transistors in the pixel circuit that is electrically connected to the driving circuit.

[0011] In some examples, the second signal output line can be used to output a pulse signal or a high-level (or low-level) signal, and the third signal output line can be used to output a high-level (or low-level) signal or a pulse signal.

[0012] In this technical solution, by controlling the switching on and off of the thin-film transistors via control signals, the driving circuit can output at least two sets of signals: (pulse signal, pulse signal, high-level (or low-level) signal) and (pulse signal, high-level (or low-level) signal, pulse signal). These two sets of signals can be used to control at least two light-emitting diodes to emit light individually, or in other words, these two sets of signals can be used to drive a pixel circuit containing two light-emitting diodes. Compared to a driving circuit using at least three light-emitting pulse signal generation circuits, the driving circuit provided in this solution contains fewer electronic components, which helps to reduce the area occupied by the driving circuit on the display panel.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the two ends of the first thin-film transistor are electrically connected to the second signal output line and the pulse signal generation circuit, respectively; the two ends of the second thin-film transistor are electrically connected to the third signal output line and the constant level input terminal, respectively; and the gates of both the first and second thin-film transistors are electrically connected to the first control signal input line.

[0014] This technical solution provides a circuit connection scheme for outputting pulse signals, pulse signals and high-level (or low-level) signals. By controlling the first thin-film transistor and the second thin-film transistor to be turned on, the driving circuit can output the above three signals simultaneously.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the two ends of the third thin-film transistor are electrically connected to the second signal output line and the constant level input line, respectively; the two ends of the fourth thin-film transistor are electrically connected to the third signal output line and the pulse signal generation circuit, respectively; and the gates of both the third and fourth thin-film transistors are electrically connected to the second control signal input line.

[0016] This technical solution provides a connection scheme for a selection circuit that outputs either (pulse signal, pulse signal, high level (or low level) signal) or (pulse signal, high level (or low level) signal, pulse signal). By controlling the first and second thin-film transistors to be turned on and the third and fourth thin-film transistors to be turned off, or by controlling the third and fourth thin-film transistors to be turned on and the first and second thin-film transistors to be turned off, the driving circuit can output either of the two sets of signals mentioned above.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the driving circuit further includes a third control signal input line, a fifth thin-film transistor, and a sixth thin-film transistor. The two ends of the fifth thin-film transistor are respectively connected to the third thin-film transistor and a constant-level input terminal; the two ends of the sixth thin-film transistor are respectively electrically connected to the second thin-film transistor and a constant-level input terminal; the third control signal input line is respectively electrically connected to the gate of the fifth thin-film transistor and the gate of the sixth thin-film transistor to control the fifth thin-film transistor to be turned on or off and the sixth thin-film transistor to be turned on or off.

[0018] In this technical solution, by using the third control signal, the fifth thin-film transistor, and the sixth thin-film transistor, the driving circuit can output three pulse signals simultaneously. This is beneficial for realizing more light-emitting modes, such as simultaneous light emission of two light-emitting diodes and intermittent light emission. From the perspective of the display panel, the display panel can provide more types of display modes, which is beneficial for enriching the user experience.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, when a first level signal is input to the first control signal input line, a second level signal is input to the second control signal input line; or, when a second level signal is input to the first control signal input line, a first level signal is input to the second control signal input line; the first level signal is used to control the first thin-film transistor to turn on and the second thin-film transistor to turn on, or to control the third thin-film transistor to turn on and the fourth thin-film transistor to turn on, and the second level signal is used to control the third thin-film transistor to turn off and the fourth thin-film transistor to turn off, or to control the first thin-film transistor to turn off and the second thin-film transistor to turn off.

[0020] This technical solution specifically provides two combinations of the level signals input by the first control signal input line and the level signals input by the second control signal input line, which is beneficial for the driving circuit provided in this application to control pixel circuits containing at least two light-emitting diodes.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, when the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, and the fourth thin-film transistor are all p-type thin-film transistors, the level value input to the constant level input terminal is greater than or equal to the maximum level value output by the pulse signal generation circuit; the first level signal is less than the minimum level value output by the pulse signal generation circuit, and the difference between the minimum level value output by the pulse signal generation circuit and the first level signal is greater than or equal to 1V; the second level signal is greater than or equal to the level value input to the constant level input terminal.

[0022] To reduce the power consumption of the drive circuit, one possible approach is to set the input level at the constant level input terminal to be equal to the maximum output level of the pulse signal generation circuit.

[0023] When the first, second, third, and fourth thin-film transistors are all n-type thin-film transistors, the input level at the constant level input terminal is less than or equal to the minimum output level of the pulse signal generation circuit; the first level signal is greater than the maximum output level of the pulse signal generation circuit, and the difference between the first level signal and the maximum output level of the pulse signal generation circuit is greater than or equal to 1V; the second level signal is less than or equal to the input level at the constant level input terminal.

[0024] This technical solution provides specific relationships between the level signals of the thin-film transistors used to control the thin-film transistors in the driving circuit and the level signals of the thin-film transistors used to control the thin-film transistors in the pixel circuit for different types of thin-film transistors, which is beneficial for realizing the control of the driving circuit over the pixel circuit containing at least two light-emitting diodes.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, the driving circuit has a first mode and a second mode, in the first mode, the first thin-film transistor and the second thin-film transistor are turned on, and the third thin-film transistor and the fourth thin-film transistor are turned off; in the second mode, the first thin-film transistor and the second thin-film transistor are turned off, and the third thin-film transistor and the fourth thin-film transistor are turned on.

[0026] This technical solution specifically provides the setting methods for the first control signal and the second control signal, which is beneficial to enable the driving circuit to output a signal that can drive the pixel circuit containing two light-emitting diodes.

[0027] In conjunction with the first aspect, in some implementations of the first aspect, the driving circuit has a first mode, a second mode, and a third mode. In the first mode, the first and second thin-film transistors are turned on, the third and fourth thin-film transistors are turned off, and the fifth and sixth thin-film transistors are turned on. In the second mode, the first and second thin-film transistors are turned off, the third and fourth thin-film transistors are turned on, and the fifth and sixth thin-film transistors are turned on. In the third mode, the first and second thin-film transistors are turned on, the third and fourth thin-film transistors are turned on, and the fifth and sixth thin-film transistors are turned off.

[0028] This technical solution specifically provides a method for setting a first control signal, a second control signal, and a third control signal. Under this setting method, the driving circuit can output three pulse signals simultaneously, which can control two light-emitting diodes to light up at the same time.

[0029] In conjunction with the first aspect, in some implementations of the first aspect, the driving circuit has a first mode and a second mode. In the first mode, the first and second thin-film transistors are turned on, the third and fourth thin-film transistors are turned off, and the fifth and sixth thin-film transistors are turned on. In the second mode, the first and second thin-film transistors are turned on, the third and fourth thin-film transistors are turned on, and the fifth and sixth thin-film transistors are turned off.

[0030] This technical solution specifically provides another type of setting method for the first, second, and third control signals. In this setting method, one of the light-emitting diodes (LEDs) emits light continuously, while the other can emit light intermittently. By controlling the emission time of the intermittent LED, it is possible to make the two LEDs emit different combinations of light to a certain extent. From the perspective of the display panel, in this case, the display panel can provide more display modes.

[0031] In a second aspect, a display device is provided, comprising a pixel circuit and a driving circuit as described in the first aspect and any possible implementation thereof, wherein the driving circuit is electrically connected to the pixel circuit, and the pixel circuit comprises a first light-emitting diode and a second light-emitting diode.

[0032] In conjunction with the second aspect, in some implementations of the second aspect, the pixel circuit includes a seventh thin-film transistor and an eighth thin-film transistor, the seventh thin-film transistor being electrically connected to a first light-emitting diode, the eighth thin-film transistor being electrically connected to a second light-emitting diode, a second signal output line being electrically connected to the gate of the seventh thin-film transistor to control the seventh thin-film transistor to be turned on or off, and a third signal output line being electrically connected to the gate of the eighth thin-film transistor to control the eighth thin-film transistor to be turned on or off.

[0033] This technical solution provides a specific electrical connection method between the pixel circuit and the driving circuit, which is beneficial for the display device to provide multiple display modes.

[0034] In conjunction with the second aspect, in some implementations of the second aspect, the driving circuit is located on the periphery of the pixel circuit.

[0035] In some scenarios, the above solution can also be understood as the driving circuit being located in the bezel area of ​​the display panel.

[0036] In this technical solution, the driving circuit is set in the bezel area of ​​the display panel, which helps to reduce the area of ​​the bezel area, increase the area ratio of the display area of ​​the display panel, and improve the user experience.

[0037] In conjunction with the second aspect, in some implementations of the second aspect, the first light-emitting diode is used to emit scattered light, and the second light-emitting diode is used to emit collimated light.

[0038] In some scenarios, the display panel is in shared display mode when the first LED is lit, and in privacy display mode when the second LED is lit.

[0039] In conjunction with the second aspect, in some implementations of the second aspect, the display device further includes a timing control module, which is electrically connected to the driving circuit.

[0040] Thirdly, an electronic device is provided, comprising: a display panel, a timing control module, a system-on-a-chip (SoC), a first memory chip, and a second memory chip. Each pixel circuit in the display panel includes a first light-emitting diode (LED) and a second LED. In a first display mode of the display panel, the first LED emits light; in a second display mode of the display panel, the second LED emits light. The first memory chip is electrically connected to the SoC, and the second memory chip is electrically connected to the timing control module. The first memory chip is programmed with a first compensation parameter and a second compensation parameter, and the second memory chip is programmed with a third compensation parameter and a fourth compensation parameter. The first and third compensation parameters are used to adjust the display effect of the display panel in the first display mode, and the second and fourth compensation parameters are used to adjust the display effect of the display panel in the second display mode.

[0041] In some examples, the timing control module may include a timing control chip.

[0042] In some scenarios, the above solution can also be understood as a part of the compensation function used to adjust the display effect of the display panel being implemented by the system-on-a-chip, and another part being implemented by the timing control module.

[0043] In this technical solution, the compensation parameters corresponding to the compensation function used to adjust the display effect of the display panel are respectively burned onto two memory chips. When the electronic device is powered on, the system-on-a-chip and the timing control module can read the compensation parameters from these two memory chips respectively, so that the two sets of compensation parameters can be stored in the random access memory at the same time. In the scenario of switching display modes, the electronic device can directly read the compensation parameters from the random access memory without reading from the memory chips. Therefore, the reading efficiency is higher, the interval of display mode switching is shorter, and the switching efficiency is higher.

[0044] In conjunction with the third aspect, in some implementations of the third aspect, the first compensation parameter and the second compensation parameter include one or more of the following: overvoltage drive compensation parameter, anti-burn-in compensation parameter, or MURA elimination compensation parameter.

[0045] In some scenarios, the above solution can also be understood as follows: the compensation function corresponding to the overvoltage drive compensation parameter, the anti-burn-in compensation parameter, or the MURA elimination compensation parameter is implemented by the system-on-a-chip.

[0046] The various compensation parameters provided in this technical solution involve a large amount of data and occupy a significant amount of storage space. By storing these compensation parameters on the corresponding memory chip of the system-on-a-chip (SoC), this portion of the compensation parameters can be processed by the SoC, while the remaining smaller compensation parameters are processed by the timing control module. This increases the available space of the random access memory (RAM) in the timing control module and allows both sets of compensation parameters to be loaded into the electronic device's RAM simultaneously, thus shortening the display panel's display mode switching time. Furthermore, since SoCs generally have stronger data processing capabilities, from this perspective, the implementation of this technical solution also helps improve the efficiency of the display panel's display mode switching.

[0047] In conjunction with the third aspect, in some implementations of the third aspect, the third compensation parameter and the fourth compensation parameter include one or more of the following: built-in self-test compensation parameter, data exchange compensation parameter, jitter compensation parameter, or brightness control management compensation parameter.

[0048] In some scenarios, the above solution can also be understood as follows: the compensation function corresponding to the built-in self-test compensation parameters, data exchange compensation parameters, jitter compensation parameters, or brightness control management compensation parameters is implemented by the timing control module.

[0049] In this technical solution, compensation parameters that are closely related to the timing control module are stored on a memory chip associated with the timing control module. The timing control module is responsible for processing these compensation parameters, which makes the electronic device more efficient in processing compensation parameters and the display panel display effect better.

[0050] In conjunction with the third aspect, in some implementations of the third aspect, the first light-emitting diode is used to emit scattered light, and the second light-emitting diode is used to emit collimated light.

[0051] In some scenarios, the display panel is in shared display mode when the first LED is lit, and in privacy display mode when the second LED is lit.

[0052] Fourthly, a driving method is provided, applied to an electronic device in the third aspect and any possible implementation thereof, the method comprising: in response to the electronic device being powered on, a system-on-a-chip (SoC) reads a first compensation parameter and a second compensation parameter from a first storage chip, and a timing control module reads a third compensation parameter and a fourth compensation parameter from a second storage chip; the SoC writes the first compensation parameter and the second compensation parameter into its random access memory (RAM), and the timing control module writes the third compensation parameter and the fourth compensation parameter into its own RAM; the SoC configures its registers using the first compensation parameter, and the timing control module configures its registers using the third compensation parameter; and the electronic device displays a first display mode.

[0053] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the method further includes: in response to the operation of switching display modes, the system-on-a-chip configures the registers of the system-on-a-chip through the second compensation parameter, the timing control module configures the registers of the timing control module through the fourth compensation parameter; and the electronic device displays the second display mode.

[0054] In this technical solution, the compensation parameters corresponding to the compensation function used to adjust the display effect of the display panel are respectively burned onto two memory chips. When the electronic device is powered on, the system-on-a-chip and the timing control module can read the compensation parameters from these two memory chips respectively, so that the two sets of compensation parameters can be stored in the random access memory at the same time. In the scenario of switching display modes, the electronic device can directly read the compensation parameters from the random access memory without reading from the memory chips. Therefore, the reading efficiency is higher, the interval of display mode switching is shorter, and the switching efficiency is higher. Attached Figure Description

[0055] Figure 1 is a schematic diagram of a display device provided in an embodiment of this application.

[0056] Figure 2 is a schematic diagram of a pixel circuit provided in an embodiment of this application.

[0057] Figure 3 is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0058] Figure 4 is a schematic diagram of a light-emitting diode provided in an embodiment of this application.

[0059] Figure 5 is a timing diagram of the pixel circuit in Figure 2.

[0060] Figure 6 is another timing diagram of the pixel circuit in Figure 2.

[0061] Figure 7 is a schematic diagram of a driving circuit provided in an embodiment of this application.

[0062] Figure 8 is a schematic diagram of another driving circuit provided in an embodiment of this application.

[0063] Figure 9 is a timing diagram of the drive circuit in Figure 8.

[0064] Figure 10 is a schematic diagram of another driving circuit provided in an embodiment of this application.

[0065] Figure 11 is a timing diagram of the drive circuit in Figure 10.

[0066] Figure 12 is another timing diagram of the drive circuit in Figure 10.

[0067] Figure 13 is a schematic diagram of an electronic device provided in an embodiment of this application.

[0068] Figure 14 is a schematic diagram of a processing submodule and a control submodule provided in an embodiment of this application.

[0069] Figure 15 is a schematic diagram of a driving method provided in an embodiment of this application. Detailed Implementation

[0070] The embodiments of this application are described in detail below, and examples of these embodiments are illustrated in the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0071] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. In the description of this application, it should be understood that the terms “center,” “longitudinal,” “lateral,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0072] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0073] Figure 1 is a schematic diagram of the structure of a display device 100 provided in an embodiment of this application. The display device 100 may include a display panel 150, which may include multiple pixel circuit modules 10, gate driver circuit modules 20 and source driver circuit modules 30. In some scenarios, the gate driver circuit module 20 may also be referred to as the gate driver circuit module 20.

[0074] In some examples, the pixel circuit module 10 may include one or more light-emitting diodes (LEDs). Exemplarily, these LEDs may be one or more of organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), or micro light-emitting diodes (Micro LEDs). By supplying current to the LEDs in the pixel circuit module 10, these LEDs can emit light. By controlling the magnitude of the current supplied to the LEDs, the intensity of the light emitted by the LEDs can be roughly controlled.

[0075] In some examples, the pixel circuit module 10 may also include a thin-film transistor (TFT) for controlling the magnitude of the current flowing into the light-emitting diode (LED). Exemplarily, by adjusting the voltage applied to the gate of the TFT, the connectivity between the source and drain of the TFT can be changed, thereby adjusting the magnitude of the current flowing through the source and drain of the TFT. The TFT can be connected in series with the LED, so that a change in the current flowing into the TFT will correspondingly change the current flowing into the LED.

[0076] In some examples, the pixel circuit module 10 may also include a storage capacitor, which can be used to store charge and keep the voltage across the light-emitting diode relatively stable during one light-emitting cycle of the light-emitting diode, so that the magnitude of the current flowing through the light-emitting diode does not change significantly and the intensity of the light emitted by the light-emitting diode can remain relatively stable.

[0077] One possibility is that the storage capacitor can be connected in roughly parallel with the light-emitting diode (LED). When the source and drain of the thin-film transistor (TFT) are conducting, the LED emits light, and the voltage across the storage capacitor is the same as the voltage across the LED. When the source and drain of the TFT are disconnected, the voltage across the storage capacitor can remain essentially constant. In this way, the current flowing through the LED can remain essentially constant, and the intensity of the light emitted by the LED is relatively stable.

[0078] In some examples, as shown in Figure 1, multiple pixel circuit modules 10 in the display panel 150 can be arranged in an array to form a pixel circuit array.

[0079] In some examples, the gate driver circuit module 20 can be used to control the switching of the thin-film transistor in the pixel circuit module 10. For example, when it is necessary to write data to the light-emitting diode to make the light-emitting diode light up, the gate driver circuit module 20 can control the source and drain of the thin-film transistor to be turned on; in other cases, the gate driver circuit module 20 can control the source and drain of the thin-film transistor to be turned off.

[0080] For example, the gate drive circuit module 20 can be electrically connected to the gate of the thin film transistor and can transmit a voltage signal to the gate of the thin film transistor. When the magnitude of the voltage signal satisfies the voltage threshold of the conduction voltage between the source and drain of the thin film transistor, the source and drain of the thin film transistor can be turned on.

[0081] One possibility is that the gate driver circuit module 20 may include a level shifter, which can be used to adjust the voltage input from the gate driver circuit module 20 to the gate of the thin-film transistor so that the voltage input from the gate driver circuit module 20 to the gate of the thin-film transistor can meet the requirements for controlling the conduction of the source and drain of the thin-film transistor.

[0082] By way of example and not limitation, the display panel 150 may include a plurality of gate drive circuit modules 20. Exemplarily, as shown in FIG1, the display panel 150 may include two gate drive circuit modules 20, which are located on the left and right sides of the pixel circuit array, respectively. Exemplarily, the gate drive circuit modules 20 included in the display panel 150 may also be located between two adjacent columns of pixel circuits in the pixel circuit array.

[0083] In some examples, the source drive circuit module 30 can be used to receive data signals from the control module and convert these data signals into voltage or current, which can then be transmitted to the pixel circuit module 10.

[0084] For example, the source drive circuit module 30 may include a digital-to-analog converter (DAC) that can be used to convert digital signals into analog signals, which can be used to control the light-emitting diodes in the pixel circuit module 10 to emit light.

[0085] In some examples, the display device 100 may also include a circuit board Bc1, which may include multiple electrical connection lines and can be used for electrical connections between the display device 100 and external circuitry. Exemplarily, the circuit board Bc1 may be a flexible printed board (FPC).

[0086] In some examples, the display device 100 may also include a control module 200. For example, one end of the circuit board Bc1 may be electrically connected to the gate drive circuit module 20 and the source drive circuit module 30 in the display panel 150, and the other end of the circuit board Bc1 may be electrically connected to the control module 200. The display panel 150 can receive one or more control signals sent by the control module 200 through the circuit board Bc1.

[0087] Referring again to Figure 1, the pixel circuit array composed of multiple pixel circuit modules 10 is roughly located in region Ar2 of Figure 1. In some scenarios, this region Ar2 of the display panel 150 can also be called the light-emitting region Ar2 or the active area (AA). Region Ar2 is roughly located in the middle of the display panel 150. The area on the display panel 150 other than region Ar2 (region Ar1 in Figure 1), or the area located around region Ar2, can be called the border area of ​​the display panel 150. In some scenarios, region Ar1 can also be called the black matrix (BM).

[0088] The gate drive circuit module 20 and / or the source drive circuit module 30 on the display panel 150 may be located on the aforementioned region Ar1. The gate drive circuit module 20 is electrically connected to the pixel circuit module 10, and the source drive circuit module 30 is electrically connected to the pixel circuit module 10. The lines of the gate drive circuit module 20 for electrical connection with the pixel circuit module 10 may also be partially located on region Ar1, and the lines of the source drive circuit module 30 for electrical connection with the pixel circuit module 10 may also be located on region Ar1.

[0089] It should be noted that the more pixel circuit modules 10 there are, or the more electronic components contained in a single pixel circuit module 10 (e.g., multiple light-emitting diodes are included in a pixel circuit module 10), the more electronic components may be contained in the gate driver circuit module 20, and the more complex the electrical connection lines between the gate driver circuit module 20 and the pixel circuit module 10 may be. Similarly, the more electronic components contained in the source driver circuit module 30, the more complex the electrical connection lines between the source driver circuit module 30 and the pixel circuit module 10 may be. In this case, the area Ar1 used to set the gate driver circuit module 20 and the source driver circuit module 30, as shown in Figure 1, will also be larger, or in other words, the area of ​​the bezel on the display panel 150 will be larger, and the area ratio of the display area of ​​the display panel 150 will be smaller.

[0090] The following describes the driving circuit for driving a pixel circuit containing multiple light-emitting diodes, based on the embodiment of this application, with the case of two light-emitting diodes in the same pixel circuit as the main focus. The driving circuit for three or more pixel circuits can be configured with reference to this.

[0091] As previously explained, the pixel circuit may include thin-film transistors (TFTs) for controlling the light-emitting diodes (LEDs). These TFTs can be either n-type or p-type. For an n-type TFT, when a high-level voltage is applied to its gate, its source and drain are connected; when a low-level voltage is applied to its gate, its source and drain are not connected. For a p-type TFT, when a high-level voltage is applied to its gate, its source and drain are not connected; when a low-level voltage is applied to its gate, its source and drain are connected.

[0092] As one possible implementation, Figure 2 shows a pixel circuit Cd10 provided in an embodiment of this application. Thin-film transistors T3 and T4 in the pixel circuit Cd10 can both be n-type thin-film transistors. For example, both of these thin-film transistors can be thin-film transistors made of indium gallium zinc oxide (IGZO). Thin-film transistors T1, T2, T5, T6-1, T6-2, T7-1, T7-2, and T8 can all be p-type thin-film transistors. For example, these thin-film transistors can be thin-film transistors made of low-temperature polysilicon (LTPS).

[0093] As one possible implementation, Figure 3 shows a pixel circuit Cd11 provided in an embodiment of this application. Thin-film transistors T3 and T4 in the pixel circuit Cd11 can both be p-type thin-film transistors; for example, both of these thin-film transistors can be thin-film transistors made of LTPS. Thin-film transistors T1, T2, T5, T6-1, T6-2, T7-1, T7-2, and T8 can all be n-type thin-film transistors; for example, these thin-film transistors can all be thin-film transistors made of IGZO.

[0094] As an example, the following description focuses on the pixel circuit Cd10 shown in Figure 2 to illustrate the driving circuit provided in the embodiments of this application.

[0095] Referring to Figure 2, the pixel circuit Cd10 may include light-emitting diodes L1 and L2, which can emit light independently.

[0096] One possibility is that LED L1 and LED L2 can have different optical characteristics. In this way, by controlling LED L1 or LED L2 to emit light separately, the pixel circuits containing these two types of LEDs can produce different display effects.

[0097] For example, LEDs L1 and L2 can have different emission angles. For instance, LED L1 can emit more diffused light, while LED L2 can emit more concentrated, narrow beams of light, such as collimated light. In other words, referring to Figure 4, the angular range of the light emitted by LED L1 can be α, and the angular range of the light emitted by LED L2 can be β. Here, α can be greater than 0°, and β can be approximately 0°. In some scenarios, LED L1 can also be called a diffused LED, and LED L2 can also be called a direct-emitting LED.

[0098] Based on the difference in the emission angles of the two types of LEDs, when LED L1 in the pixel circuit emits light alone, the user can only observe the light emitted by LED L1 within a small angular range; when LED L2 in the pixel circuit emits light alone, the user can observe the light emitted by LED L2 within a larger range.

[0099] From the perspective of the display panel 150, all pixel circuit modules 10 in the display panel 150 can include the aforementioned light-emitting diodes L1 and L2. Based on this, when all pixel circuit modules 10 on the display panel 150 emit light individually using LEDs L1, the user can observe the image displayed on the display panel 150 over a wider range; in other words, the viewing angle range of the display panel 150 is large. Within this large viewing angle range, multiple users may be able to observe the image displayed on the display panel 150, and in this scenario, the display panel 150 can roughly present a shared display effect. When all pixel circuit modules 10 on the display panel 150 emit light individually using LEDs L2, the user can observe the image displayed on the display panel 150 within a smaller viewing angle range; in other words, the viewing angle range of the display panel 150 is small. Within this smaller viewing angle range, only one user may be able to observe the image displayed on the display panel 150, and in this scenario, the display panel 150 can roughly present a privacy display effect.

[0100] For example, the maximum luminous intensity of LED L1 and LED L2 can be different. For instance, the maximum luminous intensity of LED L1 can be 100 units, and the maximum luminous intensity of LED L2 can be 10 units.

[0101] Based on the difference in luminous intensity between the two types of LEDs, in the scenario where LED L1 in the pixel circuit module emits light alone, the user can observe the light emitted by LED L1 when the ambient light is relatively bright; in the scenario where LED L2 in the pixel circuit module 10 emits light alone, the user can observe the light emitted by LED L2 when the ambient light is relatively dim.

[0102] From the perspective of the display panel 150, all pixel circuit modules 10 in the display panel 150 can include the aforementioned light-emitting diodes L1 and L2. Based on this, when all pixel circuit modules 10 on the display panel 150 emit light individually using light-emitting diodes L1, the user can observe the image displayed on the display panel 150 in scenes with high ambient light (such as outdoor scenes); when all pixel circuit modules 10 on the display panel 150 emit light individually using light-emitting diodes L2, the user can observe the image displayed on the display panel 150 in scenes with low ambient light (such as night scenes).

[0103] One possibility is that LED L1 and LED L2 can have roughly the same performance or properties. In this case, LED L1 and LED L2 can largely substitute for or complement each other.

[0104] For example, by adjusting the colors of the two light-emitting diodes (LEDs) separately, more accurate control over the color of the light emitted by the pixel circuit module 10 can be achieved. For example, if either LED L1 or LED L2 fails, the other LED can be used to emit light, thereby increasing the functional reliability of the pixel circuit module 10. For example, by using two LEDs simultaneously, the brightness of the light emitted by the pixel circuit module 10 can be increased, thus improving the visibility of the light emitted by the pixel circuit module 10 in bright ambient light conditions.

[0105] The above-described application scenario of setting two light-emitting diodes in the same pixel circuit is merely exemplary, and this application does not limit it. One possibility is that the same pixel circuit may also include three or more light-emitting diodes, and the application scenarios of these light-emitting diodes can be similar to those of the two light-emitting diodes described above.

[0106] In the following examples, the source and drain of a thin-film transistor (TFT) are not distinguished. Either the source or drain of a TFT can be referred to as one end of the TFT, and correspondingly, either the drain or source can be referred to as the other end. In other words, in the following examples, one end and the other end of a TFT can refer to one of the source and the other of the drain.

[0107] Referring again to Figure 2, the pixel circuit Cd10 may further include thin-film transistors T5, T6-1, and T6-2. One end of thin-film transistor T5 is connected to a high-level voltage VDD, and the other end is electrically connected to one end of thin-film transistor T6-1 and one end of thin-film transistor T6-2. The end of thin-film transistor T6-1 furthest from thin-film transistor T5 is electrically connected to the anode of light-emitting diode L1, and the end of thin-film transistor T6-2 furthest from thin-film transistor T5 is electrically connected to the anode of light-emitting diode L2.

[0108] One possibility is that the gate of thin-film transistor T5 can be electrically connected to the input line of signal S5, or in other words, thin-film transistor T5 can be controlled by signal S5; the gate of thin-film transistor T6-1 can be electrically connected to the input line of signal S6, or in other words, thin-film transistor T6-1 can be controlled by signal S6; and the gate of thin-film transistor T6-2 can be electrically connected to the input line of signal S7, or in other words, thin-film transistor T6-2 can be controlled by signal S7.

[0109] Considering LEDs L1 and L2, the anode of LED L1 is electrically connected to TFT T6-1, and the cathode of LED L1 is connected to a low level (e.g., grounded or connected to the negative terminal of the power supply). The anode of LED L2 is electrically connected to TFT T6-2, and the cathode of LED L2 is connected to a low level (e.g., grounded or connected to the negative terminal of the power supply). When both TFT T5 and TFT T6-1 are turned on, the anode of LED L1 can be connected to a high level VDD, and LED L1 will emit light. When both TFT T5 and TFT T6-2 are turned on, the anode of LED L2 can be connected to a high level VDD, and LED L2 will emit light.

[0110] In some examples, a thin-film transistor T1 is also connected to the connection line between thin-film transistor T5 and thin-film transistor T6-1 or thin-film transistor T6-2. This thin-film transistor T1 can be used to control the magnitude of the current flowing into thin-film transistor T6-1 or thin-film transistor T6-2. For example, by controlling the connectivity between the source and drain of thin-film transistor T1, the magnitude of the current flowing through thin-film transistor T1 can be controlled, thereby achieving control over the magnitude of the current flowing into thin-film transistor T6-1 or thin-film transistor T6-2.

[0111] In some examples, the pixel circuit Cd10 may also include a thin-film transistor T2 for controlling data writing. One end of the thin-film transistor T2 may be electrically connected to a data input line, and the other end may be connected between thin-film transistors T1 and T5. When the thin-film transistor T2 is turned on, the data to be written to the light-emitting diode L1 or L2 may be input via the thin-film transistor T2 to the connection line between thin-film transistors T5 and T6-1 or to the connection line between thin-film transistors T5 and T6-2.

[0112] When both thin-film transistors T5 and T6-1 are turned on, the data input via thin-film transistor T2 can be input to LED L1, and LED L1 can emit light according to the input data; similarly, when both thin-film transistors T5 and T6-2 are turned on, the data can be input to LED L2, and LED L2 can emit light according to the input data.

[0113] In some examples, the pixel circuit Cd10 may further include thin-film transistors T8, T7-1, and T7-2 for controlling the anode reset of light-emitting diodes L1 and L2 and the optical black storage (OBS) process of the pixel circuit Cd10. One end of thin-film transistor T8 can be electrically connected to the input line of the initial voltage VINIT3, and the other end can be connected between the aforementioned thin-film transistors T1 and T6-1, and between thin-film transistors T1 and T6-2. One end of thin-film transistor T7-1 is electrically connected to the anode of light-emitting diode L1, and the other end is electrically connected to the input line of the initial voltage VINIT2. One end of thin-film transistor T7-2 is electrically connected to the anode of light-emitting diode L2, and the other end is electrically connected to the input line of the initial voltage VINIT2.

[0114] One possibility is that thin-film transistors T8, T7-1, and T7-2 can be controlled by the same control signal S4, or that the gates of thin-film transistors T8, T7-1, and T7-2 can all be electrically connected to the input line of control signal S4.

[0115] As one possible implementation, the thin-film transistor T8 can consist of two transistors connected in series, both of which are controlled by the aforementioned control signal S4.

[0116] In some examples, the pixel circuit Cd10 may also include thin-film transistors T3 and T4 for controlling the gate reset of thin-film transistor T1. One end of thin-film transistor T3 may be electrically connected to the gate of thin-film transistor T1, and the other end of thin-film transistor T3 may be electrically connected to one end of thin-film transistor T4. The end of thin-film transistor T4 furthest from thin-film transistor T3 may be electrically connected to the input line of the initial voltage VINIT1. When both thin-film transistors T3 and T4 are turned on, the initial voltage VINIT1 can be input to the gate of thin-film transistor T1, and thin-film transistor T1 can perform a gate reset.

[0117] One possible scenario is that the end of the aforementioned thin-film transistor T3 connected to thin-film transistor T4 is also connected to the end of thin-film transistor T6-1 away from LED L1, and the end of thin-film transistor T3 connected to thin-film transistor T4 is also connected to the end of thin-film transistor T6-2 away from LED L2. Alternatively, the end of the thin-film transistor T3 connected to thin-film transistor T4 is also connected to the end of thin-film transistor T1 away from thin-film transistor T5. In this case, with both thin-film transistors T2 and T3 conducting, data can be input to thin-film transistor T1, and threshold voltage VTH compensation can be achieved for thin-film transistor T1.

[0118] For example, the gate of thin-film transistor T3 can be electrically connected to the input line of signal S3, or in other words, thin-film transistor T3 can be controlled by signal S3; the gate of thin-film transistor T4 can be electrically connected to the input line of signal S2, or in other words, thin-film transistor T4 can be controlled by signal S2.

[0119] In some examples, the pixel circuit Cd10 may also include a capacitor C1, which can be used to keep the current flowing into the light-emitting diode L1 (or light-emitting diode L2) relatively stable during the emission of light, thereby maintaining the brightness of the light-emitting diode L1 (or light-emitting diode L2) relatively stable.

[0120] One possibility is that one end of capacitor C1 can be connected to a high-level voltage VDD, and the other end of capacitor C1 can be electrically connected to the end of thin-film transistor T3 that is connected to the gate of thin-film transistor T1. Alternatively, the end of capacitor C1 furthest from the high-level voltage VDD can be electrically connected to the gate of thin-film transistor T1.

[0121] Figure 5 shows the timing diagram of the pixel circuit Cd10 driving the light-emitting diode L1, and Figure 6 shows the timing diagram of the pixel circuit Cd10 driving the light-emitting diode L2. Overall, the operating time of the pixel circuit Cd10 can be roughly divided into 6 stages: the pre-OBS stage (St1), the anode reset stage (St2), the gate reset stage (St3), the data writing and compensation stage (St4), the post-OBS stage (St51), and the light-emitting stage (St6).

[0122] During the pre-OBS phase and anode reset phase, signals S1, S5, S6, and S7 are all high, and thin-film transistors T2, T5, T6-1, and T6-2 are all off. Signals S2 and S3 are both low, and thin-film transistors T3 and T4 are both off. Signal S4 is low, and thin-film transistors T7-1, T-2, and T8 are all on. The initial voltage VINIT3 can be a positive voltage (e.g., 4V, 5V, or 6V), and the initial voltage VINIT2 can be zero or negative (e.g., 0V, -1V, or -2V). During anode reset, the anode of LED L1 is written with the initial voltage VINIT2, and the charge on the anode of LED L1 is cleared.

[0123] During the gate reset phase, signals S2 and S3 are at high levels, and both thin-film transistors T3 and T4 are in the on state. The initial voltage VINIT1 can be a negative voltage (e.g., -2V, -3V, or -4V). The gate of thin-film transistor T1 is written with the initial voltage VINIT1, thus resetting it.

[0124] During the data writing and compensation phase, signal S1 is at a low level, signal S3 is at a high level, thin film transistors T2 and T3 are both in the conducting state, the threshold voltage VTH of thin film transistor T1 is compensated, and the data voltage input from the data input line can be written to capacitor C1 through thin film transistors T2, T1 and T3.

[0125] In the post-OBS stage, signal S4 is low, and thin-film transistor T8 is on; signals S1, S5, S6, and S7 are high, and thin-film transistors T2, T5, T6-1, and T6-2 are off; signals S3 and S4 are low, and thin-film transistors T3 and T4 are off. The end of thin-film transistor T1 closest to thin-film transistor T8 can be programmed with the initial voltage VINIT3.

[0126] During the light-emitting stage, referring to Figure 5, signals S5 and S6 are at low levels, and both thin-film transistors T5 and T6-1 are in the on state. Current flows in from the high level VDD, through thin-film transistors T5, T1, and T6-1, and into LED L1, at which time LED L1 emits light. Referring to Figure 6, signals S5 and S7 are at low levels, and both thin-film transistors T5 and T6-2 are in the on state. Current flows in from the high level VDD, through thin-film transistors T5, T1, and T6-2, and into LED L2, at which time LED L2 emits light.

[0127] When signals S5, S6, and S7 are all at low levels, thin-film transistors T5, T6-1, and T6-2 are all in the conducting state, and current flows in from the high level VDD. On one hand, current flows into LED L1 through thin-film transistors T5, T1, and T6-1, and on the other hand, current flows into LED L2 through thin-film transistors T5, T1, and T6-2. At this time, LEDs L1 and L2 can emit light simultaneously.

[0128] The composition and circuit connection method of the pixel circuit Cd11 in Figure 3 are basically the same as those of the pixel circuit Cd10. For related descriptions, please refer to the relevant content in the pixel circuit Cd10.

[0129] Unlike pixel circuit Cd10, the p-type thin-film transistors in pixel circuit Cd10 are replaced by n-type thin-film transistors in pixel circuit Cd11, and vice versa. Therefore, the driving methods for pixel circuit Cd11 and Cd10 differ. For example, in pixel circuit Cd10, signal S3 needs to be high to turn on thin-film transistor T3, while in pixel circuit Cd11, thin-film transistor T3 turns on when signal S3 is low. Similarly, in pixel circuit Cd10, signal S6 needs to be low to turn on thin-film transistor T6-1, while in pixel circuit Cd11, thin-film transistor T3 turns on when signal S6 is high.

[0130] Based on the above differences, the timing diagrams for driving LED L1 and LED L2 using the pixel circuit Cd11 can be roughly referenced in Figures 5 and 6. The difference is that the high-level positions in Figure 5 or 6 correspond approximately to low-level positions in the timing diagram of the pixel circuit Cd11, and vice versa. For simplicity, the explanation of the timing diagram of the pixel circuit Cd11 will not be elaborated upon.

[0131] Figure 7 shows a signal generation circuit Cd20 provided in an embodiment of this application. The signal generation circuit Cd20 can be used to output signals S5, S6 and S7 for controlling the thin film transistors T5, T6-1 and T6-2 in the aforementioned pixel circuit Cd10 or Cd11.

[0132] One possible scenario is that the signal generation circuit Cd20 may include sub-circuits Cd21, Cd22, and Cd23, wherein sub-circuit Cd21 can be used to generate signal S5, sub-circuit Cd22 can be used to generate signal S6, and sub-circuit Cd23 can be used to generate signal S7.

[0133] In some scenarios, the aforementioned sub-circuits Cd21, Cd22, and Cd23 can all be referred to as gate-on-array (GOA) circuits, or simply EM GOA circuits. Generally, an EM GOA circuit can include more than 10 thin-film transistors or other electronic components. Thus, the aforementioned signal generation circuit Cd20 contains at least 30 thin-film transistors or other electronic components. These electronic components and their interconnections are all located on region Ar1 (the border area) in Figure 1, and region Ar1 has a relatively large area.

[0134] In order to reduce the area occupied by the circuits used to generate signals S5, S6 and S7 on the display panel 150, as shown in FIG8, this application embodiment provides a signal generation circuit Cd30. Compared with the above-mentioned signal generation circuit Cd20, the signal generation circuit Cd30 contains fewer electronic components such as thin film transistors, and when the signal generation circuit Cd30 is fabricated on the display panel 150, it occupies a smaller area.

[0135] As shown in Figure 8, the signal generation circuit Cd30 may include a sub-circuit Cd31, which can be used to generate the signal Sg567. One possible scenario is that the sub-circuit Cd31 can be an EM GOA circuit.

[0136] For example, the signal generation circuit Cd30 may include an input line for signal Sg11 and an input line for signal Sg12. Signals Sg11 and Sg12 generated by an external circuit can be input to the signal generation circuit Cd30 via these two lines, respectively. One possible scenario is that signals Sg11 and Sg12 can be used to control the signal generation circuit Cd30 to output signals S5, S6, or S7.

[0137] For example, the signal generation circuit Cd30 may include output lines for signal S5, signal S6, and signal S7. The output lines for signal S5, signal S6, and signal S7 can be electrically connected to the input lines for signal S5, signal S6, and signal S7 in the aforementioned pixel circuit Cd10 or pixel circuit Cd11, respectively, so that the signals S5, S6, and S7 generated by the signal generation circuit Cd30 can be input to the aforementioned pixel circuit Cd10 or pixel circuit Cd11.

[0138] One possibility is that the sub-circuit Cd31 can be electrically connected to the output line of signal S5.

[0139] For example, the signal generation circuit Cd30 may also include thin-film transistors Ta, Tb, Tc, and Td.

[0140] In this circuit, the gates of thin-film transistors Ta and Tb can be electrically connected to the input line of signal Sg11, and the gates of thin-film transistors Tc and Td can be electrically connected to the input line of signal Sg12. In other words, signal Sg11 can be used to control the on / off state of the source and drain of thin-film transistor Ta, and signal Sg11 can also be used to control the on / off state of the source and drain of thin-film transistor Tb. Signal Sg12 can be used to control the on / off state of the source and drain of thin-film transistor Tc, and signal Sg12 can also be used to control the on / off state of the source and drain of thin-film transistor Td.

[0141] One end of the thin-film transistor Ta can be electrically connected to the sub-circuit Cd31, and the other end can be electrically connected to the output line of signal S6. In other words, when the thin-film transistor Ta is turned on, the signal S567 generated by the sub-circuit Cd31 can be output by the output line of signal S6.

[0142] One end of the thin-film transistor Tb can be electrically connected to the constant-level input terminal Vin in the signal generation circuit Cd30, and the other end can be electrically connected to the output line of signal S7. Here, the constant-level input terminal Vin can input a high-level signal VGH. In other words, when the thin-film transistor Tb is turned on, the output line of signal S7 can output a high-level signal VGH.

[0143] One end of the thin-film transistor Tc can be electrically connected to the constant-level input terminal Vin in the signal generation circuit Cd30, and the other end can be electrically connected to the output line of signal S6. The constant-level input terminal Vin can input a high-level signal VGH. In other words, when the thin-film transistor Tc is turned on, the output line of signal S6 can output a high-level signal VGH.

[0144] One end of the thin-film transistor Td can be electrically connected to the sub-circuit Cd31, and the other end can be electrically connected to the output line of signal S7. In other words, when the thin-film transistor Td is turned on, the signal S567 generated by the sub-circuit Cd31 can be output by the output line of signal S7.

[0145] Based on the above description, the output line of signal S5 of signal generation circuit Cd30 can output signal S567, the output line of signal S6 can output signal S567 or a high-level signal VGH, and the output line of signal S7 can output signal S567 or a high-level signal VGH. Signal Sg11 can be used to control the conduction of thin-film transistor Ta so that signal S567 can be output from the output line of signal S6. Signal Sg11 can also be used to control the conduction of thin-film transistor Tb so that the high-level signal VGH can be output from the output line of signal S7. Signal Sg12 can be used to control the conduction of thin-film transistor Tc so that the high-level signal VGH can be output from the output line of signal S6. Signal Sg12 can also be used to control the conduction of thin-film transistor Td so that signal S567 can be output from the output line of signal S7.

[0146] It should be noted that the high-level signal VGH input to the constant-level input terminal Vin in the signal generation circuit Cd30 can be used to control the p-type thin-film transistor T6-1 or thin-film transistor T6-2 in the pixel circuit Cd10 to turn off. For the pixel circuit Cd11, since thin-film transistors T6-1 and T6-2 are n-type thin-film transistors, in this case, in order to control the n-type thin-film transistor T6-1 or T6-2 to turn off, the constant-level input terminal Vin in the signal generation circuit Cd30 in Figure 8 can be input with a low-level signal VGL.

[0147] Here, we will provide a unified explanation of the multiple level signals in the signal generation circuit Cd30.

[0148] When the thin-film transistors Ta, Tb, Tc, or Td in the signal generation circuit Cd30 are all p-type thin-film transistors, let: the high-level value of the pulse signal generated by the sub-circuit Cd31 be Vu, the low-level value be Vd, the larger value of the signal input by signal Sg11 or signal Sg12 be Vb, the smaller value be Vs, and the high-level signal VGH input by the constant-level input terminal Vin be VGH.

[0149] The values ​​of the above-mentioned level signals can roughly satisfy the following relationship: VGH≥Vu, Vs <Vd,Vb≥VGH。

[0150] For example, Vs can be 1V, 2V, or 3V smaller than Vd, etc. For example, in order to reduce the power consumption of the drive circuit, VGH can be equal to Vu.

[0151] When the thin-film transistors Ta, Tb, Tc, or Td in the signal generation circuit Cd30 are all n-type thin-film transistors, let: the high-level value of the pulse signal generated by the sub-circuit Cd31 be Vu, the low-level value be Vd, the larger value of the signal input by signal Sg11 or signal Sg12 be Vb, the smaller value be Vs, and the low-level signal VGL input by the constant-level input terminal Vin be VGL. The values ​​of the above level signals can roughly satisfy the following relationships: VGL≤Vd, Vb>Vu, Vs≤VGL.

[0152] For example, Vb can be 1V, 2V, or 3V greater than Vu, etc. For example, VGL can be equal to Vd.

[0153] The aforementioned thin-film transistors Ta, Tb, Tc, and Td can be either p-type or n-type thin-film transistors. The timing diagram of the signal generation circuit Cd30 is illustrated below using a p-type thin-film transistor as an example.

[0154] As shown in Figure 9, sub-circuit Cd31 can generate continuous pulse signals S567. The output line of signal S5 is electrically connected to sub-circuit Cd31, and can output continuous pulse signals S567. The timing diagram in Figure 9 roughly shows that the output lines of signals S5, S6, and S7 can output two different signal combinations. These two different signal combinations can be represented by two operating modes of signal generation circuit Cd30. The different operating modes of signal generation circuit Cd30 can correspond to the different light emission methods of the pixel circuit it controls (such as pixel circuit Cd10 mentioned above).

[0155] One operating mode of the signal generation circuit Cd30: When a low-level signal (Vs) is input to the input line of signal Sg11 and a high-level signal (Vb) is input to the input line of signal Sg12, thin-film transistors Ta and Tb are both turned on, while thin-film transistors Tc and Td are both turned off. The output line of signal S6 can output signals S567, and the output line of signal S7 can output a high-level signal VGH. In this case, referring to Figure 2 and the above description, in the pixel circuit Cd10, thin-film transistors T5 and T6-1 are both turned on, thin-film transistor T6-2 is turned off, LED L1 emits light, and LED L2 does not emit light. In a scenario where LED L1 emits light similar to scattered light and LED L2 emits light similar to collimated light, the display panel 150 can be in a shared display mode.

[0156] Another operating mode of the signal generation circuit Cd30: When a high-level signal (Vb mentioned above) is input to the input line of signal Sg11 and a low-level signal (Vs mentioned above) is input to the input line of signal Sg12, thin-film transistors Ta and Tb are both off, while thin-film transistors Tc and Td are both on. The output line of signal S6 can output a high-level signal VGH, and the output line of signal S7 can output signals S567. In this case, referring to Figure 2 and the above description, in the pixel circuit Cd10, thin-film transistors T5 and T6-2 are both on, thin-film transistor T6-1 is off, LED L1 does not emit light, and LED L2 emits light. In the scenario where LED L1 is used to emit light similar to scattered light and LED L2 is used to emit light similar to collimated light, the display panel 150 can be in a privacy display mode.

[0157] In order to make full use of LEDs L1 and L2 to realize different display modes of display panel 150 or improve the display effect of display panel, one feasible way is to control LEDs L1 and L2 to emit light simultaneously or alternately. Based on this purpose, this application provides a signal generation circuit Cd40.

[0158] As shown in Figure 10, the signal generation circuit Cd40 may include a sub-circuit Cd41, which can be used to generate the signal Sg567. One possible scenario is that the sub-circuit Cd41 can be an EM GOA circuit.

[0159] For example, the signal generation circuit Cd40 may include input lines for signal Sg21, signal Sg22, and signal Sg23. Signals Sg21, Sg22, and Sg23 generated by an external circuit can be input to the signal generation circuit Cd40 via these three lines, respectively. One possible scenario is that signals Sg21, Sg22, and Sg23 can be used to control the signal generation circuit Cd40 to output signals S5, S6, or S7.

[0160] For example, the signal generation circuit Cd40 may include output lines for signal S5, signal S6, and signal S7. The output lines for signal S5, signal S6, and signal S7 can be electrically connected to the input lines for signal S5, signal S6, and signal S7 in the aforementioned pixel circuit Cd10 or pixel circuit Cd11, respectively, so that signals S5, S6, and S7 generated by the signal generation circuit Cd30 can be input to the aforementioned pixel circuit Cd10 or pixel circuit Cd11.

[0161] One possibility is that the sub-circuit Cd41 can be electrically connected to the output line of signal S5.

[0162] For example, the signal generation circuit Cd40 may also include thin-film transistors Th, Tj, Tk, Ti, Tm, and Tn.

[0163] In this circuit, the gates of thin-film transistors Th and Ti can be electrically connected to the input line of signal Sg21; the gates of thin-film transistors Tj and Tk can be electrically connected to the input line of signal Sg22; and the gates of thin-film transistors Tm and Tn can be electrically connected to the input line of signal Sg23. In other words, signal Sg21 can be used to control the on / off state of the source and drain of thin-film transistor Th, and also to control the on / off state of the source and drain of thin-film transistor Ti. Signal Sg22 can be used to control the on / off state of the source and drain of thin-film transistor Tj, and also to control the on / off state of the source and drain of thin-film transistor Tk. Signal Sg23 can be used to control the on / off state of the source and drain of thin-film transistor Tm, and also to control the on / off state of the source and drain of thin-film transistor Tn.

[0164] One end of the thin-film transistor Th can be electrically connected to the sub-circuit Cd41, and the other end can be electrically connected to the output line of signal S6. In other words, when the thin-film transistor Th is turned on, the signal S567 generated by the sub-circuit Cd41 can be output by the output line of signal S6.

[0165] Thin-film transistor Ti can be connected in series with thin-film transistor Tn. The end of thin-film transistor Tn furthest from thin-film transistor Ti can be electrically connected to the constant-level input terminal Vin in the signal generation circuit Cd40. The end of thin-film transistor Ti furthest from thin-film transistor Tn can be electrically connected to the output line of signal S7. The constant-level input terminal Vin can input a high-level signal VGH. In other words, when both thin-film transistors Ti and Tn are turned on, the output line of signal S7 can output a high-level signal VGH.

[0166] Thin-film transistor Tj can be connected in series with thin-film transistor Tm. The end of thin-film transistor Tm furthest from thin-film transistor Tj can be electrically connected to the constant-level input terminal Vin in the signal generation circuit Cd40. The end of thin-film transistor Tj furthest from thin-film transistor Tm can be electrically connected to the output line of signal S6. The constant-level input terminal Vin can input a high-level signal VGH. In other words, when both thin-film transistors Tj and Tm are turned on, the output line of signal S6 can output a high-level signal VGH.

[0167] One end of the thin-film transistor Tk can be electrically connected to the sub-circuit Cd41, and the other end can be electrically connected to the output line of signal S7. In other words, when the thin-film transistor Tk is turned on, the signal S567 generated by the sub-circuit Cd41 can be output by the output line of signal S7.

[0168] Based on the above description, the output line of signal S5 of signal generation circuit Cd40 can output signal S567, the output line of signal S6 can output signal S567 or a high-level signal VGH, and the output line of signal S7 can output signal S567 or a high-level signal VGH. Signal Sg21 can be used to control the conduction of thin-film transistor Th so that signal S567 can be output from the output line of signal S6; signal Sg22 can be used to control the conduction of thin-film transistor Tk so that signal S567 can be output from the output line of signal S7; signal S22 can also be used to control the conduction of thin-film transistor Tj, and signal S23 can be used to control the conduction of thin-film transistor Tm so that the high-level signal VGH can be output from the output line of signal S6; signal S21 can also be used to control the conduction of thin-film transistor Ti, and signal S23 can also be used to control the conduction of thin-film transistor Tn so that the high-level signal VGH can be output from the output line of signal S7.

[0169] It should be noted that the high-level signal VGH in the signal generation circuit Cd40 can be used to control the p-type thin-film transistor T6-1 or thin-film transistor T6-2 in the pixel circuit Cd10 to turn off. For the pixel circuit Cd11, since thin-film transistors T6-1 and T6-2 are n-type thin-film transistors, in this case, in order to control the n-type thin-film transistor T6-1 or T6-2 to turn off, the constant-level input terminal Vin in the signal generation circuit Cd40 in Figure 10 can be input with a low-level signal VGL.

[0170] Here, we will provide a unified explanation of the multiple level signals in the signal generation circuit Cd40.

[0171] When the thin-film transistors Th, Ti, Tj, Tk, Tm, or Tn in the signal generation circuit Cd40 are all p-type thin-film transistors, let: the high-level value of the pulse signal generated by the sub-circuit Cd41 be Vu, the low-level value be Vd, the larger value of the input signals Sg21, Sg22, or Sg23 be Vb, the smaller value be Vs, and the high-level signal VGH input to the constant-level input terminal Vin be VGH.

[0172] The values ​​of the above-mentioned level signals can roughly satisfy the following relationship: VGH≥Vu, Vs <Vd,Vb≥VGH。

[0173] For example, Vs can be 1V, 2V, or 3V smaller than Vd, etc. For example, in order to reduce the power consumption of the drive circuit, VGH can be equal to Vu.

[0174] When the thin-film transistors Th, Ti, Tj, Tk, Tm, or Tn in the signal generation circuit Cd40 are all n-type thin-film transistors, let: the high-level value of the pulse signal generated by the sub-circuit Cd41 be Vu, the low-level value be Vd, the larger value of the input signals Sg21, Sg22, or Sg23 be Vb, the smaller value be Vs, and the low-level signal VGL input to the constant-level input terminal Vin be VGL. The values ​​of the above signal levels can roughly satisfy the following relationships: VGL ≤ Vd, Vb > Vu, Vs ≤ VGL.

[0175] For example, Vb can be 1V, 2V, or 3V greater than Vu, etc. For example, VGL can be equal to Vd.

[0176] The aforementioned thin-film transistors Th, Ti, Tj, Tk, Tm, and Tn can be either p-type or n-type thin-film transistors. The timing diagram of the signal generation circuit Cd40 is illustrated below using a p-type thin-film transistor as an example.

[0177] Figure 11 shows a timing diagram based on the signal generation circuit Cd40. The sub-circuit Cd41 generates continuous pulse signals S5 and S67. The output line of signal S5 is electrically connected to the sub-circuit Cd41, and can output continuous pulse signals S5 and S67. The timing diagram in Figure 11 roughly shows that the output lines of signal S5, signal S6, and signal S7 can output three different signal combinations. These three different signal combinations can be represented as three operating modes of the signal generation circuit Cd40. The different operating modes of the signal generation circuit Cd40 can correspond to the different light emission methods of the pixel circuit it controls (such as the pixel circuit Cd10 mentioned earlier).

[0178] One operating mode of the signal generation circuit Cd40: When a low-level signal (Vs) is input to the input line of signal Sg21, a high-level signal (Vb) is input to the input line of signal Sg22, and a low-level signal (Vs) is input to the input line of signal Sg23, thin-film transistors Th, Ti, Tm, and Tn are all in the conducting state, while thin-film transistors Tj and Tk are both in the off state. The output line of signal S6 can output signals S567, and the output line of signal S7 can output a high-level signal VGH. In this case, referring to Figure 2 and the above description, in the pixel circuit Cd10, thin-film transistors T5 and T6-1 are both conducting, thin-film transistor T6-2 is off, LED L1 emits light, and LED L2 does not emit light. In a scenario where LED L1 emits a flash-like light and LED L2 emits a collimated light, the display panel 150 can be in a shared display mode.

[0179] Another operating mode of the signal generation circuit Cd40: When a high-level signal (Vb mentioned above) is input to the input line of signal Sg21, a low-level signal (Vs mentioned above) is input to the input line of signal Sg22, and a low-level signal (Vs mentioned above) is input to the input line of signal Sg23, thin-film transistors Tj, Tk, Tm, and Tn are all in the on state, while thin-film transistors Th and Ti are both in the off state. The output line of signal S6 can output a high-level signal VGH, and the output line of signal S7 can output signals S567. In this case, referring to Figure 2 and the above description, in the pixel circuit Cd10, thin-film transistors T5 and T6-2 are both on, thin-film transistor T6-1 is off, LED L1 does not emit light, and LED L2 emits light. In the scenario where LED L1 is used to emit light similar to scattered light and LED L2 is used to emit light similar to collimated light, the display panel 150 can be in a privacy display mode.

[0180] Another operating mode of the signal generation circuit Cd40: When a low-level signal (Vs) is input to the input lines of signal Sg21, signal Sg22, and signal Sg23, and a high-level signal (Vb) is input, thin-film transistors Th, Ti, Tj, and Tk are all in the on state, while thin-film transistors Tm and Tn are both in the off state. The output lines of signals S6 and S7 can both output signals S5, S6, and S7. In this case, referring to Figure 2 and the above description, in the pixel circuit Cd10, thin-film transistors T5, T6-1, and T6-2 are all on, and LEDs L1 and L2 can emit light simultaneously. In a scenario where LED L1 emits light similar to scattered light and LED L2 emits light similar to collimated light, the display panel 150 can be roughly in a shared display mode.

[0181] For the same total luminous intensity, when two LEDs are emitting light simultaneously, the current input to each LED is smaller, the LED is less likely to be damaged due to the large current, and the LED has a longer lifespan.

[0182] Figure 12 shows another timing diagram based on the signal generation circuit Cd40. The sub-circuit Cd41 can generate continuous pulse signals S567. The output line of signal S5 is electrically connected to the sub-circuit Cd41 and can output the pulse signal S567. The timing diagram in Figure 12 roughly shows that the output lines of signal S5, signal S6, and signal S7 can output two different signal combinations. These two different signal combinations can be represented by two operating modes of the signal generation circuit Cd40. The different operating modes of the signal generation circuit Cd40 can correspond to the different light emission methods of the pixel circuit it controls (such as the pixel circuit Cd10 mentioned earlier).

[0183] When a low-level signal (Vs mentioned above) is continuously input to the input line of signal Sg21, thin-film transistors Th and Ti can remain in the on state, and the output line of signal S6 can continuously output signal S567.

[0184] One operating mode of the signal generation circuit Cd40: Based on the continuous output of signal S567 from the output line of signal S6, when a high-level signal (Vb mentioned above) is input to the input line of signal Sg22 and a low-level signal (Vs mentioned above) is input to the input line of signal Sg23, thin-film transistors Tm and Tn are both in the on state, while thin-film transistors Tj and Tk are both in the off state, and the output line of signal S7 can output a high-level signal VGH.

[0185] Under the above conditions, in conjunction with Figure 2 and the description above, in the pixel circuit Cd10, both thin-film transistors T5 and T6-1 are turned on, thin-film transistor T6-2 is turned off, LED L1 emits light, and LED L2 does not emit light.

[0186] Another operating mode of the signal generation circuit Cd40: Based on the continuous output of signal S567 from the output line of signal S6, when a low-level signal (Vs mentioned above) is input to the input line of signal Sg22 and a high-level signal (Vb mentioned above) is input to the input line of signal Sg23, thin-film transistors Tm and Tn are both in the off state, and thin-film transistors Tj and Tk are both in the on state, and the output line of signal S7 can output signal S567.

[0187] In the above scenario, referring to Figure 2 and the description above, in the pixel circuit Cd10, thin-film transistors T5, T6-1, and T6-2 are all turned on, and light-emitting diodes L1 and L2 emit light simultaneously. For the same total luminous intensity, when both light-emitting diodes emit light simultaneously, the current input to each light-emitting diode is smaller, the probability of damage to the light-emitting diodes due to large current is lower, and the lifespan of the light-emitting diodes is longer.

[0188] Let t1 be the duration of a single high-level signal input to the input line of signal Sg22 and a low-level signal input to the input line of signal Sg23, and t2 be the duration of a single low-level signal input to the input line of signal Sg22 and a high-level signal input to the input line of signal Sg23. By controlling the relative magnitudes of t1 and t2, the duration of a single light emission of LED L2 in pixel circuit Cd10 can be roughly controlled, achieving intermittent light emission of LED L2. Based on this, considering the display panel 150, the display panel 150 is roughly in a display state between privacy mode and sharing mode. In other words, in this case, the viewing angle of the display panel 150 is roughly between the viewing angle of privacy mode and the viewing angle of sharing mode. In other words, in this case, the viewing angle of the display panel 150 is adjustable.

[0189] Furthermore, since LED L1 emits light continuously while LED L2 emits light intermittently, from the user's perspective, the display effect (such as brightness) of the display panel 150 changes little when LED L2 is on or off. This method of controlling the light emission of the two LEDs helps to reduce the probability of the display panel 150 flickering when switching display modes, which helps to improve the user experience.

[0190] The signal generation circuits Cd30 and Cd40 described above can both be used to generate signals that drive a pixel circuit containing two light-emitting diodes. Based on the above description of the signal generation circuits Cd30 and Cd40, this application also provides a signal generation circuit Cd50, which can be used to generate signals that drive a pixel circuit containing M light-emitting diodes, where M is an integer greater than or equal to 3.

[0191] In some examples, the signal generation circuit Cd50 may include a sub-circuit Cd51 for generating pulse signals. The signal generation circuit Cd50 may also include (M+1) signal output lines, which may be used to output signals for controlling M light-emitting diodes. At least one of these (M+1) signal output lines is directly electrically connected to the sub-circuit Cd51.

[0192] In some examples, the signal generation circuit Cd50 may include 2×M thin-film transistors, which may be connected between the sub-circuit Cd51 and the signal output line, or these thin-film transistors may be connected between the high level in the signal generation circuit Cd50 and the signal output line.

[0193] In some examples, the signal generation circuit Cd50 may include M signal input lines that can be used to input control signals to the signal generation circuit Cd50, which can then be used to control multiple thin-film transistors within the signal generation circuit Cd50. As one possible implementation, these signal input lines may be electrically connected to the gates of the thin-film transistors in the signal generation circuit Cd50.

[0194] In some scenarios, the aforementioned signal generation circuits Cd30, Cd40, and Cd50 can also be referred to as signal selection circuits or light-emitting pulse output selectors.

[0195] As one possible implementation, the input lines of the aforementioned signal Sg11, signal Sg12, signal Sg21, signal Sg22, or signal Sg23, as well as the signal input lines in the signal generation circuit Cd50, can be electrically connected to the control module 200. In other words, the signals input to these aforementioned signal input lines can be generated by the control module 200.

[0196] Figure 13 is a schematic diagram of the structure of an electronic device 50 provided in an embodiment of this application. The electronic device 50 may include a display panel 150, a control module 200, and a processing module 300.

[0197] The display panel 150 can be used to display images, text and other information. The display panel 150 may include a pixel circuit array composed of multiple pixel circuit modules 10. Each pixel circuit in these pixel circuit modules may include multiple (e.g., two or three) light-emitting diodes.

[0198] The display panel 150 may also include one or more gate drive circuit modules 20, which can be used to control the switching of thin-film transistors in the pixel circuit module 10. By way of example and not limitation, the gate drive circuit module 20 may include one or more of the signal generation circuits 20, 30, 40 or 50 described above.

[0199] The display panel 150 may also include one or more source drive circuit modules 30. The source drive circuit module 30 can be used to receive data signals from the control module 200 and convert these data signals into voltage or current, and the converted voltage or current can be transmitted to the pixel circuit module 10.

[0200] The composition and structure of the display panel 150 are roughly as shown in Figure 1. For a detailed description of the display panel 150, please refer to the previous description, which will not be repeated here.

[0201] In some examples, the control module 200 may be electrically connected to the display panel 150 and used to send control signals to the display panel 150 to control the display mode of the display panel 150. For example, referring to FIG13, the control module 200 may be electrically connected to the display panel 150 via a circuit board Bc1 (e.g., a flexible circuit board), and data communication between the control module 200 and the display panel 150 may occur via the circuit board Bc1.

[0202] In some examples, control module 200 may include power submodule 210, control submodule 220 and storage submodule 230.

[0203] For example, the control submodule 220 can be used to receive data that needs to be displayed through the display panel 150, and decode and process the received image data to convert it into a format that can be applied to the display panel 150. Also for example, the control submodule 220 can also be used to generate control signals for controlling the gate drive circuit module 20 and the source drive circuit module 30 in the display panel 150, so that the display panel 150 can display the image to be displayed in the correct order and manner. Still for example, the control submodule 220 can also be used to adjust the display effect of the display panel 150; this part will be described in detail below and will not be elaborated here.

[0204] As one possible implementation, the control submodule 220 may include a timing controller integrated circuit (TCON IC), which can be used to implement one or more of the functions that the aforementioned control submodule 220 can perform.

[0205] For example, the power submodule 210 in the control module 200 can be electrically connected to the control submodule 220 and the storage submodule 230 respectively, and can be used to power one or more electronic components contained in the control submodule 220 and to power the storage submodule 230.

[0206] For example, the storage submodule 230 in the control module 200 may be electrically connected to the control submodule 220.

[0207] For example, the storage submodule 230 can be used to store programs or code related to the operation of the control submodule 220. The control submodule 220 can determine one or more of the following methods based on these programs or code: the method of processing image data, the method of controlling the refresh rate of the display panel 150, or the method of adjusting the display parameters of the display panel 150.

[0208] For example, the storage submodule 230 can be used to store data related to the display mode, brightness, color configuration or language selection of the display panel 150. The aforementioned control submodule 220 can determine the display mode, brightness, color configuration or language selection of the display panel 150 based on this data.

[0209] For example, the storage submodule 230 can be used to store timing parameters, which are used to indicate the start time, end time, etc. of writing data to different light-emitting diodes in the pixel circuit. The timing parameters can also be used to indicate the start time, end time, etc. of the control submodule 220 for data reading or data transmission.

[0210] In the case where the pixel circuit module 10 contains multiple light-emitting diodes, the light-emitting timing of the multiple light-emitting diodes may be different. In this case, the timing parameters stored in the storage submodule 230 can be multiple sets; or, the light-emitting timing of the multiple light-emitting diodes may be the same. In this case, the timing parameters stored in the storage submodule 230 can be one set.

[0211] One possibility is that the storage submodule 230 may include one or more storage chips; for example, the storage submodule 230 may include a flash memory chip.

[0212] In some examples, the processing module 300 can be used to send data or signals to the control module 200, which can then control the display mode of the display panel 150 based on the received data or signals.

[0213] In some examples, the processing module 300 may include a power submodule 310, a processing submodule 320, and a storage submodule 330.

[0214] By way of example and not limitation, the processing submodule 320 can be used to receive video signals and / or image signals from different sources, perform format conversions such as decoding, scaling, and color management, to generate signals suitable for the display panel 150. For example, the processing submodule 320 can be a system-on-chip (SOC), which may include one or more of various electronic components such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a memory controller, or an input / output interface.

[0215] For example, the power submodule 310 in the processing module 300 can be electrically connected to the processing submodule 320 and the storage submodule 330, and can be used to power one or more electronic components contained in the processing submodule 320 and to power the storage submodule 330.

[0216] For example, the storage submodule 330 in the processing module 300 may be electrically connected to the processing submodule 320. For instance, the storage submodule 330 may be used to store programs or code related to the operation of the processing submodule 320.

[0217] One possibility is that the storage submodule 330 may include one or more storage chips; for example, the storage submodule 230 may include a flash memory chip.

[0218] Figure 14 is a schematic diagram of a control submodule 220 and a processing submodule 320 provided in an embodiment of this application.

[0219] For example, the control submodule 220 may include an image processing module 221, which can be used to manage and control pixel refresh on the display panel 150 and signal conversion with external data sources. For example, the image processing module 221 can be used to perform one or more of the following image processing functions: signal conversion, image scaling, color management, or motion compensation, etc.

[0220] For example, the control submodule 220 may also include random access memory (RAM) 229, which can temporarily store data and programs. For instance, in an image or video display scenario, RAM 229 can be used to temporarily store data read from storage submodule 230, and image processing module 221 can read image data to be processed from RAM 229.

[0221] For example, the control submodule 220 may further include a receiving module 223 and a transmitting module 225. The receiving module 223 can be used to receive data sent by other functional modules besides the control submodule 220. For example, in an image or video display scenario, the receiving module 223 can be used to receive image data sent from the processing submodule 320. The transmitting module 225 can be used to transmit the processed image signal to the display panel 150, thereby controlling the display of the display panel 150.

[0222] For example, the control submodule 220 may further include a timing control module 227, which can be used to manage the timing of pixel refresh and data transmission on the display panel 150. For example, the timing control module 227 can be used to perform one or more of the following operations: generating vertical synchronization signals and horizontal synchronization signals, controlling the pixel clock, managing the refresh rate of the display panel, or initializing and configuring the display panel, etc.

[0223] For example, the processing submodule 320 may include an image processing module 321, which can perform noise reduction, sharpening, contrast stretching, color matching and other processing on image data from different sources.

[0224] For example, the processing submodule 320 may also include a random access memory 329, which can temporarily store data and programs. For instance, in an image or video display scenario, the random access memory 329 can be used to temporarily store data read from the storage submodule 330, and the image processing module 321 can read the image data to be processed from the random access memory 329.

[0225] For example, the processing submodule 320 may also include a sending module 323, which can send the data processed by the processing submodule 320 to a functional module outside the processing submodule 320. For example, in an image or video display scenario, the sending module 323 can receive data from the image processing module 321 and send the data to the control submodule 220 for further processing by the control submodule 220 for display on the display panel 150.

[0226] For example, the sending module 323 can send data to the control submodule 220 in accordance with the data format specified by the embedded display port (eDP) protocol or the mobile industry processor interface (MIPI) protocol.

[0227] For example, the processing submodule 320 may further include one or more of the following modules: application processing module 322, sound processing module 324, signal processing module 326, or image rendering module 328. The application processing module 322 can be used to process the operating system or application code of the electronic device 50 to implement application layer services including but not limited to interface processing, network protocol stack, and multimedia processing. The sound processing module 324 can be used to process the audio signals of the electronic device 50; for example, it can convert analog audio signals captured by a microphone into digital signals, or convert digital audio signals into analog signals for playback by speakers, etc. The signal processing module 326 can be used to perform signal processing such as signal acquisition, signal filtering, signal enhancement, or signal compression and decompression. The image rendering module 328 can be used to process and render image and video data for display on the display panel 150 or for further processing. For example, the image rendering module 328 can perform pixel rendering, vertex processing, texture mapping, blending, and compositing operations.

[0228] The processing submodule 320 may also include other functional modules such as a receiving module, and this application does not limit this.

[0229] Since the display panel 150 contains a large number of pixel circuit modules 10, the properties and performance of the light-emitting diodes in each pixel circuit module 10 may differ. In order to ensure that the display brightness, color, and other effects of the pixel circuits at different locations on the display panel 150 are relatively consistent, the control module 200 can adjust the magnitude and duration of the current flowing through different pixel circuit modules 10 to adjust the display effect of different pixel circuit modules 10. In some scenarios, the function used to adjust the display effect of different pixel circuit modules 10 can be called a compensation function, and the data corresponding to different compensation functions can be called compensation parameters.

[0230] In some examples, the compensation functions can be roughly divided into the following categories based on the different reasons for compensation: compensation functions for display effect differences caused by temperature differences of light-emitting diodes, compensation functions for display effect differences caused by differences in the aging degree of light-emitting diodes, compensation functions for display effect differences caused by different ambient light, or compensation functions for differences in human eye perception of different colors and brightness.

[0231] For example, compensation functions may include one or more of the following:

[0232] Noise reduction (NR), sharpening, dynamic contrast improvement (DCI), color gamut mapping (CGM), automatic color management (ACM), gamma correction, de-burn-in (DBI), overdrive (OD), dithering, built-in self-test (BIST), data swap, crosstalk compensation (CTC), round nose compensation (RNC), voltage drop compensation (IRC or VDC), DEMURA elimination, or brightness control management gamma (BCMG), etc.

[0233] Noise reduction refers to the process of reducing the adverse effects of noise generated by signal sources, transmission processes, and electronic components within the display panel on the display effect, thereby improving the clarity and visual appeal of the display panel.

[0234] Sharpening refers to the processing operation that enhances the clarity and detail of the edges of the image displayed on the display panel, making the image or video displayed on the display panel more vivid and focused.

[0235] Dynamic contrast enhancement refers to the processing operation that improves the contrast of images or videos displayed on a display panel by analyzing the displayed content in real time and dynamically adjusting the brightness of local areas.

[0236] Color gamut mapping refers to the process of converting colors from one color space to another to ensure that colors on different display panels match as closely as possible.

[0237] Automatic color management refers to the process of automatically adjusting the color output of the display panel to match the color standard of the displayed content's intent or characteristics.

[0238] Gamma correction refers to the process of adjusting the image signal applied to the display panel to match the brightness response of the display panel with the way the human eye perceives brightness.

[0239] Burn-in protection refers to a process used to prevent permanent pixel damage caused by displaying static images on a display panel for an extended period of time.

[0240] Overvoltage driving refers to the processing operation used to shorten the time required for pixels in a display panel to transition from one gray level to another, thereby improving the response time of the display panel.

[0241] Dithering refers to image processing operations used to simulate color depths beyond the actual hardware capabilities of a display panel.

[0242] Built-in self-test refers to the automatic execution of predefined tests during the startup or operation of the display panel.

[0243] Data exchange refers to the processing operations that rearrange pixel data within the display controller or display driver, change the local transmission order or format of pixel data, and improve display panel characteristics, interface standards, or optimize display effects.

[0244] Crosstalk compensation refers to the processing operation used to reduce or eliminate crosstalk phenomena that occur when displaying dynamic images on a display panel.

[0245] Rounded corner compensation refers to a processing operation applied to display panels with non-right-angle edges to improve the quality of the displayed image.

[0246] Voltage drop compensation refers to the processing operation used to compensate for voltage drops caused by long-distance signal transmission, ensuring uniform voltage across different display areas of the display panel and maintaining consistent image quality.

[0247] MURA elimination refers to a process used to reduce unevenness in brightness or color on a display panel.

[0248] Brightness control management refers to the processing operations used to adjust and manage the brightness of the display panel, optimize the visual experience, and improve the display panel's adaptability to different ambient lighting conditions.

[0249] In addition to the various compensation functions listed above, there are many other compensation functions that can be applied to the display panel to improve its display effect. For the sake of brevity, they will not be elaborated here. It should be noted that this application does not limit these functions.

[0250] When the pixel circuit in the display panel 150 includes multiple light-emitting diodes, for the same compensation function, different compensation parameters can be applied to compensate for the display effect of different light-emitting diodes.

[0251] One possibility is that, for the same compensation function, the compensation parameters of multiple light-emitting diodes may be different. In the case where the light-emitting diodes operating in the pixel circuit of the display panel 150 are switched from one to another, or in other words, when the display panel 150 is switched from one display mode (e.g., shared display mode) to another display mode (e.g., privacy display mode), the compensation parameters applied to different light-emitting diodes need to be switched from one set to another.

[0252] Due to the limited capacity of the random access memory 229 within the control submodule 220, compensation parameters applied to multiple sets of LEDs often cannot all be stored in the random access memory 229. To enable switching between different display modes of the display panel 150, a feasible approach is to store the compensation parameters applied to multiple sets of LEDs in the storage submodule 230, which has a larger storage space but a slower read speed. In the scenario of display mode switching, the control submodule 220 can clear the compensation parameters applied to the currently operating LED stored in the random access memory 229. Afterward, the compensation parameters applied to the LEDs about to operate are read from the storage submodule 230 into the random access memory 229.

[0253] In the above scheme, since the random access memory 229 needs to be reset during the display mode switching process, and the read and write speed of the storage submodule 230 is generally slower than that of the random access memory 229, the time interval between the two display modes is relatively long.

[0254] To shorten the switching time between different display modes, this application provides a driving method in which part of the compensation function originally executed by the control submodule 220 can be executed by the processing submodule 320. The program code and data related to this part of the compensation function can be stored in the processing submodule 320, freeing up more high-speed storage space in the control submodule 220. In this way, multiple sets of compensation parameters and multiple sets of timing control parameters applied to different light-emitting diodes can be stored in the random access memory 229. In the scenario of display mode switching, the reading speed of compensation parameters and timing control parameters is faster, and the efficiency of display mode switching is higher.

[0255] In some scenarios, timing control parameters can also be referred to as timing parameters.

[0256] In some examples, among the various compensation functions described above, the compensation function corresponding to the compensation parameter that occupies a larger storage space can be executed by the processing submodule 320. Alternatively, among the two sets of compensation parameters, the compensation parameter that occupies a larger storage space can be stored in the storage submodule 330 associated with the processing submodule 320. Furthermore, among the two sets of compensation parameters, one or more of the other types of compensation parameters can be stored in the storage submodule 230 associated with the control submodule 220.

[0257] For example, the processing submodule 320 may perform one or more of the following compensation functions: overvoltage drive, screen burn-in prevention, or MURA elimination, etc.

[0258] Here, some of the compensation functions are implemented by the processing submodule 320. It can be understood that the code (such as the algorithm) and data used to implement the compensation function are stored in the storage submodule 330 associated with the processing submodule 320, and this code can be executed by the processing submodule 320.

[0259] In some examples, among the various compensation functions described above, the compensation function most closely related to the timing control submodule 220 can be executed by the timing control submodule 220. Alternatively, among the two sets of compensation parameters, the compensation parameters of the compensation function most closely related to the timing control submodule 220 can be stored in the storage submodule 230 associated with the timing control submodule 220. Furthermore, one or more of the other types of compensation parameters from the two sets of compensation parameters can be stored in the storage submodule 330 associated with the processing submodule 320.

[0260] For example, the timing control submodule 220 may perform one or more of the following compensation functions: built-in self-test, data exchange, jitter or brightness control management, etc.

[0261] In some examples, the code and parameters related to the compensation function executed by the processing submodule 320 and the code and parameters related to the compensation function executed by the control submodule 220 can be stored in different locations on the same memory chip (e.g., the memory chip included in the storage submodule 230). In this case, the compensation function-related code and parameters of the two parts can be read sequentially from a memory chip, and when needed, this data can be sequentially read from the aforementioned memory chip into the random access memory.

[0262] To improve the speed at which the processing submodule 320 and the control submodule 220 read data from the memory chips, in some examples, the code and parameters related to the compensation function executed by the processing submodule 320 and the code and parameters related to the compensation function executed by the control submodule 220 can be stored on different memory chips. In this case, the compensation function-related code and parameters of the two parts can be read from the two memory chips respectively, and when needed, this data can be read from the two memory chips respectively into the random access memory.

[0263] Figure 15 roughly illustrates the process from powering on the electronic device 50 to performing the display mode switching operation.

[0264] S101, Electronic device 50 is powered on.

[0265] In some examples, when the device is powered off, the electronic device 50 can be powered on in response to the user pressing the power button on the electronic device 50.

[0266] For example, during the power-on process, the electronic device 50 can perform operations such as calling the power-on program, loading the operating system kernel, and initializing hardware and drivers.

[0267] S102, write the first part of the two sets of compensation parameters into random access memory 329, and write the second part of the two sets of compensation parameters into random access memory 229.

[0268] By way of example and not limitation, each pixel circuit of the display panel 150 of the electronic device 50 may include two light-emitting diodes. In this case, there may be two sets of compensation parameters for compensating the display effect of the display panel 150, for example, referred to as the first set of compensation parameters and the second set of compensation parameters.

[0269] For ease of explanation, the first set of compensation parameters can be considered to consist of two parts, A1 and B1, and the second set of compensation parameters can be considered to consist of two parts, A2 and B2. Specifically, part A1 of the first set of compensation parameters and part A2 of the second set of compensation parameters are used to implement the first group of compensation functions, and part B1 of the first set of compensation parameters and part B2 of the second set of compensation parameters are used to implement the second group of compensation functions. Alternatively, part A1 of the first set of compensation parameters and part A2 of the second set of compensation parameters both correspond to the first group of compensation functions, and part B1 of the first set of compensation parameters and part B2 of the second set of compensation parameters both correspond to the second group of compensation functions.

[0270] One possibility is that the first set of compensation parameters can be used to adjust the display effect of the display panel 150 in the first display mode, for example, the first display mode can be the aforementioned shared display mode, in which the light-emitting diode L1 is working; the second set of compensation parameters can be used to adjust the display effect of the display panel 150 in the second display mode, for example, the second display mode can be the aforementioned privacy display mode, in which the light-emitting diode L2 is working.

[0271] In some examples, the first set of compensation parameters and the second set of compensation parameters are both programmed onto the same memory chip in the electronic device 50, such as the memory chip contained in the memory submodule 230.

[0272] In some examples, the A1 portion of the first set of compensation parameters and the A2 portion of the second set of compensation parameters are both programmed onto a memory chip in the electronic device 50, which can be associated with the processing submodule 320. For example, the A1 portion of the first set of compensation parameters and the A2 portion of the second set of compensation parameters are both programmed onto the same memory chip included in the storage submodule 330. In other words, the compensation parameters corresponding to the first set of compensation functions are all programmed onto the same memory chip.

[0273] In some examples, both the B1 portion of the first set of compensation parameters and the B2 portion of the second set of compensation parameters are programmed onto a memory chip in the electronic device 50, which can be associated with the control submodule 220. Exemplarily, both the B1 portion of the first set of compensation parameters and the B2 portion of the second set of compensation parameters are programmed onto the same memory chip included in the storage submodule 230. In other words, the compensation parameters corresponding to the second set of compensation functions are all programmed onto the same memory chip.

[0274] For example, the two sets of timing parameters corresponding to the two sets of compensation parameters can be programmed into the memory chip included in the memory submodule 230 associated with the control submodule 220. Alternatively, the two sets of timing parameters corresponding to the two display modes of the display panel 150 can be programmed into the memory chip included in the memory submodule 230.

[0275] In some examples, the aforementioned compensation parameters corresponding to the compensation functions of the display panel 150 can be stored on the memory chip of the electronic device 50 as part of the driver of the display panel 150. During the hardware and driver initialization phase, the electronic device 50 can write the compensation parameters from the memory chip into the RAM of the electronic device by reading the target instruction and executing the operation indicated by the target instruction.

[0276] For example, the above target instruction can be used to instruct: to read the A1 portion of the first set of compensation parameters and the A2 portion of the second set of compensation parameters from the storage submodule 330 into the random access memory 329 corresponding to the processing submodule 320; and to read the B1 portion of the first set of compensation parameters and the B2 portion of the second set of compensation parameters from the storage submodule 230 into the random access memory 229 corresponding to the control submodule 220.

[0277] S103, the processing submodule 320 configures the registers of the processing submodule 320 using part A1 of the first set of compensation parameters in the random access memory 329, and the control submodule 220 configures the registers of the control submodule 200 using part B1 of the first set of compensation parameters in the random access memory 229, driving the display panel 150 to display the first display mode.

[0278] One possibility is that the first display mode can be the default display mode of the display panel 150. In this case, during the power-on process of the electronic device 50, the electronic device 50 can use the first set of compensation parameters to adjust the display effect of the display panel 150 in the first display mode.

[0279] By configuring the value of part A1 of the first set of compensation parameters into the register of the processing submodule 320, and through the operation and processing of the register, the electronic device 50 can realize the first set of compensation functions for adjusting the display effect of the display panel 150 in the first display mode; by configuring the value of part B1 of the first set of compensation parameters into the register of the control submodule 220, and through the operation and processing of the register, the electronic device 50 can realize the second set of compensation functions for adjusting the display effect of the display panel 150 in the first display mode.

[0280] S104, Display mode switching.

[0281] One possibility is that the electronic device 50 can perform a display mode switch in response to a user clicking a button that triggers a display mode switching operation. For example, switching from the current first display mode to a second display mode, or switching from a privacy display mode to a shared display mode.

[0282] In some examples, when a display mode switching is required, the processing submodule 320 can send a control command to the control submodule 220. After receiving the control command, the control submodule 220 can generate a switching clock signal and send the switching clock signal to the gate driver circuit module 20. After receiving the switching clock signal, the gate driver circuit module 20 can generate a new pulse signal, which can control the display panel 150 to display according to the new display mode.

[0283] S105, the processing submodule 320 configures the registers of the processing submodule 320 using part A2 of the second set of compensation parameters in the random access memory 329, and the control submodule 220 configures the registers of the control submodule 200 using part B2 of the second set of compensation parameters in the random access memory 229, driving the display panel 150 to display the second display mode.

[0284] By configuring the value of part A2 of the second set of compensation parameters into the register of the processing submodule 320, and through the operation and processing of the register, the electronic device 50 can realize the first set of compensation functions for adjusting the display effect of the display panel 150 in the second display mode; by configuring the value of part B1 of the second set of compensation parameters into the register of the control submodule 220, and through the operation and processing of the register, the electronic device 50 can realize the second set of compensation functions for adjusting the display effect of the display panel 150 in the second display mode.

[0285] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A drive circuit characterized by comprising: The drive circuit comprises: a pulse signal generation circuit, a constant level input terminal, a first control signal input circuit, a second control signal input circuit, a first signal output circuit, a second signal output circuit, a third signal output circuit, a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor, the first signal output circuit is electrically connected with the pulse signal generation circuit; the second signal output circuit is electrically connected with the pulse signal generation circuit through the first thin film transistor, and is also electrically connected with the constant level input terminal through the fourth thin film transistor; the third signal output circuit is electrically connected with the pulse signal generation circuit through the second thin film transistor, and is also electrically connected with the constant level input terminal through the third thin film transistor; the first control signal input circuit is electrically connected with the first thin film transistor to control the pulse signal generation circuit and the first signal output circuit to be turned on or turned off, and is also electrically connected with the second thin film transistor to control the constant level input terminal and the second signal output circuit to be turned on or turned off; the second control signal input circuit is electrically connected with the third thin film transistor to control the pulse signal generation circuit and the second signal output circuit to be turned on or turned off, and is also electrically connected with the fourth thin film transistor to control the constant level input terminal and the first signal output circuit to be turned on or turned off.

2. The drive circuit according to claim 1, characterized in that, two ends of the first thin film transistor are respectively electrically connected with the second signal output circuit and the pulse signal generation circuit; two ends of the second thin film transistor are respectively electrically connected with the third signal output circuit and the constant level input terminal; a gate of the first thin film transistor and a gate of the second thin film transistor are both electrically connected with the first control signal input circuit.

3. The drive circuit according to claim 2, characterized in that, two ends of the third thin film transistor are respectively electrically connected with the second signal output circuit and the constant level input terminal; two ends of the fourth thin film transistor are respectively electrically connected with the third signal output circuit and the pulse signal generation circuit; a gate of the third thin film transistor and a gate of the fourth thin film transistor are both electrically connected with the second control signal input circuit.

4. The drive circuit according to claim 3, characterized in that, the drive circuit further comprises a third control signal input circuit, a fifth thin film transistor and a sixth thin film transistor, two ends of the fifth thin film transistor are respectively electrically connected with the third thin film transistor and the constant level input terminal; two ends of the sixth thin film transistor are respectively electrically connected with the second thin film transistor and the constant level input terminal; the third control signal input circuit is respectively electrically connected with a gate of the fifth thin film transistor and a gate of the sixth thin film transistor to control the fifth thin film transistor to be turned on or turned off and the sixth thin film transistor to be turned on or turned off.

5. The drive circuit according to any one of claims 1 to 4, characterized by in the case that the first control signal input circuit inputs a first level signal, the second control signal input circuit inputs a second level signal; Or, in the case that the first control signal input line inputs a second level signal, the second control signal input line inputs a first level signal; The first level signal is used to control the first thin film transistor and the second thin film transistor to be turned on, or is used to control the third thin film transistor and the fourth thin film transistor to be turned on, The second level signal is used to control the third thin film transistor and the fourth thin film transistor to be turned off, or is used to control the first thin film transistor and the second thin film transistor to be turned off.

6. The driving circuit according to claim 5, wherein, In the case that the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are all p-type thin film transistors, the level value input by the constant level input terminal is greater than or equal to the maximum level value output by the pulse signal generation circuit; The first level signal is less than the minimum level value output by the pulse signal generation circuit, and the difference between the minimum level value output by the pulse signal generation circuit and the first level signal is greater than or equal to 1V; The second level signal is greater than or equal to the level value input by the constant level input terminal.

7. The drive circuit according to claim 3, characterized by The driving circuit has a first mode and a second mode, In the first mode, the first thin film transistor and the second thin film transistor are turned on, and the third thin film transistor and the fourth thin film transistor are turned off; In the second mode, the first thin film transistor and the second thin film transistor are turned off, and the third thin film transistor and the fourth thin film transistor are turned on.

8. The drive circuit of claim 4, wherein, The driving circuit has a first mode, a second mode and a third mode, In the first mode, the first thin film transistor and the second thin film transistor are turned on, the third thin film transistor and the fourth thin film transistor are turned off, and the fifth thin film transistor and the sixth thin film transistor are turned on; In the second mode, the first thin film transistor and the second thin film transistor are turned off, the third thin film transistor and the fourth thin film transistor are turned on, and the fifth thin film transistor and the sixth thin film transistor are turned on; In the third mode, the first thin film transistor and the second thin film transistor are turned on, the third thin film transistor and the fourth thin film transistor are turned on, and the fifth thin film transistor and the sixth thin film transistor are turned off.

9. The drive circuit according to claim 4, characterized by The driving circuit has a first mode and a second mode, In the first mode, the first thin film transistor and the second thin film transistor are turned on, the third thin film transistor and the fourth thin film transistor are turned off, and the fifth thin film transistor and the sixth thin film transistor are turned on; In the second mode, the first thin film transistor and the second thin film transistor are turned on, the third thin film transistor and the fourth thin film transistor are turned on, and the fifth thin film transistor and the sixth thin film transistor are turned off.

10. A display device, characterized by comprising: Comprise: The pixel circuit and the driving circuit according to any one of claims 1 to 9 are electrically connected, and the pixel circuit comprises a first light-emitting diode and a second light-emitting diode.

11. The display device according to claim 10, wherein The pixel circuit comprises a seventh thin film transistor and an eighth thin film transistor, the seventh thin film transistor is electrically connected with the first light-emitting diode, and the eighth thin film transistor is electrically connected with the second light-emitting diode, The second signal output line is electrically connected to the gate of the seventh thin film transistor to control the seventh thin film transistor to be turned on or turned off, The third signal output line is electrically connected to the gate of the eighth thin film transistor to control the eighth thin film transistor to be turned on or turned off.

12. The display device according to claim 10 or 11, characterized by The driving circuit is located at the periphery of the pixel circuit.

13. The display device according to any one of claims 10 to 12, wherein The first light-emitting diode is used for emitting diffuse light, and the second light-emitting diode is used for emitting collimated light.

14. The display device according to any one of claims 10 to 13, wherein The display device further comprises a timing control module, which is electrically connected with the driving circuit.

15. An electronic device, comprising: Comprise: a display panel, a timing control module, a system on chip, a first storage chip and a second storage chip, Each pixel circuit in the display panel comprises a first light-emitting diode and a second light-emitting diode, in a first display mode of the display panel, the first light-emitting diode emits light, in a second display mode of the display panel, the second light-emitting diode emits light, The first storage chip is electrically connected with the system on chip, and the second storage chip is electrically connected with the timing control module, the first storage chip is programmed with a first compensation parameter and a second compensation parameter, and the second storage chip is programmed with a third compensation parameter and a fourth compensation parameter, The first compensation parameter and the third compensation parameter are used to adjust the display effect of the display panel in the first display mode, and the second compensation parameter and the fourth compensation parameter are used to adjust the display effect of the display panel in the second display mode.

16. The electronic device of claim 15, wherein, The first compensation parameter and the second compensation parameter comprise one or more of the following: overvoltage driving compensation parameters, anti-burn screen compensation parameters or MURA elimination compensation parameters.

17. The electronic device of claim 15 or 16, wherein, The third compensation parameter and the fourth compensation parameter comprise one or more of the following: built-in self-test compensation parameters, data exchange compensation parameters, jitter compensation parameters or brightness control management compensation parameters.

18. The electronic device of any of claims 15-17, wherein, The first light-emitting diode is used for emitting diffuse light, and the second light-emitting diode is used for emitting collimated light.

19. A driving method, comprising: The method is applied to the electronic device according to any one of claims 15 to 18, and the method comprises: In response to the electronic device being powered on, the system on chip reads the first compensation parameter and the second compensation parameter from the first storage chip, and the timing control module reads the third compensation parameter and the fourth compensation parameter from the second storage chip; The system on chip writes the first compensation parameter and the second compensation parameter into the random access memory of the system on chip, and the timing control module writes the third compensation parameter and the fourth compensation parameter into the random access memory of the timing control module; The system chip configures a register of the system chip through the first compensation parameter, and the timing control module configures a register of the timing control module through the third compensation parameter; The electronic device displays a first display mode.

20. The driving method according to claim 19, wherein The method further includes: In response to the operation of switching the display mode, the system chip configures a register of the system chip through the second compensation parameter, and the timing control module configures a register of the timing control module through the fourth compensation parameter; The electronic device displays a second display mode.

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