Low-cost and high-performance radio-frequency amplifier

Abstract

The present application discloses a low-cost and high-performance radio-frequency amplifier, comprising an input stage circuit, a common-gate stage circuit, and an output load circuit. The input stage circuit implements conversion from a single-ended signal to a differential signal, implements input impedance matching, and converts an inputted radio-frequency voltage signal into a radio-frequency current signal. The input stage circuit comprises a first three-coil transformer, consisting of a primary coil, a secondary coil, and a third coil. The common-gate stage circuit transmits the radio-frequency current signal outputted by the input stage circuit to the output load circuit, increases the withstand voltage and equivalent output impedance of the circuit, and implements gain control in at least two modes. The output load circuit converts the radio-frequency current signal from the common-gate stage circuit into a radio-frequency voltage signal, implements conversion from a differential signal to a single-ended signal, and outputs an amplified radio-frequency voltage signal. The present application provides a radio-frequency amplifier having a small size, broadband matching, high linearity, a large dynamic range, and low design complexity.

Description

Low cost high performance radio frequency amplifier TECHNICAL FIELD

[0001] The present application relates to a wireless communication technology, and in particular, to a radio frequency amplifier. BACKGROUND

[0002] Referring to Fig. 1, it is a prior art radio frequency amplifier with single-ended to differential and input matching functions. The radio frequency amplifier contains input stage circuit and output load circuit from bottom to top. The input stage circuit contains transformer one Tr1, gate inductors Lg1 and Lg2, source degeneration inductor Ls, extra capacitors C1 and C2, differential NMOS pair M1 and M2, gate bias resistors R1 and R2. The output load stage circuit contains programmable array capacitor C3, transformer two Tr2 and load resistor R L The whole radio frequency amplifier presents left-right symmetrical structure, and the symmetrical devices have the same parameters. Transformer one Tr1 is used to convert single-ended signal (input voltage vin) to differential signal. The combination of all capacitors and inductors in the input stage circuit matches the input impedance to the value required by design (50 ohms in general case), and converts the voltage input signal to current signal through differential NMOS pair M1 and M2. Transformer two Tr2 is used to convert differential signal to single-ended signal (output voltage vout). The gain of the whole radio frequency amplifier is greater than 1, so the input signal is output after amplification.

[0003] The prior art radio frequency amplifier shown in Fig. 1 has the following defects.

[0004] Firstly, the input stage circuit uses source degeneration (also known as source degeneration and source degeneration) common source structure for impedance matching, and inductors Lg1 and Lg2 are added to the gates of NMOS pair M1 and M2, plus source degeneration inductor Ls, a total of 3 inductors, which leads to too large layout area, and is not easy for layout and wiring, and the design cost is high.

[0005] Second, the input stage circuit is based on the input matching of the capacitor and inductance resonance. Wherein, Zin is the input impedance, s is the complex frequency, Ls is the inductance value of the source degeneration inductance, Lg is the inductance value of the gate inductance Lg1 of the NMOS tube M1 (or the inductance value of the gate inductance Lg2 of the NMOS tube M2, both are the same), C1 is the capacitance value of the capacitor across the gate and source of the NMOS tube M1 (or the capacitance value of the capacitor C2 across the gate and source of the NMOS tube M2, both are the same), and gm is the transconductance of the common-source NMOS pair tube M1 or M2 (both are the same). When Ls+Lg and C1 resonate, the input impedance Zin only exists in the real part, which is the required value of the design (generally designed as 50 ohms). It can be found from the above analysis that this input matching can only be narrowband, that is, the bandwidth is limited, and can only be used in narrowband communication systems.

[0006] As can be seen from FIG. 1, the inductor, a large-area device, is usually used in the radio frequency amplifier in the radio frequency transceiver, which easily increases the manufacturing cost. At the same time, the design difficulty of the radio frequency amplifier is good input matching and linearity, and a certain dynamic range, so designing a small-size and high-performance radio frequency amplifier circuit will simplify the design of the radio frequency circuit and reduce the manufacturing cost. TECHNICAL PROBLEM

[0007] The technical problem to be solved by the present application is how to make the radio frequency amplifier have the characteristics of small size, wideband input matching, high linearity, and a certain dynamic range at the same time. TECHNICAL SOLUTION

[0008] To solve the above technical problems, the application provides a low-cost high-performance radio frequency amplifier, which comprises an input stage circuit, a common gate stage circuit and an output load circuit.The input stage circuit realizes conversion of single-ended signal into differential signal, realizes input impedance matching, and converts input radio frequency voltage signal into radio frequency current signal; the input stage circuit comprises a three-coil transformer I and a common source stage transistor, the three-coil transformer I is composed of a primary coil, a secondary coil and a third coil; the secondary coil is connected in parallel with a programmable capacitor array; the coupling inductance between the primary coil and the secondary coil is equivalent to the gate inductance of the common source stage transistor; the third coil is equivalent to the first part of the source degeneration inductance of the common source stage transistor, and the coupling inductance between the primary coil and the third coil is equivalent to the second part of the source degeneration inductance of the common source stage transistor, and the sum of the two parts is equivalent to the source degeneration inductance of the common source stage transistor.In the three-coil transformer I, the primary coil is two large annular coils, the secondary coil is also two large annular coils, and the secondary coil is stacked above the primary coil; the third coil is two small annular coils, which are surrounded by the large annular coils of the primary coil and the secondary coil; the center tap of the secondary coil is connected with the center tap of the third coil in a corresponding and connecting manner and grounded.The common gate stage circuit transmits the radio frequency current signal output by the input stage circuit to the output load circuit, improves the voltage resistance and equivalent output impedance of the circuit, and realizes gain control in at least two modes.The output load circuit converts the radio frequency current signal from the common gate stage circuit into a radio frequency voltage signal, realizes conversion of differential signal into single-ended signal, and outputs the amplified radio frequency voltage signal.

[0009] Further, the whole radio frequency amplifier has a left-right symmetrical structure, and the symmetrical devices have the same parameters.

[0010] Further, the input stage circuit further comprises a programmable capacitor array C1, two DC blocking capacitors C2 and C3, a differential NMOS pair M1 and M2, and two bias resistors R1 and R2; the differential NMOS pair M1 and M2 serve as the common source stage transistor.In the three-coil transformer I, one end of the primary coil is connected with an input voltage, and the other end is grounded; the secondary coil is connected in parallel with the programmable capacitor array C1, and the two ends of the secondary coil are further connected with the gates of the differential NMOS pair M1 and M2 through the two DC blocking capacitors C2 and C3; the primary coil and the secondary coil realize conversion of single-ended signal into differential signal; the two ends of the third coil are connected with the sources of the differential NMOS pair M1 and M2.The gates of the differential NMOS pair M1 and M2 are further connected with a gate bias voltage I through the two bias resistors R1 and R2; the drains of the differential NMOS pair M1 and M2 output differential current signals to the common gate stage circuit; the differential NMOS pair M1 and M2 realize conversion of voltage signal into current signal.The input stage circuit realizes input impedance matching based on the resonance of all capacitors and equivalent inductors.

[0011] Further, the common-gate stage circuit comprises NMOS tubes M3 to M8, gate-end decoupling capacitors Cg1 and Cg2, bias resistors R3 and R4. The drain of NMOS tube M1 is connected to the source of NMOS tube M3, the source of NMOS tube M4, and the source of NMOS tube M5; the drain of NMOS tube M2 is connected to the source of NMOS tube M6, the source of NMOS tube M7, and the source of NMOS tube M8; the gate of NMOS tube M3 and the gate of NMOS tube M8 are connected to gate bias voltage 2 through bias resistors R3 and R4, respectively; the gate of NMOS tube M3 and the gate of NMOS tube M8 are also connected to ground through gate-end decoupling capacitors Cg1 and Cg2, respectively; the drain of NMOS tube M3 and the drain of NMOS tube M4 are connected to an output load circuit; the drain of NMOS tube M8 and the drain of NMOS tube M7 are connected to an output load circuit; the gate of NMOS tube M4 and the gate of NMOS tube M7 are connected to a gain control signal; the gain control signal is connected to an inverter to output an inverted gain control signal; the gate of NMOS tube M5 and the gate of NMOS tube M6 are connected to the inverted gain control signal; the drain of NMOS tube M5 and the drain of NMOS tube M6 are connected to a power supply voltage.

[0012] Further, when the gain control signal is at a high level and the inverted gain control signal is at a low level, NMOS tubes M3, M4, M7, and M8 are turned on, and NMOS tubes M5 and M6 are turned off, so that the common-gate stage circuit works in a high-gain mode. When the gain control signal is at a low level and the inverted gain control signal is at a high level, NMOS tubes M4 and M7 are turned off, and NMOS tubes M3, M5, M6, and M8 are turned on, so that part of the current flows to the power supply voltage through NMOS tubes M5 and M6, and the current flowing to the output load circuit becomes small, and the common-gate stage circuit works in a low-gain mode. In the above two gain modes, the current flowing through the differential NMOS pair tubes M1 and M2 in the input stage circuit remains unchanged, i.e., the transconductance of the differential NMOS pair tubes M1 and M2 remains unchanged; the above two gain modes expand the dynamic range of the radio frequency amplifier.

[0013] Further, the common-source stage transistor in the input stage circuit is superimposed with the common-gate stage circuit to form a common-source common-gate structure; the common-gate stage transistor in the common-source common-gate structure is divided into two parts, so that the voltage falling on the common-source stage transistor becomes small.

[0014] Further, the common-gate stage circuit is connected in series with the input stage circuit, so that the equivalent output impedance viewed from the drain of the common-gate stage transistor to ground is increased.

[0015] Further, the common-gate stage circuit includes ten NMOS transistors M3, M4, M41, M5, M51, M6, M61, M7, M71, M8, two inverters B1, B2, two gain control signals GainCtrl1, GainCtrl2, and two inverted gain control signals ENB1, ENB2. When both of the gain control signals GainCtrl1, GainCtrl2 are high, the NMOS transistors M4, M41, M7, M71 are turned on, and the NMOS transistors M5, M51, M6, M61 are turned off, so that the common-gate stage circuit works in a maximum gain mode. When both of the gain control signals GainCtrl1, GainCtrl2 are low, the common-gate stage circuit works in a minimum gain mode. When one of the gain control signals GainCtrl1, GainCtrl2 is high and the other is low, the common-gate stage circuit works in an intermediate gain mode. The above four gain modes expand the dynamic range of the radio frequency amplifier.

[0016] Further, the output load circuit includes a transformer two, a programmable capacitor array C4, and a load resistor. The primary coil of the transformer two is connected in parallel with the programmable capacitor array C4, which covers different frequency bands by adjusting the programmable capacitor array C4; the center tap of the primary coil of the transformer two is connected to a power supply voltage; the secondary coil of the transformer two is connected in parallel with the load resistor; one end of the load resistor serves as an output voltage, and the other end of the load resistor is connected to ground. The radio frequency current signal output by the common-gate stage circuit is transmitted to the resonant frequency selection network composed of the transformer two and the programmable capacitor array C4, the transformer two not only converts the differential signal into a single-ended signal, but also transmits power to the load resistor through the impedance ratio of the transformer two to realize signal amplification output, and the load resistor converts the radio frequency current signal into a radio frequency voltage signal. Advantages

[0017] The technical effects achieved by the present application are as follows: (1) The gate inductors Lg1 and Lg2 and the source degeneration inductor Ls of the common-source stage transistor are omitted in the input stage circuit, thereby reducing the size of the entire radio frequency amplifier, lowering the complexity of layout design, and reducing the manufacturing cost. (2) The layout of the three-coil transformer one is optimized to achieve wideband input impedance matching. (3) The source degeneration inductor Ls of the common-source stage transistor is equivalently obtained by the three-coil transformer one, thereby retaining the advantage of high linearity. (4) At least two gain control modes are designed in the common-gate stage circuit, thereby achieving a large dynamic range. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a circuit structure schematic diagram of a prior radio frequency amplifier.

[0019] FIG. 2 is a circuit structure schematic diagram of a low-cost high-performance radio frequency amplifier proposed by the present application.

[0020] Fig. 3 is a structural schematic diagram of the three-coil transformer Trl in Fig. 2.

[0021] Fig. 4 is a layout design schematic diagram of the three-coil transformer Trl in Fig. 2.

[0022] Fig. 5 is a layout design schematic diagram of the main coil Ll in Fig. 4.

[0023] Fig. 6 is a layout design schematic diagram of the secondary coil L2 in Fig. 4.

[0024] Fig. 7 is a layout design schematic diagram of the third coil L3 in Fig. 4.

[0025] Fig. 8 is a schematic diagram of input matching of the radio frequency amplifier proposed in the present application.

[0026] Fig. 9 is a schematic diagram of the common gate stage circuit for realizing four gain modes through 2-bit control bits.

[0027] Reference numerals in the drawings: vin is input voltage, vout is output voltage, Trl and Tr2 are transformers, Ll to L3 are coils, Lgl and Lg2 are gate inductors, Ls is source degeneration inductor, C1 and C2 are gate-source cross capacitances, Ml to M8, M41, M51, M61, M71 are NMOS transistors, Rl to R4 are bias resistors, VBgm and VBcas are gate bias voltages, Cgl and Cg2 are gate decoupling capacitances, C1 to C4 are capacitances, VDD is power supply voltage, R L is load resistor, kg and ks are coupling coefficients, p1p and p1n are two terminals of the main coil, p2p and p2n are two terminals of the secondary coil, p3p and p3n are two terminals of the third coil, GainCtrl, GainCtrl1, GainCtrl2 are gain control signals, B1 and B2 are inverters, ENB, ENB1, ENB2 are inverted gain control signals. Embodiments of the present application

[0028] Please refer to Fig. 2, the low-cost high-performance radio frequency amplifier comprises an input stage circuit, a common-gate stage circuit and an output load circuit. The input stage circuit realizes conversion from single-ended signal to differential signal, matches input impedance to a desired value, for example, 50 ohms, and converts voltage signal to current signal. The common-gate stage circuit transmits radio frequency current signal output by the input stage circuit to the output load circuit, so as to improve reliability of the circuit and prevent the circuit from being broken down. The common-gate stage circuit also improves equivalent output impedance of the circuit, so that the circuit has better reverse isolation. The common-gate stage circuit also realizes gain control in different modes. The output load circuit converts radio frequency current signal from the common-gate stage circuit to radio frequency voltage signal, forms a resonant frequency selection network through transformer two Tr2 and programmable capacitor array C4, and transmits power of the primary coil of transformer two Tr2 to the load resistor R L The input stage circuit realizes conversion from single-ended signal to differential signal, matches input impedance to a desired value, for example, 50 ohms, and converts voltage signal to current signal. The common-gate stage circuit transmits radio frequency current signal output by the input stage circuit to the output load circuit, so as to improve reliability of the circuit and prevent the circuit from being broken down. The common-gate stage circuit also improves equivalent output impedance of the circuit, so that the circuit has better reverse isolation. The common-gate stage circuit also realizes gain control in different modes. The output load circuit converts radio frequency current signal from the common-gate stage circuit to radio frequency voltage signal, forms a resonant frequency selection network through transformer two Tr2 and programmable capacitor array C4, and transmits power of the primary coil of transformer two Tr2 to the load resistor R L The input stage circuit realizes conversion from single-ended signal to differential signal, matches input impedance to a desired value, for example, 50 ohms, and converts voltage signal to current signal. The common-gate stage circuit transmits radio frequency current signal output by the input stage circuit to the output load circuit, so as to improve reliability of the circuit and prevent the circuit from being broken down. The common-gate stage circuit also improves equivalent output impedance of the circuit, so that the circuit has better reverse isolation. The common-gate stage circuit also realizes gain control in different modes. The output load circuit converts radio frequency current signal from the common-gate stage circuit to radio frequency voltage signal, forms a resonant frequency selection network through transformer two Tr2 and programmable capacitor array C4, and transmits power of the primary coil of transformer two Tr2 to the load resistor R

[0029] The input stage circuit realizes conversion from single-ended signal to differential signal, matches input impedance to a desired value, for example, 50 ohms, and converts voltage signal to current signal. The common-gate stage circuit transmits radio frequency current signal output by the input stage circuit to the output load circuit, so as to improve reliability of the circuit and prevent the circuit from being broken down. The common-gate stage circuit also improves equivalent output impedance of the circuit, so that the circuit has better reverse isolation. The common-gate stage circuit also realizes gain control in different modes. The output load circuit converts radio frequency current signal from the common-gate stage circuit to radio frequency voltage signal, forms a resonant frequency selection network through transformer two Tr2 and programmable capacitor array C4, and transmits power of the primary coil of transformer two Tr2 to the load resistor R

[0030] Please refer to Fig. 3, in the three-coil transformer one Tr1, coupling coefficient between the primary coil L1 and the secondary coil L2 is kg. Coupling coefficient between the primary coil L1 and the third coil L3 is ks. The center tap of the secondary coil L2 is connected to the center tap of the third coil L3 and grounded.

[0031] Referring to FIG. 4 to FIG. 7, an exemplary layout design of the three-coil transformer Trl is shown. The black filled area represents the top layer metal, the diagonal filled area represents the second layer (sub-top layer) metal, the dot filled area represents the third layer (third top layer) metal, and the white small square represents the via metal. The main coil Ll is mainly two large annular loops, one end Plp is connected to the input voltage vin, and the other end Pln is connected to ground. The main coil Ll is mainly implemented in the second layer metal, and individual parts are connected to the third layer metal through vias. The second layer metal is usually the thickest metal, which can reduce the parasitic resistance. The secondary coil L2 is also mainly two large annular loops, in order to have a large enough coupling coefficient kg with the main coil Ll, the secondary coil L2 is basically stacked on the main coil Ll, and the main part of the secondary coil L2 corresponds to the main part of the main coil Ll. The secondary coil L2 is mainly implemented in the top layer metal, and individual parts are connected to the second layer metal through vias. The two ends p2p and p2n of the secondary coil L2 output a differential voltage signal. In order to make the differential signal have better symmetry performance, the center tap of the secondary coil L2 is connected to the center tap of the third coil L3 and given a fixed potential, which is grounded in the design, so that the potential at this point is defined, effectively improving the phase and amplitude symmetry of the differential output signal of the secondary coil L2. The third coil L3 is mainly two small annular loops, which are surrounded by the large annular loops of the main coil Ll and the secondary coil L2. The two ends P3p and P3n of the third coil L3 are respectively connected to the sources of the differential NMOS pair tubes M2 and Ml. The third coil L3 is mainly implemented in the second layer metal, and individual parts are connected to the third layer metal through vias, and the center tap is connected to the top layer metal through vias.

[0032] The coupling inductance between the primary coil L1 and the secondary coil L2 in the three-coil transformer Tr1 is equivalent to the gate inductance of the differential NMOS pair M1 and M2, i.e. Lg1 and Lg2 in Fig. 1. The third coil L3 in the three-coil transformer Tr1 is equivalent to the first part of the source degeneration inductance of the differential NMOS pair M1 and M2, and the coupling inductance between the primary coil L1 and the third coil L3 is equivalent to the second part of the source degeneration inductance of the differential NMOS pair M1 and M2. The sum of the two parts is equivalent to the source degeneration inductance Ls of the differential NMOS pair M1 and M2 in Fig. 1. Thus, the input stage circuit in Fig. 2 is equivalent to the input stage circuit in Fig. 1, and the input impedance matching is achieved based on the resonance of all the capacitors and the equivalent inductors. Since the source degeneration inductance of the differential NMOS pair M1 and M2 is integrated in the three-coil transformer Tr1, the circuit linearity is improved while the area is greatly reduced. In the layout design, the third coil L3 and the primary coil L1 are far apart, and the coupling coefficient is low, so that the wideband input matching is achieved. Each coil is designed as two annular coils, so that the center taps of the secondary coil L2 and the third coil L3 are corresponding and connected together, which greatly simplifies the wiring arrangement. By connecting the center taps of the secondary coil L2 and the third coil L3 and grounding, a certain common-mode potential is provided, which effectively improves the phase and amplitude balance characteristics of the differential signal output by the secondary coil L2, i.e. effectively reduces the amplitude error and phase error of the differential signal output by the secondary coil L2. The amplitude error of the differential signal (relative to 0) is very small, and the phase error (relative to 180 degrees) is also very small.

[0033] The common-gate stage circuit in FIG. 2 includes NMOS transistors M3 to M8 (all common-gate transistors), gate-decoupling capacitors Cg1 and Cg2, bias resistors R3 and R4. The drain of NMOS transistor one M1 is connected to the source of NMOS transistor three M3, the source of NMOS transistor four M4, and the source of NMOS transistor five M5. The drain of NMOS transistor two M2 is connected to the source of NMOS transistor six M6, the source of NMOS transistor seven M7, and the source of NMOS transistor eight M8. The gate of NMOS transistor three M3 and the gate of NMOS transistor eight M8 are connected to gate bias voltage two VBcas through bias resistors R3 and R4, respectively. The gate of NMOS transistor three M3 and the gate of NMOS transistor eight M8 are also connected to ground through gate-decoupling capacitors Cg1 and Cg2, respectively. The gate-decoupling capacitors Cg1 and Cg2 filter high-frequency harmonics and noise from the gate of NMOS transistor three M3 and the gate of NMOS transistor eight M8. The drain of NMOS transistor three M3 and the drain of NMOS transistor four M4 are connected to an output load circuit. The drain of NMOS transistor eight M8 and the drain of NMOS transistor seven M7 are connected to an output load circuit. The gate of NMOS transistor four M4 and the gate of NMOS transistor seven M7 are connected to gain control signal GainCtrl. Gain control signal GainCtrl is connected to inverter B1, which outputs inverted gain control signal ENB. ENB and GainCtrl are opposite, i.e., when GainCtrl is high, ENB is low, and when GainCtrl is low, ENB is high. The gate of NMOS transistor five M5 and the gate of NMOS transistor six M6 are connected to inverted gain control signal ENB. The drain of NMOS transistor five M5 and the drain of NMOS transistor six M6 are connected to power supply voltage VDD. The common-gate stage circuit is added to the radio frequency amplifier shown in FIG. 1, and includes six NMOS transistors M3 to M8. The added common-gate stage circuit is used to achieve different gain selection, i.e., to achieve a higher dynamic range.

[0034] When gain control signal GainCtrl is high (value equal to gate bias voltage two VBcas) and inverted gain control signal ENB is low (value 0), NMOS transistor three M3, NMOS transistor four M4, NMOS transistor seven M7, and NMOS transistor eight M8 work normally (are turned on), and NMOS transistor five M5 and NMOS transistor six M6 are turned off. The common-gate stage circuit shown in FIG. 2 works in a high-gain mode.

[0035] When the gain control signal GainCtrl is low (value is 0) and the inverting gain control signal ENB is high (value is equal to the gate bias voltage VBCas), the NMOS transistor four M4 and the NMOS transistor seven M7 are turned off, and the NMOS transistor three M3, the NMOS transistor five M5, the NMOS transistor six M6 and the NMOS transistor eight M8 are turned on (normal working), so that part of the current flows through the NMOS transistor five M5 and the NMOS transistor six M6 to the power supply voltage VDD, and the current flowing to the output load circuit is small, and the common-gate stage circuit shown in Fig. 2 works in the low-gain mode.

[0036] In the above two gain modes, the current flowing through the differential NMOS pair transistor M1 and M2 in the input stage circuit is unchanged, which means that the transconductance of the differential NMOS pair transistor M1 and M2 is unchanged, so it does not affect the input matching performance of the input stage circuit, and at the same time, a large dynamic range is provided.

[0037] The input stage circuit in Fig. 2 includes the common-source stage NMOS pair transistor M1 and M2, and after superimposing the common-gate stage circuit in Fig. 2, a common-source common-gate structure is formed. The common-gate stage NMOS transistor in the common-source common-gate structure divides a part of the voltage, so that the voltage (for example, the source-drain voltage Vds) falling on the common-source stage NMOS transistor is a little smaller, which effectively protects the common-source stage NMOS transistor and improves the reliability of the circuit, preventing the circuit from being broken down.

[0038] Compared with Fig. 1, the common-gate stage circuit newly added in Fig. 2 is connected in series with the input stage circuit, and this series connection increases the equivalent impedance seen from the drain of the common-gate stage NMOS transistor to the ground, which is called the multiplication effect. The output impedance of the common-source stage NMOS transistor M1 in Fig. 1 is ro1. The equivalent impedance (output impedance) seen from the drain of the common-gate stage NMOS transistor M3 to the ground in Fig. 2 is ro1+ro3+gm3*ro3*ro1, wherein ro3 is the output impedance of the NMOS transistor three M3, and gm3 is the transconductance of the NMOS transistor three M3. Obviously, Fig. 2 increases the equivalent output impedance of the circuit by adding the common-gate stage circuit, so that the circuit has better reverse isolation.

[0039] The common-gate stage circuit in Fig. 2 has the characteristic of controllable gain. The above two gain modes are realized by 1-bit control bits to achieve gain control, which means that the gain control signal GainCtrl has only 1 bit, and can only realize the gain control of low level or high level (i.e. 0 or 1), and can only get two gain modes.

[0040] Based on the same principle can be extended to any bit gain control. Please refer to Figure 9, the common gate circuit shown in Figure 9 includes 10 NMOS, two inverters B1 and B2, two gain control signals GainCtrl1 and GainCtrl2, two inverted gain control signals ENB1 and ENB2, so that the control of four gain modes can be achieved by 2-bit control bits. When both gain control signals GainCtrl1 and GainCtrl2 are high (represented by binary number 11), NMOS M4, M41, M7, M71 are turned on, and NMOS M5, M51, M6, M61 are turned off, which is the maximum gain. When both gain control signals GainCtrl1 and GainCtrl2 are low (represented by binary number 00), it is the minimum gain. When the two gain control signals GainCtrl1 and GainCtrl2 are high-low (represented by binary number 01) or low-high (represented by binary number 10), it is the middle two gain.

[0041] Preferably, the substrates of all NMOS M1 and M2 in the input stage circuit and all NMOS M3 to M8 in the common gate circuit are grounded.

[0042] The output load circuit in Figure 2 includes transformer two Tr2, programmable capacitor array C4, load resistor R L The primary winding of transformer two Tr2 is connected in parallel with the programmable capacitor array C4. By adjusting the programmable capacitor array C4, different frequency bands (such as a wide frequency band of 4GHz to 7GHz) can be covered, which can be used in wireless communication systems such as LTE (Long Term Evolution), Sub-6GHz, WIFI, etc. The center tap of the primary winding of transformer two Tr2 is connected to the power supply voltage VDD. The secondary winding of transformer two Tr2 is connected in parallel with the load resistor R L , one end of the load resistor R L serves as the output voltage vout, and the other end of the load resistor R L is grounded; by changing the load, it can also be applied to higher or lower frequency bands. The RF current signal output by the common gate circuit is transmitted to the resonant frequency selection network composed of transformer two Tr2 and adjustable capacitor C4, and through transformer two Tr2, both the conversion from differential signal to single-ended signal is realized, and the power is transmitted to the load resistor R L through the appropriate impedance ratio of transformer two Tr2 to realize high-power signal output, and the load stage converts the RF current signal into an RF voltage signal.

[0043] Compared with the prior art, the RF amplifier proposed in the present application has the following advantages.

[0044] First, a simple three-coil transformer Tr1 is used to realize the conversion of single-ended signal to differential signal and good input matching. Compared with the traditional circuit, three inductors are saved, which greatly reduces the layout area, the manufacturing cost and the complexity of layout design.

[0045] Second, the input matching of large bandwidth is realized. The main coil L1 and the third coil L3 of the three-coil transformer Tr1 are far apart, and the coupling coefficient is low, which is a kind of wideband design technology and can realize large bandwidth input matching. Please refer to FIG. 8, which is the input matching diagram of the radio frequency amplifier proposed in the present application. The horizontal axis is the frequency, and the vertical axis is the S parameter. The experiment shows that the input matching of the radio frequency amplifier proposed in the present application is better than -10 dB in the frequency range of 3.62 GHz to 11.07 GHz, which realizes wideband input matching. If the size of the three-coil transformer Tr1 is changed, a wider frequency coverage range will be realized.

[0046] Third, the center tap of the secondary coil L2 of the three-coil transformer Tr1 is grounded, which gives a fixed potential and effectively improves the amplitude and phase error of the differential signal output by the secondary coil L2. Through special layout design, the layout of the center tap of the secondary coil L2 and the third coil L3 is simplified.

[0047] Fourth, the input stage circuit no longer uses a special source degeneration inductor, but integrates it in the three-coil transformer Tr1. Using a special source degeneration inductor can improve the linearity. The present application omits the special source degeneration inductor, but the three-coil transformer Tr1 equivalently generates a source degeneration inductor, so that the advantages of improving linearity are maintained while a large layout area is saved.

[0048] Fifth, by controlling the gain control signal GainCtrl of the common-gate stage circuit, the common-gate stage circuit works in high and low gain modes. Assuming that the transistor width-length ratio of M3 and M8 is 3 times that of M4, M5, M6 and M7, and the transistor width-length ratio of M4 and M7 is the same as that of M5 and M6, the current flowing to the output load circuit in the high gain mode is W4 / L4+W3 / L3=4*W4 / (3L4), and the current flowing to the output load circuit in the low gain mode is W4 / L4-W5 / L5=2*W4 / (3L4). Thus, the gain ratio of the high and low gain modes is 2, i.e. 6 dB dynamic range, which realizes dynamic adjustment and expands the application scope.

[0049] The above is only the preferred embodiment of the present application and is not used to limit the present application. Various changes and modifications can be made by those skilled in the art based on the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A low cost high performance radio frequency amplifier characterized by, The input stage circuit, the common gate stage circuit and the output load circuit are included. The input stage circuit realizes conversion of single-ended signal to differential signal, realizes input impedance matching, and converts input radio frequency voltage signal to radio frequency current signal; the input stage circuit includes a three-coil transformer and a common source transistor, the three-coil transformer is composed of a primary coil, a secondary coil and a third coil; the secondary coil is connected in parallel with a programmable capacitor array; the coupling inductance between the primary coil and the secondary coil is equivalent to the gate inductance of the common source transistor; the third coil is equivalent to the first part of the source degeneration inductance of the common source transistor, and the coupling inductance between the primary coil and the third coil is equivalent to the second part of the source degeneration inductance of the common source transistor, and the sum of the two parts is equivalent to the source degeneration inductance of the common source transistor; In the three-coil transformer, the primary coil is two large annular coils, the secondary coil is also two large annular coils, and the secondary coil is stacked above the primary coil; the third coil is two small annular coils, which are surrounded by the large annular coils of the primary coil and the secondary coil; the center tap of the secondary coil is connected with the center tap of the third coil and grounded; The common gate stage circuit transmits the radio frequency current signal output by the input stage circuit to the output load circuit, improves the voltage resistance and equivalent output impedance of the circuit, and realizes gain control in at least two modes; The output load circuit converts the radio frequency current signal from the common gate stage circuit to a radio frequency voltage signal, realizes conversion from differential signal to single-ended signal, and outputs the amplified radio frequency voltage signal.

2. The low cost high performance radio frequency amplifier of claim 1, characterized by, The entire radio frequency amplifier presents a left-right symmetrical structure, and the symmetrical devices have the same parameters.

3. The low cost high performance radio frequency amplifier of claim 1, wherein, The input stage circuit further includes a programmable capacitor array (C1), two DC blocking capacitors (C2, C3), a differential NMOS pair (M1, M2), and two bias resistors (R1, R2); the differential NMOS pair (M1, M2) serves as the common source transistor; In the three-coil transformer, one end of the primary coil is connected to the input voltage, and the other end is grounded; the secondary coil is connected in parallel with the programmable capacitor array (C1), and the two ends of the secondary coil are further connected to the gates of the differential NMOS pair (M1, M2) through two DC blocking capacitors (C2, C3); the primary coil and the secondary coil realize conversion from single-ended signal to differential signal; the two ends of the third coil are connected to the sources of the differential NMOS pair (M1, M2); The gates of the differential NMOS pair (M1, M2) are further connected to a gate bias voltage one through two bias resistors (R1, R2); the drains of the differential NMOS pair (M1, M2) output a differential current signal to the common gate stage circuit; the differential NMOS pair (M1, M2) realizes conversion from voltage signal to current signal; The input stage circuit realizes input impedance matching based on the resonance of all capacitors and equivalent inductances.

4. The low cost high performance radio frequency amplifier of claim 3, wherein, The common gate stage circuit includes NMOS tubes (M3 to M8), gate decoupling capacitors (Cg1, Cg2), and bias resistors (R3, R4). The drain of the NMOS transistor one (M1) is connected to the source of the NMOS transistor three (M3), the source of the NMOS transistor four (M4) and the source of the NMOS transistor five (M5); the drain of the NMOS transistor two (M2) is connected to the source of the NMOS transistor six (M6), the source of the NMOS transistor seven (M7) and the source of the NMOS transistor eight (M8); the gate of the NMOS transistor three (M3) and the gate of the NMOS transistor eight (M8) are connected to a gate bias voltage two through two bias resistors (R3, R4) respectively; the gate of the NMOS transistor three (M3) and the gate of the NMOS transistor eight (M8) are also connected to ground through two gate-end decoupling capacitors (Cg1, Cg2) respectively; the drain of the NMOS transistor three (M3) and the drain of the NMOS transistor four (M4) are connected to an output load circuit; the drain of the NMOS transistor eight (M8) and the drain of the NMOS transistor seven (M7) are connected to the output load circuit; the gate of the NMOS transistor four (M4) and the gate of the NMOS transistor seven (M7) are connected to a gain control signal; the gain control signal is connected to an inverter to output an inverted gain control signal; the gate of the NMOS transistor five (M5) and the gate of the NMOS transistor six (M6) are connected to the inverted gain control signal; the drain of the NMOS transistor five (M5) and the drain of the NMOS transistor six (M6) are connected to a power supply voltage.

5. The low cost high performance radio frequency amplifier of claim 4, wherein, When the gain control signal is high and the inverted gain control signal is low, the NMOS transistor three (M3), the NMOS transistor four (M4), the NMOS transistor seven (M7) and the NMOS transistor eight (M8) are turned on, the NMOS transistor five (M5) and the NMOS transistor six (M6) are turned off, and the common-gate circuit works in a high-gain mode; When the gain control signal is low and the inverted gain control signal is high, the NMOS transistor four (M4) and the NMOS transistor seven (M7) are turned off, the NMOS transistor three (M3), the NMOS transistor five (M5), the NMOS transistor six (M6) and the NMOS transistor eight (M8) are turned on, part of the current flows to the power supply voltage through the NMOS transistor five (M5) and the NMOS transistor six (M6), the current flowing to the output load circuit becomes small, and the common-gate circuit works in a low-gain mode; In the above two gain modes, the current flowing through the differential NMOS pair (M1, M2) in the input stage circuit remains unchanged, that is, the transconductance of the differential NMOS pair (M1, M2) remains unchanged; the above two gain modes expand the dynamic range of the radio frequency amplifier.

6. The low cost high performance radio frequency amplifier of claim 1, wherein, The common-source transistor in the input stage circuit is superimposed on the common-gate circuit to form a common-source common-gate structure; the common-gate transistor in the common-source common-gate structure divides a part of the voltage, so that the voltage falling on the common-source transistor becomes small.

7. The low cost high performance radio frequency amplifier of claim 1, wherein, The common-gate circuit is connected in series with the input stage circuit, so that the equivalent output impedance from the drain of the common-gate transistor to the ground is increased.

8. The low cost high performance radio frequency amplifier of claim 1, wherein, The common-gate stage circuit comprises ten NMOS tubes (M3, M4, M41, M5, M51, M6, M61, M7, M71, M8), two inverters (B1, B2), two gain control signals (GainCtrl1, GainCtrl2), and two inverted gain control signals (ENB1, ENB2); When the two gain control signals (GainCtrl1, GainCtrl2) are both high, the NMOS tubes (M4, M41, M7, M71) are turned on, the NMOS tubes (M5, M51, M6, M61) are turned off, and the common-gate stage circuit works in the maximum gain mode; When the two gain control signals (GainCtrl1, GainCtrl2) are both low, the common-gate stage circuit works in the minimum gain mode; When the two gain control signals (GainCtrl1, GainCtrl2) are one high and one low or one low and one high, the common-gate stage circuit works in the intermediate two-gear gain mode. The above four gain modes expand the dynamic range of the radio frequency amplifier.

9. The low cost high performance radio frequency amplifier of claim 1, wherein, The output load circuit comprises transformer two, a programmable capacitor array (C4), and a load resistor; The primary coil of transformer two is connected in parallel with the programmable capacitor array (C4), which covers different frequency bands by adjusting the programmable capacitor array (C4); the center tap of the primary coil of transformer two is connected to the power supply voltage; the secondary coil of transformer two is connected in parallel with the load resistor; one end of the load resistor serves as the output voltage, and the other end of the load resistor is connected to the ground; The radio frequency current signal output by the common-gate stage circuit is transmitted to the resonant frequency selection network composed of transformer two and the programmable capacitor array (C4); transformer two not only realizes the conversion from a differential signal to a single-ended signal, but also transmits power to the load resistor through the impedance ratio of transformer two to realize signal amplification output; the load resistor converts the radio frequency current signal into a radio frequency voltage signal.

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