Array substrate, display panel, and electronic device

Abstract

The present disclosure relates to the technical field of display, and provides an array substrate, a display panel, and an electronic device. The array substrate comprises: a display area and a peripheral area. The peripheral area is provided with a detection line and a ground line, and the detection line and the ground line have an overlapping area in the thickness direction of the array substrate. The detection line comprises a detection trace located in the overlapping area, and the ground line comprises a ground trace located in the overlapping area. The array substrate comprises a base substrate, and the detection trace and the ground trace are respectively located on two sides of the base substrate. In embodiments of the present disclosure, the detection trace comprised in the detection line and the ground trace comprised in the ground line are respectively arranged on two sides of the base substrate, so as to isolate the detection trace from the ground trace by means of the base substrate to avoid electrostatic breakdown between the detection line and the ground line in the overlapping area, thereby preventing static electricity from being conducted to the detection line and conducted to a driving circuit along the detection line, ensuring the driving effect of the driving circuit, and thus ensuring the display effect of the display panel.

Description

Array substrate, display panel and electronic equipment

[0001] Cross-referencing

[0002] This disclosure claims priority to Chinese Patent Application No. 202411046295.6, filed on July 31, 2024, entitled "Array Substrate, Display Panel and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to an array substrate, a display panel, and an electronic device. Background Technology

[0004] With the development of display technology, electronic devices are becoming smaller and smaller, which brings challenges to wiring. In related technologies, electronic devices typically have drive circuits, detection lines, and grounding lines around their perimeter. The detection lines are connected to the drive circuits, and there is an overlap between the detection lines and the grounding lines. When static electricity is released and conducted along the grounding line, it can easily cause electrostatic breakdown in the overlap area with the detection lines, leading to a short circuit between the grounding and detection lines. In this case, the static electricity is conducted along the detection lines to the drive circuit, thus affecting the display effect of the electronic device.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide an array substrate, a display panel, and an electronic device.

[0007] According to one aspect of this disclosure, an array substrate is provided, comprising: a display area and a peripheral area located around the display area;

[0008] The peripheral area has a detection line and a ground line, the detection line and the ground line have an overlapping area in the thickness direction of the array substrate, and the detection line includes a detection trace located in the overlapping area, and the ground line includes a ground trace located in the overlapping area;

[0009] The array substrate includes a substrate, and the detection trace and the ground trace are located on both sides of the substrate.

[0010] According to any of the array substrates described in this disclosure, the array substrate includes:

[0011] A metal trace layer is located on the first side of the substrate and has the ground trace;

[0012] A gate metal layer is located on the second side of the substrate and has a first ground segment and a second ground segment. The first ground segment and the second ground segment are respectively connected to the two ends of the ground trace through vias.

[0013] An active layer is located on the side of the gate metal layer that faces away from the substrate.

[0014] A source / drain metal layer is located on the side of the active layer away from the substrate and has the detection trace;

[0015] The electrode layer is located on the side of the source / drain metal layer that is away from the substrate.

[0016] According to any of the array substrates described in this disclosure, the detection line has a trace break extending to the edge of the peripheral region, and the array substrate includes:

[0017] A metal trace layer is located on the first side of the substrate and has the detection trace, the first end of the detection trace being connected to the trace break.

[0018] A gate metal layer is located on the second side of the substrate and has the ground line;

[0019] An active layer is located on the side of the gate metal layer that faces away from the substrate.

[0020] The source / drain metal layer is located on the side of the active layer that is away from the substrate.

[0021] An electrode layer is located on the side of the source / drain metal layer away from the substrate and has a first jumper wire connected to the second end of the detection trace via a via.

[0022] According to any of the array substrates described in this disclosure, the metal trace layer has a first trace segment, and the gate metal layer has a first conductive portion;

[0023] One end of the first trace is connected to the second segment of the detection trace, and the other end is connected to the first conductive part through a via. The first conductive part is connected to the first jumper through a via.

[0024] According to any of the array substrates described in this disclosure, the metal trace layer has a second trace, one end of which is connected to the detection trace, and the other end of which forms the trace break.

[0025] According to any of the array substrates described in this disclosure, the electrode layer further has a second jumper, the first end of the second jumper forming the trace break, and the second end of the second jumper being connected to the first end of the detection trace via a via.

[0026] According to any of the array substrates described in this disclosure, the gate metal layer has a first conductive portion and a second conductive portion located on both sides of the ground line;

[0027] The first conductive part is connected to the second end of the first jumper and the second end of the detection trace through vias, and the second conductive part is connected to the second end of the second jumper and the first end of the detection trace through vias.

[0028] According to any of the array substrates described in this disclosure, the array substrate includes a first electrode layer and a second electrode layer;

[0029] The first electrode layer is located on the side of the second electrode layer opposite to the substrate, the first electrode layer has the first jumper, and the second electrode layer has the second jumper.

[0030] According to one aspect of this disclosure, an array substrate is provided, comprising: a display area and a peripheral area located around the display area;

[0031] The peripheral area has a detection line and a ground line, the detection line and the ground line have an overlapping area in the thickness direction of the array substrate, and the detection line includes a detection trace located in the overlapping area, and the ground line includes a ground trace located in the overlapping area;

[0032] The array substrate includes a substrate and a gate metal layer, a first insulating layer, an active layer, a source / drain metal layer, a second insulating layer, and an electrode layer, which are stacked sequentially on one side of the substrate. The active layer has padding traces located in the overlapping region.

[0033] Specifically, in the thickness direction of the array substrate, at least the first insulating layer and the padding layer are included between the detection trace and the ground trace.

[0034] According to any of the array substrates described in this disclosure, the ground trace is located in the gate metal layer, and the detection trace is located in the source / drain metal layer.

[0035] According to any of the array substrates described in this disclosure, the ground trace is located in the gate metal layer, and the detection trace is located in the electrode layer.

[0036] According to any of the array substrates described in this disclosure, the orthogonal projection of the pad layer traces on the substrate covers the orthogonal projection of the detection traces on the substrate.

[0037] According to one aspect of this disclosure, a display panel is provided, comprising the array substrate described in the preceding aspect.

[0038] According to one aspect of this disclosure, an electronic device is provided, including the display panel described in the foregoing aspect.

[0039] The embodiments disclosed herein include at least the following technical effects:

[0040] In this embodiment of the present disclosure, the detection traces included in the detection line and the ground traces included in the ground line are respectively disposed on both sides of the substrate. The substrate isolates the detection traces and the ground traces, preventing electrostatic breakdown in the overlapping area of ​​the detection traces and the ground traces. This avoids the electrostatic discharge from being conducted to the detection traces and then to the driving circuit, ensuring the driving effect of the driving circuit and thus ensuring the display effect of the display panel.

[0041] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0043] Figure 1 is a cross-sectional structural diagram of a display panel in the display area according to an embodiment of the present disclosure.

[0044] Figure 2 is a top view of an array substrate provided in an embodiment of this disclosure.

[0045] Figure 3 is a schematic cross-sectional view of an array substrate in the peripheral region according to an embodiment of this disclosure.

[0046] Figure 4 is a schematic cross-sectional view of another array substrate in the peripheral region provided by an embodiment of this disclosure.

[0047] Figure 5 is a schematic cross-sectional view of the peripheral region of another array substrate provided in this embodiment.

[0048] Figure 6 is a cross-sectional structural diagram of the peripheral region of another array substrate provided in this embodiment.

[0049] Figure 7 is a schematic cross-sectional view of the peripheral region of another array substrate provided in this embodiment.

[0050] Figure 8 is a cross-sectional view of the peripheral region of another array substrate provided in this embodiment.

[0051] Reference numerals: 10. Display panel; AA. Display area; BB. Peripheral area; AA1. Pixel circuit; BB1. Overlapping area; BB2. Driving circuit; BB3. Conductive part; BB4. Flexible circuit board; 1. Array substrate; 2. Electronic paper film; 3. Common electrode layer; 4. Protective film; 11. Substrate; 12. Gate metal layer; 13. First insulating layer; 14. Active layer; 15. Source / drain metal layer; 16. Second insulating layer; 17. Electrode layer; 18. Metal trace layer; 141. Pad layer trace; 171. First electrode layer; 172. Second electrode layer; GND. Ground line; G1. Ground trace; G2. First ground segment; G3. Second ground segment; AT. Detection line; A1. Detection segment; A2. First jumper; A3. Second jumper; A4. First conductive part; A5. Second conductive part; A11, Trace inspection; A12, First trace; A13, Second trace. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0053] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0054] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0055] This disclosure provides an electronic device, which may be an electronic tag, a wearable product (such as an electronic watch), etc.

[0056] Electronic devices mainly include display panels to display images. Display panels can be LCD panels, electronic paper, etc.

[0057] Taking electronic devices as examples, electronic devices include electronic paper, communication modules, and control motherboards (such as microcontrollers). The electronic paper is electrically connected to the communication module and the control motherboard respectively. When the communication module receives radio frequency signals (such as commodity prices) sent by the data system, it stores the radio frequency signals in the control motherboard, processes them through the control motherboard, and then displays them through the electronic paper.

[0058] Taking electronic paper as an example, as shown in Figure 1, the display panel 10 includes an array substrate 1, an electronic paper film 2, a common electrode layer 3 and a protective film 4. The electronic paper film 2 is located between the array substrate 1 and the common electrode layer 3, and the protective film 4 covers the common electrode layer 3.

[0059] The electronic paper film 2 includes multiple microstructures, such as microcups or microcapsules. Each microstructure includes a transparent liquid and various charged particles suspended in the transparent liquid, such as charged white particles and charged black particles. The white particles can be negatively charged and the black particles can be positively charged, or the black particles can be negatively charged and the white particles can be positively charged.

[0060] Taking the display panel 10 as an example of a liquid crystal panel, the display panel includes an array substrate 1, a liquid crystal layer and a color filter substrate, with the liquid crystal layer located between the array substrate 1 and the color filter substrate.

[0061] In some embodiments, as shown in FIG2, the array substrate 1 includes a display area AA and a peripheral area BB located around the display area AA. The display area AA is provided with an array of pixel circuits AA1. The peripheral area BB is provided with a driving circuit BB2 (e.g., GOA circuit), a voltage signal line (e.g., ground line GND) and a conductive part BB3 (e.g., silver paste dots). The driving circuit BB2 is connected to the pixel circuits AA1 of the display area AA and is used to connect to the control main board through the flexible circuit board BB4. One end of the voltage signal line is connected to the conductive part BB3, and the other end of the voltage signal line is connected to the control main board through the flexible circuit board BB4. The conductive part BB3 is used to connect to the common electrode layer 3.

[0062] In this way, under the control of the main board, the pixel circuit AA1 can be driven to work, and a voltage can be applied to the common electrode layer 3, thereby realizing the color change of the electronic paper film 2 and realizing the display of the image.

[0063] Optionally, the pixel circuit AA1 includes a switching device (such as a thin-film transistor), the control electrode of which is used to load a scan signal, and the first electrode of which is used to load a drive signal. Thus, when a scan signal is loaded onto the pixel circuit AA1, the switching device can be turned on, and simultaneously, the operation of the pixel circuit AA1 can be controlled by the drive signal loaded onto it. For example, the pixel circuit AA1 includes a thin-film transistor and a storage capacitor.

[0064] In some embodiments, as shown in FIG1, the array substrate 1 includes a substrate 11, and a gate metal layer 12, an active layer 14, a source / drain metal layer 15 and an electrode layer 17 sequentially stacked on the substrate 11.

[0065] The substrate 11 can be a glass substrate, quartz substrate, plastic substrate, or other rigid or flexible substrate, and can be a single-layer or multi-layer structure. Taking a multi-layer structure as an example, the substrate 11 includes a first polyimide layer, a first protective layer, a second polyimide layer, and a second protective layer stacked sequentially from bottom to top. The two protective layers are used to protect the polyimide layers and prevent damage to the polyimide layers by subsequent processes. A buffer layer is also covered on the second protective layer to block water and oxygen and to block alkaline ions.

[0066] The gate metal layer 12 is provided with multiple gate lines located in the display area AA, and the source / drain metal layer 15 is provided with multiple data lines located in the display area AA. In conjunction with the switching device included in the pixel circuit AA1, the gate metal layer 12 includes a first conductive part A4, which forms the control electrode of the switching device and is connected to the gate lines to load a scan signal. The active layer 14 includes an active part, which includes a channel region that overlaps with the first conductive part A4 and a connection part located on both sides of the channel region. The source / drain metal layer 15 includes a second conductive part A5 and a third conductive part BB3, which respectively form the first electrode and the second electrode of the switching device. The second conductive part A5 and the third conductive part BB3 directly cover the connection parts on both sides of the channel region of the active part, and the second conductive part A5 is connected to the data line to load a drive signal. The third conductive part BB3 is connected to the electrode layer 17.

[0067] In the case where the display panel 10 is electronic paper, the array substrate 1 includes an electrode layer 17, which is a pixel electrode layer. The film structure of the array substrate 1 is shown in Figure 1, comprising a gate metal layer 12, a first insulating layer 13 (e.g., a gate insulating layer), an active layer 14, a source / drain metal layer 15, a second insulating layer 16 (e.g., a passivation layer), and an electrode layer 17, sequentially stacked on one side of the substrate 11. When the display panel 10 is a liquid crystal panel, the array substrate 1 includes two electrode layers 17, namely a first electrode layer 171 and a second electrode layer 172. In this case, the array substrate 1 includes a gate metal layer 12, a first insulating layer 13 (e.g., a gate insulating layer), an active layer 14, a source / drain metal layer 15, a second electrode layer 172 (e.g., a common electrode layer), a second insulating layer 16 (e.g., a passivation layer), and a first electrode layer 171 (e.g., a pixel electrode layer), sequentially stacked on one side of the substrate 11.

[0068] In this embodiment, the array substrate 1 is typically obtained by cutting an array motherboard (including multiple array substrates 1 spliced ​​together). Before cutting the array motherboard, the array motherboard has detection lines AT extending to each array substrate 1. The detection lines AT enable the detection of multiple array substrates 1 on the array motherboard, thereby ensuring the manufacturing yield of the array substrates 1 and improving the detection efficiency of the array substrates 1. Thus, after the array motherboard is inspected to obtain the array substrate 1, as shown in FIG2, the peripheral area BB of the array substrate 1 has detection lines AT. One end of the detection lines AT is connected to the driving circuit BB2 of the peripheral area BB, and the other end of the detection lines AT (i.e., the trace break) extends to the outer edge of the peripheral area BB.

[0069] The detection line AT includes a detection segment A1 and a first jumper A2. One end of the detection segment A1 is connected to the first jumper A2 through a via, and the end of the first jumper A2 not connected to the detection segment A1 is connected to the drive circuit BB2. The other end of the detection segment A1 extends to the outer edge of the peripheral area BB to form a trace break in the detection line AT. Alternatively, the detection line AT includes a detection segment A1, a first jumper A2, and a second jumper A3. Both ends of the detection segment A1 are connected to the first jumper A2 and the second jumper A3 respectively through vias. The end of the first jumper A2 not connected to the detection segment A1 is connected to the drive circuit BB2, and the end of the second jumper A3 not connected to the detection segment A1 extends to the outer edge of the peripheral area BB to form a trace break in the detection line AT.

[0070] It should be noted that when the array substrate 1 includes an electrode layer 17, for the detection line AT including the first jumper A2, or the first jumper A2 and the second jumper A3, the first jumper A2 or the first jumper A2 and the second jumper A3 are both located in the electrode layer 17; when the array substrate 1 includes a first electrode layer 171 and a second electrode layer 172, for the detection line AT including the first jumper A2, the first jumper A2 can be located in the first electrode layer 171 or in the second electrode layer 172; for the detection line AT including the first jumper A2 and the second jumper A3, the first jumper A2 and the second jumper A3 can be in the same layer and located in the first electrode layer 171, or located in the second electrode layer 172, or the first jumper A2 and the second jumper A3 can be in different layers, with one located in the first electrode layer 171 and the other located in the second electrode layer 172.

[0071] As shown in Figure 2, the detection line AT and the ground line GND (voltage signal trace) of the outer area BB overlap in the thickness direction of the array substrate 1, forming an overlapping area BB1. If the distance between the detection line AT and the ground line GND is close in the thickness direction of the array substrate 1, electrostatic breakdown is likely to occur in the overlapping area BB1 when static electricity is conducted along the ground line GND, causing a short circuit between the ground line GND and the detection line AT. At this time, the conduction path of static electricity is shown as O1-O2 in Figure 2, that is, it is first conducted to the detection line AT, and then conducted along the detection line AT to the driving circuit BB2, thereby affecting the normal driving of the pixel circuit AA1 by the driving circuit BB2, and thus affecting the display effect of the image in the display area AA.

[0072] In this embodiment of the disclosure, as shown in FIG3, the detection line AT and the ground line GND (voltage signal trace) of the peripheral area BB have an overlapping area BB1 in the thickness direction of the array substrate 1, and the detection line AT includes the detection trace A11 located in the overlapping area BB1, and the ground line GND includes the ground trace G1 located in the overlapping area BB1.

[0073] In some embodiments, as shown in FIG3 or FIG4, the detection trace A11 and the ground trace G1 are located on both sides of the substrate 11.

[0074] Thus, the detection trace A11 of the detection line AT and the ground trace G1 of the ground line GND are respectively disposed on both sides of the substrate 11. The substrate 11 isolates the detection trace A11 and the ground trace G1, preventing electrostatic breakdown of the detection line AT and the ground line GND in the overlapping area BB1. This avoids the electrostatic discharge to the detection line AT and then to the driving circuit BB2, ensuring the driving effect of the driving circuit BB2 and thus ensuring the display effect of the display panel 10.

[0075] In cases where the detection trace A11 and the ground trace G1 are located on opposite sides of the substrate 11, the array substrate 1 further includes a metal trace layer 18 located on the side of the substrate 11 away from the gate metal layer 12. As shown in Figure 3 or Figure 4, the array substrate 1 includes a metal trace layer 18 located on the first side of the substrate 11, and a gate metal layer 12, an active layer 14 (not shown in the figure), a source / drain metal layer 15, and an electrode layer 17 located on the second side of the substrate 11.

[0076] The array substrate 1 described above includes a metal trace layer 18. In this case, either the ground trace G1 or the detection trace A11 can be located in the metal trace layer 18.

[0077] When the grounding trace G1 is located in the metal trace layer 18, since the metal trace layer 18 does not have other traces, it is convenient to increase the size of the grounding trace G1, etc., to facilitate the conduction of static electricity. Alternatively, the entire grounding trace GND of the peripheral area BB can be located in the metal trace layer 18, or the grounding trace G1 included on the grounding trace GND can be located in the metal trace layer 18.

[0078] As shown in Figure 3, in addition to the grounding trace G1, the grounding wire GND also includes a first grounding segment G2 and a second grounding segment G3 connected to both ends of the grounding wire GND. The end of the first grounding segment G2 away from the grounding trace G1 is connected to the flexible circuit board BB4 (the metal pin of the flexible circuit board BB4), and the end of the second grounding segment G3 away from the grounding trace G1 is connected to the conductive part BB3.

[0079] In some embodiments, as shown in FIG3, the metal trace layer 18 has a ground trace G1, the gate metal layer 12 has a first ground segment G2 and a second ground segment G3, the first ground segment G2 and the second ground segment G3 are respectively connected to the two ends of the ground trace G1 through vias (such as glass vias); the source drain metal layer 15 has a detection line AT.

[0080] Thus, the two ends of the grounding trace G1 on the metal trace layer 18 can be connected to the first grounding segment G2 and the second grounding segment G3 respectively through vias on the substrate 11, so that the grounding line GND can be connected to the flexible circuit board BB4 and the conductive part BB3 respectively. At the same time, the substrate 11 and the first insulating layer 13 isolate the grounding trace G1 from the detection trace A11 included in the detection line AT, so as to avoid electrostatic breakdown between the grounding trace G1 and the detection trace A11.

[0081] When the detection trace A11 is located in the metal trace layer 18, it can mean that the entire detection segment A1 included by the detection trace AT is located in the metal trace layer 18, or it can mean that the detection trace A11 located in the overlapping area BB1 on the detection trace AT is located in the metal trace layer 18.

[0082] As described above, as shown in Figure 4, the detection segment A1 of the detection line AT includes not only the detection trace A11, but also a first trace A12 and a second trace A13 connected to both ends of the detection trace A11. The end of the first trace A12 that is not connected to the detection trace A11 is connected to the first jumper A2. The end of the second trace A13 that is not connected to the detection trace A11 forms a trace break in the detection line AT, or is connected to the second jumper A3.

[0083] In some embodiments, as shown in FIG4, the metal trace layer 18 has a detection trace A11, the first end of which is connected to a trace break (not shown in the figure), the gate metal layer 12 has a ground line GND, and the electrode layer 17 has a first jumper A2, which is connected to the second end of the detection trace A11 through a via (such as a glass via).

[0084] Thus, one end of the detection trace A11 on the metal trace layer 18 can be connected to the first jumper A2 through a via on the substrate 11 to facilitate the transmission of the detection signal. At the same time, the substrate 11 isolates the ground trace G1 included in the ground line GND from the detection trace A11, preventing electrostatic breakdown between the ground trace G1 and the detection trace A11.

[0085] In some embodiments, the first segment A12 of the detection line AT may be provided by the source / drain metal layer 15, and the first segment A12 may be connected to the second end of the first jumper A2 and the detection line A11 through vias. Alternatively, as shown in FIG4, the metal wiring layer 18 may have the first segment A12, the gate metal layer 12 may have a first conductive portion A4, one end of the first segment A12 may be connected to the second segment of the detection line A11, and the other end may be connected to the first conductive portion A4 through a via (such as a glass via penetrating the substrate 11), and the first conductive portion A4 may be connected to the first jumper A2 through a via.

[0086] When the first trace A12 is located in the metal trace layer 18, the detection trace A11 and the first trace A12 can be set in the same layer and integrally. Vias can also be fabricated separately on the substrate 11. As long as the connection between the first trace A12 and the first conductive part A4 is ensured, it is not necessary to consider the accurate alignment of the vias on the substrate 11 and the vias on the insulating layer (gate insulating layer, passivation layer), thereby simplifying the connection process between the detection trace A11 and the first jumper A2.

[0087] In some embodiments, the second trace A13 included in the detection line AT can be as shown in FIG4, where the metal trace layer 18 has the second trace A13, one end of the second trace A13 is connected to the detection trace A11, and the other end forms the trace break of the detection line AT. Alternatively, the source / drain metal layer 15 may have the second trace A13, the gate metal layer 12 may have a second conductive portion A5, the first end of the detection trace A11 is connected to the second conductive portion A5 through a via, the second conductive portion A5 is connected to one end of the second trace A13 through a via, and the end of the second trace A13 not connected to the second conductive portion A5 forms the trace break of the detection line AT.

[0088] When the second trace A13 is located in the metal trace layer 18, the detection trace A11 and the second trace A13 can be set in the same layer and as a whole, and only the second trace A13 needs to be set, which makes it easier to simplify the wiring of the detection line AT on the array substrate 1.

[0089] In some embodiments, the second jumper A3 included in the detection line AT can be as shown in Figure 5 or Figure 6. The electrode layer 17 also has a second jumper A3. The first end of the second jumper A3 forms a trace break, and the second end of the second jumper A3 is connected to the first end of the detection trace A11 through a via.

[0090] Thus, by setting the second jumper A3 on the electrode layer 17, it is easy to increase the signal resistance on the detection line AT, thereby improving the anti-static capability of the detection line AT.

[0091] The detection line AT includes a first jumper A2 and a second jumper A3, as shown in Figure 5. The array substrate 1 includes an electrode layer 17. This allows the first jumper A2 and the second jumper A3 to be arranged on the same layer, simplifying the arrangement of the detection line AT on the array substrate 1. Alternatively, as shown in Figure 6, the array substrate 1 includes a first electrode layer 171 and a second electrode layer 172. The first electrode layer 171 is located on the side of the second electrode layer 172 facing away from the substrate 11. The first electrode layer 171 has the first jumper A2, and the second electrode layer 172 has the second jumper A3. This allows the first jumper A2 and the second jumper A3 to be arranged separately, avoiding interference between them.

[0092] Optionally, as shown in Figure 5 or Figure 6, the gate metal layer 12 has a first conductive part A4 and a second conductive part A5 located on both sides of the ground line GND. The first conductive part A4 is connected to the second end of the first jumper A2 and the detection trace A11 through vias, respectively. The second conductive part A5 is connected to the second end of the second jumper A3 and the first end of the detection trace A11 through vias, respectively.

[0093] Thus, by providing the first conductive part A4 and the second conductive part A5 on the gate metal layer 12, vias can be fabricated on the substrate 11 independently without considering the accurate alignment of the vias on the substrate 11 with the vias on the insulating layer (gate insulating layer, passivation layer), thereby simplifying the connection between the detection trace A11 and the first jumper A2 and the second jumper A3.

[0094] Among them, the first segment A12 and the second segment A13 of the detection line AT can be set in the metal trace layer 18 at the same time, or they can be set in the source and drain metal layer 15 at the same time, or one can be set in the metal trace layer 18 and the other in the source and drain metal layer 15, etc.

[0095] For example, as shown in Figure 5 or Figure 6, the first trace A12 and the second trace A13 are located on the metal trace layer 18. The two ends of the detection trace A11 are connected to the first trace A12 and the second trace A13, respectively. The first trace A12 and the second trace A13 are connected to the first conductive part A4 and the second conductive part A5, respectively, through vias (glass vias) penetrating the substrate 11. In this way, the detection trace A11 is integrated with the first trace A12 and the second trace A13 on the same layer, while the vias on the substrate 11 can be set separately, thereby simplifying the wiring of the detection line AT on the array substrate 1.

[0096] In some other embodiments, the array substrate 1 includes a film structure as shown in FIG1. ​​In this case, as shown in FIG7 or FIG8, the active layer 14 has a pad layer trace 141 located in the overlapping region BB1, and in the thickness direction of the array substrate 1, at least a first insulating layer 13 and a pad layer trace 141 are included between the detection trace A11 and the ground trace G1.

[0097] Thus, through the first insulating layer 13 located between the detection trace A11 and the ground trace G1, and the pad trace 141 included in the high-resistance active layer 14, effective isolation is achieved between the detection trace A11 and the ground trace G1, preventing electrostatic breakdown of the detection line AT and the ground line GND in the overlapping area BB1. This avoids the conduction of static electricity to the detection line AT and along the detection line AT to the drive circuit BB2, ensuring the driving effect of the drive circuit BB2, and thus ensuring the display effect of the display panel 10.

[0098] Specifically, for the padding trace 141 included in the active layer 14, the orthogonal projection of the padding trace 141 on the substrate 11 may cover the orthogonal projection of the detection trace A11 on the substrate 11, or the orthogonal projection of the padding trace 141 on the substrate 11 may be located within the orthogonal projection of the ground trace G1 on the substrate 11, so as to achieve effective isolation between the detection trace A11 and the ground trace G1.

[0099] In conjunction with the above, the detection line AT includes detection segment A1 and first jumper A2, or includes detection segment A1, first jumper A2 and second jumper A3.

[0100] When the detection line AT includes detection segment A1 and first jumper A2, detection segment A1 is located in the source / drain metal layer 15, and first jumper A2 is located in the electrode layer 17.

[0101] As shown in Figure 7, the ground line GND is located in the gate metal layer 12, and there is an overlap area BB1 between the ground line GND and the detection segment A1 in the thickness direction of the array substrate 1. That is, the detection segment A1 includes the detection trace A11, and the detection trace A11 is located in the source-drain metal layer 15. In this way, the detection trace A11 and the ground trace G1 can be effectively isolated by the first insulating layer 13 and the pad trace 141.

[0102] When the detection line AT includes detection segment A1, first jumper A2 and second jumper A3, detection segment A1 is located in the source / drain metal layer 15, and the first jumper A2 and the second jumper A3 are both located in the electrode layer 17.

[0103] Optionally, as shown in FIG7, the ground line GND is located in the gate metal layer 12, and the ground line GND and the detection segment A1 have an overlap area BB1 in the thickness direction of the array substrate 1. That is, the detection segment A1 includes the detection trace A11, and the detection trace A11 is located in the source-drain metal layer 15. In this way, the detection trace A11 and the ground trace G1 can be effectively isolated by the first insulating layer 13 and the pad trace 141.

[0104] Optionally, as shown in FIG8, the ground line GND is located in the gate metal layer 12, and the ground line GND and the second jumper A3 have an overlapping area BB1 in the thickness direction of the array substrate 1. That is, the second jumper A3 includes the detection trace A11, and the detection trace A11 is located in the electrode layer 17. In this way, the detection trace A11 and the ground trace G1 can be effectively isolated by the first insulating layer 13, the second insulating layer 16 and the pad trace 141.

[0105] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein, The array substrate comprises: a display area and a peripheral area located at the periphery of the display area; the peripheral area has a detection line and a ground line, the detection line and the ground line have a coincident area in the thickness direction of the array substrate, and the detection line comprises a detection trace located in the coincident area, and the ground line comprises a ground trace located in the coincident area; the array substrate comprises a substrate substrate, and the detection trace and the ground trace are located on two sides of the substrate substrate respectively.

2. The array substrate of claim 1, wherein, The array substrate comprises: a metal trace layer located on the first side of the substrate substrate and having the ground trace; a gate metal layer located on the second side of the substrate substrate and having a first ground segment and a second ground segment, the first ground segment and the second ground segment are connected to the two ends of the ground trace through vias respectively; an active layer located on the side of the gate metal layer away from the substrate substrate; a source-drain metal layer located on the side of the active layer away from the substrate substrate and having the detection trace; an electrode layer located on the side of the source-drain metal layer away from the substrate substrate.

3. The array substrate of claim 1, wherein, The detection line has a trace break extending to the edge of the peripheral area, and the array substrate comprises: a metal trace layer located on the first side of the substrate substrate and having the detection trace, the first end of the detection trace is connected to the trace break; a gate metal layer located on the second side of the substrate substrate and having the ground line; an active layer located on the side of the gate metal layer away from the substrate substrate; a source-drain metal layer located on the side of the active layer away from the substrate substrate; an electrode layer located on the side of the source-drain metal layer away from the substrate substrate and having a first jumper, the first jumper is connected to the second end of the detection trace through a via.

4. The array substrate of claim 3, wherein, The metal trace layer has a first segment of trace, and the gate metal layer has a first conductive part; one end of the first segment of trace is connected to the second segment of the detection trace, and the other end is connected to the first conductive part through a via, and the first conductive part is connected to the first jumper through a via.

5. The array substrate of claim 3, wherein, The metal trace layer has a second segment of trace, one end of the second segment of trace is connected to the detection trace, and the other end constitutes the trace break.

6. The array substrate of claim 3, wherein, The electrode layer also has a second jumper, the first end of the second jumper constitutes the trace break, and the second end of the second jumper is connected to the first end of the detection trace through a via.

7. The array substrate of claim 6, wherein, The gate metal layer has a first conductive part and a second conductive part located on both sides of the ground line; the first conductive part is connected to the second end of the first jumper and the second end of the detection trace through a via respectively, and the second conductive part is connected to the second end of the second jumper and the first end of the detection trace through a via respectively.

8. The array substrate of claim 6, wherein, The array substrate comprises a first electrode layer and a second electrode layer; the first electrode layer is located on the side of the second electrode layer away from the substrate substrate, the first electrode layer has the first jumper, and the second electrode layer has the second jumper.

9. An array substrate, wherein, The array substrate comprises: a display area and a peripheral area located at the periphery of the display area; The peripheral area has a detection line and a ground line, the detection line and the ground line have a coincident area in a thickness direction of the array substrate, and the detection line includes a detection trace in the coincident area, and the ground line includes a ground trace in the coincident area; The array substrate includes a substrate, and a gate metal layer, a first insulating layer, an active layer, a source-drain metal layer, a second insulating layer and an electrode layer which are sequentially stacked on one side of the substrate, and the active layer has a pad trace in the coincident area; In the thickness direction of the array substrate, the detection trace and the ground trace at least include the first insulating layer and the pad trace.

10. The array substrate of claim 9, wherein, The ground trace is located in the gate metal layer, and the detection trace is located in the source-drain metal layer.

11. The array substrate of claim 9, wherein, The ground trace is located in the gate metal layer, and the detection trace is located in the electrode layer.

12. The array substrate of any one of claims 9-11, wherein, The pad trace covers the detection trace in a normal projection of the substrate.

13. A display panel, wherein, The array substrate includes any one of claims 1-12.

14. An electronic device, comprising: The display panel includes claim 13.

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