Shift register unit, display driver and display apparatus

Abstract

Provided are a shift register unit, a display driver and a display apparatus, which belong to the technical field of display. In the shift register unit, an input control circuit can control the potential of an input node, and an output control circuit can output a display driving signal to a pixel on the basis of the potential of the input node and an enable signal provided by an enable line. Thus, by flexibly setting an enable signal and a clock signal, a shift register unit can output a signal matching a P-type transistor and / or an N-type transistor in a pixel. Moreover, an output control circuit and an input control circuit are sequentially arranged in a first direction and in a direction approaching the pixel, signal lines connected to the output control circuit and the input control circuit are sequentially arranged in the first direction and in the direction approaching the pixel, and the signal lines all extend in a second direction intersecting the first direction; as a result, the narrow bezel design of a display apparatus can also be facilitated.

Description

Shift register unit, display driver and display device

[0001] The present application claims priority from the Chinese patent application No. 202411035310.7 filed on July 30, 2024 and entitled "Shift register unit, display driver and display device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, in particular to a shift register unit, a display driver and a display device. BACKGROUND

[0003] Gate driver on array (GOA) technology is a technology of integrating a display driver on a display panel, which can facilitate the narrow frame design of the display panel. Correspondingly, the display driver is also called GOA circuit. Generally, the GOA circuit can include a plurality of shift register units connected in cascade, and the shift register unit is also called GOA unit. SUMMARY

[0004] A shift register unit, a display driver and a display device are provided. The technical solutions are as follows:

[0005] In one aspect, a shift register unit is provided, which includes:

[0006] An input control circuit, connected with a first clock line, a second clock line, an input signal terminal and an input node respectively, and configured to control the on-off of the input signal terminal and the input node in response to a first clock signal provided by the first clock line and a second clock signal provided by the second clock line;

[0007] An output control circuit, connected with the input node, an enable line and an output signal terminal respectively, and configured to control the potential of the output signal terminal based on the potential of the input node and an enable signal provided by the enable line, so as to output a display driving signal to a P-type transistor and / or an N-type transistor of each pixel in at least one row of pixels through the output signal terminal, to drive the light emitting element of the each pixel to emit light;

[0008] Wherein, the output control circuit and the input control circuit are arranged in a first direction and in a direction close to the pixels in sequence; the first clock line, the second clock line and the enable line are arranged in the first direction and in the direction close to the pixels in sequence, and the first clock line, the second clock line and the enable line all extend in a second direction; the second direction intersects with the first direction.

[0009] Optionally, the output control circuit includes:

[0010] a first output control sub-circuit, connected with the input node, the reset control line and the intermediate node respectively, and configured to control a potential of the intermediate node based on a potential of the input node and a reset control signal provided by the reset control line;

[0011] a second output control sub-circuit, connected with the intermediate node, the enable line and the output signal terminal respectively, and configured to control a potential of the output signal terminal based on a potential of the intermediate node and the enable signal;

[0012] The first output control sub-circuit and the second output control sub-circuit are arranged in the second direction and away from the input control circuit; the reset control line is located on a side of the first clock line away from the enable line, and the reset control line extends in the second direction.

[0013] Optionally, the shift register unit further comprises:

[0014] a switch control circuit, connected between the enable line and the output control circuit, and further connected with at least two first control terminals and at least two second control terminals respectively, and configured to control the on-off of the enable line and the output control circuit in response to a first control signal provided by each of the first control terminals and a second control signal provided by each of the second control terminals;

[0015] a latch circuit, connected with a third clock line, a fourth clock line, the intermediate node and the input node respectively, and configured to control the on-off of the intermediate node and the input node in response to a third clock signal provided by the third clock line and a fourth clock signal provided by the fourth clock line, and output a potential of the intermediate node to the input node after being inverted;

[0016] a driving enhancement circuit, connected between the output control circuit and the output signal terminal, and configured to output a potential of a signal output by the output control circuit to the output signal terminal after being inverted at least once;

[0017] The latch circuit is located in an area defined by the output control circuit, the input control circuit and the switch control circuit, and the driving enhancement circuit is located at least on a side of the second output control sub-circuit away from the first output control sub-circuit; the third clock line and the fourth clock line are located between the reset control line and the enable line, and the third clock line and the fourth clock line are arranged in the first direction and close to the pixel in sequence, and the third clock line and the fourth clock line extend in the second direction.

[0018] Optionally, the input control circuit comprises a first transmission gate; the first output control sub-circuit comprises an NOR gate; the second output control sub-circuit comprises an NAND gate; the latch circuit comprises a first NOT gate and a second transmission gate; the switch control circuit comprises two third transmission gates connected in series; and the driving enhancement circuit comprises three second NOT gates connected in series.

[0019] The first transmission gate is connected between the input signal terminal and the input node, and is further connected with the first clock line and the second clock line respectively; two input terminals of the NOR gate are connected with the reset control line and the input node respectively, and an output terminal of the NOR gate is connected with the intermediate node; one input terminal of the NAND gate is connected with the intermediate node, and the other input terminal of the NAND gate is connected with the enable line through the two third transmission gates connected in series, and an output terminal of the NAND gate is connected with the output signal terminal through the three second NOT gates connected in series, each of the third transmission gates is further connected with a corresponding first control terminal and a second control terminal respectively; an input terminal of the first NOT gate is connected with the intermediate node, and an output terminal of the first NOT gate is connected with the input node through the second transmission gate, and the first transmission gate is further connected with the third clock line and the fourth clock line respectively; and the shift register unit further comprises a voltage stabilizing capacitor connected between a ground terminal and the other input terminal of the NAND gate.

[0020] The NOR gate, the NAND gate and the first second NOT gate are arranged in the second direction in sequence, the first transmission gate, the second transmission gate, the first NOT gate, the fourth transmission gate and the second second NOT gate are arranged in the second direction in sequence, the third transmission gate is located on a side of the first NOT gate away from the fourth transmission gate, the voltage stabilizing capacitor is located between the NAND gate and the fourth transmission gate, the first second NOT gate to the third second NOT gate are arranged in the first direction and in a direction close to the pixel in sequence, and the size of the first second NOT gate to the third second NOT gate increases in sequence.

[0021] Optionally, the NOR gate, the NAND gate, the first NOT gate and each of the second NOT gates are further connected with a first power supply line and a second power supply line respectively, and are configured to work based on a first power supply signal provided by the first power supply line and a second power supply signal provided by the second power supply line, and the potential of the first power supply signal is greater than the potential of the second power supply signal.

[0022] The first power line and the second power line are located at least on two sides of the reset control line and the enable line in the first direction, and the first power line and the second power line extend along the second direction; the width of the first power line and the width of the second power line are greater than the width of the reset control line and the width of the enable line; the width of the first power line connected to the third second NOT gate is greater than the width of the first power line connected to other gate circuits, and the width of the second power line connected to the third second NOT gate is greater than the width of the second power line connected to the other gate circuits; the other gate circuits include at least one of the NAND gate, the NOR gate, the first NOT gate, the second second NOT gate, and the first first NOT gate.

[0023] Optionally, the first transmission gate includes a first P-type transistor and a first N-type transistor.

[0024] The gate of the first P-type transistor and the gate of the first N-type transistor are connected to the first clock line and the second clock line respectively, the first pole of the first P-type transistor and the first pole of the first N-type transistor are connected to the input signal end, and the second pole of the first P-type transistor and the second pole of the first N-type transistor are connected to the input node.

[0025] Further, the first P-type transistor and the first N-type transistor are arranged in sequence along the first direction and along the direction close to the pixel.

[0026] Optionally, the NAND gate includes a second P-type transistor, a second N-type transistor, a third P-type transistor, and a third N-type transistor.

[0027] The gate of the second P-type transistor and the gate of the third N-type transistor are connected to the reset control line, the first pole of the second P-type transistor is connected to the first power line, the second pole of the second P-type transistor is connected to the first pole of the third P-type transistor, the second pole of the third P-type transistor, the second pole of the second N-type transistor, and the second pole of the third N-type transistor are connected to the intermediate node, the first pole of the second N-type transistor and the first pole of the third N-type transistor are connected to the second power line, and the gate of the third P-type transistor and the gate of the second N-type transistor are connected to the input node.

[0028] And, the third P-type transistor and the second P-type transistor are arranged in sequence along the second direction and a direction close to the NAND gate, the second N-type transistor is located on a side of the third P-type transistor away from the second P-type transistor, and the second N-type transistor is close to the pixel relative to the third P-type transistor, the third N-type transistor is located on a side of the second P-type transistor away from the third P-type transistor, and the third N-type transistor is close to the pixel relative to the second P-type transistor.

[0029] Optionally, the first NAND gate comprises a fourth P-type transistor and a fourth N-type transistor, and the fourth N-type transistor is a double-gate transistor; and the second transfer gate comprises a fifth P-type transistor and a fifth N-type transistor.

[0030] The gate of the fourth P-type transistor and the gate of the fourth N-type transistor are connected with the intermediate node, the first pole of the fourth P-type transistor and the first pole of the fourth N-type transistor are connected with the first power supply line and the second power supply line respectively, the second pole of the fourth P-type transistor and the second pole of the fourth N-type transistor are connected with the first pole of the fifth P-type transistor and the first pole of the fifth N-type transistor, the gate of the fifth P-type transistor and the gate of the fifth N-type transistor are connected with the third clock line and the fourth clock line respectively, and the second pole of the fifth P-type transistor and the second pole of the fifth N-type transistor are connected with the input node.

[0031] And, the fourth P-type transistor and the fourth N-type transistor are arranged in sequence along the first direction and a direction close to the pixel, the fifth P-type transistor and the fifth N-type transistor are arranged in sequence along the first direction and a direction close to the pixel, the fifth P-type transistor and the fourth N-type transistor are arranged in sequence along the second direction and a direction away from the first transfer gate, and the fifth N-type transistor and the fourth P-type transistor are arranged in sequence along the second direction and a direction away from the first transfer gate.

[0032] Optionally, the NAND gate comprises a sixth P-type transistor, a sixth N-type transistor, a seventh P-type transistor and a seventh N-type transistor; a second third transfer gate comprises an eighth P-type transistor and an eighth N-type transistor; a first third transfer gate comprises a ninth P-type transistor and a ninth N-type transistor; a first second NAND gate comprises a tenth P-type transistor and a tenth N-type transistor; a second second NAND gate comprises an eleventh P-type transistor and an eleventh N-type transistor; and a third second NAND gate comprises a twelfth P-type transistor and a twelfth N-type transistor.

[0033] The gate of the sixth P-type transistor and the gate of the sixth N-type transistor are connected with the intermediate node, the gate of the seventh P-type transistor and the gate of the seventh N-type transistor are connected with the first node, the second pole of the sixth P-type transistor, the second pole of the seventh P-type transistor and the second pole of the sixth N-type transistor are connected with the second node, the first pole of the sixth N-type transistor is connected with the second pole of the seventh N-type transistor, the gate of the eighth P-type transistor and the gate of the eighth N-type transistor are connected with one-to-one corresponding one first control end and one second control end respectively, the gate of the ninth P-type transistor and the gate of the ninth N-type transistor are connected with one-to-one corresponding another first control end and another second control end respectively, the first pole of the ninth P-type transistor and the first pole of the ninth N-type transistor are connected with the enable line, the second pole of the ninth P-type transistor and the second pole of the ninth N-type transistor are connected with the first pole of the eighth P-type transistor and the first pole of the eighth N-type transistor, the second pole of the eighth P-type transistor and the second pole of the eighth N-type transistor are connected with the first node, the gate of the tenth P-type transistor and the gate of the tenth N-type transistor are connected with the second node, the gate of the eleventh P-type transistor and the gate of the eleventh N-type transistor are connected with the second pole of the tenth P-type transistor and the second pole of the tenth N-type transistor, the gate of the twelfth P-type transistor and the gate of the twelfth N-type transistor are connected with the second pole of the eleventh P-type transistor and the second pole of the eleventh N-type transistor, the second pole of the twelfth P-type transistor and the second pole of the twelfth N-type transistor are connected with the output signal end, and the first pole of the sixth P-type transistor, the first pole of the seventh P-type transistor, and the first pole of the tenth P-type transistor to the first pole of the twelfth P-type transistor are connected with the first power supply line, the first pole of the seventh N-type transistor, and the first pole of the tenth N-type transistor to the first pole of the twelfth N-type transistor are connected with the second power supply line;

[0034] And, the seventh N-type transistor, the sixth N-type transistor, the sixth P-type transistor and the seventh P-type transistor are sequentially arranged along the second direction and along a direction close to the tenth P-type transistor, the eighth N-type transistor and the eighth P-type transistor are sequentially arranged along the first direction and along a direction close to the pixel, the ninth P-type transistor and the ninth N-type transistor are sequentially arranged along the second direction and along a direction close to the eighth P-type transistor, the tenth P-type transistor and the tenth N-type transistor are sequentially arranged along the first direction and along a direction close to the pixel, the eleventh N-type transistor and the eleventh P-type transistor are sequentially arranged along the second direction and along a direction away from the eighth P-type transistor, and the twelfth P-type transistor and the twelfth N-type transistor are sequentially arranged along the second direction and along a direction close to the eleventh P-type transistor.

[0035] Optionally, sizes of the transistors in the first second NOT gate to the third second NOT gate are sequentially increased.

[0036] And, sizes of the transistors in the first transfer gate, the NOT gate, the NAND gate, the first NOT gate, the second transfer gate and each third transfer gate are all smaller than a size of the transistors in any second NOT gate.

[0037] Optionally, the first clock line, the second clock line, the enable line, the reset control line, the third clock line and the fourth clock line are all located on the same side of the first output control sub-circuit away from the second output control sub-circuit, and are arranged at equal intervals in the first direction.

[0038] Optionally, the transistors in the shift register unit include: a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked.

[0039] The first active layer is used as an active layer of a P-type transistor in the shift register unit, and the second active layer is used as an active layer of an N-type transistor in the shift register unit.

[0040] Optionally, at least part of the first source-drain metal layer is multiplexed with at least one of the first active layer, the first gate metal layer, the second gate metal layer and the second active layer, so as to reduce an overlapping area of the first source-drain metal layer and the second source-drain metal layer.

[0041] In another aspect, a display driver is provided, which includes at least two shift register units as described in the above aspect.

[0042] In yet another aspect, a display device is provided, the display device comprising a display panel, and the display driver as in another aspect above.

[0043] The display panel comprises a plurality of pixels, and the display driver is connected with the plurality of pixels and configured to transmit display driving signals to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0045] FIG. 1 is a structural schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0046] FIG. 2 is a structural schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0047] FIG. 3 is a working timing schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0048] FIG. 4 is a structural layout schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0049] FIG. 5 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0050] FIG. 6 is a circuit structural schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0051] FIG. 7 is a circuit structural layout schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0052] FIG. 8 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0053] FIG. 9 is a circuit layout schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0054] FIG. 10 is a layout schematic diagram of a part of a film layer of a shift register unit according to an embodiment of the present disclosure;

[0055] FIG. 11 is a layout schematic diagram of another part of a film layer of a shift register unit according to an embodiment of the present disclosure;

[0056] FIG. 12 is a layout schematic diagram of still another part of a film layer of a shift register unit according to an embodiment of the present disclosure;

[0057] FIG. 13 is a layout diagram of another part of a film layer of a shift register unit according to an embodiment of the present disclosure;

[0058] FIG. 14 is a layout diagram of another part of a film layer of a shift register unit according to an embodiment of the present disclosure;

[0059] FIG. 15 is a layout diagram of another part of a film layer of a shift register unit according to an embodiment of the present disclosure;

[0060] FIG. 16 is a layout diagram of another part of a film layer of a shift register unit according to an embodiment of the present disclosure;

[0061] FIG. 17 is a layout diagram of another part of a film layer of a shift register unit according to an embodiment of the present disclosure;

[0062] FIG. 18 is a circuit layout diagram of another shift register unit according to an embodiment of the present disclosure;

[0063] FIG. 19 is a layout diagram of a part of a film layer of another shift register unit according to an embodiment of the present disclosure;

[0064] FIG. 20 is a layout diagram of another part of a film layer of another shift register unit according to an embodiment of the present disclosure;

[0065] FIG. 21 is a layout diagram of another part of a film layer of another shift register unit according to an embodiment of the present disclosure;

[0066] FIG. 22 is a layout diagram of another part of a film layer of another shift register unit according to an embodiment of the present disclosure;

[0067] FIG. 23 is a layout diagram of another part of a film layer of another shift register unit according to an embodiment of the present disclosure;

[0068] FIG. 24 is a layout diagram of another part of a film layer of another shift register unit according to an embodiment of the present disclosure;

[0069] FIG. 25 is a layout diagram of another part of a film layer of another shift register unit according to an embodiment of the present disclosure;

[0070] FIG. 26 is a layout diagram of another part of a film layer of another shift register unit according to an embodiment of the present disclosure;

[0071] FIG. 27 is a flow diagram of a driving method of a shift register unit according to an embodiment of the present disclosure;

[0072] FIG. 28 is a timing diagram of a driving method of a shift register unit according to an embodiment of the present disclosure;

[0073] Figure 29 is a schematic diagram of the structure of a display driver provided in an embodiment of this disclosure;

[0074] Figure 30 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0076] It is understood that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this disclosure, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle line of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this disclosure can include either P-type transistors or N-type transistors. A P-type transistor conducts when the gate is low and is cut off when the gate is high, while an N-type transistor conducts when the gate is high and is cut off when the gate is low. In addition, multiple signals in the various embodiments of this disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two states and do not represent that the first potential or the second potential has a specific value throughout the text.

[0077] This disclosure provides a shift register unit that can better match the timing requirements of N-type transistors and / or P-type transistors in a pixel, offering good driving flexibility and driving effect. As shown in Figure 1, the shift register unit includes an input control circuit 01 and an output control circuit 02.

[0078] The input control circuit 01 is connected to the first clock line CB, the second clock line CKn, the input signal terminal IN_n, and the input node Q_n, respectively, and is used to control the on / off state of the input signal terminal IN_n and the input node Q_n in response to the first clock signal provided by the first clock line CB and the second clock signal provided by the second clock line CKn.

[0079] For example, the input control circuit 01 can control the input signal terminal IN_n to be connected to the input node Q_n when the first clock signal has the first potential and the second clock signal has the first potential, so that the input signal provided by the input signal terminal IN_n is output to the input node Q_n, thereby controlling the potential of the input node Q_n to be the potential of the input signal; and the input control circuit 01 can control the input signal terminal IN_n to be disconnected from the input node Q_n when the first clock signal has the second potential or the second clock signal has the second potential.

[0080] It can be understood that "n" represents that the shift register unit is an nth shift register unit, and correspondingly, "n-m" represents that the shift register unit is cascaded with the previous m shift register units, and "n+m" represents that the shift register unit is cascaded with the next m shift register units, n can be an integer greater than 1, and m can be an integer less than n and greater than 1. For example, m can be 1, that is, each shift register unit can be cascaded with the previous shift register unit and the next shift register unit respectively except for the first shift register unit. The following embodiments are described by taking m as 1 as an example. Generally, the multi-stage shift register unit can be connected in one-to-one correspondence with multiple rows of pixels. Of course, it is not limited to one-to-one correspondence. For example, each shift register unit can be connected with at least two rows of pixels.

[0081] Optionally, in the embodiments of the present disclosure, the first potential can be a valid potential, and the second potential can be an invalid potential. Moreover, for the P-type transistor in the pixel, the first potential can be a low potential (low, L) relative to the second potential. For the N-type transistor in the pixel, the first potential can be a high potential (high, H) relative to the second potential. It can be known accordingly that the signal output to the P-type transistor in the reset state refers to that the potential of the signal output to the P-type transistor is high potential H, and the signal output to the N-type transistor in the reset state refers to that the potential of the signal output to the N-type transistor is low potential L. In addition, the high potential can be represented by binary "1", and the low potential can be represented by binary "0".

[0082] With reference back to FIG. 1, the output control circuit 02 is connected with the input node Q_n, the enable line EN and the output signal terminal OUT_n respectively, and is configured to control the potential of the output signal terminal OUT_n based on the potential of the input node Q_n and the enable signal provided by the enable line EN, so as to output a display driving signal to the P-type transistor and / or the N-type transistor of each pixel in at least one row of pixels through the output signal terminal OUT_n, to drive the light emitting element of each pixel to emit light.

[0083] Optionally, the display driving signal can include a gate driving signal, a reset signal or a light emitting control signal. That is, the output control circuit 02 can output a gate driving signal to the data writing transistor in the pixel through the output signal terminal OUT_n. Alternatively, the output control circuit 02 can output a reset signal to the reset transistor in the pixel through the output signal terminal OUT_n. Alternatively, the output control circuit 02 can output a light emitting control signal to the light emitting control transistor in the pixel through the output signal terminal OUT_n.

[0084] For example, the output control circuit 02 can control the potential of the output signal terminal OUT_n to be low potential 0 when the potential of the input node Q_n is high potential 1 and / or the potential of the enable signal is high potential 1; and the output control circuit 02 can control the potential of the output signal terminal OUT_n to be high potential 1 when the potential of the input node Q_n is low potential 0 and the potential of the enable signal is low potential 0. In this way, the display driving signal (such as a gate driving signal) including high potential 1 and low potential 0 (i.e., including the first potential and the second potential) can be output through the output signal terminal OUT_n, and the required timing pulses can be output to the P-type transistor and / or the N-type transistor in the pixel, so as to meet the driving requirements of the PMOS switch type pixel, or meet the driving requirements of the NMOS switch type pixel, or meet the driving requirements of the CMOS switch type pixel.

[0085] In addition, the output reset and local brushing control can also be realized by flexibly setting the enable signal provided by the enable line EN. For example, in the normal output or high brushing area, the potential of the enable signal can be set to high potential 1, so that the output control circuit 02 normally works; and in the reset stage or low brushing area, the potential of the enable signal can be set to low potential 0, so that the output control circuit 02 controls the potential of the output signal to be an invalid potential, and completes the reset. The low brushing area and the high brushing area refer to display sub-areas with relatively low refresh rate (for example, the refresh rate is less than or equal to 60HZ) and relatively high refresh rate (for example, the refresh rate is greater than 60HZ). Generally, the display area can be divided into multiple display sub-areas, and different refresh rates are used for refreshing different display sub-areas.

[0086] For example, for the N-type transistor in the pixel connected to the output signal terminal OUT_n, the potential of the enable signal provided by the enable line EN can be set to high potential 1 in the porch period (or when the display panel is powered on / power off), that is, the enable signal is high, so that the output control circuit 02 controls the potential of the output signal terminal OUT_n to be low potential 0, and realizes the reset of the display driving signal output to the N-type transistor. The P-type transistor is the same, and will not be described again.

[0087] It can be understood that the PMOS switch type pixel refers to a pixel in which the pixel circuit includes a plurality of P-type transistors; the NMOS switch type pixel refers to a pixel in which the pixel circuit includes a plurality of N-type transistors; and the CMOS switch type pixel refers to a pixel in which the pixel circuit includes at least one P-type transistor and at least one N-type transistor. MOS is an abbreviation of metal-oxide-semiconductor, that is, the transistors in the pixel circuit can be MOS transistors. In addition, the transistors can also be thin film transistors (TFTs). That is, the transistors in the pixel circuit can be MOS TFTs, the P-type transistors can be referred to as PMOS TFTs, and the N-type transistors can be referred to as NMOS TFTs. Of course, this is only illustrative.

[0088] Optionally, taking the CMOS switch type pixel as an example, FIG. 2 shows a circuit structure schematic diagram of a pixel provided in an embodiment of the present disclosure. As shown in FIG. 2, the pixel can include a pixel circuit and a light emitting element L1. The pixel circuit can include 8 transistors T1 to T8 and 1 capacitor Cst, that is, a circuit of 8T1C structure. The light emitting element L1 can be an organic light-emitting diode (OLED). The connection modes of the parts are as shown in FIG. 2, and will not be described again. In addition, the signal ends connected by the pixel include a gate signal end Gate, reset signal ends Reset1, Reset2 and Reset3, a data signal end Vdata, reset power lines V1, V2 and V3, a light emitting control end EM, a pull-up power line EVDD, and a pull-down power line ELVSS. Of course, in some other embodiments, the pixel circuit can also be of other structures, such as a 8T2C structure. The light emitting element L1 can also be of other types. For example, a micro light-emitting diode (Micro-LED), also referred to as MLED. Embodiments of the present disclosure do not limit this.

[0089] For the PMOS switch type pixel, the 8 transistors T1 to T8 can all be PMOS TFTs; for the NMOS switch type pixel, the 8 transistors T1 to T8 can all be NMOS TFTs; and for the CMOS switch type pixel, as shown in FIG. 2, T2, T3, T5 and T6 can be NMOS TFTs, and the other transistors except T2, T3, T5 and T6 can be PMOS TFTs. Correspondingly, taking the gate signal end Gate as an example, the gate signal end Gate connected by the transistor T2 is identified as Gate_N, and the gate signal end Gate connected by the transistor T1 is identified as Gate_P. “N” represents the relevant signal end connected by the NMOS TFT, “P” represents the relevant signal end connected by the PMOS TFT, and the identification of the other signal ends can be the same.

[0090] For example, for the PMOS switch type pixel, since the transistors T1 and T2 receiving the gate drive signal are both PMOS TFTs, the same or similar P-type gate drive signal can be used to drive the transistors T1 and T2 to work. For the NMOS switch type pixel, since the transistors T1 and T2 receiving the gate drive signal are both NMOS TFTs, the same or similar N-type gate drive signal can be used to drive the transistors T1 and T2 to work. For the CMOS switch type pixel shown in FIG. 2, since the transistor T1 receiving the gate drive signal is a PMOS TFT and the transistor T2 is an NMOS TFT, the opposite P-type gate drive signal and N-type gate drive signal are needed to drive the transistors T1 and T2 to work, respectively. As described above, the P-type gate drive signal refers to the gate drive signal with the first potential being the low potential 0 and the second potential being the high potential 1, and the N-type control signal refers to the gate drive signal with the first potential being the high potential 1 and the second potential being the low potential 0.

[0091] Optionally, taking the pixel circuit shown in FIG. 2 as an example, FIG. 3 shows a driving timing diagram of the pixel circuit. As shown in FIG. 3, the driving timing can include stages t1 to t5 executed in sequence.

[0092] In stage t1, the potential of the light-emitting control signal provided by the light-emitting control end EM_P can be the high potential, and the potential of the light-emitting control signal provided by the light-emitting control end EM_N can be the low potential. Correspondingly, the transistors T4 and T5 can be both cut off or turned off. Further, the pull-up power line EVDD and the pull-down power line EVSS can be disconnected, so that the light-emitting of the light-emitting element L1 is turned off.

[0093] In stage t2, the potential of the gate drive signal provided by the gate signal end Gate_N is the high potential, and the potential of the reset signal provided by the reset signal end Reset1 is the high potential. Correspondingly, the transistors T2 and T3 can be both turned on. Further, the reset power line V2 can output the reset power signal to the nodes P3 and P1 in sequence through the turned-on transistors T3 and T2, so as to reset the nodes P1 and P3 to the potential V20 of the reset power signal provided by the reset power line V2, so that the potential of the node P2 gradually becomes V20-Vth_Td, and Vth_Td refers to the threshold voltage of the transistor T8.

[0094] At stage t3, the potential of the reset signal provided by the reset signal terminal Reset1 becomes low, the potential of the gate drive signal provided by the gate signal terminal Gate_P is low, and the potential of the gate drive signal provided by the gate signal terminal Gate_N is high. Accordingly, the transistor T3 is turned off, and the transistors T1, T2 and T8 are turned on. Further, the data signal terminal Vdata transmits the data signal to the node P2 through the turned-on transistor T1, so as to charge the potential of the node P2 to the potential Vdata0 of the data signal, and charge the potentials of the node P3 and the node P1 to Vdata0+Vth_Td.

[0095] At stage t4, the potential of the gate drive signal provided by the gate signal terminal Gate_N becomes low, the potential of the reset signal provided by the reset signal terminal Reset2 (i.e., Reset_P) is low, and the potential of the reset signal provided by the reset signal terminal Reset3 (i.e., Reset_N) is high. Accordingly, the transistor T2 is turned off, and the transistors T6 and T7 are turned on. Further, the reset power line V3 outputs the reset power signal to the node P2 through the turned-on transistor T7, so as to reset the node P2 to the potential V30 of the reset power signal provided by the reset power line V3. If V30>Vdata0, the potential of the node P3 can become V30+Vth_Td, otherwise, the potential of the node P3 can remain Vdata0+Vth_Td. And the reset power line V1 outputs the reset power signal to the node P4 (i.e., the anode of the OLED) through the turned-on transistor T6, so as to reset the node P4 to the potential of the reset power signal provided by the reset power line V1.

[0096] At stage t5, the potential of the reset signal provided by the reset signal terminal Reset2 (i.e., Reset_P) becomes high, the potential of the reset signal provided by the reset signal terminal Reset3 (i.e., Reset_N) becomes low, the potential of the light emitting control signal provided by the light emitting control terminal EM_P becomes low, and the potential of the light emitting control signal provided by the light emitting control terminal EM_N can become high. Accordingly, the transistors T6 and T7 are turned off, and the transistors T4, T5 and T8 are turned on. Further, a path is formed between the pull-up power line EVDD and the pull-down power line EVSS, so that the light emitting element L1 can emit light. The light emitting current Id positively correlated with the light emitting brightness can be determined by the potential of the node P1 and the potential of the node P2. Wherein, the potential of the node P1 is Vdata0+Vth_Td, and the potential of the node P2 is the potential EVDD0 of the pull-up power signal provided by the pull-up power line EVDD. Accordingly, based on the current calculation formula, Id=K(Vdata0-EVDD0) can be determined. 2K is determined by the inherent characteristics of transistor T8, such as its width-to-length ratio W / L, capacitance Cox, and mobility μ. That is, the luminous current transmitted from the pixel circuit to the light-emitting element L1 can be independent of the threshold voltage Vth_Td of the driving transistor. Therefore, the drift of the threshold voltage Vth_Td of transistor T8 will not affect the luminous brightness of the light-emitting element L1, ensuring a good luminous effect for the light-emitting element L1.

[0097] It is understandable that, based on the above introduction to the driving principle, transistors T1 and T2 can be called data writing transistors, transistors T3, T6 and T7 can be called reset transistors, transistors T4 and T5 can be called light-emitting control transistors, and transistor T8 can be called driving transistors.

[0098] Based on this, as mentioned earlier, the output signal terminal OUT_n of the shift register unit can be connected to the gate signal terminal of the pixel circuit (e.g., Gate_N and / or Gate_P as shown in Figure 2) and used to provide the required gate drive signal to the connected gate signal terminal. For example, providing the inverted P-type gate drive signal / N-type gate drive signal shown in Figure 3 to drive transistors T1 and T2 in Figure 2 to operate reliably, respectively. Alternatively, the output signal terminal OUT_n of the shift register unit can be connected to the reset signal terminal of the pixel circuit (e.g., Reset_N and / or Reset_P as shown in Figure 2) and used to provide the required reset signal to the reset signal terminal, such as the reset signal shown in Figure 3. Or, the output signal terminal OUT_n of the shift register unit can be connected to the light emission control terminal of the pixel circuit (e.g., EM_N and EM_P as shown in Figure 2) and used to provide the required light emission control signal to the light emission control terminal, such as the light emission control signal shown in Figure 3. Of course, it is not limited to satisfying the timing shown in Figure 3.

[0099] Next, referring to the circuit layout diagram shown in Figure 4, it can be seen that in the layout, the output control circuit 02 and the input control circuit 01 are arranged sequentially along the first direction X1 and in the direction closer to the pixel. The first clock line CB, the second clock line CKn, and the enable line EN can be arranged sequentially along the first direction X1 and in the direction closer to the pixel, and the first clock line CB, the second clock line CKn, and the enable line EN all extend along the second direction Y1.

[0100] The second direction Y1 can intersect with the first direction X1. For example, the first direction X1 can be the row direction of pixels, the second direction Y1 can be the column direction of pixels, and the first direction X1 and the second direction Y1 can be perpendicular to each other.

[0101] It is understandable that the layout shown in Figure 4 not only facilitates the connection between signal lines and circuits, but also allows for a relatively concentrated and compact arrangement of various circuits without wasting space, thus facilitating the narrow bezel design of the display device.

[0102] In summary, the embodiments of this disclosure provide a shift register unit. In this shift register unit, the input control circuit can control the potential of the input node. The output control circuit can output a display drive signal to the pixel based on the potential of the input node and the enable signal provided by the enable line. Thus, by flexibly setting the enable signal and clock signal, the shift register unit can output signals matching the P-type transistors and / or N-type transistors in the pixel. Furthermore, since the output control circuit and the input control circuit are arranged sequentially along a first direction and in a direction close to the pixel, and the signal lines connecting the output control circuit and the input control circuit are arranged sequentially along the first direction and in a direction close to the pixel, and all signal lines extend along a second direction intersecting the first direction, it also facilitates the narrow bezel design of the display device.

[0103] Optionally, Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. As shown in Figure 5, the output control circuit 02 may include: a first output control sub-circuit 021 and a second output control sub-circuit 022.

[0104] The first output control sub-circuit 021 can be connected to the input node Q_n, the reset control line Trst, and the intermediate node Q1_n respectively, and can be used to control the potential of the intermediate node Q1_n based on the potential of the input node Q_n and the reset control signal provided by the reset control line Trst. That is, the first output control sub-circuit 021 can control the potential of the intermediate node Q1_n based on the potential of the input node Q_n and the reset control signal.

[0105] Understandably, in addition to setting the enable line EN, a reset control line Trst is also set. This allows for flexible configuration of the reset control signal provided by the reset signal line Trst during power-on, power-off, or Porch periods, controlling the output signal terminal OUT_n to an invalid potential, thus resetting the output display drive signal and improving the reliability of power-on / off. This also avoids drive anomalies during the switch between low and high refresh rates in partial refresh scenarios and further reduces the drive power consumption of the shift register unit.

[0106] The second output control sub-circuit 022 can be connected to the intermediate node Q1_n, the enable line EN, and the output signal terminal OUT_n, respectively, and can be used to control the potential of the output signal terminal OUT_n based on the potential of the intermediate node Q1_n and the enable signal. That is, the second output control sub-circuit 022 can control the potential of the output signal terminal OUT_n based on the potential of the intermediate node Q1_n and the enable signal. Furthermore, the switch control circuit 03 can be connected between the enable line EN and the second output control sub-circuit 022.

[0107] Based on Figure 5, and referring to the layout shown in Figure 4, it can be seen that the first output control sub-circuit 021 and the second output control sub-circuit 022 can be arranged sequentially along the second direction Y1 and away from the input control circuit 01. The reset control line Trst can be located on the side of the first clock line CB away from the second clock line CKn, and the reset control line Trst can extend along the second direction Y1. This facilitates the connection between signal lines and circuits and is beneficial for the narrow bezel design of the display device.

[0108] Optionally, referring further to FIG5, it can be seen that the shift register unit provided in the embodiments of this disclosure may further include: a switch control circuit 03, a latch circuit 04, and a drive enhancement circuit 05.

[0109] The switch control circuit 03 can be connected between the enable line EN and the output control circuit 02, and can also be connected to at least two first control terminals and at least two second control terminals respectively. It can be used to control the on / off state of the enable line EN and the output control circuit 02 in response to a first control signal provided by each first control terminal and a second control signal provided by each second control terminal. That is, the output control circuit 02 and the enable line EN can be indirectly connected through the switch control circuit 03, rather than directly.

[0110] For example, the switch control circuit 03 shown in Figure 5 is connected to two first control terminals Con11 and Con12, and to two second control terminals Con21 and Con22. When the potential of the first control signal provided by each first control terminal is the first potential, and the potential of the second control signal provided by each second control terminal is the first potential, the switch control circuit 03 connects the control enable line EN to the output control circuit 02, thereby transmitting the enable signal provided by the enable line EN to the output control circuit 02. This can also be considered as connecting the enable line EN to the output control circuit 02. Conversely, when the potential of the first control signal provided by each first control terminal is the second potential, and / or the potential of the second control signal provided by each second control terminal is the second potential, the switch control circuit 03 disconnects the control enable line EN from the output control circuit 02. This can also be considered as not connecting the enable line EN to the output control circuit 02.

[0111] Understandably, by connecting the enable line EN to the output control circuit 02, the output control circuit 02 can control the potential of the output signal terminal OUT_n based on the enable signal provided by the enable line EN and the potential of the input node Q_n, thereby outputting a display drive signal to the pixel. In this way, the output of the shift register unit can be controlled by flexibly setting the control signal to connect or not connect the enable line EN to the output control circuit 02, resulting in good drive flexibility. Furthermore, by resetting the output signal of some shift register units, compared to resetting the output signal of all shift register units, the operating power consumption of the shift register units can be reduced.

[0112] The latch circuit 04 can be connected to the third clock line CK, the fourth clock line CBn, the intermediate node Q1_n and the input node Q_n respectively. It can be used to control the on / off state of the intermediate node Q1_n and the input node Q_n in response to the third clock signal provided by the third clock line CK and the fourth clock signal provided by the fourth clock line CBn. It can also output the potential of the intermediate node Q1_n to the input node Q_n after inverting the potential.

[0113] For example, the latch circuit 04 can control the intermediate node Q1_n to conduct with the input node Q_n when the potential of the third clock signal is the first potential and the potential of the fourth clock signal is the first potential, and simultaneously output the potential of the intermediate node Q1_n after inverting it to the input node Q_n; and the latch circuit 04 can control the intermediate node Q1_n to disconnect from the input node Q_n when the potential of the third clock signal is the second potential or the potential of the fourth clock signal is the second potential. In this way, the potential of the input node Q_n can be the same as the potential of the intermediate node Q1_n, which achieves the purpose of latching the potential of the input node Q_n, or it can be said that the latch circuit 04 can store the potential of the input node Q_n to prevent leakage of the potential of the input node Q_n.

[0114] Optionally, in some embodiments, the first clock line CB and the fourth clock line CBn can be shared, and the second clock line CKn and the third clock line CK can be shared. For example, the first clock line CB and the fourth clock line CBn can both be the fourth clock line CBn, and the second clock line CKn and the third clock line CK can both be the second clock line CKn.

[0115] The drive enhancement circuit 05 can be connected between the output control circuit 02 and the output signal terminal OUT_n, and can be used to invert the potential of the output signal of the output control circuit 02 at least once before outputting it to the output signal terminal OUT_n. In this way, the driving capability of the shift register unit can be enhanced.

[0116] Optionally, based on this, referring further to Figure 4, the latch circuit 04 can be located within the area defined by the output control circuit 02, the input control circuit 01, and the switch control circuit 03, and the drive enhancement circuit 05 can be located at least on the side of the second output control sub-circuit 022 away from the first output control sub-circuit 021. The third clock line CK and the fourth clock line CBn can be located between the reset control line Trst and the enable line EN, and the third clock line CK and the fourth clock line CBn can be arranged sequentially along the first direction X1 and in the direction closer to the pixel, and the third clock line CK and the fourth clock line CBn can extend along the second direction Y1. This facilitates the connection between signal lines and circuits and is beneficial for the narrow bezel design of the display device.

[0117] Optionally, based on the structure shown in Figure 5, Figure 6 shows a schematic diagram of the circuit structure of a shift register unit. As shown in Figure 6, the input control circuit 01 may include: a first transmission gate Tg1. The first output control sub-circuit 021 may include: a NOR gate. The second output control sub-circuit 022 may include: a NAND gate. The latch circuit 04 may include: a first NOT gate INV1 and a second transmission gate Tg2. The switch control circuit 03 may include: two third transmission gates Tg3-1 and Tg3-2 connected in series. The drive enhancement circuit 05 may include: three second NOT gates INV2-1, INV2-2, and INV2-3 connected in series. Here, the NOT gate can also be called an inverter, and the transmission gate can also be called a transmission switch.

[0118] The first transmission gate Tg1 can be connected between the input signal terminal IN_n and the input node Q_n, and can also be connected to the first clock line CB and the second clock line CKn respectively. The two input terminals of the NOR gate can be connected to the reset control line Trst and the input node Q_n respectively, and the output terminal of the NOR gate can be connected to the intermediate node Q1_n. One input terminal of the NAND gate can be connected to the intermediate node Q1_n, and the other input terminal of the NAND gate can be connected to the enable line EN through two third transmission gates Tg3-1 and Tg3-2 connected in series. The output terminal of the NAND gate can be connected to the output signal terminal OUT_n through three second NOT gates INV2-1, INV2-2, and INV2-3 connected in series. Each third transmission gate (e.g., Tg3-1 or Tg3-2) can also be connected to a corresponding first control terminal and a corresponding second control terminal. The input of the first NOT gate INV1 can be connected to the intermediate node Q1_n. The output of the first NOT gate INV1 can be connected to the input node Q_n through the second transmission gate Tg2. The first transmission gate Tg1 can also be connected to the third clock line CK and the fourth clock line CBn respectively.

[0119] Additionally, the shift register unit may also include a voltage regulator capacitor C1 (not shown in Figure 6) connected between ground (GND) and another input terminal of the NAND gate. This voltage regulator capacitor C1 can be used to stabilize the voltage at the input terminal of the NAND gate so that the voltage remains stable even when there is no signal at the input terminal of the NAND gate.

[0120] That is, in some embodiments, referring to Figure 1, the switch control circuit 03 can be connected to two first control terminals Con11 and Con12, and two second control terminals Con21 and Con22, respectively. The two first control terminals Con11 and Con12 correspond one-to-one with the two second control terminals Con21 and Con22. Furthermore, one of the corresponding first control terminals Con11 and one of the corresponding second control terminals Con21 can be connected to the connection node (also called another intermediate node Q2_n-1) of the second transmission gate Tg2 and the first NOT gate INV1 in the preceding shift register unit (e.g., the previous stage shift register unit cascaded with the shift register unit), as well as the intermediate node Q1_n-1 described above. The other corresponding first control terminal Con12 and the other second control terminal Con22 can be connected to one intermediate node Q1_n and another intermediate node Q2_n of the shift register unit, respectively. Therefore, the signals at intermediate nodes Q1_n and Q2_n can be used as cascade signals to drive the cascaded shift register units.

[0121] Based on this, it can be seen that by controlling the switch control circuit 03 through the cascading signals of adjacent shift register units, the enable line EN can be connected step by step. This allows the shift register unit to reset only the GOA unit at the cascading start boundary, without resetting the GOA units that have started but have not completed shifting, until the shifting is complete. In this way, not only can the driving requirement of consistent pixel local refresh output pulse width be met, but also the power consumption is saved compared to resetting all outputs. For example, for the switch control circuit 03, the switch control circuit 03 only controls the enable line EN to be connected to the output control circuit 02 when the potentials of the intermediate node Q1_n-1 and the intermediate node Q2_n-1 controlled by the previous stage shift register unit are both valid potentials, and the potentials of the intermediate node Q1_n and the intermediate node Q2_n controlled by the current stage shift register unit are also valid potentials. Only then does the switch control circuit 03 control the enable line EN to be connected to the output control circuit 02, so that the output control circuit 02 still controls the potential of the output signal based on the enable signal provided by the enable line EN.

[0122] Optionally, for the output signal terminal OUT_n and the gate signal terminal Gate_N, in the scenario where a gate drive signal is provided to the gate signal terminal Gate_N, the output signal terminal OUT_n can be identified as GN_n, the intermediate node Q1_n can be identified as GNc_n, and the intermediate node Q2_n can be identified as GPc_n. Correspondingly, the intermediate node Q1_n of the previous stage shift register unit can be identified as GNc_n-1, and the intermediate node Q2_n of the previous stage shift register unit can be identified as GPc_n-1. Furthermore, the input signal terminal IN_n can be connected to the intermediate node GPc_n-1 of the cascaded previous stage shift register unit. Of course, the input signal terminal IN_1 of the first stage shift register unit needs to be connected to the enable signal line STV to receive the enable signal from the enable signal line STV.

[0123] Optionally, in some embodiments, the drive enhancement circuit 05 can invert the potential of the output signal of the output control circuit 02 an odd number of times before outputting it to the output signal terminal OUT_n. That is, the drive enhancement circuit 05 can control the potential of the output signal terminal OUT_n to be opposite to the potential of the output signal of the output control circuit 02.

[0124] Of course, in some other embodiments, the drive enhancement circuit 05 can also invert the potential of the output signal of the output control circuit 02 an even number of times before outputting it to the output signal terminal OUT_n. That is, the drive enhancement circuit 05 can control the potential of the output signal terminal OUT_n to be the same as the potential of the output signal of the output control circuit 02.

[0125] Alternatively, the output signal terminal OUT_n may include a first output signal terminal OUTN_n and a second output signal terminal OUTP_n, and the potentials of the first output signal terminal OUTN_n and the second output signal terminal OUTP_n may be opposite at the same time. For example, referring to Figure 2, both the first output signal terminal OUTN_n and the second output signal terminal OUTP_n can be connected to the gate signal terminal Gate_N connected to the N-type transistor T2 in the pixel, and used to provide gate drive signals with opposite potentials to the gate signal terminal Gate_N respectively. Of course, the gate drive signals with opposite potentials will not be provided to the N-type transistor T2 simultaneously. Alternatively, referring to Figure 2, the first output signal terminal OUTN_n and the second output signal terminal OUTP_n can be connected to the reset signal terminal Reset3 connected to the N-type transistor T6 and the reset signal terminal Reset2 connected to the P-type transistor T7 respectively, and used to provide reset signals with opposite potentials to the reset signal terminals Reset3 and Reset2 respectively.

[0126] Accordingly, the drive enhancement circuit 05 may include two drive enhancement sub-circuits. One drive enhancement sub-circuit may be connected between the output control circuit 02 and the first output signal terminal OUTN_n, and may be used to invert the potential of the output signal of the output control circuit 02 an even number of times before outputting it to the first output signal terminal OUTN_n. The other drive enhancement sub-circuit may be connected between the output control circuit 02 and the second output signal terminal OUTP_n, and may be used to invert the potential of the output signal of the output control circuit 02 an odd number of times before outputting it to the second output signal terminal OUTP_n. Optionally, in some embodiments, the two drive enhancement sub-circuits may share at least one second NOT gate INV2.

[0127] Understandably, by configuring the drive enhancement circuit 05 to include multiple series-connected second NOT gates INV2, the driving capability of the output signal at the output signal terminal OUT_n can be amplified step by step, thus significantly enhancing the driving capability. Correspondingly, the second NOT gate INV2 can also be called an amplifier (AMP).

[0128] It can also be understood that the logic principle of a NOR gate is: all 0s output 1, any 1 outputs 0; that is, when all received signals are at a low potential (0), the output signal can be controlled to be at a high potential (1); otherwise, as long as any received signal is at a high potential (1), the output signal is controlled to be at a low potential (0). The logic principle of a NAND gate is: all 1s output 0, any 0 outputs 1; that is, when all received signals are at a high potential (1), the output signal can be controlled to be at a low potential (0); otherwise, as long as any received signal is at a low potential (0), the output signal is controlled to be at a high potential (1). Based on this, we can conclude that:

[0129] The first output control sub-circuit 021, including the NOR gate, can control the potential of the intermediate node Q1_n to be low (0) when the potential of the input node Q_n is high (1) and / or the potential of the reset control signal provided by the reset control line Trst is high (1); and the first output control sub-circuit 021, including the NOR gate, can control the potential of the intermediate node Q1_n to be high (1) when the potential of the input node Q_n is low (0) and the potential of the reset control signal provided by the reset control line Trst is low (0).

[0130] Furthermore, the second output control sub-circuit 022, which includes a NAND gate, can control the output signal terminal OUT_n to be at a low potential 0 when the potential of the intermediate node Q1_n is high potential 1 and the potential of the enable signal is also high potential 1; and the second output control sub-circuit 022, which includes a NAND gate, can control the output signal terminal OUT_n to be at a high potential 1 when the potential of the intermediate node Q1_n is low potential 0 and / or the potential of the enable signal is also low potential 0.

[0131] Furthermore, based on Figure 6 and referring to Figure 7, it can be seen that the NOR gate, NAND gate, and the first second NOT gate INV2-1 can be arranged sequentially along the second direction Y1. The first transmission gate Tg1, the second transmission gate Tg2, the first NOT gate INV1, the second third transmission gate Tg3-2, and the second second NOT gate INV2-2 can be arranged sequentially along the second direction Y1. The first third transmission gate Tg3-1 can be located on the side of the first NOT gate INV1 away from the second third transmission gate Tg3-2. The voltage regulator C1 can be located between the NAND gate and the second third transmission gate Tg3-2. The first second NOT gate INV2-1 to the third second NOT gate INV2-3 can be arranged sequentially along the first direction X1 and in the direction closer to the pixel. It is understood that the shift register unit described in the embodiments of this disclosure can be located on one side of the substrate, that is, each circuit device can be disposed on the substrate.

[0132] Optionally, the dimensions of the first second NOT gate INV2-1 to the third second NOT gate INV2-3 can be increased sequentially. Correspondingly, referring to Figure 7, it can also be seen that the orthographic projection length of the third second NOT gate INV2-3 on the substrate can include the total orthographic projection length of the other gate circuits on the substrate, excluding the third second NOT gate INV2-3. The length direction can be parallel to the second direction Y1. These other gate circuits can include, for example, NOR gates, NAND gates, and the first second NOT gate INV2-1 arranged sequentially along the second direction Y1.

[0133] It is understood that, in conjunction with Figures 4 and 7, the arrangement provided by the embodiments of this disclosure can make good use of limited space to centrally set up multiple circuit components, thereby effectively reducing the width of the frame and thus improving the driving capability and stability of the shift register unit.

[0134] It can also be understood, as shown in Figure 6, that the first third transmission gate Tg3-1 can refer to the third transmission gate Tg3 directly connected to the enable line EN; the second third transmission gate Tg3-2 can refer to the third transmission gate Tg3 directly connected to the NAND gate NAND. The first second NOT gate INV2-1 can refer to the second NOT gate INV2 directly connected to the NAND gate NAND; the second second NOT gate INV2-1 can refer to the second NOT gate INV2 connected in series between the first second NOT gate INV2-1 and the third second NOT gate INV2-3; the third second NOT gate INV2-3 can refer to the second NOT gate INV2 directly connected to the output signal terminal OUT_n. Correspondingly, it can be seen that the second third transmission gate Tg3-2 in Figure 6 can refer to the last third transmission gate Tg3, and the third second NOT gate INV2-3 can refer to the last second NOT gate INV2.

[0135] Optionally, based on Figure 6, Figure 8 shows a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this disclosure. Referring to Figure 8, it can be seen that the NOR gate, NAND gate, first NOT gate INV1, and each second NOT gate INV2 can also be connected to the first power line VGH and the second power line VGL respectively, and can be used to operate based on the first power signal provided by the first power line VGH and the second power signal provided by the second power line VGL. Furthermore, the potential of the first power signal can be greater than the potential of the second power signal. Figure 8 also schematically shows the voltage regulating capacitor C1.

[0136] Optionally, the first power line VGH and the second power line VGL are located at least on both sides of the enable line EN and the reset control line Trst in the first direction X1, and the first power line VGH and the second power line VGL can both extend along the second direction Y1.

[0137] For example, referring to Figure 4, in the first direction X1, for the NOR gate, NAND gate, and the first second NOT gate INV2-1, the first power supply line VGH and the second power supply line VGL can be shared and can be located on the left and right sides of the reset control line Trst. For the second second NOT gate INV2-2, the first power supply line VGH and the second power supply line VGL can be located on the left and right sides of the enable line EN. That is, the first power supply line VGH and the second power supply line VGL can be interspersed between the reset control line Trst and the enable line EN. For the third second NOT gate INV2-3, the first power supply line VGH and the second power supply line VGL can be adjacent to each other.

[0138] Optionally, the width of the first power line VGH and the width of the second power line VGL can both be greater than the width of the reset control line Trst, and both can be greater than the width of the enable line EN. Alternatively, they can also be greater than the width of the enable signal line STV connected to the first-stage shift register unit. Optionally, the width of the first power line VGH connected to the third second NOT gate INV2-3 can be greater than the width of the first power line VGH connected to other gate circuits, and the width of the second power line VGL connected to the third second NOT gate INV2-3 can be greater than the width of the second power line VGL connected to other gate circuits. Other gate circuits may include at least one of: NOR gate, NAND gate, first NOT gate INV1, second second NOT gate INV2-2, and first first NOT gate INV2-1. The width direction can be parallel to the first direction X1.

[0139] That is, in the embodiments of this disclosure, the widths of the reset control line Trst, the enable signal line EN, and the power-on signal line STV can all be smaller than the width of the first power line VGH and smaller than the width of the second power line VGL. Optionally, in some embodiments, the widths of the reset control line Trst, the enable signal line EN, and the power-on signal line STV can also be similar or equal.

[0140] For example, the width of the reset control line Trst can be 3 to 10 micrometers (μm). For instance, the width of the reset control line Trst can be 4 μm. The widths of the first power line VGH and the second power line VGL are generally 5 to 30 μm. For example, the widths of the first power line VGH and the second power line VGL connected by the first second NOT gate INV2-1 and the second second NOT gate INV2-2 can both be 10 μm, while the widths of the first power line VGH and the second power line VGL connected by the third second NOT gate INV2-3 can be 30 μm.

[0141] Understandably, by making the power lines (including the first power line VGH and the second power line VGL) wider, the driving capability of the gate circuit can be enhanced. Furthermore, since the last second NOT gate INV2 is directly connected to the pixel via its output signal terminal OUT_n, making the power line connected to the last second NOT gate INV2 the widest possible enhances its driving capability. Also, by separating the power line connected to the last second NOT gate INV2 from those connected to other second NOT gates INV2, the problem of abnormal output caused by a negatively biased threshold voltage Vth of the N-type transistor can be resolved. For example, when the threshold voltage Vth of the N-type transistor is negatively biased, the normal output of the N-type transistor can be ensured by individually adjusting the power signal provided by the second power line VGL connected to the last second NOT gate INV2.

[0142] To distinguish them, the first power line VGH and the second power line VGL connected to other gate circuits in the figure are labeled as VGH1 and VGL1, respectively, while the first power line VGH and the second power line VGL connected to the last second NOT gate INV2 (that is, the third second NOT gate INV2-3) are labeled as VGH2 and VGL2, respectively.

[0143] Optionally, in some embodiments, among the plurality of second NOT gates INV2, the potential of the first power signal provided by the first power line VGH2 connected to the last second NOT gate INV2 can be greater than or equal to the potential of the first power signal provided by the first power line VGH1 connected to the other second NOT gates INV2. And / or, the potential of the second power signal provided by the second power line VGL2 connected to the last second NOT gate INV2 can be less than or equal to the potential of the second power signal provided by the second power line VGL2 connected to the other second NOT gates INV2. In this way, the charging and discharging speed of the second NOT gate INV2 directly connected to the output signal terminal OUT_n can be accelerated, thereby further improving the driving capability of the shift register unit, and reducing leakage current and saving power consumption.

[0144] That is, in one embodiment, a single VGH and a single VGL power supply can be used, meaning that any NOT gate in the shift register unit is connected to the same first power line VGH and second power line VGL. Alternatively, in another embodiment, a dual VGH and dual VGL power supply can be used. Of course, it is not limited to a dual VGH and dual VGL power supply.

[0145] Optionally, the first clock line CB, the second clock line CKn, the enable line EN, the reset control line Trst, the third clock line CK, and the fourth clock line CBn can all be located on the same side of the second output control sub-circuit 022 away from the first output control sub-circuit 021, and can all extend along the second direction Y1. That is, referring to Figure 7, the signal lines connected to the shift register unit can all be located above the overall circuit structure.

[0146] Optionally, in some embodiments, the first clock line CB, the second clock line CKn, the enable line EN, the reset control line Trst, the third clock line CK, and the fourth clock line CBn can be arranged at equal intervals in the first direction X1. That is, the spacing between any two adjacent signal lines can be a fixed spacing. For example, this fixed spacing can be greater than or equal to 3μm.

[0147] Optionally, based on the foregoing description, the shift register unit provided in this embodiment can actually be divided into three modules: an input shift module, a transmission and control module, and a drive enhancement module. The shift register unit may also include a voltage regulator capacitor C1. The input shift module may include a first transmission gate Tg1, a NOR gate, a second transmission gate Tg2, and a first NOT gate INV1. The transmission and control module may include a NAND gate and two third transmission gates Tg3-1 and Tg3-2. The drive enhancement module may include three second NOT gates INV2-1, INV2-2, and INV2-3.

[0148] Furthermore, as can be seen from Figures 4 and 7, relative to the area where the pixel is located, the input shifting module can be located in the upper left part of the layout, the part of the transmission and control module except for the third transmission gate Tg3-1 can be located in the lower left part of the layout, the first second NOT gate INV2-1 and the second second NOT gate INV2-2 in the drive enhancement module can be arranged vertically or horizontally, and the third second NOT gate INV2-3 can be located at the rightmost end of the layout.

[0149] In some embodiments, in the input shift module, the NOR gate can be located at the leftmost end, and the first transmission gate Tg1, the second transmission gate Tg2, and the first NOT gate INV1 can be located to the right of the NOR gate and arranged sequentially from top to bottom. In the transmission and control module, the first third transmission gate Tg3-1 can be located above the layout to facilitate connection with the upper-level transmission signal GPc_n-1 and GNc_n-1 terminals, the NAND gate can be located below the NOR gate, and the second third transmission gate Tg3-2 can be located between the first third transmission gate Tg3-1 and the NAND gate to facilitate signal transmission. In the drive enhancement circuit, the first second NOT gate INV2-1 can be located between the NAND gate and the second second NOT gate INV2-2, and the first second NOT gate INV2-1, the second second NOT gate INV2-2, and the third second NOT gate INV2-3 can be arranged sequentially from left to right. The voltage regulator capacitor C1 can be located around the NAND gate, such as on the right side of the NAND gate, in order to stabilize the potential at the input terminal of the NAND gate.

[0150] Optionally, referring to Figure 8, the first transmission gate Tg1 may include a first P-type transistor Tp_1 and a first N-type transistor Tn_1.

[0151] The gates of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can be connected to the first clock line CB and the second clock line CKn, respectively. The first terminals of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can both be connected to the input signal terminal IN_n. The second terminals of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can both be connected to the input node Q_n.

[0152] Optionally, referring to Figure 8, the NOR gate may include: a second P-type transistor Tp_2, a second N-type transistor Tn_2, a third P-type transistor Tp_3, and a third N-type transistor Tn_3.

[0153] Specifically, the gates of the second P-type transistor Tp_2 and the third N-type transistor Tn_3 can both be connected to the reset control line Trst. The first terminal of the second P-type transistor Tp_2 can be connected to the first power supply line VGH1. The second terminal of the second P-type transistor Tp_2 can be connected to the first terminal of the third P-type transistor Tp_3. The second terminals of the third P-type transistor Tp_3, the second N-type transistor Tn_2, and the third N-type transistor Tn_3 can all be connected to the intermediate node Q1_n. The first terminals of the second N-type transistor Tn_2 and the third N-type transistor Tn_3 can both be connected to the second power supply line VGL1. The gates of the third P-type transistor Tp_3 and the second N-type transistor Tn_2 can both be connected to the input node Q_n.

[0154] Optionally, referring to Figure 8, the first NOT gate INV1 may include a fourth P-type transistor Tp_4 and a fourth N-type transistor Tn_4, where the fourth N-type transistor Tn_4 can be a dual-gate transistor. The second transmission gate Tg2 may include a fifth P-type transistor Tp_5 and a fifth N-type transistor Tn_5. It is understood that by setting the fourth N-type transistor Tn_4 as a dual-gate transistor, leakage current during the output hold phase can be reduced, thereby reducing the power consumption of the shift register unit. Of course, other transistors can also be similarly set as dual-gate transistors.

[0155] Specifically, the gates of the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can both be connected to the intermediate node Q1_n. The first terminals of the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can be connected to the first power line VGH1 and the second power line VGL1, respectively. The second terminals of the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can both be connected to the first terminals of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5, respectively. The gates of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can both be connected to the third clock line CK and the fourth clock line CBn, respectively. The second terminals of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can both be connected to the input node Q_n.

[0156] Optionally, referring to Figure 8, the NAND gate may include: a sixth P-type transistor Tp_6, a sixth N-type transistor Tn_6, a seventh P-type transistor Tp_7, and a seventh N-type transistor Tn_7. The second third transmission gate Tg3-2 may include: an eighth P-type transistor Tp_8 and an eighth N-type transistor Tn_8. The first third transmission gate Tg3-1 may include: a ninth P-type transistor Tp_9 and a ninth N-type transistor Tn_9. The first second NOT gate INV2-1 may include: a tenth P-type transistor Tp_10 and a tenth N-type transistor Tn_10. The second second NOT gate INV2-2 may include: an eleventh P-type transistor Tp_11 and an eleventh N-type transistor Tn_11. The third second NOT gate INV2-3 may include: a twelfth P-type transistor Tp_12 and a twelfth N-type transistor Tn_12.

[0157] Specifically, the gates of the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6 can both be connected to the intermediate node Q1_n; the gates of the seventh P-type transistor Tp_7 and the seventh N-type transistor Tn_7 can both be connected to the first node N1; the second terminals of the sixth P-type transistor Tp_6, the seventh P-type transistor Tp_7, and the sixth N-type transistor Tn_6 can all be connected to the second node N2; the first terminal of the sixth N-type transistor Tn_6 can be connected to the second terminal of the seventh N-type transistor Tn_7; and the gates of the eighth P-type transistor Tp_8 and the eighth N-type transistor Tn_8 can each be connected to a corresponding first control terminal Con11 (i.e., GNc_n) and a second control terminal Con21. (i.e., GPc_n) is connected. The gates of the ninth P-type transistor Tp_9 and the ninth N-type transistor Tn_9 can be connected to another first control terminal Con12 (i.e., GPc_n-1) and another second control terminal Con22 (i.e., GNc_n-1), respectively. The first terminals of the ninth P-type transistor Tp_9 and the ninth N-type transistor Tn_9 can both be connected to the enable line EN. The second terminals of the ninth P-type transistor Tp_9 and the ninth N-type transistor Tn_9 can both be connected to the first terminals of the eighth P-type transistor Tp_8 and the eighth N-type transistor Tn_8. The second terminals of the eighth P-type transistor Tp_8 and the eighth N-type transistor Tn_8 can both be connected to the first node N1.

[0158] The gates of the tenth P-type transistor Tp_10 and the tenth N-type transistor Tn_10 can both be connected to the second node N2. The gates of the eleventh P-type transistor Tp_11 and the eleventh N-type transistor Tn_11 can both be connected to the second terminals of the tenth P-type transistor Tp_10 and the eleventh N-type transistor Tn_10. The gates of the twelfth P-type transistor Tp_12 and the twelfth N-type transistor Tn_12 can both be connected to the second terminals of the eleventh P-type transistor Tp_11 and the eleventh N-type transistor Tn_11. The twelfth P-type transistor... The second terminal of the body transistor Tp_12 and the second terminal of the twelfth N-type transistor Tn_12 can both be connected to the output signal terminal OUT_n. The first terminals of the sixth P-type transistor Tp_6, the seventh P-type transistor Tp_7, and the tenth P-type transistor Tp_10 to the twelfth P-type transistor Tp_12 can all be connected to the first power supply line VGH. The first terminals of the seventh N-type transistor Tn_7 and the tenth N-type transistor Tn_10 to the twelfth N-type transistor Tn_12 can all be connected to the second power supply line VGL.

[0159] Specifically, the first terminals of the tenth P-type transistor Tp_10 and the eleventh P-type transistor Tp_11 are connected to the first power supply line VGH1, and the first terminal of the twelfth P-type transistor Tp_12 is connected to the first power supply line VGH2. The first terminals of the tenth N-type transistor Tn_10 and the eleventh N-type transistor Tn_11 are connected to the second power supply line VGL1, and the first terminal of the twelfth N-type transistor Tn_12 is connected to the second power supply line VGL2.

[0160] That is, the shift register unit provided in some embodiments of this disclosure may include 24 TFTs, namely 12 PMOS TFTs and 12 NMOS TFTs. Of course, it is not limited to including only these 24 TFTs, that is, the shift register unit provided in this disclosure can be formed by combining and reducing basic modules. For example, in some embodiments, the shift register unit may also include other gate circuits (e.g., NOT gates) connected between the intermediate node Q1_n and the second output control sub-circuit 022.

[0161] Optionally, taking the structure shown in Figure 8 as an example, Figure 9 shows a layout schematic of a shift register unit. Combining Figures 8 and 9, it can be seen that the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can be arranged sequentially along the first direction X1 and along the direction closest to the pixel.

[0162] The third P-type transistor Tp_3 and the second P-type transistor Tp_2 can be arranged and connected in series along the second direction Y1 and along the direction close to the NAND gate. The second N-type transistor Tn_2 can be located on the side of the third P-type transistor Tp_3 away from the second P-type transistor Tp_2, and the second N-type transistor Tn_2 can be closer to the pixel relative to the third P-type transistor Tp_3. The third N-type transistor Tn_3 can be located on the side of the second P-type transistor Tp_2 away from the third P-type transistor Tp_3, and the third N-type transistor Tn_3 can be closer to the pixel relative to the second P-type transistor Tp_2.

[0163] The fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can be arranged sequentially along the first direction X1 and along the direction closer to the pixel. The fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can be arranged sequentially along the first direction X1 and along the direction closer to the pixel. The fifth P-type transistor Tp_5 and the fourth N-type transistor Tn_4 can be arranged sequentially along the second direction Y1 and along the direction away from the first transmission gate Tg1. The fifth N-type transistor Tn_5 and the fourth P-type transistor Tp_4 can be arranged sequentially along the second direction Y1 and along the direction away from the first transmission gate Tg1.

[0164] The seventh N-type transistor Tn_7, the sixth N-type transistor Tn_6, the sixth P-type transistor Tp_6, and the seventh P-type transistor Tp_7 can be arranged sequentially along the second direction Y1 and in a direction close to the tenth P-type transistor Tp_10. The eighth N-type transistor Tn_8 and the eighth P-type transistor Tp_8 can be arranged sequentially along the first direction X1 and in a direction close to the pixel. The ninth P-type transistor Tp_9 and the ninth N-type transistor Tn_9 can be arranged along the second direction Y1 and in a direction close to the eighth P-type transistor Tp_8. The transistors are arranged in the following directions: the tenth P-type transistor Tp_10 and the tenth N-type transistor Tn_10 can be arranged in the first direction X1 and in the direction closer to the pixel; the eleventh N-type transistor Tn_11 and the eleventh P-type transistor Tp_11 can be arranged in the second direction Y1 and in the direction away from the eighth P-type transistor Tp_8; and the twelfth P-type transistor Tp_12 and the twelfth N-type transistor Tn_12 can be arranged in the second direction Y1 and in the direction closer to the eleventh P-type transistor Tp_11.

[0165] That is, referring to Figure 9, in this embodiment of the NOR gate, the four TFTs can be arranged vertically, and two of the four TFTs, P-type TFTs, can be connected in series, while the two N-type TFTs can be located on the upper and lower sides of the two P-type TFTs. Based on the vertical arrangement of the first transmission gate Tg1 and the second transmission gate Tg2, TFTs of the same type (i.e., P-type or N-type) can be located on the same side to facilitate connection between TFTs. The clock line can be located near the top of the P-type and N-type TFTs for easy connection. The first NOT gate INV1 is located in the middle of the layout, facilitating connection with the preceding module and transmission to the next level. The N-type and P-type TFTs can be arranged horizontally, and as mentioned above, the N-type TFT can be a dual-gate design to reduce leakage current, thereby reducing the power consumption of the shift register unit. The two TFTs in the first third transmission gate Tg3-1 can be arranged vertically, with the P-type TFT on top and the N-type TFT on the bottom. The enable line EN is located on top, and its width is generally 3-10 μm. The second third transmission gate Tg3-2 is located below the first NOT gate INV1. Its P-type TFTs and N-type TFTs can be arranged in parallel, with the P-type TFT on the right and the N-type TFT on the left. The gates of the P-type and N-type TFTs can be led downwards using gate metal layers for cascading. In the NAND gate, two N-type TFTs can be arranged in a straight line, and two P-type TFTs can be placed horizontally, facilitating signal connection and transmission. In the first second NOT gate INV2-1, the N-type and P-type TFTs can be placed horizontally, and their gate holes can be arranged in a straight line. In the second second NOT gate INV2-2 and the third second NOT gate INV2-3, the N-type and P-type TFTs in each second NOT gate INV2 can be placed vertically as shown in Figure 9, or horizontally. Alternatively, one second NOT gate INV2 can have its N-type and P-type TFTs placed horizontally, while the other can have their N-type and P-type TFTs placed vertically, depending on the layout space.

[0166] Furthermore, as shown in Figure 9, the sizes of the transistors in the first second NOT gate INV2-1 to the third second NOT gate INV2-3 can be increased sequentially. That is, the sizes of the first second NOT gate INV2-1 to the third second NOT gate INV2-3 described above can be increased sequentially. Here, transistors can refer to P-type transistors and / or N-type transistors.

[0167] Understandably, the channel width of a transistor can characterize its size. Taking an N-type transistor as an example, the channel width of the transistor in the first NOT gate INV2-1 can be 2 to 15 μm; for instance, the channel width of the transistor in the first NOT gate INV2-1 can be 8 μm. The channel width of the transistor in the second NOT gate INV2-2 can be approximately 1.5 to 10 times that of the transistor in the first NOT gate INV2-1; for instance, the channel width of the transistor in the second NOT gate INV2-2 can be 30 μm. The channel width of the transistor in the third NOT gate INV2-3 can be the largest and can be determined by the pixel load it is connected to. For instance, the channel width of the transistor in the third NOT gate INV2-3 can be 100 μm to 300 μm.

[0168] Of course, the N-type and P-type transistors in each second NOT gate INV2 can have the same or different dimensions, which can be determined by the mobility. For example, taking the third second NOT gate INV2-3 as an example, the mobility of its P-type transistor (i.e., the twelfth P-type transistor Tp_12) can be 1 / 3 of the mobility of the N-type transistor (i.e., the twelfth N-type transistor Tn_12), and correspondingly, the channel width of its P-type transistor can be 1 / 3 of the channel width of its N-type transistor.

[0169] Furthermore, the transistors in the first transmission gate Tg1, the NOR gate, the NAND gate, the first NOT gate INV1, the second transmission gate Tg2, and each of the third transmission gates Tg3 can be smaller than the transistors in any of the second NOT gates INV2. That is, except for the first to third second NOT gates INV2-3, the transistors in other gate circuits can all be relatively small. For example, the transistors in other gate circuits can be equivalent to the size of a switching transistor, and the channel width can be between 2 and 10 μm.

[0170] It is understood that the layouts shown in Figures 7 and 9 are merely illustrative, and any adjustments made based on them to facilitate narrow bezel design are applicable to the embodiments disclosed herein.

[0171] Optionally, based on Figure 9, Figures 10 to 17 show schematic diagrams of different film layer structures for a shift register unit. Referring to Figures 9 to 17, it can be seen that the transistor in the shift register unit provided in this embodiment may include: a first active layer Poly, a first gate metal layer GATE1, a second gate metal layer GATE2, a second active layer IGZO, a third gate metal layer GATE3, a first source / drain metal layer SD1, and a second source / drain metal layer SD2, stacked sequentially. These films can all be located on one side of the substrate.

[0172] The first active layer, Poly, can be used as the active layer for P-type transistors in the shift register unit, and the second active layer, IGZO, can be used as the active layer for N-type transistors in the shift register unit.

[0173] It is understood that "Poly" can refer to an active layer formed using polycrystalline silicon, and "IGZO" refers to an active layer formed using indium gallium zinc oxide. Of course, in some other embodiments, other materials can be used to form the first active layer, and other materials can also be used to form the second active layer.

[0174] It is also understandable that, taking the third second NOT gate INV2-3 as an example, since the size of the P-type transistor is generally smaller than that of the N-type transistor, it can be seen from Figures 10 and 13 that in the third second NOT gate INV2-3, the size of the active layer (i.e., the first active layer Poly) of the P-type transistor (i.e., the twelfth P-type transistor Tp_12) is smaller than the size of the active layer (i.e., the second active layer IGZO) of the N-type transistor (i.e., the twelfth N-type transistor Tn_12). Here, "size" can refer to the area of ​​the active layer projected onto the substrate. The sizes of the active layers of the P-type transistors and N-type transistors in other gate circuits are similar and will not be elaborated further.

[0175] Optionally, a first interlayer dielectric layer (ILD) and a second interlayer dielectric layer (EBB) may be further included between the third gate metal layer (GATE3) and the first source / drain metal layer (SD1). The first interlayer dielectric layer (ILD) may have multiple vias (K1) for overlapping of the films located on both sides of the ILD. The second interlayer dielectric layer (EBB) may have multiple vias (K2) for overlapping of the films located on both sides of the EBB. It is understood that the vias (K1) in the first interlayer dielectric layer (ILD) can be used for overlapping of the films between P-type transistors. The vias (K2) in the second interlayer dielectric layer (EBB) can be used for overlapping of the films between N-type transistors. Furthermore, a passivation layer (PVX) and a planarization layer (PLN) may be sequentially stacked between the first source / drain metal layer (SD1) and the second source / drain metal layer (SD2). The passivation layer (PVX) and the planarization layer (PLN) may have multiple third vias (K3) for overlapping of the films located on both sides of the passivation layer (PVX) and the planarization layer (PLN). Correspondingly, vias K1, K2, and K3 can also be called connection vias.

[0176] Based on this, it can be understood that the gate via in the first second NOT gate INV2-1 described above can refer to: the via between the first gate metal layer GATE1 and the source / drain metal layer SD; the via between the second gate metal layer GATE2 and the source / drain metal layer SD; and the via between the third gate metal layer GATE3 and the source / drain metal layer SD. Here, the source / drain metal layer can be, for example, the first source / drain metal layer.

[0177] Optionally, in this embodiment of the disclosure, each connection via can be located away from the second source / drain metal layer SD2, thereby reducing the parasitic capacitance formed between the second source / drain metal layer SD2 and other metal layers (e.g., the first source / drain metal layer). Furthermore, each connection via can be staggered, meaning their orthogonal projections on the substrate do not overlap.

[0178] Optionally, in some embodiments, as shown in FIG18, at least a portion of the first source / drain metal layer SD1 may be reused with at least one of the first active layer Poly, the first gate metal layer GATE1, the second gate metal layer GATE2, and the second active layer IGZO to reduce the overlap area between the first source / drain metal layer SD1 and the second source / drain metal layer SD2.

[0179] That is, the first source-drain metal layer SD1 can be replaced by any layer on the side of the first source-drain metal layer SD1 away from the second source-drain metal layer SD2, thereby reducing the overlap area between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, and thus reducing the parasitic capacitance formed between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, which is beneficial to further reduce the operating power consumption of the shift register unit. Of course, in some other embodiments, the same purpose can also be achieved by reducing some of the redundant vias and redundant first source-drain metal layers SD1.

[0180] Alternatively, based on Figure 18, Figures 19 to 26 show different schematic diagrams of the film layer structure of the shift register unit. Comparing Figures 10 and 19 with Figures 9 and 18, it can be seen that at position 1, the via of the first active layer Poly can be moved up and down, reusing the first active layer Poly as the first source / drain metal layer SD1 at that position. Comparing Figures 13 and 22 with Figures 9 and 18, it can be seen that at positions 2 and 5, the second active layer IGZO can be reused as the first source / drain metal layer SD1 at that position. Again, comparing Figures 10 and 19, it can be seen that at position 3, the first active layer Poly can also be reused as the first source / drain metal layer SD1 at that position. Furthermore, at position 4, the redundant via of the first active layer Poly / first source / drain metal layer SD1 can be removed. All of the above examples can reduce the overlap area of ​​the first source / drain metal layer SD1 and the second source / drain metal layer SD2, thereby reducing parasitic capacitance and power consumption.

[0181] It is understandable that, referring to Figure 8, positions 1 and 3 could refer to the connection nodes of the first third transmission gate Tg3-1 and the second third transmission gate Tg3-2. Positions 2 and 5 could refer to the connection nodes of the NOR gate and the NAND gate, i.e., the intermediate node Q1_n. Position 4 could refer to the connection node of the third P-type transistor Tp_3 and the second P-type transistor Tp_2 in the NOR gate.

[0182] It can also be understood that, compared to the structure shown in Figure 9, the structure shown in Figure 18, at positions 1 and 3, can be considered as increasing the area of ​​the first active layer Poly to reduce the area of ​​the first source / drain metal layer SD1. At positions 2 and 5, it can be considered as increasing the area of ​​the second active layer IGZO to reduce the area of ​​the first source / drain metal layer SD1. Of course, the above methods are illustrative; in some embodiments, other film layers can be reused as the first source / drain metal layer SD1 to reduce the overlap area between the first source / drain metal layer SD1 and the second source / drain metal layer SD2.

[0183] Optionally, based on the transistor arrangement of the embodiments of this disclosure, and referring to Figures 9 and 10, it can also be seen that: the first active layer Poly of the second P-type transistor Tp_2 and the third P-type transistor Tp_3 can be a whole (i.e., they can be shared); the first active layer Poly of the first P-type transistor Tp_1 and the fifth P-type transistor Tp_5 can be shared. Furthermore, referring to Figures 9 and 13, it can be seen that the second active layer IGZO of the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5 can be shared; the second active layer IGZO of the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the seventh N-type transistor Tn_7 can be shared.

[0184] Optionally, based on the transistor arrangement of this embodiment, an active layer is reused as the first source / drain metal layer SD1. Referring to Figures 18 and 19, it can be seen that: besides the first active layer Poly being shared by the second P-type transistor Tp_2 and the third P-type transistor Tp_3, and the first active layer Poly being shared by the first P-type transistor Tp_1 and the fifth P-type transistor Tp_5, the first active layer Poly of the eighth P-type transistor Tp_8 and the ninth P-type transistor Tp_9 can also be shared. Furthermore, referring to Figures 18 and 22, it can be seen that: besides the second active layer IGZO being shared by the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5; and the second active layer IGZO being shared by the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the seventh N-type transistor Tn_7, the second active layer IGZO of the second N-type transistor Tn_2 and the third N-type transistor Tn_3 can also be shared. That is, the second active layer IGZO of the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the seventh N-type transistor Tn_7 can be a whole.

[0185] Understandably, by sharing an active layer, the structure can be simplified and costs can be saved, while also facilitating narrow bezel design.

[0186] It should be noted that the layouts shown in Figures 9 to 17 are layouts of two adjacent shift register units (e.g., the nth-level shift register unit GOAn and the (n+1)th-level shift register unit GOAn+1). The layouts shown in Figures 10 to 26 are layouts of a single shift register unit (e.g., the nth-level shift register unit GOAn).

[0187] Based on the above description, the shift register unit provided in this embodiment can be a CMOS NGate GOA circuit. NGate refers to the gate signal terminal connected to the N-type transistor in the pixel, and CMOS can refer to a circuit capable of outputting the required display driving signals to both the P-type and N-type transistors in the pixel. The N-type transistors in the shift register unit can be responsible for low-level output, and the P-type transistors can be responsible for high-level output. Furthermore, the CMOS NGate GOA has a compact and concentrated layout, which helps to reduce the bezel width and improve driving capability and circuit stability. Also, the width of the display driving signal output by the CMOS NGate GOA through the output signal terminal OUT_n is adjustable. Specifically, when the potentials of the signals provided by GPc_n-1, GNc_n-1, GPc_n, and GNc_n are simultaneously valid, the enable signal provided by the enable line EN can be effective, thereby enabling the partial refresh mode.

[0188] In summary, the embodiments of this disclosure provide a shift register unit. In this shift register unit, the input control circuit can control the potential of the input node. The output control circuit can output a display drive signal to the pixel based on the potential of the input node and the enable signal provided by the enable line. Thus, by flexibly setting the enable signal and clock signal, the shift register unit can output signals matching the P-type transistors and / or N-type transistors in the pixel. Furthermore, since the output control circuit and the input control circuit are arranged sequentially along a first direction and in a direction close to the pixel, and the signal lines connecting the output control circuit and the input control circuit are arranged sequentially along the first direction and in a direction close to the pixel, and all signal lines extend along a second direction intersecting the first direction, it also facilitates the narrow bezel design of the display device.

[0189] This disclosure also provides a method for driving a shift register unit, which can be used to drive a shift register unit as described above. As shown in FIG27, the method includes:

[0190] Step 2701: In response to the first scan command, provide a first clock signal to the first clock line, provide a second clock signal to the second clock line, and provide an enable signal of the first potential to the enable line.

[0191] Step 2702: In response to the second scan command, provide a first clock signal to the first clock line, provide a second clock signal to the second clock line, and provide an enable signal of the second potential to the enable line.

[0192] The first and second clock signals are used to drive the input control circuit to control the on / off state of the input signal terminal and the input node. The enable signal is used to drive the output control circuit to control the potential of the output signal terminal based on the potential of the input node and the enable signal, so as to output a display drive signal to the pixel through the output signal terminal. Furthermore, the refresh frequency indicated by the first scan command is greater than the refresh frequency indicated by the second scan command. That is, the refresh area indicated by the first scan command can be a high refresh rate area, and the refresh area indicated by the second scan command can be a low refresh rate area.

[0193] Optionally, taking the circuit structures shown in Figures 6 and 8 as examples, Figure 28 shows a driving timing diagram of a shift register unit, including the timing of A. high refresh region and B. low refresh region.

[0194] First, referring to Figure 28, it can be seen that it shows four sets of clock signals. Furthermore, when the display panel is powered on or off, the reset control signal provided by the reset control line Trst can be set high, i.e., the potential of the reset control signal is controlled to be high, thereby controlling the potential of the output signal terminal GN_n to be an invalid potential (e.g., high potential), thus resetting the output signal. In the high refresh rate region, the enable signal provided by the enable line EN can be set high, i.e., the potential of the enable signal is controlled to be high, so that the potential of the NAND gate output signal changes with the potential of GNc_n, i.e., controlling the shift register unit to output normally. In the low refresh rate region, the enable signal provided by the enable line EN can be set low, i.e., the potential of the enable signal is controlled to be low, so that the potential of the NAND gate output signal remains high and does not change with the potential of GNc_n. Furthermore, the potential of the output signal terminal GN_n can be kept low, so that the potential of the display drive signal output to the pixel is an invalid potential, and the corresponding switch in the pixel is not activated.

[0195] Secondly, referring to Figure 28, the driving principle of the shift register unit is explained as follows:

[0196] (1) In the first stage t01 of the high refresh region, a low-level first clock signal can be provided to the first clock line CB, and a high-level second clock signal can be provided to the second clock line CKn, causing the first transmission gate Tg1 to be turned on. This causes the input signal terminal IN_n to be turned on with the input node Q_n, and the input signal terminal IN_n (i.e., GPc_n-1) can output an input signal to the input node Q_n. At this time, the potential of the output input signal can be high. In addition, a high-level reset control signal can be provided to the reset control line Trst, which can then control the potential of node GNc_n to be low after passing through the NOR gate, and then control the potential of node GPc_n to be high after passing through the first NOT gate INV1. Since the potential of node GPc_n-1 is high, it can be known that the potential of node GNc_n-1 is low. Therefore, the first third transmission gate Tg3-1 can be turned off, and the enable line EN is disconnected from the NAND gate. Since the potential of node GNc_n is low, a high-potential signal can be output via the NAND gate. This high-potential signal, after passing through three second NOT gates INV2, can make the potential of the output signal terminal GN_n low. Furthermore, in the first stage t01, a high-potential third clock signal can be provided to the third clock line CK, and a low-potential fourth clock signal can be provided to the fourth clock line CBn, causing the second transmission gate Tg2 to turn off, thereby disconnecting node GPc_n from the input node Q_n.

[0197] It is understandable that, as shown in Figure 28, the pulse widths of the low-level clock signals provided by clock line CK and clock line CB are both smaller than the pulse widths of the high-level clock signals, generally about 0 to 2 μs less than 1H. This can be flexibly selected based on the load RC. Based on this setting, the clock delay effect can be eliminated, avoiding the risk of competition between the gate circuit (e.g., NOR gate) in the first output control sub-circuit 021 and the first NOT gate INV1 in the latch circuit 04 when the first transmission gate Tg1 and the second transmission gate Tg2 are simultaneously turned on during input state switching, i.e., when the potential of the input signal provided by the input signal terminal IN_n changes.

[0198] (2) In the second stage t02 of the high refresh region, a high-level first clock signal can be provided to the first clock line CB, and a low-level second clock signal can be provided to the second clock line CKn, causing the first transmission gate Tg1 to turn off, thereby disconnecting the input signal terminal IN_n from the input node Q_n. A low-level third clock signal can be provided to the third clock line CK, and a high-level fourth clock signal can be provided to the fourth clock line CBn, causing the second transmission gate Tg2 to turn on, thereby turning the node GPc_n on with the input node Q_n, thus latching the potential of the input node Q_n as the high potential of the node GPc_n. In addition, a low-level reset control signal can be provided to the reset control line Trst, so after passing through the NOR gate, the potential of the node GNc_n can be controlled to be low, and after passing through the first NOT gate INV1, the potential of the node GPc_n can be controlled to be high. Since the potential of the node GPc_n-1 is low, it can be known that the potential of the node GNc_n-1 is high, so the first third transmission gate Tg3-1 is turned on. Because the potential of node GPc_n is high and the potential of node GNc_n is low, the second third transmission gate Tg3-2 is turned on. This allows the enable line EN to be connected to the NAND gate, which can control the potential of the output signal based on the enable signal provided by the enable line. At this time, as shown in Figure 28, the enable signal is high, and because the potential of node GNc_n is low, a high-potential signal can be output after passing through the NAND gate. This high-potential signal, after passing through three second NOT gates INV2, can make the potential of the output signal terminal GN_n low.

[0199] (3) In the third stage t03 of the high refresh region, a low-level first clock signal can be provided to the first clock line CB, and a high-level second clock signal can be provided to the second clock line CKn, causing the first transmission gate Tg1 to conduct, thereby enabling the input signal terminal IN_n to conduct with the input node Q_n. The input signal terminal IN_n can output an input signal to the input node Q_n, and the potential of the input signal (GPc_n-1) can be low at this time. In addition, a low-level reset control signal can be provided to the reset control line Trst, which can then control the potential of node GNc_n to be high after passing through the NOR gate, and then control the potential of node GPc_n to be low after passing through the first NOT gate INV1. Since the potential of node GPc_n-1 is low, it can be known that the potential of node GNc_n-1 is high, so the first third transmission gate Tg3-1 conducts. Since the potential of node GPc_n is low and the potential of node GNc_n is high, the second third transmission gate Tg3-2 is turned off. Furthermore, the enable line EN can be disconnected from the NAND gate. The enable signal's potential can remain at the high level of the previous stage. Since the potential of node GNc_n is high, a low-level signal can be output through the NAND gate. This low-level signal, after passing through three second NOT gates INV2, can make the potential of the output signal terminal GN_n high. In the third stage t03, a high-level third clock signal can be provided to the third clock line CK, and a low-level fourth clock signal can be provided to the fourth clock line CBn, causing the second transmission gate Tg2 to turn off, thereby disconnecting node GPc_n from the input node Q_n.

[0200] (4) In the low-brush region, since the enable signal is kept at a low potential, as mentioned above, the NAND output signal can be kept at a high potential. As shown in Figure 28, the high potential signal can keep the output signal terminal GN_n at a low potential after passing through three second NOT gates INV2.

[0201] Optionally, the shift register unit can also be connected to the display driver IC (DIC) and used to receive the aforementioned signals, such as clock signals, provided by the DIC. That is, the DIC can provide the required signals to the signal terminals connected to the shift register unit so that the shift register unit can output the required display driving signals to the pixels.

[0202] It is understandable that, since the driving method of the shift register unit can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the driving method of the shift register unit will not be repeated here for the sake of brevity.

[0203] This disclosure also provides a display driver. As shown in FIG29, the display driver includes at least two cascaded shift register units (GOAs) as described above.

[0204] For example, Figure 29 shows a shift register unit GOA that provides gate drive signals to the gate signal terminal Gate_N connected to the N-type transistor. That is, the output signal terminal OUT_n is connected to the pixel's gate signal terminal Gate_N. Correspondingly, a display driver including this NGate GOA can also be called a gate drive circuit.

[0205] Furthermore, the display driver shown in Figure 29 uses four sets of clock signals (including CK, CB, CKn and CBn, a total of four clock signal terminals), and is powered by dual VGH and dual VGL (including first power supply terminals VGH1 and VGH2, and second power supply terminals VGL1 and VGL2).

[0206] Furthermore, the cascading method shown in Figure 29 is as follows: the input signal terminal IN_1 of the first-stage shift register unit NGate GOA is connected to the enable signal line STV, and the input signal terminals of other-stage shift register units NGate GOA (e.g., IN_2, IN_n-1, and IN_n) are connected to the intermediate node Q2_n (i.e., node GPc_n) of the previous-stage shift register unit NGate GOA. Each-stage shift register unit can also be connected to node GNc_n-1 of the previous-stage shift register unit to receive the cascading signal provided by node GNc_n-1. Here, the third transmission gate Tg3-1 included in the shift register unit can be connected to node GNc_n-1.

[0207] It is understandable that, since the potential of node GNc_n is opposite to that of node GPc_n, for the first-stage shift register unit, an inverter F1, also known as a NOT gate, can be added between the enable signal line STV and the third transmission gate Tg3-1 to receive a signal with a potential opposite to that of the enable signal. For the design of other structures, please refer to the relevant descriptions of the shift register unit mentioned above; they will not be elaborated upon here.

[0208] Optionally, in some embodiments, a dummy shift register unit, i.e., a dummy GOA, may be added to the first or last line to meet the required timing requirements or drive the load.

[0209] It is understood that since the display driver can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the display driver will not be repeated here for the sake of brevity.

[0210] This disclosure also provides a display device. As shown in FIG30, the display device includes a display panel 10 and a display driver 00 as shown in FIG29.

[0211] The display panel 10 includes multiple pixels (not shown in Figure 30), and the display driver 00 is connected to the multiple pixels and is used to transmit display driving signals to the multiple pixels to drive the multiple pixels to emit light. For example, referring to Figure 2, the display driver 00 can be connected to the gate signal terminal Gate_N of the pixel and is used to transmit gate driving signals to the multiple pixels.

[0212] Optionally, the display device can be any product or component with display functionality, such as an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, or any other display device. Furthermore, the display device can also be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-readers.

[0213] It is understood that since the display device can have essentially the same technical effect as the shift register unit described in the various embodiments above, the technical effect of the display device will not be described again here for the sake of brevity.

[0214] It is understood that the terminology used in the embodiments of this disclosure is for illustrative purposes only and is not intended to limit the disclosure. Unless otherwise defined, the technical or scientific terms used in the implementation of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains.

[0215] For example, the use of words such as "first," "second," "third," and similar terms does not indicate any order, quantity, or importance, but is merely used to distinguish different components.

[0216] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0217] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0218] The word “connection” or “link” is not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0219] "Up," "down," "left," and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0220] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0221] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A shift register unit, comprising: an input control circuit connected with a first clock line, a second clock line, an input signal terminal and an input node respectively, and configured to control the on-off of the input signal terminal and the input node in response to a first clock signal provided by the first clock line and a second clock signal provided by the second clock line; an output control circuit connected with the input node, an enable line and an output signal terminal respectively, and configured to control the potential of the output signal terminal based on the potential of the input node and an enable signal provided by the enable line, so as to output a display driving signal to a P-type transistor and / or an N-type transistor of each pixel in at least one row of pixels through the output signal terminal, so as to drive a light emitting element of the each pixel to emit light; wherein the output control circuit and the input control circuit are arranged in a first direction and a direction close to the pixels in sequence; the first clock line, the second clock line and the enable line are arranged in the first direction and the direction close to the pixels in sequence, and the first clock line, the second clock line and the enable line all extend in a second direction; the second direction intersects the first direction.

2. The shift register cell of claim 1, wherein, The output control circuit comprises: a first output control sub-circuit connected with the input node, a reset control line and an intermediate node respectively, and configured to control the potential of the intermediate node based on the potential of the input node and a reset control signal provided by the reset control line; a second output control sub-circuit connected with the intermediate node, the enable line and the output signal terminal respectively, and configured to control the potential of the output signal terminal based on the potential of the intermediate node and the enable signal; and the first output control sub-circuit and the second output control sub-circuit are arranged in the second direction and a direction away from the input control circuit in sequence; the reset control line is located on a side of the first clock line away from the enable line, and the reset control line extends in the second direction.

3. The shift register cell of claim 2, wherein, The shift register unit further comprises: a switch control circuit connected between the enable line and the output control circuit, and further connected with at least two first control terminals and at least two second control terminals respectively, and configured to control the on-off of the enable line and the output control circuit in response to a first control signal provided by each of the first control terminals and a second control signal provided by each of the second control terminals; a latch circuit connected with a third clock line, a fourth clock line, the intermediate node and the input node respectively, and configured to control the on-off of the intermediate node and the input node in response to a third clock signal provided by the third clock line and a fourth clock signal provided by the fourth clock line, and to output the potential of the intermediate node to the input node after being inverted; a drive enhancement circuit connected between the output control circuit and the output signal terminal, and configured to output the potential of the output signal of the output control circuit to the output signal terminal after being inverted at least once. And, the latch circuit is located in a region defined by the output control circuit, the input control circuit and the switch control circuit, and the drive enhancement circuit is located at least on a side of the second output control sub-circuit away from the first output control sub-circuit; the third clock line and the fourth clock line are located between the reset control line and the enable line, and the third clock line and the fourth clock line are arranged in sequence along the first direction and along a direction close to the pixel, and the third clock line and the fourth clock line extend along the second direction.

4. The shift register cell of claim 3, wherein, The input control circuit comprises a first transmission gate; the first output control sub-circuit comprises an NOR gate; the second output control sub-circuit comprises an NAND gate; the latch circuit comprises a first NAND gate and a second transmission gate; the switch control circuit comprises two third transmission gates connected in sequence; and the drive enhancement circuit comprises three second NAND gates connected in sequence. The first transmission gate is connected between the input signal end and the input node, and is also connected with the first clock line and the second clock line respectively; two input ends of the NOR gate are connected with the reset control line and the input node respectively, and an output end of the NOR gate is connected with the intermediate node; one input end of the NAND gate is connected with the intermediate node, and the other input end of the NAND gate is connected with the enable line through the two third transmission gates connected in sequence, and an output end of the NAND gate is connected with the output signal end through the three second NAND gates connected in sequence, and each third transmission gate is also connected with one corresponding first control end and one second control end respectively; an input end of the first NAND gate is connected with the intermediate node, and an output end of the first NAND gate is connected with the input node through the second transmission gate, and the first transmission gate is also connected with the third clock line and the fourth clock line respectively; and the shift register unit further comprises a voltage stabilizing capacitor connected between a ground end and the other input end of the NAND gate. The NOR gate, the NAND gate and a first second NAND gate are arranged in sequence along the second direction, the first transmission gate, the second transmission gate, the first NAND gate, the fourth transmission gate and a second second NAND gate are arranged in sequence along the second direction, the third transmission gate is located on a side of the first NAND gate away from the fourth transmission gate, the voltage stabilizing capacitor is located between the NAND gate and the fourth transmission gate, a first second NAND gate to a third second NAND gate are arranged in sequence along the first direction and along a direction close to the pixel, and sizes of the first second NAND gate to the third second NAND gate increase in sequence.

5. The shift register cell of claim 4, wherein, The NOR gate, the NAND gate, the first NAND gate and each second NAND gate are also connected with a first power supply line and a second power supply line respectively, and are used to work based on a first power supply signal provided by the first power supply line and a second power supply signal provided by the second power supply line, and a potential of the first power supply signal is greater than a potential of the second power supply signal. The first power line and the second power line are located at least on two sides of the reset control line and the enable line in the first direction, and the first power line and the second power line extend in the second direction; the width of the first power line and the width of the second power line are greater than the width of the reset control line and the width of the enable line; the width of the first power line connected to the third second non-gate is greater than the width of the first power line connected to other gate circuits, and the width of the second power line connected to the third second non-gate is greater than the width of the second power line connected to the other gate circuits; the other gate circuits include at least one of the NAND gate, the NOR gate, the first non-gate, the second second non-gate and the first first non-gate.

6. The shift register cell of claim 4 or 5, wherein, The first transmission gate comprises a first P-type transistor and a first N-type transistor. The gate of the first P-type transistor and the gate of the first N-type transistor are connected to the first clock line and the second clock line respectively, the first pole of the first P-type transistor and the first pole of the first N-type transistor are connected to the input signal end, and the second pole of the first P-type transistor and the second pole of the first N-type transistor are connected to the input node. And the first P-type transistor and the first N-type transistor are arranged in the first direction and close to the pixel in sequence.

7. The shift register cell of any one of claims 4 to 6, wherein, The NOR gate comprises a second P-type transistor, a second N-type transistor, a third P-type transistor and a third N-type transistor. The gate of the second P-type transistor and the gate of the third N-type transistor are connected to the reset control line, the first pole of the second P-type transistor is connected to the first power line, the second pole of the second P-type transistor is connected to the first pole of the third P-type transistor, the second pole of the third P-type transistor, the second pole of the second N-type transistor and the second pole of the third N-type transistor are connected to the intermediate node, the first pole of the second N-type transistor and the first pole of the third N-type transistor are connected to the second power line, and the gate of the third P-type transistor and the gate of the second N-type transistor are connected to the input node. And the third P-type transistor and the second P-type transistor are arranged in the second direction and close to the NAND gate in sequence and are connected in series, the second N-type transistor is located on the side of the third P-type transistor away from the second P-type transistor, and the second N-type transistor is close to the pixel relative to the third P-type transistor, the third N-type transistor is located on the side of the second P-type transistor away from the third P-type transistor, and the third N-type transistor is close to the pixel relative to the second P-type transistor.

8. The shift register cell of any one of claims 4 to 7, wherein, The first non-gate comprises a fourth P-type transistor and a fourth N-type transistor, and the fourth N-type transistor is a double-gate transistor; and the second transmission gate comprises a fifth P-type transistor and a fifth N-type transistor. The gate of the fourth P-type transistor and the gate of the fourth N-type transistor are connected with the intermediate node, the first electrode of the fourth P-type transistor and the first electrode of the fourth N-type transistor are connected with the first power supply line and the second power supply line respectively, the second electrode of the fourth P-type transistor and the second electrode of the fourth N-type transistor are connected with the first electrode of the fifth P-type transistor and the first electrode of the fifth N-type transistor, the gate of the fifth P-type transistor and the gate of the fifth N-type transistor are connected with the third clock line and the fourth clock line respectively, and the second electrode of the fifth P-type transistor and the second electrode of the fifth N-type transistor are connected with the input node; Furthermore, the fourth P-type transistor and the fourth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, the fifth P-type transistor and the fifth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, the fifth P-type transistor and the fourth N-type transistor are arranged in sequence along the second direction and in a direction away from the first transfer gate, and the fifth N-type transistor and the fourth P-type transistor are arranged in sequence along the second direction and in a direction away from the first transfer gate.

9. A shift register cell as claimed in any one of claims 4 to 8, wherein, The NAND gate comprises a sixth P-type transistor, a sixth N-type transistor, a seventh P-type transistor and a seventh N-type transistor; the second third transfer gate comprises an eighth P-type transistor and an eighth N-type transistor; the first third transfer gate comprises a ninth P-type transistor and a ninth N-type transistor; the first second NAND gate comprises a tenth P-type transistor and a tenth N-type transistor; the second second NAND gate comprises an eleventh P-type transistor and an eleventh N-type transistor; and the third second NAND gate comprises a twelfth P-type transistor and a twelfth N-type transistor. The gate of the sixth P-type transistor and the gate of the sixth N-type transistor are connected with the intermediate node, the gate of the seventh P-type transistor and the gate of the seventh N-type transistor are connected with the first node, the second pole of the sixth P-type transistor, the second pole of the seventh P-type transistor and the second pole of the sixth N-type transistor are connected with the second node, the first pole of the sixth N-type transistor is connected with the second pole of the seventh N-type transistor, the gate of the eighth P-type transistor and the gate of the eighth N-type transistor are connected with one-to-one corresponding one first control end and one second control end respectively, the gate of the ninth P-type transistor and the gate of the ninth N-type transistor are connected with one-to-one corresponding another first control end and another second control end respectively, the first pole of the ninth P-type transistor and the first pole of the ninth N-type transistor are connected with the enable line, the second pole of the ninth P-type transistor and the second pole of the ninth N-type transistor are connected with the first pole of the eighth P-type transistor and the first pole of the eighth N-type transistor, the second pole of the eighth P-type transistor and the second pole of the eighth N-type transistor are connected with the first node, the gate of the tenth P-type transistor and the gate of the tenth N-type transistor are connected with the second node, the gate of the eleventh P-type transistor and the gate of the eleventh N-type transistor are connected with the second pole of the tenth P-type transistor and the second pole of the tenth N-type transistor, the gate of the twelfth P-type transistor and the gate of the twelfth N-type transistor are connected with the second pole of the eleventh P-type transistor and the second pole of the eleventh N-type transistor, the second pole of the twelfth P-type transistor and the second pole of the twelfth N-type transistor are connected with the output signal end, and the first pole of the sixth P-type transistor, the first pole of the seventh P-type transistor and the first pole of the tenth P-type transistor to the first pole of the twelfth P-type transistor are connected with the first power supply line, the first pole of the seventh N-type transistor and the first pole of the tenth N-type transistor to the first pole of the twelfth N-type transistor are connected with the second power supply line. And, the seventh N-type transistor, the sixth N-type transistor, the sixth P-type transistor and the seventh P-type transistor are sequentially arranged along the second direction and in a direction close to the tenth P-type transistor, the eighth N-type transistor and the eighth P-type transistor are sequentially arranged along the first direction and in a direction close to the pixel, the ninth P-type transistor and the ninth N-type transistor are sequentially arranged along the second direction and in a direction close to the eighth P-type transistor, the tenth P-type transistor and the tenth N-type transistor are sequentially arranged along the first direction and in a direction close to the pixel, the eleventh N-type transistor and the eleventh P-type transistor are sequentially arranged along the second direction and in a direction away from the eighth P-type transistor, and the twelfth P-type transistor and the twelfth N-type transistor are sequentially arranged along the second direction and in a direction close to the eleventh P-type transistor.

10. The shift register cell of any of claims 4 to 9, wherein, The size of the transistor in the first to third second NOT gates increases sequentially. The size of the transistor in the first transfer gate, the NOR gate, the NAND gate, the first NOT gate, the second transfer gate and each third transfer gate is smaller than the size of the transistor in any second NOT gate.

11. A shift register cell as claimed in any one of claims 3 to 10, wherein, The first clock line, the second clock line, the enable line, the reset control line, the third clock line and the fourth clock line are located on the same side of the first output control sub-circuit away from the second output control sub-circuit, and are arranged at equal intervals in the first direction.

12. The shift register cell of any one of claims 1 to 11, wherein, The transistor in the shift register unit comprises: a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked. The first active layer is used as an active layer of a P-type transistor in the shift register unit, and the second active layer is used as an active layer of an N-type transistor in the shift register unit.

13. The shift register cell of claim 12, wherein, At least part of the first source-drain metal layer is multiplexed with at least one of the first active layer, the first gate metal layer, the second gate metal layer and the second active layer to reduce the overlapping area of the first source-drain metal layer and the second source-drain metal layer.

14. A display driver, the display driver comprising: At least two shift register units as claimed in any one of claims 1 to 13 are cascaded.

15. A display device comprising: A display panel and a display driver as claimed in claim 14; The display panel comprises a plurality of pixels, and the display driver is connected with the plurality of pixels and is configured to transmit display driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

Images