Shift register unit, display driving circuit and display device

Abstract

Provided are a shift register unit, a display driving circuit and a display device. In the shift register unit, an input control circuit can control the potential of an input node under the control of a clock signal; and an output control circuit can output display driving signals to pixels by means of a signal output end on the basis of the potential of the input node and a reset control signal, in order to drive the pixels to emit light. In this way, flexibly setting the clock signal and the reset control signal enables the shift register unit to output display driving signals matching P-type transistors and / or N-type transistors in the pixels. Moreover, the output control circuit and the input control circuit are arranged in sequence in a first direction and in a direction toward the pixels, signal lines connected to the output control circuit and the input control circuit are arranged in sequence in the first direction and in the direction toward the pixels, and the signal lines all extend in a second direction intersecting the first direction, and thus the narrow bezel design of display devices can also be facilitated.

Description

Shift register unit, display driver circuit and display device

[0001] This application claims priority to Chinese Patent Application No. 202411037293.0, filed on July 30, 2024, entitled "Shift Register Unit, Display Driver Circuit and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a shift register unit, a display driver circuit, and a display device. Background Technology

[0003] Gate driver on array (GOA) technology is a technology that integrates the display driving circuitry onto the display panel, which is beneficial for the narrow bezel design of the display panel. Summary of the Invention

[0004] A shift register unit, a display driver circuit, and a display device are provided.

[0005] The technical solution is as follows:

[0006] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0007] An input control circuit is connected to a first clock line, a second clock line, an input signal terminal, and an input node, respectively, and is used to control the connection and disconnection of the input signal terminal and the input node in response to a first clock signal provided by the first clock line and a second clock signal provided by the second clock line.

[0008] An output control circuit is connected to the input node, the reset control line, and the output signal terminal, respectively, and is used to control the potential of the output signal terminal based on the potential of the input node and the reset control signal provided by the reset control line, so as to output a display driving signal to the P-type transistor and / or N-type transistor of each pixel in at least one row of pixels through the output signal terminal, so as to drive the light-emitting element of each pixel to emit light.

[0009] The output control circuit and the input control circuit are arranged sequentially along a first direction and in a direction close to the pixel; the reset control line, the first clock line and the second clock line are arranged sequentially along the first direction and in a direction close to the pixel, and the reset control line, the first clock line and the second clock line all extend along a second direction; the second direction intersects with the first direction.

[0010] Optionally, the shift register unit further includes:

[0011] A drive enhancement circuit is connected between the output control circuit and the output signal terminal, and is used to invert the potential of the signal output by the output control circuit at least once before outputting it to the output signal terminal.

[0012] The drive enhancement circuit and at least one of the input control circuit and the output control circuit are arranged sequentially along the second direction.

[0013] Optionally, the shift register unit further includes:

[0014] A latching circuit is connected to the third clock line, the fourth clock line, the input node, and the intermediate node, respectively, and is used to control the on / off state of the intermediate node and the input node in response to the third clock signal provided by the third clock line and the fourth clock signal provided by the fourth clock line, and outputs the potential of the intermediate node to the input node after inverting the potential. The intermediate node is the connection node of the drive enhancement circuit and the output control circuit.

[0015] The latch circuit is located between the drive enhancement circuit and at least one of the input control circuit and the output control circuit; the third clock line and the fourth clock line are located on the side of the reset control line near the pixel, and the third clock line and the fourth clock line are arranged sequentially along the first direction and along the direction near the pixel, and both the third clock line and the fourth clock line extend along the second direction.

[0016] Optionally, the input control circuit includes a first transmission gate; the output control circuit includes a NOR gate; the latch circuit includes a first NOT gate and a second transmission gate; and the drive enhancement circuit includes three second NOT gates.

[0017] The first transmission gate is connected between the input signal terminal and the input node, and is also connected to the first clock line and the second clock line respectively; the two input terminals of the NOR gate are connected to the input node and the reset control line respectively, and the output terminal of the NOR gate is connected to the intermediate node; the input terminal of the first NOT gate is connected to the intermediate node, and the output terminal of the first NOT gate is connected to the input node through the second transmission gate, and the second transmission gate is also connected to the third clock line and the fourth clock line respectively; the three second NOT gates are connected in series between the intermediate node and the output signal terminal.

[0018] Furthermore, the NOR gate, the first NOT gate, and the first second NOT gate are arranged sequentially along the second direction, the first transmission gate, the second transmission gate, and the second second NOT gate are arranged sequentially along the second direction, and the first second NOT gate to the third second NOT gate are arranged sequentially along the first direction and along the direction closer to the pixel, and the size of the first second NOT gate to the third second NOT gate increases sequentially.

[0019] Optionally, the NOR gate, the first NOT gate, and each of the second NOT gates are also connected to the first power line and the second power line respectively, and are used to operate based on the first power signal provided by the first power line and the second power signal provided by the second power line, wherein the potential of the first power signal is greater than the potential of the second power signal.

[0020] Wherein, the first power line and the second power line are located at least on both sides of the reset control line in the first direction, and both the first power line and the second power line extend along the second direction; the width of the first power line and the width of the second power line are both greater than the width of the reset control line; the width of the first power line connected to the third second NOT gate is greater than the width of the first power line connected to other gate circuits, and the width of the second power line connected to the third second NOT gate is greater than the width of the second power line connected to the other gate circuits; the other gate circuits include at least one of the NOR gate, the first NOT gate, the second second NOT gate, and the first first NOT gate.

[0021] Optionally, the first transmission gate includes: a first P-type transistor and a first N-type transistor;

[0022] The gate of the first P-type transistor and the gate of the first N-type transistor are respectively connected to the first clock line and the second clock line. The first terminal of the first P-type transistor and the first terminal of the first N-type transistor are both connected to the input signal terminal. The second terminal of the first P-type transistor and the second terminal of the first N-type transistor are both connected to the input node.

[0023] Furthermore, the first P-type transistor and the first N-type transistor are arranged sequentially along the first direction and in the direction closest to the pixel.

[0024] Optionally, the NOR gate includes: a second P-type transistor, a second N-type transistor, a third P-type transistor, and a third N-type transistor;

[0025] The gates of the second P-type transistor and the third N-type transistor are both connected to the reset control line. The first terminal of the second P-type transistor is connected to the first power supply line. The second terminal of the second P-type transistor is connected to the first terminal of the third P-type transistor. The second terminals of the third P-type transistor, the second terminals of the second N-type transistor, and the second terminals of the third N-type transistor are all connected to the intermediate node. The first terminals of the second N-type transistor and the first terminals of the third N-type transistor are all connected to the second power supply line. The gates of the third P-type transistor and the second N-type transistor are both connected to the input node.

[0026] Furthermore, the third P-type transistor and the second P-type transistor are arranged sequentially and connected in series along the second direction and along the direction close to the first NOT gate. The second N-type transistor is located on the side of the third P-type transistor away from the second P-type transistor, and the third N-type transistor is located on the side of the third P-type transistor close to the second P-type transistor. Both the second N-type transistor and the third N-type transistor are closer to the pixel relative to the third P-type transistor.

[0027] Optionally, the first NOT gate includes a fourth P-type transistor and a fourth N-type transistor, wherein the fourth N-type transistor is a dual-gate transistor; the second transmission gate includes a fifth P-type transistor and a fifth N-type transistor.

[0028] The gates of the fourth P-type transistor and the fourth N-type transistor are both connected to the intermediate node. The first terminals of the fourth P-type transistor and the fourth N-type transistor are respectively connected to the first power line and the second power line. The second terminals of the fourth P-type transistor and the fourth N-type transistor are both connected to the first terminals of the fifth P-type transistor and the fifth N-type transistor. The gates of the fifth P-type transistor and the fifth N-type transistor are respectively connected to the third clock line and the fourth clock line. The second terminals of the fifth P-type transistor and the fifth N-type transistor are both connected to the input node.

[0029] Furthermore, the fourth P-type transistor and the fourth N-type transistor are arranged sequentially along the first direction and in a direction close to the pixel, and the fifth P-type transistor and the fifth N-type transistor are arranged sequentially along the first direction and in a direction close to the pixel, and both the fifth P-type transistor and the fifth N-type transistor are closer to the first transmission gate than the fourth P-type transistor and the fourth N-type transistor.

[0030] Optionally, the first second NOT gate includes: a sixth P-type transistor and a sixth N-type transistor; the second second NOT gate includes: a seventh P-type transistor and a seventh N-type transistor; the third second NOT gate includes: an eighth P-type transistor and an eighth N-type transistor.

[0031] The gates of the sixth P-type transistor and the sixth N-type transistor are both connected to the intermediate node. The gates of the seventh P-type transistor and the seventh N-type transistor are both connected to the second terminals of the sixth P-type transistor and the sixth N-type transistor. The gates of the eighth P-type transistor and the eighth N-type transistor are both connected to the second terminals of the seventh P-type transistor and the seventh N-type transistor. The second terminals of the eighth P-type transistor and the eighth N-type transistor are both connected to the output signal terminal. The first terminals of the sixth P-type transistor, the seventh P-type transistor, and the eighth P-type transistor are all connected to the first power supply line. The first terminals of the sixth N-type transistor, the seventh N-type transistor, and the eighth N-type transistor are all connected to the second power supply line.

[0032] Furthermore, the sixth P-type transistor and the sixth N-type transistor are arranged sequentially along the first direction and in a direction close to the pixel, the seventh P-type transistor and the seventh N-type transistor are arranged sequentially along the second direction and in a direction away from the first transmission gate, and the eighth P-type transistor and the eighth N-type transistor are arranged sequentially along the second direction.

[0033] Optionally, the size of the transistors in the first to the third second NOT gates increases sequentially;

[0034] Furthermore, the size of the transistors in the first transmission gate, the NOR gate, the first NOT gate, and the second transmission gate is smaller than the size of the transistor in any of the second NOT gates.

[0035] Optionally, the first clock line, the second clock line, the reset control line, the third clock line, and the fourth clock line are all located on the same side of the output control circuit away from the latch circuit, and are arranged at equal intervals in the first direction.

[0036] Optionally, the transistor in the shift register unit includes: a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked sequentially;

[0037] Wherein, the first active layer is used as the active layer of the P-type transistor in the shift register unit, and the second active layer is used as the active layer of the N-type transistor in the shift register unit.

[0038] Optionally, at least a portion of the first source / drain metal layer is reused with at least one of the first active layer, the first gate metal layer, the second gate metal layer, and the second active layer to reduce the overlap area between the first source / drain metal layer and the second source / drain metal layer.

[0039] On the other hand, a display driving circuit is provided, the display driving circuit comprising: at least two cascaded shift register units as described in one aspect above.

[0040] In another aspect, a display device is provided, the display device comprising: a display panel, and a display driving circuit as described in the other aspect above;

[0041] The display panel includes multiple pixels, and the display driving circuit is connected to the multiple pixels and is used to transmit light emission control signals to the multiple pixels to drive the multiple pixels to emit light. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this disclosure;

[0044] Figure 2 is a schematic diagram of a pixel circuit provided in an embodiment of this disclosure;

[0045] Figure 3 is a schematic diagram of the working timing of a pixel circuit provided in an embodiment of this disclosure;

[0046] Figure 4 is a schematic diagram of the structural layout of a shift register unit provided in an embodiment of this disclosure;

[0047] Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0048] Figure 6 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this disclosure;

[0049] Figure 7 is a schematic diagram of the circuit structure layout of a shift register unit provided in an embodiment of this disclosure;

[0050] Figure 8 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0051] Figure 9 is a schematic circuit layout diagram of a shift register unit provided in an embodiment of this disclosure;

[0052] Figure 10 is a schematic layout diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0053] Figure 11 is a schematic layout diagram of another portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0054] Figure 12 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0055] Figure 13 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0056] Figure 14 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0057] Figure 15 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0058] Figure 16 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0059] Figure 17 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0060] Figure 18 is a schematic circuit layout of another shift register unit provided in an embodiment of this disclosure;

[0061] Figure 19 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0062] Figure 20 is a schematic diagram of another portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0063] Figure 21 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0064] Figure 22 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0065] Figure 23 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0066] Figure 24 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0067] Figure 25 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0068] Figure 26 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0069] Figure 27 is a flowchart illustrating a method for driving a shift register unit according to an embodiment of this disclosure;

[0070] Figure 28 is a schematic diagram of the driving timing of a shift register unit provided in an embodiment of this disclosure;

[0071] Figure 29 is a schematic diagram of the structure of a display driver provided in an embodiment of this disclosure;

[0072] Figure 30 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0074] It is understood that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this disclosure, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this disclosure can include any of P-type and N-type transistors. A P-type transistor conducts when the gate is low and is cut off when the gate is high, while an N-type transistor conducts when the gate is high and is cut off when the gate is low. In addition, multiple signals in the various embodiments of this disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two states and do not represent that the first potential or the second potential has a specific value throughout the text.

[0075] This disclosure provides a shift register unit that can better match the timing requirements of N-type transistors and / or P-type transistors in a pixel, offering good driving flexibility and driving effect. As shown in Figure 1, the shift register unit includes an input control circuit 01 and an output control circuit 02.

[0076] The input control circuit 01 is connected to the first clock line CB, the second clock line CKn, the input signal terminal IN_n, and the input node Q_n, respectively, and is used to control the on / off state of the input signal terminal IN_n and the input node Q_n in response to the first clock signal provided by the first clock line CB and the second clock signal provided by the second clock line CKn.

[0077] For example, the input control circuit 01 can control the input signal terminal IN_n to be connected to the input node Q_n when the potential of the first clock signal is the first potential and the potential of the second clock signal is the first potential, so that the input signal provided by the input signal terminal IN_n is output to the input node Q_n, thereby controlling the potential of the input node Q_n to be the potential of the input signal; and the input control circuit 01 can control the input signal terminal IN_n to be disconnected from the input node Q_n when the potential of the first clock signal is the second potential or the potential of the second clock signal is the second potential.

[0078] It is understandable that "n" indicates that the shift register unit is the nth level shift register unit, and correspondingly, "nm" indicates the first m levels of shift register units cascaded with this shift register unit, and "n+m" indicates the last m levels of shift register units cascaded with this shift register unit. n can be an integer greater than 1, and m can be an integer less than n but greater than 1. For example, m can be 1, meaning that, except for the first level shift register unit, each level shift register unit can be cascaded with both the preceding and following level shift register units. The following embodiments all use m=1 as an example. Furthermore, generally, multi-level shift register units can be connected one-to-one with multiple rows of pixels. However, this is not limited to a one-to-one connection. For example, each level shift register unit can be connected with at least two rows of pixels.

[0079] Optionally, in this embodiment, the first potential can be an effective potential, and the second potential can be an ineffective potential. Furthermore, for a P-type transistor in a pixel, the first potential can be low (low, L) relative to the second potential. For an N-type transistor in a pixel, the first potential can be high (high, H) relative to the second potential. Correspondingly, a reset signal output to a P-type transistor means controlling the potential of the signal output to the P-type transistor to be high (H); a reset signal output to an N-type transistor means controlling the potential of the signal output to the N-type transistor to be low (L). Additionally, a high potential can be represented by binary "1", and a low potential can be represented by binary "0".

[0080] Referring again to Figure 1, the output control circuit 02 is connected to the input node Q_n, the reset control line Trst, and the output signal terminal OUT_n, respectively. It is used to control the potential of the output signal terminal OUT_n based on the potential of the input node Q_n and the reset control signal provided by the reset control line Trst, so as to output a display driving signal to the P-type transistor and / or N-type transistor of each pixel in at least one row of pixels through the output signal terminal OUT_n, so as to drive the light-emitting element of each pixel to emit light.

[0081] Optionally, the display driving signal includes a reset signal or a light emission control signal. That is, the output control circuit 02 can output a reset signal to the reset transistor in the pixel through the output signal terminal OUT_n. Alternatively, the output control circuit 02 can output a light emission control signal to the light emission control transistor in the pixel through the output signal terminal OUT_n.

[0082] For example, the output control circuit 02 can control the output signal terminal OUT_n to a low potential 0 when the potential of the input node Q_n is high potential 1 and / or the potential of the reset control signal is high potential 1; and the output control circuit 02 can control the output signal terminal OUT_n to a high potential 1 when the potential of the input node Q_n is low potential 0 and the potential of the reset control signal is low potential 0. Thus, a display driving signal (e.g., a light emission control signal) including high potential 1 and low potential 0 (i.e., including a first potential and a second potential) can be output through the output signal terminal OUT_n, which can realize the output of pulses with the required timing to the P-type transistors and / or N-type transistors in the pixel, satisfying the driving requirements of PMOS switching pixels, or NMOS switching pixels, or CMOS switching pixels.

[0083] Furthermore, by flexibly configuring the reset control signal provided by the reset control line Trst, the output control circuit 02 can control the potential of the output signal terminal OUT_n to an invalid potential when the display panel is powered on or off, thereby globally resetting the display drive signals output to the pixels and ensuring good power-on / off reliability. Alternatively, the display drive signals output to the pixels can be reset during the blanking time of each frame (i.e., the Porch period) to ensure good uniformity of display across frames.

[0084] For example, taking the display drive signal as the light emission control signal, when the display panel is powered on or off, for the N-type transistor connected to the output signal terminal OUT_n, the potential of the reset control signal provided by the reset control line Trst can be set to a high potential (1), that is, the reset control signal is set high. This causes the output control circuit 02 to control the potential of the output signal terminal OUT_n to a low potential (0), thereby resetting the light emission control signal output to the N-type transistor. Furthermore, when the reset is complete, the potential of the reset control signal provided by the reset control line Trst can be kept at a low potential (0), so that the output control circuit 02 controls the potential of the output signal terminal OUT_n to change with the potential of the input node Q_n. Similarly, for the P-type transistor in the pixel connected to the output signal terminal OUT_n, the potential of the reset control signal provided by the reset control line Trst can be set to a low potential (0), that is, the voltage of the reset control signal is low, and at the same time, the potential of the input node Q_n is controlled to a low potential (0). This causes the output control circuit 02 to control the potential of the output signal terminal OUT_n to a high potential (1), thereby resetting the light-emitting control signal output to the P-type transistor. Furthermore, when the reset is complete, the potential of the reset control signal provided by the reset control line Trst can be kept at a high potential (1), so that the output control circuit 02 controls the potential of the output signal terminal OUT_n to change with the potential of the input node Q_n.

[0085] Optionally, in some embodiments, the reset control line Trst can be replaced with a clock line or other enable line to output a single-pulse display drive signal suitable for switching control of single-pulse P-type / N-type transistors.

[0086] It's understandable that a PMOS switching pixel refers to a pixel whose pixel circuitry includes multiple P-type transistors; an NMOS switching pixel refers to a pixel whose pixel circuitry includes multiple N-type transistors; and a CMOS switching pixel refers to a pixel whose pixel circuitry includes at least one P-type transistor and at least one N-type transistor. MOS is short for metal-oxide-semiconductor, meaning the transistors in the pixel circuitry can be MOS transistors. Additionally, the transistors can also be thin-film transistors (TFTs). That is, the transistors in the pixel circuitry can be MOS TFTs; P-type transistors can be called PMOS TFTs, and N-type transistors can be called NMOS TFTs. Of course, this is just an illustrative explanation.

[0087] Optionally, taking a CMOS switch-type pixel as an example, Figure 2 shows a schematic diagram of the circuit structure of a pixel provided in an embodiment of this disclosure. As shown in Figure 2, the pixel may include a pixel circuit and a light-emitting element L1. The pixel circuit may include eight transistors T1 to T8 and one capacitor Cst, that is, it can be an 8T1C structure circuit. The light-emitting element L1 can be an organic light-emitting diode (OLED). The connection method of each part is shown in Figure 2 and will not be described again. In addition, the signal terminals connected to the pixel include: a gate signal terminal Gate, reset signal terminals Reset1, Reset2 and Reset3, a data signal terminal Vdata, reset power supply terminals V1, V2 and V3, a light-emitting control terminal EM, a pull-up power supply terminal EVDD, and a pull-down power supply terminal ELVSS. Of course, in some other embodiments, the pixel circuit can also be other structures, such as an 8T2C structure. The light-emitting element L1 can also be other types, such as a micro-LED, also known as an MLED. This disclosure does not limit this.

[0088] For PMOS switching pixels, all eight transistors T1 to T8 can be PMOS TFTs; for NMOS switching pixels, all eight transistors T1 to T8 can be NMOS TFTs; and for CMOS switching pixels, as shown in Figure 2, T2 and T5 can be NMOS TFTs, while the other transistors can be PMOS TFTs. Furthermore, among transistors T4 and T5 connected to the light-emitting control terminal EM to receive the light-emitting control signal, transistor T4 can be a PMOS TFT, and transistor T5 can be an NMOS TFT. Accordingly, the light-emitting control terminal EM connected to transistor T4 can be labeled EM_P, and the light-emitting control terminal EM connected to transistor T5 can be labeled EM_N. "N" indicates the relevant signal terminal connected to the NMOS TFT, and "P" indicates the relevant signal terminal connected to the PMOS TFT; the labeling of other signal terminals can be similar. For example, in Figure 2, the PMOS TFT transistor T1 is connected to the gate signal terminal Gate_P, and the NMOS TFT transistor T2 is connected to the gate signal terminal Gate_N.

[0089] Taking the light emission control signal as an example, for a PMOS switching pixel, since transistors T4 and T5, which receive the light emission control signal, are both PMOS TFTs, the same or similar P-type light emission control signal can be used to drive transistors T4 and T5. For an NMOS switching pixel, since transistors T4 and T5, which receive the light emission control signal, are both NMOS TFTs, the same or similar N-type light emission control signal can be used to drive transistors T4 and T5. However, for the CMOS switching pixel shown in Figure 2, since transistor T4, which receives the light emission control signal, is a PMOS TFT and T5 is an NMOS TFT, inverted P-type and N-type light emission control signals are needed to drive transistors T4 and T5 respectively. Here, the P-type light emission control signal refers to a light emission control signal with a first potential of low potential 0 and a second potential of high potential 1; the N-type control signal refers to a light emission control signal with a first potential of high potential 1 and a second potential of low potential 0. The gate drive signal is similar and will not be elaborated further here.

[0090] Optionally, taking the pixel circuit shown in Figure 2 as an example, Figure 3 shows a driving timing diagram of a pixel circuit. As shown in Figure 3, the driving timing may include stages t1 to t5 executed sequentially.

[0091] In stage t1, the potential of the light-emitting control signal provided by the light-emitting control terminal EM_P can be high, and the potential of the light-emitting control signal provided by the light-emitting control terminal EM_N can be low. Accordingly, transistors T4 and T5 can be turned off. Furthermore, the connection between the pull-up power supply terminal EVDD and the pull-down power supply terminal EVSS can be disconnected, thereby turning off the light emission of the light-emitting element L1.

[0092] In stage t2, the gate drive signal provided by the gate signal terminal Gate_N can be at a high potential, while the reset signals provided by the reset signal terminals Reset1 / Reset3 can both be at a low potential. Correspondingly, transistors T2, T3, and T6 can all be turned on. Furthermore, the reset power supply terminal V2 can sequentially output reset power signals to nodes P3 and P1 via the turned-on transistors T3 and T2, respectively, to reset nodes P1 and P3 to the potential V20 of the reset power supply signal provided by the reset power supply terminal V2, causing the potential of node P2 to gradually become V20 - Vth_Td, where Vth_Td refers to the threshold voltage of transistor T8 (also called the driving transistor Td). Additionally, the reset power supply terminal V1 can output a reset power signal to node P4 (i.e., the anode of the OLED) via the turned-on transistor T6, to reset node P4 to the potential of the reset power supply signal provided by the reset power supply terminal V1.

[0093] In stage t3, the reset signals provided by Reset1 / Reset3 can both be at a high potential, the gate drive signal provided by Gate_N can be maintained at a high potential, and the gate drive signal provided by Gate_P can be at a low potential. Correspondingly, transistors T3 and T6 can be turned off, while transistors T1, T2, and T8 can all be turned on. Furthermore, the data signal Vdata can be transmitted to node P2 via the turned-on transistor T1, thereby charging the potential of node P2 to the potential Vdata0 of the data signal, and charging nodes P3 and P1 to a potential of Vdata0 + Vth_Td.

[0094] In stage t4, the potential of the gate drive signal provided by the gate signal terminal Gate_N becomes low, and the potential of the reset signal provided by the reset signal terminal Reset2 is also low. Accordingly, transistor T2 can be turned off, and transistor T7 can be turned on. Then, the reset power supply terminal V3 can output a reset power supply signal to node P2 via the turned-on transistor T7, resetting node P2 to the potential V30 of the reset power supply signal provided by the reset power supply terminal V3. If V30 > Vdata0, the potential of node P3 can become V30 + Vth_Td; otherwise, the potential of node P3 remains Vdata0 + Vth_Td.

[0095] In stage t5, the reset signal provided by Reset2 becomes high, the light-emitting control signal provided by EM_P becomes low, and the light-emitting control signal provided by EM_N becomes high. Correspondingly, transistor T7 is turned off, and transistors T4 and T5 are turned on. Furthermore, due to the storage effect of the storage capacitor Cst, the potential of node P1 remains at the level of the previous stage, keeping transistor T8 on. This allows a path to be formed between the pull-up power supply EVDD and the pull-down power supply EVSS, enabling the light-emitting element L1 to emit light. The luminous current Id, which is positively correlated with the luminous intensity, is determined by the potentials of node P1 and node P2. The potential of node P1 is Vdata0 + Vth_Td, and the potential of node P2 is the potential EVDD0 of the pull-up power supply signal provided by the pull-up power supply EVDD. Accordingly, based on the current calculation formula, Id = K(Vdata0 - EVDD0). 2K is determined by the inherent characteristics of transistor T8, such as its width-to-length ratio W / L, capacitance Cox, and mobility μ. That is, the luminous current transmitted from the pixel circuit to the light-emitting element L1 can be independent of the threshold voltage Vth_Td of the driving transistor. Therefore, the drift of the threshold voltage Vth_Td of transistor T8 will not affect the luminous brightness of the light-emitting element L1, ensuring a good luminous effect for the light-emitting element L1.

[0096] It is understandable that, based on the above introduction to the driving principle, transistors T1 and T2 can be called data writing transistors, transistors T3, T6 and T7 can be called reset transistors, transistors T4 and T5 can be called light-emitting control transistors, and transistor T8 can be called driving transistors.

[0097] Based on this, as described above, the output signal terminal OUT_n of the shift register unit can be connected to the light emission control terminal EM of the pixel circuit (e.g., EM_N and EM_P shown in Figure 2), and used to provide the required light emission control signal to the light emission control terminal EM. For example, it can provide the inverted P-type light emission control signal and N-type light emission control signal shown in Figure 3 to drive transistors T4 and T5 in Figure 2, respectively. Alternatively, the output signal terminal OUT_n of the shift register unit can also be connected to the reset signal terminal Reset of the pixel circuit (e.g., Reset1, Reset2, and Reset3 shown in Figure 2), and used to provide a reset signal to the reset signal terminal Reset. For example, it can provide the reset signal shown in Figure 3.

[0098] Of course, it is not limited to satisfying the timing shown in Figure 3. Nor is it limited to providing a reset signal and a light emission control signal. For example, in some other embodiments, the output signal terminal OUT_n of the shift register unit can also be connected to the gate signal terminal Gate of the pixel circuit (e.g., Gate_N or Gate_P shown in Figure 2) and used to provide a gate drive signal to the gate signal terminal Gate.

[0099] Next, referring to the circuit layout diagram shown in Figure 4, it can be seen that in the layout, the output control circuit 02 and the input control circuit 01 are arranged sequentially along the first direction X1 and towards the pixel. The reset control line Trst, the first clock line CB, and the second clock line CKn are arranged sequentially along the first direction X1 and towards the pixel, and the reset control line Trst, the first clock line CB, and the second clock line CKn all extend along the second direction Y1.

[0100] The second direction Y1 can intersect with the first direction X1. For example, the first direction X1 can be the row direction of pixels, the second direction Y1 can be the column direction of pixels, and the first direction X1 and the second direction Y1 can be perpendicular to each other.

[0101] It is understandable that the layout shown in Figure 4 not only facilitates the connection between signal lines and circuits, but also allows for a relatively concentrated and compact arrangement of various circuits without wasting space, thus facilitating the narrow bezel design of the display device.

[0102] In summary, this disclosure provides a shift register unit. The shift register unit includes an input control circuit and an output control circuit. The input control circuit can control the potential of the input node under the control of a clock signal; the output control circuit can output a display driving signal to the pixel through an output signal terminal to drive the pixel to emit light, based on the potential of the input node and a reset control signal. Thus, by flexibly setting the clock signal and reset control signal, the shift register unit can output a display driving signal matching the P-type transistor and / or N-type transistor in the pixel. Furthermore, since the output control circuit and the input control circuit are arranged sequentially along a first direction and in a direction close to the pixel, and the signal lines connecting the output control circuit and the input control circuit are arranged sequentially along the first direction and in a direction close to the pixel, and all signal lines extend along a second direction intersecting the first direction, it also facilitates the narrow bezel design of the display device.

[0103] Optionally, Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. As shown in Figure 5, the shift register unit may further include: a drive enhancement circuit 03.

[0104] The drive enhancement circuit 03 can be connected between the output control circuit 02 and the output signal terminal OUT_n, and can be used to invert the potential of the signal output by the output control circuit 02 at least once before outputting it to the output signal terminal OUT_n. In this way, the driving capability of the shift register unit can be enhanced.

[0105] Optionally, based on Figure 5 and referring to the layout shown in Figure 4, it can be seen that the drive enhancement circuit 03 and at least one of the input control circuit 01 and output control circuit 02 can be arranged sequentially along the second direction Y1. This facilitates the connection between signal lines and circuits and is beneficial for the narrow bezel design of the display device.

[0106] For example, a portion of the drive enhancement circuit 03 can be arranged sequentially with the input control circuit 01 along the second direction Y1, and another portion of the drive enhancement circuit 03 can be arranged sequentially with the output control circuit 02 along the second direction Y1. The drive enhancement circuit 03 may also include a portion located on the side of the input control circuit 01 away from the output control circuit 02. That is, the drive enhancement circuit 03 can also be arranged sequentially with the input control circuit 01 and the output control circuit 02 along the first direction X1, and in a direction away from the pixel.

[0107] Optionally, referring to Figure 5, the shift register unit may also include a latch circuit 04.

[0108] The latch circuit 04 can be connected to the third clock line CK, the fourth clock line CBn, the input node Q_n, and the intermediate node Q1_n, respectively. It can control the switching between the intermediate node Q1_n and the input node Q_n in response to the third clock signal provided by the third clock line CK and the fourth clock signal provided by the fourth clock line CBn. Furthermore, it inverts the potential of the intermediate node Q1_n and outputs it to the input node Q_n. The intermediate node Q1_n can serve as the connection node between the drive enhancement circuit 03 and the output control circuit 02.

[0109] For example, the latch circuit 04 can control the intermediate node Q1_n to conduct with the input node Q_n when the potential of the third clock signal is the first potential and the potential of the fourth clock signal is the first potential, and simultaneously output the potential of the intermediate node Q1_n after inverting it to the input node Q_n; and the latch circuit 04 can control the intermediate node Q1_n to disconnect from the input node Q_n when the potential of the third clock signal is the second potential or the potential of the fourth clock signal is the second potential. In this way, the potential of the input node Q_n can be the same as the potential of the intermediate node Q1_n, which achieves the purpose of latching the potential of the input node Q_n, or it can be said that the latch circuit 04 can store the potential of the input node Q_n to prevent leakage of the potential of the input node Q_n.

[0110] Optionally, in some embodiments, the first clock line CB and the fourth clock line CBn can be shared, and the second clock line CKn and the third clock line CK can be shared. For example, the first clock line CB and the fourth clock line CBn can both be the fourth clock line CBn, and the second clock line CKn and the third clock line CK can both be the second clock line CKn.

[0111] Optionally, based on this, referring to the layout shown in Figure 4, the latch circuit 04 can be located between the drive enhancement circuit 03, and at least one of the input control circuit 01 and the output control circuit 02. The third clock line CK and the fourth clock line CBn can be located on the side of the reset control line Trst closer to the pixel, and the third clock line CK and the fourth clock line CBn can be arranged sequentially along the first direction X1 and along the direction closer to the pixel, and both the third clock line CK and the fourth clock line CBn can extend along the second direction Y1. This facilitates the connection between signal lines and circuits and is beneficial for the narrow bezel design of the display device.

[0112] For example, a portion of the latch circuit 04 may be located between the drive enhancement circuit 03 and the input control circuit 01, and another portion of the latch circuit 04 may be located between the drive enhancement circuit 03 and the output control circuit 02.

[0113] Optionally, based on the structure shown in Figure 4 above, Figure 6 shows a schematic diagram of the circuit structure of a shift register unit. As shown in Figure 6, the input control circuit 01 may include: a first transmission gate Tg1. The output control circuit 02 may include: a NOR gate. The latch circuit 04 may include: a first NOT gate INV1 and a second transmission gate Tg2. The drive enhancement circuit 03 may include: three second NOT gates INV2-1, INV2-2, and INV2-3. Here, the NOT gate can also be called an inverter, and the transmission gate can also be called a transmission switch.

[0114] The first transmission gate Tg1 can be connected between the input signal terminal IN_n and the input node Q_n, and can also be connected to the first clock line CB and the second clock line CKn respectively. The two input terminals of the NOR gate can be connected to the input node Q_n and the reset control line Trst respectively, and the output terminal of the NOR gate can be connected to the intermediate node Q1_n. The input terminal of the first NOT gate INV1 can be connected to the intermediate node Q1_n, and the output terminal of the first NOT gate INV1 can be connected to the input node Q_n through the second transmission gate Tg2, which can also be connected to the third clock line CK and the fourth clock line CBn respectively. Three second NOT gates INV2-1, INV2-2, and INV2-3 can be connected in series between the intermediate node Q1_n and the output signal terminal OUT_n.

[0115] That is, in some embodiments, the drive enhancement circuit 03 can invert the potential of the output signal of the output control circuit 02 an odd number of times before outputting it to the output signal terminal OUT_n. In other words, the drive enhancement circuit 03 can control the potential of the output signal terminal OUT_n to be opposite to the potential of the output signal of the output control circuit 02.

[0116] Of course, in some other embodiments, the drive enhancement circuit 03 can also invert the potential of the output signal of the output control circuit 02 an even number of times before outputting it to the output signal terminal OUT_n. That is, the drive enhancement circuit 03 can control the potential of the output signal terminal OUT_n to be the same as the potential of the output signal of the output control circuit 02.

[0117] Alternatively, the output signal terminal OUT_n may include: a first output signal terminal OUTN_n and a second output signal terminal OUTP_n. The first output signal terminal OUTN_n can be connected to an N-type transistor in the pixel, and the second output signal terminal OUTP_n can be connected to a P-type transistor in the pixel. For example, referring to Figure 2, the first output signal terminal OUTN_n can be connected to the light emission control terminal EM_N, that is, it can be connected to the N-type transistor T5; the second output signal terminal OUTP_n can be connected to the light emission control terminal EM_P, that is, it can be connected to the P-type transistor T4. Correspondingly, the drive enhancement circuit 03 may include: two drive enhancement sub-circuits.

[0118] One drive enhancement sub-circuit can be connected between the output control circuit 02 and the first output signal terminal OUTN_n, and can be used to invert the potential of the output signal of the output control circuit 02 an even number of times before outputting it to the first output signal terminal OUTN_n. The other drive enhancement sub-circuit can be connected between the output control circuit 02 and the second output signal terminal OUTP_n, and can be used to invert the potential of the output signal of the output control circuit 02 an odd number of times before outputting it to the second output signal terminal OUTP_n. Optionally, in some embodiments, the two drive enhancement sub-circuits can share at least one second NOT gate INV2.

[0119] It is understandable that by setting the drive enhancement circuit 03 to include multiple second NOT gates INV2 connected in series, the driving capability of the output signal at the output signal terminal OUT_n can be amplified step by step, thus effectively enhancing the driving capability. Correspondingly, the second NOT gate INV2 can also be called an amplifier (AMP).

[0120] It can also be understood that the logic principle of the NOR gate is: all 0s output 1, any 1 outputs 0; that is, when the potentials of all received signals are low (0), the potential of the output signal can be controlled to be high (1); otherwise, as long as the potential of any received signal is high (1), the potential of the output signal is controlled to be low (0). Based on this, we can conclude that:

[0121] The output control circuit 02, including the NOR gate, can control the potential of the intermediate node Q1_n to be low (0) when the potential of the input node Q_n is high (1) and / or the potential of the reset control signal provided by the reset control line Trst is high (1); and the output control circuit 02, including the NOR gate, can control the potential of the intermediate node Q1_n to be high (1) when the potential of the input node Q_n is low (0) and the potential of the reset control signal provided by the reset control line Trst is low (0).

[0122] Understandably, in a scenario where the output signal terminal OUT_n is connected to the light-emitting control terminal EM to provide a light-emitting control signal to EM, the output signal terminal OUT_n can be identified as GP_n, and the intermediate node Q1_n can be identified as GNc_n. Furthermore, the connection node between the first NOT gate INV1 and the second transmission gate Tg2 can be identified as GPc_n. Correspondingly, the intermediate node Q1_n of the previous stage shift register unit can be identified as GNc_n-1, and the connection node between the first NOT gate INV1 and the second transmission gate Tg2 in the previous stage shift register unit can be identified as GPc_n-1. Moreover, the input signal terminal IN_n can be connected to node GPc_n-1 of the cascaded previous stage shift register unit. Of course, the input signal terminal IN_1 of the first stage shift register unit needs to be connected to the enable signal line STV to receive the enable signal from the enable signal line STV.

[0123] Furthermore, based on Figure 6 and referring to Figure 7, it can be seen that the NOR gate, the first NOT gate INV1, and the first second NOT gate INV2-1 can be arranged sequentially along the second direction Y1; the first transmission gate Tg1, the second transmission gate Tg2, and the second second NOT gate INV2-2 can be arranged sequentially along the second direction Y1; and the first second NOT gate INV2-1 to the third second NOT gate INV2-3 can be arranged sequentially along the first direction X1 and along the direction closer to the pixel. It is understood that the shift register unit described in this embodiment can be located on one side of the substrate, that is, each circuit device can be disposed on the substrate.

[0124] Optionally, the dimensions of the first second NOT gate INV2-1 to the third second NOT gate INV2-3 can be increased sequentially. Correspondingly, referring to Figure 7, it can also be seen that the orthogonal projection length of the third second NOT gate INV2-3 on the substrate can include the total orthogonal projection length of the other gate circuits on the substrate, excluding the third second NOT gate INV2-3. The length direction can be parallel to the second direction Y1. These other gate circuits can include, for example, a NOR gate, a first NOT gate INV1, and a first second NOT gate INV2-1 arranged sequentially along the second direction Y1.

[0125] As can be understood from Figure 6, the first second NOT gate INV2-1 can refer to the second NOT gate INV2 directly connected to the intermediate node Q1_n; the second second NOT gate INV2-1 can refer to the second NOT gate INV2 connected in series between the first second NOT gate INV2-1 and the third second NOT gate INV2-3; and the third second NOT gate INV2-3 can refer to the second NOT gate INV2 directly connected to the output signal terminal OUT_n. Correspondingly, the third second NOT gate INV2-3 can also refer to the last second NOT gate INV2.

[0126] It is also understood that, in conjunction with Figures 4 and 7, the arrangement provided by the embodiments of this disclosure can make good use of limited space to centrally set up multiple circuit components, thereby effectively reducing the width of the frame and thus improving the driving capability and stability of the shift register unit.

[0127] Optionally, based on Figure 6, Figure 8 shows a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this disclosure. Referring to Figure 8, it can be seen that the NOR gate, the first NOT gate INV1, and each of the second NOT gates INV2 can also be connected to the first power line VGH and the second power line VGL respectively, and can be used to operate based on the first power signal provided by the first power line VGH and the second power signal provided by the second power line VGL. Furthermore, the potential of the first power signal can be greater than the potential of the second power signal.

[0128] Optionally, the first power line VGH and the second power line VGL are located at least on both sides of the reset control line Trst in the first direction X1, and the first power line VGH and the second power line VGL can both extend along the second direction Y1.

[0129] For example, referring to Figure 7, in the first direction X1, for the NOR gate, NAND gate, and the first second NOT gate INV2-1, the first power supply line VGH and the second power supply line VGL can be shared and can be located on the left and right sides of the reset control line Trst. For the third second NOT gate INV2-3, the first power supply line VGH and the second power supply line VGL can be adjacent.

[0130] Optionally, the width of the first power line VGH and the width of the second power line VGL can both be greater than the width of the reset control line Trst. Alternatively, they can also be greater than the width of the enable signal line STV connected to the first-stage shift register unit. Optionally, the width of the first power line VGH connected to the third second NOT gate INV2-3 can be greater than the width of the first power line VGH connected to other gate circuits, and the width of the second power line VGL connected to the third second NOT gate INV2-3 can be greater than the width of the second power line VGL connected to other gate circuits. These other gate circuits can include at least one of: a NOR gate, a first NOT gate INV1, a second second NOT gate INV2-2, and a first first NOT gate INV2-1.

[0131] That is, in the embodiments of this disclosure, the widths of the reset control line Trst and the enable signal line STV can both be smaller than the width of the first power line VGH and smaller than the width of the second power line VGL. Optionally, in some embodiments, the widths of the reset control line Trst and the enable signal line STV can also be similar or equal.

[0132] For example, the width of the reset control line Trst is typically 3 to 10 micrometers (μm). For instance, the width of the reset control line Trst can be 4 μm. The widths of the first power line VGH and the second power line VGL are typically 5 to 30 μm. For example, the widths of the first power line VGH and the second power line VGL connected by the first second NOT gate INV2-1 and the second second NOT gate INV2-2 can both be 10 μm, while the widths of the first power line VGH and the second power line VGL connected by the third second NOT gate INV2-3 can be 30 μm.

[0133] Understandably, by making the power lines (including the first power line VGH and the second power line VGL) wider, the driving capability of the gate circuit can be enhanced. Furthermore, since the last second NOT gate INV2 is directly connected to the pixel via its output signal terminal OUT_n, making the power line connected to the last second NOT gate INV2 the widest possible enhances its driving capability. Also, by separating the power line connected to the last second NOT gate INV2 from those connected to other second NOT gates INV2, the problem of abnormal output caused by a negatively biased threshold voltage Vth of the N-type transistor can be resolved. For example, when the threshold voltage Vth of the N-type transistor is negatively biased, the normal output of the N-type transistor can be ensured by individually adjusting the power signal provided by the second power line VGL connected to the last second NOT gate INV2.

[0134] To distinguish them, the first power line VGH and the second power line VGL connected to other gate circuits in the figure are labeled as VGH1 and VGL1, respectively, while the first power line VGH and the second power line VGL connected to the last second NOT gate INV2 (that is, the third second NOT gate INV2-3) are labeled as VGH2 and VGL2, respectively.

[0135] Optionally, in some embodiments, among the plurality of second NOT gates INV2, the potential of the first power signal provided by the first power line VGH2 connected to the last second NOT gate INV2 can be greater than or equal to the potential of the first power signal provided by the first power line VGH1 connected to the other second NOT gates INV2. And / or, the potential of the second power signal provided by the second power line VGL2 connected to the last second NOT gate INV2 can be less than or equal to the potential of the second power signal provided by the second power line VGL2 connected to the other second NOT gates INV2. In this way, the charging and discharging speed of the second NOT gate INV2 directly connected to the output signal terminal OUT_n can be accelerated, thereby further improving the driving capability of the shift register unit, and reducing leakage current and saving power consumption.

[0136] That is, in one embodiment, a single VGH and a single VGL power supply can be used, meaning that any NOT gate in the shift register unit is connected to the same first power line VGH and second power line VGL. Alternatively, in another embodiment, a dual VGH and dual VGL power supply can be used. Of course, it is not limited to a dual VGH and dual VGL power supply.

[0137] Optionally, the first clock line CB, the second clock line CKn, the reset control line Trst, the third clock line CK, and the fourth clock line CBn can all be located on the same side of the output control circuit 02 away from the latch circuit 04, and can all extend along the second direction Y1. That is, referring to Figure 7, the signal lines connected to the shift register unit can all be located above the overall circuit structure.

[0138] Optionally, in some embodiments, the first clock line CB, the second clock line CKn, the reset control line Trst, the third clock line CK, and the fourth clock line CBn can be arranged at equal intervals in the first direction X1. That is, the spacing between any two adjacent signal lines can be a fixed spacing. For example, this fixed spacing can be greater than or equal to 3μm.

[0139] Optionally, based on the foregoing description, the shift register unit provided in this embodiment can actually be divided into two modules: an input shift module and a driver enhancement module. The input shift module may include: a first transmission gate Tg1, a NOR gate, a second transmission gate Tg2, and a first NOT gate INV1. The driver enhancement module may include: three second NOT gates INV2-1, INV2-2, and INV2-3.

[0140] Furthermore, as can be seen from Figures 4 and 7, relative to the area where the pixel is located, the input shifting module can be located in the upper left part of the layout, the driving enhancement module can be located in the lower right part of the layout, and the first second NOT gate INV2-1 and the second second NOT gate INV2-2 in the driving enhancement module can be arranged vertically or horizontally, and the third second NOT gate INV2-3 can be located at the far right end of the layout.

[0141] Optionally, in some embodiments, in the input shift module, the NOR gate can be located at the leftmost end, the first transmission gate Tg1 and the second transmission gate Tg2 can be located to the right of the NOR gate and arranged sequentially from top to bottom, and the first NOT gate INV1 can be located below the NOR gate. In the drive enhancement circuit, the first second NOT gate INV2-1 can be located below the first NOT gate INV1, and the first second NOT gate INV2-1, the second second NOT gate INV2-2, and the third second NOT gate INV2-3 can be arranged sequentially from left to right.

[0142] Optionally, referring to Figure 8, the first transmission gate Tg1 may include a first P-type transistor Tp_1 and a first N-type transistor Tn_1.

[0143] The gates of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can be connected to the first clock line CB and the second clock line CKn, respectively. The first terminals of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can both be connected to the input signal terminal IN_n. The second terminals of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can both be connected to the input node Q_n.

[0144] Optionally, referring to Figure 8, the NOR gate may include: a second P-type transistor Tp_2, a second N-type transistor Tn_2, a third P-type transistor Tp_3, and a third N-type transistor Tn_3.

[0145] Specifically, the gates of the second P-type transistor Tp_2 and the third N-type transistor Tn_3 can both be connected to the reset control line Trst. The first terminal of the second P-type transistor Tp_2 can be connected to the first power supply line VGH1. The second terminal of the second P-type transistor Tp_2 can be connected to the first terminal of the third P-type transistor Tp_3. The second terminals of the third P-type transistor Tp_3, the second N-type transistor Tn_2, and the third N-type transistor Tn_3 can all be connected to the intermediate node Q1_n. The first terminals of the second N-type transistor Tn_2 and the third N-type transistor Tn_3 can both be connected to the second power supply line VGL1. The gates of the third P-type transistor Tp_3 and the second N-type transistor Tn_2 can both be connected to the input node Q_n.

[0146] Optionally, referring to Figure 8, the first NOT gate INV1 may include a fourth P-type transistor Tp_4 and a fourth N-type transistor Tn_4, where the fourth N-type transistor Tn_4 can be a dual-gate transistor. The second transmission gate Tg2 may include a fifth P-type transistor Tp_5 and a fifth N-type transistor Tn_5. It is understood that by setting the fourth N-type transistor Tn_4 as a dual-gate transistor, leakage current during the output hold phase can be reduced, thereby reducing the power consumption of the shift register unit. Of course, other transistors can also be similarly set as dual-gate transistors.

[0147] Specifically, the gates of the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can both be connected to the intermediate node Q1_n. The first terminals of the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can be connected to the first power line VGH1 and the second power line VGL1, respectively. The second terminals of the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can both be connected to the first terminals of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5, respectively. The gates of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can both be connected to the third clock line CK and the fourth clock line CBn, respectively. The second terminals of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can both be connected to the input node Q_n.

[0148] Optionally, referring to Figure 8, the first second NOT gate INV2-1 may include: a sixth P-type transistor Tp_6 and a sixth N-type transistor Tn_6. The second second NOT gate INV2-2 may include: a seventh P-type transistor Tp_7 and a seventh N-type transistor Tn_7. The third second NOT gate INV2-3 may include: an eighth P-type transistor Tp_8 and an eighth N-type transistor Tn_8.

[0149] Specifically, the gates of the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6 can both be connected to the intermediate node Q1_n; the gates of the seventh P-type transistor Tp_7 and the seventh N-type transistor Tn_7 can both be connected to the second terminals of the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6; and the gates of the eighth P-type transistor Tp_8 and the eighth N-type transistor Tn_8 can both be connected to the second terminals of the seventh P-type transistor Tp_7 and the seventh N-type transistor Tn_7. The second terminals of the eighth P-type transistor Tp_8 and the eighth N-type transistor Tn_8 can both be connected to the output signal terminal OUT_n, and the first terminals of the sixth P-type transistor Tp_6, the seventh P-type transistor Tp_7, and the eighth P-type transistor Tp_8 can all be connected to the first power supply line VGH. The first terminals of the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, and the eighth N-type transistor Tn_8 can all be connected to the second power supply line VGL.

[0150] Specifically, the first terminals of the sixth P-type transistor Tp_6 and the seventh P-type transistor Tp_7 are connected to the first power supply line VGH1, and the first terminal of the eighth P-type transistor Tp_8 is connected to the first power supply line VGH2. The first terminals of the sixth N-type transistor Tn_6 and the seventh N-type transistor Tn_7 are connected to the second power supply line VGL1, and the first terminal of the eighth N-type transistor Tn_8 is connected to the second power supply line VGL2.

[0151] That is, the shift register unit provided in some embodiments of this disclosure may include 16 TFTs in total, consisting of 8 PMOS TFTs and 8 NMOS TFTs. However, it is not limited to only these 16 TFTs; the shift register unit provided in this disclosure can be derived by combining and reducing basic modules. For example, in some embodiments, the shift register unit may also include other gate circuits (e.g., NOT gates / NAND gates) connected between the intermediate node Q1_n and the drive enhancement circuit 04.

[0152] Optionally, taking the structure shown in Figure 8 as an example, Figure 9 shows a layout schematic of a shift register unit. Combining Figures 8 and 9, it can be seen that the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can be arranged sequentially along the first direction X1 and along the direction closest to the pixel.

[0153] The third P-type transistor Tp_3 and the second P-type transistor Tp_2 can be arranged and connected in series along the second direction Y1 and along the direction close to the first NOT gate INV1. The second N-type transistor Tn_2 can be located on the side of the third P-type transistor Tp_3 away from the second P-type transistor Tp_2. The third N-type transistor Tn_3 can be located on the side of the third P-type transistor Tp_3 close to the second P-type transistor Tp_2. Both the second N-type transistor Tn_2 and the third N-type transistor Tn_3 are closer to the pixel than the third P-type transistor Tp_2.

[0154] The fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can be arranged sequentially along the first direction X1 and along the direction closer to the pixel. The fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can be arranged sequentially along the first direction X1 and along the direction closer to the pixel. The fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 are both closer to the first transmission gate Tg1 than the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4.

[0155] Furthermore, the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6 can be arranged sequentially along the first direction X1 and along the direction closer to the pixel, the seventh P-type transistor Tp_7 and the seventh N-type transistor Tn_7 can be arranged sequentially along the second direction Y1 and along the direction away from the first transmission gate Tg1, and the eighth P-type transistor Tp_8 and the eighth N-type transistor Tn_8 can be arranged sequentially along the second direction Y1.

[0156] That is, referring to Figure 9, in this embodiment of the NOR gate, the four TFTs can be arranged vertically, and two of the four TFTs, P-type TFTs, can be connected in series, while the two N-type TFTs can be located on the upper and lower sides of the two P-type TFTs. Based on the vertical arrangement of the first transmission gate Tg1 and the second transmission gate Tg2, TFTs of the same type (i.e., P-type or N-type) can be located on the same side to facilitate connection between TFTs. The clock line can be located near the top of the P-type and N-type TFTs for easy connection. The first NOT gate INV1 is located in the middle of the layout, facilitating connection with the preceding module and transmission to the next level. The N-type and P-type TFTs can be arranged horizontally, and as mentioned above, the N-type TFTs can be a dual-gate design to reduce leakage current, thereby reducing the power consumption of the shift register unit. In the first second NOT gate INV2-1, the N-type TFT and P-type TFT can be placed horizontally, and their gate holes can be arranged in a straight line. In the second second NOT gate INV2-2 and the third second NOT gate INV2-3, the N-type TFT and P-type TFT in each second NOT gate INV2 can be placed vertically as shown in Figure 9, or they can be placed horizontally. Alternatively, the N-type TFT and P-type TFT in one second NOT gate INV2 can be placed horizontally, while the N-type TFT and P-type TFT in the other second NOT gate INV2 can be placed vertically. This can be determined according to the layout space.

[0157] Furthermore, as shown in Figure 9, the sizes of the transistors in the first second NOT gate INV2-1 to the third second NOT gate INV2-3 can be increased sequentially. That is, the sizes of the first second NOT gate INV2-1 to the third second NOT gate INV2-3 described above can be increased sequentially. Here, transistors can refer to P-type transistors and / or N-type transistors.

[0158] Understandably, the channel width of a transistor can characterize its size. Taking an N-type transistor as an example, the channel width of the transistor in the first NOT gate INV2-1 can be 2 to 15 μm; for example, the channel width of the transistor in the first NOT gate INV2-1 can be 8 μm. The channel width of the transistor in the second NOT gate INV2-2 can be approximately 1.5 to 10 times that of the transistor in the first NOT gate INV2-1; for example, the channel width of the transistor in the second NOT gate INV2-2 can be 30 μm. The channel width of the transistor in the third NOT gate INV2-3 can be the largest and can be determined by the pixel load it is connected to; for example, the channel width of the transistor in the third NOT gate INV2-3 can be 60 μm.

[0159] Of course, the N-type and P-type transistors in each second NOT gate INV2 can have the same or different dimensions, which can be determined by the mobility. For example, taking the third second NOT gate INV2-3 as an example, the mobility of its P-type transistor (i.e., the eighth P-type transistor Tp_8) can be 1 / 3 of the mobility of the N-type transistor (i.e., the eighth N-type transistor Tn_8), and correspondingly, the channel width of its P-type transistor can be 1 / 3 of the channel width of its N-type transistor.

[0160] Furthermore, the transistors in the first transmission gate Tg1, the NOR gate, the first NOT gate INV1, and the second transmission gate Tg2 can all be smaller than the transistors in any of the second NOT gates INV2. That is, except for the first to third second NOT gates INV2-3, the transistors in other gate circuits can all be relatively small. For example, the transistors in other gate circuits can be roughly the size of a switching transistor, and the channel width can be between 2 and 10 μm.

[0161] It is understood that the layouts shown in Figures 7 and 9 are merely illustrative, and any adjustments made based on them to facilitate narrow bezel design are applicable to the embodiments disclosed herein.

[0162] Optionally, based on Figure 9, Figures 10 to 17 show schematic diagrams of different film layer structures for a shift register unit. Referring to Figures 9 to 17, it can be seen that the transistor in the shift register unit provided in this embodiment may include: a first active layer Poly, a first gate metal layer GATE1, a second gate metal layer GATE2, a second active layer IGZO, a third gate metal layer GATE3, a first source / drain metal layer SD1, and a second source / drain metal layer SD2, stacked sequentially. These films can all be located on one side of the substrate.

[0163] The first active layer SD1 can be used as the active layer of the P-type transistor in the shift register unit, and the second active layer IGZO can be used as the active layer of the N-type transistor in the shift register unit.

[0164] It is understood that "Poly" can refer to an active layer formed using polycrystalline silicon, and "IGZO" refers to an active layer formed using indium gallium zinc oxide. Of course, in some other embodiments, other materials can be used to form the first active layer, and other materials can also be used to form the second active layer.

[0165] It is also understandable that, taking the third second NOT gate INV2-3 as an example, since the size of the P-type transistor is generally smaller than that of the N-type transistor, it can be seen from Figures 10 and 13 that in the third second NOT gate INV2-3, the size of the active layer (i.e., the first active layer Poly) of the P-type transistor (i.e., the eighth P-type transistor Tp_8) is smaller than the size of the active layer (i.e., the second active layer IGZO) of the N-type transistor (i.e., the eighth N-type transistor Tn_8). Here, the size can refer to the area of ​​the active layer projected onto the substrate. The sizes of the active layers of the P-type transistors and N-type transistors in other gate circuits are similar and will not be elaborated further.

[0166] Optionally, a first interlayer dielectric layer (ILD) and a second interlayer dielectric layer (EBB) may be further included between the third gate metal layer (GATE3) and the first source / drain metal layer (SD1). The first interlayer dielectric layer (ILD) may have multiple vias (K1) for overlapping of the films located on both sides of the ILD. The second interlayer dielectric layer (EBB) may have multiple vias (K2) for overlapping of the films located on both sides of the EBB. It is understood that the vias (K1) in the first interlayer dielectric layer (ILD) can be used for overlapping of the films between P-type transistors. The vias (K2) in the second interlayer dielectric layer (EBB) can be used for overlapping of the films between N-type transistors. Furthermore, a passivation layer (PVX) and a planarization layer (PLN) may be sequentially stacked between the first source / drain metal layer (SD1) and the second source / drain metal layer (SD2). The passivation layer (PVX) and the planarization layer (PLN) may have multiple third vias (K3) for overlapping of the films located on both sides of the passivation layer (PVX) and the planarization layer (PLN). Correspondingly, vias K1, K2, and K3 can also be called connection vias.

[0167] Based on this, it can be understood that the gate via in the first second NOT gate INV2-1 described above can refer to: the via between the first gate metal layer GATE1 and the source / drain metal layer SD; the via between the second gate metal layer GATE2 and the source / drain metal layer SD; and the via between the third gate metal layer GATE3 and the source / drain metal layer SD. Here, the source / drain metal layer can be, for example, the first source / drain metal layer.

[0168] Optionally, in this embodiment of the disclosure, each connection via can be located away from the second source / drain metal layer SD2, thereby reducing the parasitic capacitance formed between the second source / drain metal layer SD2 and other metal layers (e.g., the first source / drain metal layer). Furthermore, each connection via can be staggered, meaning their orthogonal projections on the substrate do not overlap.

[0169] Optionally, in some embodiments, as shown in FIG18, at least a portion of the first source / drain metal layer SD1 may be reused with at least one of the first active layer Poly, the first gate metal layer GATE1, the second gate metal layer GATE2, and the second active layer IGZO to reduce the overlap area between the first source / drain metal layer SD1 and the second source / drain metal layer SD2.

[0170] That is, the first source-drain metal layer SD1 can be replaced by any layer on the side of the first source-drain metal layer SD1 away from the second source-drain metal layer SD2, thereby reducing the overlap area between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, and thus reducing the parasitic capacitance formed between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, which is beneficial to further reduce the operating power consumption of the shift register unit. Of course, in some other embodiments, the same purpose can also be achieved by reducing some of the redundant vias and redundant first source-drain metal layers SD1.

[0171] Optionally, based on Figure 18, Figures 19 to 26 show different film layer structures for the shift register unit. Comparing Figures 13 and 12 with Figures 9 and 18, it can be seen that at position 1, the second active layer IGZO can be reused as the first source / drain metal layer SD1 at that position. Comparing Figures 11 and 20, it can be seen that at position 2, the first gate metal layer GATE1 can be reused as the first source / drain metal layer SD1 at that position. Comparing Figures 14 and 23, it can be seen that at position 3, the third gate metal layer GATE3 can be reused as the first source / drain metal layer SD1 at that position. All of these examples can reduce the overlap area of ​​the first source / drain metal layer SD1 and the second source / drain metal layer SD2, thereby reducing parasitic capacitance and lowering power consumption.

[0172] It is understandable that, referring to Figure 8, position 1 could refer to the location of the connection node between the first NOT gate INV1 and the second transmission gate Tg2, i.e., the location of node GPc_n. Position 2 could refer to the location of the connection node between the third P-type transistor Tp_3 and the second P-type transistor Tp_2 in the NOR gate. Position 3 could refer to the location of the connection node between the first second NOT gate INV2-1 and the NOR gate, i.e., the location of the intermediate node Q1_n.

[0173] It can also be understood that, compared to the structure shown in Figure 9, the structure shown in Figure 18, at position 1, can be considered as increasing the area of ​​the second active layer IGZO to reduce the area of ​​the first source / drain metal layer SD1. At position 2, it can be considered as increasing the area of ​​the first gate metal layer GATE1 to reduce the area of ​​the first source / drain metal layer SD1. At position 3, it can be considered as increasing the area of ​​the third gate metal layer GATE3 to reduce the area of ​​the first source / drain metal layer SD1. Of course, the above methods are all illustrative. In some embodiments, other film layers can also be reused as the first source / drain metal layer SD1 to achieve the purpose of reducing the overlap area of ​​the first source / drain metal layer SD1 and the second source / drain metal layer SD2.

[0174] Optionally, based on the transistor arrangement of the embodiments of this disclosure, and referring to Figures 9 and 10, it can also be seen that: the first active layer Poly of the second P-type transistor Tp_2 and the third P-type transistor Tp_3 can be a whole (i.e., they can be shared); the first active layer Poly of the first P-type transistor Tp_1 and the fifth P-type transistor Tp_5 can be shared. Furthermore, referring to Figures 9 and 13, it can be seen that the second active layer IGZO of the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5 can be shared.

[0175] Optionally, based on the transistor arrangement of this embodiment, an active layer is reused as the first source / drain metal layer SD1. Referring to Figures 18 and 22, it can be seen that, in addition to the shared second active layer IGZO of the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5, the second active layer IGZO of the fourth N-type transistor Tn_4 and the fifth N-type transistor Tn_5 can also be shared. That is, the second active layer IGZO of the first N-type transistor Tn_1, the fourth N-type transistor Tn_4, and the fifth N-type transistor Tn_5 can be a single unit.

[0176] Understandably, by sharing an active layer, the structure can be simplified and costs can be saved, while also facilitating narrow bezel design.

[0177] It should be noted that the layouts shown in Figures 9 to 17 are layouts of two adjacent shift register units (e.g., the nth-level shift register unit GOAn and the (n+1)th-level shift register unit GOAn+1). The layouts shown in Figures 10 to 26 are layouts of a single shift register unit (e.g., the nth-level shift register unit GOAn).

[0178] Based on the above description, the shift register unit provided in this embodiment can be a CMOS EM / Preset GOA circuit. EM refers to the light-emitting control terminal connected to the light-emitting control transistor in the pixel, and Preset refers to the reset signal terminal connected to the P-type reset transistor in the pixel. CMOS can be a circuit capable of outputting the required display driving signals to both the P-type and N-type transistors in the pixel. The N-type transistor in the shift register unit can be responsible for low-level output, and the P-type transistor can be responsible for high-level output. Furthermore, the layout of this CMOS EM / Preset GOA is compact and concentrated, which can help reduce the bezel width and improve driving capability and circuit stability.

[0179] In summary, this disclosure provides a shift register unit. The shift register unit includes an input control circuit and an output control circuit. The input control circuit can control the potential of the input node under the control of a clock signal; the output control circuit can output a display driving signal to the pixel through an output signal terminal to drive the pixel to emit light, based on the potential of the input node and a reset control signal. Thus, by flexibly setting the clock signal and reset control signal, the shift register unit can output a display driving signal matching the P-type transistor and / or N-type transistor in the pixel. Furthermore, since the output control circuit and the input control circuit are arranged sequentially along a first direction and in a direction close to the pixel, and the signal lines connecting the output control circuit and the input control circuit are arranged sequentially along the first direction and in a direction close to the pixel, and all signal lines extend along a second direction intersecting the first direction, it also facilitates the narrow bezel design of the display device.

[0180] This disclosure also provides a method for driving a shift register unit, which can be used to drive a shift register unit as described above. As shown in FIG27, the method includes:

[0181] Step 2701, First stage: Provide a first clock signal with a first potential to the first clock line, provide a second clock signal with a first potential to the second clock line, and provide a reset control signal with a first potential to the reset control line. The input control circuit responds to the first clock signal and the second clock signal with the first potential to control the input signal terminal to be connected to the input node. The output control circuit controls the potential of the output signal terminal based on the potential of the input node and the reset control signal with the first potential.

[0182] Step 2702, Second Stage: Provide a first clock signal of the second potential to the first clock line, provide a second clock signal of the second potential to the second clock line, and provide a reset control signal of the second potential to the reset control line. The input control circuit responds to the first clock signal of the second potential and the second clock signal of the second potential by controlling the input signal terminal to disconnect from the input node. The output control circuit controls the potential of the output signal terminal based on the potential of the input node and the reset control signal of the second potential.

[0183] Step 2703, the third stage, provides a first clock signal with a first potential to the first clock line, a second clock signal with a first potential to the second clock line, and a reset control signal with a second potential to the reset control line. The input control circuit responds to the first clock signal with the first potential and the second clock signal with the first potential, and controls the input signal terminal to be connected to the input node. The output control circuit controls the potential of the output signal terminal based on the potential of the input node and the reset control signal with the second potential.

[0184] Alternatively, taking the structures shown in Figures 6 and 8 as examples, Figure 28 shows a schematic diagram of the driving timing of a shift register unit.

[0185] First, referring to Figure 28, it shows four sets of clock signals: CK, CBn, CB, and CKn, with a period of 2H. The clock signals provided by CK and CB can differ by 1H, the clock signals provided by CKn and CB can be inverted signals, and the clock signals provided by CBn and CK can also be inverted signals. Furthermore, Figure 28 also shows the timing of dual VGH1 / VGH2 and dual VGL1 / VGL2.

[0186] Secondly, referring to Figure 27, the driving principle of the shift register unit is explained as follows:

[0187] (1) In the first stage t01, a low-level first clock signal can be provided to the first clock line CB, and a high-level second clock signal can be provided to the second clock line CKn, so that the first transmission gate Tg1 is turned on, thereby turning on the input signal terminal IN_n and the input node Q_n. The input signal terminal IN_n can output an input signal to the input node Q_n. At this time, the potential of the input signal can be high (e.g., the potential of the turn-on signal provided by the turn-on signal line STV). In addition, a high-level reset control signal can be provided to the reset control line Trst, which can then control the potential of node GNc_n (i.e., intermediate node Q1_n) to low after passing through the NOR gate, and then control the potential of node GPc_n to high after passing through the first NOT gate INV1, and control the potential of the output signal terminal GP_n to high after passing through three second NOT gates INV2. Furthermore, a high-potential third clock signal can be provided to the third clock line CK, and a low-potential fourth clock signal can be provided to the fourth clock line CBn, causing the second transmission gate Tg2 to turn off, thereby disconnecting node GPc_n from input node Q_n.

[0188] As can be understood, as shown in Figure 28, the pulse widths of the low-level clock signals provided by clock line CK and clock line CB are both shorter than the pulse widths of the high-level clock signals, generally about 0 to 2 μs shorter than 1H. This can be flexibly selected based on the load RC. Based on this setting, as mentioned earlier, the clock delay effect can be eliminated, avoiding the risk of a race between the NOR gate in the output control sub-circuit 02 and the first NOT gate INV1 in the latch circuit 04 during input state switching, which would otherwise occur when the first transmission gate Tg1 and the second transmission gate Tg2 are simultaneously turned on.

[0189] (2) In the second stage t02, a high-level first clock signal can be provided to the first clock line CB, and a low-level second clock signal can be provided to the second clock line CKn, causing the first transmission gate Tg1 to turn off, thereby disconnecting the input signal terminal IN_n from the input node Q_n. A low-level third clock signal can be provided to the third clock line CK, and a high-level fourth clock signal can be provided to the fourth clock line CBn, causing the second transmission gate Tg2 to turn on, thereby turning the node GPc_n on with the input node Q_n, thus latching the potential of the input node Q_n to the high potential of the node GPc_n. In addition, a low-level reset control signal can be provided to the reset control line Trst, so after passing through the NOR gate, the potential of the node GNc_n can be controlled to be low, after passing through the first NOT gate INV1, the potential of the node GPc_n can be controlled to be high, and after passing through three second NOT gates INV2, the potential of the output signal terminal GP_n can be controlled to be high.

[0190] (3) In the third stage t03, a low-level first clock signal can be provided to the first clock line CB, and a high-level second clock signal can be provided to the second clock line CKn, causing the second transmission gate Tg2 to open, thereby enabling the input signal terminal IN_n to conduct with the input node Q_n. The input signal terminal IN_n can output an input signal to the input node Q_n, and the potential of the input signal can be low at this time. In addition, a low-level reset control signal can be provided to the reset control line Trst, which can then control the potential of node GNc_n to be high after passing through the NOR gate, then control the potential of node GPc_n to be low after passing through the first NOT gate INV1, and finally control the potential of the output signal terminal GP_n to be low after passing through three second NOT gates INV2. Furthermore, a high-level third clock signal can be provided to the third clock line CK, and a low-level fourth clock signal can be provided to the fourth clock line CBn, causing the second transmission gate Tg2 to close, thereby disconnecting node GPc_n from the input node Q_n.

[0191] It is understood that Figure 28 can be applied to provide display drive signals to the PMOS TFT in the pixel, and the effective potential width of the display drive signal output by Figure 28 is 2H.

[0192] Optionally, the shift register unit can also be connected to a display driver IC (DDIC) and used to receive the aforementioned signals, such as clock signals, provided by the DDIC. That is, the DDIC can provide the required signals to the signal terminals connected to the shift register unit so that the shift register unit can output the required display driving signals to the pixels.

[0193] It is understandable that, since the driving method of the shift register unit can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the driving method of the shift register unit will not be repeated here for the sake of brevity.

[0194] This disclosure also provides a display driving circuit. As shown in FIG29, the display driving circuit includes at least two cascaded shift register units (GOAs) as described above.

[0195] For example, the shift register unit GOA shown in Figure 29 is an EM GOA that provides the light emission control signal, meaning that the output signal terminal OUT_n is connected to the light emission control terminal EM of the pixel. Accordingly, the display driver circuit including this EM GOA can also be called a light emission control circuit.

[0196] Furthermore, the display driver circuit shown in Figure 27 uses four sets of clock signals (including CK, CB, CKn and CBn, a total of four clock signal terminals), and is powered by dual VGH and dual VGL (including the first power supply terminals VGH1 and VGH2, and the second power supply terminals VGL1 and VGL2).

[0197] Furthermore, the cascading configuration is shown as follows: the input signal IN_1 of the first-stage shift register unit EM GOA is connected to the enable signal line STV, and the input signal IN_n of other-stage shift register units EM GOA is connected to the node GPc_n of the previous-stage shift register unit EM GOA. For the design of other structures, please refer to the relevant descriptions of the shift register units mentioned above; they will not be elaborated upon here.

[0198] Optionally, in some embodiments, a dummy shift register unit, i.e., a dummy GOA, may be added to the first or last line to meet the required timing requirements or drive the load.

[0199] It is understood that since the display driving circuit can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the display driving circuit will not be described again here for the sake of brevity.

[0200] This disclosure also provides a display device. As shown in FIG30, the display device includes: a display panel 10, and a display driving circuit 00 as shown in FIG29.

[0201] The display panel 10 may include multiple pixels (not shown in Figure 30). The display driving circuit 00 is connected to the multiple pixels and is used to transmit light emission control signals to the multiple pixels to drive the multiple pixels to emit light. For example, referring to Figure 2, the display driving circuit 00 may be connected to the light emission control terminal EM of the multiple pixels and is used to transmit the light emission control signals shown in Figure 3 to the multiple pixels, thereby driving the multiple pixels to emit light.

[0202] Optionally, the display device can be any product or component with display functionality, such as an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, or any other display device. Furthermore, the display device can also be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-readers.

[0203] It is understood that since the display device can have essentially the same technical effect as the shift register unit described in the various embodiments above, the technical effect of the display device will not be described again here for the sake of brevity.

[0204] It is understood that the terminology used in the embodiments of this disclosure is for illustrative purposes only and is not intended to limit the disclosure. Unless otherwise defined, the technical or scientific terms used in the implementation of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains.

[0205] For example, the use of words such as "first," "second," "third," and similar terms does not indicate any order, quantity, or importance, but is merely used to distinguish different components.

[0206] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0207] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0208] The word “connection” or “link” is not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0209] "Up," "down," "left," and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0210] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0211] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A shift register unit, comprising: an input control circuit connected with a first clock line, a second clock line, an input signal terminal and an input node respectively, and configured to control the on-off of the input signal terminal and the input node in response to a first clock signal provided by the first clock line and a second clock signal provided by the second clock line; an output control circuit connected with the input node, a reset control line and an output signal terminal respectively, and configured to control the potential of the output signal terminal based on the potential of the input node and a reset control signal provided by the reset control line, so as to output a display driving signal to a P-type transistor and / or an N-type transistor of each pixel in at least one row of pixels through the output signal terminal, so as to drive a light emitting element of the each pixel to emit light; wherein the output control circuit and the input control circuit are arranged in a first direction and close to the pixels; the reset control line, the first clock line and the second clock line are arranged in the first direction and close to the pixels, and the reset control line, the first clock line and the second clock line all extend in a second direction; the second direction intersects the first direction.

2. The shift register cell of claim 1, wherein, The shift register unit further comprises: a driving enhancement circuit connected between the output control circuit and the output signal terminal, and configured to output the potential of the signal output by the output control circuit after at least one inversion processing, to the output signal terminal; wherein the driving enhancement circuit is arranged in the second direction and close to at least one of the input control circuit and the output control circuit.

3. The shift register cell of claim 2, wherein, The shift register unit further comprises: a latch circuit connected with a third clock line, a fourth clock line, the input node and an intermediate node respectively, and configured to control the on-off of the intermediate node and the input node in response to a third clock signal provided by the third clock line and a fourth clock signal provided by the fourth clock line, and output the potential of the intermediate node after inversion processing to the input node, the intermediate node being a connection node of the driving enhancement circuit and the output control circuit; wherein the latch circuit is located between the driving enhancement circuit and at least one of the input control circuit and the output control circuit; the third clock line and the fourth clock line are located on a side of the reset control line close to the pixels, and the third clock line and the fourth clock line are arranged in the first direction and close to the pixels, and the third clock line and the fourth clock line all extend in the second direction.

4. The shift register cell of claim 3, wherein, The input control circuit comprises a first transmission gate; the output control circuit comprises an NOR gate; the latch circuit comprises a first NOT gate and a second transmission gate; and the driving enhancement circuit comprises three second NOT gates. The first transmission gate is connected between the input signal end and the input node, and is also connected with the first clock line and the second clock line respectively; two input ends of the NOR gate are connected with the input node and the reset control line respectively, and an output end of the NOR gate is connected with the intermediate node; an input end of the first NOT gate is connected with the intermediate node, and an output end of the first NOT gate is connected with the input node through the second transmission gate, and the second transmission gate is also connected with the third clock line and the fourth clock line respectively; the three second NOT gates are connected in series between the intermediate node and the output signal end in sequence; The NOR gate, the first NOT gate and the first second NOT gate are arranged in sequence along the second direction, the first transmission gate, the second transmission gate and the second second NOT gate are arranged in sequence along the second direction, the first second NOT gate to the third second NOT gate are arranged in sequence along the first direction and the direction close to the pixel, and the size of the first second NOT gate to the third second NOT gate increases in sequence.

5. The shift register cell of claim 4, wherein, The NOR gate, the first NOT gate and each second NOT gate are also connected with a first power supply line and a second power supply line respectively, and are used to work based on a first power supply signal provided by the first power supply line and a second power supply signal provided by the second power supply line, and the potential of the first power supply signal is greater than the potential of the second power supply signal; The first power supply line and the second power supply line are located at least on two sides of the reset control line in the first direction, and the first power supply line and the second power supply line extend along the second direction; the width of the first power supply line and the width of the second power supply line are greater than the width of the reset control line; the width of the first power supply line connected with the third second NOT gate is greater than the width of the first power supply line connected with other gate circuits, and the width of the second power supply line connected with the third second NOT gate is greater than the width of the second power supply line connected with the other gate circuits; the other gate circuits include at least one of the NOR gate, the first NOT gate, the second second NOT gate and the first first NOT gate.

6. The shift register cell of claim 4 or 5, wherein, The first transmission gate comprises a first P-type transistor and a first N-type transistor; The gate of the first P-type transistor and the gate of the first N-type transistor are connected with the first clock line and the second clock line respectively, the first pole of the first P-type transistor and the first pole of the first N-type transistor are connected with the input signal end, and the second pole of the first P-type transistor and the second pole of the first N-type transistor are connected with the input node; The first P-type transistor and the first N-type transistor are arranged in sequence along the first direction and the direction close to the pixel.

7. The shift register cell of any one of claims 4 to 6, wherein, The NOR gate comprises a second P-type transistor, a second N-type transistor, a third P-type transistor and a third N-type transistor; The gate of the second P-type transistor and the gate of the third N-type transistor are connected with the reset control line, the first electrode of the second P-type transistor is connected with the first power supply line, the second electrode of the second P-type transistor is connected with the first electrode of the third P-type transistor, the second electrode of the third P-type transistor, the second electrode of the second N-type transistor and the second electrode of the third N-type transistor are connected with the intermediate node, the first electrode of the second N-type transistor and the first electrode of the third N-type transistor are connected with the second power supply line, the gate of the third P-type transistor and the gate of the second N-type transistor are connected with the input node; And, the third P-type transistor and the second P-type transistor are arranged in sequence along the second direction and in a direction close to the first non-gate, the second N-type transistor is located on the side of the third P-type transistor away from the second P-type transistor, the third N-type transistor is located on the side of the third P-type transistor close to the second P-type transistor, and the second N-type transistor and the third N-type transistor are both close to the pixel relative to the third P-type transistor.

8. The shift register cell of any one of claims 4 to 7, wherein, The first non-gate comprises a fourth P-type transistor and a fourth N-type transistor, and the fourth N-type transistor is a double-gate transistor; the second transfer gate comprises a fifth P-type transistor and a fifth N-type transistor; The gate of the fourth P-type transistor and the gate of the fourth N-type transistor are connected with the intermediate node, the first electrode of the fourth P-type transistor and the first electrode of the fourth N-type transistor are connected with the first power supply line and the second power supply line respectively, the second electrode of the fourth P-type transistor and the second electrode of the fourth N-type transistor are connected with the first electrode of the fifth P-type transistor and the first electrode of the fifth N-type transistor, the gate of the fifth P-type transistor and the gate of the fifth N-type transistor are connected with the third clock line and the fourth clock line respectively, and the second electrode of the fifth P-type transistor and the second electrode of the fifth N-type transistor are connected with the input node; And, the fourth P-type transistor and the fourth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, the fifth P-type transistor and the fifth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, and the fifth P-type transistor and the fifth N-type transistor are both close to the first transfer gate relative to the fourth P-type transistor and the fourth N-type transistor.

9. A shift register cell as claimed in any one of claims 4 to 8, wherein, The first second non-gate comprises a sixth P-type transistor and a sixth N-type transistor; the second second non-gate comprises a seventh P-type transistor and a seventh N-type transistor; and the third second non-gate comprises an eighth P-type transistor and an eighth N-type transistor. The gate of the sixth P-type transistor and the gate of the sixth N-type transistor are connected with the intermediate node, the gate of the seventh P-type transistor and the gate of the seventh N-type transistor are connected with the second electrode of the sixth P-type transistor and the second electrode of the sixth N-type transistor, the gate of the eighth P-type transistor and the gate of the eighth N-type transistor are connected with the second electrode of the seventh P-type transistor and the second electrode of the seventh N-type transistor, the second electrode of the eighth P-type transistor and the second electrode of the eighth N-type transistor are connected with the output signal terminal, and the first electrode of the sixth P-type transistor, the first electrode of the seventh P-type transistor, and the first electrode of the eighth P-type transistor are connected with the first power supply line, and the first electrode of the sixth N-type transistor, the first electrode of the seventh N-type transistor, and the first electrode of the eighth N-type transistor are connected with the second power supply line. The sixth P-type transistor and the sixth N-type transistor are arranged in the first direction and in a direction close to the pixel, the seventh P-type transistor and the seventh N-type transistor are arranged in the second direction and in a direction away from the first transfer gate, and the eighth P-type transistor and the eighth N-type transistor are arranged in the second direction.

10. The shift register cell of any of claims 4 to 9, wherein, The sizes of the transistors in the first to third second NOT gates increase in turn. The sizes of the transistors in the first transfer gate, the NOR gate, the first NOT gate, and the second transfer gate are all smaller than the size of the transistors in any second NOT gate.

11. A shift register cell as claimed in any one of claims 3 to 10, wherein, The first clock line, the second clock line, the reset control line, the third clock line, and the fourth clock line are all located on the same side of the output control circuit away from the latch circuit and are arranged at equal intervals in the first direction.

12. The shift register cell of any one of claims 1 to 11, wherein, The transistors in the shift register unit include: a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked in turn. The first active layer is used as an active layer of a P-type transistor in the shift register unit, and the second active layer is used as an active layer of an N-type transistor in the shift register unit.

13. The shift register cell of claim 12, wherein, At least part of the first source-drain metal layer is multiplexed with at least one of the first active layer, the first gate metal layer, the second gate metal layer, and the second active layer to reduce the overlapping area of the first source-drain metal layer and the second source-drain metal layer.

14. A display drive circuit, the display drive circuit comprising: At least two shift register units as claimed in any of claims 1 to 13 are cascaded.

15. A display device comprising: A display panel and a display driving circuit as claimed in claim 14. The display panel includes a plurality of pixels, and the display driving circuit is connected with the plurality of pixels and is configured to transmit a light-emitting control signal to the plurality of pixels to drive the plurality of pixels to emit light.

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