TBC solar cell and preparation method therefor

Abstract

The present application relates to the technical field of solar cells. Disclosed are a TBC solar cell and a preparation method therefor. The TBC solar cell comprises an N-type silicon substrate, and a backlight surface of the N-type silicon substrate comprises a P-type region; and in the P-type region, a first tunneling layer, a P-type polysilicon layer, a first passivation anti-reflection layer and a first electrode layer are arranged in sequence outward from the backlight surface of the N-type silicon substrate, wherein the P-type polysilicon layer comprises a highly doped region and a lowly doped region, the lowly doped region surrounding the outer side of the highly doped region and coming into contact with the highly doped region, and the first electrode layer penetrates the first passivation anti-reflection layer and comes into contact with the highly doped region. The TBC solar cell provided in the present application can improve the back contact performance and can improve a short-circuit current parameter of cells.

Description

TBC Solar Cells and Their Fabrication Methods

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411033393.6, filed on July 30, 2024, entitled "TBC Solar Cell and Method for Preparation Thereof", the contents of which are incorporated herein by reference in part. Technical Field

[0003] This application relates to the field of solar cell technology, and in particular to a TBC solar cell and its preparation method. Background Technology

[0004] TBC (Tunneling oxide passivated back contact) solar cells refer to a back-junction, back-contact solar cell structure in which the positive and negative metal electrodes are arranged in an interdigitated manner on the back side of the cell. Its pn junction is located on the back of the cell, using P+ polycrystalline silicon as the emitter, doped with N++ as the back surface field (BSF), and depositing a tunneling oxide layer between the polycrystalline silicon substrate. This increases carrier selectivity, reduces minority carrier recombination, and improves the cell's open-circuit voltage.

[0005] Currently, N-type TBC batteries generally use a uniform emitter in the P region. In order to reduce contact resistance, the ply thickness in the P region is relatively deep, which leads to enhanced parasitic absorption in the optical field and a reduction in short-circuit current.

[0006] Application content

[0007] In view of this, this application provides a TBC solar cell and a method for its preparation, aiming to solve one of the technical problems in the prior art.

[0008] To achieve the above objectives, the technical solution adopted in this application is as follows:

[0009] In a first aspect, embodiments of this application provide a TBC solar cell, comprising an N-type substrate silicon, wherein the back surface of the N-type substrate silicon includes a P-type region; within the P-type region, a first tunneling layer, a P-type polycrystalline silicon layer, a first passivation antireflection layer, and a first electrode layer are sequentially included from the back surface of the N-type substrate silicon outwards; the P-type polycrystalline silicon layer includes a highly doped region and a low-doped region; the low-doped region surrounds the high-doped region and contacts the high-doped region; the first electrode layer penetrates the first passivation antireflection layer and contacts the high-doped region.

[0010] In one embodiment of the first aspect, the back side of the N-type substrate silicon further includes an N-type region, which is alternately disposed with the P-type region.

[0011] Within the N-type region, a second tunneling layer, an N-type polysilicon layer, a second passivation antireflection layer, and a second electrode layer are sequentially arranged from the backlight surface of the N-type substrate silicon. The second electrode layer penetrates the second passivation antireflection layer and is in contact with the N-type polysilicon layer.

[0012] In one embodiment of the first aspect, the low-doped region surrounds the outside of the first tunneling layer, and the low-doped region is in contact with the high-doped region and the N-type substrate silicon.

[0013] In one embodiment of the first aspect, the boron doping concentration in the highly doped region is higher than that in the lowly doped region.

[0014] In one embodiment of the first aspect, the boron doping concentration in the highly doped region is 1 × 10⁻⁶. 19 ~1×10 21 atoms / cm 3 In the low-doped region, the boron doping concentration is 5 × 10⁻⁶. 15 ~5×10 17 atoms / cm 3 .

[0015] In one embodiment of the first aspect, the area of ​​the highly doped region is 5%-10% of the area of ​​the P-type region, and the area of ​​the low-doped region is 90%-95% of the area of ​​the P-type region.

[0016] In one embodiment of the first aspect, the first tunneling layer and the highly doped region are located at the center of the low-doped region; and / or

[0017] The surface of the low-doped region away from the N-type substrate silicon is flush with the surface of the high-doped region away from the N-type substrate silicon.

[0018] In one embodiment of the first aspect, the thickness of the first tunneling layer is 0.1–2 nm; the thickness of the highly doped region is 50–500 nm; and the thickness of the lowly doped region is 50–1000 nm.

[0019] Secondly, embodiments of this application also provide a method for preparing a TBC solar cell, used to prepare the TBC solar cell in any of the above embodiments, comprising:

[0020] Provide a substrate silicon, and grow a tunneling layer on the back side of the substrate silicon;

[0021] A highly doped P-type polycrystalline silicon layer is grown on the surface of the tunneling layer;

[0022] Part of the tunneling layer and the highly doped P-type polysilicon layer are removed, and a low-doped P-type polysilicon layer is grown on the back side of the substrate silicon, so that the highly doped P-type polysilicon layer and the tunneling layer are embedded in the low-doped P-type polysilicon layer.

[0023] Remove part of the low-doped P-type polysilicon layer, and grow passivation and anti-reflection layers on the surfaces of the low-doped P-type polysilicon layer and the high-doped P-type polysilicon layer.

[0024] An electrode layer is fabricated on the surface of the passivation antireflection layer.

[0025] In one embodiment of the second aspect, after removing a portion of the lightly doped p-type polysilicon layer, the fabrication method further includes:

[0026] A tunneling layer is regrown on the substrate silicon surface;

[0027] An N-type polycrystalline silicon layer is grown on the surface of the tunneling layer;

[0028] Part of the tunneling layer and N-type polysilicon layer are removed to form alternating P-type and N-type regions;

[0029] A passivation and antireflection layer is grown on the surface of an N-type polycrystalline silicon layer;

[0030] An electrode layer is fabricated on the surface of the passivation antireflection layer.

[0031] Compared to existing technologies, the beneficial effects of this application are as follows: This application proposes a TBC solar cell, comprising an N-type substrate silicon, the back surface of which includes a P-type region; within the P-type region, a first tunneling layer, a P-type polycrystalline silicon layer, a first passivation antireflection layer, and a first electrode layer are sequentially included from the back surface of the N-type substrate silicon outwards; the P-type polycrystalline silicon layer includes a highly doped region and a low-doped region, the low-doped region surrounding and contacting the highly doped region; the first electrode layer penetrates the first passivation antireflection layer and contacts the highly doped region. Thus, by setting highly doped and low-doped regions in the P-type polycrystalline silicon layer, the polycrystalline silicon content in the P-type polycrystalline silicon layer is reduced, the parasitic absorption of light by the P-type polycrystalline silicon layer is reduced, the back contact performance is improved, and the short-circuit current parameters of the cell are improved. Attached Figure Description

[0032] Figure 1 shows a schematic diagram of the structure of a TBC solar cell in some embodiments of this application;

[0033] Figure 2 shows a schematic diagram of growing a lightly doped P-type polycrystalline silicon layer on a substrate silicon in some embodiments of this application;

[0034] Figure 3 shows a schematic diagram of the structure of the metal gate line region etched in the low-doped P-type polysilicon layer in some embodiments of this application;

[0035] Figure 4 shows a schematic diagram of the structure of growing a first tunneling layer and a highly doped P-type polysilicon layer in some embodiments of this application.

[0036] Figure 5 shows a schematic diagram of the structure of a first tunneling layer and a highly doped P-type polysilicon layer with the P-type region removed from a low-doped P-type polysilicon layer in some embodiments of this application.

[0037] Figure 6 shows a schematic diagram of the structure of growing a second tunneling layer and an N-type polysilicon layer in a low-doped P-type polysilicon layer in some embodiments of this application.

[0038] Figure 7 shows a schematic diagram of the structure for fabricating a textured surface on the front side of a silicon substrate in some embodiments of this application;

[0039] Figure 8 shows a schematic diagram of the structure of passivation and antireflection layers grown on the front and back sides of the substrate silicon in some embodiments of this application;

[0040] Figure 9 shows a schematic diagram of the structure of a tunneling layer and a highly doped polycrystalline silicon layer grown on a substrate silicon in some embodiments of this application;

[0041] Figure 10 shows a schematic diagram of the structure of a mask grown in a highly doped region of a highly doped polysilicon layer in some embodiments of this application;

[0042] Figure 11 shows a schematic diagram of the structure after removing part of the tunneling layer, part of the highly doped P-type polysilicon layer and the mask in some embodiments of this application;

[0043] Figure 12 shows a schematic diagram of the structure of a low-doped polysilicon layer and a BSG layer grown on the front and back sides of a substrate silicon in some embodiments of this application.

[0044] Figure 13 shows a schematic diagram of the structure for laser removal of BSG in the N-type region and GAP region of the substrate silicon front side in some embodiments of this application;

[0045] Figure 14 shows a schematic diagram of the structure after texturing following the removal of the low-doped P-type polysilicon layer and BSG in some embodiments of this application;

[0046] Figure 15 shows a schematic diagram of the structure of growing a tunneling layer and a phosphorus-doped polycrystalline silicon layer on the front and back sides of the substrate silicon in some embodiments of this application.

[0047] Figure 16 shows a schematic diagram of the structure of growing a PSG layer in a phosphorus-doped polysilicon layer in some embodiments of this application;

[0048] Figure 17 shows a schematic diagram of the structure for laser removal of PSG in the P-type region and GAP region of the substrate silicon front side in some embodiments of this application;

[0049] Figure 18 shows a schematic diagram of the structure after texturing following the removal of part of the tunneling layer, part of the phosphorus-doped polysilicon layer and PSG in some embodiments of this application.

[0050] Figure 19 shows a schematic diagram of the structure of passivation and antireflection layers grown on the front and back sides of the substrate silicon in some embodiments of this application;

[0051] Figure 20 shows a schematic diagram of the structure after an electrode is fabricated on the front side of the substrate silicon in some embodiments of this application.

[0052] Key component symbols: 100 - TBC solar cell; 110 - N-type substrate silicon; 120 - P-type region; 121 - First tunneling layer; 122 - P-type polycrystalline silicon layer; 123 - First passivation and antireflection layer; 124 - First electrode layer; 130 - N-type region; 131 - Second tunneling layer; 132 - N-type polycrystalline silicon layer; 133 - Second passivation and antireflection layer; 134 - Second electrode layer; 1221 - Highly doped region; 1222 - Lowly doped region;

[0053] 1224 - Low-doped P-type polysilicon layer; 1225 - Groove; 1226 - Highly doped P-type polysilicon layer; 140 - Textured surface; 150 - Mask; 160 - BSG layer; 170 - PSG layer. Detailed Implementation

[0054] Currently, N-type TBC batteries generally use a uniform emitter in the P region. In order to reduce contact resistance, the ply thickness in the P region is relatively deep, which leads to enhanced parasitic absorption in the optical field and a reduction in short-circuit current.

[0055] To address the aforementioned issues, as shown in Figure 1, an embodiment of this application provides a TBC solar cell 100, including a P-type region 120.

[0056] Within the P-type region 120, starting from the backlight surface of the N-type substrate silicon 110, a first tunneling layer 121, a P-type polysilicon layer 122, a first passivation and antireflection layer 123, and a first electrode layer 124 are sequentially arranged outwards. The P-type polysilicon layer 122 includes a highly doped region 1221 and a low-doped region 1222. The low-doped region 1222 surrounds the high-doped region 1221 and contacts it. The first electrode layer 124 penetrates the first passivation and antireflection layer 123 and contacts the high-doped region 1221. By providing the highly doped region 1221 and the low-doped region 1222 in the P-type polysilicon layer 122, the polysilicon content in the P-type polysilicon layer 122 is reduced, the parasitic absorption of light by the P-type polysilicon layer 122 is reduced, the back contact performance is improved, and the short-circuit current parameters of the battery are improved.

[0057] In some embodiments, N-type substrate silicon may be replaced by P-type substrate silicon.

[0058] It should be noted that in related technologies, if the entire P-type polysilicon layer is doped with a high concentration to reduce electrode contact resistance, the high doping in the low-doped regions (especially the light-absorbing active regions) will lead to increased free carrier absorption and a decrease in the number of photogenerated carriers. Conversely, if the entire P-type polysilicon layer is doped with a low concentration to reduce light absorption loss, the high contact resistance in the high-doped regions will significantly increase the series resistance and reduce the battery fill factor (FF). Clearly, the single-doping concentration P-type polysilicon layer in these technologies cannot simultaneously meet the dual requirements of "electrode conductivity" and "light absorption efficiency," making it difficult to simultaneously improve the battery short-circuit current (Isc) and fill factor (FF).

[0059] To address the aforementioned issues, this application addresses this problem by creating a highly doped region 1221 in the portion of the P-type polysilicon layer directly connected to the first electrode layer 124. This reduces the contact resistance between the first electrode 124 and the P-type polysilicon layer, thereby increasing the battery fill factor (FF). An ohmic contact is formed between the first electrode layer 124 and the highly doped region 1221, reducing the series resistance to ≤10 mΩ·cm. 2 This application also sets the remaining P-type polysilicon layer that is not connected to the first electrode layer 124 as a low-doped region 1222, which reduces the absorption of free carriers, increases the number of photogenerated carriers, and improves the light transmittance by 2%-3%.

[0060] Therefore, this application achieves a synergistic effect of "local conductivity optimization + global light absorption enhancement" by spatially separating the P-type polysilicon layer 122, so that the highly doped region 1221 directly connected to the first electrode layer 124 focuses on reducing contact resistance, and the low doped region 1222 not directly connected to the first electrode layer 124 focuses on light absorption optimization, thereby satisfying the dual requirements of "electrode conductivity" and "light absorption efficiency".

[0061] In some embodiments, the back side of the substrate silicon 110 also includes an N-type region 130, wherein the N-type region 130 and the P-type region 120 are alternately spaced.

[0062] Within the N-type region 130, from the backlight surface of the substrate silicon 110 outwards, there are a second tunneling layer 131, an N-type polysilicon layer 132, a second passivation antireflection layer 133, and a second electrode layer 134. The second electrode layer 134 penetrates the second passivation antireflection layer 133 and is in contact with the N-type polysilicon layer 132.

[0063] The sheet resistance in the N-type polysilicon layer 132 is greater than that in the highly doped region 1221 of the P-type polysilicon layer 122, which reduces the parasitic absorption of light by the N-type polysilicon layer 132, improves the back contact performance, and improves the short-circuit current parameters of the battery.

[0064] In some embodiments, the low-doped region 1222 surrounds the outside of the first tunneling layer 121 and contacts the high-doped region 1221. This structure reduces the proportion of the high-doped region 1221 in the P-type polysilicon layer 122, reduces the parasitic absorption of light by the P-type polysilicon layer 122, and improves the back contact performance, thereby improving the short-circuit current parameters of the battery.

[0065] Furthermore, in traditional uniformly doped p-type polysilicon layers, the entire p-type polysilicon layer is connected to the tunneling layer. The low-doped regions of the p-type polysilicon layer have numerous dangling bonds at the interface with the substrate silicon, resulting in a surface recombination rate (S) as high as 10. 4 Speeds above cm / s significantly reduce carrier lifetime.

[0066] To address the aforementioned issues, as shown in Figure 1, the low-doped region 1222 contacts the high-doped region 1221 and the N-type substrate silicon 110. Specifically, the top surface of the low-doped region 1222 contacts the N-type substrate silicon 110, and no first tunneling layer 121 is provided between the low-doped region 1222 and the N-type substrate silicon 110. The inner surface of the low-doped region 1222 contacts both the side surface of the first tunneling layer 121 and the side surface of the high-doped region 1221. In this way, the low-doped region 1222 reduces the interface defect density through its light doping characteristics, and simultaneously utilizes the passivation effect of the first tunneling layer 121 (such as SiO2) to reduce the surface recombination rate to ≤10. 3 cm / s, and the carrier lifetime is extended to over 200 μs.

[0067] In some embodiments, the boron doping concentration in the highly doped region 1221 is higher than that in the low-doped region 1222. This application constructs a boron doping gradient electric field within the p-type polysilicon layer 122, creating a built-in electric field at the interface between the highly doped region 1221 and the low-doped region 1222. This accelerates the directional migration of photogenerated carriers from the low-doped region 1222 to the electrode region, improving the transport efficiency by ≥15%.

[0068] In some embodiments, the boron doping concentration in the highly doped region 1221 is 1 × 10⁻⁶. 19 ~1×10 21 atoms / cm 3 In the low-doped region 1222, the boron doping concentration is 5 × 10⁻⁶. 15 ~5×10 17 atoms / cm 3 .

[0069] Specifically, in the highly doped region 1221, the boron doping concentration is 1×10⁻⁶. 19 atoms / cm 3 3×10 19 atoms / cm 3 6×10 19atoms / cm 3 1×10 20 atoms / cm 3 6×10 20 atoms / cm 3 1×10 21 atoms / cm 3 The values ​​are not limited to those in the examples. If the boron doping concentration in the highly doped region is less than 1 × 10⁻⁶, then... 19 atoms / cm 3 This will cause the contact resistance between the first electrode layer and the P-type polysilicon layer to increase to 50 mΩ·cm. 2 As the series resistance increases, the fill factor (FF) decreases by ≥2%; if it is higher than 1×10⁻⁶, the fill factor (FF) decreases by ≥2%. 21 atoms / cm 3 The lattice defect density of polycrystalline silicon increases by 1-2 orders of magnitude, and the carrier lifetime is shortened to less than 50μs, which in turn reduces the battery efficiency.

[0070] Specifically, in the low-doped region 1222, the boron doping concentration is 7 × 10⁻⁶. 15 atoms / cm 3 9×10 15 atoms / cm 3 5×10 16 atoms / cm 3 9×10 16 atoms / cm 3 1×10 17 atoms / cm 3 5×10 17 atoms / cm 3 The values ​​are not limited to those in the examples. If the boron doping concentration in the low-doped region is less than 5 × 10⁻⁶, the following applies. 15 atoms / cm 3 Insufficient selectivity of the emitter for charge carriers leads to a decrease in photogenerated carrier collection efficiency of ≥5%; if it exceeds 5×10 17 atoms / cm 3 Enhanced free carrier absorption reduces short-circuit current (Isc) by approximately 1.5 mA / cm². 2 .

[0071] In some embodiments, the area of ​​the highly doped region 1221 is 5%-10% of the area of ​​the P-type region 120, and the area of ​​the low-doped region 1222 is 90%-95% of the area of ​​the P-type region 120. This creates a stable connection between the highly doped region 1221 and the first electrode layer 124, reducing the fabrication cost of the first electrode layer 124.

[0072] Specifically, the area of ​​the highly doped region 1221 is 5%, 6%, 7%, 8%, 9%, and 10% of the area of ​​the P-type region 120. When it exceeds 10%, the amount of material used in the first electrode layer 124 increases, increasing production costs. When it is less than 5%, the connection stability between the highly doped region 1221 and the first electrode layer 124 is reduced.

[0073] Correspondingly, the area of ​​the low-doped region 1222 is 95%, 94%, 93%, 92%, 91%, and 90% of the area of ​​the P-type region 120. When it exceeds 95%, the area of ​​the high-doped region 1221 is too small, which reduces the connection stability between the high-doped region 1221 and the first electrode layer 124; when it is below 90%, the material used in the first electrode layer 124 increases, increasing the production cost.

[0074] In some embodiments, as shown in FIG1, the first tunneling layer 121 and the highly doped region 1221 are located at the center of the low-doped region 1222. The photogenerated carriers are uniformly distributed within the highly doped region 1221 and the low-doped region 1222, thereby improving product quality.

[0075] In some embodiments, the surface of the low-doped region 1222 away from the N-type substrate silicon 110 is flush with the surface of the high-doped region 1221 away from the N-type substrate silicon 110. This is beneficial for improving the deposition uniformity of the passivation antireflection layer.

[0076] In some embodiments, the thickness of the first tunneling layer 121 is 0.1–2 nm; the thickness of the highly doped region 1221 is 50–500 nm; and the thickness of the low-doped region 1222 is 50–1000 nm.

[0077] Specifically, the thickness of the first tunneling layer 121 is 0.1nm, 0.5nm, 1.0nm, 1.2nm, 1.5nm, 1.8nm, 2.0nm, etc., and is not limited to the values ​​in the examples.

[0078] Specifically, the thickness of the highly doped region 1221 is 50nm, 100nm, 150nm, 200nm, 300nm, 400nm, 500nm, etc., and is not limited to the values ​​in the examples.

[0079] Specifically, the thickness of the low-doped region 1222 is 50nm, 200nm, 400nm, 600nm, 800nm, 900nm, 1000nm, etc., and is not limited to the values ​​in the examples.

[0080] In some embodiments, the first tunneling layer 121 and the second tunneling layer 131 are made of the same material, which simplifies the manufacturing process and reduces production costs.

[0081] In some embodiments, the first passivation antireflection layer 123 and the second passivation antireflection layer 133 are made of the same material, which simplifies the manufacturing process and reduces production costs.

[0082] The passivation antireflection layer includes a passivation layer and an antireflection coating layer. Specifically:

[0083] The passivation layer is formed by stacking at least one of the following materials: aluminum oxide (Al2O3), hydrogenated amorphous silicon (a-Si:H), silicon dioxide (SiO2), and hafnium oxide (HfO2).

[0084] The antireflective coating is made of silicon nitride (SiN). x It is formed by stacking at least one of the following materials: titanium dioxide (TiO2), zinc oxide (ZnO), magnesium fluoride (MgF2), silicon oxynitride (SiON), silicon dioxide (SiO2), magnesium fluoride (MgF2), and indium tin oxide (ITO).

[0085] In one embodiment, the first passivation antireflection layer 123 comprises, from the inside out, a passivation layer made of aluminum oxide and an antireflection film layer made of silicon nitride.

[0086] In some embodiments, the first electrode layer 124 is made of copper paste, silver paste, or a combination of electroplated copper or silver seed layer + copper paste. In one embodiment, the first electrode layer 124 and the second electrode layer 134 are silver grids made of silver paste.

[0087] The fabrication method of the TBC solar cell 100 in any of the above embodiments will be described below, which is divided into two fabrication methods. The main difference between the first and second fabrication methods is that in the first fabrication method, the low-doped region of the P-type polycrystalline silicon layer is prepared first, and then the high-doped region of the P-type polycrystalline silicon layer is prepared; in the second fabrication method, the high-doped region of the P-type polycrystalline silicon layer is prepared first, and then the low-doped region of the P-type polycrystalline silicon layer is prepared.

[0088] Referring to Figures 1, 2 through 8, the first method for preparing the TBC solar cell 100 in any of the above embodiments is as follows:

[0089] Step S10: Provide substrate silicon 110, and grow a lightly doped P-type polycrystalline silicon layer 1224 on the back side of substrate silicon 110.

[0090] Specifically, the substrate silicon 110 adopts either N-type substrate silicon 110 or P-type substrate silicon 110.

[0091] As shown in Figure 2, a lightly doped P-type polycrystalline silicon layer 1224 is laid across the entire back side of the N-type substrate silicon.

[0092] Step S20: Etch trench 1225 in low-doped P-type polysilicon layer 1224, grow first tunneling layer 121 in trench 1225, and grow highly doped P-type polysilicon layer 1226 on first tunneling layer 121.

[0093] Specifically, as shown in Figures 3 and 4, the growth of the first tunneling layer 121 and the highly doped P-type polysilicon layer 1226 is confined within the trench 1225, so that the first tunneling layer 121 and the highly doped P-type polysilicon layer are in contact.

[0094] Step S30: Etch N-type region 130 in the low-doped P-type polysilicon layer 1224, and grow a second tunneling layer 131 and an N-type polysilicon layer 132 in the N-type region 130 in sequence.

[0095] Specifically, as shown in Figures 5 and 6, the low-doped P-type polysilicon layer 1224 between two adjacent P-type regions 120 is removed to expose the surface of the N-type substrate silicon 110 in order to grow the N-type region 130.

[0096] It should be noted that the P-type polycrystalline silicon layer can also be replaced by amorphous silicon materials, such as hydrogenated amorphous silicon (a-Si:H) and microcrystalline silicon (μc-Si:H).

[0097] In step S40, the lightly doped P-type polysilicon layer 1224 is etched to form alternating P-type regions 120 and N-type regions 130.

[0098] As shown in Figures 8 and 1, the residual low-doped P-type polysilicon layer 1224 connecting the P-type region 120 and the N-type region 130 is removed to form the P-type region 120 and the N-type region 130 that are spaced apart, thereby avoiding short circuits between the P-type region 120 and the N-type region 130.

[0099] In some embodiments, a textured surface 140 is prepared on the front side of the substrate silicon 110;

[0100] Step S50: Prepare passivation and antireflection layers on the front and back sides of the substrate silicon 110;

[0101] Specifically, as shown in Figure 7, a passivation antireflection layer is formed on the textured surface 140 on the back side of the substrate silicon 110, and a first passivation antireflection layer 123 and a second passivation antireflection layer 133 are formed on the front side of the substrate silicon 110.

[0102] Step 60: Print silver paste on the first passivation antireflection layer 123 on the back side of the substrate silicon 110 to form the first electrode layer 124, and print silver paste on the second passivation antireflection layer 133 on the back side of the substrate silicon 110 to form the second electrode layer 134.

[0103] Example 1

[0104] (1) A fully covered, low-doped P-type polycrystalline silicon layer 1224 is prepared on the back side of the polished substrate silicon 110.

[0105] Specifically, as shown in Figure 2, a tubular diffusion device is used to dope the surface of a silicon wafer at high temperature using special gases such as BBr3 as the main reactants. The sheet resistance after doping is 180Ω / sq.

[0106] (2) The low-doped P-type polysilicon layer 1224 of the positive electrode metal gate region is removed on the back side of the substrate silicon 110 by laser processing and wet etching.

[0107] As shown in Figure 3, the laser processing includes: using a laser (picosecond, 100-1000kHz frequency, 1-500W power) to bombard the silicon wafer according to the metal grid pattern to remove the borosilicate glass layer (BSG) in a local area, and the width of the laser-induced area is 80-160um.

[0108] Wet etching includes: using a tank cleaning device to etch the battery to remove the low-doped P-type polycrystalline silicon layer 1224 in the positive electrode metal grid area, using an alkaline solution of 5-10% by mass of NaOH or KOH.

[0109] (3) Grow the first tunneling layer 121 and the highly doped P-type polycrystalline silicon layer 1226.

[0110] As shown in Figure 4, the thickness of the first tunneling layer is 1.2 nm, the thickness of the highly doped P-type polycrystalline silicon layer 1226 is 280 nm, and the first tunneling layer 121 is grown by LPCVD (low-pressure electrochemical deposition).

[0111] Maintain a pressure of 15-100 kPa and a temperature of 550-700 ℃, and prepare the first tunneling layer 121 by purging oxygen.

[0112] A highly doped P-type polycrystalline silicon layer 1226 is grown on the outer surface of the first tunneling layer 121. The pressure is maintained at 30-80 Pa and the temperature at 550-600 °C. Borane is then introduced to prepare a highly boron-doped intrinsic amorphous silicon layer.

[0113] (4) Remove the first tunneling layer 121 and the highly doped P-type polysilicon layer 1226 outside the P-type region 120 in the low-doped P-type polysilicon layer 1224.

[0114] As shown in Figures 5 and 6, a tube annealing furnace is used to activate boron and crystallize amorphous silicon for 1000s-3000s, with the temperature controlled between 800-950℃. The N-type region is then subjected to laser treatment and wet etching to form a highly doped part that is directly connected to the first electrode 124 and a low-doped part that is not directly connected to the first electrode 124.

[0115] A laser (picosecond, 100-1000kHz frequency, 1-500W power) is used to bombard the silicon wafer according to the metal gate pattern, removing the borosilicate glass layer in a local area. The width of the laser-induced layer is more than 300um, thereby removing the first tunneling layer 121 and the highly doped P-type polycrystalline silicon layer 1226 in the gate area.

[0116] The battery is etched using a tank cleaning device to remove the first tunneling layer 121 of the N-type region 130 and the highly doped P-type polycrystalline silicon layer 1226. The solution used is an alkaline solution of NaOH or KOH with a mass ratio of 5-10%.

[0117] (5) A second tunneling layer 131 and an N-type polysilicon layer 132 are grown in the N-type region 130.

[0118] The second tunneling layer 131 is grown on the back surface using PECVD. Specifically, N2O gas is introduced at a flow rate of 10 s Lm for 40 s to 100 s, the temperature is controlled between 350 and 450 ℃, the pressure is controlled between 100 and 400 Pa, and the power is set between 6 and 1.2 kW.

[0119] After the second tunneling layer 131 is deposited, phosphorus-doped amorphous silicon is deposited. The temperature is controlled between 380 and 450°C, and the pressure is controlled between 100 and 400 Pa to deposit the doped amorphous silicon and form an N-type polycrystalline silicon layer 132.

[0120] (6) Remove the low-doped P-type polysilicon layer 1224 outside the P-type region 120 and prepare a textured surface 140 on the back side of the substrate silicon 110.

[0121] A tube annealing furnace is used to activate phosphorus and crystallize amorphous silicon for 1000s-3000s, with the temperature controlled between 650-850℃. Laser treatment and wet etching and alkaline etching are then performed to form a structure in which P-type region 120 and N-type region 130 are arranged alternately.

[0122] (7) Passivation antireflection layers are prepared on the front and back sides of the substrate silicon 110.

[0123] As shown in Figure 7, an antireflection layer is first prepared, and then an aluminum oxide layer is deposited using atomic layer deposition (ALD) technology with a thickness of 3-5 nm, a process temperature of 200-300 °C, and a deposition time of 7-12 min.

[0124] Then, a layer of silicon oxynitride is deposited using physical vapor deposition (PECVD) technology, with a thickness of 60-80 nm, a process temperature of 600-700 °C, and a deposition time of 5-8 min.

[0125] (8) Prepare electrode layer and sinter.

[0126] Specifically, as shown in Figures 8 and 1, screen printing technology is used to prepare the front electrode and electric field of the battery using metallic silver paste as raw material, so as to achieve the purpose of collecting and transporting charge carriers.

[0127] The battery is then subjected to high-temperature sintering and annealing at 780-900℃ to form good ohmic contact and improve the battery fill factor.

[0128] Referring to Figures 1, 9 to 20, the second method for preparing the TBC solar cell 100 in any of the above embodiments is as follows:

[0129] Step S100: Provide substrate silicon 110 and grow a tunneling layer on the back side of substrate silicon 110.

[0130] Specifically, the substrate silicon 110 is either N-type or P-type.

[0131] Figure 9 shows the front and back sides of the silicon 110 substrate with the tunneling layer laid flat.

[0132] Step S200: A highly doped P-type polycrystalline silicon layer 1226 is grown on the surface of the tunneling layer.

[0133] Figure 9 shows the front and back sides of the substrate silicon 110 with a highly doped P-type polycrystalline silicon layer 1226.

[0134] A tunneling layer and a boron-doped polycrystalline silicon layer are grown on the front side of a silicon 110 substrate by introducing silane and borane through LPCVD (low-voltage electrochemical deposition).

[0135] In step S300, a portion of the tunneling layer and the highly doped P-type polysilicon layer 1226 are removed, and a low-doped P-type polysilicon layer 1224 is grown on the back side of the substrate silicon 110, so that the highly doped P-type polysilicon layer 1226 and the tunneling layer are embedded in the low-doped P-type polysilicon layer.

[0136] It should be noted that, as shown in Figure 1, the highly doped region 1221 and the low-doped region 1222 in the P-type polycrystalline silicon layer 122 can also be replaced by amorphous silicon materials, such as hydrogenated amorphous silicon (a-Si:H), microcrystalline silicon (μc-Si:H), etc.

[0137] Removing part of the tunneling layer and the highly doped p-type polysilicon layer 1226 includes:

[0138] Step S310: Create mask 150.

[0139] As shown in Figure 10, a mask 150 is fabricated in the highly doped region of the P-type polysilicon layer. The mask 150 can be fabricated using one of the following three methods:

[0140] I. A borosilicate glass (BSG) mask is grown on the surface of a highly doped region using laser oxidation (SE);

[0141] II. Using laser oxidation (SE) to grow SiOx masks on the surface of highly doped regions;

[0142] III. Print a layer of ink / blocking paste on the surface of the highly doped region as a mask.

[0143] Step S320: Remove the tunneling layer and the highly doped P-type polysilicon layer 1226 located outside the mask 150.

[0144] Specifically, as shown in Figure 11, the boron-doped polycrystalline silicon layer / amorphous silicon layer and tunneling layer protected by the BSG mask 150, SiOx mask 150, or ink / blocking paste mask 150 are etched away, and then the BSG mask 150, SiOx mask 150, or ink / blocking paste mask 150 are cleaned away.

[0145] As shown in Figure 12, in step S330, a low-doped P-type polysilicon layer 1224 is grown on the back side of the substrate silicon 110, so that the high-doped P-type polysilicon layer 1226 and the tunneling layer are embedded in the low-doped P-type polysilicon layer.

[0146] As shown in Figure 12, specifically, silane and borane are introduced by LPCVD to grow a boron-doped polycrystalline silicon layer on the front side of the silicon 110 substrate.

[0147] High-temperature diffusion allows boron to diffuse into the boron-type P-type polycrystalline silicon layer and the substrate silicon 110, resulting in high-doped and low-doped regions in the P-type polycrystalline silicon layer.

[0148] In step S400, a portion of the low-doped P-type polysilicon layer 1224 is removed, and passivation and antireflection layers are grown on the surfaces of the low-doped P-type polysilicon layer 1224 and the high-doped P-type polysilicon layer 1226.

[0149] The process of removing a portion of the lightly doped P-type polysilicon layer 1224 includes:

[0150] Step S410: Fabricate a BSG layer 160 on the entire surface of the P-type polysilicon layer.

[0151] As shown in Figure 12, specifically, a borosilicate glass (BSG) layer 160 is grown on the entire surface of the P-type polycrystalline silicon layer using laser oxidation (SE).

[0152] As shown in Figure 13, in step S420, laser etching is used to remove the BSG layer 160 of the N-type region and the gap (GAP) region.

[0153] As shown in Figure 14, in step S430, the low-doped P-type polysilicon layer 1224 of the N-type region and the gap (GAP) region on the back side is etched, and the BSG layer 160 of the P-type region is cleaned and removed after etching.

[0154] In some embodiments, after removing a portion of the lightly doped p-type polysilicon layer 1224, the fabrication method further includes:

[0155] Step S440: A tunneling layer is grown again on the surface of the substrate silicon 110.

[0156] Specifically, as shown in Figure 15, a tunneling layer is deposited on the entire surface of the substrate silicon 110 after removing part of the low-doped P-type polycrystalline silicon layer 1224 by LPCVD.

[0157] Step S450: An N-type polycrystalline silicon layer 132 is grown on the surface of the tunneling layer.

[0158] Specifically, as shown in Figure 15, a phosphorus-doped polycrystalline silicon layer is deposited on the entire surface of the N-type substrate silicon 110 after the tunneling layer is deposited using LPCVD. Then, phosphorus diffusion is performed on the phosphorus-doped polycrystalline silicon layer to form an N-type polycrystalline silicon layer 132.

[0159] In step S460, part of the tunneling layer and the N-type polysilicon layer 132 are removed to form alternating P-type regions 120 and N-type regions 130.

[0160] Specifically, as shown in Figure 16, a phosphosilicate glass (PSG) layer 170 is fabricated on the entire surface of the N-type substrate silicon 110 on which the N-type polycrystalline silicon layer 132 is formed.

[0161] As shown in Figure 17, laser etching removes the PSG from the P-type region 120 and the gap (GAP) region, while retaining the PSG layer 170 of the N-type region 130.

[0162] The PSG layer on the back side is removed by HF acid cleaning, and the phosphorus-doped polysilicon and tunneling layer without PSG layer protection are removed by acid cleaning. The PSG in the N-type region 130 is then removed by acid cleaning.

[0163] As shown in Figure 18, in step S470, the GAP regions on the back and front sides of the substrate silicon 110 are fabricated as textured surfaces 140, and the P and N regions on the back side are fabricated as polished surfaces.

[0164] As shown in Figure 19, in step S480, a passivation and antireflection layer 123 is grown on the surface of the low-doped P-type polysilicon layer 1224 and the surface of the high-doped P-type polysilicon layer 1226, and a passivation and antireflection layer 123 is grown on the surface of the N-type polysilicon layer 132.

[0165] Alternating P-type regions 120 and N-type regions are formed through steps 410 to 460, and therefore the passivation and anti-reflection layers 123 of the N-type regions and P-type regions 120 are fabricated simultaneously.

[0166] Specifically, as shown in Figure 19, aluminum oxide (Al2O3) is first grown on the front and back sides of the silicon 110 substrate by atomic layer deposition (ALD), and then silicon nitride (SiN) is grown on the front and back sides of the silicon 110 substrate by plasma-enhanced chemical vapor deposition (PECVD). x Anti-reflective coating.

[0167] Step S500: An electrode layer is fabricated on the surface of the passivation antireflection layer 123.

[0168] In step 480, passivation and antireflection layers 123 are grown in both the P-type region 120 and the N-type region, thus simultaneously fabricating the electrode layers in the N-type region and the P-type region 120.

[0169] Specifically, as shown in Figure 20, the electrode layer is prepared by printing copper paste, silver paste, silver seed layer + copper paste or electroplated copper electrode on the surface of the passivation antireflection layer 123 in the P-type region 120 and N-type region 130 using a laser.

[0170] Example 2

[0171] BSG as a mask

[0172] 6.1.1 Preparation of Experimental Materials

[0173] (1) Substrate silicon: N-type single crystal silicon wafers with dimensions of 156.75mm×156.75mm and a thickness of 180μm are selected. The resistivity is 1-3Ω·cm. The surface is treated with standard texturing, and the average height of the textured pyramid is about 1.5μm.

[0174] (2) Gaseous raw materials: high-purity silane (SiH4, 99.999%), borane (B2H6, 99.99%, diluted in high-purity argon, concentration 5%), phosphine (PH3, 99.99%, diluted in high-purity argon, concentration 5%), high-purity oxygen (O2, 99.999%), and high-purity argon (Ar, 99.999%).

[0175] (3) Chemical reagents: 49% hydrofluoric acid (HF), 20% sodium hydroxide (NaOH) solution, and deionized water (resistivity ≥18.2MΩ·cm).

[0176] (4) Thin film materials: Trimethylaluminum (TMA, Al(CH3)3), ammonia (NH3, 99.999%), and silane (SiH4) and ammonia (NH3) for depositing passivation layers, and silicon nitride (SiN) for preparing silicon nitride. x ).

[0177] (5) Electrode materials: copper paste (solid content 85%, particle size ≤1μm), silver paste (silver content 92%).

[0178] 6.1.2 Specific preparation steps

[0179] (1) Preparation of the initial layer of the P region

[0180] The cleaned silicon substrate was placed in a low-pressure chemical vapor deposition (LPCVD) system, and the reaction chamber pressure was set to 50 Pa. High-purity argon gas (500 sccm flow rate) was first introduced to purge the chamber for 5 minutes to remove air. Subsequently, reaction gases were introduced at a ratio of 100 sccm for silane and 10 sccm for borane, while the temperature was raised to 600°C. Deposition was carried out under these conditions for 30 minutes, resulting in the growth of a tunneling oxide layer (SiO2) with a thickness of approximately 1-10 nm and a boron-doped polycrystalline silicon layer (B-poly) with a thickness of 30-100 nm on the front side of the silicon substrate, with a sheet resistance controlled at 80 Ω / □.

[0181] (2) Fabrication of the mask for the P-region electrode area

[0182] The deposited silicon wafer is transferred to a laser oxidation device. A 355nm wavelength, 20kHz pulse frequency, and 10W ultraviolet laser is used to scan the P-region electrode area at a scanning speed of 500mm / s. This causes the silicon wafer surface to react with oxygen to form a borosilicate glass (BSG) mask with a thickness of approximately 100nm. The laser scanning path follows a pre-designed electrode pattern, with the electrode area occupying 15% of the total P-region area.

[0183] (3) Etching and cleaning

[0184] A silicon wafer with a BSG mask was placed in an etching solution (5% hydrofluoric acid solution) for 30 seconds to remove the boron-doped polysilicon layer and tunneling layer without BSG mask protection. After etching, the wafer was ultrasonically cleaned in deionized water for 5 minutes, then dried with nitrogen gas. Next, the wafer was immersed in a 10% sodium hydroxide solution for 1 minute to completely remove the BSG mask. Finally, it was rinsed again with deionized water and dried. Boron diffusion and BSG formation occurred.

[0185] The processed silicon wafer was placed in a high-temperature diffusion furnace and subjected to boron diffusion at 850°C for 20 minutes. During diffusion, oxygen (flow rate 200 sccm) and borane (flow rate 5 sccm) were introduced to allow boron to diffuse into the boron-doped polysilicon layer and the substrate silicon. A high-concentration boron-doped polysilicon layer (sheet resistance ≤ 30 Ω / □) was formed in the P-region electrode area, while a low-concentration boron-doped polysilicon layer (sheet resistance ≥ 150 Ω / □) was formed in the non-electrode area. Simultaneously, a BSG layer with a thickness of approximately 80 nm was formed on the outermost layer of the silicon wafer to prepare for subsequent laser masking.

[0186] (4) Laser 1-open N-region and gap (GAP) region mask

[0187] Using a laser with a wavelength of 532nm, a pulse frequency of 15kHz, and a power of 8W, the laser is scanned at a scanning speed of 600mm / s according to the pre-designed N-region and GAP-region pattern to remove the BSG mask in the N-region and GAP-region.

[0188] (5) Front cleaning and etching

[0189] The silicon wafer was immersed in a 5% HF acid solution for 1 minute to remove any residual BSG mask on the front side. Then, the wafer was immersed in a 20% sodium hydroxide solution for alkaline etching for 40 seconds to remove the unprotected B-poly layer and tunneling layer. After etching, the wafer was rinsed three times with deionized water for 2 minutes each time to thoroughly remove any residual chemical reagents.

[0190] (7) Preparation of N-region

[0191] The cleaned silicon wafer was placed back into the LPCVD equipment, and the reaction chamber pressure was set to 60 Pa. High-purity argon gas (flow rate 600 sccm) was first introduced to purge for 5 min. Then, reaction gases were introduced at a ratio of 120 sccm for silane and 12 sccm for phosphine. The temperature was raised to 650 °C, and deposition was carried out for 25 min. A tunneling oxide layer with a thickness of about 8 nm and a phosphorus-doped polycrystalline silicon layer (P-poly) with a thickness of 40 nm were grown on the front side of the silicon wafer, and the sheet resistance was controlled at 100 Ω / □.

[0192] (8) Phosphorus diffusion and PSG formation

[0193] The silicon wafer was transferred to a high-temperature diffusion furnace for phosphorus diffusion at 880°C for 15 minutes. During the diffusion process, oxygen (flow rate 250 sccm) and phosphine (flow rate 6 sccm) were introduced to allow phosphorus to diffuse into the phosphorus-doped polycrystalline silicon layer, forming N-region doping. At the same time, a layer of phosphosilicate glass (PSG) with a thickness of about 120 nm was grown on the surface of the silicon wafer.

[0194] (9) Laser 2-open P-region and GAP region mask

[0195] A laser with a wavelength of 355nm, a pulse frequency of 20kHz, and a power of 10W was used to scan the P-area and GAP-area patterns at a scanning speed of 500mm / s to remove the PSG mask in the corresponding areas.

[0196] (10) Front cleaning, etching, texturing

[0197] The silicon wafer was immersed in a 5% HF acid solution for a 2-minute chain pickling process to remove the front PSG.

[0198] Subsequently, the silicon wafer was immersed in a mixed etching solution consisting of hydrofluoric acid (3% by mass), nitric acid (10% by mass), and deionized water for 30 seconds to remove the phosphorus-doped polysilicon layer and tunneling layer that were not protected by the PSG mask. After etching, the wafer was rinsed three times with deionized water for 2 minutes each time, and finally dried with nitrogen gas.

[0199] A pyramidal textured surface is formed by anisotropic etching of silicon surfaces using sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution. Formulation: KOH texturing solution. Composition: ① KOH (analytical grade): 1-2 wt% ② Isopropanol (IPA): 2-5 vol% (to promote uniformity of the texture); ③ Deionized water: balance. Process parameters: ① Temperature: 75-85℃ ② Time: 15-25 min. Procedure: ① Heat the solution to the set temperature and place the solar cells in; ② After the reaction, rinse with deionized water, then neutralize the residual alkali solution with HCl (5% concentration); ③ Ultrasonic cleaning for 10 min to remove particulate impurities.

[0200] (11) Deposition of passivation layer and antireflection layer on front and back sides

[0201] The silicon wafer was placed in an atomic layer deposition (ALD) system, using trimethylaluminum (TMA) as the aluminum source and water (H2O) as the oxygen source, to deposit aluminum oxide (Al2O3) at 400°C for 200 deposition cycles, resulting in an aluminum oxide passivation layer with a thickness of approximately 10 nm. Next, the silicon wafer was transferred to a plasma-enhanced chemical vapor deposition (PECVD) system, where silane (flow rate 80 sccm) and ammonia (flow rate 200 sccm) were introduced, and silicon nitride (SiN) was deposited at 350°C. x Antireflective coating, deposition time 15 min, film thickness controlled at 80 nm.

[0202] (12) Electrode formation

[0203] Copper paste was printed onto the back of the battery using screen printing technology. The printed pattern was a grid line structure with a grid line width of 80 μm and a spacing of 1.5 mm. After printing, it was pre-dried at 200℃ for 10 min, and then placed in a sintering furnace for rapid sintering at a peak temperature of 850℃ for 5 min to form ohmic contacts. To further improve the conductivity of the electrodes, a layer of silver paste with a thickness of approximately 5 μm was printed on the surface of the copper paste grid lines. The device was then sintered again at 850℃ for 3 min to complete the device fabrication.

[0204] Example 3

[0205] SiOx as a mask

[0206] 6.2.1 Preparation of Experimental Materials

[0207] (1) Substrate silicon: N-type single crystal silicon wafers with dimensions of 156.75mm×156.75mm and a thickness of 180μm are selected. The resistivity is 1-3Ω·cm. After standard texturing treatment, the average height of the textured pyramid is about 1.5μm.

[0208] (2) Gaseous raw materials: high-purity silane (SiH4, 99.999%), borane (B2H6, 99.99%, diluted in high-purity argon, concentration 5%), phosphine (PH3, 99.99%, diluted in high-purity argon, concentration 5%), high-purity oxygen (O2, 99.999%), and high-purity argon (Ar, 99.999%).

[0209] (3) Chemical reagents: 49% hydrofluoric acid (HF), 20% sodium hydroxide (NaOH) solution, and deionized water (resistivity ≥18.2MΩ·cm).

[0210] (4) Thin film materials: Trimethylaluminum (TMA, Al(CH3)3), ammonia (NH3, 99.999%), and silane (SiH4) and ammonia (NH3) for depositing passivation layers, and silicon nitride (SiN) for preparing silicon nitride. x ).

[0211] (5) Electrode materials: copper paste (solid content 85%, particle size ≤1μm), silver paste (silver content 92%).

[0212] 6.2.2 Specific preparation steps

[0213] (1) Preparation of the initial layer of the P region

[0214] The cleaned silicon substrate was placed in a low-pressure chemical vapor deposition (LPCVD) system, and the reaction chamber pressure was set to 40 Pa. High-purity argon gas (600 sccm flow rate) was first introduced to purge the chamber for 8 minutes to remove air. Then, a reaction gas was introduced at a silane flow rate of 120 sccm, and the temperature was raised to 620°C. Deposition was carried out under these conditions for 35 minutes, resulting in the growth of a tunneling oxide (SiO2) layer approximately 1-10 nm thick and a polycrystalline silicon layer of 30-50 nm thick on the front side of the silicon substrate, with a sheet resistance controlled at 90 Ω / □.

[0215] (2) Fabrication of the mask for the P-region electrode area

[0216] The deposited silicon wafer is transferred to a laser oxidation device, where a 355nm wavelength, 25kHz pulse frequency, and 12W ultraviolet laser is used to scan the P-region electrode area at a scanning speed of 450mm / s. In an oxygen atmosphere (150sccm flow rate), the silicon wafer surface is oxidized to form a SiOx mask with a thickness of approximately 90nm. The electrode area occupies 12% of the total P-region area, and the laser scanning path follows a pre-designed electrode pattern.

[0217] (3) Etching and cleaning

[0218] A silicon wafer with a SiOx mask was immersed in a 6% hydrofluoric acid solution for 35 seconds to etch away the unprotected polysilicon layer and tunneling layer. After etching, the wafer was ultrasonically cleaned in deionized water for 6 minutes and then dried with nitrogen. Next, the wafer was treated in a 12% sodium hydroxide solution for 1.5 minutes to completely remove the SiOx mask. Finally, it was repeatedly rinsed with deionized water and dried.

[0219] (4) Boron diffusion and BSG formation

[0220] The treated silicon wafer was placed in a high-temperature diffusion furnace and subjected to boron diffusion at 860°C for 22 minutes. During diffusion, oxygen (flow rate 220 sccm) and borane (flow rate 6 sccm) were introduced to allow boron to diffuse into the polycrystalline silicon layer and the substrate silicon. A high-concentration boron-doped polycrystalline silicon layer (sheet resistance ≤ 28 Ω / □) was formed in the P-region electrode area, and a low-concentration boron-doped polycrystalline silicon layer (sheet resistance ≥ 160 Ω / □) was formed in the non-electrode area. Simultaneously, a BSG with a thickness of approximately 75 nm was formed on the outermost layer of the silicon wafer for subsequent laser masking.

[0221] (5) Laser 1-open N-region and gap (GAP) region mask

[0222] Using a laser with a wavelength of 532nm, a pulse frequency of 18kHz, and a power of 9W, the laser is scanned at a scanning speed of 550mm / s according to the pre-designed N-region and GAP-region pattern to remove the BSG mask in the N-region and GAP-region.

[0223] (6) Front cleaning and etching

[0224] The silicon wafer was immersed in a 5% HF acid solution for 1.2 minutes to remove any residual BSG mask on the front side. Subsequently, the wafer was immersed in a 22% sodium hydroxide solution for alkaline etching for 45 seconds to remove the unprotected B-poly layer and tunneling layer. After etching, the wafer was rinsed four times with deionized water for 2.5 minutes each time to ensure complete removal of any residual chemicals.

[0225] (7) Preparation of N-region

[0226] The cleaned silicon wafer was placed back into the LPCVD equipment, and the reaction chamber pressure was set to 50 Pa. High-purity argon gas (flow rate 700 sccm) was first introduced to purge for 7 min. Then, reaction gases were introduced at a ratio of 130 sccm for silane and 13 sccm for phosphine. The temperature was raised to 660 °C, and deposition was carried out for 28 min. A tunneling oxide layer with a thickness of about 8 nm and a phosphorus-doped polycrystalline silicon layer (P-poly) with a thickness of 38 nm were grown on the front side of the silicon wafer, and the sheet resistance was controlled at 110 Ω / □.

[0227] (8) Phosphorus diffusion and PSG formation

[0228] The silicon wafer was transferred to a high-temperature diffusion furnace for phosphorus diffusion at 890°C for 16 minutes. During the diffusion process, oxygen (flow rate 260 sccm) and phosphine (flow rate 7 sccm) were introduced to allow phosphorus to diffuse into the phosphorus-doped polycrystalline silicon layer, forming N-region doping. At the same time, a layer of phosphorus silicate glass (PSG) with a thickness of about 130 nm was grown on the surface of the silicon wafer.

[0229] (9) Laser 2-open P-region and GAP region mask

[0230] A laser with a wavelength of 355nm, a pulse frequency of 22kHz, and a power of 11W was used to scan the P-area and GAP-area patterns at a scanning speed of 480mm / s to remove the PSG mask in the corresponding areas.

[0231] (10) Front cleaning, etching, texturing

[0232] The silicon wafer was immersed in a 5% HF acid solution for a 2-minute chain pickling process to remove the front PSG.

[0233] Subsequently, the silicon wafer was immersed in a mixed etching solution consisting of hydrofluoric acid (3% by mass), nitric acid (10% by mass), and deionized water for 30 seconds to remove the phosphorus-doped polysilicon layer and tunneling layer that were not protected by the PSG mask. After etching, the wafer was rinsed three times with deionized water for 2 minutes each time, and finally dried with nitrogen gas.

[0234] A pyramidal textured surface is formed by anisotropic etching of silicon surfaces using sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution. Formulation: KOH texturing solution. Composition: ① KOH (analytical grade): 1-2 wt% ② Isopropanol (IPA): 2-5 vol% (to promote uniformity of the texture); ③ Deionized water: balance. Process parameters: ① Temperature: 75-85℃ ② Time: 15-25 min. Procedure: ① Heat the solution to the set temperature and place the solar cells in; ② After the reaction, rinse with deionized water, then neutralize the residual alkali solution with HCl (5% concentration); ③ Ultrasonic cleaning for 10 min to remove particulate impurities.

[0235] (11) Deposition of passivation / antireflection layer on front and back sides

[0236] The silicon wafer was placed in an atomic layer deposition (ALD) system, using trimethylaluminum (TMA) as the aluminum source and water (H2O) as the oxygen source, to deposit aluminum oxide (Al2O3) at 420°C for 220 deposition cycles, resulting in an aluminum oxide passivation layer with a thickness of approximately 11 nm. Next, the silicon wafer was transferred to a plasma-enhanced chemical vapor deposition (PECVD) system, where silane (flow rate 90 sccm) and ammonia (flow rate 220 sccm) were introduced, and silicon nitride (SiN) was deposited at 360°C. x Antireflective coating, deposition time 16 min, film thickness controlled at 85 nm.

[0237] (12) Electrode formation

[0238] Copper paste was printed on the back of the battery using screen printing technology. The printed pattern was a grid structure with a grid line width of 75 μm and a spacing of 1.3 mm. After printing, it was pre-dried at 220℃ for 12 min, and then placed in a sintering furnace for rapid sintering at a peak temperature of 860℃ for 5.5 min to form ohmic contacts. To enhance electrode conductivity, a layer of silver paste with a thickness of approximately 4.5 μm was printed on the surface of the copper paste grid lines, and the device was sintered again at 860℃ for 3.5 min to complete the device fabrication.

[0239] Example 4

[0240] Ink / blocking paste as a mask

[0241] 6.3.1 Preparation of Experimental Materials

[0242] 1. Substrate silicon: N-type single crystal silicon wafers with dimensions of 156.75mm×156.75mm and a thickness of 180μm are selected. The resistivity is 1-3Ω·cm. The surface is treated with standard texturing, and the average height of the textured pyramid is about 1.5μm.

[0243] 2. Gas feedstock: high-purity silane (SiH4, 99.999%), borane (B2H6, 99.99%, diluted in high-purity argon, concentration 5%), phosphine (PH3, 99.99%, diluted in high-purity argon, concentration 5%), high-purity oxygen (O2, 99.999%), and high-purity argon (Ar, 99.999%).

[0244] 3. Chemical reagents: 49% hydrofluoric acid (HF), 20% sodium hydroxide (NaOH) solution, deionized water (resistivity ≥18.2 MΩ·cm), ink cleaner (main component: propylene glycol methyl ether acetate).

[0245] 4. Thin film materials: Trimethylaluminum (TMA, Al(CH3)3), ammonia (NH3, 99.999%) for depositing passivation layers, and silane (SiH4) and ammonia (NH3) for preparing silicon nitride (SiN). x ).

[0246] 5. Electrode materials: copper paste (85% solid content, particle size ≤1μm), silver paste (92% silver content).

[0247] 6. Mask material: High temperature resistant ink (softening point ≥350℃) or barrier paste (main components: silica microspheres, organic resin).

[0248] 6.3.2 Specific preparation steps

[0249] (1) Preparation of the initial layer of the P region

[0250] The cleaned silicon substrate was placed in a low-pressure chemical vapor deposition (LPCVD) system, and the reaction chamber pressure was set to 55 Pa. High-purity argon gas (550 sccm flow rate) was first introduced to purge the chamber for 6 minutes to remove air. Subsequently, reaction gases were introduced at a ratio of 110 sccm for silane and 12 sccm for borane, while the temperature was raised to 610 °C. Deposition was carried out under these conditions for 32 minutes, resulting in the growth of a tunneling oxide layer (SiO2) with a thickness of approximately 1-10 nm and a boron-doped polycrystalline silicon layer (B-poly) with a thickness of 30-100 nm on the front side of the silicon substrate, with a sheet resistance controlled at 85 Ω / □.

[0251] (2) Fabrication of the mask for the P-region electrode area

[0252] A layer of ink / blocking paste is printed in the P-area electrode area using screen printing technology. The screen mesh count is 325, the squeegee hardness is 75° Shore hardness, and the printing pressure is 30 N / cm. 2 The printing speed was 100 mm / s. The ink / block paste thickness was controlled at 15 μm, and the electrode area accounted for 18% of the total P-area area. After printing, the silicon wafer was placed in an oven and dried at 120°C for 15 minutes to allow the ink / block paste to initially cure.

[0253] (3) Etching and cleaning

[0254] A silicon wafer with an ink / blocking paste mask was placed in an etching solution (4% hydrofluoric acid solution by mass) for 40 seconds to remove the unmasked boron-doped polysilicon layer and tunneling layer. After etching, the wafer was ultrasonically cleaned in deionized water for 8 minutes and then dried with nitrogen. Subsequently, the wafer was immersed in an ink cleaning agent at 60°C for 10 minutes to completely remove the ink / blocking paste mask. Finally, it was rinsed again with deionized water and dried.

[0255] (4) Boron diffusion and BSG formation

[0256] The processed silicon wafer was placed in a high-temperature diffusion furnace and subjected to boron diffusion at 870°C for 25 minutes. During diffusion, oxygen (flow rate 240 sccm) and borane (flow rate 7 sccm) were introduced to allow boron to diffuse into the boron-doped polysilicon layer and the substrate silicon. A high-concentration boron-doped polysilicon layer (sheet resistance ≤ 32 Ω / □) was formed in the P-region electrode area, while a low-concentration boron-doped polysilicon layer (sheet resistance ≥ 170 Ω / □) was formed in the non-electrode area. Simultaneously, a BSG layer with a thickness of approximately 90 nm was formed on the outermost layer of the silicon wafer to prepare for subsequent laser masking.

[0257] (5) Front cleaning and etching

[0258] The silicon wafer was immersed in a 6% (w / w) HF acid solution for 1.5 minutes to remove any residual BSG mask on the front side. Subsequently, the wafer was immersed in an 18% sodium hydroxide solution for alkaline etching for 50 seconds to remove the unprotected B-poly layer and tunneling layer. After etching, the wafer was rinsed five times with deionized water for three minutes each time to thoroughly remove any residual chemical reagents.

[0259] (6) Preparation of N-region

[0260] The cleaned silicon wafer was placed back into the LPCVD equipment, and the reaction chamber pressure was set to 58 Pa. High-purity argon gas (flow rate 750 sccm) was first introduced to purge for 8 minutes. Then, reaction gases were introduced at a ratio of 140 sccm for silane and 15 sccm for phosphine. The temperature was raised to 670°C, and deposition was carried out for 30 minutes to grow a tunneling oxide layer with a thickness of about 9 nm and a phosphorus-doped polycrystalline silicon layer (P-poly) with a thickness of 42 nm on the front side of the silicon wafer. The sheet resistance was controlled at 120 Ω / □.

[0261] (7) Phosphorus diffusion and PSG formation

[0262] The silicon wafer was transferred to a high-temperature diffusion furnace and phosphorus diffusion was performed at 900°C for 18 minutes. During the diffusion process, oxygen (flow rate 280 sccm) and phosphine (flow rate 8 sccm) were introduced to allow phosphorus to diffuse into the phosphorus-doped polycrystalline silicon layer, forming N-region doping. At the same time, a phosphorus silicate glass (PSG) layer with a thickness of about 140 nm was grown on the surface of the silicon wafer.

[0263] (8) Laser-cut P-region and GAP-region mask

[0264] A laser with a wavelength of 355nm, a pulse frequency of 25kHz, and a power of 13W was used to scan the P-area and GAP-area patterns at a scanning speed of 520mm / s to remove the PSG mask in the corresponding areas.

[0265] (9) Front cleaning, etching, texturing

[0266] The silicon wafer was immersed in a 5% HF acid solution for a 2-minute chain pickling process to remove the front PSG.

[0267] Subsequently, the silicon wafer was immersed in a mixed etching solution consisting of hydrofluoric acid (3% by mass), nitric acid (10% by mass), and deionized water for 30 seconds to remove the phosphorus-doped polysilicon layer and tunneling layer that were not protected by the PSG mask. After etching, the wafer was rinsed three times with deionized water for 2 minutes each time, and finally dried with nitrogen gas.

[0268] A pyramidal textured surface is formed by anisotropic etching of silicon surfaces using sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution. Formulation: KOH texturing solution. Composition: ① KOH (analytical grade): 1-2 wt% ② Isopropanol (IPA): 2-5 vol% (to promote uniformity of the texture); ③ Deionized water: balance. Process parameters: ① Temperature: 75-85℃ ② Time: 15-25 min. Procedure: ① Heat the solution to the set temperature and place the solar cells in; ② After the reaction, rinse with deionized water, then neutralize the residual alkali solution with HCl (5% concentration); ③ Ultrasonic cleaning for 10 min to remove particulate impurities.

[0269] (10) Deposition of passivation / antireflection layer on front and back sides

[0270] The silicon wafer was placed in an atomic layer deposition (ALD) system, using trimethylaluminum (TMA) as the aluminum source and water (H2O) as the oxygen source, to deposit aluminum oxide (Al2O3) at 410°C for 230 deposition cycles, resulting in an aluminum oxide passivation layer with a thickness of approximately 12 nm. Next, the silicon wafer was transferred to a plasma-enhanced chemical vapor deposition (PECVD) system, where silane (flow rate 100 sccm) and ammonia (flow rate 240 sccm) were introduced, and a silicon nitride (SiNx) antireflective film was deposited at 370°C for 18 minutes, with the film thickness controlled at 90 nm.

[0271] (11) Electrode formation

[0272] Copper paste was printed on the back of the battery using screen printing technology. The printed pattern was a grid line structure with a grid line width of 85 μm and a spacing of 1.6 mm. After printing, it was pre-dried at 230℃ for 15 min, and then placed in a sintering furnace for rapid sintering at a peak temperature of 870℃ for 6 min to form ohmic contacts. To further improve the conductivity of the electrodes, a layer of silver paste with a thickness of approximately 5.5 μm was printed on the surface of the copper paste grid lines. The device was then sintered again at 870℃ for 4 min to complete the device fabrication.

Claims

1. A TBC solar cell, characterized by, The N-type substrate silicon comprises a P-type region on the back surface; a first tunneling layer, a P-type polysilicon layer, a first passivation anti-reflection layer and a first electrode layer are sequentially arranged from the back surface of the N-type substrate silicon to the outside, the P-type polysilicon layer comprises a high-doped region and a low-doped region, the low-doped region is arranged outside the high-doped region and in contact with the high-doped region, and the first electrode layer penetrates through the first passivation anti-reflection layer and is in contact with the high-doped region.

2. A TBC solar cell according to claim 1, characterized in that The back surface of the N-type substrate silicon further comprises an N-type region, which is arranged alternately with the P-type region, a second tunneling layer, an N-type polysilicon layer, a second passivation anti-reflection layer and a second electrode layer are sequentially arranged from the back surface of the N-type substrate silicon to the outside in the N-type region, and the second electrode layer penetrates through the second passivation anti-reflection layer and is in contact with the N-type polysilicon layer.

3. A TBC solar cell according to claim 1 or 2, characterized in that The low-doped region is arranged outside the first tunneling layer, and the low-doped region is in contact with the high-doped region and the N-type substrate silicon.

4. The TBC solar cell according to claim 1 or 2, characterized in that, The boron doping concentration in the high-doped region is higher than that in the low-doped region.

5. A TBC solar cell according to claim 4, characterized in that In the high doped region, the boron doping concentration is 1 x 1019 19 atoms / cm 21 In the low doped region, the boron doping concentration is 5 x 1018 3 atoms / cm 15 In the low doped region, the boron doping concentration is 5 x 1018 17 atoms / cm 3 .

6. The TBC solar cell of claim 1, wherein, The area of the high-doped region is 5%-10% of the area of the P-type region, and the area of the low-doped region is 90%-95% of the area of the P-type region.

7. The TBC solar cell of claim 1, wherein, The first tunneling layer and the high-doped region are located at the center of the low-doped region; and / or The surface of the low-doped region away from the N-type substrate silicon is flush with the surface of the high-doped region away from the N-type substrate silicon.

8. The TBC solar cell of claim 1, wherein, The thickness of the first tunneling layer is 0.1-2 nm, the thickness of the high-doped region is 50-500 nm, and the thickness of the low-doped region is 50-1000 nm.

9. A method for producing a TBC solar cell, for producing a TBC solar cell according to any one of claims 1 to 8, characterized in that The method comprises: growing a substrate silicon, growing a tunneling layer on the back surface of the substrate silicon; growing a high-doped P-type polysilicon layer on the surface of the tunneling layer; removing part of the tunneling layer and the high-doped P-type polysilicon layer, growing a low-doped P-type polysilicon layer on the back surface of the substrate silicon, embedding the high-doped P-type polysilicon layer and the tunneling layer in the low-doped P-type polysilicon layer; removing part of the low-doped P-type polysilicon layer, growing a passivation anti-reflection layer on the surface of the low-doped P-type polysilicon layer and the surface of the high-doped P-type polysilicon layer; and forming an electrode layer on the surface of the passivation anti-reflection layer.

10. A method for preparing a TBC solar cell according to claim 9, characterized in that, After removing part of the low-doped P-type polysilicon layer, the preparation method further comprises: growing a tunneling layer on the surface of the substrate silicon again; growing an N-type polysilicon layer on the surface of the tunneling layer; removing part of the tunneling layer and the N-type polysilicon layer to form a P-type region and an N-type region alternately arranged in intervals; growing a passivation anti-reflection layer on the surface of the N-type polysilicon layer; and forming an electrode layer on the surface of the passivation anti-reflection layer.

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